MCP2022PT-330E/SL

MCP2021/2/1P/2P LIN Transceiver with Voltage Regulator Features: Description: • The MCP2021/2/1P/2P are Compliant with LIN Bus Specifications 1.3, 2.1 and are Compliant to SAE J2602-2 • Support Baud Rates up to 20 kBaudwith LIN-compatible Output Driver • 43V Load Dump Protected • Very Low EMI Meets Stringent OEM Requirements • Wide Supply Voltage, 6.0V-18.0V Continuous: - Maximum input voltage of 30V • Extended Temperature Range: -40 to +125°C • Interface to PIC® EUSART and Standard USARTs • Local Interconnect Network (LIN) Bus Pin: - Internal pull-up resistor and diode - Protected against ground shorts - Protected against loss of ground - High-current drive • Automatic Thermal Shutdown • On-Chip Voltage Regulator: - Output voltage of 5.0V with tolerances of ±3% overtemperature range - Available with alternate output voltage of 3.3V with tolerances of ±3% overtemperature range - Maximum continuous input voltage of 30V - Internal thermal overload protection - Internal short circuit current limit - External components limited to filter capacitor and load capacitor • Two Low-Power modes: - Receiver On, Transmitter Off, Voltage Regulator On ( 85 µA) - Receiver Monitoring Bus, Transmitter Off, Voltage Regulator Off ( 16 µA) The MCP2021/2/1P/2P provides a bidirectional, halfduplex communication physical interface to automotive and industrial LIN systems that meets the LIN bus specification Revision 2.1 and SAE J2602-2. The devices incorporate a voltage regulator with 5V at 50 mA or 3.3V at 50 mA regulated power-supply outputs.  2005-2014 Microchip Technology Inc. The regulator is short-circuit protected, and is protected by an internal thermal shutdown circuit. The device has been specifically designed to operate in the automotive operating environment and will survive all specified transient conditions while meeting all of the stringent quiescent current requirements. The MCP2021/2/1P/2P family of devices includes the following packages. 8-pin PDIP, DFN and SOIC packages: • MCP2021-330, LIN-compatible driver, 8-pin, 3.3V regulator, wake up on dominant level of LBUS • MCP2021-500, LIN-compatible driver, 8-pin, 5.0V regulator, wake up on dominant level of LBUS • MCP2021P-330, LIN-compatible driver, 8-pin, 3.3V regulator, wake up at falling edge of LBUS voltage • MCP2021P-500, LIN-compatible driver, 8-pin, 5.0V regulator, wake up at falling edge of LBUS voltage 14-pin PDIP, TSSOP and SOIC packages with RESET output: • MCP2022-330, LIN-compatible driver, 14-pin, 3.3V regulator, RESET output, wake up on dominant level of LBUS • MCP2022-500, LIN-compatible driver, 14-pin, 5.0V regulator, RESET output, wake up on dominant level of LBUS • MCP2022P-330, LIN-compatible driver, 14-pin, 3.3V regulator, RESET output, wake up at falling edge of LBUS voltage • MCP2022P-500, LIN-compatible driver, 14-pin, 5.0V regulator, RESET output, wake up at falling edge of LBUS voltage DS20002018H-page 1 MCP2021/2/1P/2P Package Types MCP2021, 6x5 DFN-S* MCP2021, MCP2021P 4x4 DFN* RXD 1 CS/LWAKE 2 VREG 3 TXD 4 EP 9 8 FAULT/TXE 7 VBB 6 LBUS 5 VSS RXD 1 CS/LWAKE 2 VREG TXD RXD 1 8 2 7 3 6 4 5 EP 9 3 4 7 VBB 6 LBUS 5 VSS MCP2022, MCP2022P PDIP, SOIC, TSSOP MCP2021, MCP2021P PDIP, SOIC CS/LWAKE VREG TXD FAULT/TXE 8 FAULT/TXE VBB LBUS VSS RXD CS/LWAKE 1 14 2 13 VREG TXD 3 12 4 5 11 10 6 9 7 8 RESET NC NC * Includes Exposed Thermal Pad (EP); see Table 1-2. FAULT/TXE VBB LBUS VSS NC NC NC MCP2021/2 Block Diagram Short Circuit Protection Thermal Protection RESET (MCP2022 ONLY) Voltage Regulator VREG Internal Circuits VBB Ratiometric Reference Wake-Up Logic and Power Control – RXD + ~30 kΩ CS/LWAKE TXD LBUS OC FAULT/TXE VSS Thermal Protection DS20002018H-page 2 Short Circuit Protection  2005-2014 Microchip Technology Inc. MCP2021/2/1P/2P MCP2021P/2P Block Diagram Short-Circuit Protection RESET (MCP2022P ONLY) Thermal Protection Voltage Regulator VREG Internal Circuits Ratiometric Reference Wake-Up Logic and Power Control – RXD + CS/LWAKE TXD VBB ~30 kΩ OC LBUS FAULT/TXE VSS Thermal and Short-Circuit Protection  2005-2014 Microchip Technology Inc. Short-Circuit Protection DS20002018H-page 3 MCP2021/2/1P/2P NOTES: DS20002018H-page 4  2005-2014 Microchip Technology Inc. MCP2021/2/1P/2P 1.0 DEVICE OVERVIEW EQUATION 1-1: RTP  (VBBmin - 5.5) / 250 mA. 5.5V = VUVLO + 1.0V, 250 mA is the peak current at Power-On when VBB = 5.5V The MCP2021/2/1P/2P provides a physical interface between a microcontroller and a LIN half-duplex bus. It is intended for automotive and industrial applications with serial bus speeds up to 20 Kbaud. The MCP2021/2/1P/2P provides a half-duplex, bidirectional communications interface between a microcontroller and the serial network bus. This device will translate the CMOS/TTL logic levels to LIN-level logic, and vice versa. The LIN specification 2.0 requires that the transceiver(s) of all nodes in the system be connected via the LIN pin, referenced to ground, and with a maximum external termination resistance load of 510Ω from LIN bus to battery supply. The 510Ωcorresponds to one Master and sixteen Slave nodes. The MCP2021/2/1P/2P-500 provides a +5V, 50 mA, regulated power output. The regulator uses an LDO design, is short-circuit protected, and will turn the regulator output off if it falls below 3.5V. The MCP2021/2/1P/2P thermal-shutdown protection. also includes The regulator is specifically designed to operate in the automotive environment and will survive +43V load dump transients, double-battery jumps, and reverse battery connections when a reverse blocking diode is used. The other members of the MCP2021/2/1P/2P-330 family output +3.3V at 50 mA with a turn-off voltage of 2.5V. (See Section 1.6 “Internal Voltage Regulator”). MCP2021/2 wakes from Power-Down mode on a dominant level on LBUS. MCP2021P/2P wakes at a transition from recessive level to dominant level on LBUS. 1.1 1.1.1 1.2 1.2.1 Internal Protection ESD PROTECTION For component-level ESD ratings, please refer to the Section 2.1 “Absolute Maximum Ratings†”. 1.2.2 GROUND LOSS PROTECTION The LIN Bus specification states that the LIN pin must transition to the recessive state when ground is disconnected. Therefore, a loss of ground effectively forces the LIN line to a high-impedance level. 1.2.3 THERMAL PROTECTION The thermal protection circuit monitors the die temperature and is able to shut down the LIN transmitter and voltage regulator if it detects a thermal overload. There are three causes for a thermal overload. A thermal shut down can be triggered by any one, or a combination of, the following thermal overload conditions: • Voltage regulator overload • LIN bus output overload • Increase in die temperature due to increase in environmental temperature Driving the TXD and checking the RXD pin makes it possible to determine whether there is a bus contention (i.e., RXD = low, TXD = high) or a thermal overload condition (i.e., RXD = high, TXD = low). Optional External Protection REVERSE BATTERY PROTECTION An external reverse-battery-blocking diode should be used to provide polarity protection (see Figure 1-6). 1.1.2 TRANSIENT VOLTAGE PROTECTION (LOAD DUMP) An external 43V transient suppressor (TVS) diode, between VBB and ground, with a 50Ω transient protection resistor (RTP) in series with the battery supply and the VBB pin, protect the device from power transients (see Figure 1-6) and ESD events. While this protection is optional, it is considered good engineering practice. The resistor value is chosen according to Equation 1-1.  2005-2014 Microchip Technology Inc. DS20002018H-page 5 MCP2021/2/1P/2P FIGURE 1-1: THERMAL SHUTDOWN STATE DIAGRAMS LBUS Overload to VBB Output Overload Voltage Regulator Shutdown Operation Mode Temperature = 2V CS/LWAKE VREG FAULT/TXE = 1 Forced internally FAULT/TXE = 0 Forced externally FAULT/TXE LBUS disconnected; e.g., Master pull-up & internal resistor off; LBUS floating. LBUS STATE Operation Mode Transmitter-Off Mode Power-Down Mode Forced Power-Down Mode after BUS-OFF instruction or a longer LIN-Bus inactivity ( > = 4 sec according to LIN specification) DS20002018H-page 10  2005-2014 Microchip Technology Inc. MCP2021/2/1P/2P TABLE 1-1: OVERVIEW OF OPERATIONAL MODES Transmitter Receiver Voltage Regulator POR OFF OFF OFF Read VBB; if VBB > 5.75V, proceed to Ready mode Ready OFF ON ON Bus OFF MCP2021/2: If CS/LWAKE is high level, then proceed to state Operation mode. MCP2021P/2P: If CS/LWAKE is high level and FAULT/TXE is high level, then proceed to Operation mode. If CS/LWAKE is high level and FAULT/TXE is low level, then proceed to TXOFF mode. Operation ON ON ON If CS/LWAKE is low level, then proceed to Power-Down mode. If FAULT/TXE is low level or TXD/LBUS permanent dominant is detected, then proceed to Transmitter-Off mode. Normal Operation mode Power-Down OFF Activity Detect OFF On LIN bus falling, go to Ready mode. On CS/LWAKE high level, go through Ready mode; then, to either operation or Transmitter-Off mode (refer to Figure 1-2 and Figure 1-3). Low-Power mode Transmitter-Off OFF ON ON If CS/LWAKE is low level, then proceed to Power-Down mode. If FAULT/TXE is high, then proceed to Operation mode. State  2005-2014 Microchip Technology Inc. Operation Comments DS20002018H-page 11 MCP2021/2/1P/2P 1.4 Pin Descriptions TABLE 1-2: PINOUT DESCRIPTIONS Devices Pin Name Function 8-Pin PDIP, SOIC 4x4 DFN 6x5 DFN-S 14-Pin PDIP, SOIC, TSSOP Pin Type Normal Operation RXD 1 1 1 O CS/LWAKE 2 2 2 TTL Receive Data Output (CMOS) VREG 3 3 3 O Power Output TXD 4 4 4 I Transmit Data Input (TTL) VSS 5 5 11 P LBUS 6 6 12 I/O NC — — 6 – 10 — No Connection VBB 7 7 13 P Battery Supply Chip Select (TTL) Ground LIN bus (Bidirectional) FAULT/TXE 8 8 14 OD Fault Detect Output, Transmitter Enable (OD) RESET — — 5 OD RESET Signal Output (OD) EP — 9 — — Exposed Thermal Pad Legend: O = Output, P = Power, I = Input, TTL = TTL input buffer, OD = Open-Drain Output 1.4.1 RECEIVE DATA OUTPUT (RXD) 1.4.3 POWER OUTPUT (VREG) The Receive Data Output pin is a standard CMOS output and follows the state of the LIN pin. Positive Supply Voltage Regulator Output pin. 1.4.2 The Transmit Data Input pin has an internal pull-up to VREG. The LIN pin is low (dominant) when TXD is low, and high (recessive) when TXD is high. CHIP SELECT PIN (CS/LWAKE) An internal pull-down resistor will keep the CS/LWAKE pin low. This is done to ensure that no disruptive data will be present on the bus while the microcontroller is executing a POR and I/O initialization sequence. The pin must see a high level to activate the transmitter. If CS/LWAKE = 0 when the VBB supply is turned on, the device stays in Ready mode (Low-Power mode). In Ready mode, both the receiver and the voltage regulator are on and the LIN transmitter driver is off. If CS/LWAKE = 1 when the VBB supply is turned on, the device will proceed to either Operation or Transmitter-Off mode (refer to Figure 1-2 and Figure 1-3) after the VREG output has stabilized. This pin may also be used as a local wake-up input (see Figure 1-6). In this implementation, the microcontroller will set the I/O pin that controls the CS/LWAKE as an high-impedance input. The internal pull-down resistor will keep the input low. An external switch, or other source, can then wake up the transceiver and the microcontroller. Note: CS/LWAKE should not be tied directly to VREG as this could force the MCP202X into Operation mode before the microcontroller is initialized. 1.4.4 TRANSMIT DATA INPUT (TXD) For extra bus security, TXD is internally forced to ‘1’ when VREG is less than 1.8V (typical). If the thermal protection detects an overtemperature condition while the signal TXD is low, the transmitter is shut down. The recovery from the thermal shutdown is equal to adequate cooling time. 1.4.5 GROUND PIN (VSS) Ground pin. 1.4.6 LIN BUS PIN (LBUS) The bidirectional LIN bus Interface pin is the driver unit for the LIN pin and is controlled by the signal TXD. LIN has an open collector output with a current limitation. To reduce EMI, the edges during the signal changes are slope-controlled. To further reduce radiated emissions, the LBUS pin has corner-rounding control for both falling and rising edges. The internal LIN receiver observes the activities on the LIN bus, and generates output signal RXD that follows the state of the LBUS. A 1st degree with 1 µs time constant (160 kHz), low-pass input filter is placed to maintain EMI immunity. 1.4.7 NO CONNECTION (NC) No internal connection. DS20002018H-page 12  2005-2014 Microchip Technology Inc. MCP2021/2/1P/2P 1.4.8 BATTERY POSITIVE SUPPLY VOLTAGE (VBB) Battery Positive Supply Voltage pin. This pin is also the input for the internal voltage regulator. 1.4.9 This pin has an internal pull-up resistor of approximately 750 kΩ. The internal pull-up resistor may be too weak for some applications. We recommend adding a 10 kOhm external pull-up resistor to ensure a logic high level. FAULT/TXE Note 1: The FAULT/TXE pin is true (0) whenever the internal circuits have detected a short or thermal excursion and have disabled the LBUS output driver. Fault Detect Output and Transmitter Enable Input bidirectional pin. This pin is an open-drain output. Its state is defined as shown in Table 1-3. The transmitter driver is disabled whenever this pin is low (‘0’), either from an internal Fault condition or by external drive. This allows the transmitter to be placed in an OFF state and still allow the voltage regulator to operate. Refer to Table 1-1. 2: FAULT/TXE is true (0) when VREG not OK and has disabled the LBUS output driver. The FAULT/TXE pin sampled at a rate faster than every 10 µs. The FAULT/TXE also signals a mismatch between the TXD input and the LBUS level. This can be used to detect a bus contention. Since the bus exhibits a propagation delay, the sampling of the internal compare is debounced to eliminate false faults. TABLE 1-3: FAULT/TXE TRUTH TABLE FAULT/TXE TXD In RXD Out LINBUS I/O Thermal Override L H VBB H H External Input Driven Output Definition OFF H L FAULT, TXD driven low, LBUS shorted to VBB (Note 1) VBB OFF H H OK L L GND OFF H H OK H L GND OFF H H OK, data is being received from the LBUS x x VBB ON H L FAULT, transceiver in thermal shutdown x x VBB x L x NO FAULT, the CPU is commanding the transceiver to turn off the transmitter driver Legend: x = don’t care Note 1: The FAULT/TXE is valid after approximately 25 µs after TXD falling edge. This is to eliminate false fault reporting during bus propagation delays. 1.4.10 RESET RESET is an open-drain output pin. This pin reflects an internal signal that tracks the internal system voltage has reached a valid, stable level. 1.4.11 EXPOSED THERMAL PAD (EP) It is recommended to connect this pad to VSS to enhance electromagnetic immunity and thermal resistance. As long as the internal voltage is valid, this pin will keep high-impedance. When the system voltage drops below the minimum required, the voltage regulator will shut down and immediately convert the RESET output to short to GND. A pull-up resistor is needed to change the output to high/low voltage. When connected to a microcontroller input, this can provide a warning that the voltage regulator is shutting down (see Figure 1-2). Alternately, it can act as an external brown-out by connecting the RESET output to MCLR (see Figure 1-2). In addition to monitoring the internal voltage, RESET is asserted immediately upon entering the Power-Down mode.  2005-2014 Microchip Technology Inc. DS20002018H-page 13 MCP2021/2/1P/2P 1.5 Typical Applications FIGURE 1-6: TYPICAL MCP2021/MCP2021P APPLICATION +12 +12 RTP(5) WAKE-UP 43V(5) Master Node Only CBAT +12 CREG 220 kΩ VDD VREG TXD TXD VBB 1 kΩ (6) RXD RXD I/O LBUS LIN Bus CS/LWAKE (3) MMBZ27V (4) FAULT/TXE I/O 220 pF VSS 100 nF VSS Note 1: Note CREG, the load capacitor, should be ceramic or tantalum rated for extended temperatures, 1.0 – 22 µF. See Figure 2-1 to select the correct ESR. 2: CBAT is the filter capacitor for the external voltage supply. 3: This diode is only needed if CS/LWAKE is connected to the VBAT supply. 4: Transient suppressor diode. 5: These components are required for additional load dump protection above 43V. 6: An external 10 kΩ resistor is recommended for some applications. DS20002018H-page 14  2005-2014 Microchip Technology Inc. MCP2021/2/1P/2P FIGURE 1-7: TYPICAL MCP2022/MCP2022P APPLICATION +12 +12 RTP(5) WAKE-UP 43V(5) +12 VDD VREG TXD TXD RXD RXD VBB 1 kΩ LBUS LIN Bus CS/LWAKE (3) MMBZ27V (4) FAULT/TXE I/O INT or MCLR VSS Master Node Only CREG 220 kΩ I/O CBAT 220 pF RESET VSS 100 nF VDD (6) Note 1: Note CREG, the load capacitor, should be ceramic or tantalum rated for extended temperatures, 1.0 – 22 µF. See Figure 2-1 to select the correct ESR. 2: CF is the filter capacitor for the external voltage supply. 3: This diode is only needed if is connected to the VBAT supply. 4: Transient suppressor diode. 5: These components are required for additional load dump protection above 43V. 6: Required if CPU does not have internal pull-up. FIGURE 1-8: TYPICAL LIN NETWORK CONFIGURATION 40m + Return LIN bus 1 kΩ VBB LIN bus MCP202X LIN bus MCP202X Slave 1 (MCU) LIN bus MCP202X LIN bus MCP202X Slave 2 (MCU) Slave n 3.5V), the VREG will be switched back on. The regulator has a thermal shutdown. If the thermal protection circuit detects an overtemperature condition, and the signals TXD and RXD are Low, or TXD is High, the regulator will shut down. The recovery from the thermal shutdown is equal to adequate cooling time. The regulator requires an external output bypass capacitor for stability. See Figure 2-1 for correct capacity and ESR for stable operation. Note: A ceramic capacitor of at least 10 µF or a tantalum capacitor of at least 2.2 µF is recommended for stability. In worst-case scenarios, the ceramic capacitor may derate by 50%, based on tolerance, voltage and temperature. Therefore, in order to ensure stability, ceramic capacitors smaller than 10 µF may require a small series resistance to meet the ESR requirements, as shown in Table 1-4. TABLE 1-4: RECOMMENDED SERIES RESISTANCE FOR CERAMIC CAPACITORS Resistance Capacitor Ω 1 µF 0.47Ω 2.2 µF 0.22Ω 4.7 µF 0.1Ω 6.9 µF  2005-2014 Microchip Technology Inc. MCP2021/2/1P/2P FIGURE 1-9: VOLTAGE REGULATOR BLOCK DIAGRAM Pass Element VREG VBB Sampling Network Fast Transient Loop Buffer VSS VREF  2005-2014 Microchip Technology Inc. DS20002018H-page 17 MCP2021/2/1P/2P 1.6.2 3.3V REGULATOR A metal option provides for a alternate 3.30 VDC ±3% at up to 50 mA of load current over the entire operating temperature range of -40°C to +125°C. All specifications given above for the 5.0V operation apply except for any difference noted here. The same input tracking of 4.25V applies the 3.3V regulator. Note: The regulator has an overload current limiting of approximately 100 mA. If VREG is lower than 2.5V, the VREG will turn off. FIGURE 1-10: VOLTAGE REGULATOR OUTPUT ON POR 8 VBB V Minimum VBB to maintain regulation VON 6 VOFF 4 2 0 t VREG 5 V VREG-NOM 4 3 2 1 0 t (1) Note 1: 2: 3: 4: DS20002018H-page 18 (2) (3) (4) Start-up, VBB < VON, regulator off. VBB > VON, regulator on. VBB  Minimum VBB to maintain regulation. VBB < VOFF, regulator will turn off.  2005-2014 Microchip Technology Inc. MCP2021/2/1P/2P FIGURE 1-11: VOLTAGE REGULATOR OUTPUT ON OVERCURRENT SITUATION IREG mA lLIM 0 t VREG 6 V 5 VREG-NOM 4 VSD 3 2 1 0 Note 1: 2: 1.7 t (1) (2) IREG less than lLIM, regulator on. After IREG exceeds lLIM, the voltage regulator output will be reduced until VSD is reached. ICSP™ Considerations The following should be considered when the MCP2021/2/1P/2P is connected to pins supporting in-circuit programming: • Power used for programming the microcontroller can be supplied from the programmer or from the MCP2021/2/1P/2P. • The voltage on VREG should not exceed the maximum output voltage of VREG.  2005-2014 Microchip Technology Inc. DS20002018H-page 19 MCP2021/2/1P/2P NOTES: DS20002018H-page 20  2005-2014 Microchip Technology Inc. MCP2021/2/1P/2P 2.0 ELECTRICAL CHARACTERISTICS 2.1 Absolute Maximum Ratings† VIN DC Voltage on RXD and TXD .......................................................................................................... -0.3 to VREG+0.3V VIN DC Voltage on FAULT and RESET.........................................................................................................-0.3 to +5.5V VIN DC Voltage on CS/LWAKE.......................................................................................................................-0.3 to +43V VBB Battery Voltage, non-operating (LIN bus recessive, no regulator load, t < 60s) .....................................-0.3 to +43V VBB Battery Voltage, transient ISO 7637 Test 1 ......................................................................................................-200V VBB Battery Voltage, transient ISO 7637 Test 2a ...................................................................................................+150V VBB Battery Voltage, transient ISO 7637 Test 3a ....................................................................................................-300V VBB Battery Voltage, transient ISO 7637 Test 3b ...................................................................................................+200V VBB Battery Voltage, continuous ....................................................................................................................-0.3 to +30V VLBUS Bus Voltage, continuous.......................................................................................................................-18 to +30V VLBUS Bus Voltage, transient (Note 1)............................................................................................................-27 to +43V ILBUS Bus Short Circuit Current Limit ....................................................................................................................200 mA ESD protection on LIN, VBB (IEC 61000-4-2, 330 Ohm, 150 pF) (Note 3) .............................................. minimum ±9 kV ESD protection on LIN, VBB (Charge Device Model) (Note 2)..............................................................................±1500V ESD protection on LIN, VBB (Human Body Model, 1 kOhm, 100 pF) (Note 4) ....................................................... ±8 kV ESD protection on LIN, VBB (Machine Model) (Note 2) ..........................................................................................±800V ESD protection on all other pins (Human Body Model) (Note 2) ............................................................................ > 4 kV Maximum Junction Temperature ............................................................................................................................. 150C Storage Temperature .................................................................................................................................. -55 to +150C Note 1: ISO 7637/1 load dump compliant (t < 500 ms). 2: According to JESD22-A114-B. 3: According to IBEE, without bus filter. 4: Limited by Test Equipment. † NOTICE: Stresses above those listed under “Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.  2005-2014 Microchip Technology Inc. DS20002018H-page 21 MCP2021/2/1P/2P 2.2 DC Specifications DC Specifications Electrical Characteristics: Unless otherwise indicated, all limits are specified for: VBB = 6.0V to 18.0V TA = -40°C to +125°C CREG = 10 µF Parameter Sym. VBB Quiescent Operating Current IBBQ VBB Transmitter-Off Current IBBTO Min. Typ. Max. Units Conditions 115 210 µA IOUT = 0 mA, LBUS recessive Power — 120 215 µA VOUT = 3.3V — 90 190 µA With VREG on, transmitter off, receiver on, FAULT/TXE = VIL, CS = VIH — 95 210 µA VOUT = 3.3V IBBPD — 16 26 µA With VREG powered-off, receiver on and transmitter off, FAULT/TXE = VIH, TXD = VIH, CS = VIL) IBBNOGND -1 — 1 mA VBB = 12V, GND to VBB, VLIN = 0-18V High-Level Input Voltage (TXD, FAULT/TXE) VIH 2.0 or (0.25 VREG + 0.8) — VREG +0.3 V Low-Level Input Voltage (TXD, FAULT/TXE) VIL -0.3 — 0.15 VREG V High-Level Input Current (TXD, FAULT/TXE) IIH -2.5 — — µA Input voltage = 0.8*VREG Low-Level Input Current (TXD, FAULT/TXE) IIL -10 — — µA Input voltage = 0.2*VREG Pull-up Current on Input (TXD) IPUTXD -3.0 — — µA ~800 kΩ internal pull-up to VREG @ VIH = 0.7*VREG High-Level Input Voltage (CS/LWAKE) VIH 0.7 VREG — VBB V Through a current-limiting resistor Low-Level Input Voltage (CS/LWAKE) VIL -0.3 — 0.3VREG V High-Level Input Current (CS/LWAKE) IIH — — 7.0 µA Input voltage = 0.8*VREG Low-Level Input Current (CS/LWAKE) IIL — — 3.0 µA Input voltage = 0.2*VREG IPDCS — — 6.0 µA ~1.3 MΩ internal pull-down to VSS @ VIH = 3.5V VBB Power-Down Current VBB Current with VSS Floating Microcontroller Interface Pull-down Current on Input (CS/LWAKE) Note 1: 2: 3: Internal current limited. 2.0 ms maximum recovery time (RLBUS = 0Ω, TX = 0.4 VREG, VLBUS = VBB). Characterized, not 100% tested. Node has to sustain the current that can flow under this condition; bus must be operational under this condition. DS20002018H-page 22  2005-2014 Microchip Technology Inc. MCP2021/2/1P/2P 2.2 DC Specifications (Continued) DC Specifications Parameter Electrical Characteristics: Unless otherwise indicated, all limits are specified for: VBB = 6.0V to 18.0V TA = -40°C to +125°C CREG = 10 µF Sym. Min. Typ. Max. Units Conditions High-Level Input Voltage VIH(LBUS) 0.6 VBB — 18 V Recessive state Low-Level Input Voltage VIL(LBUS) -8 — 0.4 VBB V Dominant state — Bus Interface VHYS — Input Hysteresis 0.175 VBB V Low-Level Output Current IOL(LBUS) 40 — 200 mA Output voltage = 0.1 VBB, VBB = 12V Pull-up Current on Input IPU(LBUS) 5 — 180 µA ~30 kΩ internal pull-up @ VIH (LBUS) = 0.7 VBB ISC 50 — 200 mA (Note 1) High-Level Output Voltage VOH(LBUS) 0.8 VBB — VBB V Low-Level Output Voltage VOLLO (LBUS) — — 0.2 VBB V Input Leakage Current (at the receiver during dominant bus level) IBUS_PAS_DOM -1 — — mA Driver off, VBUS = 0V, VBAT = 12V Leakage Current (disconnected from ground) IBUS_NO_GND -1 — +1 mA GNDDEVICE = VBAT, 0V < VBUS < 18V, VBAT = 12V Leakage Current (disconnected from VBAT) IBUS — — 10 µA VBAT = GND, 0 < VBUS < 18V, TA = -40°C to +85°C (Note 3) 50 µA TA = +85°C to +125°C Receiver Center Voltage VBUS_CNT 0.475 VBB 0.5 VBB 0.525 VBB V VBUS_CNT = (VIL (LBUS) + VIH (LBUS))/2 Rslave 20 30 47 k Short Circuit Current Limit Slave Termination VIH (LBUS) - VIL(LBUS) VOH (LBUS) must be at least 0.8 VBB Voltage Regulator – 5.0V Output Voltage Load Regulation Quiescent Current Power Supply Ripple Reject Note 1: 2: 3: VOUT 4.85 5.00 5.15 V 0 mA < IOUT < 50 mA, VOUT2 — 10 50 mV 5 mA < IOUT < 50 mA refer to Section 1.6 “Internal Voltage Regulator” IVRQ — — 25 µA IOUT = 0 mA, (Note 2) PSRR — — 50 dB 1 VPP @10-20 kHz CLOAD = 10 µf, ILOAD = 50 mA Internal current limited. 2.0 ms maximum recovery time (RLBUS = 0Ω, TX = 0.4 VREG, VLBUS = VBB). Characterized, not 100% tested. Node has to sustain the current that can flow under this condition; bus must be operational under this condition.  2005-2014 Microchip Technology Inc. DS20002018H-page 23 MCP2021/2/1P/2P 2.2 DC Specifications (Continued) DC Specifications Parameter Electrical Characteristics: Unless otherwise indicated, all limits are specified for: VBB = 6.0V to 18.0V TA = -40°C to +125°C CREG = 10 µF Sym. Min. Typ. Max. Units Conditions Output Noise Voltage eN — — 100 µVRMS 10 Hz – 40 MHz CFILTER = 10 µf, CBP = 0.1 µf, CLOAD 10 µf, ILOAD = 50 mA Shutdown Voltage VSD 3.5 — 4.0 V Input Voltage to Maintain Regulation VBB 6.0 — 18.0 V Input Voltage to Turn Off Output VOFF 4.0 — 4.5 V Input Voltage to Turn On Output VON 5.5 — 6.0 V Output Voltage VOUT 3.20 3.30 3.40 V Line Regulation VOUT1 — 10 50 mV IOUT = 1 mA, 6.0V < VBB < 18V Load Regulation VOUT2 — 10 50 mV 5 mA < IOUT < 50 mA Refer to Section 1.6 “Internal Voltage Regulator” IVRQ — — 25 µA IOUT = 0 mA, (Note 2) Power Supply Ripple Reject PSRR — — 50 dB 1 VPP @10-20 kHz CLOAD = 10 µf, ILOAD = 50 mA Output Noise Voltage eN — — 100 Shutdown Voltage VSD 2.5 — 2.7 V Input Voltage to Maintain Regulation VBB 6.0 — 18.0 V Input Voltage to Turn Off Output VOFF 4.0 — 4.5 V Input Voltage to Turn On Output VON 5.5 — 6.0 V See Figure 1-11 (Note 2) Voltage Regulator – 3.3V Quiescent Current Note 1: 2: 3: 0 mA < IOUT < 50 mA µVRMS 10 Hz – 40 MHz /Hz CFILTER = 10 µf, CBP = 0.1 µf CLOAD = 10 µf, ILOAD = 50 mA See Figure 1-11 (Note 2) Internal current limited. 2.0 ms maximum recovery time (RLBUS = 0Ω, TX = 0.4 VREG, VLBUS = VBB). Characterized, not 100% tested. Node has to sustain the current that can flow under this condition; bus must be operational under this condition. DS20002018H-page 24  2005-2014 Microchip Technology Inc. MCP2021/2/1P/2P FIGURE 2-1: ESR CURVES FOR LOAD CAPACITOR SELECTION ESR Curves 10 Instable Unstable Stable only ESR [ohm] 1 with Tantalum or Electrolytic cap. Stable with Tantalum, Electrolytic and Ceramic cap. Instable Unstable 0.1 0.01 Unstable Instable 0.001 0.1 1 10 100 1000 Load Capacitance [µF] Load Capacitor [uF] Note: The graph shows the minimum required capacitance after derating due to tolerance, temperature and voltage.  2005-2014 Microchip Technology Inc. DS20002018H-page 25 MCP2021/2/1P/2P 2.3 AC Specification AC CHARACTERISTICS Parameter VBB = 6.0V to 18.0V; TA = -40°C to +125°C Sym. Min. Typ. Max. Units Test Conditions Bus Interface – Constant Slope Time Parameters Slope rising and falling edges tSLOPE 3.5 — 22.5 µs 7.3V