MCP2050-500E/SL

MCP2050 LIN Transceiver with Voltage Regulator Features: • The MCP2050 is compliant with: - LIN Bus Specifications Version 1.3, 2.1 and with SAE J2602-2 • Support Baud Rates Up to 20 kBaud • 43V Load Dump Protected • Maximum Continuous Input Voltage of 30V • Wide LIN Compliant Supply Voltage, 6.0-18.0V • Extended Temperature Range: -40 to +125°C • Interface to PIC® EUSART and Standard USARTs • Wake-Up on LIN Bus Activity or Local Wake Input • LIN Bus Pin - Internal pull-up termination resistor and diode for slave node - Protected against VBAT shorts - Protected against loss of ground - High current drive • TXD and LIN Bus Dominant Time-Out Function • Two Low-Power Modes - Transmitter Off mode: 90 µA (typical) - Power Down mode: 4.5 µA (typical) • Output Indicating Internal Reset State (POR or Sleep Wake) • MCP2050 On-Chip Voltage Regulator - Output voltage of 5.0V or 3.3V with 70 mA capability and tolerances of ±3% over operating temperature range - Internal short-circuit current limit - Only external filter and load capacitors needed • Programmable Windowed Watchdog Timer (WWDT) - External resistor programmable from 7 ms to 140 ms - Disabled by connecting the WWDTSELECT pin to VREG or let the pin float • Ratiometric Output of VBAT Voltage Scaled to VREG • Automatic Thermal Shutdown • High Electromagnetic Immunity (EMI), Low Electromagnetic Emission (EME) • Robust ESD Performance: ±15 kV for LBUS and VBB pin (IEC61000-4-2) • Transient Protection for LBUS and VBB Pins in Automotive Environment (ISO7637)  2012-2014 Microchip Technology Inc. • Meets Stringent Automotive Design Requirements Including “OEM Hardware Requirements for LIN, CAN and FlexRay Interfaces in Automotive Applications”, Version 1.3, May 2012 • Multiple Package Options Including Small 5x5 QFN Description: The MCP2050 provides a bidirectional, half-duplex communication physical interface to meet the LIN bus specification Revision 2.1 and SAE J2602. The device incorporates a voltage regulator with 5V or 3.3V 70 mA regulated power supply output. The on-chip WWDT allows users to adjust the size of the reset window by using an external resistor. The ratiometric VBAT pin scales down VBAT to the range of VREG so it can be monitored by an A/D converter. The device has been designed to meet the stringent quiescent current requirements of the automotive industry and will survive +43V load dump transients, and double battery jumps. MCP2050 family members: - MCP2050-500, 14-pin, LIN driver with 5.0V regulator - MCP2050-330, 14-pin, LIN driver with 3.3V regulator - MCP2050-500, 20-pin QFN, LIN driver with 5.0V regulator - MCP2050-330, 20-pin QFN, LIN driver with 3.3V regulator DS20002299C-page 1 MCP2050 Package Types 5 16 RESET 17 1 2 3 4 VBAT RATIO EP 21 NC LBUS VSS 8 9 10 RXD CS/LWAKE VREG TXD 15 14 13 12 11 WWDTTRIG WWDTSELECT FAULT/TXE VBB NC NC NC 11 10 9 8 NC NC 4 5 6 7 WWDTRESET WWDTTRIG WWDTSELECT FAULT/TXE VBB LBUS VSS 20 14 13 12 6 7 TXD RESET NC 1 2 3 19 18 VBAT RATIO RXD CS/LWAKE VREG WWDTRESET NC MCP2050 5 x 5 QFN* MCP2050 PDIP, SOIC * Includes Exposed Thermal Pad (EP), see Table 1-2. Block Diagram 4.2V WWDTTRIG Programmable Windowed Watchdog WWDTselect Short-Circuit Protection VREG RESET Thermal Protection Voltage Regulator VREG Internal Circuits 4.2V VREG Wake-Up Logic and Power Control WWDTRESET VBB Ratiometric Reference Bus Wakeup RXD CS/LWAKE ~30 kΩ Slope Control LBUS TXD Bus Dominant Timer FAULT/TXE VSS VBB Thermal and Short-Circuit Protection DS20002299C-page 2 VREG VBATRATIO 300Ω  2012-2014 Microchip Technology Inc. MCP2050 1.0 FUNCTION DESCRIPTION The MCP2050 provides a physical interface between a microcontroller and a LIN half-duplex bus. It is intended for automotive and industrial applications with serial bus baud rates up to 20 kbaud. This device will translate the CMOS/TTL logic levels to LIN logic levels, and vice versa. The device offers optimum EMI and ESD performance; it can withstand high voltage on the LIN bus. The device supports two low-power modes to meet automotive industry power consumption requirements. The MCP2050 also provides a +5V or 3.3V 70 mA regulated power output. FIGURE 1-1: POR(2) VREG OFF RX OFF TX OFF 1.1 Modes of Operation The MCP2050 works in five modes: Power-On Reset mode, Power-Down mode, Ready mode, Operation mode, and Transmitter Off mode. For an overview of all operational modes, please refer to Table 1-1. For the operational mode transition, please refer to Figure 1-1. STATE DIAGRAM VBB > VON READY VREG ON RX ON TX OFF CS/LWAKE = 1& FAULT/TXE = 0 CS/LWAKE = 1 OR Voltage Rising Edge on LBUS CS/LWAKE = 1 & FAULT/TXE = 1 (3) & TXD = 1& VREG_OK = 1 (1) CS/LWAKE = 1& FAULT/TXE = 1 (3)& TXD = 1 TX OFF VREG ON RX ON TX OFF CS/LWAKE = 0 POWER-DOWN VREG OFF RX OFF TX OFF OPERATION VREG ON RX ON TX ON CS/LWAKE = 1& FAULT/TXE = 0 CS/LWAKE = 0 Note 1: VREG_OK: Regulator Output Voltage > 0.8VREG_NOM. 2: If the voltage on pin VBB falls below VOFF, the device will enter Power-On Reset mode from all other modes, which is not shown in the figure. 3: FAULT/TXE = 1 represents input and no fault conditions. FAULT/TXE = 0 represents input low or a fault condition. Refer to Table 1-3.  2012-2014 Microchip Technology Inc. DS20002299C-page 3 MCP2050 1.1.1 POWER-ON-RESET MODE Upon application of VBB, or whenever the voltage on VBB is below the threshold of regulator turn-off voltage VOFF (typically. 4.50V), the device enters Power-On Reset mode (POR). During this mode, the device maintains the digital section in a reset mode and waits until the voltage on pin VBB rises above the threshold of regulator turn-on voltage VON (typically 5.75V) to enter into Ready mode. In Power-On-Reset mode, the LIN physical layer and voltage regulator are disabled, and RESET output is forced to low. 1.1.2 READY MODE The device enters Ready mode from POR mode after the voltage on VBB rises above the threshold of regulator turn-on voltage VON or from Power-Down mode when a remote or local wake-up event happens. Upon entering Ready mode, the voltage regulator and receiver section of the transceiver are powered up. The transmitter remains in off state. The device is ready to receive data but not to transmit. In order to minimize the power consumption, the regulator operates in a reduced-power mode. It has a lower GBW product and thus is slower. However, the 70 mA drive capability is unchanged. The device stays in Ready mode until the output of the voltage regulator has stabilized and the CS/LWAKE pin is high (‘1’). 1.1.3 OPERATION MODE If VREG is OK (VREG > 0.8 VREG_NOM), CS/LWAKE pin, FAULT/TXE pin and TXD pin are high, the part enters the Operation mode from either Ready or Transmitter Off mode. In this mode, all internal modules are operational. The internal pull-up resistor between LBUS and VBB is connected only in this mode. The device goes into the Power-Down mode at the falling edge on CS/LWAKE; or to the Transmitter Off mode at the falling on FAULT/TXE while CS/LWAKE stays high. 1.1.4 TRANSMITTER OFF MODE In Transmitter Off mode, the receiver is enabled but the LBUS transmitter is off. It is a lower-power mode. In order to minimize the power consumption, the window watchdog timer is disabled and the regulator operates in a reduced-power mode. It has a lower GBW product and thus is slower. However, the 70 mA drive capability is unchanged. The transmitter may be re-enabled whenever the FAULT/TXE signal returns high, by removing the internal fault condition and the CPU returning the FAULT/TXE high. The transmitter will not be enabled even if the FAULT/TXE pin is brought high externally, when the internal fault is still present. However, externally forcing the FAULT/TXE high, while the internal fault is still present, should be avoided since this will induce high current and power dissipation in the FAULT/TXE pin. The transmitter is also turned off whenever the voltage regulator is unstable or recovering from a fault. This prevents unwanted disruption of the bus during times of uncertain operation. 1.1.5 POWER-DOWN MODE In Power-Down mode, the transceiver and the voltage regulator are both off. Only the Bus Wake-up section and the CS/LWAKE pin wake-up circuits are in operation. This is the lowest-power mode. If any bus activity (e.g. a BREAK character) occurs during Power-Down mode, the device will immediately enter Ready mode and enable the voltage regulator. Then, once the regulator output has stabilized (approximately 0.3 ms to 1.2 ms) it goes to Operation mode. Refer to Section 1.1.6 “Remote Wake-up” for more details. The part will also enter Ready mode from Power-Down mode, followed by Operation mode, if the CS/LWAKE pin becomes active high (‘1’). 1.1.6 REMOTE WAKE-UP The remote wake-up sub module observes the LBUS in order to detect bus activity. In Power-Down mode, normal LIN recessive/dominant threshold is disabled, and the LIN bus Wake-Up Voltage Threshold VWK(LBUS) is used to detect bus activities. Bus activity is detected when the voltage on the LBUS falls below the LIN bus Wake-Up Voltage Threshold VWK(LBUS) (approximately 3.4V) for at least tBDB (a typical duration of 80 µs) followed by a rising edge. Such a condition causes the device to leave Power-Down mode DS20002299C-page 4  2012-2014 Microchip Technology Inc. MCP2050 . TABLE 1-1: State OVERVIEW OF OPERATIONAL MODES Transmitter Receiver Internal Voltage Watch Dog Wake Module Regulator Timer Operation Comments PoR Off Off Off Off Off Proceed to Ready mode after VBB>VON. — Ready Off On Off On On If CS/LWAKE high, then proceed to Operation or Transmitter Off mode. Bus Off state Operation On On Off On On If CS/LWAKE low level, then proceed to Power-Down. If FAULT/TXE low level, then Transmitter-Off mode. Normal Operation mode Power-Down Off Off On Activity Detect Off Off On LIN bus rising edge or CS/LWAKE high level, proceed to READY mode. LowestPower mode Transmitter Off Off On Off On Off If CS/LWAKE low level, then proceed to Power down. If FAULT/TXE high, then Operation mode. Bus Off state, Lower-Power mode 1.2 1.2.1 Windowed Watchdog Reset The Watchdog Timer monitors for activity on the Windowed Watchdog Timer Trigger input pin WWDTTRIG. The WWDTTRIG pin is expected to be strobed within a given time frame. When this time frame has expired without an edge transition on the WWDTTRIG pin, the WWDTRESET pin is driven active (low) to reset the system. This feature is enabled by connecting a resistor between the WWDTSELECT pin and VSS. Monitoring is then done by requiring the host processor to force a falling edge transition on the WWDTTRIG pin within a predetermined time frame (TWD). WWDT DURING INITIAL POWER-UP The WWDTRESET is driven high after a power-on reset. The Watchdog Timer begins counting at this point, awaiting an edge on WWDTTRIG pin. Note that there is no window enabled, yet. If no falling edge is detected on the WWDTTRIG pin before the timer expires, the WWDTRESET is pulse low and the timer is restarted. When a trigger edge on the WWDTTRIG pin is seen, the window is enabled and the timer is reset. The start time of the trigger window is fixed at 50% of the total watchdog period, after the last trigger. The length of the window is determined by the value of the resistor on pin WWDTSELECT. The Watchdog Timer is disabled if WWDTSELECT is floating. FIGURE 1-2: WWDTRESET DURING INITIAL POWER-UP Internal reset WWDTRESET tPOWERUP tWDRST tPOWERUP tWDRST tPOWERUP Figure 1-2 shows the behavior of the WWDTRESET pin after a system reset with no trig at all. If no trig is given during the power-up window, WWDTRESET is reset low for the time tWDRST. Duration for tPOWERUP and tWDRST are: • tPOWERUP = 0.8 ms x (RWWDTSELECT+1) typical • tWDRST = 150 μs typical • RWWDTSELECT is in kΩ The power-up window length tPOWERUP duration is determined by the value of the resistor connected between pin WWDTSELECT and pin VSS, while the reset pulse duration is about 150 μs. Once a trig is asserted, the power-up sequence “stops” and the normal behavior begins.  2012-2014 Microchip Technology Inc. DS20002299C-page 5 MCP2050 1.2.2 WINDOWED WATCHDOG BEHAVIOR EQUATION 1-1: After windowed watchdog begins its normal behavior, three different cases can appear. tWLENGTH = (0.175 ms × RWWDTSELECT) + 1.2 typical • A pulse (falling edge) on the WWDTTRIG pin is detected within the trigger window; the watchdog timer will be reset, and a new watchdog period will begin; WWDTRESET pin remains high (Figure 1-3.) tWDRST = 150 μs typical RWWDTSELECT is in kΩ; its value ranges from 33 kΩ to 680 kΩ and window length ranges from 7 ms to 120 ms typical. • A pulse (falling edge) on the WWDTTRIG pin is detected before the trigger window (too early trigger); WWDTRESET is asserted (low) immediately after the falling edge is detected for approximately tWDRST; the counter is reset and the next watchdog period begins at the rising edge of the voltage on WWDTRESET pin (Figure 1-12). If the WWDTSELECT pin is floating, the watchdog is disabled and the WWDTRESET remains high. • No pulse on the WWDTTRIG pin is detected during the whole watchdog window (no trigger); WWDTRESET is asserted (low) for approximately tWDRST when the timer has expired; the counter is reset and the next watchdog period begins at the rising edge of the voltage on WWDTRESET pin (Figure 1-5). The trigger window is between 50% to 100% of the watchdog window length, tWLENGTH. The window length is determined by the external resistor between WWDTSELECT pin and VSS. FIGURE 1-3: CORRECT TRIGGER Window length Next period 50% TWD Too early Trigger window Earliest trigger point Lastest trigger point 1 WWDTTRIG 0 1 WWDTRESET New period begins Window length 50% Too early DS20002299C-page 6 Trigger window  2012-2014 Microchip Technology Inc. MCP2050 FIGURE 1-4: TOO EARLY TRIGGER Window length Next period 50% TWD Too early Trigger window Earliest trigger point Lastest trigger point 1 WWDTTRIG 0 1 tWDRST WWDTRESET 0 New period begins Window length 50% Too early FIGURE 1-5: Trigger window NO TRIGGER Window length Next period 50% TWD Too early Trigger window Earliest trigger point Lastest trigger point 1 No trigger, timer expired WWDTTRIG 1 WWDTRESE T tWDRST 0 Window length New period begins 50% Too early  2012-2014 Microchip Technology Inc. Trigger window DS20002299C-page 7 MCP2050 1.3 Pin Descriptions Please refer to Table 1-2 for the pinout overview. TABLE 1-2: PINOUT DESCRIPTIONS Devices PIN Name Function PIN Type 14-Pin PDIP, SOIC 5 x 5 QFN VBATRATIO 1 18 Analog Output RXD 2 1 Output CS/LWAKE 3 2 VREG 4 3 Output TXD 5 4 Input, HV-tolerant RESET 6 5 Output NC 7 6,9,10,11, 16,19,20 Not Connected Normal Operation VBATRATIO = VBAT/24 × VREG Receive Data Output TTL Input, HV-tolerant Chip Select and Local Wake-up Input Voltage Regulator Output Transmit Data Input Reset Output — VSS 8 8 Power Ground LBUS 9 7 I/O, HV LIN Bus VBB 10 12 Power Battery FAULT/TXE 11 13 I/O, HV-tolerant WWDTSELECT 12 14 Input A Resistor between this pin and Ground determines the Watchdog Window length WWDTTRIG 13 15 Input Windowed Watchdog Trigger Input WWDTRESET 14 17 Output, HV-tolerant Windowed Watchdog Reset Output EP — 21 1.3.1 Exposed Thermal Pad Exposed Thermal Pad can be left unconnected, (EP) or connected to the ground. VBATRATIO This is an analog output pin that reflects the voltage at the VBAT pin. It is scaled by VREG such that: VBATRATIO = VBAT/24 × VREG 0 VON, regulator on. VBB  minimum VBB to maintain regulation. VBB < VOFF, regulator will turn off. DS20002299C-page 13 MCP2050 FIGURE 1-10: VOLTAGE REGULATOR OUTPUT ON OVER CURRENT SITUATION IREG mA lLIM 0 t VREG 6 5 V VREG-NOM 4 VSD 3 2 1 0 Note 1: 2: 1.6 1.6.1 (1) (2) IREG less than lLIM, regulator on. After IREG exceeds lLIM, the voltage regulator output will be reduced until VSD is reached. Optional External Protection REVERSE BATTERY PROTECTION An external reverse-battery-blocking diode should be used to provide polarity protection (see Figure 1-12). 1.6.2 t TRANSIENT VOLTAGE PROTECTION (LOAD DUMP) An external 43V transient suppressor (TVS) diode, between VBB and ground, with a transient protection resistor (RTP) in series with the battery supply and the VBB pin protects the device from power transients and ESD events greater than 43V (see Figure 1-12). The maximum value for the RTP protection resistor depends on two parameters: the minimum voltage the part will start at, and the impacts of this RTP resistor on the VBB value, thus on the Bus recessive level and slopes. Equation 1-4 provides a max RTP value according to the maximum relative variation the user can accept on the slope when IREG varies. Since both Equation 1-2 and Equation 1-3 must be fulfilled, the maximum allowed value for RTP is thus the smaller of the two values found when solving Equation 1-2 and Equation 1-3. Usually Equation 1-2 gives the higher constraint (smaller value) for RTP as shown in the following example where VBATmin is 8V. However, the user needs to check that the value found with Equation 1-2 also fulfills Equation 1-3 and Equation 1-4. While this protection is optional, it should be considered as good engineering practice. This leads to a set of three equations to fulfill. Equation 1-2 provides a max RTP value according to the minimum battery voltage the user wants the part to start at. Equation 1-3 provides a max RTP value according to the maximum error on the recessive level thus VBB since the part uses VBB as the reference value for the recessive level. DS20002299C-page 14  2012-2014 Microchip Technology Inc. MCP2050 EQUATION 1-2: V BATmin – 5.5V R TP  ------------------------------------250mA The following formula gives an indication of the minimum value of CBAT using RTOT and L: EQUATION 1-5: 5.5V = VOFF + 1.0V 250 mA is the peak current at power-on when VBB =5.5V Assume VBATMIN = 8V. Equation 1-2 shows 10Ω EQUATION 1-3: V RECESSIVE R TP  ---------------------------------I REGMAX Where: L = Inductor (measured in mH) RTOT = RLINE + RTP (measured in ) Equation 1-5 allows lower CBAT/CREG values than the 10x ratio we recommend. Assume that we have a good quality VBAT connection with RTOT = 0.1 and L = 0.1 mH. Solving the equation gives CBAT/CREG = 1. Where: VRECESSIVE = Maximum variation tolerated on the recessive level Assume ∆VRECCESSIVE = 1V and IREGMAX = 50 mA Equation 1-3 shows 20Ω EQUATION 1-4: Slope   V BATMIN – 1V  R TP  ----------------------------------------------------------------I REGMAX Where: Slope = Maximum variation tolerated on the slope level IREGMAX = Maximum current the current will provide to the load VBATMIN > VOFF + 1.0V If we increase RTOT up to 1 the result becomes CBAT/CREG = 1.4. However, if the connection is highly resistive or highly inductive (poor connection), the CBAT/CREG ratio greatly increases. TABLE 1-5: CBAT/CREG RATIO BY VBAT CONNECTION TYPE Connection Type RTOT L CBAT/CREG Ratio Good 0.1 0.1 mH 1 Typical 1 0.1 mH 1.4 Highly inductive 0.1 1 mH 7 Highly resistive 10 0.1 mH 7 Figure 1-11 shows the minimum recommended CBAT/CREG ratio as a function of the impedance of the VBAT connection. FIGURE 1-11: MINIMUM RECOMMENDED CBAT/CREG RATIO Assume ∆Slope = 15%, VBATMIN = 8V and IREGMAX = 50 mA. Equation 1-3 shows 20Ω CBAT/CREG Ratio as Function of the VBAT Line Impedance CBAT CAPACITOR Selecting CBAT = 10 x CREG is recommended. However, this leads to a high-value capacitor. Lower values for CBAT capacitor can be used with respect to some rules. In any case, the voltage at the VBB pin should remain above VOFF when the device is turned on. The current peak at start-up (due to the fast charge of the CREG and CBAT capacitors) may induce a significant drop on the VBB pin. This drop is proportional to the impedance of the VBAT connection (see Figure 1-12). 10 RBAT = 10 RBAT = 4 CBAT/CREG 1.6.3 2 2 100L + R TOT ----------------------------------2 RTOT 2 1 + L + ------------100 C BAT -------------- = C REG RBAT = 2 RBAT = 1 RBAT = 0.3 RBAT = 0.1 1 0.1 1 VBAT Line Inductance [mH] The VBAT connection is mainly inductive and resistive. Therefore, it can be modeled as a resistor (RTOT) in series with an inductor (L). RTOT and L can be measured.  2012-2014 Microchip Technology Inc. DS20002299C-page 15 MCP2050 1.7 Typical Applications FIGURE 1-12: TYPICAL APPLICATION CIRCUIT VBAT VBAT RTP 220 kΩ 43V(5) CREG WAKE-UP VDD VREG TXD TXD (6) RXD I/O VBB 1 kΩ RXD VBATRATIO A/D MCU Master Node Only VBB CBAT LIN Bus LBUS CS/LWAKE (3) I/O FAULT/TXE I/O WWDTTRIG MMBZ27V (4) 220 pF WWDTRESET IRQ RESET RESET VSS (6) WWDTSELECT VSS 100 nF Note 1: CREG, the load capacitor, should be ceramic or tantalum rated for extended temperatures, 1.0-22 µF. See Figure 2-1 for selecting the correct ESR. 2: CBAT is the filter capacitor for the external voltage supply. It’s typically 10 · CREG, with no ESR restriction. See Figure 1-11 to select the minimum recommended value for CBAT. The RTP value is added to the line resistance. 3: This diode is only needed if CS/LWAKE is connected to VBAT supply. 4: ESD protection diode. 5: This component is for additional load dump protection. 6: An external 10 kΩ resistor is recommended for some applications. DS20002299C-page 16  2012-2014 Microchip Technology Inc. MCP2050 FIGURE 1-13: TYPICAL LIN NETWORK CONFIGURATION 40m + Return LIN bus 1 kΩ VBB LIN bus MCP2050 LIN bus MCP2050 Slave 1 (MCU) LIN bus MCP202XA LIN bus MCP2003 Slave 2 (MCU) Slave n