MCP23008/MCP23S08
8-Bit I/O Expander with Serial Interface
Features
• 8-Bit Remote Bidirectional I/O Port
- I/O pins default to input
• High-Speed I2C Interface (MCP23008)
- 100 kHz
- 400 kHz
- 1.7 MHz
• High-Speed SPI Interface (MCP23S08)
- 10 MHz
• Hardware Address Pins
- Three for the MCP23008 to allow up to eight
devices on the bus
- Two for the MCP23S08 to allow up to four
devices using the same Chip Select
• Configurable Interrupt Output Pin
- Configurable as active-high, active-low or
open-drain
• Configurable Interrupt Source
- Interrupt-on-change from configured defaults
or pin change
• Polarity Inversion Register to Configure the
Polarity of the Input Port Data
• External Reset Input
• Low Standby Current: 1 µA (max.)
• Operating Voltage:
- 1.8V to 5.5V at -40°C to +85°C
I2C at 100 kHz
SPI at 5 MHz
- 2.7V to 5.5V at -40°C to +85°C
I2C at 400 kHz
SPI at 10 MHz
- 4.5V to 5.5V at -40°C to +125°C
I2C at 1.7 kHz
SPI at 10 MHz
Packages
•
•
•
•
18-pin PDIP (300 mil)
18-pin SOIC (300 mil)
20-pin SSOP
20-pin QFN
Block Diagram
MCP23S08
SCK
SI
SO
MCP23008
SCL
SDA
Serial
Interface
MCP23S08
A1:A0
A2:A0
3
Decode
8
GPIO
Control
RESET
INT
Serializer/
Deserializer
Interrupt
Logic
GP0
GP1
GP2
GP3
GP4
GP5
GP6
GP7
8
VDD
VSS
2004-2019 Microchip Technology Inc.
POR
Configuration/
Control
Registers
DS20001919F-page 1
MCP23008/MCP23S08
Package Types
MCP23008
1
2
3
4
5
6
7
8
9
18
17
16
15
14
13
12
11
10
SSOP
SCL
SDA
A2
A1
A0
RESET
NC
INT
VSS
N/C
VDD
GP7
GP6
GP5
GP4
GP3
GP2
GP1
GP0
1
2
3
4
5
6
7
8
9
10
MCP23008
SCL
SDA
A2
A1
A0
RESET
NC
INT
VSS
MCP23008
PDIP/SOIC
20
19
18
17
16
15
14
13
12
11
VDD
GP7
GP6
GP5
GP4
GP3
GP2
GP1
GP0
N/C
SDA
SCL
VDD
VSS
GP7
20
19
18
17
16
QFN
A2
1
15
GP6
A1
2
14
GP5
A0
3
13
GP4
RESET
4
12
GP3
NC
5
11
GP2
2004-2019 Microchip Technology Inc.
6
7
8
9
10
N/C
INT
N/C
GP0
GP1
MCP23008
DS20001919F-page 2
MCP23008/MCP23S08
Package Types: (Continued)
MCP23S08
1
2
3
4
5
6
7
8
9
18
17
16
15
14
13
12
11
10
SSOP
SCK
SI
SO
A1
A0
RESET
CS
INT
VSS
N/C
VDD
GP7
GP6
GP5
GP4
GP3
GP2
GP1
GP0
1
2
3
4
5
6
7
8
9
10
MCP23S08
SCK
SI
SO
A1
A0
RESET
CS
INT
VSS
MCP23S08
PDIP/SOIC
20
19
18
17
16
15
14
13
12
11
VDD
GP7
GP6
GP5
GP4
GP3
GP2
GP1
GP0
N/C
SO
1
A1
2
SI
SCK
VDD
VSS
GP7
20
19
18
17
16
QFN
MCP23S08
15
GP6
14
GP5
13
GP4
2004-2019 Microchip Technology Inc.
10
GP2
GP1
11
9
5
GP0
CS
8
GP3
N/C
12
7
4
INT
RESET
6
3
N/C
A0
DS20001919F-page 3
MCP23008/MCP23S08
1.0
DEVICE OVERVIEW
The MCP23X08 device provides 8-bit, general
purpose, parallel I/O expansion for I2C bus or SPI
applications. The two devices differ in the number of
hardware address pins and the serial interface:
• MCP23008 – I2C interface; three address pins
• MCP23S08 – SPI interface; two address pins
The MCP23X08 consists of multiple 8-bit Configuration
registers for input, output and polarity selection. The
system master can enable the I/Os as either inputs or
outputs by writing the I/O Configuration bits. The data
for each input or output is kept in the corresponding
Input or Output register. The polarity of the Input Port
register can be inverted with the Polarity Inversion
register. All registers can be read by the system master.
1.1
The interrupt output can be configured to activate
under two conditions (mutually exclusive):
1.
2.
When any input state differs from its
corresponding Input Port register state, this is
used to indicate to the system master that an
input state has changed.
When an input state differs from a preconfigured
register value (DEFVAL register).
The Interrupt Capture register captures port values at
the time of the interrupt, thereby saving the condition
that caused the interrupt.
The Power-on Reset (POR) sets the registers to their
default values and initializes the device state machine.
The hardware address pins are used to determine the
device address.
Pin Descriptions
TABLE 1-1:
PINOUT DESCRIPTION
Pin
Name
PDIP/
SOIC
QFN
SSOP
Pin
Type
SCL/SCK
1
19
1
I
SDA/SI
2
20
2
I/O
Serial data I/O (MCP23008)/Serial data input (MCP23S08).
A2/SO
3
1
3
I/O
Hardware address input (MCP23008)/
Serial data output (MCP23S08).
A2 must be biased externally.
A1
4
2
4
I
Hardware address input. Must be biased externally.
A0
5
3
5
I
Hardware address input. Must be biased externally.
RESET
6
4
6
I
External Reset input. Must be biased externally.
NC/CS
7
5
7
I
No connect (MCP23008)/External Chip Select input (MCP23S08).
INT
8
7
8
O
Interrupt output. Can be configured for active-high, active-low or
open-drain.
VSS
9
17
9
P
Ground.
GP0
10
9
12
I/O
Bidirectional I/O pin. Can be enabled for interrupt-on-change and/or
internal weak pull-up resistor.
GP1
11
10
13
I/O
Bidirectional I/O pin. Can be enabled for interrupt-on-change and/or
internal weak pull-up resistor.
GP2
12
11
14
I/O
Bidirectional I/O pin. Can be enabled for interrupt-on-change and/or
internal weak pull-up resistor.
GP3
13
12
15
I/O
Bidirectional I/O pin. Can be enabled for interrupt-on-change and/or
internal weak pull-up resistor.
GP4
14
13
16
I/O
Bidirectional I/O pin. Can be enabled for interrupt-on-change and/or
internal weak pull-up resistor.
GP5
15
14
17
I/O
Bidirectional I/O pin. Can be enabled for interrupt-on-change and/or
internal weak pull-up resistor.
GP6
16
15
18
I/O
Bidirectional I/O pin. Can be enabled for interrupt-on-change and/or
internal weak pull-up resistor.
GP7
17
16
19
I/O
Bidirectional I/O pin. Can be enabled for interrupt-on-change and/or
internal weak pull-up resistor.
VDD
18
18
20
P
Power.
N/C
—
6, 8
10, 11
—
—
2004-2019 Microchip Technology Inc.
Function
Serial clock input.
DS20001919F-page 4
MCP23008/MCP23S08
1.2
Power-on Reset (POR)
The on-chip POR circuit holds the device in Reset until
VDD has reached a high enough voltage to deactivate
the POR circuit (i.e., release the device from Reset).
The maximum VDD rise time is specified in
Section 2.0, Electrical Characteristics.
When the device exits the POR condition (releases
Reset), device operating parameters (i.e., voltage,
temperature, serial bus frequency, etc.) must be met to
ensure proper operation.
1.3
Serial Interface
1.3.2
1.3.2.1
I2C INTERFACE
I2C Write Operation
The I2C Write operation includes the control byte and
register address sequence, as shown in the bottom of
Figure 1-1. This sequence is followed by eight bits of
data from the master and an Acknowledge (ACK) from
the MCP23008. The operation is ended with a STOP
or RESTART condition being generated by the master.
Data is written to the MCP23008 after every byte
transfer. If a STOP or RESTART condition is
generated during a data transfer, the data will not be
written to the MCP23008.
This block handles the functionality of the I2C
(MCP23008) or SPI (MCP23S08) interface protocol.
The MCP23X08 contains eleven registers that can be
addressed through the serial interface block (Table 1-2):
Byte writes and sequential writes are both supported
by the MCP23008. The MCP23008 increments its
address counter after each ACK during the data
transfer.
TABLE 1-2:
1.3.2.2
Address
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
1.3.1
REGISTER ADDRESSES
Access to:
IODIR
IPOL
GPINTEN
DEFVAL
INTCON
IOCON
GPPU
INTF
INTCAP (Read-only)
GPIO
OLAT
SEQUENTIAL OPERATION BIT
The Sequential Operation (SEQOP) bit (IOCON
register) controls the operation of the Address Pointer.
The Address Pointer can either be enabled (default) to
allow the Address Pointer to increment automatically
after each data transfer, or it can be disabled.
When
operating
in
Sequential
mode
(IOCON.SEQOP = 0), the Address Pointer automatically increments to the next address after each byte
is clocked.
When operating in Byte mode (IOCON.SEQOP = 1),
the MCP23X08 does not increment its address
counter after each byte during the data transfer. This
gives the ability to continually read the same address
by providing extra clocks (without additional control
bytes). This is useful for polling the GPIO register for
data changes.
2004-2019 Microchip Technology Inc.
I2C Read Operation
The I2C Read operation includes the control byte
sequence, as shown in the bottom of Figure 1-1. This
sequence is followed by another control byte (including the START condition and ACK) with the R/W bit
equal to a logic ‘1’ (R/W = 1). The MCP23008 then
transmits the data contained in the addressed register.
The sequence is ended with the master generating a
STOP or RESTART condition.
1.3.2.3
I2C Sequential Write/Read
For sequential operations (Write or Read), instead of
transmitting a STOP or RESTART condition after the
data transfer, the master clocks the next byte pointed to
by the Address Pointer (see Section 1.3.1 “Sequential Operation Bit” for details regarding sequential
operation control).
The sequence ends with the master sending a STOP or
RESTART condition.
The MCP23008 Address Pointer will roll over to
address zero after reaching the last register address.
Refer to Figure 1-1.
1.3.3
1.3.3.1
SPI INTERFACE
SPI Write Operation
The SPI Write operation is started by lowering CS. The
Write command (slave address with R/W bit cleared) is
then clocked into the device. The opcode is followed by
an address and at least one data byte.
1.3.3.2
SPI Read Operation
The SPI Read operation is started by lowering CS. The
SPI Read command (slave address with R/W bit set) is
then clocked into the device. The opcode is followed by
an address, with at least one data byte being clocked
out of the device.
DS20001919F-page 5
MCP23008/MCP23S08
MCP23008 I2C DEVICE PROTOCOL
FIGURE 1-1:
S - START
SR - RESTART
S
OP
DIN
W ADDR
DIN
....
P
P - STOP
w
- Write
SR
OP
R
DOUT ....
DOUT
P
OP
W
DIN
DIN
P
R - Read
OP
- Device opcode
SR
ADDR
- Device address
P
DOUT
- Data out from MCP23008
DIN
....
- Data into MCP23008
OP
S
DOUT
R
SR
SR
OP
W
OP
DOUT
....
R
ADDR
P
DOUT
....
DOUT
P
DIN
....
DIN
P
P
Byte and Sequential Write
Byte
S
OP
W
ADDR
DIN
Sequential
S
OP
W ADDR
DIN
P
DIN
....
P
Byte and Sequential Read
1.3.3.3
Byte S
OP
W
SR
OP
R
DOUT
Sequential S
OP
W
SR
OP
R
DOUT
SPI Sequential Write/Read
For sequential operations, instead of deselecting the
device by raising CS, the master clocks the next byte
pointed to by the Address Pointer.
1.4
P
....
DOUT
P
Hardware Address Decoder
The sequence ends by the raising of CS.
The hardware address pins are used to determine the
device address. To address a device, the corresponding address bits in the control byte must match the pin
state.
The MCP23S08 Address Pointer will roll over to
address zero after reaching the last register address.
• MCP23008 has address pins A2, A1 and A0.
• MCP23S08 has address pins A1 and A0.
The pins must be biased externally.
2004-2019 Microchip Technology Inc.
DS20001919F-page 6
MCP23008/MCP23S08
1.4.1
ADDRESSING I2C DEVICES
(MCP23008)
The MCP23008 is a slave I2C device that supports 7-bit
slave addressing, with the read/write bit filling out the
control byte. The slave address contains four fixed bits
and three user-defined hardware address bits (pins A2,
A1 and A0). Figure 1-2 shows the control byte format.
1.4.2
I2C CONTROL BYTE
FORMAT
FIGURE 1-2:
Control Byte
S
0
1
0
A2 A1 A0 R/W ACK
0
Slave Address
R/W bit
ACK bit
Start
bit
ADDRESSING SPI DEVICES
(MCP23S08)
R/W = 0 = write
R/W = 1 = read
The MCP23S08 is a slave SPI device. The slave
address contains five fixed bits and two user-defined
hardware address bits (pins A1 and A0), with the
read/write bit filling out the control byte. Figure 1-3
shows the control byte format.
FIGURE 1-3:
SPI CONTROL BYTE
FORMAT
CS
Control Byte
0
1
0
0
A1 A0 R/W
0
Slave Address
R/W bit
R/W = 0 = write
R/W = 1 = read
I2C ADDRESSING REGISTERS
FIGURE 1-4:
S
0
1
0
0
A2 A1 A0
0
ACK
A7
A6
A5
A4
A3
A2
A1
A0
A1
A0
ACK
R/W = 0
Device Opcode
Register Address
The ACKs are provided by the MCP23008.
FIGURE 1-5:
SPI ADDRESSING REGISTERS
CS
0
1
0
0
0
A1 A0 R/W
Device Opcode
2004-2019 Microchip Technology Inc.
A7
A6
A5
A4
A3
A2
Register Address
DS20001919F-page 7
MCP23008/MCP23S08
1.5
GPIO Port
1.6
The GPIO module contains the data port (GPIO),
internal pull-up resistors and the Output Latches
(OLAT).
Configuration and Control
Registers
The Configuration and Control blocks contain the
registers as shown in Table 1-3.
Reading the GPIO register reads the value on the port.
Reading the OLAT register only reads the OLAT, not
the actual value on the port.
Writing to the GPIO register actually causes a write to
the OLAT. Writing to the OLAT register forces the
associated output drivers to drive to the level in OLAT.
Pins configured as inputs turn off the associated output
driver and put it in high-impedance.
TABLE 1-3:
Register
Name
IODIR
CONFIGURATION AND CONTROL REGISTERS
Address
(hex)
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
POR/RST
value
00
IO7
IO6
IO5
IO4
IO3
IO2
IO1
IO0
1111 1111
IPOL
01
IP7
IP6
IP5
IP4
IP3
IP2
IP1
IP0
0000 0000
GPINTEN
02
GPINT7
GPINT6
GPINT5
GPINT4
GPINT3
GPINT2
GPINT1
GPINT0
0000 0000
DEFVAL
03
DEF7
DEF6
DEF5
DEF4
DEF3
DEF2
DEF1
DEF0
0000 0000
INTCON
04
IOC7
IOC6
IOC5
IOC4
IOC3
IOC2
IOC1
IOC0
0000 0000
IOCON
05
—
—
SREAD
DISSLW
HAEN*
ODR
INTPOL
—
--00 000-
GPPU
06
PU7
PU6
PU5
PU4
PU3
PU2
PU1
PU0
0000 0000
INTF
07
INT7
INT6
INT5
INT4
INT3
INT2
INT1
INTO
0000 0000
INTCAP
08
ICP7
ICP6
ICP5
ICP4
ICP3
ICP2
ICP1
ICP0
0000 0000
GPIO
09
GP7
GP6
GP5
GP4
GP3
GP2
GP1
GP0
0000 0000
OLAT
0A
OL7
OL6
OL5
OL4
OL3
OL2
OL1
OL0
0000 0000
* Not used on the MCP23008.
2004-2019 Microchip Technology Inc.
DS20001919F-page 8
MCP23008/MCP23S08
1.6.1
I/O DIRECTION (IODIR) REGISTER
Controls the direction of the data I/O.
When a bit is set, the corresponding pin becomes an
input. When a bit is clear, the corresponding pin
becomes an output.
REGISTER 1-1:
IODIR – I/O DIRECTION REGISTER (ADDR 0x00)
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
IO7
IO6
IO5
IO4
IO3
IO2
IO1
IO0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-0
x = Bit is unknown
IO7:IO0: These bits control the direction of data I/O [7:0]
1 = Pin is configured as an input
0 = Pin is configured as an output
2004-2019 Microchip Technology Inc.
DS20001919F-page 9
MCP23008/MCP23S08
1.6.2
INPUT POLARITY (IPOL) REGISTER
The IPOL register allows the user to configure the
polarity on the corresponding GPIO port bits.
If a bit is set, the corresponding GPIO register bit will
reflect the inverted value on the pin.
REGISTER 1-2:
IPOL – INPUT POLARITY PORT REGISTER (ADDR 0x01)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
IP7
IP6
IP5
IP4
IP3
IP2
IP1
IP0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-0
x = Bit is unknown
IP7:IP0: These bits control the polarity inversion of the input pins [7:0]
1 = GPIO register bit will reflect the opposite logic state of the input pin
0 = GPIO register bit will reflect the same logic state of the input pin
2004-2019 Microchip Technology Inc.
DS20001919F-page 10
MCP23008/MCP23S08
1.6.3
INTERRUPT-ON-CHANGE
CONTROL (GPINTEN) REGISTER
The GPINTEN register controls
rupt-on-change feature for each pin.
the
inter-
If a bit is set, the corresponding pin is enabled for
interrupt-on-change. The DEFVAL and INTCON
registers must also be configured if any pins are
enabled for interrupt-on-change.
REGISTER 1-3:
GPINTEN – INTERRUPT-ON-CHANGE PINS (ADDR 0x02)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
GPINT7
GPINT6
GPINT5
GPINT4
GPINT3
GPINT2
GPINT1
GPINT0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-0
x = Bit is unknown
GPINT7:GPINT0: General Purpose I/O Interrupt-on-Change [7:0]
1 = Enable GPIO input pin for interrupt-on-change event
0 = Disable GPIO input pin for interrupt-on-change event
Refer to INTCON and GPINTEN.
2004-2019 Microchip Technology Inc.
DS20001919F-page 11
MCP23008/MCP23S08
1.6.4
DEFAULT COMPARE (DEFVAL)
REGISTER FOR
INTERRUPT-ON-CHANGE
The default comparison value is configured in the
DEFVAL register. If enabled (via GPINTEN and
INTCON) to compare against the DEFVAL register, an
opposite value on the associated pin will cause an
interrupt to occur.
REGISTER 1-4:
DEFVAL – DEFAULT VALUE REGISTER (ADDR 0x03)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
DEF7
DEF6
DEF5
DEF4
DEF3
DEF2
DEF1
DEF0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-0
x = Bit is unknown
DEF7:DEF0: These bits set the compare value for pins configured for interrupt-on-change from
defaults [7:0]. Refer to INTCON.
If the associated pin level is the opposite from the register bit, an interrupt occurs.
Refer to INTCON and GPINTEN.
2004-2019 Microchip Technology Inc.
DS20001919F-page 12
MCP23008/MCP23S08
1.6.5
INTERRUPT CONTROL (INTCON)
REGISTER
The INTCON register controls how the associated pin
value is compared for the interrupt-on-change feature.
If a bit is set, the corresponding I/O pin is compared
against the associated bit in the DEFVAL register. If a
bit value is clear, the corresponding I/O pin is compared
against the previous value.
REGISTER 1-5:
INTCON – INTERRUPT-ON-CHANGE CONTROL REGISTER (ADDR 0x04)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
IOC7
IOC6
IOC5
IOC4
IOC3
IOC2
IOC1
IOC0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-0
x = Bit is unknown
IOC7:IOC0: These bits control how the associated pin value is compared for interrupt-on-change [7:0]
1 = Controls how the associated pin value is compared for interrupt-on-change
0 = Pin value is compared against the previous pin value
Refer to INTCON and GPINTEN.
2004-2019 Microchip Technology Inc.
DS20001919F-page 13
MCP23008/MCP23S08
1.6.6
CONFIGURATION (IOCON)
REGISTER
The IOCON register
configuring the device:
contains
several
bits
for
• The Sequential Operation (SEQOP) controls the
incrementing function of the Address Pointer. If
the Address Pointer is disabled, the Address
Pointer does not automatically increment after
each byte is clocked during a serial transfer. This
feature is useful when it is desired to continuously
poll (read) or modify (write) a register.
• The Slew Rate (DISSLW) bit controls the slew
rate function on the SDA pin. If enabled, the SDA
slew rate will be controlled when driving from a
high to a low.
REGISTER 1-6:
• The Hardware Address Enable (HAEN) control bit
enables/disables the hardware address pins (A1,
A0) on the MCP23S08. This bit is not used on the
MCP23008. The address pins are always enabled
on the MCP23008.
• The Open-Drain (ODR) control bit
enables/disables the INT pin for open-drain
configuration.
• The Interrupt Polarity (INTPOL) control bit sets
the polarity of the INT pin. This bit is functional
only when the ODR bit is cleared, configuring the
INT pin as active push-pull.
IOCON – I/O EXPANDER CONFIGURATION REGISTER (ADDR 0x05)
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
U-0
—
—
SEQOP
DISSLW
HAEN
ODR
INTPOL
—
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-6
Unimplemented: Read as ‘0’
bit 5
SEQOP: Sequential Operation Mode
1 = Sequential operation disabled, Address Pointer does not increment
0 = Sequential operation enabled, Address Pointer increments
bit 4
DISSLW: Slew Rate Control Bit for SDA Output
1 = Slew rate disabled
0 = Slew rate enabled
bit 3
HAEN: Hardware Address Enable (MCP23S08 only)
Address pins are always enabled on MCP23008.
1 = Enables the MCP23S08 address pins
0 = Disables the MCP23S08 address pins
bit 2
ODR: This bit configures the INT pin as an open-drain output
1 = Open-drain output (overrides the INTPOL bit)
0 = Active driver output (INTPOL bit sets the polarity)
bit 1
INTPOL: This bit sets the polarity of the INT output pin
1 = Active-high
0 = Active-low
bit 0
Unimplemented: Read as ‘0’
2004-2019 Microchip Technology Inc.
x = Bit is unknown
DS20001919F-page 14
MCP23008/MCP23S08
1.6.7
PULL-UP RESISTOR
CONFIGURATION (GPPU)
REGISTER
The GPPU register controls the pull-up resistors for the
PORT pins. If a bit is set and the corresponding pin is
configured as an input, the corresponding PORT pin is
internally pulled up with a 100 k resistor.
REGISTER 1-7:
GPPU – GPIO PULL-UP RESISTOR REGISTER (ADDR 0x06)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
PU7
PU6
PU5
PU4
PU3
PU2
PU1
PU0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-0
x = Bit is unknown
PU7:PU0: These bits control the weak pull-up resistors on each pin (when configured as an input) [7:0]
1 = Pull-up enabled
0 = Pull-up disabled
2004-2019 Microchip Technology Inc.
DS20001919F-page 15
MCP23008/MCP23S08
1.6.8
INTERRUPT FLAG (INTF)
REGISTER
Note:
The INTF register reflects the interrupt condition on the
PORT pins of any pin that is enabled for interrupts via
the GPINTEN register. A ‘set’ bit indicates that the
associated pin caused the interrupt.
This register is ‘read-only’. Writes to this register will be
ignored.
REGISTER 1-8:
INTF will always reflect the pin(s) that
have an interrupt condition. For example,
one pin causes an interrupt to occur and is
captured in INTCAP and INF. If before
clearing the interrupt another pin
changes, which would normally cause an
interrupt, it will be reflected in INTF, but
not INTCAP.
INTF – INTERRUPT FLAG REGISTER (ADDR 0x07)
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
INT7
INT6
INT5
INT4
INT3
INT2
INT1
INT0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-0
x = Bit is unknown
INT7:INT0: These bits reflect the interrupt condition on the port. Will reflect the change only if interrupts
are enabled (GPINTEN) [7:0].
1 = Pin caused interrupt
0 = Interrupt not pending
2004-2019 Microchip Technology Inc.
DS20001919F-page 16
MCP23008/MCP23S08
1.6.9
INTERRUPT CAPTURE (INTCAP)
REGISTER
The INTCAP register captures the GPIO port value at
the time the interrupt occurred. The register is
‘read-only’ and is updated only when an interrupt
occurs. The register will remain unchanged until the
interrupt is cleared via a read of INTCAP or GPIO.
REGISTER 1-9:
INTCAP – INTERRUPT CAPTURED VALUE FOR PORT REGISTER (ADDR 0x08)
R-x
R-x
R-x
R-x
R-x
R-x
R-x
R-x
ICP7
ICP6
ICP5
ICP4
ICP3
ICP2
ICP1
ICP0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-0
x = Bit is unknown
ICP7:ICP0: These bits reflect the logic level on the PORT pins at the time of interrupt due to pin
change [7:0]
1 = Logic-high
0 = Logic-low
2004-2019 Microchip Technology Inc.
DS20001919F-page 17
MCP23008/MCP23S08
1.6.10
PORT (GPIO) REGISTER
The GPIO register reflects the value on the port.
Reading from this register reads the port. Writing to this
register modifies the Output Latch (OLAT) register.
REGISTER 1-10:
GPIO – GENERAL PURPOSE I/O PORT REGISTER (ADDR 0x09)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
GP7
GP6
GP5
GP4
GP3
GP2
GP1
GP0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-0
x = Bit is unknown
GP7:GP0: These bits reflect the logic level on the pins [7:0]
1 = Logic-high
0 = Logic-low
2004-2019 Microchip Technology Inc.
DS20001919F-page 18
MCP23008/MCP23S08
1.6.11
OUTPUT LATCH REGISTER (OLAT)
The OLAT register provides access to the output
latches. A read from this register results in a read of the
OLAT and not the port itself. A write to this register
modifies the output latches that modify the pins
configured as outputs.
REGISTER 1-11:
OLAT – OUTPUT LATCH REGISTER 0 (ADDR 0x0A)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
OL7
OL6
OL5
OL4
OL3
OL2
OL1
OL0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-0
x = Bit is unknown
OL7:OL0: These bits reflect the logic level on the output latch [7:0]
1 = Logic-high
0 = Logic-low
2004-2019 Microchip Technology Inc.
DS20001919F-page 19
MCP23008/MCP23S08
1.7
Interrupt Logic
FIGURE 1-7:
INTERRUPT-ON-CHANGE
FROM REGISTER
DEFAULT
The interrupt output pin will activate if an internal
interrupt occurs. The interrupt block is configured by
the following registers:
• GPINTEN – enables the individual inputs
• DEFVAL – holds the values that are compared
against the associated input port values
• INTCON – controls if the input values are
compared against DEFVAL or the previous values
on the port
• IOCON (ODR and INPOL) – configures the INT
pin as push-pull, open-drain and active-level
Only pins configured as inputs can cause interrupts.
Pins configured as outputs have no affect on INT.
Interrupt activity on the port will cause the port value to
be captured and copied into INTCAP. The interrupt will
remain active until the INTCAP or GPIO register is
read. Writing to these registers will not affect the
interrupt.
The first interrupt event will cause the port contents to
be copied into the INTCAP register. Subsequent
interrupt conditions on the port will not cause an
interrupt to occur as long as the interrupt is not cleared
by a read of INTCAP or GPIO.
1.7.1
DEFVAL
GP:
7
6
5
4
3
2
1
0
X
X
X
X
X
0
X
X
GP2
INT
ACTIVE
Port value
is captured
into INTCAP
ACTIVE
Read GPIU
or INTCAP
(INT clears only if interrupt
condition does not exist.)
INTERRUPT CONDITIONS
There are two possible configurations to cause
interrupts (configured via INTCON):
1.
2.
Pins configured for interrupt-on-pin-change
will cause an interrupt to occur if a pin changes
to the opposite state. The default state is reset
after an interrupt occurs. For example, an
interrupt occurs by an input changing from ‘1’ to
‘0’. The new initial state for the pin is a logic ‘0’.
Pins configured for interrupt-on-change from
register value will cause an interrupt to occur if
the corresponding input pin differs from the
register bit. The interrupt condition will remain as
long as the condition exists, regardless if the
INTAP or GPIO is read.
See Figure 1-6 and Figure 1-7 for more information on
interrupt operations.
FIGURE 1-6:
INTERRUPT-ON-PIN-CHANGE
GPx
INT
Port value
is captured
into INTCAP
ACTIVE
Read GPIU
or INTCAP
2004-2019 Microchip Technology Inc.
ACTIVE
Port value
is captured
into INTCAP
DS20001919F-page 20
MCP23008/MCP23S08
2.0
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings †
Ambient temperature under bias.............................................................................................................-40°C to +125°C
Storage temperature .............................................................................................................................. -65°C to +150°C
Voltage on VDD with respect to VSS ......................................................................................................... -0.3V to +5.5V
Voltage on all other pins with respect to VSS (except VDD)............................................................. -0.6V to (VDD + 0.6V)
Total power dissipation (Note) .............................................................................................................................700 mW
Maximum current out of VSS pin ...........................................................................................................................150 mA
Maximum current into VDD pin ..............................................................................................................................125 mA
Input clamp current, IIK (VI < 0 or VI > VDD) 20 mA
Output clamp current, IOK (VO < 0 or VO > VDD) 20 mA
Maximum output current sunk by any output pin ....................................................................................................25 mA
Maximum output current sourced by any output pin ...............................................................................................25 mA
Note:
Power dissipation is calculated as follows:
PDIS = VDD x {IDD - IOH} + {(VDD-VOH) x IOH} + (VOL x IOL)
†
NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions above those
indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability.
2004-2019 Microchip Technology Inc.
DS20001919F-page 21
MCP23008/MCP23S08
2.1
DC Characteristics
DC Characteristics
Param
No.
Operating Conditions (unless otherwise indicated):
1.8V VDD 5.5V at -40C TA +85C (I-Temp)
4.5V VDD 5.5V at -40C TA +125C (E-Temp) (Note 1)
Characteristic
Sym.
Min.
Typ.
Max.
Units
Conditions
D001
Supply Voltage
VDD
1.8
—
5.5
V
D002
VDD Start Voltage to
Ensure Power-on
Reset
VPOR
—
VSS
—
V
D003
VDD Rise Rate to
Ensure Power-on
Reset
SVDD
0.05
—
—
V/ms
D004
Supply Current
IDD
—
—
1
mA
D005
Standby current
IDDS
—
—
1
µA
—
—
2
µA
VSS
—
0.15 VDD
V
VSS
—
0.2 VDD
V
0.25 VDD + 0.8
—
VDD
V
0.8 VDD
—
VDD
V
For entire VDD range.
IIL
—
—
±1
µA
VSS VPIN VDD
Design guidance only.
Not tested.
SCL/SCK = 1 MHz
4.5V - 5.5V @ +125C
(Note 1)
Input Low-Voltage
D030
A0, A1 (TTL buffer)
D031
CS, GPIO, SCL/SCK,
SDA, A2, RESET
(Schmitt Trigger)
VIL
Input High-Voltage
D040
A0, A1
(TTL buffer)
D041
CS, GPIO, SCL/SCK,
SDA, A2, RESET
(Schmitt Trigger)
VIH
Input Leakage Current
D060
I/O PORT pins
Output Leakage Current
D065
I/O PORT pins
ILO
—
—
±1
µA
VSS VPIN VDD
D070
GPIO weak pull-up
current
IPU
40
75
115
µA
VDD = 5V, GP Pins = VSS
–40°C TA +85°C
VOL
—
—
0.6
V
IOL = 8.5 mA, VDD = 4.5V
—
—
0.6
V
IOL = 1.6 mA, VDD = 4.5V
Output Low-Voltage
D080
GPIO
INT
SO, SDA
—
—
0.6
V
IOL = 3.0 mA, VDD = 1.8V
SDA
—
—
0.8
V
IOL = 3.0 mA, VDD = 4.5V
VDD – 0.7
—
—
V
IOH = -3.0 mA, VDD = 4.5V
VDD – 0.7
—
—
Output High-Voltage
D090
GPIO, INT, SO
VOH
IOH = -400 µA, VDD = 1.8V
Capacitive Loading Specs on Output Pins
D101
GPIO, SO, INT
CIO
—
—
50
pF
D102
SDA
CB
—
—
400
pF
Note 1:
This parameter is characterized, not 100% tested.
2004-2019 Microchip Technology Inc.
DS20001919F-page 22
MCP23008/MCP23S08
FIGURE 2-1:
LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS
VDD
Pin
1 k
SCL and
SDA pin
MCP23008
50 pF
135 pF
FIGURE 2-2:
RESET AND DEVICE RESET TIMER TIMING
VDD
RESET
30
32
Internal
RESET
34
Output pin
2004-2019 Microchip Technology Inc.
DS20001919F-page 23
MCP23008/MCP23S08
TABLE 2-1:
DEVICE RESET SPECIFICATIONS
Operating Conditions (unless otherwise indicated):
1.8V VDD 5.5V at -40C TA +85C (I-Temp)
4.5V VDD 5.5V at -40C TA +125C (E-Temp) (Note 1)
AC Characteristics
Param
No.
Characteristic
Sym.
Min.
Typ.(1)
Max.
Units
30
RESET Pulse Width
(Low)
TRSTL
1
—
—
µs
32
Device Active After
RESET high
THLD
—
0
—
µs
34
Output High-Impedance
from RESET Low
TIOZ
—
—
1
µs
Note 1:
Conditions
VDD = 5.0V
This parameter is characterized, not 100% tested.
FIGURE 2-3:
I2C BUS START/STOP BITS TIMING
SCL
93
91
90
92
SDA
STOP
Condition
START
Condition
FIGURE 2-4:
I2C BUS DATA TIMING
103
102
100
101
SCL
90
106
91
107
SDA
In
109
109
92
110
SDA
Out
2004-2019 Microchip Technology Inc.
DS20001919F-page 24
MCP23008/MCP23S08
I2C BUS DATA REQUIREMENTS
2
I C AC Characteristics
Param
No.
100
101
Operating Conditions (unless otherwise indicated):
1.8V VDD 5.5V at -40C TA +85C (I-Temp)
4.5V VDD 5.5V at -40C TA +125C (E-Temp) (Note 1)
RPU (SCL, SDA) = 1 k, CL (SCL, SDA) = 135 pF
Characteristic
Sym.
Min.
Typ.
Max.
Clock High Time:
THIGH
100 kHz mode
4.0
—
—
µs
1.8V – 5.5V (I-Temp)
400 kHz mode
0.6
—
—
µs
2.7V – 5.5V (I-Temp)
1.7 MHz mode
0.12
—
—
µs
4.5V – 5.5V (E-Temp)
100 kHz mode
4.7
—
—
µs
1.8V – 5.5V (I-Temp)
400 kHz mode
1.3
—
—
µs
2.7V – 5.5V (I-Temp)
0.32
—
—
µs
4.5V – 5.5V (E-Temp)
—
—
1000
ns
1.8V – 5.5V (I-Temp)
Clock Low Time:
TLOW
1.7 MHz mode
102
SDA and SCL Rise Time:
100 kHz mode
103
20 + 0.1
1.7 MHz mode
20
100 kHz mode
90
TR
(Note 1)
400 kHz mode
SDA and SCL Fall Time:
TF
(Note 1)
107
ns
2.7V – 5.5V (I-Temp)
ns
4.5V – 5.5V (E-Temp)
1.8V – 5.5V (I-Temp)
—
300
ns
—
300
ns
2.7V – 5.5V (I-Temp)
1.7 MHz mode
20
—
80
ns
4.5V – 5.5V (E-Temp)
100 kHz mode
4.7
—
—
µs
1.8V – 5.5V (I-Temp)
400 kHz mode
0.6
—
—
µs
2.7V – 5.5V (I-Temp)
0.16
—
—
µs
4.5V – 5.5V (E-Temp)
4.0
—
—
µs
1.8V – 5.5V (I-Temp)
START Condition Setup Time:
START Condition Hold Time:
TSU:STA
THD:STA
400 kHz mode
0.6
—
—
µs
2.7V – 5.5V (I-Temp)
1.7 MHz mode
0.16
—
—
µs
4.5V – 5.5V (E-Temp)
Data Input Hold Time:
THD:DAT
100 kHz mode
0
—
3.45
µs
1.8V – 5.5V (I-Temp)
400 kHz mode
0
—
0.9
µs
2.7V – 5.5V (I-Temp)
1.7 MHz mode
0
—
0.15
µs
4.5V – 5.5V (E-Temp)
100 kHz mode
250
—
—
ns
1.8V – 5.5V (I-Temp)
400 kHz mode
100
—
—
ns
2.7V – 5.5V (I-Temp)
0.01
—
—
µs
4.5V – 5.5V (E-Temp)
4.0
—
—
µs
1.8V – 5.5V (I-Temp)
Data Input Setup Time:
STOP Condition Setup Time:
100 kHz mode
Note 1:
2:
300
160
—
TSU:DAT
1.7 MHz mode
92
—
—
20 + 0.1 CB(2)
100 kHz mode
106
CB(2)
400 kHz mode
1.7 MHz mode
91
Units Conditions
TSU:STO
400 kHz mode
0.6
—
—
µs
2.7V – 5.5V (I-Temp)
1.7 MHz mode
0.16
—
—
µs
4.5V – 5.5V (E-Temp)
This parameter is characterized, not 100% tested.
CB is specified to be from 10 to 400 pF.
2004-2019 Microchip Technology Inc.
DS20001919F-page 25
MCP23008/MCP23S08
I2C BUS DATA REQUIREMENTS (CONTINUED)
Operating Conditions (unless otherwise indicated):
1.8V VDD 5.5V at -40C TA +85C (I-Temp)
4.5V VDD 5.5V at -40C TA +125C (E-Temp) (Note 1)
RPU (SCL, SDA) = 1 k, CL (SCL, SDA) = 135 pF
2
I C AC Characteristics
Param
No.
Characteristic
109
Sym.
Min.
Typ.
Max.
100 kHz mode
—
—
3.45
µs
1.8V – 5.5V (I-Temp)
400 kHz mode
—
—
0.9
µs
2.7V – 5.5V (I-Temp)
—
—
0.18
µs
4.5V – 5.5V (E-Temp)
100 kHz mode
4.7
—
—
µs
1.8V – 5.5V (I-Temp)
400 kHz mode
1.3
—
—
µs
2.7V – 5.5V (I-Temp)
N/A
—
N/A
µs
4.5V – 5.5V (E-Temp)
100 kHz and 400 kHz
—
—
400
pF
(Note 1)
1.7 MHz
—
—
100
pF
(Note 1)
100 kHz and 400 kHz
—
—
50
ns
1.7 MHz
—
—
10
ns
Output Valid From Clock:
TAA
1.7 MHz mode
110
Bus Free Time:
TBUF
1.7 MHz mode
Bus Capacitive Loading:
CB
Input Filter Spike
Suppression: (SDA and SCL)
Note 1:
2:
Units Conditions
TSP
Spike suppression off
This parameter is characterized, not 100% tested.
CB is specified to be from 10 to 400 pF.
FIGURE 2-5:
SPI INPUT TIMING
3
CS
11
6
1
Mode 1,1
7
10
2
SCK Mode 0,0
4
5
SI
MSb in
SO
2004-2019 Microchip Technology Inc.
LSb in
high-impedance
DS20001919F-page 26
MCP23008/MCP23S08
FIGURE 2-6:
SPI OUTPUT TIMING
CS
8
SCK
2
9
Mode 1,1
Mode 0,0
12
SO
MSb out
LSb out
don’t care
SI
TABLE 2-2:
SPI INTERFACE AC CHARACTERISTICS
SPI Interface AC Characteristics
Param
No.
14
13
Characteristic
Clock Frequency
Operating Conditions (unless otherwise indicated):
1.8V VDD 5.5V at -40C TA +85C (I-Temp)
4.5V VDD 5.5V at -40C TA +125C (E-Temp) (Note 1)
Sym.
Min.
Typ.
Max.
Units
Conditions
FCLK
—
—
5
MHz
1.8V – 5.5V (I-Temp)
—
—
10
MHz
2.7V – 5.5V (I-Temp)
—
—
10
MHz
4.5V – 5.5V (E-Temp)
1
CS Setup Time
TCSS
50
—
—
ns
2
CS Hold Time
TCSH
100
—
—
ns
1.8V – 5.5V (I-Temp)
50
—
—
ns
2.7V – 5.5V (I-Temp)
50
—
—
ns
4.5V – 5.5V (E-Temp)
100
—
—
ns
1.8V – 5.5V (I-Temp)
50
—
—
ns
2.7V – 5.5V (I-Temp)
50
—
—
ns
4.5V – 5.5V (E-Temp)
20
—
—
ns
1.8V – 5.5V (I-Temp)
3
4
5
CS Disable Time
Data Setup Time
Data Hold Time
TCSD
TSU
THD
10
—
—
ns
2.7V – 5.5V (I-Temp)
10
—
—
ns
4.5V – 5.5V (E-Temp)
20
—
—
ns
1.8V – 5.5V (I-Temp)
10
—
—
ns
2.7V – 5.5V (I-Temp)
10
—
—
ns
4.5V – 5.5V (E-Temp)
6
CLK Rise Time
TR
—
—
2
µs
Note 1
7
CLK Fall Time
TF
—
—
2
µs
Note 1
8
Clock High Time
THI
90
—
—
ns
1.8V – 5.5V (I-Temp)
Note 1:
2:
45
—
—
ns
2.7V – 5.5V (I-Temp)
45
—
—
ns
4.5V – 5.5V (E-Temp)
This parameter is characterized, not 100% tested.
TV = 90 ns (max) when Address Pointer rolls over from address 0x0A to 0x00.
2004-2019 Microchip Technology Inc.
DS20001919F-page 27
MCP23008/MCP23S08
TABLE 2-2:
SPI INTERFACE AC CHARACTERISTICS (CONTINUED)
Operating Conditions (unless otherwise indicated):
1.8V VDD 5.5V at -40C TA +85C (I-Temp)
4.5V VDD 5.5V at -40C TA +125C (E-Temp) (Note 1)
SPI Interface AC Characteristics
Param
No.
9
Characteristic
Clock Low Time
Sym.
Min.
Typ.
Max.
Units
TLO
90
—
—
ns
Conditions
1.8V – 5.5V (I-Temp)
45
—
—
ns
2.7V – 5.5V (I-Temp)
45
—
—
ns
4.5V – 5.5V (E-Temp)
10
Clock Delay Time
TCLD
50
—
—
ns
11
Clock Enable Time
TCLE
50
—
—
ns
TV
—
—
90
ns
1.8V – 5.5V (I-Temp)
—
—
45
ns
2.7V – 5.5V (I-Temp)
—
—
45
ns
4.5V – 5.5V (E-Temp)
(2)
Output Valid from Clock Low
12
13
Output Hold Time
THO
0
—
—
ns
14
Output Disable Time
TDIS
—
—
100
ns
Note 1:
2:
This parameter is characterized, not 100% tested.
TV = 90 ns (max) when Address Pointer rolls over from address 0x0A to 0x00.
FIGURE 2-7:
GPIO AND INT TIMING
SCL/SCK
SDA/SI
In
D1
D0
LSb of data byte zero
during a Write or Read
command, depending
on parameter.
50
GPn
Output
Pin
51
INT
Pin
INT pin active
GPn
Input
Pin
inactive
53
52
Register
Loaded
2004-2019 Microchip Technology Inc.
DS20001919F-page 28
MCP23008/MCP23S08
TABLE 2-3:
GP AND INT PINS
AC Characteristics
Param
No.
Characteristic
Operating Conditions (unless otherwise indicated):
1.8V VDD 5.5V at -40C TA +85C (I-Temp)
4.5V VDD 5.5V at -40C TA +125C (E-Temp) (Note 1)
Sym.
Min.
Typ.
Max.
Units
50
Serial data to output valid
TGPOV
—
—
500
ns
51
Interrupt pin disable time
TINTD
—
—
600
ns
52
GP input change to register
valid
TGPIV
—
—
450
ns
53
IOC event to INT active
TGPINT
—
—
600
ns
Glitch Filter on GP Pins
TGLITCH
—
—
150
ns
Note 1:
Conditions
This parameter is characterized, not 100% tested
2004-2019 Microchip Technology Inc.
DS20001919F-page 29
MCP23008/MCP23S08
3.0
PACKAGING INFORMATION
3.1
Package Marking Information
Example:
18-Lead PDIP (300 mil)
MCP23008-E/P^^
e3
MCP23008-E/P
1912256
18-Lead SOIC (300 mil)
0634256
Example:
MCP23008
E/SO e3
1912256
20-Lead QFN
Example:
23S08
E/ML e3
1912
256
Example:
20-Lead SSOP
MCP23S08
E/SS e3
1912256
Legend: XX...X
Y
YY
WW
NNN
e3
*
Note:
Customer-specific information
Year code (last digit of calendar year)
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code
Pb-free JEDEC designator for Matte Tin (Sn)
This package is Pb-free. The Pb-free JEDEC designator ( e3 )
can be found on the outer packaging for this package.
In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
2004-2019 Microchip Technology Inc.
DS20001919F-page 30
MCP23008/MCP23S08
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DS20001919F-page 35
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