MCP3002T-I/ST

MCP3002 2.7V Dual Channel 10-Bit A/D Converter with SPI Serial Interface Features Description • • • • The MCP3002 is a successive approximation 10-bit analog-to-digital (A/D) converter with on-board sample and hold circuitry. • • • • • • • • 10-bit resolution ±1 LSB maximum DNL ±1 LSB maximum INL Analog inputs programmable as single-ended or pseudo-differential pairs On-chip sample and hold SPI serial interface (modes 0,0 and 1,1) Single supply operation: 2.7V - 5.5V 200 ksps max sampling rate at VDD = 5V 75 ksps max sampling rate at VDD = 2.7V Low power CMOS technology: - 5 nA typical standby current, 2 µA maximum - 550 µA maximum active current at 5V Industrial temperature range: -40°C to +85°C 8-pin MSOP, PDIP, SOIC and TSSOP packages Applications MSOP, PDIP, SOIC, TSSOP Functional Block Diagram VDD VSS Input Channel Mux The MCP3002 is offered in 8-pin MSOP, PDIP, TSSOP and 150 mil SOIC packages. Package Types Sensor Interface Process Control Data Acquisition Battery Operated Systems CH0 CH1 The MCP3002 operates over a broad voltage range, 2.7V to 5.5V. Low-current design permits operation with a typical standby current of 5 nA and a typical active current of 375 µA. CS/SHDN 1 CH0 2 CH1 3 VSS 4 MCP3002 • • • • The MCP3002 is programmable to provide a single pseudo-differential input pair or dual single-ended inputs. Differential Nonlinearity (DNL) and Integral Nonlinearity (INL) are both specified at ±1 LSB. Communication with the device is done using a simple serial interface compatible with the SPI protocol. The device is capable of conversion rates of up to 200 ksps at 5V and 75 ksps at 2.7V. 8 VDD/VREF 7 CLK 6 DOUT 5 DIN DAC Comparator 10-Bit SAR Sample and Hold Control Logic CS/SHDN DIN CLK  2000-2011 Microchip Technology Inc. Shift Register DOUT DS21294E-page 1 MCP3002 1.0 ELECTRICAL CHARACTERISTICS † Notice: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. Absolute Maximum Ratings † VDD ..................................................................................7.0V All Inputs and Outputs w.r.t. VSS ............. -0.6V to VDD + 0.6V Storage Temperature.....................................-65°C to +150°C Ambient temperature with power applied.......-65°C to +150°C ESD Protection On All Pins (HBM)  4 kV ELECTRICAL CHARACTERISTICS All parameters apply at VDD = 5V, TA = -40°C to +85°C, fSAMPLE = 200 ksps and fCLK = 16*fSAMPLE, unless otherwise noted. Typical values apply for VDD = 5V, TA = +25°C, unless otherwise noted. PARAMETER SYM MIN TYP MAX UNITS TCONV — — 10 clock cycles CONDITIONS Conversion Rate: Conversion Time 1.5 Analog Input Sample Time TSAMPLE Throughput Rate FSAMPLE — — Integral Nonlinearity INL — Differential Nonlinearity DNL clock cycles 200 75 ksps ksps ±0.5 ±1 LSB — ±0.25 ±1 LSB Offset Error — — ±1.5 LSB Gain Error — — ±1 LSB VDD = 5V VDD = 2.7V DC Accuracy: Resolution 10 bits No missing codes over temperature Dynamic Performance: THD — -76 — dB VIN = 0.1V to 4.9V@1 kHz Signal to Noise and Distortion (SINAD) SINAD — 61 — dB VIN = 0.1V to 4.9V@1 kHz Spurious Free Dynamic Range SFDR — 78 — dB VIN = 0.1V to 4.9V@1 kHz VSS — VDD V Total Harmonic Distortion Analog Inputs: Input Voltage Range for CH0 or CH1 in Single-ended Mode Input Voltage Range for IN+ in Pseudo-Differential Mode IN+ IN- — VDD+IN- Input Voltage Range for IN- in Pseudo-Differential Mode IN- VSS-100 — VSS+100 mV Leakage Current — 0.001 ±1 µA Switch Resistance RSS — 1K —  See Figure 4-1 Sample Capacitor CSAMPLE — 20 — pF See Figure 4-1 Note 1: This parameter is established by characterization and not 100% tested. 2: The sample cap will eventually lose charge, especially at elevated temperatures, therefore fCLK 10 kHz for temperatures at or above 70°C. DS21294E-page 2  2000-2011 Microchip Technology Inc. MCP3002 ELECTRICAL CHARACTERISTICS (CONTINUED) All parameters apply at VDD = 5V, TA = -40°C to +85°C, fSAMPLE = 200 ksps and fCLK = 16*fSAMPLE, unless otherwise noted. Typical values apply for VDD = 5V, TA = +25°C, unless otherwise noted. PARAMETER SYM MIN TYP MAX UNITS CONDITIONS High Level Input Voltage VIH 0.7 VDD — — V Low Level Input Voltage VIL — — 0.3 VDD V High Level Output Voltage VOH 4.1 — — V IOH = -1 mA, VDD = 4.5V Low Level Output Voltage VOL — — 0.4 V IOL = 1 mA, VDD = 4.5V Input Leakage Current ILI -10 — 10 µA VIN = VSS or VDD Output Leakage Current ILO -10 — 10 µA VOUT = VSS or VDD CIN, COUT — — 10 pF VDD = 5.0V (Note 1) TA = 25°C, f = 1 MHz Clock Frequency fCLK — — — — 3.2 1.2 MHz MHz VDD = 5V (Note 2) VDD = 2.7V (Note 2) Clock High Time tHI 140 — — ns Clock Low Time tLO 140 — — ns tSUCS 100 — — ns Data Input Setup Time tSU 50 — — ns Data Input Hold Time tHD 50 — — ns CLK Fall To Output Data Valid tDO — — — — 125 200 ns ns VDD = 5V, see Figure 1-2 VDD = 2.7V, see Figure 1-2 CLK Fall To Output Enable tEN — — 125 200 ns ns VDD = 5V, see Figure 1-2 VDD = 2.7V, see Figure 1-2 CS Rise To Output Disable tDIS — — 100 ns See Test Circuits, Figure 1-2 Note 1 CS Disable Time tCSH 310 — — ns DOUT Rise Time tR — — 100 ns See Test Circuits, Figure 1-2 Note 1 DOUT Fall Time tF — — 100 ns See Test Circuits, Figure 1-2 Note 1 Operating Voltage VDD 2.7 — 5.5 V Operating Current IDD — — 525 300 650 — µA VDD = 5.0V, DOUT unloaded VDD = 2.7V, DOUT unloaded Standby Current IDDS — 0.005 2 µA CS = VDD = 5.0V Digital Input/Output: Data Coding Format Pin Capacitance (All Inputs/Outputs) Straight Binary Timing Parameters: CS Fall To First Rising CLK Edge Power Requirements: Note 1: This parameter is established by characterization and not 100% tested. 2: The sample cap will eventually lose charge, especially at elevated temperatures, therefore fCLK 10 kHz for temperatures at or above 70°C.  2000-2011 Microchip Technology Inc. DS21294E-page 3 MCP3002 TEMPERATURE CHARACTERISTICS Electrical Specifications: Unless otherwise indicated, VDD = +2.7V to +5.5V, VSS = GND. Parameters Sym Min Typ Max Units Specified Temperature Range TA -40 — +85 °C Operating Temperature Range TA -40 — +85 °C Storage Temperature Range TA -65 — +150 °C Thermal Resistance, 8L-MSOP JA — 211 — °C/W Thermal Resistance, 8L-PDIP JA — 89.5 — °C/W Thermal Resistance, 8L-SOIC JA — 149.5 — °C/W Thermal Resistance, 8L-TSSOP JA — 139 — °C/W Conditions Temperature Ranges Thermal Package Resistances tCSH CS tSUCS tHI tLO CLK tSU DIN tHD MSB IN tEN DOUT FIGURE 1-1: DS21294E-page 4 tR tDO NULL BIT MSB OUT tF tDIS LSB Serial Timing.  2000-2011 Microchip Technology Inc. MCP3002 Load Circuit for tDIS and tEN Load Circuit for tR, tF, tDO Test Point 1.4V VDD 3 kΩ Test Point DOUT 3 kΩ DOUT 30 pF CL = 30 pF VDD /2 tDIS Waveform 2 tEN Waveform tDIS Waveform 1 VSS Voltage Waveforms for tEN Voltage Waveforms for tR, tF VOH VOL DOUT tF tR CS 1 CLK 2 3 4 B9 DOUT tEN Voltage Waveforms for tDIS Voltage Waveforms for tDO CS CLK tDO DOUT VIH DOUT Waveform 1* 90% tDIS DOUT Waveform 2† 10% * Waveform 1 is for an output with internal conditions such that the output is high, unless disabled by the output control. † Waveform 2 is for an output with internal conditions such that the output is low, unless disabled by the output control. FIGURE 1-2: Test Circuits.  2000-2011 Microchip Technology Inc. DS21294E-page 5 MCP3002 2.0 TYPICAL PERFORMANCE CHARACTERISTICS Note: The graphs provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore outside the warranted range. Note: Unless otherwise indicated, VDD = 5V, fSAMPLE = 200 ksps, fCLK = 16* fSAMPLE, TA = +25°C. 0.6 0.6 Positive INL 0.2 0.0 -0.2 Negative INL 0.0 Negative INL -0.4 -0.6 -0.6 0 25 50 75 100 125 150 175 200 225 250 Sample Rate (ksps) FIGURE 2-1: vs. Sample Rate. 1.0 0.8 0.6 0.4 0.2 0.0 -0.2 -0.4 -0.6 -0.8 -1.0 Integral Nonlinearity (INL) 0 VDD = 5V f SAMPLE = 200 ksps 0 128 256 FIGURE 2-2: vs. Code. 384 512 640 Digital Code 768 0.5 0.4 0.3 0.2 0.1 0.0 -0.1 -0.2 -0.3 -0.4 -0.5 -25 FIGURE 2-3: vs. Temperature. DS21294E-page 6 0 25 50 Temperature (°C) 75 100 Integral Nonlinearity (INL) 100 128 256 384 512 640 Digital Code 768 896 1024 FIGURE 2-5: Integral Nonlinearity (INL) vs. Code (VDD = 2.7V). INL (LSB) Negative INL 50 75 Sample Rate (ksps) VDD = 2.7V f SAMPLE = 75 ksps 0 Positive INL -50 1.0 0.8 0.6 0.4 0.2 0.0 -0.2 -0.4 -0.6 -0.8 -1.0 896 1024 Integral Nonlinearity (INL) 25 FIGURE 2-4: Integral Nonlinearity (INL) vs. Sample Rate (VDD = 2.7V). INL (LSB) INL (LSB) Positive INL 0.2 -0.2 -0.4 INL (LSB) VDD = 2.7V 0.4 INL (LSB) INL (LSB) 0.4 0.5 0.4 0.3 0.2 0.1 0.0 -0.1 -0.2 -0.3 -0.4 -0.5 VDD = 2.7V fSAMPLE = 75 ksps Positive INL Negative INL -50 -25 0 25 50 Temperature (°C) 75 100 FIGURE 2-6: Integral Nonlinearity (INL) vs. Temperature (VDD = 2.7V).  2000-2011 Microchip Technology Inc. MCP3002 Note: Unless otherwise indicated, VDD = 5V, fSAMPLE = 200 ksps, fCLK = 16* fSAMPLE, TA = +25°C. 0.8 0.6 Positive INL 0.4 DNL (LSB) INL(LSB) 1.0 0.8 0.6 0.4 0.2 0.0 -0.2 -0.4 -0.6 -0.8 -1.0 Negative INL 3.0 3.5 FIGURE 2-7: vs. VDD. 0.0 -0.2 4.0 VDD (V) 4.5 All points taken at fSAMPLE = 200 ksps except VDD = 2.7V, fSAMPLE = 75 ksps -0.6 -0.8 5.0 2.5 5.5 Integral Nonlinearity (INL) 3.0 4.0 VDD (V) 4.5 5.0 5.5 Differential Nonlinearity 0.6 0.4 VDD = 2.7V 0.4 DNL (LSB) Positive DNL 0.2 0.0 -0.2 Negative DNL Positive DNL 0.2 0.0 -0.2 Negative DNL -0.4 -0.4 -0.6 -0.6 0 25 50 75 100 125 150 175 200 225 0 250 25 FIGURE 2-8: Differential Nonlinearity (DNL) vs. Sample Rate. 1.0 0.8 0.6 0.4 0.2 0.0 -0.2 -0.4 -0.6 -0.8 -1.0 DNL (LSB) 128 256 384 512 640 Digital Code 768 896 1024 FIGURE 2-9: Differential Nonlinearity (DNL) vs. Code (Representative Part).  2000-2011 Microchip Technology Inc. 75 100 FIGURE 2-11: Differential Nonlinearity (DNL) vs. Sample Rate (VDD = 2.7V). VDD = 5V f SAMPLE = 200 ksps 0 50 Sample Rate (ksps) Sample Rate (ksps) DNL (LSB) 3.5 FIGURE 2-10: (DNL) vs. VDD. 0.6 DNL (LSB) Negative DNL -0.4 All points taken at fSAMPLE = 200 ksps except VDD = 2.7V, fSAMPLE = 75 ksps 2.5 Positive DNL 0.2 1.0 0.8 0.6 0.4 0.2 0.0 -0.2 -0.4 -0.6 -0.8 -1.0 VDD = 2.7V fSAMPLE = 75 ksps 0 128 256 384 512 640 Digital Code 768 896 1024 FIGURE 2-12: Differential Nonlinearity (DNL) vs. Code (Representative Part, VDD = 2.7V). DS21294E-page 7 MCP3002 Note: Unless otherwise indicated, VDD = 5V, fSAMPLE = 200 ksps, fCLK = 16* fSAMPLE, TA = +25°C. 0.4 0.4 0.3 0.3 0.2 Positive DNL DNL (LSB) DNL (LSB) 0.2 0.1 0.0 -0.1 Negative DNL -0.2 0.0 -0.1 Negative DNL -0.3 -0.4 -0.4 -50 -25 0 25 50 Temperature (°C) 75 100 FIGURE 2-13: Differential Nonlinearity (DNL) vs. Temperature. -50 1.0 1.0 0.8 0.6 0.4 0.2 0.0 -0.2 -0.4 -0.6 -0.8 -1.0 -25 0 25 50 Temperature (°C) 75 100 FIGURE 2-16: Differential Nonlinearity (DNL) vs. Temperature (VDD = 2.7V). All points taken at fSAMPLE = 200 ksps except VDD = 2.7V, fSAMPLE = 75 ksps Offset Error (LSB) Gain Error (LSB) Positive DNL 0.1 -0.2 -0.3 All points taken at fSAMPLE = 200 ksps except VDD = 2.7V, fSAMPLE = 75 ksps 0.8 0.6 0.4 0.2 0.0 2.5 3.0 FIGURE 2-14: 3.5 4.0 VDD (V) 4.5 5.0 5.5 Gain Error vs. VDD. 2.5 3.0 3.5 FIGURE 2-17: 0.0 4.0 VDD (V) 4.5 5.0 5.5 Offset Error vs. VDD. 0.8 VDD = 2.7V f SAMPLE = 75 ksps -0.1 -0.2 -0.3 VDD = 5V fSAMPLE = 200 ksps -0.4 0.7 Offset Error (LSB) Gain Error (LSB) VDD = 2.7V fSAMPLE = 75 ksps 0.6 0.5 VDD = 2.7V fSAMPLE = 75 ksps 0.4 VDD = 5V fSAMPLE = 200 ksps 0.3 0.2 0.1 -0.5 0.0 -50 -25 FIGURE 2-15: DS21294E-page 8 0 25 50 Temperature (°C) 75 100 Gain Error vs. Temperature. -50 -25 FIGURE 2-18: Temperature. 0 25 50 Temperature (°C) 75 100 Offset Error vs.  2000-2011 Microchip Technology Inc. MCP3002 80 80 70 70 60 60 SINAD (dB) SNR (dB) Note: Unless otherwise indicated, VDD = 5V, fSAMPLE = 200 ksps, fCLK = 16* fSAMPLE, TA = +25°C. 50 VDD = 2.7V fSAMPLE = 75 ksps 40 30 VDD = 5V fSAMPLE = 200 ksps 10 0 10 Input Frequency (kHz) 100 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 1 10 Input Frequency (kHz) 100 FIGURE 2-22: Signal-to-Noise and Distortion (SINAD) vs. Input Frequency. FIGURE 2-19: Signal-to-Noise Ratio (SNR) vs. Input Frequency. 80 70 VDD = 2.7V fSAMPLE = 75 ksps SINAD (dB) THD (dB) 30 10 VDD = 5V fSAMPLE = 200 ksps VDD = 5V fSAMPLE = 200 ksps 60 50 40 30 20 VDD = 2.7V fSAMPLE = 75 ksps 10 0 1 10 Input Frequency (kHz) -40 100 FIGURE 2-20: Total Harmonic Distortion (THD) vs. Input Frequency. -35 -30 -25 -20 -15 -10 Input Signal Level (dB) -5 0 FIGURE 2-23: Signal-to-Noise and Distortion (SINAD) vs. Signal Level. 10.0 10.0 ENOB (rms) 9.9 9.8 9.7 9.6 9.5 VDD = 2.7V fSAMPLE = 75 ksps 40 20 1 ENOB 50 20 0 VDD = 5V fSAMPLE = 200 ksps All points at fSAMPLE = 200 ksps except VDD = 2.7V, fSAMPLE = 75 ksps 9.4 9.5 9.0 VDD = 2.7V fSAMPLE = 75 ksps 8.5 VDD = 5V fSAMPLE = 200 ksps 8.0 2.5 3.0 FIGURE 2-21: (ENOB) vs. VDD. 3.5 4.0 VDD (V) 4.5 5.0 Effective Number of Bits  2000-2011 Microchip Technology Inc. 5.5 1 10 Input Frequency (kHz) 100 FIGURE 2-24: Effective Number of Bits (ENOB) vs. Input Frequency. DS21294E-page 9 MCP3002 Note: Unless otherwise indicated, VDD = 5V, fSAMPLE = 200 ksps, fCLK = 16* fSAMPLE, TA = +25°C. 100 600 90 VDD = 5V 80 fSAMPLE = 200 ksps 500 60 50 VDD = 2.7V 40 fSAMPLE = 75 ksps IDD (µA) SFDR (dB) 70 30 20 400 300 200 100 10 0 1 10 All points at fCLK = 3.2 MHz except at VDD = 2.5V, fCLK = 1.2 MHz 0 100 2.0 2.5 3.0 Input Frequency (kHz) FIGURE 2-25: Spurious Free Dynamic Range (SFDR) vs. Input Frequency. 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 IDD (µA) Amplitude (dB) VDD = 5V fSAMPLE = 200 ksps fINPUT = 10.976 kHz 4096 points 0 20000 40000 60000 Frequency (Hz) 80000 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 600 550 500 450 400 350 300 250 200 150 100 50 0 4.0 4.5 VDD (V) 5.0 5.5 6.0 IDD vs. VDD. VDD = 5V VDD = 2.7V 10 100000 FIGURE 2-26: Frequency Spectrum of 10 kHz input (Representative Part). 100 1000 Clock Frequency (kHz) 10000 IDD vs. Clock Frequency. FIGURE 2-29: 600 VDD = 2.7V fSAMPLE = 75 ksps fINPUT = 1.00708 kHz 4096 points 500 VDD = 5V fCLK = 3.2 MHz IDD (µA) 400 300 VDD = 2.7V fCLK = 1.2 MHz 200 35000 30000 25000 20000 15000 10000 5000 100 0 Amplitude (dB) FIGURE 2-28: 3.5 0 -50 -25 Frequency (Hz) FIGURE 2-27: Frequency Spectrum of 1 kHz input (Representative Part, VDD = 2.7V). DS21294E-page 10 FIGURE 2-30: 0 25 50 Temperature (°C) 75 100 IDD vs. Temperature.  2000-2011 Microchip Technology Inc. MCP3002 70 Analog Input Leakage (nA) Note: Unless otherwise indicated, VDD = 5V, fSAMPLE = 200 ksps, fCLK = 16* fSAMPLE, TA = +25°C. CS = VDD 60 IDDS (pA) 50 40 30 20 10 0 2.5 3.0 3.5 FIGURE 2-31: 100.00 4.0 4.5 VDD (V) 5.0 5.5 6.0 IDDS vs. VDD. 2.0 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0.0 VDD = 5V -50 -25 0 25 50 Temperature (°C) 75 100 FIGURE 2-33: Analog Input leakage current vs. Temperature. VDD = CS = 5V IDDS (nA) 10.00 1.00 0.10 0.01 -50 FIGURE 2-32: -25 0 25 50 Temperature (°C) 75 100 IDDS vs. Temperature.  2000-2011 Microchip Technology Inc. DS21294E-page 11 MCP3002 3.0 PIN DESCRIPTIONS The descriptions of the pins are listed in Table 3-1. Additional descriptions of the device pins follows. TABLE 3-1: PIN FUNCTION TABLE MSOP, PDIP, SOIC, TSSOP Name 1 CS/SHDN 2 CH0 Channel 0 Analog Input 3 CH1 Channel 1 Analog Input 4 VSS Ground 5 DIN Serial Data In 6 DOUT Serial Data Out 7 CLK Serial Clock 8 VDD/VREF 3.1 Function Chip Select/Shutdown Input +2.7V to 5.5V Power Supply and Reference Voltage Input Analog Inputs (CH0/CH1) Analog inputs for channels 0 and 1 respectively. These channels can programmed to be used as two independent channels in Single-Ended mode or as a single pseudo-differential input where one channel is IN+ and one channel is IN-. See Section 5.0 “Serial Communications” for information on programming the channel configuration. 3.2 Chip Select/Shutdown (CS/SHDN) The CS/SHDN pin is used to initiate communication with the device when pulled low and will end a conversion and put the device in low power standby when pulled high. The CS/SHDN pin must be pulled high between conversions. DS21294E-page 12 3.3 Serial Clock (CLK) The SPI clock pin is used to initiate a conversion and to clock out each bit of the conversion as it takes place. See Section 6.2 “Maintaining Minimum Clock Speed” for constraints on clock speed. 3.4 Serial Data Input (DIN) The SPI port serial data input pin is used to clock in input channel configuration data. 3.5 Serial Data Output (DOUT) The SPI serial data output pin is used to shift out the results of the A/D conversion. Data will always change on the falling edge of each clock as the conversion takes place.  2000-2011 Microchip Technology Inc. MCP3002 4.0 DEVICE OPERATION The MCP3002 A/D converter employs a conventional SAR architecture. With this architecture, a sample is acquired on an internal sample/hold capacitor for 1.5 clock cycles starting on the second rising edge of the serial clock after the start bit has been received. Following this sample time, the input switch of the converter opens and the device uses the collected charge on the internal sample and hold capacitor to produce a serial 10-bit digital output code. IN+ input level goes above VDD level. If the voltage at IN+ is equal to or greater than {[VDD + (IN-)] - 1 LSB}, then the output code will be 3FFh. 4.2 Digital Output Code The digital output code produced by an A/D Converter is a function of the input signal and the reference voltage. For the MCP3002, VDD is used as the reference voltage. Conversion rates of 200 ksps are possible on the MCP3002. See Section 6.2 “Maintaining Minimum Clock Speed” for information on minimum clock rates. V REF LSB Size = -------------1024 Communication with the device is done using a 3-wire SPI-compatible interface. As the VDD level is reduced, the LSB size is reduced accordingly. The theoretical digital output code produced by the A/D Converter is shown below. 4.1 Analog Inputs The MCP3002 device offers the choice of using the analog input channels configured as two single-ended inputs that are referenced to VSS or a single pseudodifferential input. The configuration setup is done as part of the serial command before each conversion begins. When used in the pseudo-differential mode, CH0 and CH1 are programmed as the IN+ and IN- inputs as part of the command string transmitted to the device. The IN+ input can range from IN- to the reference voltage, VDD. The IN- input is limited to ±100 mV from the VSS rail. The IN- input can be used to cancel small signal common-mode noise which is present on both the IN+ and IN- inputs. 1024*V IN Digital Output Code = ------------------------V DD Where: VIN = analog input voltage VDD = supply voltage For the A/D converter to meet specification, the charge holding capacitor (CSAMPLE) must be given enough time to acquire a 10-bit accurate voltage level during the 1.5 clock cycle sampling period. The analog input model is shown in Figure 4-1. In this diagram, it is shown that the source impedance (RS) adds to the internal sampling switch (RSS) impedance, directly affecting the time that is required to charge the capacitor, CSAMPLE. Consequently, larger source impedances increase the offset, gain, and integral linearity errors of the conversion. Ideally, the impedance of the signal source should be near zero. This is achievable with an operational amp lifer such as the MCP601 which has a closed loop output impedance of tens of ohms. The adverse affects of higher source impedances are shown in Figure 4-2. When operating in the pseudo-differential mode, if the voltage level of IN+ is equal to or less than IN-, the resultant code will be 000h. If the voltage at IN+ is equal to or greater than {[VDD + (IN-)] - 1 LSB}, then the output code will be 3FFh. If the voltage level at IN- is more than 1 LSB below VSS, then the voltage level at the IN+ input will have to go below VSS to see the 000h output code. Conversely, if IN- is more than 1 LSB above VSS, then the 3FFh code will not be seen unless the  2000-2011 Microchip Technology Inc. DS21294E-page 13 MCP3002 VDD VT = 0.6V CHx RSS Sampling Switch CPIN 7 pF VA VT = 0.6V SS ILEAKAGE ±1 nA RS = 1 kW CSAMPLE = DAC capacitance = 20 pF VSS Legend VA RSS CHx CPIN VT = = = = = = = = = ILEAKAGE SS RS CSAMPLE FIGURE 4-1: signal source source impedance input channel pad input pin capacitance threshold voltage leakage current at the pin due to various junctions sampling switch sampling switch resistor sample/hold capacitance Analog Input Model. Clock Frequency (MHz) 4.0 V DD = 5V 3.5 fSAMPLE = 200 ksps 3.0 2.5 2.0 1.5 VDD = 2.7V fSAMPLE = 75 ksps 1.0 0.5 0.0 100 1000 10000 Input Resistance (Ohms) FIGURE 4-2: Maximum Clock Frequency vs. Input resistance (RS) to maintain less than a 0.1 LSB deviation in INL from nominal conditions. DS21294E-page 14  2000-2011 Microchip Technology Inc. MCP3002 5.0 SERIAL COMMUNICATIONS 5.1 Overview Communication with the MCP3002 is done using a standard SPI-compatible serial interface. Initiating communication with the device is done by bringing the CS line low. See Figure 5-1. If the device was powered up with the CS pin low, it must be brought high and back low to initiate communication. The first clock received with CS low and DIN high will constitute a start bit. The SGL/DIFF bit and the ODD/SIGN bit follow the start bit and are used to select the input channel configuration. The SGL/DIFF is used to select Single-Ended or Pseudo-Differential mode. The ODD/SIGN bit selects which channel is used in Single-Ended mode, and is used to determine polarity in Pseudo-Differential mode. Following the ODD/SIGN bit, the MSBF bit is transmitted to and is used to enable the LSB first format for the device. If the MSBF bit is high, then the data will come from the device in MSB first format and any further clocks with CS low, will cause the device to output zeros. If the MSBF bit is low, then the device will output the converted word LSB first after the word has been transmitted in the MSB first format. Table 5-1 shows the configuration bits for the MCP3002. The device will begin to sample the analog input on the second rising edge of the clock, after the start bit has been received. The sample period will end on the falling edge of the third clock following the start bit. If necessary, it is possible to bring CS low and clock in leading zeros on the DIN line before the start bit. This is often done when dealing with microcontroller-based SPI ports that must send 8 bits at a time. Refer to Section 6.1 “Using the MCP3002 with Microcontroller (MCU) SPI Ports” for more details on using the MCP3002 devices with hardware SPI ports. If it is desired, the CS can be raised to end the conversion period at any time during the transmission. Faster conversion rates can be obtained by using this technique if not all the bits are captured before starting a new cycle. Some system designers use this method by capturing only the highest-order 8 bits and ‘throwing away’ the lower 2 bits. TABLE 5-1: CONFIGURING BITS FOR THE MCP3002 CONFIG BITS CHANNEL SELECTION GND SGL/ DIFF ODD/ SIGN 0 Single-Ended Mode 1 0 + 1 1 PseudoDifferential Mode 0 0 IN+ IN- — 0 1 IN- IN+ — 1 — + — On the falling edge of the clock for the MSBF bit, the device will output a low null bit. The next sequential 10 clocks will output the result of the conversion with MSB first as shown in Figure 5-1. Data is always output from the device on the falling edge of the clock. If all 10 data bits have been transmitted and the device continues to receive clocks while the CS is held low (and the MSBF bit is high), the device will output the conversion result LSB first as shown in Figure 5-2. If more clocks are provided to the device while CS is still low (after the LSB first data has been transmitted), the device will clock out zeros indefinitely.  2000-2011 Microchip Technology Inc. DS21294E-page 15 MCP3002 tCYC tCYC tCSH CS tSUCS HI-Z DOUT MSBF ODD/ SIGN DIN SGL/ DIFF Start CLK ODD/ SIGN Don’t Care Null B9 B8 B7 Bit tSAMPLE B6 B5 B4 B3 B2 B1 B0* tCONV HI-Z tDATA** * After completing the data transfer, if further clocks are applied with CS low, the A/D Converter will output zeros indefinitely. See Figure 5-2 for details on obtaining LSB first data. ** tDATA: during this time, the bias current and the comparator powers down while the reference input becomes a high-impedance node. FIGURE 5-1: Communication with the MCP3002 using MSB first format only. tCYC tCSH CS tSUCS Power Down DOUT HI-Z tSAMPLE MSBF SGL/ DIFF ODD/ SIGN DIN Start CLK Don’t Care HI-Z Null Bit B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 B1 B2 B3 B4 B5 B6 B7* B8 B9 (MSB) tDATA ** tCONV * After completing the data transfer, if further clocks are applied with CS low, the A/D Converter will output zeros indefinitely. ** tDATA: During this time, the bias circuit and the comparator powers down while the reference input becomes a high-impedance node, leaving the CLK running to clock out LSB first data or zeroes. FIGURE 5-2: DS21294E-page 16 Communication with MCP3002 using LSB first format.  2000-2011 Microchip Technology Inc. MCP3002 6.0 APPLICATIONS INFORMATION 6.1 Using the MCP3002 with Microcontroller (MCU) SPI Ports As an example, Figure 6-1 and Figure 6-2 show how the MCP3002 can be interfaced to a MCU with a hardware SPI port. Figure 6-1 depicts the operation shown in SPI Mode 0,0, which requires that the SCLK from the MCU idles in the ‘low’ state, while Figure 6-2 shows the similar case of SPI Mode 1,1 where the clock idles in the ‘high’ state. With most microcontroller SPI ports, it is required to send groups of eight bits. It is also required that the microcontroller SPI port be configured to clock out data on the falling edge of clock and latch data in on the rising edge. Depending on how communication routines are used, it is very possible that the number of clocks required for communication will not be a multiple of eight. Therefore, it may be necessary for the MCU to send more clocks than are actually required. This is usually done by sending ‘leading zeros’ before the start bit, which are ignored by the device. As shown in Figure 6-1, the first byte transmitted to the A/D Converter contains one leading zero before the start bit. Arranging the leading zero this way produces the output 10 bits to fall in positions easily manipulated by the MCU. When the first 8 bits are transmitted to the device, the MSB data bit is clocked out of the A/D converter on the falling edge of clock number 6. After the second eight clocks have been sent to the device, the receive register will contain the lowest-order eight bits of the conversion results. Easier manipulation of the converted data can be obtained by using this method. CS 3 DIN 4 5 FIGURE 6-1: low). 8 9 10 11 12 13 14 15 16 Data is clocked out of A/D Converter on falling edges Don’t Care B8 B7 B6 B5 B4 B3 B2 B1 B0 X X X X X X X Start Bit MCU Transmitted Data (Aligned with falling edge of clock) X = Don’t Care Bits 7 NULL B9 BIT DOUT MCU Received Data (Aligned with rising edge of clock) 6 MSBF 2 Start 1 SGL/ DIFF ODD/ SIGN SCLK MCU latches data from A/D Converter on rising edges of SCLK X X 1 X SGL/ ODD/ MS DIFF SIGN BF X X X X 0 (Null) B9 X X B8 Data stored into MCU receive register after transmission of first 8 bits B7 B6 B5 B4 B3 B2 B1 X B0 Data stored into MCU receive register after transmission of second 8 bits SPI Communication with the MCP3002 using 8-bit segments (Mode 0,0: SCLK idles  2000-2011 Microchip Technology Inc. DS21294E-page 17 MCP3002 CS MCU latches data from A/D Converter on rising edges of SCLK SCLK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 X = Don’t Care Bits FIGURE 6-2: high). 6.2 Don’t Care HI-Z DOUT MCU Received Data (Aligned with rising edge of clock) MSBF Start DIN MCU Transmitted Data (Aligned with falling edge of clock) SGL/ DIFF ODD/ SIGN Data is clocked out of A/D Converter on falling edges NULL B9 BIT B8 B7 B6 B5 B4 B3 B2 B1 B0 X X X X X X X X Start Bit X 1 X SGL/ ODD/ MSBF DIFF SIGN X X X X X 0 X (Null) B9 X B8 Data stored into MCU receive register after transmission of first 8 bits B7 B6 B5 B4 B3 B2 B0 B1 Data stored into MCU receive register after transmission of second 8 bits SPI Communication with the MCP3002 using 8-bit segments (Mode 1,1: SCLK idles Maintaining Minimum Clock Speed When the MCP3002 initiates the sample period, charge is stored on the sample capacitor. When the sample period is complete, the device converts one bit for each clock that is received. It is important for the user to note that a slow clock rate will allow charge to bleed off the sample cap while the conversion is taking place. At 85°C (worst case condition), the part will maintain proper charge on the sample cap for 700 µs at VDD = 2.7V and 1.5 ms at VDD = 5V. This means that at VDD = 2.7V, the time it takes to transmit the 1.5 clocks for the sample period and the 10 clocks for the actual conversion must not exceed 700 µs. Failure to meet this criteria may induce linearity errors into the conversion outside the rated specifications. Low-pass (anti-aliasing) filters can be designed using Microchip’s interactive FilterLab® software. FilterLab will calculate capacitor and resistors values, as well as, determine the number of poles that are required for the application. For more information on filtering signals, see the application note AN699 “Anti-Aliasing Analog Filters for Data Acquisition Systems.” VDD 10 µF VIN R1 C1 R2 + - C2 6.3 Buffering/Filtering the Analog Inputs If the signal source for the A/D Converter is not a low impedance source, it will have to be buffered or inaccurate conversion results may occur. It is also recommended that a filter be used to eliminate any signals that may be aliased back in to the conversion results. This is illustrated in Figure 6-3 below where an op amp is used to drive, filter, and gain the analog input of the MCP3002. This amplifier provides a low impedance output for the converter input and a lowpass filter, which eliminates unwanted high-frequency noise. DS21294E-page 18 1 µF MCP601 R3 R4 IN+ MCP3002 IN- FIGURE 6-3: Typical Anti-Aliasing Filter Circuit (2 pole Active Filter).  2000-2011 Microchip Technology Inc. MCP3002 6.4 Layout Considerations When laying out a printed circuit board for use with analog components, care should be taken to reduce noise wherever possible. A bypass capacitor should always be used with this device and should be placed as close as possible to the device pin. A bypass capacitor value of 1 µF is recommended. Digital and analog traces should be separated as much as possible on the board and no traces should run underneath the device or the bypass capacitor. Extra precautions should be taken to keep traces with highfrequency signals (such as clock lines) as far as possible from analog traces. Use of an analog ground plane is recommended in order to keep the ground potential the same for all devices on the board. Providing VDD connections to devices in a “star” configuration can also reduce noise by eliminating current return paths and associated errors. See Figure 6-4. For more information on layout tips when using A/D converters, refer to AN-688 “Layout Tips for 12-Bit A/D Converter Applications” (DS00688). VDD Connection Device 4 Device 1 Device 3 Device 2 FIGURE 6-4: VDD traces arranged in a ‘Star’ configuration in order to reduce errors caused by current return paths.  2000-2011 Microchip Technology Inc. DS21294E-page 19 MCP3002 7.0 PACKAGING INFORMATION 7.1 Package Marking Information 8-Lead MSOP (3x3 mm) Example 3002I 130256 8-Lead PDIP (300 mil) XXXXXXXX XXXXXNNN YYWW 8-Lead SOIC (3.90 mm) Example 3002 I/P 3 256 1130 Example 3002I SN 3 1130 NNN Legend: XX...X Y YY WW NNN e3 * Note: DS21294E-page 20 Customer-specific information Year code (last digit of calendar year) Year code (last 2 digits of calendar year) Week code (week of January 1 is week ‘01’) Alphanumeric traceability code Pb-free JEDEC designator for Matte Tin (Sn) This package is Pb-free. The Pb-free JEDEC designator ( e3 ) can be found on the outer packaging for this package. In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information.  2000-2011 Microchip Technology Inc. MCP3002 Package Marking Information (Continued) 8-Lead TSSOP (4.4 mm) Example 3002 l130 256 Legend: XX...X Y YY WW NNN e3 * Note: Customer-specific information Year code (last digit of calendar year) Year code (last 2 digits of calendar year) Week code (week of January 1 is week ‘01’) Alphanumeric traceability code Pb-free JEDEC designator for Matte Tin (Sn) This package is Pb-free. The Pb-free JEDEC designator ( e3 ) can be found on the outer packaging for this package. In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information.  2000-2011 Microchip Technology Inc. DS21294E-page 21 MCP3002          3 &' !&" &4# *!(!!& 4%&  &#& &&255***'  '54 D N E E1 NOTE 1 1 2 e b A2 A c φ L L1 A1 6&! '! 7'&! 8"')  %! 77+ + 8 8 89 : ; &  9 ?&  @ =,01 @  ##4 4!!  , ;, , &# %%   @ , 9 B#& +  ##4B#& + -01 9 7&  -01 3 &7& 7 3 & & 7  01  = ; ,+3 3 &  D @ ;D 7# 4!!  ; @ - 7#B#& )  @    !"#$%&" ' ()"&'"!&) &#*&&&#   '! !#+#  &"#' #%!  & "! ! #%!  & "! !! &$#,'' !# - '! #&   +/, 012 0!'!   &$&"! **& "&&  ! +32 % '! ("!"*& "&&  (% % '& "  !!        * 10 DS21294E-page 22  2000-2011 Microchip Technology Inc. MCP3002 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2000-2011 Microchip Technology Inc. DS21294E-page 23 MCP3002       !"## $%    3 &' !&" &4# *!(!!& 4%&  &#& &&255***'  '54 N NOTE 1 E1 1 3 2 D E A2 A L A1 c e eB b1 b 6&! '! 7'&! 8"')  %! 81?+ 8 8 89 : ; &  & &  @ @   ##4 4!!  , - , 0!& &  , @ @  "# &  "# B#& +  - -,  ##4B#& +  , ; 9 7&  -; -=,  & & 7 , - , 7# 4!!  ;  , )  =  )  ;  0 @ @ 6 7#B#& 7 * 7#B#& 9  *E 01 -   !"#$%&" ' ()"&'"!&) &#*&&&#   E%&1 & !& - '! !#+#  &"#' #%!  & "! ! #%!  & "! !! &$#F !#  '! #&   +/, 0120!'!   &$&"! **& "&&  !       * 1;0 DS21294E-page 24  2000-2011 Microchip Technology Inc. MCP3002 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2000-2011 Microchip Technology Inc. DS21294E-page 25 MCP3002 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS21294E-page 26  2000-2011 Microchip Technology Inc. MCP3002     !&'"()#$% *  3 &' !&" &4# *!(!!& 4%&  &#& &&255***'  '54  2000-2011 Microchip Technology Inc. DS21294E-page 27 MCP3002   +, ,   +!-(-$%+   3 &' !&" &4# *!(!!& 4%&  &#& &&255***'  '54 D N E E1 NOTE 1 1 2 b e c A φ A2 A1 L L1 6&! '! 7'&! 8"')  %! 77+ + 8 8 89 : ; &  9 ?&  @ =,01 @  ##4 4!!  ;  , &# %%  , @ ,  9 B#& +  ##4B#& + - =01   ##47&   - - 3 &7& 7 , = , 3 & & 7 , +3 3 &  D @ ;D 7# 4!!   @  7#B#& )  @ -   !"#$%&" ' ()"&'"!&) &#*&&&#   '! !#+#  &"#' #%!  & "! ! #%!  & "! !! &$#,'' !# - '! #&   +/, 012 0!'!   &$&"! **& "&&  ! +32 % '! ("!"*& "&&  (% % '& "  !!        * 1;=0 DS21294E-page 28  2000-2011 Microchip Technology Inc. MCP3002 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2000-2011 Microchip Technology Inc. DS21294E-page 29 MCP3002 APPENDIX A: REVISION HISTORY Revision E (November 2011) Updated Product Identification System Corrected MSOP marking drawings. Updated Package Specification Drawings with new additions. Revision D (October 2008) Updates to packaging outline drawings. Revision C (January 2007) Updates to packaging outline drawings. Revision B (August 2001) Undocumented changes. Revision A (February 2000) Initial release of this document. DS21294E-page 30  2000-2011 Microchip Technology Inc. MCP3002 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. X /XX Device Temperature Range Package Device MCP3002: 10-Bit Serial A/D Converter MCP3002T: 10-Bit Serial A/D Converter (Tape and Reel) (SOIC and TSSOP only Temperature Range I = -40C to Package MS P SN ST = = = = +85C Examples: a) MCP3002-I/P: b) MCP3002-I/SN: c) MCP3002-I/ST: d) MCP3002-I/MS: Industrial Temperature, 8LD PDIP package. Industrial Temperature, 8LD SOIC package. Industrial Temperature, 8LD TSSOP package. Industrial Temperature, 8LD MSOP package. (Industrial) Plastic Micro Small Outline (MSOP), 8-lead Plastic DIP (300 mil Body), 8-lead Plastic SOIC (150 mil Body), 8-lead Plastic TSSOP (4.4 mm), 8-lead  2000-2011 Microchip Technology Inc. DS21294E-page 31 MCP3002 NOTES: DS21294E-page 32  2000-2011 Microchip Technology Inc. Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. • Microchip is willing to work with the customer who is concerned about the integrity of their code. • Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer’s risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights. Trademarks The Microchip name and logo, the Microchip logo, dsPIC, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART, PIC32 logo, rfPIC and UNI/O are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor, MXDEV, MXLAB, SEEVAL and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. Analog-for-the-Digital Age, Application Maestro, chipKIT, chipKIT logo, CodeGuard, dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN, ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial Programming, ICSP, Mindi, MiWi, MPASM, MPLAB Certified logo, MPLIB, MPLINK, mTouch, Omniscient Code Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit, PICtail, REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. © 2000-2011, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. ISBN: 978-1-61341-755-3 Microchip received ISO/TS-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company’s quality system processes and procedures are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified.  2000-2011 Microchip Technology Inc. DS21294E-page 33 Worldwide Sales and Service AMERICAS ASIA/PACIFIC ASIA/PACIFIC EUROPE Corporate Office 2355 West Chandler Blvd. Chandler, AZ 85224-6199 Tel: 480-792-7200 Fax: 480-792-7277 Technical Support: http://www.microchip.com/ support Web Address: www.microchip.com Asia Pacific Office Suites 3707-14, 37th Floor Tower 6, The Gateway Harbour City, Kowloon Hong Kong Tel: 852-2401-1200 Fax: 852-2401-3431 Australia - Sydney Tel: 61-2-9868-6733 Fax: 61-2-9868-6755 India - Bangalore Tel: 91-80-3090-4444 Fax: 91-80-3090-4123 India - New Delhi Tel: 91-11-4160-8631 Fax: 91-11-4160-8632 Austria - Wels Tel: 43-7242-2244-39 Fax: 43-7242-2244-393 Denmark - Copenhagen Tel: 45-4450-2828 Fax: 45-4485-2829 India - Pune Tel: 91-20-2566-1512 Fax: 91-20-2566-1513 France - Paris Tel: 33-1-69-53-63-20 Fax: 33-1-69-30-90-79 Japan - Yokohama Tel: 81-45-471- 6166 Fax: 81-45-471-6122 Germany - Munich Tel: 49-89-627-144-0 Fax: 49-89-627-144-44 Korea - Daegu Tel: 82-53-744-4301 Fax: 82-53-744-4302 Italy - Milan Tel: 39-0331-742611 Fax: 39-0331-466781 Atlanta Duluth, GA Tel: 678-957-9614 Fax: 678-957-1455 Boston Westborough, MA Tel: 774-760-0087 Fax: 774-760-0088 Chicago Itasca, IL Tel: 630-285-0071 Fax: 630-285-0075 Cleveland Independence, OH Tel: 216-447-0464 Fax: 216-447-0643 Dallas Addison, TX Tel: 972-818-7423 Fax: 972-818-2924 Detroit Farmington Hills, MI Tel: 248-538-2250 Fax: 248-538-2260 Indianapolis Noblesville, IN Tel: 317-773-8323 Fax: 317-773-5453 Los Angeles Mission Viejo, CA Tel: 949-462-9523 Fax: 949-462-9608 Santa Clara Santa Clara, CA Tel: 408-961-6444 Fax: 408-961-6445 Toronto Mississauga, Ontario, Canada Tel: 905-673-0699 Fax: 905-673-6509 China - Beijing Tel: 86-10-8569-7000 Fax: 86-10-8528-2104 China - Chengdu Tel: 86-28-8665-5511 Fax: 86-28-8665-7889 Korea - Seoul Tel: 82-2-554-7200 Fax: 82-2-558-5932 or 82-2-558-5934 China - Hangzhou Tel: 86-571-2819-3187 Fax: 86-571-2819-3189 Malaysia - Kuala Lumpur Tel: 60-3-6201-9857 Fax: 60-3-6201-9859 China - Hong Kong SAR Tel: 852-2401-1200 Fax: 852-2401-3431 Malaysia - Penang Tel: 60-4-227-8870 Fax: 60-4-227-4068 China - Nanjing Tel: 86-25-8473-2460 Fax: 86-25-8473-2470 Philippines - Manila Tel: 63-2-634-9065 Fax: 63-2-634-9069 China - Qingdao Tel: 86-532-8502-7355 Fax: 86-532-8502-7205 Singapore Tel: 65-6334-8870 Fax: 65-6334-8850 China - Shanghai Tel: 86-21-5407-5533 Fax: 86-21-5407-5066 Taiwan - Hsin Chu Tel: 886-3-5778-366 Fax: 886-3-5770-955 China - Shenyang Tel: 86-24-2334-2829 Fax: 86-24-2334-2393 Taiwan - Kaohsiung Tel: 886-7-536-4818 Fax: 886-7-330-9305 China - Shenzhen Tel: 86-755-8203-2660 Fax: 86-755-8203-1760 Taiwan - Taipei Tel: 886-2-2500-6610 Fax: 886-2-2508-0102 China - Wuhan Tel: 86-27-5980-5300 Fax: 86-27-5980-5118 Thailand - Bangkok Tel: 66-2-694-1351 Fax: 66-2-694-1350 Spain - Madrid Tel: 34-91-708-08-90 Fax: 34-91-708-08-91 UK - Wokingham Tel: 44-118-921-5869 Fax: 44-118-921-5820 China - Xian Tel: 86-29-8833-7252 Fax: 86-29-8833-7256 China - Xiamen Tel: 86-592-2388138 Fax: 86-592-2388130 China - Zhuhai Tel: 86-756-3210040 Fax: 86-756-3210049 DS21294E-page 34 Netherlands - Drunen Tel: 31-416-690399 Fax: 31-416-690340 China - Chongqing Tel: 86-23-8980-9588 Fax: 86-23-8980-9500 08/02/11  2000-2011 Microchip Technology Inc.