MCP3021A6T-E/OT

MCP3021 Low-Power 10-Bit A/D Converter with I2C Interface Features General Description • • • • • Microchip’s MCP3021 is a successive approximation A/D converter (ADC) with a 10-bit resolution. Available in the SOT-23 package, this device provides one single-ended input with very low-power consumption. Based on an advanced CMOS technology, the MCP3021 provides a low maximum conversion current and standby current of 250 µA and 1 µA, respectively. Low-current consumption, combined with the small SOT-23 package, make this device ideal for battery-powered and remote data acquisition applications. • • • • • • • • 10-bit Resolution ±1 LSB DNL, ±1 LSB INL maximum 250 µA Max Conversion Current 5 nA Typical Standby Current, 1 µA maximum I2C Compatible Serial Interface - 100 kHz I2C Standard mode - 400 kHz I2C Fast mode Up to 8 Devices on a Single 2-wire Bus 22.3 ksps in I2C Fast mode Single-Ended Analog Input Channel On-Chip Sample and Hold On-Chip Conversion Clock Single-Supply Specified Operation: 2.7V to 5.5V Temperature Range: - Extended: -40°C to +125°C Small SOT-23-5 Package Applications • • • • • Data Logging Multi-Zone Monitoring Handheld Portable Applications Battery-Powered Test Equipment Remote or Isolated Data Acquisition Communication to the MCP3021 is performed using a 2-wire I2C compatible interface. Standard (100 kHz) and Fast (400 kHz) I2C modes are available with the device. An on-chip conversion clock enables independent timing for the I2C and conversion clocks. The device is also addressable, allowing up to eight devices on a single 2-wire bus. The MCP3021 runs on a single-supply voltage that operates over a broad range of 2.7V to 5.5V. This device also provides excellent linearity of ±1 LSB differential nonlinearity (DNL) and ±1 LSB integral nonlinearity (INL), maximum. Package Type 5-Pin SOT-23 VSS 2 AIN 3  2003-2017 Microchip Technology Inc. MCP3021 VDD 1 5 SCL 4 SDA DS20001805C-page 1 MCP3021 Functional Block Diagram VDD VSS DAC AIN – Sample and Hold Comparator + 10-bit SAR Clock Control Logic I2C Interface SCL DS20001805C-page 2 SDA  2003-2017 Microchip Technology Inc. MCP3021 1.0 ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings † VDD...........................................................................................................................................................................+7.0V Analog input pin w.r.t. VSS ..................................................................................................................-0.6V to VDD +0.6V SDA and SCL pins w.r.t. VSS ...............................................................................................................-0.6V to VDD +1.0V Storage Temperature ............................................................................................................................. -65°C to +150°C Ambient Temperature with power applied ............................................................................................... -65°C to +125°C Maximum Junction Temperature ........................................................................................................................... +150°C ESD protection on all pins (HBM) .......................................................................................................................... ≥ 4 kV † Notice: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not intended. Exposure to maximum rating conditions for extended periods may affect device reliability. DC ELECTRICAL SPECIFICATIONS Electrical Characteristics: Unless otherwise noted, all parameters apply at VDD = 5.0V, VSS = GND, RPU = 2 k TA = -40°C to +85°C, I2C Fast Mode Timing: fSCL = 400 kHz (Note 3). Parameter Sym. Min. Typ. Max. Units Conditions DC Accuracy Resolution — 10 bits Integral Nonlinearity INL — ±0.25 ±1 LSB Differential Nonlinearity DNL — ±0.25 ±1 LSB No missing codes Offset Error — — ±0.75 ±3 LSB Gain Error — — -1 ±3 LSB THD — -70 — dB VIN = 0.1V to 4.9V @ 1 kHz Signal-to-Noise and Distortion SINAD — 60 — dB VIN = 0.1V to 4.9V @ 1 kHz Spurious Free Dynamic Range SFDR — 74 — dB VIN = 0.1V to 4.9V @ 1 kHz Input Voltage Range — VSS-0.3 — VDD+0.3 V 2.7V  VDD  5.5V Leakage Current — -1 — +1 µA Dynamic Performance Total Harmonic Distortion Analog Input SDA/SCL (open-drain output) Data Coding Format — High-Level Input Voltage VIH 0.7 VDD — — Low-Level Input Voltage VIL — — 0.3 VDD V Low-Level Output Voltage VOL — — 0.4 V IOL = 3 mA, RPU = 1.53 k VHYST — 0.05VDD — V fSCL = 400 kHz only Hysteresis of Schmitt Trigger Inputs Note 1: 2: 3: 4: 5: Straight Binary — V Sample time is the time between conversions after the address byte has been sent to the converter. Refer to Figure 5-6. This parameter is periodically sampled and not 100% tested. RPU = Pull-up resistor on SDA and SCL. SDA and SCL = VSS to VDD at 400 kHz. tACQ and tCONV are dependent on internal oscillator timing. See Figure 5-5 and Figure 5-6 in relation to SCL.  2003-2017 Microchip Technology Inc. DS20001805C-page 3 MCP3021 DC ELECTRICAL SPECIFICATIONS (CONTINUED) Electrical Characteristics: Unless otherwise noted, all parameters apply at VDD = 5.0V, VSS = GND, RPU = 2 k TA = -40°C to +85°C, I2C Fast Mode Timing: fSCL = 400 kHz (Note 3). Parameter Input Leakage Current Output Leakage Current Pin Capacitance (all inputs/outputs) Bus Capacitance Sym. Min. Typ. Max. Units Conditions ILI -1 — +1 µA VIN = VSS to VDD ILO -1 — +1 µA VOUT = VSS to VDD CIN, COUT — — 10 pF TA = 25°C, f = 1 MHz; (Note 2) CB — — 400 pF SDA drive low, 0.4V VDD 2.7 — 5.5 V 250 µA Power Requirements Operating Voltage Conversion Current IDD — 175 Standby Current IDDS — 0.005 1 µA SDA, SCL = VDD Active Bus Current IDDA — — 120 µA Note 4 Conversion Time tCONV — 8.96 — µs Note 5 Analog Input Acquisition Time tACQ — 1.12 — µs Note 5 Sample Rate fSAMP — — 22.3 ksps Conversion Rate Note 1: 2: 3: 4: 5: fSCL = 400 kHz (Note 1) Sample time is the time between conversions after the address byte has been sent to the converter. Refer to Figure 5-6. This parameter is periodically sampled and not 100% tested. RPU = Pull-up resistor on SDA and SCL. SDA and SCL = VSS to VDD at 400 kHz. tACQ and tCONV are dependent on internal oscillator timing. See Figure 5-5 and Figure 5-6 in relation to SCL. TEMPERATURE SPECIFICATIONS Electrical Characteristics: Unless otherwise noted, all parameters apply at VDD = 5.0V, VSS = GND. Parameter Sym. Min. Typ. Max. Units TA -40 — +125 °C Extended Temperature Range TA -40 — +125 °C Storage Temperature Range TA -65 — +150 °C JA — 256 — °C/W Conditions Temperature Ranges Operating Temperature Range Thermal Package Resistances Thermal Resistance, SOT-23 DS20001805C-page 4  2003-2017 Microchip Technology Inc. MCP3021 TIMING SPECIFICATIONS Electrical Characteristics: All parameters apply at VDD = 2.7V - 5.5V, VSS = GND, TA = -40°C to +85°C. Parameter Sym. Min. Typ. Max. Units Clock Frequency fSCL 0 — 100 kHz Clock High Time THIGH 4000 — — ns Clock Low Time TLOW 4700 — — ns SDA and SCL Rise Time TR — — 1000 ns From VIL to VIH (Note 1) SDA and SCL Fall Time TF — — 300 ns From VIL to VIH (Note 1) THD:STA 4000 — — ns Start Condition Setup Time TSU:STA 4700 — — ns Data Input Setup Time TSU:DAT 250 — — ns Stop Condition Setup Time TSU:STO 4000 — — ns Stop Condition Hold Time I2 Conditions C Standard Mode Start Condition Hold Time THD:STD 4000 — — ns Output Valid from Clock TAA — — 3500 ns Bus Free Time TBUF 4700 — — ns Note 2 Input Filter Spike Suppression TSP — — 50 ns SDA and SCL pins (Note 1) I2C Fast Mode Clock Frequency FSCL 0 — 400 kHz Clock High Time THIGH 600 — — ns Clock Low Time TLOW 1300 — — ns SDA and SCL Rise Time TR 20 + 0.1CB — 300 ns From VIL to VIH (Note 1) SDA and SCL Fall Time TF 20 + 0.1CB — 300 ns From VIL to VIH (Note 1) Start Condition Hold Time THD:STA 600 — — ns Start Condition Setup time TSU:STA 600 — — ns Data Input Hold Time THD:DAT 0 — 0.9 ms Data Input Setup Time TSU:DAT 100 — — ns Stop Condition Setup Time TSU:STO 600 — — ns Stop Condition Hold Time THD:STD 600 — — ns Output Valid from Clock TAA — — 900 ns Bus Free Time TBUF 1300 — — ns Note 2 Input Filter Spike Suppression TSP — — 50 ns SDA and SCL pins (Note 1) Note 1: 2: This parameter is periodically sampled and not 100% tested. Time the bus must be free before a new transmission can start. THIGH TF SCL TSP THD:DAT TSU:DAT TSU:STO THD:STA TAA SDA OUT FIGURE 1-1: TR TSU:STA TLOW SDA IN VHYS TBUF Standard and Fast Mode Bus Timing Data.  2003-2017 Microchip Technology Inc. DS20001805C-page 5 MCP3021 2.0 TYPICAL PERFORMANCE CURVES Note: The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore outside the warranted range. Note: Unless otherwise indicated, VDD = 5V, VSS = 0V, I2C Fast Mode Timing (SCL = 400 kHz), Continuous Conversion Mode (fSAMP = 22.3 ksps), TA = +25°C. 0.25 1 0.251 0.20 0.8 0.20 0.8 0.15 0.6 0.15 0.6 Positive INL 0.10 0.4 INL (LSB) INL (LSB) 0.10 0.4 0.005 0.2 0 -0.005 -0.2 Negative INL -0.10 -0.4 0 -0.005 -0.2 -0.10 -0.4 -0.15 -0.6 -0.15 -0.6 -0.20 -0.8 -0.20 -0.8 Negative INL -0.25 -1 -0.25 -1 0 100 FIGURE 2-1: 200 I2C Bus Rate (kHz) 300 0 400 100 INL vs. Clock Rate. 300 400 FIGURE 2-4: (VDD = 2.7V). INL vs. Clock Rate 0.25 1 0.20 0.8 0.20 0.8 Positive INL 0.15 0.6 0.15 0.6 0.10 0.4 0.005 0.2 0.005 0.2 INL (LSB) 0.10 0.4 0 -0.005 -0.2 Positive INL 0 -0.005 -0.2 -0.10 -0.4 Negative INL -0.10 -0.4 -0.15 -0.6 -0.15 -0.6 -0.20 -0.8 -0.20 -0.8 Negative INL -0.25 -1 -0.25 -1 2.5 3 3.5 4 4.5 5 2.5 5.5 3 3.5 VDD (V) 4 4.5 5 5.5 VDD (V) FIGURE 2-2: INL vs. VDD - I2C Standard Mode (fSCL = 100 kHz). FIGURE 2-5: (fSCL = 400 kHz). 0.5 0.5 0.4 0.4 0.3 0.3 0.2 0.2 0.1 0.1 INL (LSB) INL (LSB) 200 2 I C Bus Rate (kHz) 0.25 1 INL (LSB) Positive INL 0.005 0.2 0 -0.1 0 -0.1 -0.2 -0.2 -0.3 -0.3 -0.4 -0.4 -0.5 INL vs. VDD - I2C Fast Mode -0.5 0 256 512 Digital Code FIGURE 2-3: INL vs. Code (Representative Part). DS20001805C-page 6 768 1024 0 256 512 768 1024 Digital Code FIGURE 2-6: INL vs. Code (Representative Part, VDD = 2.7V).  2003-2017 Microchip Technology Inc. MCP3021 Note: Unless otherwise indicated, VDD = 5V, VSS = 0V, I2C Fast Mode Timing (SCL = 400 kHz), Continuous Conversion Mode (fSAMP = 22.3 ksps), TA = +25°C. 0.25 1 0.25 1 0.20 0.8 Positive INL 0.15 0.6 0.10 0.4 0.10 0.4 0.005 0.2 0.005 0.2 INL (LSB) INL (LSB) 0.20 0.8 0.15 0.6 0 -0.005 -0.2 -0.10 -0.4 Positive INL 0 -0.005 -0.2 -0.10 -0.4 Negative INL -0.15 -0.6 -0.15 -0.6 -0.20 -0.8 -0.20 -0.8 -0.25 -1 Negative INL -0.25 -1 -50 -25 0 25 50 75 100 125 -50 -25 0 FIGURE 2-7: INL vs. Temperature. FIGURE 2-10: (VDD = 2.7V). 1 0.25 1 0.25 0.20 0.8 0.8 0.20 0.15 0.6 75 100 125 INL vs. Temperature 0.10 0.4 0.005 0.2 DNL (LSB) DNL (LSB) 50 0.15 0.6 Positive DNL 0.10 0.4 0 -0.005 -0.2 -0.10 -0.4 Negative DNL -0.15 -0.6 -0.20 -0.8 Positive DNL 0.005 0.2 0 -0.005 -0.2 -0.10 -0.4 Negative DNL -0.15 -0.6 -0.20 -0.8 -0.25 -1 -0.25 -1 0 100 200 300 400 0 100 I2C Bus Rate (kHz) FIGURE 2-8: 200 300 400 2 I C Bus Rate (kHz) DNL vs. Clock Rate. FIGURE 2-11: (VDD = 2.7V). 1 0.25 DNL vs. Clock Rate 1 0.25 0.20 0.8 0.20 0.8 0.15 0.6 0.15 0.6 Positive DNL 0.10 0.4 0.10 0.4 0.005 0.2 DNL (LSB) DNL (LSB) 25 Temperature (°C) Temperature (°C) 0 -0.005 -0.2 -0.10 -0.4 Negative DNL Positive DNL 0.005 0.2 0 -0.005 -0.2 -0.10 -0.4 Negative DNL -0.15 -0.6 -0.20 -0.8 -0.15 -0.6 -0.20 -0.8 -0.25 -1 -0.25 -1 2.5 3 3.5 4 4.5 5 5.5 VDD (V) FIGURE 2-9: DNL vs. VDD - I2C Standard Mode (fSCL = 100 kHz).  2003-2017 Microchip Technology Inc. 2.5 3 3.5 4 4.5 5 5.5 VDD (V) FIGURE 2-12: DNL vs. VDD - I2C Fast Mode (fSCL = 400 kHz). DS20001805C-page 7 MCP3021 0.5 0.5 0.4 0.4 0.3 0.3 0.2 0.2 DNL (LSB) DNL (LSB) Note: Unless otherwise indicated, VDD = 5V, VSS = 0V, I2C Fast Mode Timing (SCL = 400 kHz), Continuous Conversion Mode (fSAMP = 22.3 ksps), TA = +25°C. 0.1 0 -0.1 0.1 0 -0.1 -0.2 -0.2 -0.3 -0.3 -0.4 -0.4 -0.5 -0.5 0 256 512 768 1024 0 256 512 Digital Code 0.25 1 1 0.25 0.20 0.8 0.20 0.8 0.15 0.6 0.15 0.6 0.005 0.2 0 -0.005 -0.2 -0.10 -0.4 Negative DNL -0.15 -0.6 Positive DNL 0.10 0.4 Positive DNL DNL (LSB) DNL (LSB) 0.10 0.4 0.005 0.2 0 -0.005 -0.2 -0.10 -0.4 Negative DNL -0.15 -0.6 -0.20 -0.8 -0.20 -0.8 -0.25 -1 -0.25 -1 -50 -25 0 25 50 75 100 125 -50 -25 0 25 Temperature (°C) FIGURE 2-14: DNL vs. Temperature. FIGURE 2-17: (VDD = 2.7V). 0 0.251 -0.025 -0.1 0.225 0.9 -0.05 -0.2 0.20.8 -0.075 -0.3 -0.1 -0.4 -0.125 -0.5 Fast Mode (fSCL=100 kHz) -0.15 -0.6 Standard Mode (fSCL=400 kHz) -0.175 -0.7 -0.2 -0.8 75 100 125 DNL vs. Temperature fSCL = 100 kHz & 400 kHz 0.175 0.7 0.15 0.6 0.125 0.5 0.10.4 0.075 0.3 0.05 0.2 -0.225 -0.9 0.025 0.1 -0.25 -1 2.5 50 Temperature (°C) Offset Error (LSB) Gain Error (LSB) 1024 FIGURE 2-16: DNL vs. Code (Representative Part, VDD = 2.7V). FIGURE 2-13: DNL vs. Code (Representative Part). 0 768 Digital Code 3 3.5 4 4.5 5 5.5 0 0 2.5 3 VDD (V) FIGURE 2-15: DS20001805C-page 8 Gain Error vs. VDD. 3.5 4 4.5 5 5.5 VDD (V) FIGURE 2-18: Offset Error vs. VDD.  2003-2017 Microchip Technology Inc. MCP3021 Note: Unless otherwise indicated, VDD = 5V, VSS = 0V, I2C Fast Mode Timing (SCL = 400 kHz), Continuous Conversion Mode (fSAMP = 22.3 ksps), TA = +25°C. 1.5 0.375 2 0.50 0.45 1.8 0.40 1.6 Offset Error (LSB) Gain Error (LSB) 0.2501 0.5 0.125 0 VDD = 2.7V -0.125 -0.5 -0.250 -1 VDD = 5V -0.375 -1.5 -50 -25 0.35 1.4 0.25 1 0.20 0.8 0.15 0.6 0.10 0.4 0.05 0.2 00 0 25 50 75 100 VDD = 5V 0.30 1.2 125 -50 VDD = 2.7V -25 0 Temperature (°C) FIGURE 2-19: Gain Error vs. Temperature. FIGURE 2-22: Temperature. 84 96 75 100 125 Offset Error vs. 84 96 72 84 60 72 VDD = 5V 60 72 48 60 SINAD (dB) SNR (dB) 50 VDD = 5V 72 84 VDD = 2.7V 36 48 Y 48 60 24 36 12 24 12 24 1 VDD = 2.7V 36 48 24 36 120 120 10 1 10 Input Frequency (kHz) FIGURE 2-20: Input Frequency (kHz) SNR vs. Input Frequency. FIGURE 2-23: -120 84 96 -12 -24 72 84 -24 -36 60 72 -36 -48 SINAD (dB) THD (dB) 25 Temperature (°C) VDD = 5V VDD = 2.7V -48 -60 -60 -72 SINAD vs. Input Frequency. VDD = 5V 48 60 VDD = 2.7V 36 48 24 36 -72 -84 12 24 -84 -96 1 10 120 -40 Input Frequency (kHz) FIGURE 2-21: THD vs. Input Frequency.  2003-2017 Microchip Technology Inc. -30 -20 -10 0 Input Signal Level (dB) FIGURE 2-24: Level. SINAD vs. Input Signal DS20001805C-page 9 MCP3021 Note: Unless otherwise indicated, VDD = 5V, VSS = 0V, I2C Fast Mode Timing (SCL = 400 kHz), Continuous Conversion Mode (fSAMP = 22.3 ksps), TA = +25°C. 10 12 10 12 9.95 11.95 9.5 11.5 9.90 11.9 ENOB (rms) ENOB (rms) 9.85 11.85 9.80 11.8 9.75 11.75 9.70 11.7 9.65 11.65 VDD = 2.7V 9.0 11 8.5 10.5 9.60 11.6 9.55 11.55 9.50 11.5 8.0 10 7.7 9.5 7.0 9 2.5 3 3.5 4 4.5 5 5.5 1 10 VDD (V) FIGURE 2-25: Input Frequency (kHz) FIGURE 2-28: ENOB vs. VDD. 96 84 -10 Amplitude (dB) 72 60 SFDR (dB) ENOB vs. Input Frequency. 10 VDD = 5 V 84 72 VDD = 2.7V 48 60 36 48 24 36 -30 -50 -70 -90 -110 12 24 -130 120 1 0 10 500 1000 FIGURE 2-26: 1500 2000 2500 Frequency (Hz) Input Frequency (kHz) SFDR vs. Input Frequency. 10 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 FIGURE 2-29: Spectrum Using I2C Standard Mode (Representative Part, 1 kHz Input Frequency). 250 200 IDD (µA) Amplitude (dB) VDD = 5V 150 100 50 0 0 2000 4000 6000 8000 10000 2.5 DS20001805C-page 10 3.5 4 4.5 5 5.5 VDD (V) Frequency (Hz) FIGURE 2-27: Spectrum Using I2C Fast Mode (Representative Part, 1 kHz Input Frequency). 3 FIGURE 2-30: IDD (Conversion) vs. VDD.  2003-2017 Microchip Technology Inc. MCP3021 200 100 180 90 160 80 140 70 120 100 IDDA (µA) IDD (µA) Note: Unless otherwise indicated, VDD = 5V, VSS = 0V, I2C Fast Mode Timing (SCL = 400 kHz), Continuous Conversion Mode (fSAMP = 22.3 ksps), TA = +25°C. VDD = 5V 80 60 50 VDD = 5V 40 30 60 VDD = 2.7V 20 40 VDD = 2.7V 20 10 0 0 0 100 200 300 0 400 100 200 I2C Clock Rate (kHz) FIGURE 2-31: Rate. 300 400 I2C Clock Rate (kHz) IDD (Conversion) vs. Clock FIGURE 2-34: Rate. IDDA (Active Bus) vs. Clock 100 250 90 80 200 150 100 VDD = 5V 70 IDDA (µA) IDD (µA) VDD = 5V VDD = 2.7V 60 50 40 30 VDD = 2.7V 20 50 10 0 0 -50 -25 0 25 50 75 100 -50 125 -25 0 25 FIGURE 2-32: Temperature. 50 75 100 125 Temperature (°C) Temperature (°C) IDD (Conversion) vs. FIGURE 2-35: Temperature. IDDA (Active Bus) vs. 60 100 90 50 80 40 60 IDDS (pA) IDDA (µA) 70 50 40 30 20 30 20 10 10 0 0 2.5 3 3.5 4 4.5 5 5.5 2.5 3 VDD (V) FIGURE 2-33: IDDA (Active Bus) vs. VDD.  2003-2017 Microchip Technology Inc. 3.5 4 4.5 5 5.5 VDD (V) FIGURE 2-36: IDDS (Standby) vs. VDD. DS20001805C-page 11 MCP3021 Note: Unless otherwise indicated, VDD = 5V, VSS = 0V, I2C Fast Mode Timing (SCL = 400 kHz), Continuous Conversion Mode (fSAMP = 22.3 ksps), TA = +25°C. 2.1 Test Circuit 1000 100 VDD = 5V IDDS (nA) 10 1 0.1 10 µF 0.01 0.1 µF 2 k 0.001 AIN 0.0001 -50 -25 0 25 50 75 100 125 Temperature (°C) FIGURE 2-37: Temperature. VIN VDD 2 k SDA MCP3021 VSS SCL IDDS (Standby) vs. VCM = 2.5V 2 Analog Input Leakage (nA) 1.8 1.6 FIGURE 2-39: 1.4 Typical Test Configuration. 1.2 1 0.8 0.6 0.4 0.2 0 -50 -25 0 25 50 75 100 125 Temperature (°C) FIGURE 2-38: Temperature. DS20001805C-page 12 Analog Input Leakage vs.  2003-2017 Microchip Technology Inc. MCP3021 3.0 PIN FUNCTIONS Table 3-1 lists the function of the pins. TABLE 3-1: PIN FUNCTION TABLE Name 3.1 Function VDD +2.7V to 5.5V Power Supply VSS Ground AIN Analog Input SDA Serial Data In/Out SCL Serial Clock In VDD and VSS The VDD pin, with respect to VSS, provides power to the device as well as a voltage reference for the conversion process. Refer to Section 6.4 “Device Power and Layout Considerations” for tips on power and grounding. 3.2 Analog Input (AIN) AIN is the input pin to the sample and hold circuitry of the Successive Approximation Register (SAR) converter. Care should be taken in driving this pin. Refer to Section 6.1 “Driving the Analog Input” for more information. For proper conversions, the voltage on this pin can vary from VSS to VDD.  2003-2017 Microchip Technology Inc. 3.3 Serial Data (SDA) SD is a bidirectional pin used to transfer addresses and data into and out of the device. It is an open-drain terminal, therefore, the SDA bus requires a pull-up resistor to VDD (typically 10 k for 100 kHz and 2 k for 400 kHz SCL clock speeds. Refer to Section 6.2 “Connecting to the I2C Bus” for more information. For normal data transfer, SDA is allowed to change only during SCL low. Changes during SCL high are reserved for indicating the Start and Stop conditions. Refer to Section 5.1 “I2C Bus Characteristics” for more information. 3.4 Serial Clock (SCL) SCL is an input pin used to synchronize the data transfer to and from the device on the SDA pin and is an open-drain terminal. Therefore, the SCL bus requires a pull-up resistor to VDD (typically, 10 k for 100 kHz and 2 k for 400 kHz SCL clock speeds. Refer to Section 6.2 “Connecting to the I2C Bus” for more information. For normal data transfer, SDA is allowed to change only during SCL low. Changes during SCL high are reserved for indicating the Start and Stop conditions. Refer to Section 6.1 “Driving the Analog Input” for more information. DS20001805C-page 13 MCP3021 4.0 DEVICE OVERVIEW 4.2 The conversion time is the time required to obtain the digital result once the analog input is disconnected from the holding capacitor. With the MCP3021, the specified conversion time is typically 8.96 µs. This time is dependent on the internal oscillator and independent of SCL. The MCP3021 employs a classic SAR architecture. This architecture uses an internal sample and hold capacitor to store the analog input while the conversion is taking place. At the end of the acquisition time, the input switch of the converter opens and the device uses the collected charge on the internal sample and hold capacitor to produce a serial 10-bit digital output code. The acquisition time and conversion is self-timed using an internal clock. After each conversion, the results are stored in a 10-bit register that can be read at any time. 4.3 Acquisition Time (tACQ) The acquisition time is the amount of time the sample cap array is acquiring charge. Communication with the device is accomplished with a 2-wire I2C interface. Maximum sample rates of 22.3 ksps are possible with the MCP3021 in a continuous conversion mode and an SCL clock rate of 400 kHz. 4.1 Conversion Time (tCONV) The acquisition time is, typically, 1.12 µs. This time is dependent on the internal oscillator and independent of SCL. 4.4 Digital Output Code Sample Rate Sample rate is the inverse of the maximum amount of time that is required from the point of acquisition of the first conversion to the point of acquisition of the second conversion. The digital output code produced by the MCP3021 is a function of the input signal and power supply voltage (VDD). As the VDD level is reduced, the LSB size is reduced accordingly. The theoretical LSB size is shown below. The sample rate can be measured either by single or continuous conversions. A single conversion includes a Start bit, Address byte, two data bytes, and a Stop bit. This sample rate is measured from one Start bit to the next Start bit. EQUATION V DD LSB SIZE = -----------1024 For continuous conversions (requested by the Master by issuing an Acknowledge after a conversion), the maximum sample rate is measured from conversion to conversion, or a total of 18 clocks (two data bytes and two Acknowledge bits). Refer to Section 5.2 “Device Addressing” for more information. VDD = Supply voltage The output code of the MCP3021 is transmitted serially with MSB first, the format of the code is straight binary. Output Code 11 1111 1111 11 1111 1110 (1023) (1022) 00 0000 0011 (3) 00 0000 0010 (2) 00 0000 0001 (1) 00 0000 0000 (0) .5 LSB 1.5 LSB 2.5 LSB FIGURE 4-1: DS20001805C-page 14 AIN VDD-1.5 LSB VDD-2.5 LSB Transfer Function.  2003-2017 Microchip Technology Inc. MCP3021 4.5 Differential Nonlinearity (DNL) In the ideal ADC transfer function, each code has a uniform width. That is, the difference in analog input voltage is constant from one code transition point to the next. Differential nonlinearity (DNL) specifies the deviation of any code in the transfer function from an ideal code width of 1 LSB. The DNL is determined by subtracting the locations of successive code transition points after compensating for any gain and offset errors. A positive DNL implies that a code is longer than the ideal code width, whereas a negative DNL implies that a code is shorter than the ideal width. 4.6 Integral Nonlinearity (INL) Integral nonlinearity (INL) is a result of cumulative DNL errors and specifies how much the overall transfer function deviates from a linear response. The method of measurement used in the MCP3021 ADC to determine INL is the end-point method. 4.7 Offset Error Offset error is defined as a deviation of the code transition points that are present across all output codes. This has the effect of shifting the entire A/D transfer function. The offset error is measured by finding the difference between the actual location of the first code transition and the desired location of the first transition. The ideal location of the first code transition is located at 1/2 LSB above VSS. 4.8 Gain Error Gain error determines the amount of deviation from the ideal slope of the ADC transfer function. Before the gain error is determined, the offset error is measured and subtracted from the conversion result. The gain error can then be determined by finding the location of the last code transition and comparing that location to the ideal location. The ideal location of the last code transition is 1.5 LSBs below full-scale or VDD. 4.9 Conversion Current (IDD) Conversion current is the average amount of current over the time required to perform a 10-bit conversion. 4.10 Active Bus Current (IDDA) The average amount of current over the time required to monitor the I2C bus. Any current that the device consumes while it is not being addressed is referred to as Active Bus current. 4.11 Standby Current (IDDS) The average amount of current required while no conversion is occurring and no data is being output (i.e., SCL and SDA lines are quiet). 4.12 I2C Standard Mode Timing I2C specification where the frequency of SCL is 100 kHz. 4.13 I2C Fast Mode Timing I2C specification where the frequency of SCL is 400 kHz.  2003-2017 Microchip Technology Inc. DS20001805C-page 15 MCP3021 5.0 SERIAL COMMUNICATIONS 5.1 I2C Bus Characteristics The following bus protocol are defined: • Data transfer may be initiated only when the bus is not busy. • During data transfer, the data line must remain stable whenever the clock line is high. Changes in the data line while the clock line is high will be interpreted as a Start or Stop condition. Accordingly, the following bus conditions are defined (refer to Figure 5-1). 5.1.1 BUS NOT BUSY (A) Both data and clock lines remain high. 5.1.2 START DATA TRANSFER (B) A high-to-low transition of the SDA line while the clock (SCL) is high determines a Start condition. All commands must be preceded by a Start condition. 5.1.3 STOP DATA TRANSFER (C) A low-to-high transition of the SDA line while the clock (SCL) is high determines a Stop condition. All operations must be ended with a Stop condition. 5.1.4 DATA VALID (D) The state of the data line represents valid data when after a Start condition, the data line is stable for the duration of the high period of the clock signal. Each data transfer is initiated with a Start condition and terminated with a Stop condition. The number of data bytes being transferred between the Start and Stop conditions is determined by the master device and is unlimited. 5.1.5 ACKNOWLEDGE Each receiving device, when addressed, is obliged to generate an Acknowledge bit after the reception of each byte. The master device must generate an extra clock pulse that is associated with this Acknowledge bit. The device that acknowledges has to pull down the SDA line during the acknowledge clock pulse in such a way that the SDA line is stable low during the high period of the acknowledge-related clock pulse. Setup and hold times must be taken into account. During reads, a master device must signal an end of data to the slave by not generating an Acknowledge bit on the last byte that is clocked out of the slave (NAK). In this case, the slave (MCP3021) releases the bus to allow the master device to generate the Stop condition. The MCP3021 supports a bidirectional 2-wire bus and data transmission protocol. The device that sends data onto the bus is the transmitter and the device receiving data is the receiver. The bus has to be controlled by a master device that generates the serial clock (SCL), controls the bus access and generates the Start and Stop conditions, whereas the MCP3021 works as a slave device. Both master and slave devices can operate as either transmitter or receiver, but the master device determines which mode is activated. The data on the line must be changed during the low period of the clock signal. There is one clock pulse per bit of data. (A) (B) (D) (D) (C) (A) SCL SDA START CONDITION FIGURE 5-1: DS20001805C-page 16 ADDRESS OR DATA ACKNOWLEDGE ALLOWED VALID TO CHANGE STOP CONDITION Data Transfer Sequence on the Serial Bus.  2003-2017 Microchip Technology Inc. MCP3021 Device Addressing 5.3 The address byte is the first byte received following the Start condition from the master device. The first part of the control byte consists of a 4-bit device code, which is set to 1001 for the MCP3021. The device code is followed by three address bits: A2, A1, and A0. The default address bits are 101. Contact the Microchip factory for additional address bit options.The address bits allow up to eight MCP3021 devices on the same bus and are used to determine which device is accessed. The eighth bit of the slave address determines if the master device wants to read conversion data or write to the MCP3021. When set to a 1, a read operation is selected. When set to a 0, a write operation is selected. There are no writable registers on the MCP3021, therefore, this bit must be set to a 1 to initiate a conversion. The MCP3021 is a slave device that is compatible with the 2-wire I2C serial interface protocol. A hardware connection diagram is shown in Figure 6-2. Communication is initiated by the microcontroller (master device), which sends a Start bit followed by the address byte. On completion of the conversion(s) performed by the MCP3021, the microcontroller must send a Stop bit to end the communication. The last bit in the device address byte is the R/W bit. When this bit is a logic 1, a conversion is executed. Setting this bit to logic 0 also results in an Acknowledge (ACK) from the MCP3021, with the device then releasing the bus. This can be used for device polling. Refer to Section 6.3 “Device Polling” for more information. START Executing a Conversion This section describes the details of communicating with the MCP3021 device. Initiating the sample and hold acquisition, reading the conversion data, and executing multiple conversions are discussed. 5.3.1 INITIATING THE SAMPLE AND HOLD The acquisition and conversion of the input signal begins with the falling edge of the R/W bit of the address byte. At this point, the internal clock initiates the sample, hold and conversion cycle, all of which are internal to the ADC. tACQ + tCONV is initiated here Address Byte SCL 1 2 3 4 5 SDA 1 0 0 1 A2 A1 A0 R/W Start bit Device bits FIGURE 5-3: Address Byte. 6 7 8 9 ACK 5.2 Address bits Initiating the Conversion, tACQ + tCONV is initiated here READ/WRITE Lower Data Byte (n) R/W SLAVE ADDRESS A 17 18 19 20 21 22 23 24 25 26 0 0 Device code 1 1 0 1 Address bits(1) Note 1: Contact Microchip for additional address bits. FIGURE 5-2: SDA D6 D5 D4 D3 D2 D1 D0 X X ACK 1 ACK SCL FIGURE 5-4: Initiating the Conversion, Continuous Conversions. Device Addressing.  2003-2017 Microchip Technology Inc. DS20001805C-page 17 MCP3021 The input signal is initially sampled with the first falling edge of the clock following the transmission of a logic-high R/W bit. Additionally, with the rising edge of the SCL, the ADC transmits an Acknowledge bit (ACK = 0). The master must release the data bus during this clock pulse to allow the MCP3021 to pull the line low (refer to Figure 5-3). For consecutive samples, sampling begins on the last bit of the lower data byte. Refer to Figure 5-6 for the timing diagram. 5.3.2 READING THE CONVERSION DATA After the MCP3021 acknowledges the address byte, the device transmits four 0 bits followed by the upper four data bits of the conversion. The master device acknowledges this byte with an ACK = low. With the following six clock pulses, the MCP3021 transmits the lower six data bits from the conversion. The last two bits are “don’t cares”, and do not contain valid data. The master sends an ACK = high, indicating to the MCP3021 that no more data is requested. The master can send a Stop bit to end the transmission. tACQ + tCONV is initiated here 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 SCL S T A R T Address Byte Lower Data Byte S T O P A N D D D D A A A R C D D D D D D / C S 1 0 0 1 A P 2 1 0 W K 0 0 0 0 9 8 7 6 K 5 4 3 2 1 0 X X A K SDA Device bits FIGURE 5-5: 5.3.3 Upper Data Byte Address bits Executing a Conversion. CONSECUTIVE CONVERSIONS For consecutive samples, sampling begins on the falling edge of the last bit of the lower data byte. See Figure 5-6 for timing. tACQ + tCONV is initiated here tACQ + tCONV is initiated here fSAMP = 22.3 ksps (fCLK = 400 kHz) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 SCL S T A R T SDA Address Byte Upper Data Byte (n) Lower Data Byte (n) A R A D D D A C D D D D D D C 0 0 0 0 0 D S 1 0 0 1 A2 A1 A0 / C 7 6 5 4 3 2 1 0 X X 8 9 K K K W Device bits FIGURE 5-6: DS20001805C-page 18 Address bits Continuous Conversion.  2003-2017 Microchip Technology Inc. MCP3021 6.0 APPLICATION INFORMATION 6.1 Driving the Analog Input The MCP3021 has a single-ended analog input (AIN). For proper conversion results, the voltage at the AIN pin must be kept between VSS and VDD. If the converter has no offset error, gain error, INL or DNL errors and the voltage level of AIN is equal to or less than VSS + 1/2 LSB, the resultant code is 000h. Additionally, if the voltage at AIN is equal to or greater than VDD - 1.5 LSB, the output code is 1FFh. The analog input model is shown in Figure 6-1. In this diagram, the source impedance (RSS) adds to the internal sampling switch (RS) impedance, directly affecting the time required to charge the capacitor (CSAMPLE). Consequently, a larger source impedance increases the offset error, gain error and integral linearity errors of the conversion. Ideally, the impedance of the signal source should be near zero. This is achievable with an operational amplifier such as the MCP6022, which has a closed-loop output impedance of tens of ohms. VDD RSS Sampling Switch VT = 0.6V AIN CPIN 7 pF VA VT = 0.6V SS RS = 1 k CSAMPLE = DAC capacitance = 20 pF ILEAKAGE ±1 nA VSS Legend VA RSS AIN CPIN VT ILEAKAGE SS RS CSAMPLE = = = = = = = = = signal source source impedance analog input pad analog input pin capacitance threshold voltage leakage current at the pin due to various junctions sampling switch sampling switch resistor sample/hold capacitance FIGURE 6-1: 6.2 Analog Input Model, AIN. Connecting to the I2C Bus The I2C bus is an open collector bus, requiring pull-up resistors connected to the SDA and SCL lines. This configuration is shown in Figure 6-2. The number of devices connected to the bus is only limited by the maximum bus capacitance of 400 pF. A possible configuration using multiple devices is shown in Figure 6-3. SDA SCL VDD PIC® Microcontroller PIC16F876 Microcontroller RPU RPU MCP3021 SDA AIN SCL 24LC01 EEPROM Analog Input Signal MCP3021 10-bit ADC TC74 Temperature Sensor RPU is typically: 10 k for fSCL = 100 kHz 2 k for fSCL = 400 kHz FIGURE 6-2: Bus. Pull-up Resistors on I2C  2003-2017 Microchip Technology Inc. FIGURE 6-3: Multiple Devices on I2C Bus. DS20001805C-page 19 MCP3021 6.3 Device Polling 6.4.2 In some instances, it may be necessary to test for MCP3021 presence on the I2C bus without performing a conversion as described in Figure 6-4 where the R/W bit in the address byte is set to a zero. The MCP3021 acknowledges by pulling SDA low during the ACK clock and then releases the bus back to the I2C master. A Stop or repeated Start bit can be issued from the master and I2C communication can continue. Address Byte 1 SDA Start bit 2 3 0 0 4 5 6 7 8 1 A2 A1 A0 0 9 ACK 1 SCL Start bit Device bits Address bits R/W MCP3021 response FIGURE 6-4: 6.4 6.4.1 Device Polling. Device Power and Layout Considerations POWERING THE MCP3021 VDD supplies the power to the device and the reference voltage. A bypass capacitor value of 0.1 µF is recommended. Adding a 10 µF capacitor in parallel is recommended to attenuate higher frequency noise that is present in some systems. LAYOUT CONSIDERATIONS When laying out a printed circuit board for use with analog components, care should be taken to reduce noise wherever possible. A bypass capacitor from VDD to ground must be used always with this device and placed as close as possible to the device pin. A bypass capacitor value of 0.1 µF is recommended. Digital and analog traces should be separated as much as possible on the board, with no traces running underneath the device or the bypass capacitor. Extra precautions should be taken to keep traces with highfrequency signals (such as clock lines) as far as possible from analog traces. The MCP3021 must be connected entirely to the analog ground place as well as the analog power trace. The pull-up resistors can be placed close to the microcontroller and tied to the digital power or VCC. Use of an analog ground plane is recommended in order to keep the ground potential the same for all devices on the board. Providing VDD connections to devices in a Star configuration can also reduce noise by eliminating current return paths and associated errors (Figure 6-6). For more information on layout tips when using the MCP3021 or other ADC devices, refer to the Microchip Technology Application Note, “AN688 Layout Tips for 12-Bit A/D Converter Application” (DS00688). VDD Connection VDD VDD 10 µF Device 4 Device 1 0.1 µF VDD AIN MCP3021 SCL SDA RPU RPU Device 3 To Microcontroller Device 2 FIGURE 6-5: Note: Powering the MCP3021. When power-down of the MCP3021 is needed during applications (after power-up), it is highly recommended to bring down the VDD to VSS level. This can guarantee a Full Reset of the device for the next power-up cycle. DS20001805C-page 20 FIGURE 6-6: VDD traces arranged in a Star configuration in order to reduce errors caused by current return paths.  2003-2017 Microchip Technology Inc. MCP3021 6.4.3 USING A REFERENCE FOR SUPPLY The MCP3021 uses VDD as power and also as a reference. In some applications, it may be necessary to use a stable reference to achieve the required accuracy. Figure 6-7 shows an example using the MCP1541 as a 4.096V 2% reference. VDD MCP1541 4.096V Reference VCC 1 µF CL VDD AIN MCP3021 SCL SDA RPU To Microcontroller 0.1 µF FIGURE 6-7: Stable Power and Reference Configuration.  2003-2017 Microchip Technology Inc. DS20001805C-page 21 MCP3021 7.0 PACKAGING INFORMATION 7.1 Package Marking Information 5-Pin SOT-23 3 2 1 2 1 3 4 Part Number 4 5 Address Option SOT-23 MCP3021A0T-E/OT 000 GP MCP3021A1T-E/OT 001 GS MCP3021A2T-E/OT 010 GK MCP3021A3T-E/OT 011 GL MCP3021A4T-E/OT 100 GM MCP3021A5T-E/OT 101 GJ * MCP3021A6T-E/OT 110 GQ MCP3021A7T-E/OT 111 GR * Default option. Contact Microchip Factory for other address options. Legend: XX...X Y YY WW NNN e3 * Note: DS20001805C-page 22 Customer-specific information Year code (last digit of calendar year) Year code (last 2 digits of calendar year) Week code (week of January 1 is week ‘01’) Alphanumeric traceability code Pb-free JEDEC designator for Matte Tin (Sn) This package is Pb-free. The Pb-free JEDEC designator ( e3 ) can be found on the outer packaging for this package. In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information.  2003-2017 Microchip Technology Inc. MCP3021 5-Lead Plastic Small Outline Transistor (OT) (SOT-23) Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging E E1 p B p1 n D 1  c A Units Dimension Limits n Number of Pins p Pitch p1 Outside lead pitch (basic) Overall Height Molded Package Thickness Standoff § Overall Width Molded Package Width Overall Length Foot Length Foot Angle Lead Thickness Lead Width Mold Draft Angle Top Mold Draft Angle Bottom * Controlling Parameter § Significant Characteristic  L  A A2 A1 E E1 D L  c B   MIN .035 .035 .000 .102 .059 .110 .014 0 .004 .014 0 0 A2 A1 INCHES* NOM 5 .038 .075 .046 .043 .003 .110 .064 .116 .018 5 .006 .017 5 5 MAX .057 .051 .006 .118 .069 .122 .022 10 .008 .020 10 10 MILLIMETERS NOM 5 0.95 1.90 0.90 1.18 0.90 1.10 0.00 0.08 2.60 2.80 1.50 1.63 2.80 2.95 0.35 0.45 0 5 0.09 0.15 0.35 0.43 0 5 0 5 MIN MAX 1.45 1.30 0.15 3.00 1.75 3.10 0.55 10 0.20 0.50 10 10 Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side. JEDEC Equivalent: MO-178 Drawing No. C04-091  2003-2017 Microchip Technology Inc. DS20001805C-page 23 MCP3021 NOTES: DS20001805C-page 24  2003-2017 Microchip Technology Inc. MCP3021 APPENDIX A: REVISION HISTORY Revision C (January 2017) The following is the list of modifications: • Added a note to Section 6.4.1 “Powering the MCP3021”. • Updated Figure 6-5. • Fixed Section 7.1 “Package Marking Information” format to reflect the correct package marking as “1 2 3 4” instead of “1 10 10 10”. Revision B (January 2013) • Added a note to each package outline drawing. Revision A (June 2003) • Original Release of this Document.  2003-2017 Microchip Technology Inc. DS20021805C-page 25 MCP3021 NOTES: DS20021805C-page 26  2003-2017 Microchip Technology Inc. MCP3021 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. XX X /XX Device Address Options Temperature Range Package Device: Examples: a) b) MCP3021T: 10-Bit 2-Wire Serial A/D Converter (Tape and Reel) c) d) Temperature Range: Address Options: E = -40C to +125C XX e) A2 A1 A0 A0 = 0 0 0 A1 = 0 0 1 A2 = 0 1 0 A3 = 0 1 1 A4 = 1 0 0 A5 * = 1 0 1 A6 = 1 1 0 A7 = 1 1 1 f) g) h) MCP3021A0T-E/OT: Tape and Reel MCP3021A1T-E/OT: Tape and Reel MCP3021A2T-E/OT: Tape and Reel MCP3021A3T-E/OT: Tape and Reel MCP3021A4T-E/OT: Tape and Reel MCP3021A5T-E/OT: Tape and Reel MCP3021A6T-E/OT: Tape and Reel MCP3021A7T-IE/OT: Tape and Reel Extended, A0 Address, Extended, A1 Address, Extended, A2 Address, Extended, A3 Address, Extended, A4 Address, Extended, A5 Address, Extended, A6 Address, Extended, A7 Address, * Default option. Contact Microchip factory for other address options Package: OT = SOT-23, 5-lead (Tape and Reel)  2003-2017 Microchip Technology Inc. DS20001805C-page 27 MCP3021 NOTES: DS20001805C-page 28  2003-2017 Microchip Technology Inc. Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. • Microchip is willing to work with the customer who is concerned about the integrity of their code. • Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer’s risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights unless otherwise stated. Microchip received ISO/TS-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company’s quality system processes and procedures are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified. QUALITY MANAGEMENT SYSTEM CERTIFIED BY DNV == ISO/TS 16949 ==  2003-2017 Microchip Technology Inc. Trademarks The Microchip name and logo, the Microchip logo, AnyRate, AVR, AVR logo, AVR Freaks, BeaconThings, BitCloud, CryptoMemory, CryptoRF, dsPIC, FlashFlex, flexPWR, Heldo, JukeBlox, KEELOQ, KEELOQ logo, Kleer, LANCheck, LINK MD, maXStylus, maXTouch, MediaLB, megaAVR, MOST, MOST logo, MPLAB, OptoLyzer, PIC, picoPower, PICSTART, PIC32 logo, Prochip Designer, QTouch, RightTouch, SAM-BA, SpyNIC, SST, SST Logo, SuperFlash, tinyAVR, UNI/O, and XMEGA are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. ClockWorks, The Embedded Control Solutions Company, EtherSynch, Hyper Speed Control, HyperLight Load, IntelliMOS, mTouch, Precision Edge, and Quiet-Wire are registered trademarks of Microchip Technology Incorporated in the U.S.A. Adjacent Key Suppression, AKS, Analog-for-the-Digital Age, Any Capacitor, AnyIn, AnyOut, BodyCom, chipKIT, chipKIT logo, CodeGuard, CryptoAuthentication, CryptoCompanion, CryptoController, dsPICDEM, dsPICDEM.net, Dynamic Average Matching, DAM, ECAN, EtherGREEN, In-Circuit Serial Programming, ICSP, Inter-Chip Connectivity, JitterBlocker, KleerNet, KleerNet logo, Mindi, MiWi, motorBench, MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach, Omniscient Code Generation, PICDEM, PICDEM.net, PICkit, PICtail, PureSilicon, QMatrix, RightTouch logo, REAL ICE, Ripple Blocker, SAM-ICE, Serial Quad I/O, SMART-I.S., SQI, SuperSwitcher, SuperSwitcher II, Total Endurance, TSHARC, USBCheck, VariSense, ViewSpan, WiperLock, Wireless DNA, and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. Silicon Storage Technology is a registered trademark of Microchip Technology Inc. in other countries. GestIC is a registered trademark of Microchip Technology Germany II GmbH & Co. KG, a subsidiary of Microchip Technology Inc., in other countries. All other trademarks mentioned herein are property of their respective companies. © 2003-2017, Microchip Technology Incorporated, All Rights Reserved. ISBN: 978-1-5224-1290-8 DS20001805C-page 29 Worldwide Sales and Service AMERICAS ASIA/PACIFIC ASIA/PACIFIC EUROPE Corporate Office 2355 West Chandler Blvd. Chandler, AZ 85224-6199 Tel: 480-792-7200 Fax: 480-792-7277 Technical Support: http://www.microchip.com/ support Web Address: www.microchip.com Asia Pacific Office Suites 3707-14, 37th Floor Tower 6, The Gateway Harbour City, Kowloon China - Xiamen Tel: 86-592-2388138 Fax: 86-592-2388130 Austria - Wels Tel: 43-7242-2244-39 Fax: 43-7242-2244-393 China - Zhuhai Tel: 86-756-3210040 Fax: 86-756-3210049 Denmark - Copenhagen Tel: 45-4450-2828 Fax: 45-4485-2829 India - Bangalore Tel: 91-80-3090-4444 Fax: 91-80-3090-4123 Finland - Espoo Tel: 358-9-4520-820 Atlanta Duluth, GA Tel: 678-957-9614 Fax: 678-957-1455 Hong Kong Tel: 852-2943-5100 Fax: 852-2401-3431 Australia - Sydney Tel: 61-2-9868-6733 Fax: 61-2-9868-6755 China - Beijing Tel: 86-10-8569-7000 Fax: 86-10-8528-2104 Austin, TX Tel: 512-257-3370 China - Chengdu Tel: 86-28-8665-5511 Fax: 86-28-8665-7889 Boston Westborough, MA Tel: 774-760-0087 Fax: 774-760-0088 China - Chongqing Tel: 86-23-8980-9588 Fax: 86-23-8980-9500 Chicago Itasca, IL Tel: 630-285-0071 Fax: 630-285-0075 Dallas Addison, TX Tel: 972-818-7423 Fax: 972-818-2924 Detroit Novi, MI Tel: 248-848-4000 Houston, TX Tel: 281-894-5983 Indianapolis Noblesville, IN Tel: 317-773-8323 Fax: 317-773-5453 Tel: 317-536-2380 Los Angeles Mission Viejo, CA Tel: 949-462-9523 Fax: 949-462-9608 Tel: 951-273-7800 Raleigh, NC Tel: 919-844-7510 New York, NY Tel: 631-435-6000 San Jose, CA Tel: 408-735-9110 Tel: 408-436-4270 Canada - Toronto Tel: 905-695-1980 Fax: 905-695-2078 DS20001805C-page 30 China - Dongguan Tel: 86-769-8702-9880 China - Guangzhou Tel: 86-20-8755-8029 China - Hangzhou Tel: 86-571-8792-8115 Fax: 86-571-8792-8116 China - Hong Kong SAR Tel: 852-2943-5100 Fax: 852-2401-3431 China - Nanjing Tel: 86-25-8473-2460 Fax: 86-25-8473-2470 China - Qingdao Tel: 86-532-8502-7355 Fax: 86-532-8502-7205 China - Shanghai Tel: 86-21-3326-8000 Fax: 86-21-3326-8021 China - Shenyang Tel: 86-24-2334-2829 Fax: 86-24-2334-2393 China - Shenzhen Tel: 86-755-8864-2200 Fax: 86-755-8203-1760 France - Paris Tel: 33-1-69-53-63-20 Fax: 33-1-69-30-90-79 India - New Delhi Tel: 91-11-4160-8631 Fax: 91-11-4160-8632 France - Saint Cloud Tel: 33-1-30-60-70-00 India - Pune Tel: 91-20-3019-1500 Germany - Garching Tel: 49-8931-9700 Germany - Haan Tel: 49-2129-3766400 Japan - Osaka Tel: 81-6-6152-7160 Fax: 81-6-6152-9310 Japan - Tokyo Tel: 81-3-6880- 3770 Fax: 81-3-6880-3771 Germany - Heilbronn Tel: 49-7131-67-3636 Germany - Karlsruhe Tel: 49-721-625370 Korea - Daegu Tel: 82-53-744-4301 Fax: 82-53-744-4302 Germany - Munich Tel: 49-89-627-144-0 Fax: 49-89-627-144-44 Korea - Seoul Tel: 82-2-554-7200 Fax: 82-2-558-5932 or 82-2-558-5934 Germany - Rosenheim Tel: 49-8031-354-560 Malaysia - Kuala Lumpur Tel: 60-3-6201-9857 Fax: 60-3-6201-9859 Malaysia - Penang Tel: 60-4-227-8870 Fax: 60-4-227-4068 Philippines - Manila Tel: 63-2-634-9065 Fax: 63-2-634-9069 Singapore Tel: 65-6334-8870 Fax: 65-6334-8850 Taiwan - Hsin Chu Tel: 886-3-5778-366 Fax: 886-3-5770-955 Taiwan - Kaohsiung Tel: 886-7-213-7830 China - Wuhan Tel: 86-27-5980-5300 Fax: 86-27-5980-5118 Taiwan - Taipei Tel: 886-2-2508-8600 Fax: 886-2-2508-0102 China - Xian Tel: 86-29-8833-7252 Fax: 86-29-8833-7256 Thailand - Bangkok Tel: 66-2-694-1351 Fax: 66-2-694-1350 Israel - Ra’anana Tel: 972-9-744-7705 Italy - Milan Tel: 39-0331-742611 Fax: 39-0331-466781 Italy - Padova Tel: 39-049-7625286 Netherlands - Drunen Tel: 31-416-690399 Fax: 31-416-690340 Norway - Trondheim Tel: 47-7289-7561 Poland - Warsaw Tel: 48-22-3325737 Romania - Bucharest Tel: 40-21-407-87-50 Spain - Madrid Tel: 34-91-708-08-90 Fax: 34-91-708-08-91 Sweden - Gothenberg Tel: 46-31-704-60-40 Sweden - Stockholm Tel: 46-8-5090-4654 UK - Wokingham Tel: 44-118-921-5800 Fax: 44-118-921-5820  2003-2017 Microchip Technology Inc. 11/07/16