MCP3208-BI/SLVAO

MCP3204/3208 2.7V 4-Channel/8-Channel 12-Bit A/D Converters with SPI Serial Interface Features Description • • • • • • The Microchip Technology Inc. MCP3204/3208 devices are successive approximation 12-bit Analogto-Digital (A/D) Converters with on-board sample and hold circuitry. The MCP3204 is programmable to provide two pseudo-differential input pairs or four single-ended inputs. The MCP3208 is programmable to provide four pseudo-differential input pairs or eight single-ended inputs. Differential Nonlinearity (DNL) is specified at ±1 LSB, while Integral Nonlinearity (INL) is offered in ±1 LSB (MCP3204/3208-B) and ±2 LSB (MCP3204/3208-C) versions. • • • • • • • • 12-bit resolution ± 1 LSB max DNL ± 1 LSB max INL (MCP3204/3208-B) ± 2 LSB max INL (MCP3204/3208-C) 4 (MCP3204) or 8 (MCP3208) input channels Analog inputs programmable as single-ended or pseudo-differential pairs On-chip sample and hold SPI serial interface (modes 0,0 and 1,1) Single supply operation: 2.7V - 5.5V 100 ksps max. sampling rate at VDD = 5V 50 ksps max. sampling rate at VDD = 2.7V Low power CMOS technology: - 500 nA typical standby current, 2 µA max. - 400 µA max. active current at 5V Industrial temp range: -40°C to +85°C Available in PDIP, SOIC and TSSOP packages Applications Sensor Interface Process Control Data Acquisition Battery Operated Systems Package Types PDIP, SOIC, TSSOP CH0 CH1 CH2 CH3 NC NC DGND Functional Block Diagram VDD VSS VREF CH0 CH1 1 2 3 4 5 6 7 MCP3204 • • • • Communication with the devices is accomplished using a simple serial interface compatible with the SPI protocol. The devices are capable of conversion rates of up to 100 ksps. The MCP3204/3208 devices operate over a broad voltage range (2.7V - 5.5V). Low current design permits operation with typical standby and active currents of only 500 nA and 320 µA, respectively. The MCP3204 is offered in 14-pin PDIP, 150 mil SOIC and TSSOP packages. The MCP3208 is offered in 16-pin PDIP and SOIC packages. 14 13 12 11 10 9 8 VDD VREF AGND CLK DOUT DIN CS/SHDN PDIP, SOIC Input Channel Mux DAC Comparator 12-Bit SAR Sample and Hold Control Logic CS/SHDN DIN CLK Shift Register 1 2 3 4 5 6 7 8 MCP3208 CH7* CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 16 15 14 13 12 11 10 9 VDD VREF AGND CLK DOUT DIN CS/SHDN DGND DOUT * Note: Channels 5-7 available on MCP3208 Only © 2008 Microchip Technology Inc. DS21298E-page 1 MCP3204/3208 1.0 †Notice: Stresses above those listed under "Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings† VDD...................................................................................7.0V All inputs and outputs w.r.t. VSS ............... -0.6V to VDD +0.6V Storage temperature .....................................-65°C to +150°C Ambient temp. with power applied ................-65°C to +125°C Soldering temperature of leads (10 seconds) ............. +300°C ESD protection on all pins.............................................> 4 kV ELECTRICAL SPECIFICATIONS Electrical Characteristics: Unless otherwise noted, all parameters apply at VDD = 5V, VSS = 0V, VREF = 5V, TA = -40°C to +85°C,fSAMPLE = 100 ksps and fCLK = 20*fSAMPLE Parameters Sym Min Typ Max Units tCONV — — 12 clock cycles Conditions Conversion Rate Conversion Time Analog Input Sample Time tSAMPLE 1.5 Throughput Rate fSAMPLE — — — — Integral Nonlinearity INL — — Differential Nonlinearity DNL clock cycles 100 50 ksps ksps VDD = VREF = 5V VDD = VREF = 2.7V ±0.75 ±1.0 ±1 ±2 LSB MCP3204/3208-B MCP3204/3208-C — ±0.5 ±1 LSB No missing codes over-temperature Offset Error — ±1.25 ±3 LSB Gain Error — ±1.25 ±5 LSB Total Harmonic Distortion — -82 — dB VIN = 0.1V to 4.9V@1 kHz Signal to Noise and Distortion (SINAD) — 72 — dB VIN = 0.1V to 4.9V@1 kHz Spurious Free Dynamic Range — 86 — dB VIN = 0.1V to 4.9V@1 kHz Voltage Range 0.25 — VDD V Note 2 Current Drain — — 100 0.001 150 3.0 µA µA CS = VDD = 5V VSS — VREF V DC Accuracy Resolution 12 bits Dynamic Performance Reference Input Analog Inputs Input Voltage Range for CH0CH7 in Single-Ended Mode Input Voltage Range for IN+ in IN— VREF+INpseudo-differential Mode Note 1: This parameter is established by characterization and not 100% tested. 2: See graphs that relate linearity performance to VREF levels. 3: Because the sample cap will eventually lose charge, effective clock rates below 10 kHz can affect linearity performance, particularly at elevated temperatures. See Section 6.2 “Maintaining Minimum Clock Speed”, “Maintaining Minimum Clock Speed”, for more information. DS21298E-page 2 © 2008 Microchip Technology Inc. MCP3204/3208 ELECTRICAL SPECIFICATIONS (CONTINUED) Electrical Characteristics: Unless otherwise noted, all parameters apply at VDD = 5V, VSS = 0V, VREF = 5V, TA = -40°C to +85°C,fSAMPLE = 100 ksps and fCLK = 20*fSAMPLE Parameters Sym Min Typ Max Units VSS-100 — VSS+100 mV Leakage Current — 0.001 ±1 µA Switch Resistance — 1000 — Ω See Figure 4-1 Sample Capacitor — 20 — pF See Figure 4-1 — — V Input Voltage Range for IN- in pseudo-differential Mode Conditions Digital Input/Output Data Coding Format Straight Binary High Level Input Voltage VIH Low Level Input Voltage VIL — — 0.3 VDD V High Level Output Voltage VOH 4.1 — — V Low Level Output Voltage 0.7 VDD IOH = -1 mA, VDD = 4.5V VOL — — 0.4 V IOL = 1 mA, VDD = 4.5V Input Leakage Current ILI -10 — 10 µA VIN = VSS or VDD Output Leakage Current ILO -10 — 10 µA VOUT = VSS or VDD CIN,COUT — — 10 pF VDD = 5.0V (Note 1) TA = 25°C, f = 1 MHz Clock Frequency fCLK — — — — 2.0 1.0 MHz MHz VDD = 5V (Note 3) VDD = 2.7V (Note 3) Clock High Time tHI 250 — — ns Pin Capacitance (All Inputs/Outputs) Timing Parameters Clock Low Time tLO 250 — — ns tSUCS 100 — — ns tSU 50 — — ns Data Input Hold Time tHD 50 — — ns CLK Fall To Output Data Valid tDO — — 200 ns See Figures 1-2 and 1-3 CLK Fall To Output Enable tEN — — 200 ns See Figures 1-2 and 1-3 CS Rise To Output Disable tDIS — — 100 ns See Figures 1-2 and 1-3 CS Disable Time CS Fall To First Rising CLK Edge Data Input Setup Time tCSH 500 — — ns DOUT Rise Time tR — — 100 ns See Figures 1-2 and 1-3 (Note 1) DOUT Fall Time tF — — 100 ns See Figures 1-2 and 1-3 (Note 1) Operating Voltage VDD 2.7 — 5.5 V Operating Current IDD — — 320 225 400 — µA VDD=VREF = 5V, DOUT unloaded VDD=VREF = 2.7V, DOUT unloaded Standby Current IDDS — 0.5 2.0 µA CS = VDD = 5.0V Power Requirements Note 1: 2: 3: This parameter is established by characterization and not 100% tested. See graphs that relate linearity performance to VREF levels. Because the sample cap will eventually lose charge, effective clock rates below 10 kHz can affect linearity performance, particularly at elevated temperatures. See Section 6.2 “Maintaining Minimum Clock Speed”, “Maintaining Minimum Clock Speed”, for more information. © 2008 Microchip Technology Inc. DS21298E-page 3 MCP3204/3208 TEMPERATURE CHARACTERISTICS Electrical Specifications: Unless otherwise indicated, VDD = 5V, VSS = 0V, VREF = 5V Parameters Sym Min Typ Max Units Specified Temperature Range TA -40 — +125 °C Operating Temperature Range TA -40 — +125 °C Storage Temperature Range TA -65 — +150 °C Thermal Resistance, 14L-PDIP θJA — 70 — °C/W Thermal Resistance, 14L-SOIC θJA — 95.3 — °C/W Thermal Resistance, 14L-TSSOP θJA — 100 — °C/W Thermal Resistance, 16L-PDIP θJA — 70 — °C/W Thermal Resistance, 16L-SOIC θJA — 86.1 — °C/W Conditions Temperature Ranges Thermal Package Resistances tCSH CS tSUCS tHI tLO CLK tSU DIN tHD MSB IN tEN DOUT FIGURE 1-1: DS21298E-page 4 tR tDO Null Bit MSB OUT tF tDIS LSB Serial Interface Timing. © 2008 Microchip Technology Inc. MCP3204/3208 Test Point 1.4V VDD 3 kΩ Test Point 3 kΩ tDIS Waveform 2 VDD/2 tEN Waveform DOUT DOUT 100 pF CL = 100 pF tDIS Waveform 1 VSS Voltage Waveforms for tR, tF Voltage Waveforms for tEN VOH VOL DOUT CS tF tR 1 CLK 2 3 4 Voltage Waveforms for tDO B11 DOUT CLK tEN tDO DOUT Voltage Waveforms for tDIS CS FIGURE 1-2: Load Circuit for tR, tF, tDO. VIH DOUT Waveform 1* 90% TDIS DOUT 10% Waveform 2† * Waveform 1 is for an output with internal conditions such that the output is high, unless disabled by the output control. † Waveform 2 is for an output with internal conditions such that the output is low, unless disabled by the output control. FIGURE 1-3: © 2008 Microchip Technology Inc. Load circuit for tDIS and tEN. DS21298E-page 5 MCP3204/3208 NOTES: DS21298E-page 6 © 2008 Microchip Technology Inc. MCP3204/3208 2.0 TYPICAL PERFORMANCE CHARACTERISTICS The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore outside the warranted range. Note: Note: Unless otherwise indicated, VDD = VREF = 5V, VSS = 0V, fSAMPLE = 100 ksps, fCLK = 20* fSAMPLE, TA = +25°C. 1.0 2.0 0.8 Positive INL VDD = VREF = 2.7 V 1.5 0.6 1.0 INL (LSB) INL (LSB) 0.4 0.2 0.0 -0.2 Positive INL 0.5 0.0 -0.5 -0.4 Negative INL Negative INL -1.0 -0.6 -1.5 -0.8 -2.0 -1.0 0 25 50 75 100 125 0 150 10 20 FIGURE 2-1: vs. Sample Rate. 30 40 50 60 70 80 Sample Rate (ksps) Sample Rate (ksps) Integral Nonlinearity (INL) FIGURE 2-4: Integral Nonlinearity (INL) vs. Sample Rate (VDD = 2.7V). 2.5 2.0 2.0 1.5 Positive INL 1.0 1.0 Positive INL INL (LSB) INL (LSB) 1.5 0.5 0.0 -0.5 -1.0 Negative INL 0.5 0.0 -0.5 -1.0 -1.5 Negative INL -1.5 -2.0 0 1 2 3 4 5 -2.0 0.0 0.5 1.0 1.5 VREF (V) Integral Nonlinearity (INL) 2.5 3.0 FIGURE 2-5: Integral Nonlinearity (INL) vs. VREF (VDD = 2.7V). 1.0 1.0 0.8 0.8 0.6 0.6 0.4 0.4 INL (LSB) INL (LSB) FIGURE 2-2: vs. VREF . 2.0 VREF (V) 0.2 0.0 -0.2 VDD = VREF = 2.7 V FSAMPLE = 50 ksps 0.2 0.0 -0.2 -0.4 -0.4 -0.6 -0.6 -0.8 -0.8 -1.0 -1.0 0 512 1024 1536 2048 2560 3072 3584 4096 Digital Code FIGURE 2-3: Integral Nonlinearity (INL) vs. Code (Representative Part). © 2008 Microchip Technology Inc. 0 512 1024 1536 2048 2560 3072 3584 4096 Digital Code FIGURE 2-6: Integral Nonlinearity (INL) vs. Code (Representative Part, VDD = 2.7V). DS21298E-page 7 MCP3204/3208 Note: Unless otherwise indicated, VDD = VREF = 5 V, VSS = 0 V, fSAMPLE = 100 ksps, fCLK = 20* fSAMPLE, TA = +25°C. 1.0 1.0 0.6 0.6 0.4 0.4 0.2 0.0 Negative INL -0.2 VDD = VREF = 2.7 V FSAMPLE = 50 ksps 0.8 Positive INL INL (LSB) INL (LSB) 0.8 Positive INL 0.2 0.0 -0.2 -0.4 -0.4 -0.6 -0.6 -0.8 -0.8 Negative INL -1.0 -1.0 -50 -25 0 25 50 75 -50 100 -25 0 Temperature (°C) FIGURE 2-7: vs. Temperature. Integral Nonlinearity (INL) 1.0 2.0 0.8 1.5 75 100 VDD = VREF = 2.7 V 1.0 0.4 DNL (LSB) DNL (LSB) 50 FIGURE 2-10: Integral Nonlinearity (INL) vs. Temperature (VDD = 2.7V). 0.6 0.2 Positive DNL 0.0 -0.2 -0.4 0.5 Positive DNL 0.0 -0.5 Negative DNL -1.0 Negative DNL -0.6 -1.5 -0.8 -1.0 -2.0 0 25 50 75 100 125 150 0 10 Sample Rate (ksps) 2.0 2.0 DNL (LSB) 3.0 Positive DNL 0.0 Negative DNL -1.0 30 40 50 60 70 80 FIGURE 2-11: Differential Nonlinearity (DNL) vs. Sample Rate (VDD = 2.7V). 3.0 1.0 20 Sample Rate (ksps) FIGURE 2-8: Differential Nonlinearity (DNL) vs. Sample Rate. DNL (LSB) 25 Temperature (°C) -2.0 VDD = VREF = 2.7 V FSAMPLE = 50 ksps Positive DNL 1.0 0.0 Negative DNL -1.0 -2.0 -3.0 -3.0 0 1 2 3 4 VREF (V) FIGURE 2-9: (DNL) vs. VREF . DS21298E-page 8 Differential Nonlinearity 5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 VREF (V) FIGURE 2-12: Differential Nonlinearity (DNL) vs. VREF (VDD = 2.7V). © 2008 Microchip Technology Inc. MCP3204/3208 1.0 1.0 0.8 0.8 0.6 0.6 0.4 0.4 DNL (LSB) DNL (LSB) Note: Unless otherwise indicated, VDD = VREF = 5V, VSS = 0V, fSAMPLE = 100 ksps, fCLK = 20* fSAMPLE, TA = +25°C. 0.2 0.0 -0.2 0.2 0.0 -0.2 -0.4 -0.4 -0.6 -0.6 -0.8 -0.8 -1.0 VDD = VREF = 2.7 V FSAMPLE = 50 ksps -1.0 0 512 1024 1536 2048 2560 3072 3584 4096 0 512 1024 1536 Digital Code 1.0 1.0 0.8 0.8 0.6 DNL (LSB) DNL (LSB) 0.4 0.2 0.0 -0.2 Negative DNL -0.6 3584 4096 Positive DNL 0.2 0.0 -0.2 -0.4 Negative DNL -0.6 -0.8 -0.8 -1.0 -1.0 -50 -25 0 25 50 75 100 -50 -25 Temperature (°C) 0 25 50 75 100 Temperature (°C) FIGURE 2-14: Differential Nonlinearity (DNL) vs. Temperature. FIGURE 2-17: Differential Nonlinearity (DNL) vs. Temperature (VDD = 2.7V). 4 20 3 18 VDD = VREF = 2.7 V FSAMPLE = 50 ksps 2 Offset Error (LSB) Gain Error (LSB) 3072 VDD = VREF = 2.7 V FSAMPLE = 50 ksps 0.6 Positive DNL -0.4 2560 FIGURE 2-16: Differential Nonlinearity (DNL) vs. Code (Representative Part, VDD = 2.7V). FIGURE 2-13: Differential Nonlinearity (DNL) vs. Code (Representative Part). 0.4 2048 Digital Code 1 0 -1 VDD = VREF = 5 V FSAMPLE = 100 ksps -2 -3 16 VDD = VREF = 5V FSAMPLE = 100 ksps 14 12 10 8 VDD = VREF = 2.7V FSAMPLE = 50 ksps 6 4 2 -4 0 0 1 2 3 4 5 0 1 VREF (V) FIGURE 2-15: Gain Error vs. VREF . © 2008 Microchip Technology Inc. 2 3 4 5 VREF (V) FIGURE 2-18: Offset Error vs. VREF . DS21298E-page 9 MCP3204/3208 Note: Unless otherwise indicated, VDD = VREF = 5V, VSS = 0V, fSAMPLE = 100 ksps, fCLK = 20* fSAMPLE, TA = +25°C. 2.0 0.2 VDD = VREF = 2.7 V FSAMPLE = 50 ksps -0.2 1.8 Offset Error (LSB) Gain Error (LSB) 0.0 -0.4 -0.6 -0.8 -1.0 VDD = VREF = 5 V FSAMPLE = 100 ksps -1.2 -1.4 VDD = VREF = 5 V FSAMPLE = 100 ksps 1.6 1.4 1.2 1.0 VDD = VREF = 2.7 V FSAMPLE = 50 ksps 0.8 0.6 0.4 0.2 -1.6 0.0 -1.8 -50 -25 0 25 50 75 -50 100 -25 0 Temperature (°C) FIGURE 2-19: Gain Error vs. Temperature. 100 FIGURE 2-22: Temperature. 80 75 100 Offset Error vs. VDD = VREF = 5 V FSAMPLE = 100 ksps 90 80 SFDR (dB) 70 SNR (dB) 50 100 VDD = VREF = 5 V FSAMPLE = 100 ksps 90 60 50 40 VDD = VREF = 2.7V FSAMPLE = 50 ksps 30 70 60 VDD = VREF = 2.7 V FSAMPLE = 50 ksps 50 40 30 20 20 10 10 0 0 1 10 100 1 10 Input Frequency (kHz) FIGURE 2-20: Input Frequency. 100 Input Frequency (kHz) Signal-to-Noise (SNR) vs. FIGURE 2-23: Signal-to-Noise and Distortion (SINAD) vs. Input Frequency. 0 80 -10 VDD = VREF = 5 V FSAMPLE = 100 ksps 70 -20 -30 60 VDD = VREF = 2.7V FSAMPLE = 50 ksps -40 SINAD (dB) THD (dB) 25 Temperature (°C) -50 -60 -70 50 VDD = VREF = 2.7 V FSAMPLE = 50 ksps 40 30 20 -80 VDD = VREF = 5V FSAMPLE = 100 ksps -90 10 0 -100 1 10 100 Input Frequency (kHz) FIGURE 2-21: Total Harmonic Distortion (THD) vs. Input Frequency. DS21298E-page 10 -40 -35 -30 -25 -20 -15 -10 -5 0 Input Signal Level (dB) FIGURE 2-24: Signal-to-Noise and Distortion (SINAD) vs. Input Signal Level. © 2008 Microchip Technology Inc. MCP3204/3208 12.0 12.00 11.75 11.50 11.25 11.00 10.75 10.50 10.25 10.00 9.75 9.50 9.25 9.00 11.5 11.0 ENOB (rms) ENOB (rms) Note: Unless otherwise indicated, VDD = VREF = 5V, VSS = 0V, fSAMPLE = 100 ksps, fCLK = 20* fSAMPLE, TA = +25°C. VDD = VREF = 5 V FSAMPLE =100 ksps VDD = VREF = 2.7 V FSAMPLE = 50 ksps 10.5 VDD = VREF = 5 V FSAMPLE = 100 ksps 10.0 9.5 VDD = VREF = 2.7 V FSAMPLE = 50 ksps 9.0 8.5 8.0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 1 VREF (V) FIGURE 2-25: (ENOB) vs. VREF. Effective Number of Bits 100 FIGURE 2-28: Effective Number of Bits (ENOB) vs. Input Frequency. 0 Power Supply Rejection (dB) 100 VDD = VREF = 5 V FSAMPLE = 100 ksps 90 80 SFDR (dB) 10 Input Frequency (kHz) 70 60 VDD = VREF = 2.7 V FSAMPLE = 50 ksps 50 40 30 20 10 -10 -20 -30 -40 -50 -60 -70 -80 0 1 10 1 100 10 Input Frequency (kHz) Amplitude (dB) VDD = VREF = 5 V FSAMPLE = 100 ksps FINPUT = 9.985 kHz 4096 points 0 10000 20000 30000 40000 50000 Frequency (Hz) FIGURE 2-27: Frequency Spectrum of 10 kHz input (Representative Part). © 2008 Microchip Technology Inc. 1000 10000 FIGURE 2-29: Power Supply Rejection (PSR) vs. Ripple Frequency. Amplitude (dB) FIGURE 2-26: Spurious Free Dynamic Range (SFDR) vs. Input Frequency. 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 100 Ripple Frequency (kHz) 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 VDD = VREF = 2.7 V FSAMPLE = 50 ksps FINPUT = 998.76 Hz 4096 points 0 5000 10000 15000 20000 25000 Frequency (Hz) FIGURE 2-30: Frequency Spectrum of 1 kHz input (Representative Part, VDD = 2.7V). DS21298E-page 11 MCP3204/3208 Note: Unless otherwise indicated, VDD = VREF = 5V, VSS = 0V, fSAMPLE = 100 ksps, fCLK = 20* fSAMPLE, TA = +25°C. 500 100 VREF = VDD All points at FCLK = 2 MHz, except at VREF = VDD = 2.5 V, FCLK = 1 MHz 450 400 80 70 300 IREF (µA) IDD (µA) 350 VREF = VDD All points at FCLK = 2 MHz except at VREF = VDD = 2.5 V, FCLK = 1 MHz 90 250 200 60 50 40 150 30 100 20 50 10 0 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 2.0 2.5 3.0 3.5 FIGURE 2-31: 4.0 4.5 5.0 5.5 6.0 VDD (V) VDD (V) FIGURE 2-34: IDD vs. VDD. IREF vs. VDD. 100 400 90 350 VDD = VREF = 5 V 80 70 VDD = VREF = 5 V 250 200 IREF (µA) IDD (µA) 300 VDD = VREF = 2.7 V 150 60 50 40 VDD = VREF = 2.7 V 30 100 20 50 10 0 0 10 100 1000 10 10000 100 Clock Frequency (kHz) FIGURE 2-32: 1000 10000 Clock Frequency (kHz) IDD vs. Clock Frequency. IREF vs. Clock Frequency. FIGURE 2-35: 400 100 VDD = VREF = 5 V FCLK = 2 MHz 350 VDD = VREF = 5 V FCLK = 2 MHz 90 80 300 IREF (µA) IDD (µA) 70 250 200 VDD = VREF = 2.7 V FCLK = 1 MHz 150 60 50 40 VDD = VREF = 2.7 V FCLK = 1 MHz 30 100 20 50 10 0 0 -50 -25 0 25 50 75 100 -50 -25 Temperature (°C) FIGURE 2-33: DS21298E-page 12 IDD vs. Temperature. 0 25 50 75 100 Temperature (°C) FIGURE 2-36: IREF vs. Temperature. © 2008 Microchip Technology Inc. MCP3204/3208 Note: Unless otherwise indicated, VDD = VREF = 5V, VSS = 0V, fSAMPLE = 100 ksps, fCLK = 20* fSAMPLE, TA = +25°C. 2.0 70 Analog Input Leakage (nA) 80 VREF = CS = VDD IDDS (pA) 60 50 40 30 20 10 0 1.8 1.6 1.4 1.2 VDD = VREF = 5 V FCLK = 2 MHz 1.0 0.8 0.6 0.4 0.2 0.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD (V) FIGURE 2-37: -50 -25 0 25 50 75 100 Temperature (°C) FIGURE 2-39: Analog Input Leakage Current vs. Temperature. IDDS vs. VDD. 100.00 VDD = VREF = CS = 5 V IDDS (nA) 10.00 1.00 0.10 0.01 -50 -25 0 25 50 75 100 Temperature (°C) FIGURE 2-38: IDDS vs. Temperature. © 2008 Microchip Technology Inc. DS21298E-page 13 MCP3204/3208 NOTES: DS21298E-page 14 © 2008 Microchip Technology Inc. MCP3204/3208 3.0 PIN DESCRIPTIONS The descriptions of the pins are listed in Table 3-1. TABLE 3-1: PIN FUNCTION TABLE MCP3204 MCP3208 PDIP, SOIC, TSSOP PDIP, SOIC 1 1 CH0 Analog Input 2 2 CH1 Analog Input 3 3 CH2 Analog Input 3.1 Symbol 4 4 CH3 Analog Input — 5 CH4 Analog Input — 6 CH5 Analog Input — 7 CH6 Analog Input — 8 CH7 7 9 DGND 8 10 CS/SHDN 9 11 DIN 10 12 DOUT Serial Data Out 11 13 CLK Serial Clock 12 14 AGND 13 15 VREF Reference Voltage Input 14 16 VDD +2.7V to 5.5V Power Supply 5, 6 — NC No Connection Digital Ground (DGND) Digital ground connection to internal digital circuitry. 3.2 Analog Inputs (CH0 - CH7) Analog inputs for channels 0 - 7 for the multiplexed inputs. Each pair of channels can be programmed to be used as two independent channels in single-ended mode or as a single pseudo-differential input, where one channel is IN+ and one channel is IN. See Section 4.1 “Analog Inputs”, “Analog Inputs”, and Section 5.0 “Serial communications”, “Serial Communications”, for information on programming the channel configuration. 3.4 Analog Input Digital Ground Chip Select/Shutdown Input Serial Data In Analog Ground 3.5 Serial Data Input (DIN) The SPI port serial data input pin is used to load channel configuration data into the device. Analog Ground (AGND) Analog ground connection to internal analog circuitry. 3.3 Definition 3.6 Serial Data Output (DOUT) The SPI serial data output pin is used to shift out the results of the A/D conversion. Data will always change on the falling edge of each clock as the conversion takes place. 3.7 Chip Select/Shutdown (CS/SHDN) The CS/SHDN pin is used to initiate communication with the device when pulled low and will end a conversion and put the device in low power standby when pulled high. The CS/SHDN pin must be pulled high between conversions. Serial Clock (CLK) The SPI clock pin is used to initiate a conversion and clock out each bit of the conversion as it takes place. See Section 6.2 “Maintaining Minimum Clock Speed”, “Maintaining Minimum Clock Speed”, for constraints on clock speed. © 2008 Microchip Technology Inc. DS21298E-page 15 MCP3204/3208 NOTES: DS21298E-page 16 © 2008 Microchip Technology Inc. MCP3204/3208 4.0 DEVICE OPERATION The MCP3204/3208 A/D converters employ a conventional SAR architecture. With this architecture, a sample is acquired on an internal sample/hold capacitor for 1.5 clock cycles starting on the fourth rising edge of the serial clock after the start bit has been received. Following this sample time, the device uses the collected charge on the internal sample/hold capacitor to produce a serial 12-bit digital output code. Conversion rates of 100 ksps are possible on the MCP3204/3208. See Section 6.2 “Maintaining Minimum Clock Speed”, “Maintaining Minimum Clock Speed”, for information on minimum clock rates. Communication with the device is accomplished using a 4-wire SPI-compatible interface. 4.1 4.2 Reference Input For each device in the family, the reference input (VREF) determines the analog input voltage range. As the reference input is reduced, the LSB size is reduced accordingly. The theoretical digital output code produced by the A/D converter is a function of the analog input signal and the reference input, as shown below. EQUATION 4-1: 4096 × V IN Digital Output Code = --------------------------V REF Where: VIN = analog input voltage VREF = reference voltage Analog Inputs The MCP3204/3208 devices offer the choice of using the analog input channels configured as single-ended inputs or pseudo-differential pairs. The MCP3204 can be configured to provide two pseudo-differential input pairs or four single-ended inputs, while the MCP3208 can be configured to provide four pseudo-differential input pairs or eight single-ended inputs. Configuration is done as part of the serial command before each conversion begins. When used in the pseudodifferential mode, each channel pair (i.e., CH0 and CH1, CH2 and CH3 etc.) is programmed to be the IN+ and IN- inputs as part of the command string transmitted to the device. The IN+ input can range from IN- to (VREF + IN-). The IN- input is limited to ±100 mV from the VSS rail. The IN- input can be used to cancel small signal common-mode noise which is present on both the IN+ and IN- inputs. When using an external voltage reference device, the system designer should always refer to the manufacturer’s recommendations for circuit layout. Any instability in the operation of the reference device will have a direct effect on the operation of the A/D converter. When operating in the pseudo-differential mode, if the voltage level of IN+ is equal to or less than IN-, the resultant code will be 000h. If the voltage at IN+ is equal to or greater than {[VREF + (IN-)] - 1 LSB}, then the output code will be FFFh. If the voltage level at IN- is more than 1 LSB below VSS, the voltage level at the IN+ input will have to go below VSS to see the 000h output code. Conversely, if IN- is more than 1 LSB above VSS, then the FFFh code will not be seen unless the IN+ input level goes above VREF level. For the A/D converter to meet specification, the charge holding capacitor (CSAMPLE) must be given enough time to acquire a 12-bit accurate voltage level during the 1.5 clock cycle sampling period. The analog input model is shown in Figure 4-1. This diagram illustrates that the source impedance (RS) adds to the internal sampling switch (RSS) impedance, directly effecting the time that is required to charge the capacitor (CSAMPLE). Consequently, larger source impedances increase the offset, gain and integral linearity errors of the conversion (see Figure 4-2). © 2008 Microchip Technology Inc. DS21298E-page 17 MCP3204/3208 VDD RSS VT = 0.6V CHx CPIN 7 pF VA Sampling Switch SS RS = 1 kΩ ILEAKEAGE ±1 nA VT = 0.6V CSAMPLE = DAC capacitance = 20 pF VSS Legend VA = Signal Source Ileakage = Leakage Current At The Pin Due To Various Junctions Rss = Source Impedance SS = Sampling switch CHx = Input Channel Pad Rs = Sampling switch resistor Cpin = Input Pin Capacitance Csample = Sample/hold capacitance Vt = Threshold Voltage FIGURE 4-1: Analog Input Model. Clock Frequency (MHz) 2.5 VDD = 5 V 2.0 1.5 1.0 VDD = 2.7 V 0.5 0.0 100 1000 10000 Input Resistance (Ohms) FIGURE 4-2: Maximum Clock Frequency vs. Input resistance (RS) to maintain less than a 0.1 LSB deviation in INL from nominal conditions. DS21298E-page 18 © 2008 Microchip Technology Inc. MCP3204/3208 5.0 SERIAL COMMUNICATIONS Communication with the MCP3204/3208 devices is accomplished using a standard SPI-compatible serial interface. Initiating communication with either device is done by bringing the CS line low (see Figure 5-1). If the device was powered up with the CS pin low, it must be brought high and back low to initiate communication. The first clock received with CS low and DIN high will constitute a start bit. The SGL/DIFF bit follows the start bit and will determine if the conversion will be done using single-ended or differential input mode. The next three bits (D0, D1 and D2) are used to select the input channel configuration. Table 5-1 and Table 5-2 show the configuration bits for the MCP3204 and MCP3208, respectively. The device will begin to sample the analog input on the fourth rising edge of the clock after the start bit has been received. The sample period will end on the falling edge of the fifth clock following the start bit. Once the D0 bit is input, one more clock is required to complete the sample and hold period (DIN is a “don’t care” for this clock). On the falling edge of the next clock, the device will output a low null bit. The next 12 clocks will output the result of the conversion with MSB first, as shown in Figure 5-1. Data is always output from the device on the falling edge of the clock. If all 12 data bits have been transmitted and the device continues to receive clocks while the CS is held low, the device will output the conversion result LSB first, as shown in Figure 5-2. If more clocks are provided to the device while CS is still low (after the LSB first data has been transmitted), the device will clock out zeros indefinitely. If necessary, it is possible to bring CS low and clock in leading zeros on the DIN line before the start bit. This is often done when dealing with microcontroller-based SPI ports that must send 8 bits at a time. Refer to Section 6.1 “Using the MCP3204/3208 with Microcontroller (MCU) SPI Ports” for more details on using the MCP3204/3208 devices with hardware SPI ports. © 2008 Microchip Technology Inc. TABLE 5-1: CONFIGURATION BITS FOR THE MCP3204 Control Bit Selections Input Configuration Single/ D2* D1 D0 Diff Channel Selection 1 X 0 0 single-ended CH0 1 X 0 1 single-ended CH1 1 X 1 0 single-ended CH2 1 X 1 1 single-ended CH3 0 X 0 0 differential CH0 = IN+ CH1 = IN- 0 X 0 1 differential CH0 = INCH1 = IN+ 0 X 1 0 differential CH2 = IN+ CH3 = IN- 0 X 1 1 differential CH2 = INCH3 = IN+ * D2 is a “don’t care” for MCP3204 TABLE 5-2: CONFIGURATION BITS FOR THE MCP3208 Control Bit Selections Input Configuration Channel Selection Single /Diff D2 1 0 0 0 single-ended CH0 1 0 0 1 single-ended CH1 1 0 1 0 single-ended CH2 1 0 1 1 single-ended CH3 1 1 0 0 single-ended CH4 1 1 0 1 single-ended CH5 1 1 1 0 single-ended CH6 1 1 1 1 single-ended CH7 0 0 0 0 differential CH0 = IN+ CH1 = IN- 0 0 0 1 differential CH0 = INCH1 = IN+ 0 0 1 0 differential CH2 = IN+ CH3 = IN- 0 0 1 1 differential CH2 = INCH3 = IN+ 0 1 0 0 differential CH4 = IN+ CH5 = IN- 0 1 0 1 differential CH4 = INCH5 = IN+ 0 1 1 0 differential CH6 = IN+ CH7 = IN- 0 1 1 1 differential CH6 = INCH7 = IN+ D1 D0 DS21298E-page 19 MCP3204/3208 tCYC tCYC tCSH CS tSUCS CLK SGL/ DIN Start DIFF D2 D1 D0 HI-Z DOUT Start SGL/ DIFF D2 Don’t Care Null Bit B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0* HI-Z tCONV tSAMPLE tDATA ** * After completing the data transfer, if further clocks are applied with CS low, the A/D converter will output LSB first data, followed by zeros indefinitely (see Figure 5-2 below). ** tDATA: during this time, the bias current and the comparator power down while the reference input becomes a high impedance node, leaving the CLK running to clock out the LSB-first data or zeros. FIGURE 5-1: Communication with the MCP3204 or MCP3208. tCYC tCSH CS tSUCS Power Down CLK Start DIN D2 D1 D0 Don’t Care SGL/ DIFF DOUT HI-Z * Null B11B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10B11 Bit HI-Z (MSB) tSAMPLE tCONV tDATA ** * After completing the data transfer, if further clocks are applied with CS low, the A/D converter will output zeros indefinitely. ** tDATA: During this time, the bias circuit and the comparator power down while the reference input becomes a high impedance node, leaving the CLK running to clock out LSB first data or zeroes. FIGURE 5-2: DS21298E-page 20 Communication with MCP3204 or MCP3208 in LSB First Format. © 2008 Microchip Technology Inc. MCP3204/3208 6.0 APPLICATIONS INFORMATION 6.1 Using the MCP3204/3208 with Microcontroller (MCU) SPI Ports As is shown in Figure 6-1, the first byte transmitted to the A/D converter contains five leading zeros before the start bit. Arranging the leading zeros this way allows the output 12 bits to fall in positions easily manipulated by the MCU. The MSB is clocked out of the A/D converter on the falling edge of clock number 12. Once the second eight clocks have been sent to the device, the MCU’s receive buffer will contain three unknown bits (the output is at high impedance for the first two clocks), the null bit and the highest order four bits of the conversion. Once the third byte has been sent to the device, the receive register will contain the lowest order eight bits of the conversion results. Employing this method ensures simpler manipulation of the converted data. With most microcontroller SPI ports, it is required to send groups of eight bits. It is also required that the microcontroller SPI port be configured to clock out data on the falling edge of clock and latch data in on the rising edge. Because communication with the MCP3204/3208 devices may not need multiples of eight clocks, it will be necessary to provide more clocks than are required. This is usually done by sending ‘leading zeros’ before the start bit. As an example, Figure 6-1 and Figure 6-2 illustrate how the MCP3204/ 3208 can be interfaced to a MCU with a hardware SPI port. Figure 6-1 depicts the operation shown in SPI Mode 0,0, which requires that the SCLK from the MCU idles in the ‘low’ state, while Figure 6-2 shows the similar case of SPI Mode 1,1, where the clock idles in the ‘high’ state. Figure 6-2 shows the same thing in SPI Mode 1,1, which requires that the clock idles in the high state. As with mode 0,0, the A/D converter outputs data on the falling edge of the clock and the MCU latches data from the A/D converter in on the rising edge of the clock. CS MCU latches data from A/D converter on rising edges of SCLK SCLK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 Data is clocked out of A/D converter on falling edges SGL/ Start DIFF D2 DIN DOUT Data stored into MCU receive register after transmission of first X = “Don’t Care” Bits 8 bits Don’t Don’tCare Care NULL BIT B11 B10 B9 B8 HI-Z Start Bit MCU Transmitted Data SGL/ D2 SGL/ (Aligned with falling 0 0 0 0 0 1 DIFF DIFF D2 edge of clock) MCU Received Data (Aligned with rising ? ? ? ? ? ? ? ? edge of clock) FIGURE 6-1: DO D1 D1 D1 DO DO ? ? ? ? X X X X X B7 X 0 ? 0 B11 B10 B9 B8 ? (Null) B11 B10 B9 B8 Data stored into MCU receive register after transmission of second 8 bits B6 B5 B4 B3 B2 B1 B0 X X X X X X X X B7 B6 B6 B5 B5 B4 B4 B3 B3 B2 B2 B1 B1 B0 B0 B7 Data stored into MCU receive register after transmission of last 8 bits SPI Communication using 8-bit segments (Mode 0,0: SCLK idles low). © 2008 Microchip Technology Inc. DS21298E-page 21 MCP3204/3208 CS MCU latches data from A/D converter on rising edges of SCLK SCLK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 Data is clocked out of A/D converter on falling edges SGL/ DIN Start DIFF FIGURE 6-2: 6.2 NULL BIT B11 B10 B9 0 ? 0 ? 0 ? 1 SGL/ D2 0 ? D1 DO DIFF ? ? ? ? Data stored into MCU receive register after transmission of first 8 bits ? ? X X X X X X 0 ? (Null) B11 B10 B9 B8 Data stored into MCU receive register after transmission of second 8 bits B7 B6 B5 B4 B3 B2 B1 B0 X X X X X X X X B7 B6 B5 B4 B3 B2 B1 B0 Data stored into MCU receive register after transmission of last 8 bits SPI Communication using 8-bit segments (Mode 1,1: SCLK idles high). Maintaining Minimum Clock Speed When the MCP3204/3208 initiates the sample period, charge is stored on the sample capacitor. When the sample period is complete, the device converts one bit for each clock that is received. It is important for the user to note that a slow clock rate will allow charge to bleed off the sample capacitor while the conversion is taking place. At 85°C (worst case condition), the part will maintain proper charge on the sample capacitor for at least 1.2 ms after the sample period has ended. This means that the time between the end of the sample period and the time that all 12 data bits have been clocked out must not exceed 1.2 ms (effective clock frequency of 10 kHz). Failure to meet this criterion may introduce linearity errors into the conversion outside the rated specifications. It should be noted that during the entire conversion cycle, the A/D converter does not require a constant clock speed or duty cycle, as long as all timing specifications are met. DS21298E-page 22 B8 Start Bit MCU Transmitted Data (Aligned with falling 0 edge of clock) X = “Don’t Care” Bits Don’t Care D1 DO HI-Z DOUT MCU Received Data (Aligned with rising edge of clock) D2 6.3 Buffering/Filtering the Analog Inputs If the signal source for the A/D converter is not a low impedance source, it will have to be buffered or inaccurate conversion results may occur (see Figure 4-2). It is also recommended that a filter be used to eliminate any signals that may be aliased back into the conversion results, as is illustrated in Figure 6-3, where an op amp is used to drive the analog input of the MCP3204/3208. This amplifier provides a low impedance source for the converter input, and a low pass filter, which eliminates unwanted high frequency noise. Low-pass (anti-aliasing) filters can be designed using Microchip’s free interactive FilterLab® software. FilterLab will calculate capacitor and resistor values, as well as determine the number of poles that are required for the application. For more information on filtering signals, see AN699, “Anti-Aliasing Analog Filters for Data Acquisition Systems”. © 2008 Microchip Technology Inc. MCP3204/3208 VDD 10 µF 4.096V Reference 0.1 µF 1 µF MCP1541 1 µF IN+ VREF MCP3204 VIN R1 C1 MCP601 IN- + R2 - C2 R3 R4 FIGURE 6-3: The MCP601 Operational Amplifier is used to implement a second order anti-aliasing filter for the signal being converted by the MCP3204. 6.4 Layout Considerations VDD When laying out a printed circuit board for use with analog components, care should be taken to reduce noise wherever possible. A bypass capacitor should always be used with this device, placed as close as possible to the device pin. A bypass capacitor value of 1 µF is recommended. Digital and analog traces should be separated as much as possible on the board, with no traces running underneath the device or the bypass capacitor. Extra precautions should be taken to keep traces with high frequency signals (such as clock lines) as far as possible from analog traces. Use of an analog ground plane is recommended in order to keep the ground potential the same for all devices on the board. Providing VDD connections to devices in a “star” configuration can also reduce noise by eliminating return current paths and associated errors (see Figure 6-4). For more information on layout tips when using A/D converters, refer to AN688, “Layout Tips for 12-Bit A/D converter Applications”. © 2008 Microchip Technology Inc. Connection Device 4 Device 1 Device 3 Device 2 FIGURE 6-4: VDD traces arranged in a ‘Star’ configuration in order to reduce errors caused by current return paths. DS21298E-page 23 MCP3204/3208 6.5 Utilizing the Digital and Analog Ground Pins The MCP3204/3208 devices provide both digital and analog ground connections to provide another means of noise reduction. As shown in Figure 6-5, the analog and digital circuitry is separated internal to the device. This reduces noise from the digital portion of the device being coupled into the analog portion of the device. The two grounds are connected internally through the substrate, which has a resistance of 5 -10Ω. If no ground plane is utilized, then both grounds must be connected to VSS on the board. If a ground plane is available, both digital and analog ground pins should be connected to the analog ground plane. If both an analog and a digital ground plane are available, both the digital and the analog ground pins should be connected to the analog ground plane. Following these steps will reduce the amount of digital noise from the rest of the board being coupled into the A/D converter. VDD MCP3204/08 Digital Side Analog Side -SPI Interface -Shift Register -Control Logic -Sample Cap -Capacitor Array -Comparator Substrate 5 - 10Ω DGND AGND 0.1 µF Analog Ground Plane FIGURE 6-5: Separation of Analog and Digital Ground Pins. DS21298E-page 24 © 2008 Microchip Technology Inc. MCP3204/3208 7.0 PACKAGING INFORMATION 7.1 Package Marking Information 14-Lead PDIP (300 mil) (MCP3204) Example: XXXXXXXXXXXXXX XXXXXXXXXXXXXX YYWWNNN 14-Lead SOIC (150 mil) (MCP3204) XXXXXXXXXXX XXXXXXXXXXX YYWWNNN 14-Lead TSSOP (4.4mm)* (MCP3204) MCP3204-B I/P e3 0819256 Example: MCP3204-B I/SL e3 XXXXXXXI/XXXX 0819256 Example: XXXXXXXX 3204-C YYWW 0819 NNN 256 Legend: XX...X Y YY WW NNN e3 * Note: Customer-specific information Year code (last digit of calendar year) Year code (last 2 digits of calendar year) Week code (week of January 1 is week ‘01’) Alphanumeric traceability code Pb-free JEDEC designator for Matte Tin (Sn) This package is Pb-free. The Pb-free JEDEC designator ( e3 ) can be found on the outer packaging for this package. In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. © 2008 Microchip Technology Inc. DS21298E-page 25 MCP3204/3208 Package Marking Information (Continued) 16-Lead PDIP (300 mil) (MCP3208) Example: XXXXXXXXXXXXXX XXXXXXXXXXXXXX YYWWNNN 16-Lead SOIC (150 mil) (MCP3208) XXXXXXXXXXXXX XXXXXXXXXXXXX YYWWNNN DS21298E-page 26 MCP3208-BI/P e3 0819256 Example: MCP3208-B I/SL e3 XXXXIXXXXXX 0819256 © 2008 Microchip Technology Inc. MCP3204/3208                 3 %& %! %4" ) '  % 4$%  %"% %%255)))&  &54 N NOTE 1 E1 1 3 2 D E A2 A L A1 c b1 b e eB 6% &  9&% 7!&(  $ 7+8- 7 7 7: ;  %  % %  < <   ""4 4  0 , 0 1 % %  0 < <  !" %  !" ="% -  , ,0  ""4="% -  0 > : 9%  ,0 0 0 % % 9 0 , 0 9" 4  >  0 ( 0 ?  (  >  1 < < 6 9"="% 9 ) 9"="% :  )* 1+ ,     !"#$%! & '(!%&! %( %")%%%"   *$%+ %  % , &   "-"  %!"& "$   % !    "$   % !     %#".  "  &  "%   -/0 1+21 &    %#%!  ))% !%%          ) +01 © 2008 Microchip Technology Inc. DS21298E-page 27 MCP3204/3208    ! "  !  ##$% &'   !"(   3 %& %! %4" ) '  % 4$%  %"% %%255)))&  &54 D N E E1 NOTE 1 1 2 3 e h b A A2 c φ L A1 β L1 6% &  9&% 7!&(  $ α h 99- - 7 7 7: ;  %  : 8%  < 1+ <  ""4 4  0 < < %" $$*   < 0 : ="% -  ""4="% - ,1+ : 9%  >?01+ 0 ?1+ +&$ @ % A  0 < 0 3 %9% 9  <  3 % % 9 -3 3 % I B < >B 9" 4   < 0 9"="% ( , < 0  " $%  D 0B < 0B  " $%1 %% & E 0B < 0B     !"#$%! & '(!%&! %( %")%%%"   *$%+ %  % , &   "-"  %!"& "$   % !    "$   % !     %#"0&&  "  &  "%   -/0 1+2 1 &    %#%!  ))% !%%    -32 $ &  '! !)% !%%  '$ $ &% !           ) +?01 DS21298E-page 28 © 2008 Microchip Technology Inc. MCP3204/3208   3 %& %! %4" ) '  % 4$%  %"% %%255)))&  &54 © 2008 Microchip Technology Inc. DS21298E-page 29 MCP3204/3208    )* !*#+ ! "  !)  &   )!!"    3 %& %! %4" ) '  % 4$%  %"% %%255)))&  &54 D N E E1 NOTE 1 1 2 e b A2 A c A1 φ 6% &  9&% 7!&(  $ L L1 99- - 7 7 7: ;  %  : 8%  < ?01+ <  ""4 4  >  0 %" $$  0 < 0  : ="% -  ""4="% - , ?1+   ""49%   0 0 3 %9% 9 0 ? 0 3 % % 9 0 -3 3 % I B < >B 9" 4   <  9"="% (  < ,     !"#$%! & '(!%&! %( %")%%%"   &   "-"  %!"& "$   % !    "$   % !     %#"0&&  " , &  "%   -/0 1+2 1 &    %#%!  ))% !%%    -32 $ &  '! !)% !%%  '$ $ &% !           ) +>1 DS21298E-page 30 © 2008 Microchip Technology Inc. MCP3204/3208 ,                3 %& %! %4" ) '  % 4$%  %"% %%255)))&  &54 N NOTE 1 E1 1 2 3 D E A A2 L A1 c b1 b e eB 6% &  9&% 7!&(  $ 7+8- 7 7 7: ; ? %  % %  < <   ""4 4  0 , 0 1 % %  0 < <  !" %  !" ="% -  , ,0  ""4="% -  0 > : 9%  ,0 00 0 % % 9 0 , 0 9" 4  >  0 ( 0 ?  (  >  1 < < 6 9"="% 9 ) 9"="% :  )* 1+ ,     !"#$%! & '(!%&! %( %")%%%"   *$%+ %  % , &   "-"  %!"& "$   % !    "$   % !     %#".  "  &  "%   -/0 1+2 1 &    %#%!  ))% !%%          ) +1 © 2008 Microchip Technology Inc. DS21298E-page 31 MCP3204/3208 ,   ! "  !  ##$% &'   !"(   3 %& %! %4" ) '  % 4$%  %"% %%255)))&  &54 D N E E1 NOTE 1 1 3 2 e b h α h A1 L β L1 6% &  9&% 7!&(  $ c φ A2 A 99- - 7 7 7: ; ? %  : 8%  < 1+ <  ""4 4  0 < < %" $$*   < 0 : ="% -  ""4="% - ,1+ : 9%  1+ 0 ?1+ +&$ @ % A  0 < 0 3 %9% 9  <  3 % % 9 -3 3 % I B < >B 9" 4   < 0 9"="% ( , < 0  " $%  D 0B < 0B  " $%1 %% & E 0B < 0B     !"#$%! & '(!%&! %( %")%%%"   *$%+ %  % , &   "-"  %!"& "$   % !    "$   % !     %#"0&&  "  &  "%   -/0 1+2 1 &    %#%!  ))% !%%    -32 $ &  '! !)% !%%  '$ $ &% !           ) +>1 DS21298E-page 32 © 2008 Microchip Technology Inc. MCP3204/3208   3 %& %! %4" ) '  % 4$%  %"% %%255)))&  &54 © 2008 Microchip Technology Inc. DS21298E-page 33 MCP3204/3208 NOTES: DS21298E-page 34 © 2008 Microchip Technology Inc. MCP3204/3208 APPENDIX A: REVISION HISTORY Revision E (September 2008) The following is the list of modifications: 1. Updated package outline drawings Section 7.0 “Packaging Information”. in Revision D (January 2007) The following is the list of modifications: 1. Undocumented changes Revision C (May 2002) The following is the list of modifications: 1. Undocumented changes Revision B (August 1999) The following is the list of modifications: 1. Undocumented changes Revision A (November 1998) • Initial release of this document. © 2008 Microchip Technology Inc. DS21298E-page 35 MCP3204/3208 NOTES: DS21298E-page 36 © 2008 Microchip Technology Inc. MCP3204/3208 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. –X Device Grade Device X /XX Temperature Package Range MCP3204: 4-Channel 12-Bit Serial A/D Converter MCP3204T: 4-Channel 12-Bit Serial A/D Converter (Tape and Reel) MCP3208: 8-Channel 12-Bit Serial A/D Converter MCP3208T: 8-Channel 12-Bit Serial A/D Converter (Tape and Reel) Grade: B C Temperature Range I Package P SL ST = ±1 LSB INL = ±2 LSB INL = -40°C to +85°C (Industrial) = Plastic DIP (300 mil Body), 14-lead, 16-lead = Plastic SOIC (150 mil Body), 14-lead, 16-lead = Plastic TSSOP (4.4mm), 14-lead © 2008 Microchip Technology Inc. Examples: a) MCP3204-BI/P: ±1 LSB INL, Industrial Temperature, PDIP package. b) MCP3204-BI/SL: ±1 LSB INL, Industrial Temperature, SOIC package. c) MCP3204-CI/ST: ±2 LSB INL, Industrial Temperature, TSSOP package. a) MCP3208-BI/P: ±1 LSB INL, Industrial Temperature, PDIP package. b) MCP3208-BI/SL: ±1 LSB INL, Industrial Temperature, SOIC package. c) MCP3208-CI/ST: ±2 LSB INL, Industrial Temperature, TSSOP package. DS21298E-page 37 MCP3204/3208 NOTES: DS21298E-page 38 © 2008 Microchip Technology Inc. Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. • Microchip is willing to work with the customer who is concerned about the integrity of their code. • Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer’s risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights. Trademarks The Microchip name and logo, the Microchip logo, Accuron, dsPIC, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART, rfPIC, SmartShunt and UNI/O are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. FilterLab, Linear Active Thermistor, MXDEV, MXLAB, SEEVAL, SmartSensor and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. Analog-for-the-Digital Age, Application Maestro, CodeGuard, dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN, ECONOMONITOR, FanSense, In-Circuit Serial Programming, ICSP, ICEPIC, Mindi, MiWi, MPASM, MPLAB Certified logo, MPLIB, MPLINK, mTouch, PICkit, PICDEM, PICDEM.net, PICtail, PIC32 logo, PowerCal, PowerInfo, PowerMate, PowerTool, REAL ICE, rfLAB, Select Mode, Total Endurance, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. © 2008, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. Microchip received ISO/TS-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company’s quality system processes and procedures are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified. © 2008 Microchip Technology Inc. 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