MCP3304T-CI/SL

MCP3302/04 13-Bit Differential Input, Low Power A/D Converter with SPI Serial Interface Features General Description • • • • • • • • • • • • • The MCP3302/04 13-bit A/D converter features full differential inputs and low-power consumption in a small package that is ideal for battery-powered systems and remote data acquisition applications. Full Differential Inputs 2 Differential or 4 Single-ended inputs (MCP3302) 4 Differential or 8 Single-ended Inputs (MCP3304) ±1 LSB maximum DNL ±1 LSB maximum INL (MCP3302/04-B) ±2 LSB maximum INL (MCP3302/04-C) Single supply operation: 4.5V to 5.5V 100 ksps sampling rate with 5V supply voltage 50 nA typical standby current, 1 µA maximum 450 µA maximum active current at 5V Industrial Temperature Range: -40°C to +85°C 14 and 16-pin PDIP, SOIC, and TSSOP packages Mixed Signal PICtail™ Demo Board (P/N: MXSIGDM) compatible Applications The MCP3302 is user-programmable to provide two differential input pairs or four single-ended inputs. The MCP3304 is also user-programmable to configure into four differential input pairs or eight single-ended inputs. Incorporating a successive approximation architecture with on-board sample and hold circuitry, these 13-bit A/D converters are specified to have ±1 LSB Differential Nonlinearity (DNL); ±1 LSB Integral Nonlinearity (INL) for B-grade and ±2 LSB for C-grade devices. The industry-standard SPI serial interface enables 13-bit A/D converter capability to be added to any PIC® microcontroller. The MCP3302/04 devices feature low current design that permits operation with typical standby and active currents of only 50 nA and 300 µA, respectively. The device is capable of conversion rates of up to 100 ksps with tested specifications over a 4.5V to 5.5V supply range. The reference voltage can be varied from 400 mV to 5V, yielding input-referred resolution between 98 µV and 1.22 mV. • Remote Sensors • Battery-operated Systems • Transducer Interface The MCP3302 is available in 14-pin PDIP, 150 mil SOIC and TSSOP packages. The MCP3304 is available in 16-pin PDIP and 150 mil SOIC packages. The full differential inputs of these devices enable a wide variety of signals to be used in applications such as remote data acquisition, portable instrumentation, and battery-operated applications. Package Types PDIP, SOIC, TSSOP PDIP, SOIC 14 13 12 11 10 9 8 VDD VREF AGND CLK DOUT DIN CS/SHDN CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 1 2 3 4 5 6 7 8 MCP3304  2011 Microchip Technology Inc. 1 2 3 4 5 6 7 MCP3302 CH0 CH1 CH2 CH3 NC NC DGND 16 15 14 13 12 11 10 9 VDD VREF AGND CLK DOUT DIN CS/SHDN DGND DS21697F-page 1 MCP3302/04 Functional Block Diagram VREF CH0 CH1 VDD AGND DGND Input Channel Mux CH7* CDAC Sample & Hold Circuits - Comparator 13-Bit SAR + Control Logic CS/SHDN DIN CLK Shift Register DOUT * Channels 5-7 available on MCP3304 Only DS21697F-page 2  2011 Microchip Technology Inc. MCP3302/04 1.0 ELECTRICAL CHARACTERISTICS † Notice: Stresses above those listed under “Maximum ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. Absolute Maximum Ratings † VDD...................................................................................7.0V All inputs and outputs w.r.t. VSS ............... -0.3V to VDD +0.3V Storage temperature .....................................-65°C to +150°C Ambient temp. with power applied ................-65°C to +125°C Maximum Junction Temperature .................................. 150°C ESD protection on all pins (HBM)  4 kV ELECTRICAL SPECIFICATIONS Electrical Characteristics: Unless otherwise noted, all parameters apply at VDD = 5V, VSS = 0V, and VREF = 5V. Full differential input configuration (Figure 1-5) with fixed common mode voltage of 2.5V. All parameters apply over temperature with TA = -40°C to +85°C (Note 7). Conversion speed (FSAMPLE) is 100 ksps with FCLK = 21*FSAMPLE Parameter Symbol Min Typ Max Units FSAMPLE — — 100 ksps Conditions Conversion Rate Maximum Sampling Frequency Conversion Time TCONV 13 CLK periods Acquisition Time TACQ 1.5 CLK periods See FCLK specification. Note 8 DC Accuracy Resolution 12 data bits + sign ±0.5 ±1 bits Integral Nonlinearity INL — LSB MCP3302/04-B — ±1 ±2 LSB MCP3302/04-C Differential Nonlinearity DNL — ±0.5 ±1 LSB Monotonic over temperature Positive Gain Error -3 -0.75 +2 LSB Negative Gain Error -3 -0.5 +2 LSB Offset Error -3 +3 +6 LSB THD — -91 — dB Note 3 SINAD — 78 — dB Note 3 Dynamic Performance Total Harmonic Distortion Signal-to-Noise and Distortion Spurious Free Dynamic Range SFDR — 92 — dB Note 3 Common Mode Rejection CMRR — 79 — dB Note 6 CT — > -110 — dB Note 6 PSR — 74 — dB Note 4 Note 2 Channel to Channel Crosstalk Power Supply Rejection Reference Input Voltage Range 0.4 — VDD V Current Drain — 100 150 µA — 0.001 3 µA Note 1: 2: 3: 4: 5: 6: 7: 8: 9: CS = VDD = 5V This specification is established by characterization and not 100% tested. See characterization graphs that relate converter performance to VREF level. VIN = 0.1V to 4.9V @ 1 kHz. VDD =5V DC ±500 mVP-P @ 1 kHz, see test circuit Figure 1-4. Maximum clock frequency specification must be met. VREF = 400 mV, VIN = 0.1V to 4.9V @ 1 kHz. TSSOP devices are only specified at 25°C and +85°C. For slow sample rates, see Section 5.2 “Driving the Analog Input” for limitations on clock frequency. 4.5V - 5.5V is the supply voltage range for specified performance.  2011 Microchip Technology Inc. DS21697F-page 3 MCP3302/04 ELECTRICAL SPECIFICATIONS (CONTINUED) Electrical Characteristics: Unless otherwise noted, all parameters apply at VDD = 5V, VSS = 0V, and VREF = 5V. Full differential input configuration (Figure 1-5) with fixed common mode voltage of 2.5V. All parameters apply over temperature with TA = -40°C to +85°C (Note 7). Conversion speed (FSAMPLE) is 100 ksps with FCLK = 21*FSAMPLE Parameter Symbol Min Full Scale Input Span CH0 - CH7 -VREF Absolute Input Voltage CH0 - CH7 -0.3 — Typ Max Units — VREF V — VDD + 0.3 V 0.001 ±1 µA Conditions Analog Inputs Leakage Current Switch Resistance RS — 1 — kΩ See Figure 5-3 Sample Capacitor CSAMPLE — 25 — pF See Figure 5-3 Digital Input/Output Data Coding Format Binary Two’s Complement High Level Input Voltage VIH 0.7 VDD — — Low Level Input Voltage VIL — — 0.3 VDD V High Level Output Voltage VOH 4.1 — — V IOH = -1 mA, VDD = 4.5V Low Level Output Voltage VOL — — 0.4 V IOL = 1 mA, VDD = 4.5V Input Leakage Current ILI -10 — 10 µA VIN = VSS or VDD Output Leakage Current ILO -10 — 10 µA VOUT = VSS or VDD CIN, COUT — — 10 pF TA = +25°C, F = 1 MHz, Note 1 VDD = 5V, FSAMPLE = 100 ksps Pin Capacitance V Timing Specifications: Clock Frequency (Note 8) FCLK 0.105 — 2.1 MHz Clock High Time THI 210 — — ns Note 5 Clock Low Time TLO 210 — — ns Note 5 TSUCS 100 — — ns CS Fall To First Rising CLK Edge Data In Setup time TSU 50 — — ns Data In Hold Time THD 50 — — ns CLK Fall To Output Data Valid TDO — — 125 ns VDD = 5V, see Figure 1-2 — — 200 ns VDD = 2.7V, see Figure 1-2 — — 125 ns VDD = 5V, see Figure 1-2 — — 200 ns VDD = 2.7V, see Figure 1-2 100 ns See test circuits, Figure 1-2 Note 1 CLK Fall To Output Enable TEN CS Rise To Output Disable TDIS — — CS Disable Time TCSH 475 — — ns DOUT Rise Time TR — — 100 ns See test circuits, Figure 1-2 Note 1 DOUT Fall Time TF — — 100 ns See test circuits, Figure 1-2 Note 1 Note 1: 2: 3: 4: 5: 6: 7: 8: 9: This specification is established by characterization and not 100% tested. See characterization graphs that relate converter performance to VREF level. VIN = 0.1V to 4.9V @ 1 kHz. VDD =5V DC ±500 mVP-P @ 1 kHz, see test circuit Figure 1-4. Maximum clock frequency specification must be met. VREF = 400 mV, VIN = 0.1V to 4.9V @ 1 kHz. TSSOP devices are only specified at 25°C and +85°C. For slow sample rates, see Section 5.2 “Driving the Analog Input” for limitations on clock frequency. 4.5V - 5.5V is the supply voltage range for specified performance. DS21697F-page 4  2011 Microchip Technology Inc. MCP3302/04 ELECTRICAL SPECIFICATIONS (CONTINUED) Electrical Characteristics: Unless otherwise noted, all parameters apply at VDD = 5V, VSS = 0V, and VREF = 5V. Full differential input configuration (Figure 1-5) with fixed common mode voltage of 2.5V. All parameters apply over temperature with TA = -40°C to +85°C (Note 7). Conversion speed (FSAMPLE) is 100 ksps with FCLK = 21*FSAMPLE Parameter Symbol Min Typ Max Units Conditions Operating Voltage VDD 4.5 — 5.5 V Operating Current IDD — 300 450 µA VDD, VREF = 5V, DOUT unloaded — 200 — µA VDD, VREF = 2.7V, DOUT unloaded — 0.05 1 µA CS = VDD = 5.0V Power Requirements: Standby Current Note 1: 2: 3: 4: 5: 6: 7: 8: 9: IDDS Note 9 This specification is established by characterization and not 100% tested. See characterization graphs that relate converter performance to VREF level. VIN = 0.1V to 4.9V @ 1 kHz. VDD =5V DC ±500 mVP-P @ 1 kHz, see test circuit Figure 1-4. Maximum clock frequency specification must be met. VREF = 400 mV, VIN = 0.1V to 4.9V @ 1 kHz. TSSOP devices are only specified at 25°C and +85°C. For slow sample rates, see Section 5.2 “Driving the Analog Input” for limitations on clock frequency. 4.5V - 5.5V is the supply voltage range for specified performance. TEMPERATURE CHARACTERISTICS Electrical Specifications: Unless otherwise indicated, VDD = +2.7V to +5.5V, VSS = GND. Parameters Sym Min Typ Max Units TA -40 — +125 °C Operating Temperature Range TA -40 — +125 °C Storage Temperature Range TA -65 — +150 °C Thermal Resistance, 14L-PDIP JA — 70 — °C/W Thermal Resistance, 14L-SOIC JA — 95.3 — °C/W Thermal Resistance, 14L-TSSOP JA — 100 — °C/W Thermal Resistance, 16L-PDIP JA — 70 — °C/W Thermal Resistance, 16L-SOIC JA — 86.1 — °C/W Conditions Temperature Ranges Specified Temperature Range Thermal Package Resistances TCSH CS TSUCS THI TLO CLK TSU DIN THD MSB IN TEN DOUT FIGURE 1-1: T TDO Null Bit Sign BIT TF TDIS LSB Timing Parameters.  2011 Microchip Technology Inc. DS21697F-page 5 MCP3302/04 1.1 Test Circuits VREF = 5V 1 µF MCP330X 1.4V 3 kΩ DOUT IN(+) CL = 100 pF 0.1 µF 0.1 µF 5VP-P Test Point VREFVDD MCP330X IN(-) 5VP-P FIGURE 1-2: VDD = 5V VSS Load Circuit for TR, TF, TDO. VCM = 2.5V Test Point MCP330X VDD VDD/2 3 kΩ DOUT 100 pF TDIS Waveform 2 FIGURE 1-5: Full Differential Test Configuration Example. TEN Waveform TDIS Waveform 1 VSS VREF = 2.5V VDD = 5V 1µF 0.1µF 0.1µF Voltage Waveforms for TDIS 5VP-P VIH CS IN(+) IN(-) DOUT Waveform 1* 90% TDIS VREF VDD MCP330X VSS VCM = 2.5V 10% DOUT Waveform 2† FIGURE 1-6: Pseudo Differential Test Configuration Example. *Waveform 1 is for an output with internal conditions such that the output is high, unless disabled by the output control. †Waveform 2 is for an output with internal conditions such that the output is low, unless disabled by the output control. FIGURE 1-3: TEN. Load circuit for TDIS and 1/2 MCP602 1 k + 20 kΩ 2.63V - 5V ±500 mVP-P 1 k To VDD on DUT 5VP-P 1 k FIGURE 1-4: Power Supply Sensitivity Test Circuit (PSRR). DS21697F-page 6  2011 Microchip Technology Inc. MCP3302/04 2.0 TYPICAL PERFORMANCE CURVES Note: The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore outside the warranted range. Note: Unless otherwise indicated, VDD = VREF = 5V, full differential input configuration, VSS = 0V, FSAMPLE = 100 ksps, FCLK = 21*FSAMPLE, TA = +25°C. . 1 1 0.8 0.8 0.6 0.6 Positive INL 0 -0.2 -0.4 Positive INL 0.4 0.2 INL (LSB) INL (LSB) 0.4 0.2 0 -0.2 -0.4 Negative INL -0.6 -0.6 -0.8 -0.8 -1 Negative INL -1 0 50 100 150 200 -50 -25 0 25 FIGURE 2-1: vs. Sample Rate. Integral Nonlinearity (INL) FIGURE 2-4: vs. Temperature. 2 1 1.5 0.8 100 125 150 Integral Nonlinearity (INL) 0 -0.5 Positive DNL 0.4 Positive INL 0.5 DNL (LSB) INL (LSB) 75 0.6 1 Negative INL 0.2 0 -0.2 Negative DNL -0.4 -1 -0.6 -1.5 -0.8 -2 0 1 2 3 4 -1 5 0 VREF(V) FIGURE 2-2: vs. VREF. Integral Nonlinearity (INL) 1 100 150 Sample Rate (ksps) 200 2 1.5 0.6 1 0.4 DNL(LSB) 0.2 0 -0.2 -0.4 Positive DNL 0.5 0 -0.5 Negative DNL -1 -0.6 -1.5 -0.8 -1 -4096 50 FIGURE 2-5: Differential Nonlinearity (DNL) vs. Sample Rate. 0.8 INL (LSB) 50 Temperature(°C) Sample Rate (ksps) -2 -3072 -2048 -1024 0 1024 2048 3072 4096 0 1 FIGURE 2-3: Integral Nonlinearity (INL) vs. Code (Representative Part).  2011 Microchip Technology Inc. 2 3 4 5 6 VREF(V) Code FIGURE 2-6: (DNL) vs. VREF. Differential Nonlinearity DS21697F-page 7 MCP3302/04 Note: Unless otherwise indicated, VDD = VREF = 5V, Full differential input configuration, VSS = 0V, FSAMPLE = 100 ksps, FCLK = 21*FSAMPLE, TA = +25°C. 20 18 0.6 16 2IIVHW(UURU/6% 1 0.8 DNL (LSB) 0.4 14 0.2 12 0 10 -0.2 -0.4 8 6 -0.6 4 -0.8 2 -1 -4096 0 -3072 -2048 -1024 0 1024 2048 3072 4096 0 1 2 Code 3 4 5 6 VREF(V) FIGURE 2-7: Differential Nonlinearity (DNL) vs. Code (Representative Part). Offset Error vs. VREF. FIGURE 2-10: 1 0 0.8 DNL (LSB) 0.4 Posittive Gain Error (LSB) 0.6 Positive DNL 0.2 0 -0.2 Negaitive DNL -0.4 -0.6 -0.8 -1 -50 -25 0 25 50 75 100 125 -0.2 -0.4 -0.6 -0.8 -1 -1.2 150 -50 Temperature (°C) FIGURE 2-8: Differential Nonlinearity (DNL) vs. Temperature. FIGURE 2-11: Temperature. 50 Temperature (°C) 100 150 Positive Gain Error vs. 100 90 3 80 2 70 1 60 SNR (db) Positive Gain Error (LSB) 4 0 0 50 40 30 -1 20 -2 10 -3 0 0 1 2 3 4 5 6 VREF(V) FIGURE 2-9: DS21697F-page 8 Positive Gain Error vs. VREF. 1 10 100 Input Frequency (kHz) FIGURE 2-12: Signal-to-Noise Ratio (SNR) vs. Input Frequency.  2011 Microchip Technology Inc. MCP3302/04 Note: Unless otherwise indicated, VDD = VREF = 5V, Full differential input configuration, VSS = 0V, FSAMPLE = 100 ksps, FCLK = 21*FSAMPLE, TA = +25°C. 0 80 -10 70 -20 60 SINAD (dB) THD (dB) -30 -40 -50 -60 50 40 30 -70 70 20 -80 10 -90 0 -100 1 10 -40 100 -30 Input Frequency (kHz) FIGURE 2-13: Total Harmonic Distortion (THD) vs. Input Frequency. -10 0 FIGURE 2-16: Signal-to-Noise and Distortion (SINAD) vs. Input Signal Level. 3.1 13 3 12 2.9 ENOB (rms) Offset Error (LSB) -20 Input Signal Level (dB) 2.8 2.7 11 10 9 2.6 8 2.5 -50 0 50 100 150 7 0 1 Temperature (°C) FIGURE 2-14: Temperature. Offset Error vs. FIGURE 2-17: (ENOB) vs. VREF. 2 3 VREF (V) 4 5 6 Effective Number of Bits 79 100 78 90 77 80 70 75 SFDR (dB) SINAD (dB) 76 74 73 72 60 50 40 30 71 20 70 10 69 1 10 Input Frequency (kHz) FIGURE 2-15: Signal-to-Noise and Distortion (SINAD) vs. Input Frequency.  2011 Microchip Technology Inc. 100 0 1 10 100 Input Frequency (kHz) FIGURE 2-18: Spurious Free Dynamic Range (SFDR) vs. Input Frequency. DS21697F-page 9 MCP3302/04 450 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 400 350 300 IDD (µA) Amplitude (dB) Note: Unless otherwise indicated, VDD = VREF = 5V, Full differential input configuration, VSS = 0V, FSAMPLE = 100 ksps, FCLK = 21*FSAMPLE, TA = +25°C. 200 150 100 50 0 0 10000 20000 30000 Frequency (Hz) 40000 2 50000 FIGURE 2-19: Frequency Spectrum of 10 kHz Input (Representative Part). 2.5 3 3.5 4 4.5 5 5.5 6 VDD (V) IDD vs. VDD. FIGURE 2-22: 12.85 600 500 12.8 400 12.75 IDD (µA) ENOB (rms) 250 12.7 300 200 12.65 100 0 12.6 1 10 0 100 50 Input Frequency (kHz) 100 150 200 Sample Rate (ksps) FIGURE 2-20: Effective Number of Bits (ENOB) vs. Input Frequency. IDD vs. Sample Rate. FIGURE 2-23: -30 390 -35 380 -40 370 -50 IDD (µA) PSR(dB) -45 -55 -60 -65 360 350 340 -70 330 -75 320 -80 1 10 100 1000 10000 -50 Ripple Frequency (kHz) FIGURE 2-21: Power Supply Rejection (PSR) vs. Ripple Frequency. A 0.1 µF bypass capacitor is connected to the VDD pin. DS21697F-page 10 0 50 100 150 Temperature (°C) FIGURE 2-24: IDD vs. Temperature.  2011 Microchip Technology Inc. MCP3302/04 Note: Unless otherwise indicated, VDD = VREF = 5V, Full differential input configuration, VSS = 0V, FSAMPLE = 100 ksps, FCLK = 21*FSAMPLE, TA = +25°C. 120 80 100 70 60 IDDS (pA) IREF (µA) 80 60 40 50 40 30 20 20 10 0 0 2 2.5 3 3.5 4 4.5 5 5.5 2 6 2.5 3 3.5 VDD (V) FIGURE 2-25: 4 4.5 5 5.5 6 VDD (V) IREF vs. VDD. FIGURE 2-28: IDDS vs. VDD. 100 120 100 10 IDDS (nA) IREF (µA) 80 60 1 0.1 40 0.01 20 0.001 0 0 50 100 150 -50 200 -25 0 IREF vs. Sample Rate. FIGURE 2-26: FIGURE 2-29: 50 75 100 IDDS vs. Temperature. 4 93 3.5 Nega ative Gain Error (LSB) 92 91 IREF (µA) 25 Temperature (°C) Sample Rate (ksps) 90 89 88 87 3 2.5 2 1.5 1 0.5 0 5 0 -0.5 86 -1 -50 0 50 100 Temperature (°C) FIGURE 2-27: IREF vs. Temperature.  2011 Microchip Technology Inc. 150 0 1 2 3 4 5 6 VREF (V) FIGURE 2-30: Negative Gain Error vs. Reference Voltage. DS21697F-page 11 MCP3302/04 2 80 1.5 79 Common Mode Rejection Ration(dB) Nega ative Gain Error (LSB) Note: Unless otherwise indicated, VDD = VREF = 5V, Full differential input configuration, VSS = 0V, FSAMPLE = 100 ksps, FCLK = 21*FSAMPLE, TA = +25°C. 1 0.5 0 -0.5 -1 -1.5 -2 -50 0 50 100 150 78 77 76 75 74 73 72 71 70 1 Temperature (°C) FIGURE 2-31: Temperature. DS21697F-page 12 Negative Gain Error vs. FIGURE 2-32: vs. Frequency. 10 100 Input Frequency (kHz) 1000 Common Mode Rejection  2011 Microchip Technology Inc. MCP3302/04 3.0 PIN DESCRIPTIONS The descriptions of the pins are listed in Table 3-1. TABLE 3-1: PIN FUNCTION TABLE MCP3302 MCP3304 PDIP, SOIC, TSSOP PDIP, SOIC 1 1 CH0 Analog Input 2 2 CH1 Analog Input 3 3 CH2 Analog Input 3.1 Symbol Description 4 4 CH3 Analog Input — 5 CH4 Analog Input — 6 CH5 Analog Input — 7 CH6 Analog Input Analog Input — 8 CH7 7 9 DGND 8 10 CS/SHDN 9 11 DIN 10 12 DOUT Serial Data Out 11 13 CLK Serial Clock 12 14 AGND 13 15 VREF Reference Voltage Input 14 16 VDD +4.5V to 5.5V Power Supply 5, 6 — NC No Connection Analog Inputs (CH0-CH7) Digital Ground Chip Select / Shutdown Input Serial Data In 3.4 Analog Ground Serial Data Input (DIN) Analog input channels. These pins have an absolute voltage range of VSS - 0.3V to VDD+ 0.3V. The full scale differential input range is defined as the absolute value of (IN+) - (IN-). This difference can not exceed the value of VREF - 1 LSB or digital code saturation will occur. The SPI port serial data input pin is used to clock in input channel configuration data. Data is latched on the rising edge of the clock. See Figure 6-2 for serial communication protocol. 3.2 The SPI serial data output pin is used to shift out the results of the A/D conversion. Data will always change on the falling edge of each clock as the conversion takes place. See Figure 6-2 for serial communication protocol. Digital Ground (DGND) Ground connection to internal digital circuitry. To ensure accuracy this pin must be connected to the same ground as AGND. If an analog ground plane is available, it is recommended that this device be tied to the analog ground plane in the circuit. See Section 5.6 “Layout Considerations” for more information regarding circuit layout. 3.3 Chip Select/Shutdown (CS/SHDN) The CS/SHDN pin is used to initiate communication with the device when pulled low. This pin will end a conversion and put the device in low-power standby when pulled high. The CS/SHDN pin must be pulled high between conversions and cannot be tied low for multiple conversions. See Figure 6-2 for serial communication protocol.  2011 Microchip Technology Inc. 3.5 3.6 Serial Data Output (DOUT) Serial Clock (CLK) The SPI clock pin is used to initiate a conversion, as well as to clock out each bit of the conversion as it takes place. See Section 5.2 “Driving the Analog Input” for constraints on clock speed, and Figure 6-2 for serial communication protocol. DS21697F-page 13 MCP3302/04 3.7 Analog Ground (AGND) Ground connection to internal analog circuitry. To ensure accuracy, this pin must be connected to the same ground as DGND. If an analog ground plane is available, it is recommended that this device be tied to the analog ground plane in the circuit. See Section 5.6 “Layout Considerations” for more information regarding circuit layout. 3.8 3.9 Power Supply (VDD) The device can operate from 2.7V to 5.5V, but the data conversion performance is from 4.5V to 5.5V supply range. To ensure accuracy, a 0.1 µF ceramic bypass capacitor should be placed as close as possible to the pin. See Section 5.6 “Layout Considerations” for more information regarding circuit layout. Voltage Reference (VREF) This input pin provides the reference voltage for the device, which determines the maximum range of the analog input signal and the LSB size. The LSB size is determined according to the equation shown below. As the reference input is reduced, the LSB size is reduced accordingly. EQUATION 3-1: LSB Size = 2 x VREF 8192 When using an external voltage reference device, the system designer should always refer to the manufacturer’s recommendations for circuit layout. Any instability in the operation of the reference device will have a direct effect on the accuracy of the ADC conversion results. DS21697F-page 14  2011 Microchip Technology Inc. MCP3302/04 4.0 DEFINITION OF TERMS Bipolar Operation - This applies to either a differential or single-ended input configuration, where both positive and negative codes are output from the A/D converter. Full bipolar range includes all 8192 codes. For bipolar operation on a single-ended input signal, the A/D converter must be configured to operate in pseudo differential mode. Unipolar Operation - This applies to either a singleended or differential input signal where only one side of the device transfer is being used. This could be either the positive or negative side, depending on which input (IN+ or IN-) is being used for the DC bias. Full unipolar operation is equivalent to a 12-bit converter. Full Differential Operation - Applying a full differential signal to both the IN(+) and IN(-) inputs is referred to as full differential operation. This configuration is described in Figure 1-5. Pseudo-Differential Operation - Applying a singleended signal to only one of the input channels with a bipolar output is referred to as pseudo differential operation. To obtain a bipolar output from a singleended input signal the inverting input of the A/D converter must be biased above VSS. This operation is described in Figure 1-6. Integral Nonlinearity - The maximum deviation from a straight line passing through the endpoints of the bipolar transfer function is defined as the maximum integral nonlinearity error. The endpoints of the transfer function are a point 1/2 LSB above the first code transition (0x1000) and 1/2 LSB below the last code transition (0x0FFF). Differential Nonlinearity - The difference between two measured adjacent code transitions and the 1 LSB ideal is defined as differential nonlinearity. Positive Gain Error - This is the deviation between the last positive code transition (0x0FFF) and the ideal voltage level of VREF-1/2 LSB, after the bipolar offset error has been adjusted out. Negative Gain Error - This is the deviation between the last negative code transition (0X1000) and the ideal voltage level of -VREF-1/2 LSB, after the bipolar offset error has been adjusted out. Offset Error - This is the deviation between the first positive code transition (0x0001) and the ideal 1/2 LSB voltage level. Acquisition Time - The acquisition time is defined as the time during which the internal sample capacitor is charging. This occurs for 1.5 clock cycles of the external CLK as defined in Figure 6-2. Conversion Time - The conversion time occurs immediately after the acquisition time. During this time, successive approximation of the input signal occurs as the 13-bit result is being calculated by the internal circuitry. This occurs for 13 clock cycles of the external CLK as defined in Figure 6-2.  2011 Microchip Technology Inc. Signal-to-Noise Ratio - Signal-to-Noise Ratio (SNR) is defined as the ratio of the signal-to-noise measured at the output of the converter. The signal is defined as the rms amplitude of the fundamental frequency of the input signal. The noise value is dependant on the device noise as well as the quantization error of the converter and is directly affected by the number of bits in the converter. The theoretical signal-to-noise ratio limit based on quantization error only for an N-bit converter is defined as: EQUATION 4-1: SNR =  6.02N + 1.76 dB For a 13-bit converter, the theoretical SNR limit is 80.02 dB. Total Harmonic Distortion - Total Harmonic Distortion (THD) is the ratio of the rms sum of the harmonics to the fundamental, measured at the output of the converter. For the MCP3302/04, it is defined using the first 9 harmonics, as is shown in the following equation: EQUATION 4-2: 2 2 2 2 2 V 2 + V 3 + V 4 + ..... + V 8 + V 9 THD(-dB) = – 20 log ------------------------------------------------------------------------------2 V1 Here V1 is the rms amplitude of the fundamental and V2 through V9 are the rms amplitudes of the second through ninth harmonics. Signal-to-Noise plus Distortion (SINAD) - Numerically defined, SINAD is the calculated combination of SNR and THD. This number represents the dynamic performance of the converter, including any harmonic distortion. EQUATION 4-3: SINAD(dB) = 20 log 10  SNR  10  + 10 –  THD  10  EffectIve Number of Bits - Effective Number of Bits (ENOB) states the relative performance of the ADC in terms of its resolution. This term is directly related to SINAD by the following equation: EQUATION 4-4: SINAD – 1.76 ENOB  N  = -----------------------------------6.02 For SINAD performance of 78 dB, the effective number of bits is 12.66. Spurious Free Dynamic Range - Spurious Free Dynamic Range (SFDR) is the ratio of the rms value of the fundamental to the next largest component in the output spectrum of the ADC. This is, typically, the first harmonic, but could also be a noise peak. DS21697F-page 15 MCP3302/04 NOTES: DS21697F-page 16  2011 Microchip Technology Inc. MCP3302/04 5.0 APPLICATIONS INFORMATION 5.2 5.1 Conversion Description The analog input of the MCP3302/04 is easily driven, either differentially or single ended. Any signal that is common to the two input channels will be rejected by the common mode rejection of the device. During the charging time of the sample capacitor, a small charging current will be required. For low-source impedances, this input can be driven directly. For larger source impedances, a larger acquisition time will be required, due to the RC time constant that includes the source impedance. For the A/D Converter to meet specification, the charge holding capacitor (CSAMPLE) must be given enough time to acquire a 13-bit accurate voltage level during the 1.5 clock cycle acquisition period. The MCP3302/04 A/D converter employ a conventional SAR architecture. With this architecture, the potential between the IN+ and IN- inputs are simultaneously sampled and stored with the internal sample circuits for 1.5 clock cycles (tACQ). Following this sampling time, the input hold switches of the converter open and the device uses the collected charge to produce a serial 13-bit binary two’s complement output code. This conversion process is driven by the external clock and must include 13 clock cycles, one for each bit. During this process, the most significant bit (MSB) is output first. This bit is the sign bit and indicates whether the IN+ input or the IN- input is at a higher potential. CDAC Hold CSAMP + Comp CSAMP INHold 13-Bit SAR Shift Register DOUT FIGURE 5-1: An analog input model is shown in Figure 5-3. This model is accurate for an analog input, regardless of whether it is configured as a single-ended input, or the IN+ and IN- input in differential mode. In this diagram, it is shown that the source impedance (RS) adds to the internal sampling switch (RSS) impedance, directly affecting the time that is required to charge the capacitor (CSAMPLE). Consequently, a larger source impedance with no additional acquisition time increases the offset, gain, and integral linearity errors of the conversion. To overcome this, a slower clock speed can be used to allow for the longer charging time. Figure 5-2 shows the maximum clock speed associated with source impedances. Simplified Block Diagram. Maximum Clock Frequency (MHz) IN+ Driving the Analog Input 2.5 2.0 1.5 1.0 0.5 0.0 100 1000 10000 100000 Source Resistance (ohms) FIGURE 5-2: Maximum Clock Frequency vs. Source Resistance (RS) to maintain ±1 LSB INL.  2011 Microchip Technology Inc. DS21697F-page 17 MCP3302/04 VDD RS VT = 0.6V CHx CPIN 7 pF VA Sampling Switch VT = 0.6V SS RSS = 1 k CSAMPLE = DAC capacitance = 25 pF ILEAKAGE ±1 nA VSS Legend VA RS CHx CPIN VT ILEAKAGE SS RSS CSAMPLE = = = = = = = = = FIGURE 5-3: 5.2.1 signal source source impedance input channel pad input pin capacitance threshold voltage leakage current at the pindue to various junctions sampling switch sampling switch resistor sample/hold capacitance Analog Input Model. MAINTAINING MINIMUM CLOCK SPEED When the MCP3302/04 initiates, charge is stored on the sample capacitor. When the sample period is complete, the device converts one bit for each clock that is received. It is important for the user to note that a slow clock rate will allow charge to bleed off the sample capacitor while the conversion is taking place. For the MCP330X devices, the recommended minimum clock speed during the conversion cycle (TCONV) is 105 kHz. Failure to meet this criteria may induce linearity errors into the conversion outside the rated specifications. It should be noted that during the entire conversion cycle, the A/D converter does not have requirements for clock speed or duty cycle, as long as all timing specifications are met. 5.3 Using the values in Figure 5-4, we have a 100 Hz corner frequency. See Figure 5-2 for relation between input impedance and acquisition time. VDD = 5V 0.1 µF C 10 µF IN+ VIN 1 k R IN- MCP330X VREF Biasing Solutions For pseudo-differential bipolar operation, the biasing circuit shown in Figure 5-4 shows a single-ended input AC coupled to the converter. This configuration will give a digital output range of -4096 to +4095. With the 2.5V reference, the LSB size equal to 610 µV. Although the ADC is not production tested with a 2.5V reference as shown, linearity will not change more than 0.1 LSB. See Figure 2-2 and Figure 2-6 for INL and DNL errors versus VREF at VDD = 5V. A trade-off exists between the high-pass corner and the acquisition time. The value of C will need to be quite large in order to bring down the high-pass corner. The value of R needs to be 1 kΩ, or less, since higher input impedances require additional acquisition time. DS21697F-page 18 VOUT 1 µF VIN MCP1525 0.1 µF FIGURE 5-4: Pseudo-differential biasing circuit for bipolar operation.  2011 Microchip Technology Inc. MCP3302/04 Using an external operation amplifier on the input allows for gain and also buffers the input signal from the input to the ADC allowing for a higher source impedance. This circuit is shown in Figure 5-5. VDD = 5V 10 k 1 k VIN 0.1 µF MCP6021 1 µF + IN+ IN- 1 M MCP330X VREF 5.4 Common Mode Input Range The common mode input range has no restriction and is equal to the absolute input voltage range: VSS -0.3V to VDD + 0.3V. However, for a given VREF, the common mode voltage has a limited swing, if the entire range of the A/D converter is to be used. Figure 5-7 and Figure 5-8 show the relationship between VREF and the common mode voltage swing. A smaller VREF allows for wider flexibility in a common mode voltage. VREF levels, down to 400 mV, exhibit less than 0.1 LSB change in INL and DNL. For characterization graphs that show this performance relationship, see Figure 2-2 and Figure 2-6. 1 µF VOUT VIN MCP1525 0.1 µF FIGURE 5-5: Adding an amplifier allows for gain and also buffers the input from any highimpedance sources. This circuit shows that some headroom will be lost due to the amplifier output not being able to swing all the way to the rail. An example would be for an output swing of 0V to 5V. This limitation can be overcome by supplying a VREF that is slightly less than the common mode voltage. Using a 2.048V reference for the A/D converter while biasing the input signal at 2.5V solves the problem. This circuit is shown in Figure 5-6. Common Mode Range (V) VDD = 5V 5 4.05V 4 2.8V 3 2 2.3V 1 0.95V 0 -1 0.25 1.0 2.5 VREF(V) 4.0 5.0 FIGURE 5-7: Common Mode Input Range of Full Differential Input Signal versus VREF. VDD = 5V 10 k MCP606 VIN + 1 µF 1 M 0.1 µF 1 k IN+ IN- MCP330X VREF 10 k VOUT VIN MCP1525 5 4.05V 4 2.8V 3 2 2.3V 1 0.95V 0 -1 0.25 2.048V 1 µF Common Mode Range (V) VDD = 5V 0.5 1.25 2.0 2.5 VREF (V) 0.1 µF FIGURE 5-8: Common Mode Input Range versus VREF for Pseudo Differential Input. FIGURE 5-6: Circuit solution to overcome amplifier output swing limitation.  2011 Microchip Technology Inc. DS21697F-page 19 MCP3302/04 5.5 Buffering/Filtering the Analog Inputs Inaccurate conversion results may occur if the signal source for the A/D converter is not a low-impedance source. Buffering the input will overcome the impedance issue. It is also recommended that an analog filter be used to eliminate any signals that may be aliased back into the conversion results. This is illustrated in Figure 5-9, where an op amp is used to drive the analog input of the MCP3302/04. This amplifier provides a low-impedance source for the converter input and a low-pass filter, which eliminates unwanted high-frequency noise. Values shown are for a 10 Hz Butterworth Low-Pass filter. Low-pass (anti-aliasing) filters can be designed using Microchip’s interactive FilterLab® software. FilterLab will calculate capacitor and resistor values, as well as determine the number of poles that are required for the application. For more detailed information on filtering signals, see AN699 “Anti-Aliasing, Analog Filters for Data Acquisition Systems”, at www.microchip.com. 5.6 Layout Considerations When laying out a printed circuit board for use with analog components, care should be taken to reduce noise wherever possible. A bypass capacitor from VDD to ground should always be used with this device and should be placed as close as possible to the device pin. A bypass capacitor value of 0.1 µF is recommended. Digital and analog traces on the board should be separated as much as possible, with no traces running underneath the device or the bypass capacitor. Extra precautions should be taken to keep traces with highfrequency signals (such as clock lines) as far as possible from analog traces. Use of an analog ground plane is recommended in order to keep the ground potential the same for all devices on the board. Providing VDD connections to devices in a “star” configuration can also reduce noise by eliminating current return paths and associated errors (see Figure 5-10). Layout tips for using the MCP3302, MCP3304, or other ADC devices, are available in AN688, “Layout Tips for 12-Bit A/D Converter Applications”, from www.microchip.com. VDD 10 µF 4.096V Reference 0.1 µF MCP1541 VDD Connection 1 µF CL VREF IN+ 0.1 µF MCP330X 7.86 k VIN 2.2 µF 14.6 k 1 µF MCP601 + Device 4 IN- - FIGURE 5-9: The MCP601 Operational Amplifier is used to implement a 2nd order antialiasing filter for the signal being converted by the MCP3302/04. Device 1 Device 3 Device 2 FIGURE 5-10: VDD traces arranged in a ‘Star’ configuration in order to reduce errors caused by current return paths. DS21697F-page 20  2011 Microchip Technology Inc. MCP3302/04 5.7 Utilizing the Digital and Analog Ground Pins The MCP3302/04 devices provide both digital and analog ground connections to provide another means of noise reduction. As shown in Figure 5-11, the analog and digital circuitry are separated internal to the device. This reduces noise from the digital portion of the device being coupled into the analog portion of the device. The two grounds are connected internally through the substrate which has a resistance of 5 -10Ω. If no ground plane is utilized, then both grounds must be connected to VSS on the board. If a ground plane is available, both digital and analog ground pins should be connected to the analog ground plane. If both an analog and a digital ground plane are available, both the digital and the analog ground pins should be connected to the analog ground plane, as shown in Figure 5-11. Following these steps will reduce the amount of digital noise from the rest of the board being coupled into the A/D Converter. VDD MCP3302/04 Digital Side -SPI Interface -Shift Register -Control Logic Analog Side -Sample Cap -Capacitor Array -Comparator Substrate 5 - 10 DGND AGND 0.1 µF Analog Ground Plane FIGURE 5-11: Separation of Analog and Digital Ground Pins.MCP3302/04.  2011 Microchip Technology Inc. DS21697F-page 21 MCP3302/04 NOTES: DS21697F-page 22  2011 Microchip Technology Inc. MCP3302/04 6.0 SERIAL COMMUNICATIONS 6.1 Output Code Format The output code format is a binary two’s complement scheme, with a leading sign bit that indicates the sign of the output. If the IN+ input is higher than the INinput, the sign bit will be a zero. If the IN- input is higher, the sign bit will be a ‘1’. The diagram shown in Figure 6-1 shows the output code transfer function. In this diagram, the horizontal axis is the analog input voltage and the vertical axis is the output code of the ADC. It shows that when IN+ is equal to IN-, both the sign bit and the data word is zero. As IN+ gets larger with respect to IN-, the sign bit is a zero and the data word gets larger. The full scale output code is reached at +4095 when the input [(IN+) - (IN-)] reaches VREF - 1 LSB. When IN- is larger than IN+, the two’s complement output codes will be seen with the sign bit being a one. Some examples of analog input levels and corresponding output codes are shown in Table 6-1. TABLE 6-1: BINARY TWO’S COMPLEMENT OUTPUT CODE EXAMPLES. Sign Bit Binary Data Decimal DATA (IN+)-(IN-)=VREF-1 LSB 0 1111 1111 1111 +4095 (IN+)-(IN-) = VREF-2 LSB 0 1111 1111 1110 +4094 IN+ = (IN-) +2 LSB 0 0000 0000 0010 +2 IN+ = (IN-) +1 LSB 0 0000 0000 0001 +1 IN+ = IN- 0 0000 0000 0000 0 IN+ = (IN-) - 1 LSB 1 1111 1111 1111 -1 IN+ = (IN-) - 2 LSB 1 1111 1111 1110 -2 IN+ - 1 0000 0000 0001 -4095 1 0000 0000 0000 -4096 Analog Input Levels Full Scale Positive Full Scale Negative IN- = -VREF +1 LSB IN+ - IN- = -VREF  2011 Microchip Technology Inc. DS21697F-page 23 MCP3302/04 Output Code Positive Full Scale Output = VREF -1 LSB 0 + 1111 1111 1111 (+4095) 0 + 1111 1111 1110 (+4094) 0 + 0000 0000 0011 (+3) 0 + 0000 0000 0010 (+2) 0 + 0000 0000 0001 (+1) IN+ > IN- 0 + 0000 0000 0000 (0) IN+ < IN- -VREF 1 + 1111 1111 1111 (-1) 1 + 1111 1111 1110 (-2) Analog Input Voltage IN+ - IN- VREF 1 + 1111 1111 1101 (-3) 1 + 0000 0000 0001 (-4095) Negative Full Scale Output = -VREF FIGURE 6-1: 6.2 1 + 0000 0000 0000 (-4096) Output Code Transfer Function. Communicating with the MCP3302 and MCP3304 Communication with the MCP3302/04 devices is done using a standard SPI-compatible serial interface. Initiating communication with either device is done by bringing the CS line low (see Figure 6-2). If the device was powered up with the CS pin low, it must be brought high and back low to initiate communication. The first clock received with CS low and DIN high will constitute a start bit. The SGL/DIFF bit follows the start bit and will determine if the conversion will be done using singleended or differential input mode. Each channel in Single-ended mode will operate as a 12-bit converter with a unipolar output. No negative codes will be output in Single-ended mode. The next three bits (D0, D1, and D2) are used to select the input channel configuration. Table 6-1 and Table 6-2 show the configuration bits for the MCP3302 and MCP3304, respectively. The device will begin to sample the analog input on the fourth rising edge of the clock after the start bit has been received. The sample period will end on the falling edge of the fifth clock following the start bit. clocks will output the result of the conversion with the sign bit first, followed by the 12 remaining data bits, as shown in Figure 6-2. Note that if the device is operating in the Single-ended mode, the sign bit will always be transmitted as a ‘0’. Data is always output from the device on the falling edge of the clock. If all 13 data bits have been transmitted, and the device continues to receive clocks while the CS is held low, the device will output the conversion result, LSB, first, as shown in Figure 6-3. If more clocks are provided to the device while CS is still low (after the LSB first data has been transmitted), the device will clock out zeros indefinitely. If necessary, it is possible to bring CS low and clock in leading zeros on the DIN line before the start bit. This is often done when dealing with microcontroller-based SPI ports that must send 8 bits at a time. Refer to Section 6.3 “Using the MCP3302/04 with Microcontroller (MCU) SPI Ports” for more details on using the MCP3302/04 devices with hardware SPI ports. After the D0 bit is input, one more clock is required to complete the sample and hold period (DIN is a “don’t care” for this clock). On the falling edge of the next clock, the device will output a low null bit. The next 13 DS21697F-page 24  2011 Microchip Technology Inc. MCP3302/04 TABLE 6-1: CONFIGURATION BITS FOR THE MCP3302 Control Bit Selections Single D2* D1 /Diff D0 Input Configuration Channel Selection TABLE 6-2: CONFIGURATION BITS FOR THE MCP3304 Control Bit Selections Single /Diff D2 D1 D0 Input Configuration Channel Selection 1 X 0 0 single ended CH0 1 0 0 0 single ended CH0 1 X 0 1 single ended CH1 1 0 0 1 single ended CH1 1 X 1 0 single ended CH2 1 0 1 0 single ended CH2 1 X 1 1 single ended CH3 1 0 1 1 single ended CH3 0 X 0 0 differential CH0 = IN+ CH1 = IN- 1 1 0 0 single ended CH4 1 1 0 1 single ended CH5 0 X 0 1 differential CH0 = INCH1 = IN+ 1 1 1 0 single ended CH6 0 X 1 0 differential CH2 = IN+ CH3 = IN- 1 1 1 1 single ended CH7 0 0 0 0 differential 0 X 1 1 differential CH2 = INCH3 = IN+ CH0 = IN+ CH1 = IN- 0 0 0 1 differential CH0 = INCH1 = IN+ 0 0 1 0 differential CH2 = IN+ CH3 = IN- 0 0 1 1 differential CH2 = INCH3 = IN+ 0 1 0 0 differential CH4 = IN+ CH5 = IN- 0 1 0 1 differential CH4 = INCH5 = IN+ 0 1 1 0 differential CH6 = IN+ CH7 = IN- 0 1 1 1 differential CH6 = INCH7 = IN+ *D2 is don’t care for MCP3302  2011 Microchip Technology Inc. DS21697F-page 25 MCP3302/04 TSAMPLE TSAMPLE TCSH CS TSUCS CLK Start SGL/ D2 D1 D0 DIFF DIN HI-Z DOUT Start SGL/ DIFF Don’t Care Null SB† B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 * Bit D2 HI-Z TCONV TACQ TDATA ** * After completing the data transfer, if further clocks are applied with CS low, the A/D Converter will output LSB first data, followed by zeros indefinitely. See Figure 6-3 below. ** TDATA: during this time, the bias current and the comparator power down while the reference input becomes a high-impedance node, leaving the CLK running to clock out the LSB-first data or zeros. † When operating in Single-ended mode, the sign bit will always be transmitted as a ‘0’. FIGURE 6-2: Communication with MCP3302/04 (MSB first Format). TSAMPLE TCSH CS TSUCS Power Down CLK Start DIN D2 D1 D0 Don’t Care SGL/ DIFF DOUT HI-Z Null Bit SB† B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 SB* HI-Z (MSB) TACQ TCONV TDATA ** * After completing the data transfer, if further clocks are applied with CS low, the A/D Converter will output zeros indefinitely. ** TDATA: During this time, the bias circuit and the comparator power down while the reference input becomes a high-impedance node, leaving the CLK running to clock out LSB first data or zeroes. † When operating in Single-ended mode, the sign bit will always be transmitted as a ‘0’. FIGURE 6-3: DS21697F-page 26 Communication with MCP3302/04 (LSB first Format).  2011 Microchip Technology Inc. MCP3302/04 6.3 Using the MCP3302/04 with Microcontroller (MCU) SPI Ports As shown in Figure 6-4, the first byte transmitted to the A/D Converter contains 6 leading zeros before the start bit. Arranging the leading zeros this way produces the 13 data bits to fall in positions easily manipulated by the MCU. The sign bit is clocked out of the A/D Converter on the falling edge of clock number 11, followed by the remaining data bits (MSB first). After the second eight clocks have been sent to the device, the MCU receive buffer will contain 2 unknown bits (the output is at highimpedance for the first two clocks), the null bit, the sign bit, and the 4 highest order bits of the conversion. After the third byte has been sent to the device, the receive register will contain the lowest order eight bits of the conversion results. Easier manipulation of the converted data can be obtained by using this method. With most microcontroller SPI ports, it is required to send groups of eight bits. It is also required that the microcontroller SPI port be configured to clock out data on the falling edge of clock and latch data in on the rising edge. Because communication with the MCP3302 and MCP3304 devices may not need multiples of eight clocks, it will be necessary to provide more clocks than are required. This is usually done by sending ‘leading zeros’ before the start bit. For example, Figure 6-4 and Figure 6-5 show how the MCP3302/04 devices can be interfaced to a MCU with a hardware SPI port. Figure 6-4 depicts the operation shown in SPI Mode 0,0, which requires that the SCLK from the MCU idles in the ‘low’ state, while Figure 6-5 shows the similar case of SPI Mode 1,1, where the clock idles in the ‘high’ state. CS Figure 6-5 shows the same situation in SPI Mode 1,1, which requires that the clock idles in the high state. As with mode 0,0, the A/D Converter outputs data on the falling edge of the clock and the MCU latches data from the A/D Converter in on the rising edge of the clock. MCU latches data from A/D Converter on rising edges of SCLK SCLK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 B3 B2 B1 B0 Data is clocked out of A/D Converter on falling edges Start SGL/ D2 DIFF DIN DOUT D1 Don’t Care D0 HI-Z NULL SB B11 B10 B9 BIT B8 B7 B6 B5 B4 X X X Start Bit MCU Transmitted Data 1 SGL/ D2 D1 (Aligned with falling 0 0 0 0 DIFF edge of clock) MCU Received Data ? ? ? ? ? ? ? ? (Aligned with rising edge of clock) ? = Unknown Bits X = Don’t Care Bits Data stored into MCU receive register after transmission of first 8 bits DO ? X X X X X 0 SB B11 B10 B9 ? (Null) X X B8 Data stored into MCU receive register after transmission of second 8 bits B7 B6 B5 X B4 X B3 X B2 X B1 X B0 Data stored into MCU receive register after transmission of last 8 bits FIGURE 6-4: SPI Communication with the MCP3302/04 using 8-bit segments (Mode 0,0: SCLK idles low).  2011 Microchip Technology Inc. DS21697F-page 27 MCP3302/04 CS SCLK MCU latches data from A/D Converter on rising edges of SCLK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 Data is clocked out of A/D Converter on falling edges Start DIN D1 Don’tCare Care Don’t D0 NULL SB B11 B10 B9 BIT B8 B7 B6 B5 B4 B3 B2 B1 B0 X X X X X X X X Start Bit MCU Transmitted Data (Aligned with falling 0 edge of clock) ? = Unknown Bits X = Don’t Care Bits D2 HI-Z DOUT MCU Received Data (Aligned with rising edge of clock) SGL/ DIFF 0 ? 0 ? 0 ? SGL/ DIFF 1 ? ? ? D1 D2 ? DO ? Data stored into MCU receive register after transmission of first 8 bits X X ? ? X 0 (Null) X X X SB B11 B10 B9 X B8 Data stored into MCU receive register after transmission of second 8 bits B7 B6 B5 B4 B3 B2 B1 B0 Data stored into MCU receive register after transmission of last 8 bits FIGURE 6-5: SPI Communication with the MCP3302/04 using 8-bit segments (Mode 1,1: SCLK idles high). DS21697F-page 28  2011 Microchip Technology Inc. MCP3302/04 7.0 PACKAGING INFORMATION 7.1 Package Marking Information 14-Lead PDIP (300 mil) Example: XXXXXXXXXXXXXX XXXXXXXXXXXXXX YYWWNNN 14-Lead SOIC (150 mil) MCP3302-B I/P^^ e3 1112256 Example: XXXXXXXXXXX XXXXXXXXXXX YYWWNNN 14-Lead TSSOP (4.4mm) XXXXXXXX XYWW NNN Legend: XX...X Y YY WW NNN e3 * Note: MCP3302-B e3 I/SL^^ 1112256 Example: 3302-C I112 256 Customer-specific information Year code (last digit of calendar year) Year code (last 2 digits of calendar year) Week code (week of January 1 is week ‘01’) Alphanumeric traceability code Pb-free JEDEC designator for Matte Tin (Sn) This package is Pb-free. The Pb-free JEDEC designator ( e3 ) can be found on the outer packaging for this package. In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information.  2011 Microchip Technology Inc. DS21697F-page 29 MCP3302/04 7.2 Package Marking Information (Continued) 16-Lead PDIP (300 mil) Example: XXXXXXXXXXXXXX XXXXXXXXXXXXXX YYWWNNN 16-Lead SOIC (150 mil) XXXXXXXXXXXXX XXXXXXXXXXXXX YYWWNNN DS21697F-page 30 MCP3304-B I/P e3 1112256 Example: MCP3304-B XXXIIXXXXXXX I/SL e3 1112256  2011 Microchip Technology Inc. MCP3302/04                 3 %& %! %4" ) '  % 4$%  %"% %%255)))&  &54 N NOTE 1 E1 1 3 2 D E A2 A L A1 c b1 b e eB 6% &  9&% 7!&(  $ 7+8- 7 7 7: ;  %  % %  < 1+ <   ""4 4  0 , 0 1 % %  0 < <  !" %  !" ="% -  , ,0  ""4="% -  0 > : 9%  ,0 0 0 % % 9 0 , 0 9" 4  >  0 6 9"="% ( 0 ?  9 ) 9"="% (  >  :  )* 1 < < ,     !"#$%! & '(!%&! %( %")%%%"   *$%+ %  % , &   "-"  %!"& "$   % !    "$   % !     %#".  "  &  "%   -/0 1+21 &    %#%!  ))% !%%          ) +01  2011 Microchip Technology Inc. DS21697F-page 31 MCP3302/04 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS21697F-page 32  2011 Microchip Technology Inc. MCP3302/04 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2011 Microchip Technology Inc. DS21697F-page 33 MCP3302/04   3 %& %! %4" ) '  % 4$%  %"% %%255)))&  &54 DS21697F-page 34  2011 Microchip Technology Inc. MCP3302/04 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2011 Microchip Technology Inc. DS21697F-page 35 MCP3302/04 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS21697F-page 36  2011 Microchip Technology Inc. MCP3302/04 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2011 Microchip Technology Inc. DS21697F-page 37 MCP3302/04 !                3 %& %! %4" ) '  % 4$%  %"% %%255)))&  &54 N NOTE 1 E1 1 2 3 D E A A2 L A1 c b1 b e eB 6% &  9&% 7!&(  $ 7+8- 7 7 7: ; ? %  % %  < 1+ <   ""4 4  0 , 0 1 % %  0 < <  !" %  !" ="% -  , ,0  ""4="% -  0 > : 9%  ,0 00 0 % % 9 0 , 0 9" 4  >  0 6 9"="% ( 0 ?  9 ) 9"="% (  >  :  )* 1 < < ,     !"#$%! & '(!%&! %( %")%%%"   *$%+ %  % , &   "-"  %!"& "$   % !    "$   % !     %#".  "  &  "%   -/0 1+2 1 &    %#%!  ))% !%%          ) +1 DS21697F-page 38  2011 Microchip Technology Inc. MCP3302/04 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2011 Microchip Technology Inc. DS21697F-page 39 MCP3302/04 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS21697F-page 40  2011 Microchip Technology Inc. MCP3302/04 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2011 Microchip Technology Inc. DS21697F-page 41 MCP3302/04 NOTES: DS21697F-page 42  2011 Microchip Technology Inc. MCP3302/04 APPENDIX A: REVISION HISTORY Revision F (April 2011) The following is the list of modifications: 1. 2. Updated content to designate that the devices now have tested specifications in the 4.5V to 5.5V supply range. Removed figures 2.4 to 2.6, 2.10 to 2.12, 2.16 and 2.17 in Section 2.0 “Typical Performance Curves”. Revision E (December 2008) The following is the list of modifications: Update to Package Outline Drawings. Revision D (December 2007) The following is the list of modifications: Update to Package Outline Drawings. Revision C (January 2007) The following is the list of modifications: Update to Package Outline Drawings. Revision B (February 2002) The following is the list of modifications: Undocumented Changes. Revision A (November 2001) Original Release of this Document.  2011 Microchip Technology Inc. DS21697F-page 43 MCP3302/04 NOTES: DS21697F-page 44  2011 Microchip Technology Inc. MCP3302/04 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, contact the local Microchip sales office. PART NO. -X X /XX Device Grade Temperature Range Package Examples: a) b) Device Grade: MCP3302: MCP3302T: MCP3304: MCP3304T: B C Temperature Range I Package P SL ST 13-Bit Serial A/D Converter 13-Bit Serial A/D Converter (Tape and Reel) 13-Bit Serial A/D Converter 13-Bit Serial A/D Converter (Tape and Reel) = ±1 LSB INL = ±2 LSB INL = -40C to c) a) +85C (Industrial) b) = Plastic DIP (300 mil Body), 14-lead, 16-lead = Plastic SOIC (150 mil Body), 14-lead, 16-lead = Plastic TSSOP (4.4mm), 14-lead  2011 Microchip Technology Inc. MCP3302-BI/P: ±1 LSB INL, Industrial Temperature, 14-LD PDIP package MCP3302-BI/SL: ±1 LSB INL, Industrial Temperature, 14-LD SOIC package MCP3302-CI/ST: ±2 LSB INL, Industrial Temperature, 14-LD TSSOP package MCP3304-BI/P: ±1 LSB INL, Industrial Temperature, 16-LD PDIP package MCP3304-BI/SL: ±1 LSB INL, Industrial Temperature, 16-LD SOIC package DS21697F-page 45 MCP3302/04 NOTES: DS21697F-page 46  2011 Microchip Technology Inc. Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. • Microchip is willing to work with the customer who is concerned about the integrity of their code. • Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer’s risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights. Trademarks The Microchip name and logo, the Microchip logo, dsPIC, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART, PIC32 logo, rfPIC and UNI/O are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor, MXDEV, MXLAB, SEEVAL and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. Analog-for-the-Digital Age, Application Maestro, CodeGuard, dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN, ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial Programming, ICSP, Mindi, MiWi, MPASM, MPLAB Certified logo, MPLIB, MPLINK, mTouch, Omniscient Code Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit, PICtail, REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. © 2011, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. ISBN: 978-1-61341-005-9 Microchip received ISO/TS-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company’s quality system processes and procedures are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified.  2011 Microchip Technology Inc. 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