MCP33121-05T-E/MN

MCP33131/21/11-XX 1 Msps/500 kSPS 16/14/12-Bit Single-Ended Input SAR ADC Features Typical Applications • Sample Rate (Throughput): - MCP33131/21/11-10: 1 Msps - MCP33131/21/11-05: 500 kSPS • 16/14/12-Bit Resolution with No Missing Codes • No Latency Output • Wide Operating Voltage Range: - Analog Supply Voltage (AVDD): 1.8V - Digital Input/Output Interface Voltage (DVIO): 1.7V - 5.5V - External Reference (VREF): 2.5V - 5.1V • Pseudo-Differential Input Operation with Single-Ended Configuration: - Input Full-Scale Range: 0V to +VREF • Ultra Low Current Consumption (typical): - During Input Acquisition (Standby): ~ 0.8 µA - During Conversion: • • • • • • • High-Precision Data Acquisition Medical Instruments Test Equipment Electric Vehicle Battery Management Systems Motor Control Applications Switch-Mode Power Supply Applications Battery-Powered Equipment System Design Supports The MCP331x1-XX Evaluation Kit demonstrates the performance of the MCP331x1-XX SAR ADC family devices. The evaluation kit includes: (a) MCP331x1-XX Evaluation Board, (b) PIC32MZ EF Curiosity Board for data collection, and (c) SAR ADC Utility PC GUI. Contact Microchip Technology Inc. for the evaluation tools and the PIC32 MCU firmware example codes. MCP331x1-10: ~1.6 mA Package Types MCP331x1-05: ~1.4 mA VREF 1 • SPI-Compatible Serial Communication: - SCLK Clock Rate: up to 100 MHz • ADC Self-Calibration for Offset, Gain, and Linearity Errors: - During Power-Up (automatic) - On-Demand via user’s command during normal operation • AEC-Q100 Qualified: - Temperature Grade 1: -40°C to +125°C • Package Options: MSOP-10 and TDFN-10 MSOP-10 AVDD 2 TDFN-10 10 DVIO Top View 9 SDI AIN+ 3 AIN- 4 GND 5 8 SCLK 7 SDO 6 CNVST VREF 1 10 DVIO AVDD 2 Top View 9 SDI AIN+ 3 8 SCLK AIN- 4 7 SDO 6 CNVST GND 5 MCP331x1-XX Device Offering (Note 1): Part Number Resolution Sample Rate MCP33131-10 16-bit 1 Msps Single-Ended MCP33121-10 14-bit 1 Msps Single-Ended Input Type Input Range Performance (Typical) SNR (dBFS) SFDR (dB) THD (dB) INL (LSB) DNL (LSB) 0V to 5.1V 86.7 98.9 -97.4 ±2.2 ±0.9 0V to 5.1V 83.5 98.8 -97.2 ±0.55 ±0.25 ±0.06 MCP33111-10 12-bit 1 Msps Single-Ended 0V to 5.1V 73.8 95.9 -93.7 ±0.12 MCP33131-05 16-bit 500 kSPS Single-Ended 0V to 5.1V 86.7 98.9 -97.4 ±2.2 ±0.9 MCP33121-05 14-bit 500 kSPS Single-Ended 0V to 5.1V 83.5 98.8 -97.2 ±0.55 ±0.25 MCP33111-05 12-bit 500 kSPS Single-Ended 0V to 5.1V 73.8 95.9 -93.7 ±0.12 ±0.06 Note 1: SNR, SFDR, and THD are measured with fIN = 10 kHz, VIN = -1 dBFS, VREF = 5.1V.  2018 Microchip Technology Inc. DS20006122A-page 1 MCP33131/21/11-XX Application Diagram 2.5V to 5.1V 1.8V 1.7V to 5.5V VREF AVDD DVIO 22Ω Analog Input 1.7 nF (0V to VREF) Ground Reference of Analog Input Description MCP33131/MCP33121/MCP33111-10 MCP33131/MCP33121/MCP33111-05 The and are single-ended 16, 14, and 12-bit, single-channel 1 Msps and 500 kSPS ADC family devices, respectively, featuring low power consumption and high performance, using a successive approximation register (SAR) architecture. The device operates with a 2.5V to 5.1V external reference (VREF), which supports a wide range of input full-scale range from 0V to VREF. The reference voltage setting is independent of the analog supply voltage (AVDD) and is higher than AVDD. The conversion output is available through an easy-to-use simple SPIcompatible 3-wire interface. The device requires a 1.8V analog supply voltage (AVDD) and a 1.7V to 5.5V digital I/O interface supply voltage (DVIO). The wide digital I/O interface supply (DVIO) range (1.7V - 5.5V) allows the device to interface with most host devices (Master) available in the current industry such as the PIC32 microcontrollers, without using external voltage level shifters. AIN+ MCP331x1-XX AINGND SDI CNVST SCLK Host Device (PIC32MZ) SDO During Standby, most of the internal analog circuitry is shutdown in order to reduce current consumption. Typically, the device consumes less than 1 µA during Standby. A new conversion is started on the rising edge of CNVST. When the conversion is complete and the host lowers CNVST, the output data is presented on SDO, and the device enters Standby to begin acquiring the next input sample. The user can clock out the ADC output data using the SPI-compatible serial clock during Standby. The ADC system clock is generated by an internal on-chip clock, therefore the conversion is performed independent of the SPI serial clock (SCLK). This device can be used for various high-speed and high-accuracy analog-to-digital data conversion applications, where design simplicity, low power, and no output latency are needed. The device is AEC-Q100 qualified for automotive applications and operates over the extended temperature range of -40°C to +125°C. The available package options are Pb-free TDFN-10 and MSOP-10. When the device is first powered-up, it performs a self-calibration to minimize offset, gain and linearity errors. The device performance stays stable across the specified temperature range. However, when extreme changes in the operating environment, such as in the reference voltage, are made with respect to the initial conditions (e.g. the reference voltage was not fully settled during the initial power-up sequence), the user may send a recalibrate command anytime to initiate another self-calibration to restore optimum performance. When the initial power-up sequence is completed, the device enters a low-current input acquisition mode, where sampling capacitors are connected to the input pins. This mode is called Standby. DS20006122A-page 2  2018 Microchip Technology Inc. MCP33131/MCP33121/MCP33111-XX 1.0 KEY ELECTRICAL CHARACTERISTICS 1.1 Absolute Maximum Ratings† †Notice: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. External Analog Supply Voltage (AVDD) ................... -0.3V to 2.0V External Digital Supply Voltage (DVIO) ..................... -0.3V to 5.8V External Reference Voltage (VREF) .......................... -0.3V to 5.8V Analog Inputs w.r.t GND .................... .......... –0.3V to VREF+0.3V Current at Input Pins ...........................................................±2 mA Current at Output and Supply Pins .................................±250 mA Storage Temperature ...........................................-65°C to +150°C Maximum Junction Temperature (TJ) ....... .........................+150°C ESD protection on all pins .... ≤2kV HBM, ≤2kV CDM, ≤200V MM 1.2 Electrical Specifications TABLE 1-1: KEY ELECTRICAL CHARACTERISTICS Electrical Specifications: Unless otherwise specified, all parameters apply for TA = -40°C to +125°C, AVDD = 1.8V, DVIO = 3.3V, VREF = 5V, GND = 0V, Analog Input (VIN) = -1 dBFS sine wave, fIN = 10 kHz, CLOAD_SDO = 20 pF. • MCP331x1-10: Sample Rate (fS) = 1 Msps, SPI Clock Input (SCLK) = 60 MHz. • MCP331x1-05: Sample Rate (fS) = 500 kSPS, SPI Clock Input (SCLK) = 30 MHz. Parameters Sym. Min. Typ. Max. Units Conditions Analog Supply Voltage Range AVDD 1.7 1.8 1.9 V (Note 3) Digital Input/Output Interface Voltage Range DVIO 1.7 — 5.5 V (Note 3) IDDAN — — — 1.6 1.4 0.8 2.4 2.0 — mA mA µA fs = 1 Msps (MCP331x1-10) fs = 500 kSPS (MCP331x1-05) During input acquisition (tACQ) — — — 290 200 30 — — — A A nA fs = 1 Msps (MCP331x1-10) fs = 500 kSPS (MCP331x1-05) During input acquisition (tACQ) 5.1 5.1 V -40°C ≤ TA ≤ 85°C 85°C < TA ≤ 125°C 450 220 240 600 360 — µA µA nA fs = 1 Msps (MCP331x1-10) fs = 500 kSPS (MCP331x1-05) During input acquisition (tACQ) — — — — 6.2 3.1 0.6 2.6 — — — — mW mW mW W Averaged power for tACQ + tCNV — — — 4.2 0.8 2.6 — — — mW mW W Power Supply Requirements Analog Supply Current at AVDD pin: During Conversion During Standby Digital Supply Current At DVDD pin: During Output Data Reading During Standby IDDAN_STBY IIO_DATA IIO_STBY External Reference Voltage Input Reference Voltage (Note 2), (Note 3) Reference Load Current at VREF pin: During Conversion During Standby VREF 2.5 2.7 IREF — — IREF_STBY Total Power Consumption (Including AVDD, DVIO, VREF pins) MCP331x1-10 at 1 Msps at 500 ksps at 100 ksps During Standby PDISS_TOTAL PDISS_STBY During input acquisition (tACQ) MCP331x1-05 at 500 ksps at 100 ksps During Standby Note PDISS_TOTAL PDISS_STBY Averaged power for tACQ + tCNV During input acquisition (tACQ) 1: This parameter is ensured by design and not 100% tested. 2: This parameter is ensured by characterization and not 100% tested. 3: Decoupling capacitor is recommended on the following pins: (a) AVDD pin: 1 F ceramic capacitor, (b) DVIO pin: 0.1 F ceramic capacitor, (c) VREF pin: 10 F tantalum capacitor. 4: PSRR (dB) = -20 log (DVOUT/AVDD), where DVOUT = change in conversion result. 5: ENOB = (SINAD - 1.76)/6.02  2018 Microchip Technology Inc. DS20006122A-page 3 MCP33131/MCP33121/MCP33111-XX TABLE 1-1: KEY ELECTRICAL CHARACTERISTICS (CONTINUED) Electrical Specifications: Unless otherwise specified, all parameters apply for TA = -40°C to +125°C, AVDD = 1.8V, DVIO = 3.3V, VREF = 5V, GND = 0V, Analog Input (VIN) = -1 dBFS sine wave, fIN = 10 kHz, CLOAD_SDO = 20 pF. • MCP331x1-10: Sample Rate (fS) = 1 Msps, SPI Clock Input (SCLK) = 60 MHz. • MCP331x1-05: Sample Rate (fS) = 500 kSPS, SPI Clock Input (SCLK) = 30 MHz. Parameters Sym. Min. Typ. Max. Input Voltage Range VIN+ Input Full-Scale Voltage Range FSR Units Conditions -0.1 — VREF+0.1 V (Note 2) 0 — +VREF VPP (Note 2) CS — 31 — pF (Note 1) BW-3dB — 25 — MHz (Note 1) — 2.5 — ns Time delay between CNVST rising edge and when input is sampled ILEAK_AN_INPUT — ±2 ±200 nA During input acquisition (tACQ) fs — — 1 Msps — — 500 kSPS 16 — — Bits MCP33131-10 and MCP33131-05 14 — — Bits MCP33121-10 and MCP33121-05 12 — — Bits MCP33111-10 and MCP33111-05 -6 ±2.2 +6 LSB MCP33131-10 and MCP33131-05 -1.5 ±0.55 +1.5 LSB MCP33121-10 and MCP33121-05 LSB MCP33111-10 and MCP33111-05 Analog Inputs Input Sampling Capacitance -3dB Input Bandwidth Aperture Delay (Note 1) Leakage Current at Analog Input Pin System Performance Sample Rate (Throughput rate) Resolution (No Missing Codes) Integral Nonlinearity INL ±0.12 Differential Nonlinearity DNL Gain Error GER Gain Error Drift with temperature ±0.9 +1.8 LSB MCP33131-10 and MCP33131-05 -0.8 ±0.25 +0.8 LSB MCP33121-10 and MCP33121-05 -0.3 ±0.06 +0.3 LSB MCP33111-10 and MCP33111-05 ±0.1 ±2.3 mV MCP33131-10 and MCP33131-05 — ±0.125 ±3 mV MCP33121-10 and MCP33121-05 — ±0.8 ±3.66 mV MCP33111-10 and MCP33111-05 — ±0.8 — V/oC — ±4 — LSB — ±1 — LSB MCP33121-10 and MCP33121-05 — ±0.2 — LSB MCP33111-10 and MCP33111-05 — ±0.35 — V/oC Input Common-Mode Rejection Ratio CMRR — 84 — dB Power Supply Rejection Ratio PSRR — 60 — dB Note MCP331x1-05 -0.98 Offset Error Offset Error Drift with Temperature MCP331x1-10 MCP33131-10 and MCP33131-05 (Note 4) 1: This parameter is ensured by design and not 100% tested. 2: This parameter is ensured by characterization and not 100% tested. 3: Decoupling capacitor is recommended on the following pins: (a) AVDD pin: 1 F ceramic capacitor, (b) DVIO pin: 0.1 F ceramic capacitor, (c) VREF pin: 10 F tantalum capacitor. 4: PSRR (dB) = -20 log (DVOUT/AVDD), where DVOUT = change in conversion result. 5: ENOB = (SINAD - 1.76)/6.02 DS20006122A-page 4  2018 Microchip Technology Inc. MCP33131/MCP33121/MCP33111-XX TABLE 1-1: KEY ELECTRICAL CHARACTERISTICS (CONTINUED) Electrical Specifications: Unless otherwise specified, all parameters apply for TA = -40°C to +125°C, AVDD = 1.8V, DVIO = 3.3V, VREF = 5V, GND = 0V, Analog Input (VIN) = -1 dBFS sine wave, fIN = 10 kHz, CLOAD_SDO = 20 pF. • MCP331x1-10: Sample Rate (fS) = 1 Msps, SPI Clock Input (SCLK) = 60 MHz. • MCP331x1-05: Sample Rate (fS) = 500 kSPS, SPI Clock Input (SCLK) = 30 MHz. Parameters Sym. Min. Typ. Max. Units Conditions — 86.8 — — 80.9 — VREF = 2.5V, fIN = 1 kHz 83.5 86.7 — VREF = 5V, fIN = 10 kHz — 80.9 — VREF = 2.5V, fIN = 10 kHz Dynamic Performance Signal-to-Noise Ratio SNR MCP33131-10 and MCP33131-05: 16-bit ADC dBFS VREF = 5V, fIN = 1 kHz MCP33121-10 and MCP33121-05: 14-bit ADC — 83.6 — — 79.8 — dBFS VREF = 2.5V, fIN = 1 kHz VREF = 5V, fIN = 1 kHz 81.5 83.5 — VREF = 5V, fIN = 10 kHz — 79.8 — VREF = 2.5V, fIN = 10 kHz MCP33111-10 and MCP33111-05: 12-bit ADC Signal-to-Noise and Distortion Ratio (Note 5) — 73.8 — — 73.2 — VREF = 2.5V, fIN = 1 kHz 71.1 73.8 — VREF = 5V, fIN = 10 kHz — 73.2 — VREF = 2.5V, fIN = 10 kHz SINAD dBFS VREF = 5V, fIN = 1 kHz MCP33131-10 and MCP33131-05: 16-bit ADC — 86.9 — — 80.9 — dBFS VREF = 2.5V, fIN = 1 kHz VREF = 5V, fIN = 1 kHz — 86.6 — VREF = 5V, fIN = 10 kHz — 80 — VREF = 2.5V, fIN = 10 kHz MCP33121-10 and MCP33121-05: 14-bit ADC — 83.6 — — 79.8 — dBFS VREF = 2.5V, fIN = 1 kHz VREF = 5V, fIN = 1 kHz — 83.4 — VREF = 5V, fIN = 10 kHz — 79.1 — VREF = 2.5V, fIN = 10 kHz MCP33111-10 and MCP33111-05: 12-bit ADC Note — 73.8 — — 73.2 — dBFS VREF = 2.5V, fIN = 1 kHz VREF = 5V, fIN = 1 kHz — 73.8 — VREF = 5V, fIN = 10 kHz — 73 — VREF = 2.5V, fIN = 10 kHz 1: This parameter is ensured by design and not 100% tested. 2: This parameter is ensured by characterization and not 100% tested. 3: Decoupling capacitor is recommended on the following pins: (a) AVDD pin: 1 F ceramic capacitor, (b) DVIO pin: 0.1 F ceramic capacitor, (c) VREF pin: 10 F tantalum capacitor. 4: PSRR (dB) = -20 log (DVOUT/AVDD), where DVOUT = change in conversion result. 5: ENOB = (SINAD - 1.76)/6.02  2018 Microchip Technology Inc. DS20006122A-page 5 MCP33131/MCP33121/MCP33111-XX TABLE 1-1: KEY ELECTRICAL CHARACTERISTICS (CONTINUED) Electrical Specifications: Unless otherwise specified, all parameters apply for TA = -40°C to +125°C, AVDD = 1.8V, DVIO = 3.3V, VREF = 5V, GND = 0V, Analog Input (VIN) = -1 dBFS sine wave, fIN = 10 kHz, CLOAD_SDO = 20 pF. • MCP331x1-10: Sample Rate (fS) = 1 Msps, SPI Clock Input (SCLK) = 60 MHz. • MCP331x1-05: Sample Rate (fS) = 500 kSPS, SPI Clock Input (SCLK) = 30 MHz. Parameters Sym. Spurious Free Dynamic Range SFDR Min. Typ. Max. Units Conditions MCP33131-10 and MCP33131-05: 16-bit ADC — 99.4 — — 94.4 — dBc VREF = 5V, fIN = 1 kHz VREF = 2.5V, fIN = 1 kHz — 98.9 — VREF = 5V, fIN = 10 kHz — 93.9 — VREF = 2.5V, fIN = 10 kHz MCP33121-10 and MCP33121-05: 14-bit ADC — 99.3 — — 94.4 — dBc VREF = 5V, fIN = 1 kHz VREF = 2.5V, fIN = 1 kHz — 98.8 — VREF = 5V, fIN = 10 kHz — 93.9 — VREF = 2.5V, fIN = 10 kHz MCP33111-10 and MCP33111-05: 12-bit ADC Total Harmonic Distortion (first five harmonics) — 97.4 — — 94.2 — VREF = 2.5V, fIN = 1 kHz — 95.9 — VREF = 5V, fIN = 10 kHz — 93.7 — VREF = 2.5V, fIN = 10 kHz THD dBc VREF = 5V, fIN = 1 kHz MCP33131-10 and MCP33131-05: 16-bit ADC — -97.6 — — -92.5 — dBc VREF = 2.5V, fIN = 1 kHz VREF = 5V, fIN = 1 kHz — -97.4 — VREF = 5V, fIN = 10 kHz — -92.4 — VREF = 2.5V, fIN = 10 kHz MCP33121-10 and MCP33121-05: 14-bit ADC — -97.4 — — -92.4 — dBc VREF = 2.5V, fIN = 1 kHz VREF = 5V, fIN = 1 kHz — -97.2 — VREF = 5V, fIN = 10 kHz — -92.3 — VREF = 2.5V, fIN = 10 kHz MCP33111-10 and MCP33111-05: 12-bit ADC Note — -94.4 — — -91.7 — dBc VREF = 5V, fIN = 1 kHz VREF = 2.5V, fIN = 1 kHz — -93.7 — VREF = 5V, fIN = 10 kHz — -91.5 — VREF = 2.5V, fIN = 10 kHz 1: This parameter is ensured by design and not 100% tested. 2: This parameter is ensured by characterization and not 100% tested. 3: Decoupling capacitor is recommended on the following pins: (a) AVDD pin: 1 F ceramic capacitor, (b) DVIO pin: 0.1 F ceramic capacitor, (c) VREF pin: 10 F tantalum capacitor. 4: PSRR (dB) = -20 log (DVOUT/AVDD), where DVOUT = change in conversion result. 5: ENOB = (SINAD - 1.76)/6.02 DS20006122A-page 6  2018 Microchip Technology Inc. MCP33131/MCP33121/MCP33111-XX TABLE 1-1: KEY ELECTRICAL CHARACTERISTICS (CONTINUED) Electrical Specifications: Unless otherwise specified, all parameters apply for TA = -40°C to +125°C, AVDD = 1.8V, DVIO = 3.3V, VREF = 5V, GND = 0V, Analog Input (VIN) = -1 dBFS sine wave, fIN = 10 kHz, CLOAD_SDO = 20 pF. • MCP331x1-10: Sample Rate (fS) = 1 Msps, SPI Clock Input (SCLK) = 60 MHz. • MCP331x1-05: Sample Rate (fS) = 500 kSPS, SPI Clock Input (SCLK) = 30 MHz. Parameters Sym. Min. Typ. Max. tCAL ReCalNSCLK Units Conditions — 500 650 ms — 1024 — clocks 0.7 * DVIO — DVIO + 0.3 V DVIO ≥ 2.3V 0.9 * DVIO — DVIO + 0.3 V DVIO < 2.3V -0.3 — 0.3 * DVIO V DVIO ≥ 2.3V -0.3 — 0.2 * DVIO V DVIO < 2.3V — 0.2 * DVIO — V All digital inputs IOL = 500 µA (sink) System Self-Calibration Self-Calibration Time Number of SCLK Clocks for Recalibrate Command (Note 2) Includes clocks for data bits Serial Interface Timing Information: See Table 1-2 Digital Inputs/Outputs High-level Input voltage Low-level input voltage Hysteresis of Schmitt Trigger Inputs VIH VIL VHYST Low-level output voltage VOL — — 0.2 * DVIO V High-level output voltage VOH 0.8 * DVIO — — V IOL = - 500 µA (source) Input leakage current ILI — — ±1 µA CNVST/SDI/SCLK = GND or DVIO Output leakage current ILO — — ±1 µA Output is high-Z, SDO = GND or DVIO CINT — 7 — pF TA = 25°C (Note 1) Internal capacitance (all digital inputs and outputs) Note 1: This parameter is ensured by design and not 100% tested. 2: This parameter is ensured by characterization and not 100% tested. 3: Decoupling capacitor is recommended on the following pins: (a) AVDD pin: 1 F ceramic capacitor, (b) DVIO pin: 0.1 F ceramic capacitor, (c) VREF pin: 10 F tantalum capacitor. 4: PSRR (dB) = -20 log (DVOUT/AVDD), where DVOUT = change in conversion result. 5: ENOB = (SINAD - 1.76)/6.02  2018 Microchip Technology Inc. DS20006122A-page 7 MCP33131/MCP33121/MCP33111-XX TABLE 1-2: SERIAL INTERFACE TIMING SPECIFICATIONS Electrical Specifications: Unless otherwise specified, all parameters apply for TA = -40°C to +125°C, AVDD = 1.8V, DVIO = 3.3V, GND = 0V, Analog Input (AIN) = -1 dBFS sine wave, Resolution = 16-bit (MCP33131-10), fIN = 10 kHz, CLOAD_SDO = 20 pF, +25°C is applied for typical value. All timings are measured at 50%. See Figure 1-1 for timing diagram. • MCP331x1-10: Sample Rate (fS) = 1 Msps, SPI Clock Input (SCLK) = 60 MHz. • MCP331x1-05: Sample Rate (fS) = 500 kSPS, SPI Clock Input (SCLK) = 30 MHz. Parameters Symbol Min. Typ. Max. Units Serial Clock frequency fSCLK — — 100 MHz SCLK Period tSCLK 10 — — ns SCLK Low Time tSCLK_L SCLK High Time tSCLK_H Output Valid from SCLK Low tDO Quiet time tQUIET Conditions See tSCLK specification DVIO ≥ 3.3V, fSCLK = 100 MHz (Max) 12 — — ns DVIO ≥ 2.3V, fSCLK = 83.3 MHz (Max) 16 — — ns DVIO ≥ 1.7V, fSCLK = 62.5 MHz (Max) 3 — — ns DVIO ≥ 2.3V 4.5 — — ns DVIO ≥ 1.7V DVIO ≥ 2.3V 3 — — ns 4.5 — — ns DVIO ≥ 1.7V — — 9.5 ns DVIO ≥ 3.3V — — 12 ns DVIO ≥ 2.3V — — 16 ns DVIO ≥ 1.7V 10 — — ns (Note 2) SDI High to CNVST Rising Edge 3-Wire Operation: SDI Valid Setup time tSU_SDIH_CNV 5 — — ns tCNVH 10 — — ns tEN — — 10 ns DVIO ≥ 2.3V — — 15 ns DVIO ≥ 1.7V — — 15 ns (Note 2) CNVST Pulse Width High Time Output Enable Time Output Disable Time tDIS MCP331x1-10 Sample Rate fs — — 1 Msps Input Acquisition Time (Note 2) tACQ 290 250 300 — — ns -40°C ≤ TA ≤ 85°C 85°C < TA ≤ 125°C Data Conversion Time tCNV — — 700 710 750 ns -40°C ≤ TA ≤ 85°C 85°C < TA ≤ 125°C Time between Conversions tCYC 1 — — µs tCYC = tACQ + tCNV, fS = 1 Msps Throughput rate MCP331x1-05 Sample Rate fs — — 500 kSPS Input Acquisition Time (Note 2) tACQ 700 800 — ns Data Conversion Time tCNV — 1200 1300 ns -40°C ≤ TA ≤ 125°C Time between Conversions tCYC 2 — — µs tCYC = tACQ + tCNV, fS = 500 kSPS Note 1: 2: Throughput rate -40°C ≤ TA ≤ 125°C This parameter is ensured by design and not 100% tested. This parameter is ensured by characterization and not 100% tested. TABLE 1-3: TEMPERATURE CHARACTERISTICS Parameters Symbol Min. Typ. Max. Units Operating Temperature Range TA -40 — +125 °C (Note 1) Storage Temperature Range TA -65 — +150 °C (Note 1) Thermal Resistance, MSOP-10 JA — 202 — °C/W Thermal Resistance, TDFN-10 JA — 68 — °C/W Conditions Temperature Ranges Thermal Package Resistance Note 1: The internal junction temperature (Tj) must not exceed the absolute maximum specification of +150oC. DS20006122A-page 8  2018 Microchip Technology Inc. MCP33131/MCP33121/MCP33111-XX tCYC = 1/fS SDI = “High” tCNVH tSU_SDIH_CNV CNVST tSCLK 1 SCLK 2 3 tDO Hi-Z SDO Dn-1 (MSB) tCNV (MAX) Input Acquisition (tACQ) Dn-3 n n-1 tSCLK_L tSCLK_H D1 tDIS D0 tQUIET Hi-Z tEN (Note 2) tEN ADC State Dn-2 (Note 1) (Note 3) Conversion (tCNV) Input Acquisition (tACQ) Note 1: n = 16 for 16-bit, 14 for 14-bit device, and 12 for 12-bit device. 2: tEN when CNVST is lowered after tCNV (MAX). 3: tEN when CNVST is lowered before tCNV (MAX). FIGURE 1-1: Details. Interface Timing Diagram. CNVST is used as chip select. See Figure 7-2 for More  2018 Microchip Technology Inc. DS20006122A-page 9 MCP33131/MCP33121/MCP33111-XX NOTES: DS20006122A-page 10  2018 Microchip Technology Inc. MCP33131/MCP33121/MCP33111-XX 2.0 TYPICAL PERFORMANCE CURVES FOR 16-BIT DEVICES (MCP33131-XX) Note: The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore outside the warranted range. Note: Unless otherwise specified, all parameters apply for TA = +25°C, AVDD = 1.8V, DVIO = 3.3V, VREF = 5V, GND = 0V, Differential Analog Input (VIN) = -1 dBFS, fIN = 10 kHz, CLOAD_SDO = 20 pF. MCP33131-10: Sample Rate (fS) = 1 Msps, SPI Clock Input (SCLK) = 60 MHz. MCP33131-05: Sample Rate (fS) = 500 kSPS, SPI Clock Input (SCLK) = 30 MHz. 2 4 V REF = 5V V REF = 2.5V 2 INL (LSB) INL (LSB) 1 0 -1 -2 0 -2 0 16,384 32,768 49,152 -4 65,536 0 16,384 32,768 Code FIGURE 2-1: 49,152 FIGURE 2-4: INL vs. Output Code. 2 INL vs. Output Code. 2 V REF = 2.5V 1.5 1.5 1 1 DNL (LSB) DNL (LSB) V REF = 5V 0.5 0 0.5 0 -0.5 -1 65,536 Code -0.5 0 16,384 32,768 49,152 -1 65,536 0 16,384 32,768 Code FIGURE 2-2: 49,152 65,536 Code FIGURE 2-5: DNL vs. Output Code. 3 DNL vs. Output Code. 1.5 2 Max INL (LSB) 1 0 DNL (LSB) INL (LSB) Max DNL (LSB) 1 V REF = 5V -1 Min INL (LSB) -20 0 20 40 60 80 V REF = 5V 0 -0.5 -2 -3 -40 0.5 100 120 140 -1 -40 Min DNL (LSB) -20 o FIGURE 2-3: INL vs. Temperature.  2018 Microchip Technology Inc. 0 20 40 60 80 100 120 140 Temperature (oC) Temperature ( C) FIGURE 2-6: DNL vs. Temperature. DS20006122A-page 11 MCP33131/MCP33121/MCP33111-XX Note: Unless otherwise specified, all parameters apply for TA = +25°C, AVDD = 1.8V, DVIO = 3.3V, VREF = 5V, GND = 0V, Differential Analog Input (VIN) = -1 dBFS, fIN = 10 kHz, CLOAD_SDO = 20 pF. MCP33131-10: Sample Rate (fS) = 1 Msps, SPI Clock Input (SCLK) = 60 MHz. MCP33131-05: Sample Rate (fS) = 500 kSPS, SPI Clock Input (SCLK) = 30 MHz. 2 8 6 DNL (LSB) INL (LSB) 4 2 0 -2 -4 1 0.5 0 Min INL (LSB) -0.5 -6 -8 Max DNL (LSB) 1.5 Max INL (LSB) -1 2 2.5 3 3.5 4 4.5 5 5.5 Min DNL (LSB) 2 2.5 3 FIGURE 2-7: INL vs. Reference Voltage. FIGURE 2-10: MCP33131-10 V REF = 5V 5 5.5 DNL vs. Reference Voltage. SNR = 86.7 dBFS SINAD = 86.6 dBFS SFDR = 103.6 dBc THD = -101.4 dBc Resolution = 16-bit -40 -60 -80 V REF = 2.5V -20 fs = 1 Msps -100 -120 -140 fs = 1 Msps SNR = 81.7 dBFS SINAD = 81.6 dBFS SFDR = 98.0 dBc THD = -95.8 dBc Resolution = 16-bit -40 -60 -80 -100 -120 -140 0 100 200 300 400 -160 500 0 100 Frequency (kHz) -60 -80 500 0 fs = 0.5 Msps -20 SNR = 86.7 dBFS SINAD = 86.6 dBFS SFDR = 105.0 dBc THD = -101.5 dBc Resolution = 16-bit -40 Amplitude (dBFS) -40 400 MCP33131-05 MCP33131-05 V REF = 5V 300 FIGURE 2-11: FFT for 10 kHz Input Signal: fS = 1 Msps, VIN = -1 dBFS, VREF = 2.5V. 0 -20 200 Frequency (kHz) FIGURE 2-8: FFT for 10 kHz Input Signal: fS = 1 Msps, VIN = -1 dBFS, VREF = 5V. Amplitude (dBFS) 4.5 MCP33131-10 Amplitude (dBFS) Amplitude (dBFS) -20 -100 -120 -140 -160 4 0 0 -160 3.5 Reference Voltage (V) Reference Voltage (V) VREF = 2.5V fs = 0.5 Msps SNR = 81.8 dBFS SINAD = 81.7 dBFS SFDR = 98.9 dBc THD = -96.0 dBc Resolution = 16-bit -60 -80 -100 -120 -140 0 50 100 150 200 250 Frequency (kHz) FIGURE 2-9: FFT for 10 kHz Input Signal: fS = 500 kSPS, VIN = -1 dBFS, VREF = 5V. DS20006122A-page 12 -160 0 50 100 150 200 250 Frequency (kHz) FIGURE 2-12: FFT for 10 kHz Input Signal: fS = 500 kSPS, VIN = -1 dBFS, VREF = 2.5V.  2018 Microchip Technology Inc. MCP33131/MCP33121/MCP33111-XX Note: Unless otherwise specified, all parameters apply for TA = +25°C, AVDD = 1.8V, DVIO = 3.3V, VREF = 5V, GND = 0V, Differential Analog Input (VIN) = -1 dBFS, fIN = 10 kHz, CLOAD_SDO = 20 pF. MCP33131-10: Sample Rate (fS) = 1 Msps, SPI Clock Input (SCLK) = 60 MHz. MCP33131-05: Sample Rate (fS) = 500 kSPS, SPI Clock Input (SCLK) = 30 MHz. 90 14 -90 100 -92 98 84 82 13 80 ENOB SNR (dB) SINAD (dB) 78 -94 SFDR (dB) 13.5 THD (dB) 86 ENOB (Bits) SNR/SINAD (dB) 88 96 THD (dB) SFDR (dB) 12.5 -96 94 -98 92 76 74 2 2.5 3 3.5 4 4.5 -100 12 5.5 5 2 2.5 3 SNR/SINAD/ENOB vs. VREF FIGURE 2-16: SNR/SINAD (dB) SNR/SINAD (dB) 87 86 85 SNR (dB) SINAD (dB) 83 -40 -20 0 20 40 60 80 100 120 140 V REF = 2.5V 82 81 80 79 78 77 76 SNR (dB) 75 SINAD (dB) 74 -40 -20 0 Temperature ( C) 80 84 V REF = 5V SNR/SINAD (dBFS) 89 SNR/SINAD (dBFS) 60 100 120 140 85 90 88 87 86 85 84 80 -30 40 FIGURE 2-17: SNR/SINAD vs. Temperature: VREF = 2.5V. FIGURE 2-14: SNR/SINAD vs. Temperature: VREF = 5V. 81 20 Temperature (oC) o 82 90 5.5 5 SFDR/THD vs. VREF 83 V REF = 5V 83 4.5 84 88 84 4 Reference Voltage (V) Reference Voltage (V) FIGURE 2-13: 3.5 SNR (dBFS) SINAD(dBFS) -25 -20 82 81 80 79 78 77 76 -15 -10 -5 Input Amplitude (dBFS) FIGURE 2-15: SNR/SINAD vs. Input Amplitude: FIN = 10 kHz.  2018 Microchip Technology Inc. 0 V REF = 2.5V 83 75 -30 SNR (dBFS) SINAD(dBFS) -25 -20 -15 -10 -5 0 Input Amplitude (dBFS) FIGURE 2-18: SNR/SINAD vs. Input Amplitude: FIN = 10 kHz. DS20006122A-page 13 MCP33131/MCP33121/MCP33111-XX Unless otherwise specified, all parameters apply for TA = +25°C, AVDD = 1.8V, DVIO = 3.3V, VREF = 5V, GND = 0V, Differential Analog Input (VIN) = -1 dBFS, fIN = 10 kHz, CLOAD_SDO = 20 pF. MCP33131-10: Sample Rate (fS) = 1 Msps, SPI Clock Input (SCLK) = 60 MHz. MCP33131-05: Sample Rate (fS) = 500 kSPS, SPI Clock Input (SCLK) = 30 MHz. 90 90 SNR/SINAD (dB) 84 82 80 78 76 72 SNR (dB) 84 82 80 78 76 74 SINAD (dB) 70 0 10 86 72 10 1 10 2 10 SNR (dB) SINAD (dB) 70 0 10 3 10 -92 THD (dB) SFDR (dB) -100 THD (dB) 98 SFDR (dB) THD (dB) -98 THD (dB) SFDR (dB) 96 40 98 -93 97 -94 96 -95 95 VREF = 2.5V -96 -40 -20 94 80 100 120 140 60 20 40 60 94 80 100 120 140 Temperature ( C) Temperature ( C) FIGURE 2-23: THD/SFDR vs. Temperature: VREF = 2.5V. FIGURE 2-20: THD/SFDR vs. Temperature: VREF = 5V. -75 110 THD (dB) SFDR (dB) -75 110 THD (dB) SFDR (dB) -80 -85 100 -85 100 -90 95 -90 95 -95 90 -95 90 -100 85 -100 85 80 -105 -105 -110 0 10 VREF = 5V 10 1 10 2 75 3 10 Input Frequency (kHz) FIGURE 2-21: THD/SFDR vs. Input Frequency: VREF = 5V. DS20006122A-page 14 THD (dB) 105 SFDR (dB) THD (dB) 0 o o -80 3 99 -92 VREF = 5V 20 10 100 -91 102 100 0 2 -90 104 -96 -102 -40 -20 10 FIGURE 2-22: SNR/SINAD vs.Input Frequency: VIN = -1 dBFS. FIGURE 2-19: SNR/SINAD vs.Input Frequency: VIN = -1 dBFS. -94 1 Input Frequency (kHz) Input Frequency (kHz) SFDR (dB) SNR/SINAD (dB) 86 74 V REF = 2.5V 88 V REF = 5V 88 -110 100 105 SFDR (dB) Note: 80 VREF = 2.5V 101 102 75 103 Input Frequency (kHz) FIGURE 2-24: THD/SFDR vs. Input Frequency: VREF = 2.5V.  2018 Microchip Technology Inc. MCP33131/MCP33121/MCP33111-XX Unless otherwise specified, all parameters apply for TA = +25°C, AVDD = 1.8V, DVIO = 3.3V, VREF = 5V, GND = 0V, Differential Analog Input (VIN) = -1 dBFS, fIN = 10 kHz, CLOAD_SDO = 20 pF. MCP33131-10: Sample Rate (fS) = 1 Msps, SPI Clock Input (SCLK) = 60 MHz. MCP33131-05: Sample Rate (fS) = 500 kSPS, SPI Clock Input (SCLK) = 30 MHz. -65 -70 95 -70 -75 90 -75 THD (dB) -80 85 VREF = 5V -85 80 -90 75 -95 -80 105 THD (dB) SFDR (dB) 100 95 90 85 VREF = 2.5V -85 80 -90 75 70 -95 70 -100 65 -100 65 -105 -30 60 -105 -30 -25 -20 -15 -10 -5 0 -25 -20 Input Amplitude (dBFS)
10 5 Occurrences 14132 143 3 4 5 6 7 8 5 9 0 -5 10 -3 -1 1 FIGURE 2-29: VREF = 2.5V. 10.49 400 700 9.18 300 600 7.86 Offset Error 6.55 400 5.24 300 3.93 Gain Error 200 2.62 100 1.31 VREF = 5V 0 -100 -40 -20 0 20 40 60 80 0 -1.31 100 120 140 Temperature (oC) FIGURE 2-27: Offset and Gain Error vs. Temperature: VREF = 5V.  2018 Microchip Technology Inc. Offset/Gain Error (uV) 800 Offset/Gain Error (LSB) Offset/Gain Error (uV) Shorted Input Histogram: 500 5 7 9 11 13 15 Output Code Output Code FIGURE 2-26: VREF = 5V. 3 1167 2377 2 12208 1 20814 27533 12848 18039 50970 0 1 119771 9092 0 2 128876 137150 4 3 133072 79707 12211 Occurrences 6 93862 60 V REF = 2.5V 402464 4 59995 65 3224 0
105 V REF = 5V 757379 2 -5 FIGURE 2-28: THD/SFDR vs. Input Amplitude: VREF = 2.5V. 5 8 -10 Input Amplitude (dBFS) FIGURE 2-25: THD/SFDR vs. Input Amplitude: VREF = 5V. 10 -15 SFDR (dB) -60 100 THD (dB) 105 THD (dB) SFDR (dB) -65 SFDR (dB) -60 Shorted Input Histogram: 10.49 7.86 Offset Error 200 5.24 100 2.62 0 0 -100 -2.62 Gain Error -200 -5.24 -300 -7.86 VREF = 2.5V -400 -500 -40 -20 0 20 40 60 80 Offset/Gain Error (LSB) Note: -10.49 -13.11 100 120 140 o Temperature ( C) FIGURE 2-30: Offset and Gain Error vs. Temperature: VREF = 2.5V. DS20006122A-page 15 MCP33131/MCP33121/MCP33111-XX Note: Unless otherwise specified, all parameters apply for TA = +25°C, AVDD = 1.8V, DVIO = 3.3V, VREF = 5V, GND = 0V, Differential Analog Input (VIN) = -1 dBFS, fIN = 10 kHz, CLOAD_SDO = 20 pF. MCP33131-10: Sample Rate (fS) = 1 Msps, SPI Clock Input (SCLK) = 60 MHz. MCP33131-05: Sample Rate (fS) = 500 kSPS, SPI Clock Input (SCLK) = 30 MHz. 8 86 V REF 16 = 5V 78 1. 8V ) 8 D (A V D = 4 IIO_STBY (DVIO = 3.3V) Y CMRR (dB) 80 12 Total Power Consumption TB Current (
A) 6 82 4 I D D A N _S 2 Total Power (
W) 84 76 10-1 100 101 102 103 Temperature (°C) Input Frequency (kHz) FIGURE 2-31: VREF = 5V. CMRR vs. Input Frequency: 2 FIGURE 2-34: Power Consumption vs. Temperature During Shutdown. 2 8 (AV D D l ota n tio mp su I DDAN r we Po n Co 4 T I REF 2 (V REF = 5V) (AV DD 1 0 0.1 10 6 4 IREF (VREF = 5V) 2 1 Temperature (°C) FIGURE 2-33: Power Consumption vs. Temperature: CLOAD_SDO = 20 pF. I DDAN (AV DD Total Power = 1.8V) Consumption 0.5 6 4 2 IREF (VREF = 5V) IIO_DATA (DVIO = 3.3V) 0 20 35 50 65 80 95 110 125 DS20006122A-page 16 0 0.5 8 1.5 Current (mA) n Total Power (mW) Current (mA) 8 1 0 -40 -25 -10 5 0.4 MCP331x1-05 nsumptio 0.5 0.3 2 = 1.8V er Co Total Pow 1.5 0.2 2 IREF (VREF = 5V) FIGURE 2-35: Power Consumption vs. Sample Rate: CLOAD_SDO = 20 pF. ) (AV DD we l Po Tota 0.5 ns r Co Sample Rate (Msps) 2.5 I DDAN 4 tion ump 0 FIGURE 2-32: Power Consumption vs. Sample Rate: CLOAD_SDO = 20 pF. 2 .8 =1 I DDAN 1 Sample Rate (Msps) MCP331x1-10 6 V) IIO_DATA (DVIO = 3.3V) ) I IO_DATA (DVIO = 3.3V 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.5 Current (mA) 6 ) .8V =1 Total Power (mW) Current (mA) 1.5 0.5 8 MCP331x1-05 MCP331x1-10 1 0 20 35 50 65 80 95 110 125 Total Power (mW) 10-2 Total Power (mW) 74 10-3 IREF_STBY (VREF = 5V) 0 -40 -25 -10 5 0 -40 -25 -10 5 IIO_DATA (DVIO = 3.3V) 0 20 35 50 65 80 95 110 125 Temperature (°C) FIGURE 2-36: Power Consumption vs. Temperature: CLOAD_SDO = 20 pF.  2018 Microchip Technology Inc. MCP33131/MCP33121/MCP33111-XX 3.0 TYPICAL PERFORMANCE CURVES FOR 14-BIT DEVICES (MCP33121-XX) Note: The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore outside the warranted range. Note: Unless otherwise specified, all parameters apply for TA = +25°C, AVDD = 1.8V, DVIO = 3.3V, VREF = 5V, GND = 0V, Differential Analog Input (VIN) = -1 dBFS, fIN = 10 kHz, CLOAD_SDO = 20 pF. MCP33121-10: Sample Rate (fS) = 1 Msps, SPI Clock Input (SCLK) = 60 MHz. MCP33121-05: Sample Rate (fS) = 500 kSPS, SPI Clock Input (SCLK) = 30 MHz. 1 1 V REF = 5V V REF = 2.5V 0.5 INL (LSB) INL (LSB) 0.5 0 -0.5 -1 0 -0.5 0 4,096 8,192 12,288 -1 16,384 0 4,096 8,192 Code FIGURE 3-1: 12,288 FIGURE 3-4: INL vs. Output Code. INL vs. Output Code. 1 1 V REF = 2.5V V REF = 5V 0.5 DNL (LSB) DNL (LSB) 0.5 0 -0.5 -1 16,384 Code 0 -0.5 0 4,096 8,192 12,288 -1 16,384 0 4,096 8,192 Code FIGURE 3-2: 12,288 16,384 Code FIGURE 3-5: DNL vs. Output Code. DNL vs. Output Code. 1 1 0.8 Max INL (LSB) 0.6 Max DNL (LSB) 0.5 DNL (LSB) INL (LSB) 0.4 0.2 0 V REF = 5V -0.2 -0.4 0 V REF = 5V Min DNL (LSB) -0.5 -0.6 Min INL (LSB) -0.8 -1 -40 -20 0 20 40 60 80 100 120 140 -1 -40 -20 FIGURE 3-3: INL vs. Temperature.  2018 Microchip Technology Inc. 0 20 40 60 80 100 120 140 Temperature (oC) Temperature (oC) FIGURE 3-6: DNL vs. Temperature. DS20006122A-page 17 MCP33131/MCP33121/MCP33111-XX Note: Unless otherwise specified, all parameters apply for TA = +25°C, AVDD = 1.8V, DVIO = 3.3V, VREF = 5V, GND = 0V, Differential Analog Input (VIN) = -1 dBFS, fIN = 10 kHz, CLOAD_SDO = 20 pF. MCP33121-10: Sample Rate (fS) = 1 Msps, SPI Clock Input (SCLK) = 60 MHz. MCP33121-05: Sample Rate (fS) = 500 kSPS, SPI Clock Input (SCLK) = 30 MHz. 2 1 1.5 Max DNL (LSB) Max INL (LSB) 0.5 DNL (LSB) INL (LSB) 1 0.5 0 -0.5 -1 0 -0.5 Min INL (LSB) Min DNL (LSB) -1.5 -2 2 2.5 3 3.5 4 4.5 5 -1 5.5 2 2.5 3 Reference Voltage (V) FIGURE 3-7: INL vs. Reference Voltage. FIGURE 3-10: V REF = 5V SNR = 83.6 dBFS SINAD = 83.6 dBFS SFDR = 104.3 dBc THD = -100.8 dBc Resolution = 14-bit -40 -60 -80 Amplitude (dBFS) Amplitude (dBFS) 5 5.5 DNL vs. Reference Voltage. VREF = 2.5V -20 fs = 1 Msps -100 -120 -140 fs = 1 Msps SNR = 80.3 dBFS SINAD = 80.2 dBFS SFDR = 97.9 dBc THD = -95.8 dBc Resolution = 14-bit -40 -60 -80 -100 -120 -140 0 100 200 300 400 -160 500 0 100 200 Frequency (kHz) 400 500 FIGURE 3-11: FFT for 10 kHz Input Signal: fS = 1 Msps, VIN = -1 dBFS, VREF = 2.5V. MCP33121-05 MCP33121-05 0 0 VREF = 5V -20 300 Frequency (kHz) FIGURE 3-8: FFT for 10 kHz Input Signal: fS = 1 Msps, VIN = -1 dBFS, VREF = 5V. fs = 0.5 Msps -40 -60 -80 V REF = 2.5V -20 SNR = 83.5 dBFS SINAD = 83.4 dBFS SFDR = 105.0 dBc THD = -101.6 dBc Resolution = 14-bit Amplitude (dBFS) Amplitude (dBFS) 4.5 0 -20 -100 -120 -140 -160 4 MCP33121-10 MCP33121-10 0 -160 3.5 Reference Voltage (V) fs = 0.5 Msps SNR = 80.6 dBFS SINAD = 80.5 dBFS SFDR = 99.4 dBc THD = -96.4 dBc Resolution = 14-bit -40 -60 -80 -100 -120 -140 0 50 100 150 200 250 Frequency (kHz) FIGURE 3-9: FFT for 10 kHz Input Signal: fS = 500 kSPS, VIN = -1 dBFS, VREF = 5V. DS20006122A-page 18 -160 0 50 100 150 200 250 Frequency (kHz) FIGURE 3-12: FFT for 10 kHz Input Signal: fS = 500 kSPS, VIN = -1 dBFS, VREF = 2.5V.  2018 Microchip Technology Inc. MCP33131/MCP33121/MCP33111-XX Unless otherwise specified, all parameters apply for TA = +25°C, AVDD = 1.8V, DVIO = 3.3V, VREF = 5V, GND = 0V, Differential Analog Input (VIN) = -1 dBFS, fIN = 10 kHz, CLOAD_SDO = 20 pF. MCP33121-10: Sample Rate (fS) = 1 Msps, SPI Clock Input (SCLK) = 60 MHz. MCP33121-05: Sample Rate (fS) = 500 kSPS, SPI Clock Input (SCLK) = 30 MHz. -90 100 84 13.5 -92 98 82 13 80 12.5 76 2 2.5 3 3.5 4 4.5 5 SFDR (dB) 94 12 -98 92 11.5 5.5 -100 2 2.5 3 Reference Voltage (V) FIGURE 3-16: 85 SNR/SINAD (dB) SNR/SINAD (dB) 83 82 SNR (dB) SINAD (dB) 80 -40 -20 0 20 40 60 80 100 120 140 V REF = 2.5V 79 78 77 76 75 74 SNR (dB) 73 SINAD (dB) 72 -40 -20 0 60 80 100 120 140 86 SNR/SINAD (dBFS) 84 83 82 81 80 SNR (dBFS) SINAD(dBFS) -25 -20 84 83 82 81 80 79 78 77 -15 -10 -5 Input Amplitude (dBFS) FIGURE 3-15: SNR/SINAD vs. Input Amplitude: FIN = 10 kHz.  2018 Microchip Technology Inc. V REF = 2.5V 85 V REF = 5V 85 SNR/SINAD (dBFS) 40 FIGURE 3-17: SNR/SINAD vs. Temperature: VREF = 2.5V. 86 76 -30 20 Temperature (oC) FIGURE 3-14: SNR/SINAD vs. Temperature: VREF = 5V. 77 90 5.5 5 80 Temperature (oC) 78 4.5 SFDR/THD vs. VREF. 81 84 79 4 82 V REF = 5V 81 3.5 Reference Voltage (V) SNR/SINAD/ENOB vs. VREF. FIGURE 3-13: 96 THD (dB) -96 ENOB SNR (dB) SINAD (dB) 78 -94 SFDR (dB) 14 THD (dB) 86 ENOB (Bits) SNR/SINAD (dB) Note: 0 76 -30 SNR (dBFS) SINAD(dBFS) -25 -20 -15 -10 -5 0 Input Amplitude (dBFS) FIGURE 3-18: SNR/SINAD vs. Input Amplitude: FIN = 10 kHz. DS20006122A-page 19 MCP33131/MCP33121/MCP33111-XX Unless otherwise specified, all parameters apply for TA = +25°C, AVDD = 1.8V, DVIO = 3.3V, VREF = 5V, GND = 0V, Differential Analog Input (VIN) = -1 dBFS, fIN = 10 kHz, CLOAD_SDO = 20 pF. MCP33121-10: Sample Rate (fS) = 1 Msps, SPI Clock Input (SCLK) = 60 MHz. MCP33121-05: Sample Rate (fS) = 500 kSPS, SPI Clock Input (SCLK) = 30 MHz. 90 90 V REF = 5V 84 82 80 78 76 72 SNR (dB) 84 82 80 78 76 74 SINAD (dB) 70 100 86 72 101 102 SNR (dB) SINAD (dB) 70 100 103 101 Input Frequency (kHz) -92 FIGURE 3-22: SNR/SINAD vs.Input Frequency: VIN = -1 dBFS. 104 THD (dB) SFDR (dB) -98 98 -100 THD (dB) 100 100 THD (dB) SFDR (dB) -91 SFDR (dB) THD (dB) -90 102 -96 96 0 20 40 60 98 -93 97 -94 96 -95 95 VREF = 2.5V 94 80 100 120 140 -96 -40 -20 o Temperature ( C) 0 20 40 60 94 80 100 120 140 o (oC) Temperature Temperature ( C) FIGURE 3-23: THD/SFDR vs. Temperature: VREF = 2.5V. FIGURE 3-20: THD/SFDR vs. Temperature: VREF = 5V. -75 -75 110 THD (dB) SFDR (dB) 110 THD (dB) SFDR (dB) -85 100 -85 100 -90 95 -90 95 -95 90 -95 90 -100 85 -100 85 80 -105 -105 -110 100 VREF = 5V 101 102 75 103 Input Frequency (kHz) FIGURE 3-21: THD/SFDR vs. Input Frequency: VREF = 5V. DS20006122A-page 20 THD (dB) -80 SFDR (dB) 105 -80 THD (dB) 99 -92 VREF = 5V -102 -40 -20 103 Input Frequency (kHz) FIGURE 3-19: SNR/SINAD vs.Input Frequency: VIN = -1 dBFS. -94 102 SFDR (dB) 74 V REF = 2.5V 88 86 SNR/SINAD (dB) SNR/SINAD (dB) 88 -110 100 105 SFDR (dB) Note: 80 VREF = 2.5V 101 102 75 103 Input Frequency (kHz) FIGURE 3-24: THD/SFDR vs. Input Frequency: VREF = 2.5V.  2018 Microchip Technology Inc. MCP33131/MCP33121/MCP33111-XX Unless otherwise specified, all parameters apply for TA = +25°C, AVDD = 1.8V, DVIO = 3.3V, VREF = 5V, GND = 0V, Differential Analog Input (VIN) = -1 dBFS, fIN = 10 kHz, CLOAD_SDO = 20 pF. MCP33121-10: Sample Rate (fS) = 1 Msps, SPI Clock Input (SCLK) = 60 MHz. MCP33121-05: Sample Rate (fS) = 500 kSPS, SPI Clock Input (SCLK) = 30 MHz. -70 -75 90 -75 -80 85 VREF = 5V 70 65 -100 65 60 -105 -30 -100 -105 -30 0 -25
105 10 985144 0 60 V REF = 2.5V 6 4 719460 6 4 234082 2 2 79234 15798 63284 148 -2 -1 0 1 2 3 4 0 -4 5 -3 -2 -1 Output Code FIGURE 3-26: VREF = 5V. 0 1 2 3 2 4 5 6 Output Code Shorted Input Histogram: FIGURE 3-29: VREF = 2.5V. Shorted Input Histogram: 2.29 400 2.62 600 1.97 300 1.97 500 1.64 Offset Error 400 1.31 300 0.98 200 0.66 Gain Error VREF = 5V 100 0 -40 -20 0 20 40 60 80 0.33 0 100 120 140 o Temperature ( C) FIGURE 3-27: Offset and Gain Error vs. Temperature: VREF = 5V.  2018 Microchip Technology Inc. Offset/Gain Error (uV) 700 Offset/Gain Error (LSB) Offset/Gain Error (uV) -5
105 8 8 0 -3 -10 V REF = 5V Occurrences Occurrences -15 FIGURE 3-28: THD/SFDR vs. Input Amplitude: VREF = 2.5V. FIGURE 3-25: THD/SFDR vs. Input Amplitude: VREF = 5V. 10 -20 Input Amplitude (dBFS) Input Amplitude (dBFS) 12 85 VREF = 2.5V 75 70 -5 90 -80 -95 75 -95 -10 95 -90 -90 -15 100 80 80 -20 105 THD (dB) SFDR (dB) -85 -85 -25 THD (dB) -65 95 SFDR (dB) 100 -70 -65 THD (dB) -60 105 THD (dB) SFDR (dB) SFDR (dB) -60 200 1.31 Offset Error 100 0.66 0 0 Gain Error -100 -0.66 VREF = 2.5V -200 -300 -40 -20 0 20 40 60 80 -1.31 Offset/Gain Error (LSB) Note: -1.97 100 120 140 o Temperature ( C) FIGURE 3-30: Offset and Gain Error vs. Temperature: VREF = 2.5V. DS20006122A-page 21 MCP33131/MCP33121/MCP33111-XX Note: Unless otherwise specified, all parameters apply for TA = +25°C, AVDD = 1.8V, DVIO = 3.3V, VREF = 5V, GND = 0V, Differential Analog Input (VIN) = -1 dBFS, fIN = 10 kHz, CLOAD_SDO = 20 pF. MCP33121-10: Sample Rate (fS) = 1 Msps, SPI Clock Input (SCLK) = 60 MHz. MCP33121-05: Sample Rate (fS) = 500 kSPS, SPI Clock Input (SCLK) = 30 MHz. 86 8 VREF = 5V 16 1. 8V ) D V D = 8 (A 78 4 IIO_STBY (DVIO = 3.3V) Y CMRR (dB) 80 12 Total Power Consumption TB Current (
A) 6 82 4 D A N _S 2 Total Power (
W) 84 I D 76 IREF_STBY (VREF = 5V) 10-1 100 101 102 0 -40 -25 -10 5 103 Input Frequency (kHz) FIGURE 3-31: VREF = 5V. Temperature (°C) CMRR vs. Input Frequency: 2 FIGURE 3-34: Power Consumption vs. Temperature During Shutdown. 8 2 MCP331x1-10 D l ota n tio mp su r we Po n Co 4 T 2 I REF (V REF = 5V) (AV DD 1 =1 I DDAN 1 4 tion wer l Po Tota 0.5 0 0 0.1 Sample Rate (Msps) 0.2 mp nsu Co 2 IREF (VREF = 5V) 0.3 0.4 0 0.5 Sample Rate (Msps) FIGURE 3-32: Power Consumption vs. Sample Rate: CLOAD_SDO = 20 pF. 2.5 FIGURE 3-35: Power Consumption vs. Sample Rate: CLOAD_SDO = 20 pF. 10 MCP331x1-10 1 6 4 IREF (VREF = 5V) 0.5 2 1.5 Current (mA) Total Pow 8 8 MCP331x1-05 Total Power (mW) (AV DD = 1.8V ption er Consum 1.5 2 ) I DDAN 2 Current (mA) 6 ) .8V IIO_DATA (DVIO = 3.3V) ) I IO_DATA (DVIO = 3.3V 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.5 Current (mA) (AV D I DDAN Total Power (mW) Current (mA) 6 ) .8V =1 0.5 8 MCP331x1-05 1.5 1 0 20 35 50 65 80 95 110 125 Total Power (mW) 10-2 1 0 20 35 50 65 80 95 110 125 Temperature (°C) FIGURE 3-33: Power Consumption vs. Temperature: CLOAD_SDO = 20 pF. DS20006122A-page 22 Total Power = 1.8V) Consumption 0.5 6 4 2 IREF (VREF = 5V) IIO_DATA (DVIO = 3.3V) 0 -40 -25 -10 5 I DDAN (AV DD Total Power (mW) 74 10-3 0 -40 -25 -10 5 IIO_DATA (DVIO = 3.3V) 0 20 35 50 65 80 95 110 125 Temperature (°C) FIGURE 3-36: Power Consumption vs.  2018 Microchip Technology Inc. MCP33131/MCP33121/MCP33111-XX 4.0 TYPICAL PERFORMANCE CURVES FOR 12-BIT DEVICES (MCP33111-XX) Note: The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore outside the warranted range. Note: Unless otherwise specified, all parameters apply for TA = +25°C, AVDD = 1.8V, DVIO = 3.3V, VREF = 5V, GND = 0V, Differential Analog Input (VIN) = -1 dBFS, fIN = 10 kHz, CLOAD_SDO = 20 pF. MCP33111-10: Sample Rate (fS) = 1 Msps, SPI Clock Input (SCLK) = 60 MHz. MCP33111-05: Sample Rate (fS) = 500 kSPS, SPI Clock Input (SCLK) = 30 MHz. 0.5 0.5 V REF = 5V V REF = 2.5V 0.3 INL (LSB) INL (LSB) 0.3 0.1 -0.1 -0.3 -0.5 0.1 -0.1 -0.3 0 1,024 2,048 3,072 -0.5 4,096 0 1,024 2,048 Code FIGURE 4-1: 3,072 FIGURE 4-4: INL vs. Output Code. 0.5 INL vs. Output Code. 0.5 V REF = 5V V REF = 2.5V 0.3 DNL (LSB) DNL (LSB) 0.3 0.1 -0.1 -0.3 -0.5 0.1 -0.1 -0.3 0 1,024 2,048 3,072 -0.5 4,096 0 1,024 2,048 Code FIGURE 4-2: DNL vs. Output Code. FIGURE 4-5: 4,096 DNL vs. Output Code. 0.2 Max INL (LSB) 0.15 0.15 0.1 Max DNL (LSB) V REF = 5V 0 -0.05 -0.1 DNL (LSB) 0.1 0.05 0.05 0 V REF = 5V -0.05 -0.1 -0.15 -0.2 -40 3,072 Code 0.2 INL (LSB) 4,096 Code Min INL (LSB) -20 0 20 40 60 80 Min DNL (LSB) -0.15 100 120 140 -0.2 -40 -20 o FIGURE 4-3: INL vs. Temperature.  2018 Microchip Technology Inc. 0 20 40 60 80 100 120 140 Temperature (oC) Temperature ( C) FIGURE 4-6: DNL vs. Temperature. DS20006122A-page 23 MCP33131/MCP33121/MCP33111-XX Note: Unless otherwise specified, all parameters apply for TA = +25°C, AVDD = 1.8V, DVIO = 3.3V, VREF = 5V, GND = 0V, Differential Analog Input (VIN) = -1 dBFS, fIN = 10 kHz, CLOAD_SDO = 20 pF. MCP33111-10: Sample Rate (fS) = 1 Msps, SPI Clock Input (SCLK) = 60 MHz. MCP33111-05: Sample Rate (fS) = 500 kSPS, SPI Clock Input (SCLK) = 30 MHz. 0.6 0.5 0.4 Max DNL (LSB) DNL (LSB) INL (LSB) Max INL (LSB) 0.2 0 -0.2 0 Min DNL (LSB) Min INL (LSB) -0.4 -0.6 2 2.5 3 3.5 4 4.5 5 -0.5 2 5.5 2.5 Reference Voltage (V) FIGURE 4-7: INL vs. Reference Voltage. MCP33111-10 V REF = 5V 4.5 5 5.5 DNL vs. Reference Voltage. MCP33111-10 V REF = 2.5V fs = 1 Msps Amplitude (dBFS) -60 fs = 1 Msps -20 SNR = 73.8 dBFS SINAD = 73.7 dBFS SFDR = 99.7 dBc THD = -98.4 dBc Resolution = 12-bit -40 -80 -100 SNR = 73.4 dBFS SINAD = 73.4 dBFS SFDR = 99.0 dBc THD = -95.1 dBc Resolution = 12-bit -40 -60 -80 -100 0 100 200 300 400 -120 500 0 100 Frequency (kHz) 300 400 500 FIGURE 4-11: FFT for 10 kHz Input Signal: fS = 1 Msps, VIN = -1 dBFS, VREF = 2.5V. MCP33111-05 MCP33111-05 0 0 V REF = 5V V REF = 2.5V fs = 0.5 Msps -20 Amplitude (dBFS) -60 fs = 0.5 Msps -20 SNR = 73.8 dBFS SINAD = 73.8 dBFS SFDR = 99.9 dBc THD = -97.5 dBc Resolution = 12-bit -40 -80 SNR = 73.4 dBFS SINAD = 73.4 dBFS SFDR = 100.1 dBc THD = -96.4 dBc Resolution = 12-bit -40 -60 -80 -100 -100 -120 200 Frequency (kHz) FIGURE 4-8: FFT for 10 kHz Input Signal: fS = 1 Msps, VIN = -1 dBFS, VREF = 5V. Amplitude (dBFS) 4 0 -20 Amplitude (dBFS) 3.5 FIGURE 4-10: 0 -120 3 Reference Voltage (V) -120 0 50 100 150 200 250 Frequency (kHz) FIGURE 4-9: FFT for 10 kHz Input Signal: fS = 500 kSPS, VIN = -1 dBFS, VREF = 5V. DS20006122A-page 24 0 50 100 150 200 250 Frequency (kHz) FIGURE 4-12: FFT for 10 kHz Input Signal: fS = 500 kSPS, VIN = -1 dBFS, VREF = 2.5V.  2018 Microchip Technology Inc. MCP33131/MCP33121/MCP33111-XX 11.9 73 11.8 72.5 11.7 ENOB SNR (dB) SINAD (dB) 72 71.5 2 2.5 3 3.5 4 4.5 11.6 100 -91 98 -92 96 THD (dB) SFDR (dB) -93 -95 92 2 2.5 Reference Voltage (V) FIGURE 4-13: SNR/SINAD/ENOB vs. VREF 3.5 FIGURE 4-16: 4 4.5 SFDR/THD vs. VREF SNR/SINAD (dB) 72.8 72.6 SNR (dB) SINAD (dB) 72.2 -40 -20 0 20 73 72.5 72 71.5 71 70.5 40 60 80 V REF = 2.5V 73.5 73 SNR (dB) SINAD (dB) 70 -40 -20 100 120 140 Temperature (oC) 0 20 40 60 80 FIGURE 4-17: SNR/SINAD vs. Temperature: VREF = 2.5V. 75 75 V REF = 2.5V 74 SNR/SINAD (dBFS) SNR/SINAD (dBFS) V REF = 5V 73 72 70 -30 100 120 140 Temperature (oC) FIGURE 4-14: SNR/SINAD vs. Temperature: VREF = 5V. 71 90 5.5 5 74 V REF = 5V SNR/SINAD (dB) 3 Reference Voltage (V) 73.2 72.4 94 -94 11.5 5.5 5 -90 SFDR (dB) 73.5 THD (dB) Unless otherwise specified, all parameters apply for TA = +25°C, AVDD = 1.8V, DVIO = 3.3V, VREF = 5V, GND = 0V, Differential Analog Input (VIN) = -1 dBFS, fIN = 10 kHz, CLOAD_SDO = 20 pF. MCP33111-10: Sample Rate (fS) = 1 Msps, SPI Clock Input (SCLK) = 60 MHz. MCP33111-05: Sample Rate (fS) = 500 kSPS, SPI Clock Input (SCLK) = 30 MHz. ENOB (Bits) SNR/SINAD (dB) Note: SNR (dBFS) SINAD(dBFS) -25 -20 -15 -10 -5 Input Amplitude (dBFS) FIGURE 4-15: SNR/SINAD vs. Input Amplitude: FIN = 10 kHz.  2018 Microchip Technology Inc. 0 74 73 72 71 70 -30 SNR (dBFS) SINAD(dBFS) -25 -20 -15 -10 -5 0 Input Amplitude (dBFS) FIGURE 4-18: SNR/SINAD vs. Input Amplitude: FIN = 10 kHz. DS20006122A-page 25 MCP33131/MCP33121/MCP33111-XX Unless otherwise specified, all parameters apply for TA = +25°C, AVDD = 1.8V, DVIO = 3.3V, VREF = 5V, GND = 0V, Differential Analog Input (VIN) = -1 dBFS, fIN = 10 kHz, CLOAD_SDO = 20 pF. MCP33111-10: Sample Rate (fS) = 1 Msps, SPI Clock Input (SCLK) = 60 MHz. MCP33111-05: Sample Rate (fS) = 500 kSPS, SPI Clock Input (SCLK) = 30 MHz. 80 80 V REF = 5V 74 72 70 68 66 62 SNR (dB) 74 72 70 68 66 64 SINAD (dB) 60 0 10 76 62 10 1 10 2 10 SNR (dB) SINAD (dB) 60 100 3 101 Input Frequency (kHz) 103 Input Frequency (kHz) FIGURE 4-22: SNR/SINAD vs. Input Frequency: VIN = -1 dBFS. FIGURE 4-19: SNR/SINAD vs. Input Frequency: VIN = -1 dBFS. 99 -91 -92 98 -92 98 -93 97 -93 97 -94 96 -94 96 THD (dB) SFDR (dB) -91 -95 THD (dB) -90 SFDR (dB) 100 -90 THD (dB) 102 100 THD (dB) SFDR (dB) -95 95 95 VREF = 2.5V VREF = 5V -96 -40 -20 0 20 40 60 -96 -40 -20 94 80 100 120 140 20 40 60 94 80 100 120 140 FIGURE 4-23: THD/SFDR vs. Temperature: VREF = 2.5V. FIGURE 4-20: THD/SFDR vs. Temperature: VREF = 5V. -75 110 THD (dB) SFDR (dB) -75 110 THD (dB) SFDR (dB) -80 -85 100 -85 100 -90 95 -90 95 -95 90 -95 90 -100 85 -100 85 80 -105 -105 -110 0 10 VREF = 5V 10 1 10 2 75 3 10 Input Frequency (kHz) FIGURE 4-21: THD/SFDR vs. Input Frequency: VREF = 5V. DS20006122A-page 26 THD (dB) 105 SFDR (dB) THD (dB) 0 Temperature (oC) Temperature (oC) -80 99 SFDR (dB) 64 V REF = 2.5V 78 76 SNR/SINAD (dB) SNR/SINAD (dB) 78 -110 100 105 SFDR (dB) Note: 80 VREF = 2.5V 101 102 75 103 Input Frequency (kHz) FIGURE 4-24: THD/SFDR vs. Input Frequency: VREF = 2.5V.  2018 Microchip Technology Inc. MCP33131/MCP33121/MCP33111-XX Unless otherwise specified, all parameters apply for TA = +25°C, AVDD = 1.8V, DVIO = 3.3V, VREF = 5V, GND = 0V, Differential Analog Input (VIN) = -1 dBFS, fIN = 10 kHz, CLOAD_SDO = 20 pF. MCP33111-10: Sample Rate (fS) = 1 Msps, SPI Clock Input (SCLK) = 60 MHz. MCP33111-05: Sample Rate (fS) = 500 kSPS, SPI Clock Input (SCLK) = 30 MHz. -55 100 -60 -65 95 -65 -70 90 -70 85 VREF = 5V -80 80 -85 75 -90 70 -95 -100 -30 -25 -20 -15 -10 -5 0 -75 105 THD (dB) SFDR (dB) 95 90 -80 80 -85 75 -90 70 65 -95 65 60 -100 -30 -25 5 12
10 -5 0 60 1048574 V REF = 2.5V Occurrences 10 8 6 4 2 8 6 4 2 0 -3 -2 -1 0 1 2 0 -3 3 2 -2 -1 Output Code FIGURE 4-26: VREF = 5V. Shorted Input Histogram: 300 0.25 200 0.16 100 0.08 Offset Error VREF = 5V -20 0 20 40 60 80 0 -0.08 100 120 140 o Temperature ( C) FIGURE 4-27: Offset and Gain Error vs. Temperature: VREF = 5V.  2018 Microchip Technology Inc. Offset/Gain Error (uV) 0.33 Gain Error Offset/Gain Error (LSB) 400 -100 -40 FIGURE 4-29: VREF = 2.5V. 0.41 0 0 1 2 3 Output Code 500 Offset/Gain Error (uV) -10 5 V REF = 5V 1048576 -15 FIGURE 4-28: THD/SFDR vs. Input Amplitude: VREF = 2.5V. 10 Occurrences -20 Input Amplitude (dBFS) FIGURE 4-25: THD/SFDR vs. Input Amplitude: VREF = 5V.
10 85 VREF = 2.5V Input Amplitude (dBFS) 12 100 Shorted Input Histogram: 300 0.49 200 0.33 100 0.16 Offset Error 0 0 Gain Error -100 -0.16 VREF = 2.5V -200 -300 -40 -20 0 20 40 60 80 -0.33 Offset/Gain Error (LSB) THD (dB) -75 THD (dB) 105 THD (dB) SFDR (dB) -60 SFDR (dB) -55 SFDR (dB) Note: -0.49 100 120 140 o Temperature ( C) FIGURE 4-30: Offset and Gain Error vs. Temperature: VREF = 2.5V. DS20006122A-page 27 MCP33131/MCP33121/MCP33111-XX Note: Unless otherwise specified, all parameters apply for TA = +25°C, AVDD = 1.8V, DVIO = 3.3V, VREF = 5V, GND = 0V, Differential Analog Input (VIN) = -1 dBFS, fIN = 10 kHz, CLOAD_SDO = 20 pF. MCP33111-10: Sample Rate (fS) = 1 Msps, SPI Clock Input (SCLK) = 60 MHz. MCP33111-05: Sample Rate (fS) = 500 kSPS, SPI Clock Input (SCLK) = 30 MHz. 8 86 16 VREF = 5V 78 1. 8V ) 8 D (A V D = 4 IIO_STBY (DVIO = 3.3V) Y CMRR (dB) 80 12 Total Power Consumption TB Current (
A) 6 82 4 I D D A N _S 2 Total Power (
W) 84 76 10-2 10-1 100 101 102 103 Temperature (°C) Input Frequency (kHz) FIGURE 4-31: VREF = 5V. CMRR vs. Input Frequency: 2 FIGURE 4-34: Power Consumption vs. Temperature During Shutdown. 2 8 (AV D D l ota n tio mp su I DDAN r we Po n Co 4 T 2 I REF (V REF = 5V) 6 1 ) .8V (AV DD =1 I DDAN 1 4 tion ump 0 0 0.1 Sample Rate (Msps) 0.2 ns r Co we l Po Tota 0.5 2 IREF (VREF = 5V) IIO_DATA (DVIO = 3.3V) ) I IO_DATA (DVIO = 3.3V 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.5 Current (mA) 6 ) .8V =1 Total Power (mW) Current (mA) 1.5 0.5 8 MCP331x1-05 MCP331x1-10 1 0 20 35 50 65 80 95 110 125 Total Power (mW) 74 10-3 IREF_STBY (VREF = 5V) 0 -40 -25 -10 5 0.3 0.4 0 0.5 Sample Rate (Msps) FIGURE 4-35: Power Consumption vs. Sample Rate: CLOAD_SDO = 20 pF. FIGURE 4-32: Power Consumption vs. Sample Rate: CLOAD_SDO = 20 pF. MCP331x1D-10 = 1.8V Total Pow 1.5 1 6 4 IREF (VREF = 5V) 0.5 2 IIO_DATA (DVIO = 3.3V) 0 -40 -25 -10 5 0 20 35 50 65 80 95 110 125 Temperature (°C) FIGURE 4-33: Power Consumption vs. Temperature: CLOAD_SDO = 20 pF. DS20006122A-page 28 1.5 Current (mA) ption er Consum 8 Total Power (mW) (AV DD 8 MCP331x1-05 ) I DDAN 2 Current (mA) 2 10 MCP331x1-10 1 I DDAN (AV DD Total Power = 1.8V) Consumption 0.5 6 4 2 Total Power (mW) 2.5 IREF (VREF = 5V) 0 -40 -25 -10 5 IIO_DATA (DVIO = 3.3V) 0 20 35 50 65 80 95 110 125 Temperature (°C) FIGURE 4-36: Power Consumption vs. Temperature: CLOAD_SDO = 20 pF.  2018 Microchip Technology Inc. MCP33131/MCP33121/MCP33111-XX 5.0 PIN FUNCTION DESCRIPTIONS TABLE 5-1: PIN FUNCTION TABLE Pin Number Pin Name Function 1 VREF 2 AVDD 3 4 AIN+ AIN- 5 GND 6 CNVST 7 SDO 8 SCLK 9 10 SDI DVIO Reference voltage input (2.5V - 5.1V). This pin should be decoupled with a 10 F tantalum capacitor. DC supply voltage input for analog section (1.8V). This pin should be decoupled with a 1 F ceramic capacitor. Analog input. Ground reference pin for analog input. Connect this pin to the ground reference of the analog input. Power supply ground reference. This pin is a common ground for both the analog power supply (AVDD) and digital I/O supply (DVIO). Conversion-start control and active-low SPI chip-select digital input. A new conversion is started on the rising edge of CNVST. When the conversion is complete, output data is available at SDO by lowering CNVST. SPI-compatible serial digital data output: ADC conversion data is shifted out by SCLK clock, with MSB first. SPI-compatible serial data clock digital input. The ADC output is synchronously shifted out by this clock. SPI-compatible serial data digital input. Tie to DVIO for normal operation. DC supply voltage for digital input/output interface (1.7V - 5.5V). This pin should be decoupled with a 0.1 F ceramic capacitor. 5.1 Supply Voltages (AVDD, DVIO) Note: The reference pin needs a tantalum decoupling capacitor (10 F, 10V rating). Additional multiple ceramic capacitors can be added in parallel to decouple high-frequency noises. Note: During the initial power-up sequence, the reference voltage (VREF) must be provided prior to supplying AVDD or within about 64 ms after supplying AVDD. Otherwise, it is strongly recommended to send a recalibrate command. See Section 7.1 “Recalibrate Command” for more details. The device has two power supply pins: (a) Analog power supply (AVDD): 1.8V (b) Digital input/output interface power supply (DVIO): 1.7V to 5.5V. The large supply voltage range of DVIO allows the device to interface with various host devices that are operating with different supply voltages. See Table 1-2 for timing specifications for I/O interface signal parameters depending on DVIO voltage. Note: 5.2 Proper decoupling capacitors (1 F to AVDD, 0.1 F to DVIO) should be mounted as close as possible to the respective pins. See Figure 6-1 for example circuit. Reference Voltage (VREF) The device requires a single-ended external reference voltage (VREF). The external input reference range is from 2.5V to 5.1V. This reference voltage sets the input full-scale range from 0V to VREF. See Figure 6-1 to Figure 6-2 for example application circuit and reference voltage settings.  2018 Microchip Technology Inc. 5.2.1 VOLTAGE REFERENCE SELECTION The performance of the voltage reference has a large impact on the accuracy of high-precision data acquisition systems. The voltage reference should have high-accuracy, low-noise, and low-temperature drift. A ±0.1% output accuracy of the reference directly corresponds to ±0.1% absolute accuracy of the ADC output. The RMS output noise voltage of the reference should be less than 1/2 LSB of the ADC. DS20006122A-page 29 MCP33131/MCP33121/MCP33111-XX 6.0 DEVICE OVERVIEW The device converts unipolar single-ended analog input into unipolar straight binary codes. time. Although the device can be driven directly with a low impedance source, using a low noise input driver is highly recommended. When the MCP33131/MCP33121/MCP33111-XX is first powered-up, it performs a self-calibration and enters a low current input acquisition mode (Standby) by itself. The external reference voltage (VREF) ranging from 2.5V to 5.1V sets the input full-scale range (FSR) from 0V to +VREF. MCP331x1-XX VREF The device initiates data conversion on the rising edge of the conversion-start control (CNVST). The data conversion time (tCNV) is set by the internal clock. Once the conversion is complete, the device starts the next input acquisition. During this input acquisition time (tACQ), the user can clock out the output data by providing the external SPI serial clock (SCLK). The device provides conversion data with no missing codes. This ADC device family has a large input full-scale range, high precision, high throughput with no output latency, and is an ideal choice for various ADC applications. Sample VIN+ SW1+ AIN+ CPIN During input acquisition (Standby), the internal input sampling capacitors are connected to the input signal, while most of the internal analog circuits are shutdown to save power. During this input acquisition time (tACQ), the device consumes less than 1 A. The user can operate the device with an easy-to-use SPI-compatible 3-wire interface. VT = 0.6V D1 RSON CS+ (200 ) (31 pF) SW2+ ILEAKAGE (~ ±1 nA) D2 VREF D1 AIN- VT = 0.6V Sample VINSW1- CPIN D2 RSON CS- (200 ) (31 pF) SW2- ILEAKAGE (~ ±1 nA) where: CS+ , CS- = Input sample and hold capacitor ≈ 31 pF. RSON = On-resistance of the sampling switch ≈ 200  CPIN = Package pin + ESD capacitor ≈ 2 pF. AIN+ = Analog input. AIN- = Ground reference of analog input. Simplified Equivalent Analog Input Circuit. 6.1 Analog Input Figure shows a simplified equivalent circuit of the input architecture with a switched capacitor input stage. The input sampling capacitor (CS+) is about 31 pF. The back-to-back diodes (D1 - D2) at each input pin are ESD protection diodes. Note that these ESD diodes are tied to VREF, so that each input signal can swing from 0V to VREF. The input sampling and hold circuit in AIN+ path is also repeated in AIN- path. This allows the device to perform a pseudo-differential conversion of the input signal. Therefore, the common mode signal presented at both input pins is rejected. In applications, AIN+ pin is for the input signal and AIN- pin is for the ground reference of the input signal. The user must connect the AIN- pin to a clean ground plane of the input signal externally. Note: The ESD diodes at the analog input pins are biased from VREF. Any input voltage outside the absolute maximum range can turn on the input ESD protection diodes and results in input leakage current which may cause conversion errors and permanent damage to the device. Care must be taken in setting the input voltage ranges so that the input voltage does not exceed the absolute maximum input voltage range. During input acquisition phase (Standby), the sampling switches are closed and each input sees the sampling capacitor (≈ 31 pF) in series with the on-resistance of the sampling switch, RSON (≈ 200). For high-precision data conversion applications, the input voltage needs to be fully settled within 1/2 LSB during the input acquisition period (tACQ). The settling time is directly related to the source impedance: A lower impedance source results in faster input settling DS20006122A-page 30  2018 Microchip Technology Inc. MCP33131/MCP33121/MCP33111-XX 6.1.1 6.2 INPUT VOLTAGE RANGE The device has two analog input pins: AIN+ and AINpins. The analog input signal is applied to the AIN+ pin, and the ground reference of the input signal is tied to the AIN- pin. The MCP33131/MCP33121/MCP33111-XX can be driven directly when the source impedance of the input driver is low. Large source impedance of the input signal may affect the ADC’s performance. In general, the source impedance is less sensitive to the ADC’s DC performances such as INL and DNL. However, it affects significantly to the dynamic performances such as THD, SFDR and SNR. The voltage difference between AIN+ and AIN- is the ADC input (VIN) and needs to be between 0V and +VREF to produce unsaturated output codes. Equation 6-4 shows the input full-scale range (FSR) and input range. The device will output unipolar straight binary codes for the analog input. If the input (VIN) is greater than the reference voltage (VREF), the output code will be saturated. If the input (VIN) is less than or equals to 0V, the output will be all 0’s. EQUATION 6-1: Input Range: where VIN = AIN+ Therefore, it is a good design practice to isolate the ADC input from the high impedance source using a low noise input driver amplifier. Figure 6-1 shows an input configuration example using a low-noise OP amplifier such as MCP6286 and Figure 6-2 shows the transfer function of the MCP33131/MCP33121/MCP33111-XX. FSR AND INPUT RANGE Input Full-Scale Range (FSR) = Analog Input Conditioning Circuit VREF 0V  V IN   VREF – 1LSB  - AIN- VREF 2.5V to 5.1V Voltage Reference VDC MCP1501 (Note 2) 0.1 F R1 0V AIN+ (22 ±0.1%) Analog Input MCP6286 (Note 1) 0.1 F VREF 1 1 0V 1.7V to 5.5V 10 F (Tantalum) fC = 2R1 C VREF 1.8V CR C1 (1.7nF, NPO) VREF AVDD DVIO SDI VIN MCP331x1-XX 0V (PIC32MZ) SCLK AIN- Ground Reference of Analog Input Host Device CNVST GND SDO Note 1: Contact Microchip Technology Inc. for more selections of the low-noise input driver amplifiers. 2: Contact Microchip Technology Inc. for the MCP1501 application circuit. FIGURE 6-1: Unipolar-Input Application Example Digital Output Code 2n - 1 2n/2 0 +VREF/2 +VREF VIN (V) Analog Input Voltage VIN range FIGURE 6-2: Transfer Function for Figure 6-1.  2018 Microchip Technology Inc. DS20006122A-page 31 MCP33131/MCP33121/MCP33111-XX 6.3 ADC Input Driver Selection • ADC Input-Referred Noise: The noise and distortion of the ADC input driver can degrade the dynamic performance (SNR, SFDR, and THD) of the overall ADC application system. Therefore, the ADC input driver needs better performance specifications than the ADC itself. The data sheet of the driver typically shows the output noise voltage and harmonic distortion parameters. Figure 6-3 shows a simplified system noise presentation block diagram for the front-end driver and ADC. When the ADC is operating with a full-scale input range, the ADC input-referred RMS noise for a single-ended input configuration is approximated as shown in Equation 6-4. EQUATION 6-4: ADC INPUT-REFERRED NOISE VN_ADC Input-Referred Noise = V REF -------------- 10 2 2 SNR – ----------20 (V) • Noise Contribution from the Front-End Driver: ADC Input Driver -+ R -+ ADC C VN_RMS_Driver Noise FIGURE 6-3: Representation. VN_ADC Input-Referred Noise Simplified System Noise • Unity-Gain Bandwidth: An input driver with higher bandwidth usually results in better overall linearity performance. Typically, the driver should have the unity-gain bandwidth greater than 5 times the -3 dB cutoff frequency of the anti-aliasing filter: EQUATION 6-2: BANDWIDTH REQUIREMENT FOR ADC INPUT DRIVER BWInput Driver  5 x f B 5  --------------2RC (Hz) for a single-pole RC filter where, fB = -3 dB bandwidth of RC anti-aliasing filter as shown in Figure 6-3. • Distortion: The nonlinearity characteristics of the input driver cause distortions in the ADC output. Therefore, the input driver should have less distortion than the ADC itself. The recommended total harmonic distortion (THD) of the driver is at least 10 dB less than that of the ADC: EQUATION 6-3: THDInput Buffer DS20006122A-page 32 RECOMMENDED THD FOR ADC INPUT DRIVER ≤ THDADC -10 (dB) The noise from the input driver can degrade the ADC’s SNR performance. Therefore, the selected input driver should have the lowest possible broadband noise density and 1/f noise. When an anti-aliasing filter is used after the input driver, the output noise density of the input driver is integrated over the -3 dB bandwidth of the filter. Equation 6-5 shows the RMS output noise voltage calculation using the RC filter’s bandwidth and noise density (eN) of the input driver. GN in Equation 6-5 is the noise gain of the driver amplifier and becomes 1 for a unity gain buffer driver. EQUATION 6-5: VN_RMS_Driver Noise NOISE FROM FRONT-END DRIVER AMPLIFIER eN  G N -------  f B 2 (V) where eN is the broadband noise density (V/√Hz) of the front-end driver amplifier and is typically given in its data sheet. In Equation 6-5, 1/f noise (eNFlicker) is ignored assuming it is very small compared to the broadband noise (eN). For high precision ADC applications, the noise contribution from the front-end input driver amplifier is typically constrained to be less than about 20% (or 1/5 times) of the ADC input-referred noise as shown in Equation 6-6: EQUATION 6-6: RECOMMENDED ADC INPUT DRIVER NOISE VN_RMS_Driver Noise  1--- VN_ADC Input-Referred Noise 5 Using Equation 6-4 to Equation 6-6, the recommended noise voltage density (eN) limit of the ADC input driver is expressed in Equation 6-7:  2018 Microchip Technology Inc. MCP33131/MCP33121/MCP33111-XX EQUATION 6-7: eN G N -------  f B 2 eN NOISE DENSITY FOR ADC INPUT DRIVER 1 1  ------ -------------------------10 G  fB N V REF 10 SNR – ----------20 TABLE 6-1: RC Filter ADC ADC SNR fB Input-Referred (Table 2) (dBFS) Noise 3 MHZ 2.5V 3.3V 5V Note 81 83 87 1: 2: 78.8V 82.6 V 79 V V   --------- Hz VREF Noise Voltage Density (eN) ADC SNR fB Input-Referred (Note 2) (dBFS) Noise 2.5V 3.3V 5V Note 80 6.3 nV/√Hz 5.6 nV/√Hz 3 MHZ 7.6 nV/√Hz 4 MHz 6.6 nV/√Hz 5 MHZ 5.9 nV/√Hz 3 MHZ 7.3 nV/√Hz 4 MHz 6.3 nV/√Hz 5 MHZ 5.6 nV/√Hz See Equation 6-4 for the ADC input-referred noise calculation for single-ended input. fB is -3dB bandwidth of the RC anti-aliasing filter. 98.2 V 118.1 V 83.5 1: ADC 2.5V 3.3V 5V Note ADC SNR Input-Referred (dBFS) Noise 73.2 73.5 73.8 1: 2: Noise Voltage Density (eN) 3 MHZ 8.1 nV/√Hz 4 MHz 7.1 nV/√Hz 5 MHZ 6.3 nV/√Hz 3 MHZ 9.0 nV/√Hz 4 MHz 7.8 nV/√Hz 5 MHZ 7.0 nV/√Hz 3 MHZ 10.9 nV/√Hz 4 MHz 9.4 nV/√Hz 5 MHZ 8.4 nV/√Hz Noise Voltage Density (eN) of Input Driver for MCP33111-XX (Note 1) VREF ADC Input Driver Amplifier (GN = 1) See Equation 6-4 for the ADC input-referred noise calculation for single-ended input. fB is -3dB bandwidth of the RC anti-aliasing filter. TABLE 6-3: 7.3 nV/√Hz 5 MHZ 88.4V 81.5 2: ADC Input Driver Amplifier (GN = 1) 4 MHz  2018 Microchip Technology Inc. RC Filter (Note 1) Noise Voltage Density (eN) of Input Driver for MCP33131-XX (Note 1) Noise Voltage Density (eN) of Input Driver for MCP33121-XX ADC 1 5  --- VN_ADC Input-Referred Noise Using Equation 6-7, the recommended maximum noise voltage density limit for unity gain input driver for single-ended input ADC can be estimated. Table 6-1 to Table 6-3 show a few example results with GN = 1. The user may use these tables as a reference when selecting the ADC input driver amplifier. VREF TABLE 6-2: 193.3V 246.6 V 360.9 V RC Filter ADC Input Driver Amplifier (GN = 1) (Note 2) fB Noise Voltage Density (eN) 3 MHZ 17.8 nV/√Hz 4 MHz 15.4 nV/√Hz 5 MHZ 13.8 nV/√Hz 3 MHZ 22.7 nV/√Hz 4 MHz 19.7 nV/√Hz 5 MHZ 17.6 nV/√Hz 3 MHZ 33.3 nV/√Hz 4 MHz 28.8 nV/√Hz 5 MHZ 25.8 nV/√Hz See Equation 6-4 for the ADC input-referred noise calculation for single-ended input. fB is -3dB bandwidth of the RC anti-aliasing filter. DS20006122A-page 33 MCP33131/MCP33121/MCP33111-XX 6.4 Device Operation 6.4.2 The start of the conversion is controlled by CNVST. On the rising edge of CNVST, the sampled charge is locked (sample switches are opened) and the ADC performs the conversion. Once a conversion is started, it will not stop until the current conversion is complete. The data conversion time (tCNV) is not user-controllable. After the conversion is complete and the host lowers CNVST, the output data is presented on SDO. When the MCP33131/MCP33121/MCP33111-XX is first powered-up, it self-calibrates internal systems and enters input acquisition mode by itself. The device operates in two phases: (a) Input Acquisition (Standby) and (b) Data Conversion. Figure 6-4 shows the ADC operating sequence. 6.4.1 DATA CONVERSION PHASE INPUT ACQUISITION PHASE (STANDBY) Any noise injection during the conversion phase may affect the accuracy of the conversion. To reduce environment noise, minimize I/O events and running clocks during the conversion time. During the input acquisition phase (tACQ), also called Standby, the two input sampling capacitors, CS+ and CS-, are connected to the AIN+ and AIN- pins, respectively. The input voltage is sampled until a rising edge on CNVST is detected. The input voltage should be fully settled within 1/2 LSB during tACQ. The output data is clocked out MSB first. While the output data is being transferred, the device enters the next input acquisition phase. During this input acquisition time (tACQ), the ADC consumes less than 1 A. The acquisition time (tACQ) is user-controllable. This acquisition time (tACQ) can be increased as long as needed for additional power savings. Note: Transferring output data during the acquisition phase can disturb the next input sample. It is highly recommended to allow at least tQUIET (10 ns, typical) between the last edge on the SPI interface and the rising edge on CNVST. See Figure 1-1 for tQUIET. tCYC = 1/fS Input Acquisition (Standby) Operating Condition IDDAN Data Conversion tACQ MCP331x1-10: 300 ns (typical) MCP331x1-05: 800 ns (typical) tCNV MCP331x1-10: 700 ns (typical) MCP331x1-05: 1200 ns (typical) Input Acquisition (Standby) tACQ MCP331x1-10: 300 ns (typical) MCP331x1-05: 800 ns (typical) (a) ADC acquires input sample #1. (a) Conversion is initiated at the rising edge of CNVST. (a) At the falling edge of CNVST, ADC output is available at SDO. (b) No ADC output is available yet. (b) All circuits are turned-on. (b) ADC output can be clocked out (c) Most analog circuits are (c) ADC output is not available yet. by providing clocks. turned off. (c) ADC acquires input sample #2. MCP331x1-10: ~ 1.6 mA (d) Most analog circuits are turned off. MCP331x1-05: ~ 1.4 mA I Off ~ 0.8 A (a) Device is first powered-up and (b) Performs a power-up self-calibration. Output Data SDO FIGURE 6-4: DS20006122A-page 34 Device Operating Sequence.  2018 Microchip Technology Inc. MCP33131/MCP33121/MCP33111-XX 6.4.3 SAMPLE (THROUGHPUT) RATE EQUATION 6-9: The device completes data conversion within the maximum specification of the data conversion time (tCNV). The continuous input sample rate is the inverse of the sum of input acquisition time (tACQ) and data conversion time (tCNV). Equation 6-8 shows the continuous sample rate calculation using the minimum and maximum specifications of the input acquisition time (tACQ) and data conversion time (tCNV). EQUATION 6-8: tACQ = N  T SCLK + t QUIET + t EN 1 N f SCLK = --------------- = -----------------------------------------------------T SCLK tACQ –  t QUIET + tEN  where N is the number of output data bits, given by N SAMPLE RATE 1 Sample Rate = --------------------------------- t ACQ + tCNV  (a) MCP331x1-10: 1 Sample Rate = ----------------------------------------- = 1 Msps  290ns + 710ns  TABLE 6-4: Input Acquisition Time: tACQ (nS) (Note 4) 14-bit for MCP33121-XX 12-bit for MCP33111-XX = Period of SPI clock N x TSCLK = Output data window tQUIET = Quiet time between the last output bit and beginning of the next conversion start. = 10 ns (min) = Output enable time = 10 ns (max), with DVIO ≥2.3V tEN Note: See Figure 1-1 for digital interface timing diagram. where fSCLK is the minimum SPI serial clock frequency required to transfer all N-bits of output data during input acquisition time (tACQ). Table 6-4 and Table 6-5 show the examples of calculated minimum SPI clock (fSCLK) requirements for various input acquisition times for 1 Msps and 500 kSPS family devices, respectively. SPI CLOCK SPEED VS. INPUT ACQUISITION TIME (TACQ) FOR MCP331X1-10 Data Conversion Time: tCNV (nS) (Note 5) SPI Clock (fSCLK) Speed Requirement (Note 1), (Note 2) Sample Rate: fS (Msps) MCP33131-10 (16-bit) MCP33121-10 (14-bit) MCP33111-10 (12-bit) 250 69.57 MHz 60.87 MHz 52.17 MHz 1 270 64 MHz 56 MHz 48 MHz 0.98 0.97 750 280 61.54 MHz 53.85 MHz 46.15 MHz 290 59.26 MHz 51.85 MHz 44.44 MHz 1 300 57.15 MHz 50 MHz 42.86 MHz 0.99 320 53.33 MHz 46.67 MHz 40 MHz 0.97 400 42.11 MHz 36.84 MHz 30 MHz 0.9 540 30.77 MHz 26.92 MHz 23.08 MHz 0.8 22.86 MHz 20 MHz 17.14 MHz 0.7 720 17.2 MHz 15.05 MHz 12.9 MHz 0.6 1290 12.6 MHz 11.02 MHz 9.45 MHz 0.5 1750 9.04 MHz 7.91 MHz 6.78 MHz 0.4 2620 6.15 MHz 5.39 MHz 4.62 MHz 0.3 4290 3.75 MHz 3.28 MHz 2.81 MHz 0.2 9290 1.73 MHz 1.51 MHz 1.3 MHz 0.1 720 Note 16-bit for MCP33131-XX = = SERIAL SPI CLOCK FREQUENCY REQUIREMENT The ADC output is collected during the input acquisition time (tACQ). For continuous input sampling and data conversion sequence, the SPI clock frequency should be fast enough to clock out all output data bits during the input acquisition time (tACQ). For the continuous sampling rate (fS), the minimum SPI clock frequency requirement is determined by the following equation: = TSCLK (b) MCP331x1-05: 1 Sample Rate = -------------------------------------------- = 500 kSPS  700ns + 1300ns  6.4.4 SPI CLOCK FREQUENCY REQUIREMENT 1: 2: 3: 4: 5: 710 Conditions 85°C < TA ≤ 125°C (Note 3) -40°C ≤ TA ≤ 85°C This is the minimum SPI clock speed requirement to collect all N-bits of the ADC output during the input acquisition time (tACQ), when the ADC is operating in continuous input sampling mode. See Equation 6-9 for the calculation of the SPI clock speed requirement. In extended temperature range, the device takes longer data conversion time (tCNV: 750 nS, max). Using a shorter input acquisition time is recommended (tACQ: 250 nS) for 1 Msps throughput rate. Input acquisition time (tACQ) is user-controllable. Data conversion time (tCNV) is not user-controllable.  2018 Microchip Technology Inc. DS20006122A-page 35 MCP33131/MCP33121/MCP33111-XX TABLE 6-5: SPI CLOCK SPEED VS. INPUT ACQUISITION TIME (TACQ) FOR MCP331X1-05 Input Acquisition Time: tACQ (nS) (Note 3) Data Conversion Time: tCNV (nS) (Note 4) (Note 1), (Note 2) MCP33131-05 (16-bit) MCP33121-05 (14-bit) MCP33111-05 (12-bit) Sample Rate: fS (kSPS) 700 23.53MHz 20.59 MHz 17.65 MHz 500 740 22.22 MHz 19.44 MHz 16.67 MHz 490 790 20.78 MHz 18.18 MHz 15.58 MHz 480 17.58 MHz 15.39 MHz 13.19 MHz 450 13.56 MHz 11.86 MHz 10.17 MHz 400 1560 10.39 MHz 9.09 MHz 7.79 MHz 350 2030 7.96 MHz 6.97 MHz 5.97 MHz 300 2700 5.97 MHz 5.22MHz 4.48 MHz 250 3700 4.35 MHz 3.8 MHz 3.26 MHz 200 5370 2.99 MHz 2.62 MHz 2.25 MHz 150 8700 1.84 MHz 1.61 MHz 1.38 MHz 100 930 1300 1200 Note SPI Clock (fSCLK) Speed Requirement 1: -40°C ≤ TA ≤ 125°C This is the minimum SPI clock speed requirement to collect all N-bits of the ADC output during the input acquisition time (tACQ), when the ADC is operating in continuous input sampling mode. See Equation 6-9 for the calculation of the SPI clock speed requirement. Input acquisition time (tACQ) is user-controllable. Data conversion time (tCNV) is not user-controllable. 2: 3: 4: 6.5 Conditions Transfer Function 311.3 V 1.2451 mV Figure 6-5 shows the ideal transfer function and Table 6-7 shows the digital output codes for the MCP33131/MCP33121/MCP33111-XX. The pseudo-differential analog input is: VIN = (VIN+) - (VIN-) where VIN+ is the analog input voltage at AIN+ pin with respect to the ground reference (GND), and Vin- is the voltage at AIN- pin, which is 0V when tied to the analog input ground reference (GND). The LSB size is given by Equation 6-10. and an example of LSB size vs. reference voltage is summarized in Table 6-6. EQUATION 6-10: 77.8 V 5.1 LSB SIZE - EXAMPLE Digital Output Code (Unipolar Straight Binary) 111 ...111 111 ...110 100 ...000 V REF LSB = -----------N 2 where N is the resolution of the ADC in bits. 000 ...001 TABLE 6-6: Reference Voltage (VREF) LSB SIZE VS. REFERENCE LSB Size 0V MCP33131-XX (16-bit) MCP33121-XX (14-bit) MCP33111-XX (12-bit) 2.5V 38.2V 152.6 V 0.6104 mV 2.7V 41.2 V 164.8 V 0.6592 mV 3V 45.8 V 183.1 V 0.7324 mV 3.3V 50.4 V 201.4 V 0.8057 mV 3.5V 53.4 V 213.6 V 0.8545 mV 4V 61.0 V 244.1 V 0.9766 mV 4.5V 68.7 V 274.7 V 1.0986 mV 5V 76.3 V 305.2 V 1.2207 mV DS20006122A-page 36 000 ...000 0V+ 1 LSB VREF 2 VREF - 1.5 LSB VREF - 1 LSB 0V + 0.5 LSB Analog Input Voltage FIGURE 6-5: Ideal Transfer Function.  2018 Microchip Technology Inc. MCP33131/MCP33121/MCP33111-XX 6.6 Digital Output Code The digital output code is proportional to the input voltage. The output data is in unipolar straight binary format. The following is an example of the output code: (a) for a zero or negative input: Analog Input: VIN ≤ 0 (V) Output Code: 0000...0000 (b) for a mid-scale input: Analog Input: VIN = +VREF /2 (V) Output Code: 1000...0000 (c) for a positive full-scale input: Analog Input: VIN = +VREF (V) Output Code: 1111...1111 The code will be locked at 1111...11 for all voltages greater than (VREF - 1 LSB) and 0000...00 for voltages less than 0V. Table 6-7 shows an example of output codes of various input levels. TABLE 6-7: DIGITAL OUTPUT CODE Digital Output Codes Input Voltage (V) MCP33131-XX (16-bit) MCP33121-XX (14-bit) MCP33111-XX (12-bit) VREF 1111-1111-1111-1111 11-1111-1111-1111 1111-1111-1111 VREF - 1 LSB 1111-1111-1111-1111 11-1111-1111-1111 1111-1111-1111 . . . . . . . . VREF/2 1000-0000-0000-0000 10-0000-0000-0000 1000-0000-0000 . . . . . . . . 2 LSB 0000-0000-0000-0010 00-0000-0000-0010 0000-0000-0010 1 LSB 0000-0000-0000-0001 00-0000-0000-0001 0000-0000-0001 ≤ 0V 0000-0000-0000-0000 00-0000-0000-0000 0000-0000-0000  2018 Microchip Technology Inc. DS20006122A-page 37 MCP33131/MCP33121/MCP33111-XX 7.0 DIGITAL SERIAL INTERFACE SDO returns to high-Z state after the last data bit is clocked out or when CNVST goes high, whichever occurs first. The device has a SPI-compatible serial digital interface using four digital pins: CNVST, SDI, SDO and SCLK. Figure 7-1 shows the connection diagram with the host device and Figure 7-2 shows the SPI-compatible serial interface timing diagram. CS DVIO DVIO The SDI pin can be tied to the digital I/O interface supply voltage (DVIO) or just maintain logic “High” level by the host. The CNVST pin is used for both chip select (CS) and conversion-start control. CNVST SDI SDO SCLK A rising edge on CNVST initiates the conversion process. Once the conversion is initiated, the device will complete the conversion regardless of the state of CNVST. This means the CNVST pin can be used for other purposes during tCNV. SDI 10 k (Note 1) SCLK (b) Host Device (Master) (a) MCP33131/21/11-XX Note 1: Adding this pull-up is needed when monitoring status of Recalibrate. When the conversion is complete, the output is available at SDO by lowering CNVST. Data is sent MSB-first and changes on the falling edge of SCLK. FIGURE 7-1: Diagram. Output data can be sampled on either edge of SCLK. However, a digital host capturing data on the falling edge of SCLK can achieve a faster read out rate. Digital Interface Connection tCYC = 1/fS SDI = DVIO (Note 1) tCNVH (a) Exit input acquisition mode and (b) Enter new conversion mode tSU_SDIH_CNV CNVST tSCLK (Note 2) 1 SCLK 2 (Note 5) 3 4 tDO 14 tSCLK_L 15 tSCLK_H 16 tQUIET tDIS Hi-Z SDO tCNV (MAX) D14 D13 D12 D2 D1 D0 Hi-Z tEN (Note 3) tEN (Note 4) ADC State Input Acquisition (tACQ) D15 (MSB) Conversion (tCNV) Input Acquisition (tACQ) Note 1: SDI must maintain “High” during the entire tCYC. 2: Any SCLK toggling events (dummy clocks) before CNVST is changed to “Low” are ignored. 3: tEN when CNVST is lowered after tCNV (Max). 4: tEN when CNVST is lowered before tCNV (Max). 5: Recommended data detection: Detect SDO on the falling edge of SCLK. FIGURE 7-2: DS20006122A-page 38 SPI Compatible Serial Interface Timing Diagram (16-bit device).  2018 Microchip Technology Inc. MCP33131/MCP33121/MCP33111-XX 7.1 Recalibrate Command A self-calibration is initiated by sending the recalibrate command. The host device sends a recalibrate command by transmitting 1024 SCLK pulses (including the clocks for data bits) while the device is in the acquisition phase (Standby). The user may use the recalibrate command in the following cases: • When the reference voltage was not fully settled during the first-power sequence. • During operation, to ensure optimum performance across varying environment conditions, such as reference voltage and temperature. The device drives SDO low during the recalibration procedure, and returns to high-Z once completed. The status of the recalibration procedure can be monitored by placing a pull-up on SDO, so that SDO goes high when the recalibration is complete. Figure 7-3 shows the recalibrate command timing diagram. The calibration takes approximately 500 ms (tCAL). (Note 1) SDI = DVIO Start recalibration Finish recalibration Complete data reading Device Recalibration CNVST 1024 clocks (SPITM Recalibrate command) 2 1 3 1024 15 16 SCLK tCAL (Note 2) “High” with Pull-up SDO “High” with Pull-up “Low” ADC Output Data Stream Hi-Z Hi-Z Hi-Z (Note 3) ADC State (Note 4) tCNV Note 1: SDI must remain “High” during the entire recalibration cycle. 2: The 1024 clocks include the clocks for data bits. 3: SDO outputs “Low” during calibration, and Hi-Z when exiting the calibration. 4: After finishing the recalibration procedure, the device is ready for a new input sampling immediately. FIGURE 7-3: Note: Recalibrate Command Timing Diagram. When the device performs a self-calibration, it is important to note that both AVDD and the reference voltage (VREF) must be stabilized for a correct calibration. This is also true when the device is first powered-up, the reference voltage (VREF) must be stabilized before self-calibration begins. This means the VREF must be provided prior to supplying AVDD or within about 64 ms after supplying AVDD.  2018 Microchip Technology Inc. DS20006122A-page 39 MCP33131/MCP33121/MCP33111-XX NOTES: DS20006122A-page 40  2018 Microchip Technology Inc. MCP33131/MCP33121/MCP33111-XX 8.0 TERMINOLOGY Analog Input Bandwidth (Full-Power Bandwidth) The analog input frequency at which the spectral power of the fundamental frequency (as determined by FFT analysis) is reduced by 3 dB. Aperture Delay or Sampling Delay This is the time delay between the rising edge of the CNVST input and when the input signal is held for a conversion. Differential Nonlinearity (DNL, No Missing Codes) An ideal ADC exhibits code transitions that are exactly 1 LSB apart. DNL is the deviation from this ideal value. No missing codes to 16-bit resolution indicates that all 65,536 codes (16,384 codes for 14-bit, 4096 codes for 12-bit) must be present over all the operating conditions. EQUATION 8-2:  PS  SINAD = 10 log  ----------------------  PD + P N = – 10 log 10 SNR – ----------10 – 10 THD – -----------10 SINAD is either given in units of dBc (dB to carrier), when the absolute power of the fundamental is used as the reference, or dBFS (dB to full-scale), when the power of the fundamental is extrapolated to the converter full-scale range. Effective Number of Bits (ENOB) The effective number of bits for a sine wave input at a given input frequency can be calculated directly from its measured SINAD using the following formula: EQUATION 8-3: SINAD – 1.76 ENOB = ---------------------------------6.02 Integral Nonlinearity (INL) Gain Error INL is the maximum deviation of each individual code from an ideal straight line drawn from negative full scale through positive full scale. Gain error is the deviation of the ADC’s actual input full-scale range from its ideal value. The gain error is given as a percentage of the ideal input full-scale range. Gain error is usually expressed in LSB or as a percentage of full-scale range (%FSR). Signal-to-Noise Ratio (SNR) SNR is the ratio of the power of the fundamental (PS) to the noise floor power (PN), below the Nyquist frequency and excluding the power at DC and the first nine harmonics. EQUATION 8-1:  PS  SNR = 10 log  -------  PN SNR is either given in units of dBc (dB to carrier), when the absolute power of the fundamental is used as the reference, or dBFS (dB to full-scale), when the power of the fundamental is extrapolated to the converter full-scale range. Signal-to-Noise and Distortion (SINAD) SINAD is the ratio of the power of the fundamental (PS) to the power of all the other spectral components including noise (PN) and distortion (PD) below the Nyquist frequency, but excluding DC:  2018 Microchip Technology Inc. Offset Error Offset error is the difference between the ideal voltage (0V + 0.5 LSB) that produces the first code transition (“000... 000” to “000... 001”) and the actual voltage producing that code. Temperature Drift The temperature drift for offset error and gain error specifies the maximum change from the initial (+25°C) value to the value at across the TMIN to TMAX range. The value is normalized by the reference voltage and expressed in V/oC or ppm/oC. Maximum Conversion Rate The maximum clock rate at which parametric testing is performed. Spurious-Free Dynamic Range (SFDR) SFDR is the ratio of the power of the fundamental to the highest other spectral component (either spur or harmonic). SFDR is typically given in units of dBc (dB to carrier) or dBFS. DS20006122A-page 41 MCP33131/MCP33121/MCP33111-XX Total Harmonic Distortion (THD) THD is the ratio of the power of the fundamental (PS) to the summed power of the first 13 harmonics (PD). EQUATION 8-4:  PS  THD = 10 log  --------  PD THD is typically given in units of dBc (dB to carrier). THD is also shown by: EQUATION 8-5: 2 2 2 2 V2 + V 3 + V 4 +  + V n THD = – 20 log -----------------------------------------------------------------2 V1 Where: V1 = RMS amplitude of the fundamental frequency V1 through Vn = Amplitudes of the second through nth harmonics Common-Mode Rejection Ratio (CMRR) Common-mode rejection is the ability of a device to reject a signal that is common to both sides of a differential or pseudo-differential input pair. The common-mode signal can be an AC or DC signal or a combination of the two. CMRR is measured using the ratio of the differential signal gain to the common-mode signal gain and expressed in dB with the following equation: EQUATION 8-6: Where:  A DIFF CMRR = 20 log  ------------------  ACM  ADIFF = Output Code/Differential Voltage ADIFF = Output Code/Common-Mode Voltage DS20006122A-page 42  2018 Microchip Technology Inc. MCP33131/MCP33121/MCP33111-XX 9.0 PACKAGING INFORMATION 9.1 Package Marking Information Example 10-Lead MSOP (3x3 mm) Corresponding Part Number: 31-10 = MCP33131-10 31-05 = MCP33131-05 21-10 = MCP33121-10 21-05 = MCP33121-05 11-10 = MCP33111-10 11-05 = MCP33111-05 10-Lead TDFN (3x3x0.9 mm) 31-10 839256 Example Corresponding Part Number: XXXX YYWW NNN PIN 1 = MCP33131-10 = MCP33131-05 211 = MCP33121-10 210 = MCP33121-05 111 = MCP33111-10 110 = MCP33111-05 311 1839 256 PIN 1 Legend: XX...X Y YY WW NNN e3 * Note: 311 310 Customer-specific information Year code (last digit of calendar year) Year code (last 2 digits of calendar year) Week code (week of January 1 is week ‘01’) Alphanumeric traceability code Pb-free JEDEC® designator for Matte Tin (Sn) This package is Pb-free. The Pb-free JEDEC designator ( e3 ) can be found on the outer packaging for this package. In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information.  2018 Microchip Technology Inc. DS20006122A-page 43 MCP33131/MCP33121/MCP33111-XX 10-Lead Plastic Micro Small Outline Package (MS) [MSOP] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging 0.20 H D D 2 A N E 2 E1 2 E1 E 0.20 H 1 0.25 C 2 e B 8X b 0.13 C A B TOP VIEW H C SEATING PLANE A2 A 8X A1 0.10 C SEE DETAIL A SIDE VIEW END VIEW Microchip Technology Drawing C04-021D Sheet 1 of 2 DS20006122A-page 44  2018 Microchip Technology Inc. MCP33131/MCP33121/MCP33111-XX 10-Lead Plastic Micro Small Outline Package (MS) [MSOP] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging 4X Ĭ1 c C SEATING PLANE L Ĭ (L1) 4X Ĭ1 DETAIL A Units Dimension Limits Number of Pins N e Pitch Overall Height A Molded Package Thickness A2 Standoff A1 Overall Width E Molded Package Width E1 Overall Length D Foot Length L Footprint L1 Mold Draft Angle Ĭ Foot Angle Ĭ1 c Lead Thickness b Lead Width MIN 0.75 0.00 0.40 0° 5° 0.08 0.15 MILLIMETERS NOM 10 0.50 BSC 0.85 4.90 BSC 3.00 BSC 3.00 BSC 0.60 0.95 REF - MAX 1.10 0.95 0.15 0.80 8° 15° 0.23 0.33 Notes: 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.15mm per side. 3. Dimensioning and tolerancing per ASME Y14.5M. BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only. Microchip Technology Drawing C04-021D Sheet 2 of 2  2018 Microchip Technology Inc. DS20006122A-page 45 MCP33131/MCP33121/MCP33111-XX 10-Lead Plastic Micro Small Outline Package (MS) [MSOP] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging G SILK SCREEN Z C G1 Y1 X1 E RECOMMENDED LAND PATTERN Units Dimension Limits E Contact Pitch Contact Pad Spacing C Overall Width Z Contact Pad Width (X10) X1 Contact Pad Length (X10) Y1 Distance Between Pads (X5) G1 Distance Between Pads (X8) G MIN MILLIMETERS NOM 0.50 BSC 4.40 MAX 5.80 0.30 1.40 3.00 0.20 Notes: 1. Dimensioning and tolerancing per ASME Y14.5M BSC: Basic Dimension. Theoretically exact value shown without tolerances. Microchip Technology Drawing No. C04-2021B DS20006122A-page 46  2018 Microchip Technology Inc. MCP33131/MCP33121/MCP33111-XX Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2018 Microchip Technology Inc. DS20006122A-page 47 MCP33131/MCP33121/MCP33111-XX Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS20006122A-page 48  2018 Microchip Technology Inc. MCP33131/MCP33121/MCP33111-XX APPENDIX A: REVISION HISTORY Revision A (November 2018) • Original release of this document.  2018 Microchip Technology Inc. DS20006122A-page 49 MCP33131/MCP33121/MCP33111-XX NOTES:  2018 Microchip Technology Inc. DS20006122A-page 50 MCP33131/MCP33121/MCP33111-XX PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. ─XX PART NO. X Device Input Type Device: Input Type X Sample Rate Tape and Reel ─X /XX Temperature Package Range MCP33131-10: 1 Msps 16-Bit Single-Ended Input SAR ADC MCP33121-10: MCP33111-10: 1 Msps 14-Bit Single-Ended Input SAR ADC 1 Msps 12-Bit Single-Ended Input SAR ADC MCP33131-05: 500 kSPS 16-Bit Single-Ended Input SAR ADC MCP33121-05: 500 kSPS 14-Bit Single-Ended Input SAR ADC MCP33111-05: 500 kSPS 12-Bit Single-Ended Input SAR ADC Blank Examples: a) MCP33131-10-I/MS: b) MCP33131-10T-I/MS: c) MCP33131-10-I/MN: d) MCP33131-10T-I/MN: e) MCP33121-10-I/MS: 1 Msps, 10LD MSOP, 14-bit device f) MCP33121-10T-I/MS: 1 Msps, 10LD MSOP, Tape and Reel, 14-bit device g) MCP33121-10-I/MN: 1 Msps, 10LD TDFN, 14-bit device = Single-Ended Input 1 Msps, 10LD MSOP, 16-bit device 1 Msps, 10LD MSOP, Tape and Reel, 16-bit device 1 Msps, 10LD TDFN, 16-bit device 1 Msps, 10LD TDFN, Tape and Reel, 16-bit device Sample Rate: 10 05 = 1 Msps = 500 kSPS h) MCP33121-10T-I/MN: 1 Msps, 10LD TDFN, Tape and Reel, 14-bit device Tape and Reel Option: Blank T = Standard packaging (tube or tray) = Tape and Reel i) MCP33111-10-I/MS: 1 Msps, 10LD MSOP, 12-bit device Temperature Range: E I = -40C to +125C (Extended) = -40C to +85C (Industrial) j) MCP33111-10T-I/MS: 1 Msps, 10LD MSOP, Tape and Reel, 12-bit device k) MCP33111-10-I/MN: Package: MS MN = = 1 Msps, 10LD TDFN, 12-bit device l) MCP33111-10T-I/MN: m) MCP33131-05-I/MS: 1 Msps, 10LD TDFN, Tape and Reel, 12-bit device 500 kSPS, 10LD MSOP, 16-bit device n) MCP33131-05T-I/MS: o) MCP33131-05-I/MN: p) MCP33131-05T-I/MN: q) MCP33121-05-I/MS: r) MCP33121-05T-I/MS: 500 kSPS, 10LD MSOP, Tape and Reel, 14-bit device s) MCP33121-05-I/MN: 500 kSPS, 10LD TDFN, 14-bit device t) MCP33121-05T-I/MN: 500 kSPS, 10LD TDFN, Tape and Reel, 14-bit device u) MCP33111-05-I/MS: 500 kSPS, 10LD MSOP, 12-bit device v) MCP33111-05T-I/MS: 500 kSPS, 10LD MSOP, Tape and Reel, 12-bit device w) MCP33111-05-I/MN: 500 kSPS, 10LD TDFN, 12-bit device x) MCP33111-05T-I/MN: 500 kSPS, 10LD TDFN, Tape and Reel, 12-bit device Note 1: Plastic Micro Small Outline Package (MSOP), 10-Lead Thin Plastic Dual Flat No Lead Package (TDFN), 10-Lead Tape and Reel identifier appears only in the catalog part number description. This identifier is used for ordering purposes and is not printed on the device package. Check with your Microchip Sales Office for package availability with the Tape and Reel option. DS20006122A-page 51 500 kSPS, 10LD MSOP, Tape and Reel, 16-bit device 500 kSPS, 10LD TDFN, 16-bit device 500 kSPS, 10LD TDFN, Tape and Reel, 16-bit device 500 kSPS, 10LD MSOP, 14-bit device  2018 Microchip Technology Inc. MCP33131/MCP33121/MCP33111-XX NOTES:  2018 Microchip Technology Inc. DS20006122A-page 52 Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. • Microchip is willing to work with the customer who is concerned about the integrity of their code. • Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer’s risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights unless otherwise stated. Microchip received ISO/TS-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company’s quality system processes and procedures are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified. QUALITY MANAGEMENT SYSTEM CERTIFIED BY DNV Trademarks The Microchip name and logo, the Microchip logo, AnyRate, AVR, AVR logo, AVR Freaks, BeaconThings, BitCloud, chipKIT, chipKIT logo, CryptoMemory, CryptoRF, dsPIC, FlashFlex, flexPWR, Heldo, JukeBlox, KEELOQ, KEELOQ logo, Kleer, LANCheck, LINK MD, maXStylus, maXTouch, MediaLB, megaAVR, MOST, MOST logo, MPLAB, OptoLyzer, PIC, picoPower, PICSTART, PIC32 logo, Prochip Designer, QTouch, RightTouch, SAM-BA, SpyNIC, SST, SST Logo, SuperFlash, tinyAVR, UNI/O, and XMEGA are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. ClockWorks, The Embedded Control Solutions Company, EtherSynch, Hyper Speed Control, HyperLight Load, IntelliMOS, mTouch, Precision Edge, and Quiet-Wire are registered trademarks of Microchip Technology Incorporated in the U.S.A. Adjacent Key Suppression, AKS, Analog-for-the-Digital Age, Any Capacitor, AnyIn, AnyOut, BodyCom, CodeGuard, CryptoAuthentication, CryptoCompanion, CryptoController, dsPICDEM, dsPICDEM.net, Dynamic Average Matching, DAM, ECAN, EtherGREEN, In-Circuit Serial Programming, ICSP, InterChip Connectivity, JitterBlocker, KleerNet, KleerNet logo, Mindi, MiWi, motorBench, MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach, Omniscient Code Generation, PICDEM, PICDEM.net, PICkit, PICtail, PureSilicon, QMatrix, RightTouch logo, REAL ICE, Ripple Blocker, SAM-ICE, Serial Quad I/O, SMART-I.S., SQI, SuperSwitcher, SuperSwitcher II, Total Endurance, TSHARC, USBCheck, VariSense, ViewSpan, WiperLock, Wireless DNA, and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. Silicon Storage Technology is a registered trademark of Microchip Technology Inc. in other countries. GestIC is a registered trademark of Microchip Technology Germany II GmbH & Co. KG, a subsidiary of Microchip Technology Inc., in other countries. All other trademarks mentioned herein are property of their respective companies. © 2018, Microchip Technology Incorporated, All Rights Reserved. ISBN: 978-1-5224-3911-0 == ISO/TS 16949 ==  2018 Microchip Technology Inc. DS20006122A-page 53 Worldwide Sales and Service AMERICAS ASIA/PACIFIC ASIA/PACIFIC EUROPE Corporate Office 2355 West Chandler Blvd. Chandler, AZ 85224-6199 Tel: 480-792-7200 Fax: 480-792-7277 Technical Support: http://www.microchip.com/ support Web Address: www.microchip.com Australia - Sydney Tel: 61-2-9868-6733 India - Bangalore Tel: 91-80-3090-4444 China - Beijing Tel: 86-10-8569-7000 India - New Delhi Tel: 91-11-4160-8631 Austria - Wels Tel: 43-7242-2244-39 Fax: 43-7242-2244-393 China - Chengdu Tel: 86-28-8665-5511 India - Pune Tel: 91-20-4121-0141 Denmark - Copenhagen Tel: 45-4450-2828 Fax: 45-4485-2829 China - Chongqing Tel: 86-23-8980-9588 Japan - Osaka Tel: 81-6-6152-7160 Finland - Espoo Tel: 358-9-4520-820 China - Dongguan Tel: 86-769-8702-9880 Japan - Tokyo Tel: 81-3-6880- 3770 China - Guangzhou Tel: 86-20-8755-8029 Korea - Daegu Tel: 82-53-744-4301 France - Paris Tel: 33-1-69-53-63-20 Fax: 33-1-69-30-90-79 China - Hangzhou Tel: 86-571-8792-8115 Korea - Seoul Tel: 82-2-554-7200 China - Hong Kong SAR Tel: 852-2943-5100 Malaysia - Kuala Lumpur Tel: 60-3-7651-7906 China - Nanjing Tel: 86-25-8473-2460 Malaysia - Penang Tel: 60-4-227-8870 China - Qingdao Tel: 86-532-8502-7355 Philippines - Manila Tel: 63-2-634-9065 China - Shanghai Tel: 86-21-3326-8000 Singapore Tel: 65-6334-8870 China - Shenyang Tel: 86-24-2334-2829 Taiwan - Hsin Chu Tel: 886-3-577-8366 China - Shenzhen Tel: 86-755-8864-2200 Taiwan - Kaohsiung Tel: 886-7-213-7830 China - Suzhou Tel: 86-186-6233-1526 Taiwan - Taipei Tel: 886-2-2508-8600 China - Wuhan Tel: 86-27-5980-5300 Thailand - Bangkok Tel: 66-2-694-1351 China - Xian Tel: 86-29-8833-7252 Vietnam - Ho Chi Minh Tel: 84-28-5448-2100 Atlanta Duluth, GA Tel: 678-957-9614 Fax: 678-957-1455 Austin, TX Tel: 512-257-3370 Boston Westborough, MA Tel: 774-760-0087 Fax: 774-760-0088 Chicago Itasca, IL Tel: 630-285-0071 Fax: 630-285-0075 Dallas Addison, TX Tel: 972-818-7423 Fax: 972-818-2924 Detroit Novi, MI Tel: 248-848-4000 Houston, TX Tel: 281-894-5983 Indianapolis Noblesville, IN Tel: 317-773-8323 Fax: 317-773-5453 Tel: 317-536-2380 Los Angeles Mission Viejo, CA Tel: 949-462-9523 Fax: 949-462-9608 Tel: 951-273-7800 Raleigh, NC Tel: 919-844-7510 New York, NY Tel: 631-435-6000 San Jose, CA Tel: 408-735-9110 Tel: 408-436-4270 Canada - Toronto Tel: 905-695-1980 Fax: 905-695-2078 DS20006122A-page 54 China - Xiamen Tel: 86-592-2388138 China - Zhuhai Tel: 86-756-3210040 Germany - Garching Tel: 49-8931-9700 Germany - Haan Tel: 49-2129-3766400 Germany - Heilbronn Tel: 49-7131-67-3636 Germany - Karlsruhe Tel: 49-721-625370 Germany - Munich Tel: 49-89-627-144-0 Fax: 49-89-627-144-44 Germany - Rosenheim Tel: 49-8031-354-560 Israel - Ra’anana Tel: 972-9-744-7705 Italy - Milan Tel: 39-0331-742611 Fax: 39-0331-466781 Italy - Padova Tel: 39-049-7625286 Netherlands - Drunen Tel: 31-416-690399 Fax: 31-416-690340 Norway - Trondheim Tel: 47-7289-7561 Poland - Warsaw Tel: 48-22-3325737 Romania - Bucharest Tel: 40-21-407-87-50 Spain - Madrid Tel: 34-91-708-08-90 Fax: 34-91-708-08-91 Sweden - Gothenberg Tel: 46-31-704-60-40 Sweden - Stockholm Tel: 46-8-5090-4654 UK - Wokingham Tel: 44-118-921-5800 Fax: 44-118-921-5820  2018 Microchip Technology Inc. 10/25/17