MCP33131D-05T-E/MN

MCP33131D/21D/11D-XX 1 Msps/500 kSPS 16/14/12-Bit Differential Input SAR ADC Features Typical Applications • Sample Rate (Throughput): - MCP33131D/21D/11D-10: 1 Msps - MCP33131D/21D/11D-05: 500 kSPS • 16/14/12-Bit Resolution with No Missing Codes • No Latency Output • Wide Operating Voltage Range: - Analog Supply Voltage (AVDD): 1.8V - Digital Input/Output Interface Voltage (DVIO): 1.7V - 5.5V - External Reference (VREF): 2.5V - 5.1V • Differential Input Operation - Input Full-Scale Range: -VREF to +VREF • Ultra Low Current Consumption (typical): - During Input Acquisition (Standby): ~ 0.8 µA - During Conversion: • • • • • • • High-Precision Data Acquisition Medical Instruments Test Equipment Electric Vehicle Battery Management Systems Motor Control Applications Switch-Mode Power Supply Applications Battery-Powered Equipment System Design Supports The MCP331x1D-XX Evaluation Kit demonstrates the performance of the MCP331x1D-XX SAR ADC family devices. The evaluation kit includes: (a) MCP331x1D Evaluation Board, (b) PIC32MZ EF Curiosity Board for data collection, and (c) SAR ADC Utility PC GUI. Contact Microchip Technology Inc. for the evaluation tools and the PIC32 MCU firmware example codes. MCP33131D/21D/11D-10: ~1.6 mA MCP33131D/21D/11D-05: ~1.4 mA Package Types • SPI-Compatible Serial Communication: - SCLK Clock Rate: up to 100 MHz • ADC Self-Calibration for Offset, Gain, and Linearity Errors: - During Power-Up (automatic) - On-Demand via user’s command during normal operation • AEC-Q100 Qualified: - Temperature Grade 1: -40°C to +125°C • Package Options: MSOP-10 and TDFN-10 10 DVIO VREF 1 MSOP-10 AVDD 2 Top View 9 SDI AIN+ 3 AIN- 4 GND 5 8 SCLK 7 SDO 6 CNVST VREF 1 10 DVIO AVDD 2 TDFN-10 AIN+ 3 AIN- 4 9 SDI Top View 8 SCLK 7 SDO 6 CNVST GND 5 MCP331x1D-XX Device Offering (Note 1): Sample Rate Input Type Input Range (Differential) Performance (Typical) Part Number Resolution MCP33131D-10 16-bit 1 Msps Differential ±5.1V 91.3 103.5 -99.3 ±2 ±0.8 MCP33121D-10 14-bit 1 Msps Differential ±5.1V 85.1 103.5 -99.2 ±0.5 ±0.25 ±0.06 SNR (dBFS) SFDR (dB) THD (dB) INL (LSB) DNL (LSB) MCP33111D-10 12-bit 1 Msps Differential ±5.1V 73.9 99.3 -96.7 ±0.12 MCP33131D-05 16-bit 500 kSPS Differential ±5.1V 91.3 103.5 -99.3 ±2 ±0.8 MCP33121D-05 14-bit 500 kSPS Differential ±5.1V 85.1 103.5 -99.2 ±0.5 ±0.25 MCP33111D-05 12-bit 500 kSPS Differential ±5.1V 73.9 99.3 -96.7 ±0.12 ±0.06 Note 1: SNR, SFDR, and THD are measured with fIN = 10 kHz, VIN = -1 dBFS, VREF = 5.1V.  2018 Microchip Technology Inc. DS20005947B-page 1 MCP33131D/MCP33121D/MCP33111D-XX Application Diagram 2.5V to 5.1V 1.8V VREF AVDD DVIO 22Ω 0V to VREF AIN+ 1.7 nF SDI MCP331x1D-XX 22Ω 0V to VREF 1.8V to 5.5V AIN1.7 nF Description The MCP33131D/MCP33121D/MCP33111D-10 and MCP33131D/MCP33121D/MCP33111D-05 are fully-differential 16, 14, and 12-bit, single-channel 1 Msps and 500 kSPS ADC family devices, respectively, featuring low power consumption and high performance, using a successive approximation register (SAR) architecture. The device operates with a 2.5V to 5.1V external reference (VREF), which supports a wide range of input full-scale range from -VREF to +VREF. The reference voltage setting is independent of the analog supply voltage (AVDD) and is higher than AVDD. The conversion output is available through an easy-to-use simple SPI- compatible 3-wire interface. The device requires a 1.8V analog supply voltage (AVDD) and a 1.7V to 5.5V digital I/O interface supply voltage (DVIO). The wide digital I/O interface supply (DVIO) range (1.7V – 5.5V) allows the device to interface with most host devices (Master) available in the current industry such as the PIC32 microcontrollers, without using external voltage level shifters. GND CNVST Host Device SCLK (PIC32MZ) SDO During Standby, most of the internal analog circuitry is shutdown in order to reduce current consumption. Typically, the device consumes less than 1 µA during Standby. A new conversion is started on the rising edge of CNVST. When the conversion is complete and the host lowers CNVST, the output data is presented on SDO, and the device enters Standby to begin acquiring the next input sample. The user can clock out the ADC output data using the SPI-compatible serial clock during Standby. The ADC system clock is generated by the internal on-chip clock, therefore the conversion is performed independent of the SPI serial clock (SCLK). This device can be used for various high-speed and high-accuracy analog-to-digital data conversion applications, where design simplicity, low power, and no output latency are needed. The device is AEC-Q100 qualified for automotive applications and operates over the extended temperature range of -40°C to +125°C. The available package options are Pb-free small 3 mm x 3 mm TDFN-10 and MSOP-10. When the device is first powered-up, it performs a self-calibration to minimize offset, gain and linearity errors. The device performance stays stable across the specified temperature range. However, when extreme changes in the operating environment, such as in the reference voltage, are made with respect to the initial conditions (e.g. the reference voltage was not fully settled during the initial power-up sequence), the user may send a recalibrate command anytime to initiate another self-calibration to restore optimum performance. When the initial power-up sequence is completed, the device enters a low-current input acquisition mode, where sampling capacitors are connected to the input pins. This mode is called Standby. DS20005947B-page 2  2018 Microchip Technology Inc. MCP33131D/MCP33121D/MCP33111D-XX 1.0 KEY ELECTRICAL CHARACTERISTICS 1.1 Absolute Maximum Ratings† †Notice: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. External Analog Supply Voltage (AVDD)............. -0.3V to 2.0V External Digital Supply Voltage (DVIO)............... -0.3V to 5.8V External Reference Voltage (VREF).................... -0.3V to 5.8V Analog Inputs w.r.t GND ............... .......... -0.3V to VREF+0.3V Current at Input Pins ....................................................±2 mA Current at Output and Supply Pins ..........................±250 mA Storage Temperature ....................................-65°C to +150°C Maximum Junction Temperature (TJ). .........................+150°C ESD protection on all pins .... ≤2kV HBM, ≤200V MM, ≤2kV CDM 1.2 Electrical Specifications TABLE 1-1: KEY ELECTRICAL CHARACTERISTICS Electrical Specifications: Unless otherwise specified, all parameters apply for TA = -40°C to +125°C, AVDD = 1.8V, DVIO = 3.3V, VREF = 5V, GND = 0V, Differential Analog Input (VIN) = -1 dBFS sine wave, fIN = 10 kHz, CLOAD_SDO = 20 pF • MCP331x1D-10: Sample Rate (fS) = 1 Msps, SPI Clock Input (SCLK) = 60 MHz. • MCP331x1D-05: Sample Rate (fS) = 500 kSPS, SPI Clock Input (SCLK) = 30 MHz. Parameters Sym. Min. Typ. Max. Units Conditions Analog Supply Voltage Range AVDD 1.7 1.8 1.9 V (Note 3) Digital Input/Output Interface Voltage Range DVIO 1.7 — 5.5 V (Note 3) IDDAN — — — 1.6 1.4 0.8 2.4 2.0 — mA mA µA fs = 1 Msps (MCP331x1D-10) fs = 500 kSPS (MCP331x1D-05) During input acquisition (tACQ) — — — 290 200 30 — — — A A nA fs = 1 Msps (MCP331x1D-10) fs = 500 kSPS (MCP331x1D-05) During input acquisition (tACQ) 5.1 5.1 V -40°C ≤ TA ≤ 85°C 85°C < TA ≤ 125°C 450 220 240 600 360 — µA µA nA fs = 1 Msps (MCP331x1D-10) fs = 500 kSPS (MCP331x1D-05) During input acquisition (tACQ) — — — — 6.2 3.1 0.6 2.6 — — — — mW mW mW W Averaged power for tACQ + tCNV — — — 4.2 0.8 2.6 — — — mW mW W Power Supply Requirements Analog Supply Current at AVDD pin: During Conversion During Standby Digital Supply Current At DVDD pin: During Output Data Reading During Standby IDDAN_STBY IIO_DATA IIO_STBY External Reference Voltage Input Reference Voltage (Note 2), (Note 3) Reference Load Current at VREF pin: During Conversion During Standby VREF 2.5 2.7 IREF — — IREF_STBY Total Power Consumption (Including AVDD, DVIO, VREF pins) MCP331x1D-10 at 1 Msps at 500 kSPS at 100 kSPS During Standby PDISS_TOTAL PDISS_STBY During input acquisition (tACQ) MCP331x1D-05 at 500 kSPS at 100 kSPS During Standby Note PDISS_TOTAL PDISS_STBY Averaged power for tACQ + tCNV During input acquisition (tACQ) 1: This parameter is ensured by design and not 100% tested. 2: This parameter is ensured by characterization and not 100% tested. 3: Decoupling capacitor is recommended on the following pins: (a) AVDD pin: 1 F ceramic capacitor, (b) DVIO pin: 0.1 F ceramic capacitor, (c) VREF pin: 10 F tantalum capacitor. 4: Differential Input Full-Scale Range (FSR) = 2 x VREF 5: PSRR (dB) = -20 log (DVOUT/AVDD), where DVOUT = change in conversion result. 6: ENOB = (SINAD - 1.76)/6.02  2018 Microchip Technology Inc. DS20005947B-page 3 MCP33131D/MCP33121D/MCP33111D-XX TABLE 1-1: KEY ELECTRICAL CHARACTERISTICS (CONTINUED) Electrical Specifications: Unless otherwise specified, all parameters apply for TA = -40°C to +125°C, AVDD = 1.8V, DVIO = 3.3V, VREF = 5V, GND = 0V, Differential Analog Input (VIN) = -1 dBFS sine wave, fIN = 10 kHz, CLOAD_SDO = 20 pF • MCP331x1D-10: Sample Rate (fS) = 1 Msps, SPI Clock Input (SCLK) = 60 MHz. • MCP331x1D-05: Sample Rate (fS) = 500 kSPS, SPI Clock Input (SCLK) = 30 MHz. Parameters Sym. Min. Typ. Max. Units Conditions Input Voltage Range (Note 2) VIN+ -0.1 — VREF+0.1 V VIN- -0.1 — VREF+0.1 V Input Full-Scale Voltage Range FSR -VREF — +VREF VPP Differential Input (Note 2), (Note 4) Input Common-Mode Voltage Range VCM 0 VREF/2 VREF CS — 31 — pF (Note 1) BW-3dB — 25 — MHz (Note 1) — 2.5 — ns Time delay between CNVST rising edge and when input is sampled ILEAK_AN_INPUT — ±2 ±200 nA During input acquisition (tACQ) fs — — 1 Msps MCP331x1D-10 — — 500 kSPS MCP331x1D-05 16 — — Bits 14 — — Bits MCP33121D-10 and MCP33121D-05 12 — — Bits MCP33111D-10 and MCP33111D-05 Analog Inputs Input Sampling Capacitance -3dB Input Bandwidth Aperture Delay (Note 1) Leakage Current at Analog Input Pin Differential Input: VIN = (VIN+ - VIN-) (Note 2) System Performance Sample Rate (Throughput rate) Resolution (No Missing Codes) Integral Nonlinearity INL -6 ±2 +6 LSB MCP33131D-10 and MCP33131D-05 -1.5 ±0.5 +1.5 LSB MCP33121D-10 and MCP33121D-05 LSB MCP33111D-10 and MCP33111D-05 ±0.12 Differential Nonlinearity DNL -0.98 ±0.8 +1.8 LSB MCP33131D-10 and MCP33131D-05 -0.8 ±0.25 +0.8 LSB MCP33121D-10 and MCP33121D-05 -0.3 ±0.06 +0.3 LSB MCP33111D-10 and MCP33111D-05 ±0.1 ±2.3 mV MCP33131D-10 and MCP33131D-05 — ±0.125 ±3 mV MCP33121D-10 and MCP33121D-05 — ±0.8 ±3.66 mV MCP33111D-10 and MCP33111D-05 — ±0.8 — V/oC Offset Error Offset Error Drift with Temperature Gain Error GER Gain Error Drift with temperature — ±2 — LSB MCP33131D-10 and MCP33131D-05 — ±0.5 — LSB MCP33121D-10 and MCP33121D-05 MCP33111D-10 and MCP33111D-05 — ±0.1 — LSB — ±0.35 — V/oC Input common-mode rejection ratio CMRR — 84 — dB Power Supply Rejection Ratio PSRR — 70 — dB Note MCP33131D-10 and MCP33131D-05 (Note 5) 1: This parameter is ensured by design and not 100% tested. 2: This parameter is ensured by characterization and not 100% tested. 3: Decoupling capacitor is recommended on the following pins: (a) AVDD pin: 1 F ceramic capacitor, (b) DVIO pin: 0.1 F ceramic capacitor, (c) VREF pin: 10 F tantalum capacitor. 4: Differential Input Full-Scale Range (FSR) = 2 x VREF 5: PSRR (dB) = -20 log (DVOUT/AVDD), where DVOUT = change in conversion result. 6: ENOB = (SINAD - 1.76)/6.02 DS20005947B-page 4  2018 Microchip Technology Inc. MCP33131D/MCP33121D/MCP33111D-XX TABLE 1-1: KEY ELECTRICAL CHARACTERISTICS (CONTINUED) Electrical Specifications: Unless otherwise specified, all parameters apply for TA = -40°C to +125°C, AVDD = 1.8V, DVIO = 3.3V, VREF = 5V, GND = 0V, Differential Analog Input (VIN) = -1 dBFS sine wave, fIN = 10 kHz, CLOAD_SDO = 20 pF • MCP331x1D-10: Sample Rate (fS) = 1 Msps, SPI Clock Input (SCLK) = 60 MHz. • MCP331x1D-05: Sample Rate (fS) = 500 kSPS, SPI Clock Input (SCLK) = 30 MHz. Parameters Sym. Min. Typ. Max. Units Conditions — 91.6 — — 86.6 — VREF = 2.5V, fIN = 1 kHz 88.7 91.3 — VREF = 5V, fIN = 10 kHz — 86.6 — VREF = 2.5V, fIN = 10 kHz Dynamic Performance Signal-to-Noise Ratio SNR MCP33131D-10 and MCP33131D-05: 16-bit ADC dBFS VREF = 5V, fIN = 1 kHz MCP33121D-10 and MCP33121D-05: 14-bit ADC — 85.2 — — 83.5 — dBFS VREF = 5V, fIN = 1 kHz VREF = 2.5V, fIN = 1 kHz 81.7 85.1 — VREF = 5V, fIN = 10 kHz — 83.5 — VREF = 2.5V, fIN = 10 kHz MCP33111D-10 and MCP33111D-05: 12-bit ADC Signal-to-Noise and Distortion Ratio (Note 6) — 73.9 — — 73.8 — VREF = 2.5V, fIN = 1 kHz 71.1 73.9 — VREF = 5V, fIN = 10 kHz — 73.8 — VREF = 2.5V, fIN = 10 kHz SINAD dBFS VREF = 5V, fIN = 1 kHz MCP33131D-10 and MCP33131D-05: 16-bit ADC — 91.5 — — 86.6 — dBFS VREF = 5V, fIN = 1 kHz — 91 — VREF = 5V, fIN = 10 kHz — 86.2 — VREF = 2.5V, fIN = 10 kHz — 85.2 — — 83.5 — — 85 — VREF = 5V, fIN = 10 kHz — 83.3 — VREF = 2.5V, fIN = 10 kHz — 73.9 — — 73.8 — — 73.9 — VREF = 5V, fIN = 10 kHz — 73.8 — VREF = 2.5V, fIN = 10 kHz VREF = 2.5V, fIN = 1 kHz MCP33121D-10 and MCP33121D-05: 14-bit ADC dBFS VREF = 5V, fIN = 1 kHz VREF = 2.5V, fIN = 1 kHz MCP33111D-10 and MCP33111D-05: 12-bit ADC Note dBFS VREF = 5V, fIN = 1 kHz VREF = 2.5V, fIN = 1 kHz 1: This parameter is ensured by design and not 100% tested. 2: This parameter is ensured by characterization and not 100% tested. 3: Decoupling capacitor is recommended on the following pins: (a) AVDD pin: 1 F ceramic capacitor, (b) DVIO pin: 0.1 F ceramic capacitor, (c) VREF pin: 10 F tantalum capacitor. 4: Differential Input Full-Scale Range (FSR) = 2 x VREF 5: PSRR (dB) = -20 log (DVOUT/AVDD), where DVOUT = change in conversion result. 6: ENOB = (SINAD - 1.76)/6.02  2018 Microchip Technology Inc. DS20005947B-page 5 MCP33131D/MCP33121D/MCP33111D-XX TABLE 1-1: KEY ELECTRICAL CHARACTERISTICS (CONTINUED) Electrical Specifications: Unless otherwise specified, all parameters apply for TA = -40°C to +125°C, AVDD = 1.8V, DVIO = 3.3V, VREF = 5V, GND = 0V, Differential Analog Input (VIN) = -1 dBFS sine wave, fIN = 10 kHz, CLOAD_SDO = 20 pF • MCP331x1D-10: Sample Rate (fS) = 1 Msps, SPI Clock Input (SCLK) = 60 MHz. • MCP331x1D-05: Sample Rate (fS) = 500 kSPS, SPI Clock Input (SCLK) = 30 MHz. Parameters Sym. Spurious Free Dynamic Range SFDR Min. Typ. Max. Units Conditions MCP33131D-10 and MCP33131D-05: 16-bit ADC — 103.7 — — 98 — dBc VREF = 5V, fIN = 1 kHz VREF = 2.5V, fIN = 1 kHz — 103.5 — VREF = 5V, fIN = 10 kHz — 97.5 — VREF = 2.5V, fIN = 10 kHz MCP33121D-10 and MCP33121D-05: 14-bit ADC — 103.6 — — 98 — dBc VREF = 5V, fIN = 1 kHz VREF = 2.5V, fIN = 1 kHz — 103.5 — VREF = 5V, fIN = 10 kHz — 97.4 — VREF = 2.5V, fIN = 10 kHz MCP33111D-10 and MCP33111D-05: 12-bit ADC Total Harmonic Distortion (first five harmonics) — 99.3 — — 97.7 — — 99.3 — VREF = 5V, fIN = 10 kHz — 97.2 — VREF = 2.5V, fIN = 10 kHz — -100.4 — — -95.4 — THD dBc VREF = 5V, fIN = 1 kHz VREF = 2.5V, fIN = 1 kHz MCP33131D-10 and MCP33131D-05: 16-bit ADC dBc VREF = 5V, fIN = 1 kHz VREF = 2.5V, fIN = 1 kHz — -99.3 — VREF = 5V, fIN = 10 kHz — -95.4 — VREF = 2.5V, fIN = 10 kHz — -100.1 — — -95.3 — MCP33121D-10 and MCP33121D-05: 14-bit ADC dBc VREF = 5V, fIN = 1 kHz VREF = 2.5V, fIN = 1 kHz — -99.2 — VREF = 5V, fIN = 10 kHz — -95.3 — VREF = 2.5V, fIN = 10 kHz — -97.5 — — -94.4 — — -96.7 — VREF = 5V, fIN = 10 kHz — -94.4 — VREF = 2.5V, fIN = 10 kHz MCP33111D-10 and MCP33111D-05: 12-bit ADC Note dBc VREF = 5V, fIN = 1 kHz VREF = 2.5V, fIN = 1 kHz 1: This parameter is ensured by design and not 100% tested. 2: This parameter is ensured by characterization and not 100% tested. 3: Decoupling capacitor is recommended on the following pins: (a) AVDD pin: 1 F ceramic capacitor, (b) DVIO pin: 0.1 F ceramic capacitor, (c) VREF pin: 10 F tantalum capacitor. 4: Differential Input Full-Scale Range (FSR) = 2 x VREF 5: PSRR (dB) = -20 log (DVOUT/AVDD), where DVOUT = change in conversion result. 6: ENOB = (SINAD - 1.76)/6.02 DS20005947B-page 6  2018 Microchip Technology Inc. MCP33131D/MCP33121D/MCP33111D-XX TABLE 1-1: KEY ELECTRICAL CHARACTERISTICS (CONTINUED) Electrical Specifications: Unless otherwise specified, all parameters apply for TA = -40°C to +125°C, AVDD = 1.8V, DVIO = 3.3V, VREF = 5V, GND = 0V, Differential Analog Input (VIN) = -1 dBFS sine wave, fIN = 10 kHz, CLOAD_SDO = 20 pF • MCP331x1D-10: Sample Rate (fS) = 1 Msps, SPI Clock Input (SCLK) = 60 MHz. • MCP331x1D-05: Sample Rate (fS) = 500 kSPS, SPI Clock Input (SCLK) = 30 MHz. Parameters Sym. Min. Typ. Max. tCAL ReCalNSCLK Units Conditions — 500 650 ms — 1024 — clocks 0.7 * DVIO — DVIO + 0.3 V DVIO ≥ 2.3V 0.9 * DVIO — DVIO + 0.3 V DVIO < 2.3V -0.3 — 0.3 * DVIO V DVIO ≥ 2.3V -0.3 — 0.2 * DVIO V DVIO < 2.3V VHYST — 0.2 * DVIO — V All digital inputs Low-level output voltage VOL — — 0.2 * DVIO V IOL = 500 µA (sink) High-level output voltage System Self-Calibration Self-Calibration Time Number of SCLK Clocks for Recalibrate Command (Note 2) Includes clocks for data bits Serial Interface Timing Information: See Table 1-2 Digital Inputs/Outputs High-level Input voltage Low-level input voltage Hysteresis of Schmitt Trigger Inputs VIH VIL VOH 0.8 * DVIO — — V IOL = - 500 µA (source) Input leakage current ILI — — ±1 µA CNVST/SDI/SCLK = GND or DVIO Output leakage current ILO — — ±1 µA Output is high-Z, SDO = GND or DVIO CINT — 7 — pF TA = 25°C (Note 1) Internal capacitance (all digital inputs and outputs) Note 1: This parameter is ensured by design and not 100% tested. 2: This parameter is ensured by characterization and not 100% tested. 3: Decoupling capacitor is recommended on the following pins: (a) AVDD pin: 1 F ceramic capacitor, (b) DVIO pin: 0.1 F ceramic capacitor, (c) VREF pin: 10 F tantalum capacitor. 4: Differential Input Full-Scale Range (FSR) = 2 x VREF 5: PSRR (dB) = -20 log (DVOUT/AVDD), where DVOUT = change in conversion result. 6: ENOB = (SINAD - 1.76)/6.02  2018 Microchip Technology Inc. DS20005947B-page 7 MCP33131D/MCP33121D/MCP33111D-XX TABLE 1-2: SERIAL INTERFACE TIMING SPECIFICATIONS Electrical Specifications: Unless otherwise specified, all parameters apply for TA = -40°C to +125°C, AVDD = 1.8V, DVIO = 3.3V, VREF = 5V, GND = 0V, Differential Analog Input (VIN) = -1 dBFS sine wave, fIN = 10 kHz, CLOAD_SDO = 20 pF. +25°C is applied for typical value. All timings are measured at 50%. See Figure 1-1 for timing diagram. • MCP331x1D-10: Sample Rate (fS) = 1 Msps, SPI Clock Input (SCLK) = 60 MHz. • MCP331x1D-05: Sample Rate (fS) = 500 kSPS, SPI Clock Input (SCLK) = 30 MHz. Parameters Symbol Min. Typ. Max. Units Conditions Serial Clock frequency fSCLK — — 100 MHz SCLK Period tSCLK 10 — — ns DVIO ≥ 3.3V, fSCLK = 100 MHz (Max) 12 — — ns DVIO ≥ 2.3V, fSCLK = 83.3 MHz (Max) 16 — — ns DVIO ≥ 1.7V, fSCLK = 62.5 MHz (Max) 3 — — ns DVIO ≥ 2.3V 4.5 — — ns DVIO ≥ 1.7V 3 — — ns DVIO ≥ 2.3V 4.5 — — ns DVIO ≥ 1.7V — — 9.5 ns DVIO ≥ 3.3V — — 12 ns DVIO ≥ 2.3V — — 16 ns DVIO ≥ 1.7V 10 — — ns (Note 2) SDI High to CNVST Rising Edge SCLK Low Time tSCLK_L SCLK High Time tSCLK_H Output Valid from SCLK Low tDO Quiet time tQUIET See tSCLK specification 3-Wire Operation: SDI Valid Setup time tSU_SDIH_CNV 5 — — ns tCNVH 10 — — ns CNVST Pulse Width High Time Output Enable Time tEN Output Disable Time tDIS — — 10 ns DVIO ≥ 2.3V — — 15 ns DVIO ≥ 1.7V — — 15 ns (Note 2) MCP331x1D-10 fs — — 1 Msps Input Acquisition Time (Note 2) Sample Rate tACQ 290 250 300 — — ns -40°C ≤ TA ≤ 85°C 85°C < TA ≤ 125°C Data Conversion Time tCNV — — 700 710 750 ns -40°C ≤ TA ≤ 85°C 85°C < TA ≤ 125°C Time between Conversions tCYC 1 — — µs tCYC = tACQ + tCNV, fS = 1 Msps Throughput rate MCP331x1D-05 fs — — 500 kSPS Input Acquisition Time (Note 2) Sample Rate tACQ 700 800 — ns Data Conversion Time tCNV — 1200 1300 ns -40°C ≤ TA ≤ 125°C Time between Conversions tCYC 2 — — µs tCYC = tACQ + tCNV, fS = 500 kSPS Note 1: 2: Throughput rate -40°C ≤ TA ≤ 125°C This parameter is ensured by design and not 100% tested. This parameter is ensured by characterization and not 100% tested. TABLE 1-3: TEMPERATURE CHARACTERISTICS Parameters Symbol Min. Typ. Max. Units Operating Temperature Range TA -40 — +125 °C (Note 1) Storage Temperature Range TA -65 — +150 °C (Note 1) Thermal Resistance, MSOP-10 JA — 202 — °C/W Thermal Resistance, TDFN-10 JA — 68 — °C/W Conditions Temperature Ranges Thermal Package Resistance Note 1: The internal junction temperature (Tj) must not exceed the absolute maximum specification of +150oC. DS20005947B-page 8  2018 Microchip Technology Inc. MCP33131D/MCP33121D/MCP33111D-XX tCYC = 1/fS SDI = “High” tCNVH tSU_SDIH_CNV CNVST tSCLK 1 SCLK 2 3 tDO Hi-Z SDO Dn-1 (MSB) tCNV (MAX) Input Acquisition (tACQ) Dn-3 n n-1 tSCLK_L tSCLK_H D1 tDIS D0 tQUIET Hi-Z tEN (Note 2) tEN ADC State Dn-2 (Note 1) (Note 3) Conversion (tCNV) Input Acquisition (tACQ) Note 1: n = 16 for 16-bit, 14 for 14-bit device, and 12 for 12-bit device. 2: tEN when CNVST is lowered after tCNV (MAX). 3: tEN when CNVST is lowered before tCNV (MAX). FIGURE 1-1: details. Interface Timing Diagram. CNVST is used as chip select. See Figure 7-2 for more  2018 Microchip Technology Inc. DS20005947B-page 9 MCP33131D/MCP33121D/MCP33111D-XX NOTES: DS20005947B-page 10  2018 Microchip Technology Inc. MCP33131D/MCP33121D/MCP33111D-XX 2.0 TYPICAL PERFORMANCE CURVES FOR 16-BIT DEVICES (MCP33131D-XX) Note: The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore outside the warranted range. Note: Unless otherwise specified, all parameters apply for TA = +25°C, AVDD = 1.8V, DVIO = 3.3V, VREF = 5V, GND = 0V, Differential Analog Input (VIN) = -1 dBFS, fIN = 10 kHz, CLOAD_SDO = 20 pF. MCP33131D-10: Sample Rate (fS) = 1 Msps, SPI Clock Input (SCLK) = 60 MHz. MCP33131D-05: Sample Rate (fS) = 500 kSPS, SPI Clock Input (SCLK) = 30 MHz. 2 3 V REF = 5V V REF = 2.5V 2 1 INL (LSB) INL (LSB) 1 0 0 -1 -1 -2 -2 0 16,384 32,768 49,152 -3 65,536 0 16,384 32,768 Code FIGURE 2-1: 49,152 INL vs. Output Code. FIGURE 2-4: INL vs. Output Code. 1 1 V REF = 2.5V V REF = 5V 0.5 DNL (LSB) DNL (LSB) 0.5 0 0 -0.5 -0.5 -1 0 16,384 32,768 49,152 -1 65,536 0 16,384 32,768 FIGURE 2-2: DNL vs. Output Code. FIGURE 2-5: 65,536 DNL vs. Output Code. 1 3 2 Max INL (LSB) -1 -20 0 20 40 60 V REF = 5V 0 -0.5 Min INL (LSB) -2 DNL (LSB) V REF = 5V 0 Max DNL (LSB) 0.5 1 -3 -40 49,152 Code Code INL (LSB) 65,536 Code Min DNL (LSB) 80 100 120 140 -1 -40 -20 INL vs. Temperature.  2017 Microchip Technology Inc. 20 40 60 80 100 120 140 Temperature ( C) Temperature ( C) FIGURE 2-3: 0 o o FIGURE 2-6: DNL vs. Temperature. DS20005947B-page 11 MCP33131D/MCP33121D/MCP33111D-XX Note: Unless otherwise specified, all parameters apply for TA = +25°C, AVDD = 1.8V, DVIO = 3.3V, VREF = 5V, GND = 0V, Differential Analog Input (VIN) = -1 dBFS, fIN = 10 kHz, CLOAD_SDO = 20 pF. MCP33131D-10: Sample Rate (fS) = 1 Msps, SPI Clock Input (SCLK) = 60 MHz. MCP33131D-05: Sample Rate (fS) = 500 kSPS, SPI Clock Input (SCLK) = 30 MHz. 4 1 Max INL (LSB) 3 Max DNL (LSB) 0.5 DNL (LSB) INL (LSB) 2 1 0 -1 -2 -0.5 Min DNL (LSB) Min INL (LSB) -3 -4 0 2 2.5 3 3.5 4 4.5 5 -1 5.5 2 2.5 3 Reference Voltage (V) FIGURE 2-7: INL vs. Reference Voltage. VREF = 5V Amplitude (dBFS) -80 -100 -120 -140 5.5 fs = 1 Msps SNR = 86.7 dBFS SINAD = 86.2 dBFS SFDR = 97.4 dBc THD = -95.6 dBc Offset = -2 LSB Resolution = 16-bit -40 -60 -80 -100 -120 -140 0 100 200 300 400 -160 500 0 100 200 Frequency (kHz) MCP33131D-05 -20 fs = 0.5 Msps -80 VREF = 2.5V -20 Amplitude (dBFS) -60 500 MCP33131D-05 0 SNR = 91.5 dBFS SINAD = 91.3 dBFS SFDR = 108.0 dBc THD = -102.5 dBc Offset = 1 LSB Resolution = 16-bit -40 400 FIGURE 2-11: FFT for 10 kHz Input Signal: fS = 1 Msps, VIN = -1 dBFS, VREF = 2.5V. 0 VREF = 5V 300 Frequency (kHz) FIGURE 2-8: FFT for 10 kHz Input Signal: fS = 1 Msps, VIN = -1 dBFS, VREF = 5V. Amplitude (dBFS) 5 DNL vs. Reference Voltage. VREF = 2.5V -20 SNR = 91.5 dBFS SINAD = 91.3 dBFS SFDR = 108.5 dBc THD = -102.2 dBc Offset = 1 LSB Resolution = 16-bit -60 -100 -120 fs = 0.5 Msps SNR = 86.9 dBFS SINAD = 86.5 dBFS SFDR = 97.2 dBc THD = -95.6 dBc Offset = -2 LSB Resolution = 16-bit -40 -60 -80 -100 -120 -140 -140 -160 4.5 MCP33131D-10 fs = 1 Msps -40 -160 4 0 -20 Amplitude (dBFS) FIGURE 2-10: MCP33131D-10 0 3.5 Reference Voltage (V) 0 50 100 150 200 250 Frequency (kHz) FIGURE 2-9: FFT for 10 kHz Input Signal: fS = 500 kSPS, VIN = -1 dBFS, VREF = 5V. DS20005947B-page 12 -160 0 50 100 150 200 250 Frequency (kHz) FIGURE 2-12: FFT for 10 kHz Input Signal: fS = 500 kSPS, VIN = -1 dBFS, VREF = 2.5V.  2017 Microchip Technology Inc. MCP33131D/MCP33121D/MCP33111D-XX Note: Unless otherwise specified, all parameters apply for TA = +25°C, AVDD = 1.8V, DVIO = 3.3V, VREF = 5V, GND = 0V, Differential Analog Input (VIN) = -1 dBFS, fIN = 10 kHz, CLOAD_SDO = 20 pF. MCP33131D-10: Sample Rate (fS) = 1 Msps, SPI Clock Input (SCLK) = 60 MHz. MCP33131D-05: Sample Rate (fS) = 500 kSPS, SPI Clock Input (SCLK) = 30 MHz. 95 15.5 -92 107 -95 102 87.5 85 13.5 SFDR (dB) -98 97 ENOB SNR (dB) SINAD (dB) 82.5 80 THD (dB) 2 2.5 3 3.5 4 4.5 5 12.5 5.5 -101 Reference Voltage (V) FIGURE 2-13: 2 2.5 3 3.5 4 SNR/SINAD/ENOB vs. VREF FIGURE 2-16: VREF = 2.5V SNR/SINAD (dB) SNR/SINAD (dB) 92 5.5 87 90.4 90.2 90 SNR (dB) 89.8 86 85 SNR (dB) 84 SINAD (dB) SINAD (dB) 89.6 -40 -20 0 20 40 60 83 -40 -20 80 100 120 140 0 20 40 60 80 100 120 140 Temperature (oC) Temperature (oC) FIGURE 2-17: SNR/SINAD vs. Temperature: VREF = 2.5V. FIGURE 2-14: SNR/SINAD vs. Temperature: VREF = 5V. 90 95 89 SNR/SINAD (dBFS) VREF = 5V 93 91 89 85 -30 5 SFDR/THD vs. VREF VREF = 5V 87 4.5 Reference Voltage (V) 90.6 SNR/SINAD (dBFS) SFDR (dB) 14.5 THD (dB) 90 ENOB (Bits) SNR/SINAD (dB) 92.5 SNR (dBFS) SINAD(dBFS) -25 -20 VREF = 2.5V 88 87 86 85 84 83 82 SNR (dBFS) SINAD(dBFS) 81 -15 -10 -5 Input Amplitude (dBFS) FIGURE 2-15: SNR/SINAD vs. Input Amplitude: FIN = 10 kHz.  2017 Microchip Technology Inc. 0 80 -30 -25 -20 -15 -10 -5 0 Input Amplitude (dBFS) FIGURE 2-18: SNR/SINAD vs. Input Amplitude: FIN = 10 kHz. DS20005947B-page 13 MCP33131D/MCP33121D/MCP33111D-XX Unless otherwise specified, all parameters apply for TA = +25°C, AVDD = 1.8V, DVIO = 3.3V, VREF = 5V, GND = 0V, Differential Analog Input (VIN) = -1 dBFS, fIN = 10 kHz, CLOAD_SDO = 20 pF. MCP33131D-10: Sample Rate (fS) = 1 Msps, SPI Clock Input (SCLK) = 60 MHz. MCP33131D-05: Sample Rate (fS) = 500 kSPS, SPI Clock Input (SCLK) = 30 MHz. 95 95 V REF = 2.5V 90 SNR/SINAD (dB) 85 80 SNR (dB) 75 85 80 SNR (dB) 75 SINAD (dB) 70 100 90 101 102 SINAD (dB) 70 100 103 101 Input Frequency (kHz) -92 -92 106 104 -96 102 VREF = 5V -98 100 -100 98 20 40 60 -95 VREF = 2.5V 97 -96 96 -97 95 0 20 40 60 94 80 100 120 140 Temperature (oC) FIGURE 2-23: THD/SFDR vs. Temperature: VREF = 2.5V. FIGURE 2-20: THD/SFDR vs. Temperature: VREF = 5V. -75 110 THD (dB) SFDR (dB) -75 110 THD (dB) SFDR (dB) -80 -85 100 -85 100 -90 95 -90 95 -95 90 -95 90 -100 85 -100 85 80 -105 -105 -110 0 10 VREF = 5V 10 1 10 2 75 3 10 Input Frequency (kHz) FIGURE 2-21: THD/SFDR vs. Input Frequency: VREF = 5V. DS20005947B-page 14 THD (dB) 105 SFDR (dB) THD (dB) 98 -98 -40 -20 96 80 100 120 140 99 -94 Temperature (oC) -80 100 THD (dB) SFDR (dB) -93 THD (dB) -94 SFDR (dB) THD (dB) THD (dB) SFDR (dB) 0 103 FIGURE 2-22: SNR/SINAD vs.Input Frequency: VIN = -1 dBFS. FIGURE 2-19: SNR/SINAD vs.Input Frequency: VIN = -1 dBFS. -102 -40 -20 102 Input Frequency (kHz) SFDR (dB) SNR/SINAD (dB) V REF = 5V -110 0 10 105 SFDR (dB) Note: 80 VREF = 2.5V 10 1 10 2 75 3 10 Input Frequency (kHz) FIGURE 2-24: THD/SFDR vs. Input Frequency: VREF = 2.5V.  2017 Microchip Technology Inc. MCP33131D/MCP33121D/MCP33111D-XX Unless otherwise specified, all parameters apply for TA = +25°C, AVDD = 1.8V, DVIO = 3.3V, VREF = 5V, GND = 0V, Differential Analog Input (VIN) = -1 dBFS, fIN = 10 kHz, CLOAD_SDO = 20 pF. MCP33131D-10: Sample Rate (fS) = 1 Msps, SPI Clock Input (SCLK) = 60 MHz. MCP33131D-05: Sample Rate (fS) = 500 kSPS, SPI Clock Input (SCLK) = 30 MHz. -65 110 THD (dB) SFDR (dB) -70 100 -75 -80 95 -85 VREF = 5V 90 -90 85 -95 -100 -105 -30 -25 -20 -15 -10 -5 0 THD (dB) 105 -75 SFDR (dB) THD (dB) -70 -65 105 THD (dB) SFDR (dB) 95 -80 -85 90 VREF = 2.5V 80 80 -95 75 75 -100 70 70 -105 -30 -25 -20 -15 -10 -5 0 65 Input Amplitude (dBFS) FIGURE 2-28: THD/SFDR vs. Input Amplitude: VREF = 2.5V. FIGURE 2-25: THD/SFDR vs. Input Amplitude: VREF = 5V.
105 6 V REF = 5V 665631 85 -90 Input Amplitude (dBFS) 8 100 SFDR (dB) Note:
105 V REF = 2.5V 485575 5 Occurrences 4 165598 134228 2 242712 2 83720 125959 1 2 3 63608 32905 41102 117 0 3 1 41867 33 0 -6 -5 -4 -3 -2 -1 4 4 5 0 -10 -9 -8 -7 -6 -5 -4 -3 -2 -1 0 1 2 3 4 5 6 6 Output Code Output Code Shorted Input Histogram: FIGURE 2-29: VREF = 2.5V. Shorted Input Histogram: 3.9 400 5.2 500 3.3 300 3.9 200 2.6 100 1.3 400 2.6 Gain Error 300 2 200 1.3 100 0.66 Offset Error 0 -100 -40 -20 0 20 40 VREF = 5V 60 80 0 -0.66 100 120 140 o Temperature ( C) FIGURE 2-27: Offset and Gain Error vs. Temperature: VREF = 5V.  2017 Microchip Technology Inc. Offset/Gain Error (uV) 600 Offset/Gain Error (LSB) Offset/Gain Error (uV) FIGURE 2-26: VREF = 5V. 13523 73 10 490 0 -100 -200 -300 -40 0 Gain Error -1.3 VREF = 2.5V Offset Error -20 0 20 40 60 80 -2.6 Offset/Gain Error (LSB) Occurrences 6 -3.9 100 120 140 o Temperature ( C) FIGURE 2-30: Offset and Gain Error vs. Temperature: VREF = 2.5V. DS20005947B-page 15 MCP33131D/MCP33121D/MCP33111D-XX Note: Unless otherwise specified, all parameters apply for TA = +25°C, AVDD = 1.8V, DVIO = 3.3V, VREF = 5V, GND = 0V, Differential Analog Input (VIN) = -1 dBFS, fIN = 10 kHz, CLOAD_SDO = 20 pF. MCP33131D-10: Sample Rate (fS) = 1 Msps, SPI Clock Input (SCLK) = 60 MHz. MCP33131D-05: Sample Rate (fS) = 500 kSPS, SPI Clock Input (SCLK) = 30 MHz. 8 86 V REF 16 = 5V 78 1. 8V ) 8 D (A V D = 4 IIO_STBY (DVIO = 3.3V) Y CMRR (dB) 80 12 Total Power Consumption TB Current (
A) 6 82 4 I D D A N _S 2 Total Power (
W) 84 76 10-1 100 101 102 103 Temperature (°C) Input Frequency (kHz) FIGURE 2-31: VREF = 5V. CMRR vs. Input Frequency: 2 FIGURE 2-34: Power Consumption vs. Temperature during Shutdown. 2 8 on (AV D D I DDAN er ow pti um s on 4 C P tal To 2 I REF (V REF = 5V) (AV DD 1 0.5 0 0.1 10 IREF (VREF = 5V) 2 1.5 Current (mA) 6 Total Power (mW) Current (mA) ption 4 0 20 35 50 65 80 95 110 125 Temperature (°C) FIGURE 2-33: Power Consumption vs. Temperature: CLOAD_SDO = 20 pF. DS20005947B-page 16 0.4 0 0.5 8 1 I DDAN (AV DD Total Power = 1.8V) Consumption 0.5 6 4 2 IREF (VREF = 5V) IIO_DATA (DVIO = 3.3V) 0 -40 -25 -10 5 0.3 MCP331x1D-05 8 1 0.5 2 IREF (VREF = 5V) 2 = 1.8V er Consum Total Pow 1.5 0.2 C FIGURE 2-35: Power Consumption vs. Sample Rate: CLOAD_SDO = 20 pF. ) I DDAN wer l Po Tota um ons Sample Rate (Msps) 2.5 2 4 n ptio 0 FIGURE 2-32: Power Consumption vs. Sample Rate: CLOAD_SDO = 20 pF. (AV DD =1 I DDAN 1 Sample Rate (Msps) MCP331x1D-10 6 ) .8V IIO_DATA (DVIO = 3.3V) ) I IO_DATA (DVIO = 3.3V 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.5 Current (mA) 6 ) .8V =1 Total Power (mW) Current (mA) 1.5 0.5 8 MCP331x1D-05 MCP331x1D-10 1 0 20 35 50 65 80 95 110 125 Total Power (mW) 10-2 Total Power (mW) 74 10-3 IREF_STBY (VREF = 5V) 0 -40 -25 -10 5 0 -40 -25 -10 5 IIO_DATA (DVIO = 3.3V) 0 20 35 50 65 80 95 110 125 Temperature (°C) FIGURE 2-36: Power Consumption vs. Temperature: CLOAD_SDO = 20 pF.  2017 Microchip Technology Inc. MCP33131D/MCP33121D/MCP33111D-XX 3.0 TYPICAL PERFORMANCE CURVES FOR 14-BIT DEVICES (MCP33121D-XX) Note: The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore outside the warranted range. Note: Unless otherwise specified, all parameters apply for TA = +25°C, AVDD = 1.8V, DVIO = 3.3V, VREF = 5V, GND = 0V, Differential Analog Input (VIN) = -1 dBFS, fIN = 10 kHz, CLOAD_SDO = 20 pF. MCP33121D-10: Sample Rate (fS) = 1 Msps, SPI Clock Input (SCLK) = 60 MHz. MCP33121D-05: Sample Rate (fS) = 500 kSPS, SPI Clock Input (SCLK) = 30 MHz. 1 1 V REF = 5V V REF = 2.5V 0.5 INL (LSB) INL (LSB) 0.5 0 -0.5 -1 0 -0.5 0 4,096 8,192 12,288 -1 16,384 0 4,096 8,192 Code FIGURE 3-1: 12,288 INL vs. Output Code. FIGURE 3-4: 1 INL vs. Output Code. 1 V REF = 5V V REF = 2.5V 0.5 DNL (LSB) DNL (LSB) 0.5 0 -0.5 -1 0 -0.5 0 4,096 8,192 12,288 -1 16,384 0 4,096 8,192 Code FIGURE 3-2: DNL vs. Output Code. FIGURE 3-5: 16,384 DNL vs. Output Code. 1 Max INL (LSB) Max DNL (LSB) 0.5 V REF = 5V 0 -0.5 DNL (LSB) 0.5 V REF = 5V 0 -0.5 Min INL (LSB) -1 -40 12,288 Code 1 INL (LSB) 16,384 Code -20 0 20 40 60 Min DNL (LSB) 80 100 120 140 -1 -40 -20 o FIGURE 3-3: INL vs. Temperature.  2017 Microchip Technology Inc. 0 20 40 60 80 100 120 140 o Temperature ( C) Temperature ( C) FIGURE 3-6: DNL vs. Temperature. DS20005947B-page 17 MCP33131D/MCP33121D/MCP33111D-XX Note: Unless otherwise specified, all parameters apply for TA = +25°C, AVDD = 1.8V, DVIO = 3.3V, VREF = 5V, GND = 0V, Differential Analog Input (VIN) = -1 dBFS, fIN = 10 kHz, CLOAD_SDO = 20 pF. MCP33121D-10: Sample Rate (fS) = 1 Msps, SPI Clock Input (SCLK) = 60 MHz. MCP33121D-05: Sample Rate (fS) = 500 kSPS, SPI Clock Input (SCLK) = 30 MHz. 1 1 Max INL (LSB) DNL (LSB) INL (LSB) Max DNL (LSB) 0.5 0.5 0 0 -0.5 -0.5 Min DNL (LSB) Min INL (LSB) -1 2 2.5 3 3.5 4 4.5 5 -1 5.5 2 2.5 3 FIGURE 3-7: INL vs. Reference Voltage. VREF = 5V -20 -80 -100 -120 0 100 200 300 400 -40 -60 -80 -100 -120 -160 500 0 100 200 MCP33121D-05 -80 Amplitude (dBFS) -60 VREF = 2.5V -20 fs = 0.5 Msps SNR = 85.1 dBFS SINAD = 85.1 dBFS SFDR = 107.9 dBc THD = -102.1 dBc Offset = 0 LSB Resolution = 14-bit -40 500 MCP33121D-05 0 -20 400 FIGURE 3-11: FFT for 10 kHz Input Signal: fS = 1 Msps, VIN = -1 dBFS, VREF = 2.5V. 0 VREF = 5V 300 Frequency (kHz) FIGURE 3-8: FFT for 10 kHz Input Signal: fS = 1 Msps, VIN = -1 dBFS, VREF = 5V. Amplitude (dBFS) fs = 1 Msps SNR = 83.4 dBFS SINAD = 83.2 dBFS SFDR = 96.9 dBc THD = -95.4 dBc Offset = -1 LSB Resolution = 14-bit Frequency (kHz) -100 -120 fs = 0.5 Msps SNR = 83.6 dBFS SINAD = 83.4 dBFS SFDR = 97.3 dBc THD = -95.5 dBc Offset = -1 LSB Resolution = 14-bit -40 -60 -80 -100 -120 -140 -140 -160 5.5 -140 -140 -160 5 DNL vs. Reference Voltage. VREF = 2.5V -20 SNR = 85.2 dBFS SINAD = 85.2 dBFS SFDR = 106.9 dBc THD = -100.2 dBc Offset = 0 LSB Resolution = 14-bit -60 4.5 MCP33121D-10 fs = 1 Msps -40 4 0 Amplitude (dBFS) Amplitude (dBFS) FIGURE 3-10: MCP33121D-10 0 3.5 Reference Voltage (V) Reference Voltage (V) 0 50 100 150 200 250 Frequency (kHz) FIGURE 3-9: FFT for 10 kHz Input Signal: fS = 500 kSPS, VIN = -1 dBFS, VREF = 5V. DS20005947B-page 18 -160 0 50 100 150 200 250 Frequency (kHz) FIGURE 3-12: FFT for 10 kHz Input Signal: fS = 500 kSPS, VIN = -1 dBFS, VREF = 2.5V.  2017 Microchip Technology Inc. MCP33131D/MCP33121D/MCP33111D-XX Note: Unless otherwise specified, all parameters apply for TA = +25°C, AVDD = 1.8V, DVIO = 3.3V, VREF = 5V, GND = 0V, Differential Analog Input (VIN) = -1 dBFS, fIN = 10 kHz, CLOAD_SDO = 20 pF. MCP33121D-10: Sample Rate (fS) = 1 Msps, SPI Clock Input (SCLK) = 60 MHz. MCP33121D-05: Sample Rate (fS) = 500 kSPS, SPI Clock Input (SCLK) = 30 MHz. 86 14.5 -92 107 -95 102 83 82 12.5 SFDR (dB) -98 97 ENOB SNR (dB) SINAD (dB) 81 80 THD (dB) 2 2.5 3 3.5 4 4.5 11.5 5.5 5 -101 2 2.5 3 SNR/SINAD/ENOB vs. VREF FIGURE 3-13: 3.5 4 4.5 5 92 5.5 Reference Voltage (V) Reference Voltage (V) FIGURE 3-16: SFDR/THD vs. VREF 83 84.6 V REF = 2.5V V REF = 5V 84.4 SNR/SINAD (dB) SNR/SINAD (dB) SFDR (dB) 13.5 THD (dB) 84 ENOB (Bits) SNR/SINAD (dB) 85 84.2 84 SNR (dB) 83.8 82.5 82 SNR (dB) 81.5 SINAD (dB) SINAD (dB) 83.6 -40 -20 0 20 40 60 80 81 -40 -20 100 120 140 0 20 40 60 80 Temperature ( C) FIGURE 3-17: SNR/SINAD vs. Temperature: VREF = 2.5V. FIGURE 3-14: SNR/SINAD vs. Temperature: VREF = 5V. 88 88 V REF = 2.5V 86 SNR/SINAD (dBFS) SNR/SINAD (dBFS) V REF = 5V 84 82 80 78 -30 100 120 140 Temperature (oC) o SNR (dBFS) SINAD(dBFS) -25 -20 -15 -10 -5 Input Amplitude (dBFS) FIGURE 3-15: SNR/SINAD vs. Input Amplitude: FIN = 10 kHz.  2017 Microchip Technology Inc. 0 86 84 82 80 78 -30 SNR (dBFS) SINAD(dBFS) -25 -20 -15 -10 -5 0 Input Amplitude (dBFS) FIGURE 3-18: SNR/SINAD vs. Input Amplitude: FIN = 10 kHz. DS20005947B-page 19 MCP33131D/MCP33121D/MCP33111D-XX Unless otherwise specified, all parameters apply for TA = +25°C, AVDD = 1.8V, DVIO = 3.3V, VREF = 5V, GND = 0V, Differential Analog Input (VIN) = -1 dBFS, fIN = 10 kHz, CLOAD_SDO = 20 pF. MCP33121D-10: Sample Rate (fS) = 1 Msps, SPI Clock Input (SCLK) = 60 MHz. MCP33121D-05: Sample Rate (fS) = 500 kSPS, SPI Clock Input (SCLK) = 30 MHz. 90 90 V REF = 2.5V 85 SNR/SINAD (dB) 80 75 SNR (dB) 70 10 80 75 SNR (dB) 70 SINAD (dB) 65 0 10 85 1 10 2 10 SINAD (dB) 65 0 10 3 10 Input Frequency (kHz) 1 -92 3 100 THD (dB) SFDR (dB) 104 -96 102 V REF = 5V -98 100 -100 THD (dB) -94 SFDR (dB) THD (dB) 10 -92 106 SFDR (dB) THD (dB) -94 98 V REF = 2.5V -96 96 98 0 20 40 96 80 100 120 140 60 -98 -40 -20 o Temperature ( C) 0 20 40 60 94 80 100 120 140 o Temperature Temperature (o(C)C) FIGURE 3-23: THD/SFDR vs. Temperature: VREF = 2.5V. FIGURE 3-20: THD/SFDR vs. Temperature: VREF = 5V. -75 -75 110 THD (dB) SFDR (dB) 110 THD (dB) SFDR (dB) -85 100 -85 100 -90 95 -90 95 -95 90 -95 90 -100 85 -100 85 80 -105 -105 -110 100 VREF = 5V 101 102 75 103 Input Frequency (kHz) FIGURE 3-21: THD/SFDR vs. Input Frequency: VREF = 5V. DS20005947B-page 20 THD (dB) -80 SFDR (dB) 105 -80 THD (dB) 2 FIGURE 3-22: SNR/SINAD vs.Input Frequency: VIN = -1 dBFS. FIGURE 3-19: SNR/SINAD vs.Input Frequency: VIN = -1 dBFS. -102 -40 -20 10 Input Frequency (kHz) SFDR (dB) SNR/SINAD (dB) V REF = 5V -110 0 10 105 SFDR (dB) Note: 80 VREF = 2.5V 10 1 10 2 75 3 10 Input Frequency (kHz) FIGURE 3-24: THD/SFDR vs. Input Frequency: VREF = 2.5V.  2017 Microchip Technology Inc. MCP33131D/MCP33121D/MCP33111D-XX Unless otherwise specified, all parameters apply for TA = +25°C, AVDD = 1.8V, DVIO = 3.3V, VREF = 5V, GND = 0V, Differential Analog Input (VIN) = -1 dBFS, fIN = 10 kHz, CLOAD_SDO = 20 pF. MCP33121D-10: Sample Rate (fS) = 1 Msps, SPI Clock Input (SCLK) = 60 MHz. MCP33121D-05: Sample Rate (fS) = 500 kSPS, SPI Clock Input (SCLK) = 30 MHz. -65 105 THD (dB) SFDR (dB) -75 100 -75 95 -80 95 -80 90 VREF = 5V -85 90 THD (dB) -70 SFDR (dB) 105 -70 THD (dB) -65 110 THD (dB) SFDR (dB) 100 VREF = 2.5V -85 85 -90 85 -90 80 -95 80 -95 75 -100 75 -100 70 70 -105 -30 -105 -30 -25 -20 -15 -10 -5 0 -25 Input Amplitude (dBFS)
10 10 -5 0 65
105 VREF = 5V VREF = 2.5V 844912 8 8 Occurrences Occurrences -10 FIGURE 3-28: THD/SFDR vs. Input Amplitude: VREF = 2.5V. 5 872448 -15 Input Amplitude (dBFS) FIGURE 3-25: THD/SFDR vs. Input Amplitude: VREF = 5V. 10 -20 SFDR (dB) Note: 6 4 176128 2 6 4 203163 2 501 -2 -1 0 1 2 0 -4 3 -3 -2 Output Code Shorted Input Histogram: 0 1 2 3 FIGURE 3-29: VREF = 2.5V. Shorted Input Histogram: 0.82 300 0.98 400 0.66 200 0.66 100 0.33 300 0.49 Gain Error 200 0.33 100 0.16 0 0 Offset Error VREF = 5V -100 -200 -40 -20 0 20 40 60 80 -0.16 -0.33 100 120 140 Temperature (oC) FIGURE 3-27: Offset and Gain Error vs. Temperature: VREF = 5V.  2017 Microchip Technology Inc. Offset/Gain Error (uV) 500 Offset/Gain Error (LSB) Offset/Gain Error (uV) FIGURE 3-26: VREF = 5V. -1 Output Code 0 0 Gain Error -100 -0.33 -200 -0.66 Offset Error -300 -400 -40 -20 0 20 40 VREF = 2.5V 60 80 -0.98 Offset/Gain Error (LSB) 0 -3 -1.3 100 120 140 Temperature (oC) FIGURE 3-30: Offset and Gain Error vs. Temperature: VREF = 2.5V. DS20005947B-page 21 MCP33131D/MCP33121D/MCP33111D-XX Note: Unless otherwise specified, all parameters apply for TA = +25°C, AVDD = 1.8V, DVIO = 3.3V, VREF = 5V, GND = 0V, Differential Analog Input (VIN) = -1 dBFS, fIN = 10 kHz, CLOAD_SDO = 20 pF. MCP33121D-10: Sample Rate (fS) = 1 Msps, SPI Clock Input (SCLK) = 60 MHz. MCP33121D-05: Sample Rate (fS) = 500 kSPS, SPI Clock Input (SCLK) = 30 MHz. 86 V REF 8 = 5V 16 1. 8V ) D V D = 8 (A 78 4 IIO_STBY (DVIO = 3.3V) Y CMRR (dB) 80 12 Total Power Consumption TB Current (
A) 6 82 4 D A N _S 2 Total Power (
W) 84 I D 76 IREF_STBY (VREF = 5V) 10-1 100 101 102 0 -40 -25 -10 5 103 Input Frequency (kHz) FIGURE 3-31: VREF = 5V. Temperature (°C) CMRR vs. Input Frequency: 2 FIGURE 3-34: Power Consumption vs. Temperature during Shutdown. 8 2 MCP331x1D-10 D pti um s on 4 C er ow lP ta To 2 I REF (V REF = 5V) (AV DD 1 =1 I DDAN 1 4 tion ump 0 0.1 Sample Rate (Msps) 0.2 ns r Co we l Po Tota 0.5 0 2 IREF (VREF = 5V) 0.3 0.4 0 0.5 Sample Rate (Msps) FIGURE 3-32: Power Consumption vs. Sample Rate: CLOAD_SDO = 20 pF. 2.5 FIGURE 3-35: Power Consumption vs. Sample Rate: CLOAD_SDO = 20 pF. 10 MCP331x1D-10 1 6 4 IREF (VREF = 5V) 0.5 2 1.5 Current (mA) Total Pow 8 8 MCP331x1D-05 Total Power (mW) (AV DD = 1.8V ption er Consum 1.5 2 ) I DDAN 2 Current (mA) 6 ) .8V IIO_DATA (DVIO = 3.3V) ) I IO_DATA (DVIO = 3.3V 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.5 Current (mA) on (AV D I DDAN Total Power (mW) Current (mA) 6 ) .8V =1 0.5 8 MCP331x1D-05 1.5 1 0 20 35 50 65 80 95 110 125 Total Power (mW) 10-2 1 0 20 35 50 65 80 95 110 125 Temperature (°C) FIGURE 3-33: Power Consumption vs. Temperature: CLOAD_SDO = 20 pF. DS20005947B-page 22 Total Power = 1.8V) Consumption 0.5 6 4 2 IREF (VREF = 5V) IIO_DATA (DVIO = 3.3V) 0 -40 -25 -10 5 I DDAN (AV DD Total Power (mW) 74 10-3 0 -40 -25 -10 5 IIO_DATA (DVIO = 3.3V) 0 20 35 50 65 80 95 110 125 Temperature (°C) FIGURE 3-36: Power Consumption vs.  2017 Microchip Technology Inc. MCP33131D/MCP33121D/MCP33111D-XX 4.0 TYPICAL PERFORMANCE CURVES FOR 12-BIT DEVICES (MCP33111D-XX) Note: The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore outside the warranted range. Note: Unless otherwise specified, all parameters apply for TA = +25°C, AVDD = 1.8V, DVIO = 3.3V, VREF = 5V, GND = 0V, Differential Analog Input (VIN) = -1 dBFS, fIN = 10 kHz, CLOAD_SDO = 20 pF. MCP33111D-10: Sample Rate (fS) = 1 Msps, SPI Clock Input (SCLK) = 60 MHz. MCP33111D-05: Sample Rate (fS) = 500 kSPS, SPI Clock Input (SCLK) = 30 MHz. 0.5 0.5 V REF = 5V V REF = 2.5V 0.3 INL (LSB) INL (LSB) 0.3 0.1 -0.1 -0.3 -0.5 0.1 -0.1 -0.3 0 1,024 2,048 3,072 -0.5 4,096 0 1,024 2,048 Code FIGURE 4-1: 3,072 INL vs. Output Code. FIGURE 4-4: 0.5 INL vs. Output Code. 0.5 V REF = 2.5V V REF = 5V 0.3 DNL (LSB) DNL (LSB) 0.3 0.1 -0.1 -0.3 -0.5 0.1 -0.1 -0.3 0 1,024 2,048 3,072 -0.5 4,096 0 1,024 2,048 Code FIGURE 4-2: FIGURE 4-5: 0.2 0.2 0.15 0.15 V REF = 5V 0 -0.05 DNL (LSB) 0.05 Max DNL (LSB) 0.05 V REF = 5V 0 -0.05 -0.1 -0.1 -0.2 -40 0 20 40 60 Min DNL (LSB) -0.15 Min INL (LSB) -20 80 100 120 140 -0.2 -40 -20  2017 Microchip Technology Inc. 20 40 60 80 100 120 140 Temperature ( C) Temperature ( C) INL vs. Temperature. 0 o o FIGURE 4-3: 4,096 DNL vs. Output Code. 0.1 Max INL (LSB) -0.15 3,072 Code DNL vs. Output Code. 0.1 INL (LSB) 4,096 Code FIGURE 4-6: DNL vs. Temperature. DS20005947B-page 23 MCP33131D/MCP33121D/MCP33111D-XX Note: Unless otherwise specified, all parameters apply for TA = +25°C, AVDD = 1.8V, DVIO = 3.3V, VREF = 5V, GND = 0V, Differential Analog Input (VIN) = -1 dBFS, fIN = 10 kHz, CLOAD_SDO = 20 pF. MCP33111D-10: Sample Rate (fS) = 1 Msps, SPI Clock Input (SCLK) = 60 MHz. MCP33111D-05: Sample Rate (fS) = 500 kSPS, SPI Clock Input (SCLK) = 30 MHz. 0.4 0.4 0.3 0.3 Max INL (LSB) 0.2 DNL (LSB) INL (LSB) 0.2 0.1 0 -0.1 Min INL (LSB) -0.2 Max DNL (LSB) 0.1 0 -0.1 -0.2 Min DNL (LSB) -0.3 -0.4 2 -0.3 2.5 3 3.5 4 4.5 5 -0.4 2 5.5 2.5 Reference Voltage (V) FIGURE 4-7: INL vs. Reference Voltage. MCP33111D-10 VREF = 5V 4.5 5 5.5 DNL vs. Reference Voltage. MCP33111D-10 VREF = 2.5V fs = 1 Msps SNR = 73.9 dBFS SINAD = 73.9 dBFS SFDR = 99.8 dBc THD = -96.5 dBc Offset = 0 LSB Resolution = 12-bit -40 -60 fs = 1 Msps -20 Amplitude (dBFS) Amplitude (dBFS) 4 0 -20 -80 SNR = 73.8 dBFS SINAD = 73.7 dBFS SFDR = 97.0 dBc THD = -95.6 dBc Offset = -1 LSB Resolution = 12-bit -40 -60 -80 -100 -100 0 100 200 300 400 500 -120 0 100 FIGURE 4-8: FFT for 10 kHz Input Signal: fS = 1 Msps, VIN = -1 dBFS, VREF = 5V. VREF = 5V VREF = 2.5V -80 -100 -120 fs = 0.5 Msps -20 Amplitude (dBFS) -60 500 MCP33111D-05 SNR = 74.0 dBFS SINAD = 73.9 dBFS SFDR = 99.5 dBc THD = -95.1 dBc Offset = 0 LSB Resolution = 12-bit -40 400 0 fs = 0.5 Msps -20 300 FIGURE 4-11: FFT for 10 kHz Input Signal: fS = 1 Msps, VIN = -1 dBFS, VREF = 2.5V. MCP33111D-05 0 200 Frequency (kHz) Frequency (kHz) Amplitude (dBFS) 3.5 FIGURE 4-10: 0 -120 3 Reference Voltage (V) SNR = 73.8 dBFS SINAD = 73.8 dBFS SFDR = 96.2 dBc THD = -94.3 dBc Offset = -1 LSB Resolution = 12-bit -40 -60 -80 -100 0 50 100 150 200 250 Frequency (kHz) FIGURE 4-9: FFT for 10 kHz Input Signal: fS = 500 kSPS, VIN = -1 dBFS, VREF = 5V. DS20005947B-page 24 -120 0 50 100 150 200 250 Frequency (kHz) FIGURE 4-12: FFT for 10 kHz Input Signal: fS = 500 kSPS, VIN = -1 dBFS, VREF = 2.5V.  2017 Microchip Technology Inc. MCP33131D/MCP33121D/MCP33111D-XX Unless otherwise specified, all parameters apply for TA = +25°C, AVDD = 1.8V, DVIO = 3.3V, VREF = 5V, GND = 0V, Differential Analog Input (VIN) = -1 dBFS, fIN = 10 kHz, CLOAD_SDO = 20 pF. MCP33111D-10: Sample Rate (fS) = 1 Msps, SPI Clock Input (SCLK) = 60 MHz. MCP33111D-05: Sample Rate (fS) = 500 kSPS, SPI Clock Input (SCLK) = 30 MHz. 73 12 72.8 11 -91 105 -94 100 THD (dB) SFDR (dB) -97 95 SFDR (dB) 13 THD (dB) 73.2 ENOB (Bits) SNR/SINAD (dB) Note: ENOB SNR (dB) SINAD (dB) 72.6 2 2.5 3 3.5 4 4.5 5 10 5.5 -100 2 2.5 3 4 4.5 SNR/SINAD/ENOB vs. VREF FIGURE 4-16: SFDR/THD vs. VREF 72.9 72.98 VREF = 2.5V VREF = 5V SNR/SINAD (dB) SNR/SINAD (dB) 72.97 72.96 72.95 72.94 SNR (dB) 72.93 72.85 72.8 72.75 SNR (dB) 72.7 SINAD (dB) SINAD (dB) 72.92 -40 -20 0 20 40 60 72.65 -40 -20 80 100 120 140 0 20 40 60 80 100 120 140 Temperature (oC) o Temperature ( C) FIGURE 4-17: SNR/SINAD vs. Temperature: VREF = 2.5V. FIGURE 4-14: SNR/SINAD vs. Temperature: VREF = 5V. 75 75 V REF = 2.5V 74 SNR/SINAD (dBFS) SNR/SINAD (dBFS) V REF = 5V 73 72 71 70 -30 90 5.5 5 Reference Voltage (V) Reference Voltage (V) FIGURE 4-13: 3.5 SNR (dBFS) SINAD(dBFS) -25 -20 -15 -10 -5 Input Amplitude (dBFS) FIGURE 4-15: SNR/SINAD vs. Input Amplitude: FIN = 10 kHz.  2017 Microchip Technology Inc. 0 74 73 72 71 70 -30 SNR (dBFS) SINAD(dBFS) -25 -20 -15 -10 -5 0 Input Amplitude (dBFS) FIGURE 4-18: SNR/SINAD vs. Input Amplitude: FIN = 10 kHz. DS20005947B-page 25 MCP33131D/MCP33121D/MCP33111D-XX Unless otherwise specified, all parameters apply for TA = +25°C, AVDD = 1.8V, DVIO = 3.3V, VREF = 5V, GND = 0V, Differential Analog Input (VIN) = -1 dBFS, fIN = 10 kHz, CLOAD_SDO = 20 pF. MCP33111D-10: Sample Rate (fS) = 1 Msps, SPI Clock Input (SCLK) = 60 MHz. MCP33111D-05: Sample Rate (fS) = 500 kSPS, SPI Clock Input (SCLK) = 30 MHz. 80 80 V REF = 2.5V 75 SNR/SINAD (dB) 70 SNR (dB) 65 SINAD (dB) 60 0 10 10 1 10 2 10 75 70 SNR (dB) 65 SINAD (dB) 60 0 10 3 10 Input Frequency (kHz) 98 -96 THD (dB) VREF = 5V 96 -97 40 60 98 -93 97 VREF = 2.5V -94 96 -95 95 -96 -40 -20 94 80 100 120 140 0 20 40 94 80 100 120 140 60 o o Temperature ( C) Temperature ( C) FIGURE 4-23: THD/SFDR vs. Temperature: VREF = 2.5V. FIGURE 4-20: THD/SFDR vs. Temperature: VREF = 5V. -75 -75 110 THD (dB) SFDR (dB) 110 THD (dB) SFDR (dB) -85 100 -85 100 -90 95 -90 95 -95 90 -95 90 -100 85 -100 85 80 -105 -105 -110 0 10 VREF = 5V 10 1 10 2 75 3 10 Input Frequency (kHz) FIGURE 4-21: THD/SFDR vs. Input Frequency: VREF = 5V. DS20005947B-page 26 THD (dB) -80 SFDR (dB) 105 -80 THD (dB) 99 -92 SFDR (dB) THD (dB) -94 20 3 THD (dB) SFDR (dB) 100 0 10 -91 THD (dB) SFDR (dB) -98 -40 -20 2 FIGURE 4-22: SNR/SINAD vs. Input Frequency: VIN = -1 dBFS. 102 -92 -93 10 Input Frequency (kHz) FIGURE 4-19: SNR/SINAD vs. Input Frequency: VIN = -1 dBFS -95 1 SFDR (dB) SNR/SINAD (dB) V REF = 5V -110 0 10 105 SFDR (dB) Note: 80 VREF = 2.5V 10 1 10 2 75 3 10 Input Frequency (kHz) FIGURE 4-24: THD/SFDR vs. Input Frequency: VREF = 2.5V.  2017 Microchip Technology Inc. MCP33131D/MCP33121D/MCP33111D-XX Unless otherwise specified, all parameters apply for TA = +25°C, AVDD = 1.8V, DVIO = 3.3V, VREF = 5V, GND = 0V, Differential Analog Input (VIN) = -1 dBFS, fIN = 10 kHz, CLOAD_SDO = 20 pF. MCP33111D-10: Sample Rate (fS) = 1 Msps, SPI Clock Input (SCLK) = 60 MHz. MCP33111D-05: Sample Rate (fS) = 500 kSPS, SPI Clock Input (SCLK) = 30 MHz. -65 -70 95 -70 95 -75 90 -75 90 -80 85 VREF = 5V 80 -80 -85 105 THD (dB) SFDR (dB) 85 VREF = 2.5V 80 -90 75 -90 75 -95 70 -95 70 -100 65 -100 65 -105 -30 60 -105 -30 -25 -20 -15 -10 -5 0 -25 -20 Input Amplitude (dBFS) 10 10
10 -5 0 60 5 V REF = 5V V REF = 2.5V 845413 8 8 Occurrences Occurrences -10 FIGURE 4-28: THD/SFDR vs. Input Amplitude: VREF = 2.5V.
105 872448 -15 Input Amplitude (dBFS) FIGURE 4-25: THD/SFDR vs. Input Amplitude: VREF = 5V. 6 4 176128 2 0 -3 -2 -1 6 4 203163 2 0 1 2 0 -3 3 -2 -1 FIGURE 4-26: VREF = 5V. Shorted Input Histogram: 0 -200 -0.082 -400 -0.16 -600 -0.25 Offset Error VREF = 5V -800 -20 0 20 40 60 80 -0.33 -0.41 100 120 140 o Temperature ( C) FIGURE 4-27: Offset and Gain Error vs. Temperature: VREF = 5V.  2017 Microchip Technology Inc. 1 2 Shorted Input Histogram: 0 Offset/Gain Error (uV) 0.082 Gain Error 0 -1000 -40 FIGURE 4-29: VREF = 2.5V. 0.16 Offset/Gain Error (LSB) 400 200 0 Output Code Output Code Offset/Gain Error (uV) 100 0 Gain Error -200 -0.16 -400 -0.33 Offset Error -600 -0.49 VREF = 2.5V -800 -40 -20 0 20 40 60 80 Offset/Gain Error (LSB) THD (dB) -85 THD (dB) -60 100 THD (dB) SFDR (dB) -65 SFDR (dB) 105 -60 SFDR (dB) Note: -0.66 100 120 140 o Temperature ( C) FIGURE 4-30: Offset and Gain Error vs. Temperature: VREF = 2.5V. DS20005947B-page 27 MCP33131D/MCP33121D/MCP33111D-XX Note: Unless otherwise specified, all parameters apply for TA = +25°C, AVDD = 1.8V, DVIO = 3.3V, VREF = 5V, GND = 0V, Differential Analog Input (VIN) = -1 dBFS, fIN = 10 kHz, CLOAD_SDO = 20 pF. MCP33111D-10: Sample Rate (fS) = 1 Msps, SPI Clock Input (SCLK) = 60 MHz. MCP33111D-05: Sample Rate (fS) = 500 kSPS, SPI Clock Input (SCLK) = 30 MHz. 8 86 V REF 16 = 5V 78 1. 8V ) 8 D (A V D = 4 IIO_STBY (DVIO = 3.3V) Y CMRR (dB) 80 12 Total Power Consumption TB Current (
A) 6 82 4 I D D A N _S 2 Total Power (
W) 84 76 10-2 10-1 100 101 102 103 Temperature (°C) Input Frequency (kHz) FIGURE 4-31: VREF = 5V. CMRR vs. Input Frequency: 2 FIGURE 4-34: Power Consumption vs. Temperature during Shutdown. 2 8 (AV D on D AN I DD er ow pti m su 4 n Co P tal To 2 I REF (V REF = 5V) 6 ) (AV DD 1 = V 1.8 I DDAN 1 4 n ptio wer l Po Tota 0.5 0 0 0.1 Sample Rate (Msps) 0.2 um ons C 2 IREF (VREF = 5V) IIO_DATA (DVIO = 3.3V) ) I IO_DATA (DVIO = 3.3V 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.5 Current (mA) 6 V) .8 =1 Total Power (mW) Current (mA) 1.5 0.5 8 MCP331x1D-05 MCP331x1D-10 1 0 20 35 50 65 80 95 110 125 Total Power (mW) 74 10-3 IREF_STBY (VREF = 5V) 0 -40 -25 -10 5 0.3 0.4 0 0.5 Sample Rate (Msps) FIGURE 4-35: Power Consumption vs. Sample Rate: CLOAD_SDO = 20 pF. FIGURE 4-32: Power Consumption vs. Sample Rate: CLOAD_SDO = 20 pF. MCP331x1D-10 = 1.8V Total Pow 1.5 1 6 4 IREF (VREF = 5V) 0.5 2 IIO_DATA (DVIO = 3.3V) 0 -40 -25 -10 5 0 20 35 50 65 80 95 110 125 Temperature (°C) FIGURE 4-33: Power Consumption vs. Temperature: CLOAD_SDO = 20 pF. DS20005947B-page 28 1.5 Current (mA) ption er Consum 8 Total Power (mW) (AV DD 8 MCP331x1D-05 ) I DDAN 2 Current (mA) 2 10 MCP331x1D-10 1 I DDAN (AV DD Total Power = 1.8V) Consumption 0.5 6 4 2 Total Power (mW) 2.5 IREF (VREF = 5V) 0 -40 -25 -10 5 IIO_DATA (DVIO = 3.3V) 0 20 35 50 65 80 95 110 125 Temperature (°C) FIGURE 4-36: Power Consumption vs. Temperature: CLOAD_SDO = 20 pF.  2017 Microchip Technology Inc. MCP33131D/MCP33121D/MCP33111D-XX 5.0 PIN FUNCTION DESCRIPTIONS TABLE 5-1: PIN FUNCTION TABLE Pin Number Pin Name Function 1 VREF 2 AVDD 3 4 5 AIN+ AINGND 6 CNVST 7 SDO 8 SCLK 9 10 SDI DVIO Reference voltage input (2.5V - 5.1V). This pin should be decoupled with a 10 F tantalum capacitor. DC supply voltage input for analog section (1.8V). This pin should be decoupled with a 1 F ceramic capacitor. Differential positive analog input. Differential negative analog input. Power supply ground reference. This pin is a common ground for both the analog power supply (AVDD) and digital I/O supply (DVIO). Conversion-start control and active-low SPI chip-select digital input. A new conversion is started on the rising edge of CNVST. When the conversion is complete, output data is available at SDO by lowering CNVST. SPI-compatible serial digital data output: ADC conversion data is shifted out by SCLK clock, with MSB first. SPI-compatible serial data clock digital input. The ADC output is synchronously shifted out by this clock. SPI-compatible serial data digital input. Tie to DVIO for normal operation. DC supply voltage for digital input/output interface (1.7V - 5.5V). This pin should be decoupled with a 0.1 F ceramic capacitor. 5.1 Supply Voltages and Reference Voltage Note: The device has two power supply pins: Analog power supply (AVDD): 1.8V Digital input/output interface power supply (DVIO): 1.7V to 5.5V. a) b) The large supply voltage range of DVIO allows the device to interface with various host devices that are y operating with different supply voltages. See Table 1-2 for timing specifications for I/O interface signal parameters depending on DVIO voltage. Note: 5.2 Proper decoupling capacitors (1 F to AVDD, 0.1 F to DVIO) should be mounted as close as possible to the respective pins. Reference Voltage (VREF) 5.2.1 During the initial power-up sequence, the reference voltage (VREF) must be provided prior to supplying AVDD or within about 64 ms after supplying AVDD. Otherwise, it is strongly recommended to send a recalibrate command. See Section 7.1 “Recalibrate Command” for more details. VOLTAGE REFERENCE SELECTION The performance of the voltage reference has a large impact on the accuracy of high-precision data acquisition systems. The voltage reference should have high-accuracy, low-noise, and low-temperature drift. A ±0.1% output accuracy of the reference directly corresponds to ±0.1% absolute accuracy of the ADC output. The RMS output noise voltage of the reference should be less than 1/2 LSB of the ADC. The device requires a single-ended external reference voltage (VREF). The external input reference range is from 2.5V to 5.1V. This reference voltage sets the input full-scale range from 0V to VREF. See Figure 6-2 to Figure 6-8 for example application circuits and reference voltage settings. Note: The reference pin needs a tantalum decoupling capacitor (10 F, 10V rating). Additional multiple ceramic capacitors can be added in parallel to decouple high-frequency noises.  2018 Microchip Technology Inc. DS20005947B-page 29 MCP33131D/MCP33121D/MCP33111D-XX 6.0 DEVICE OVERVIEW When the MCP33131D/MCP33121D/MCP33111D-XX is first powered-up, it performs a self-calibration and enters a low current input acquisition mode (Standby) by itself. The external reference voltage (VREF) ranging from 2.5V to 5.1V sets the differential input full-scale range (FSR) from -VREF to +VREF. MCP331x1D-XX VREF VT = 0.6V D1 AIN+ CPIN D2 The differential input signal needs an appropriate input common-mode voltage from 0V to VREF, depending on the input signal condition. VREF/2 is typically used for a symmetric differential input. During input acquisition (Standby), the internal input sampling capacitors are connected to the input signal, while most of the internal analog circuits are shutdown to save power. During this input acquisition time (tACQ), the device consumes less than 1 A. The user can operate the device with an easy-to-use SPI-compatible 3-wire interface. The device initiates data conversion on the rising edge of the conversion-start control (CNVST). The data conversion time (tCNV) is set by the internal clock. Once the conversion is complete and the host lowers CNVST, the output data is available on SDO and the device starts the next input acquisition by itself. During this input acquisition time (tACQ), the user can clock out the output data by providing the SPI-compatible serial clock (SCLK). The device provides conversion data with no missing codes. This ADC device family has a large input full-scale range, high precision, high throughput with no output latency, and is an ideal choice for various ADC applications. 6.1 Analog Inputs Figure 6-1 shows a simplified equivalent circuit of the differential input architecture with a switched capacitor input stage. The input sampling capacitors (CS+ and CS-) are about 31 pF each. The back-to-back diodes (D1 - D2) at each input are ESD protection diodes. Note that these ESD diodes are tied to VREF, so that each input signal can swing from 0V to +VREF and from -VREF to +VREF differentially. During input acquisition (Standby), the sampling switches are closed and each input sees the sampling capacitor (≈ 31 pF) in series with the on-resistance of the sampling switch, RSON (≈ 200). Sample VIN+ SW1+ RSON CS+ (200 ) (31 pF) SW2+ ILEAKAGE (~ ±1 nA) VREF D1 AIN- VT = 0.6V Sample VINSW1- CPIN RSON (200 ) D2 CS- SW2- (31 pF) ILEAKAGE (~ ±1 nA) where: CS+, CS- = Input sample and hold capacitor ≈ 31 pF. RSON = On-resistance of the sampling switch ≈ 200  CPIN = Package pin + ESD capacitor ≈ 2 pF. FIGURE 6-1: Simplified Equivalent Analog Input Circuit. 6.1.1 ABSOLUTE MAXIMUM INPUT VOLTAGE RANGE The input voltage at each input pin (AIN+ and AIN-) must meet the following absolute maximum input voltage limits: • (VIN+, VIN-) < VREF + 0.1V • (VIN+, VIN-) > GND - 0.1V Note: The ESD diodes at the analog input pins are biased from VREF. Any input voltage outside the absolute maximum range can turn on the input ESD protection diodes and results in input leakage current which may cause conversion errors and permanent damage to the device. Care must be taken in setting the input voltage ranges so that the input voltage does not exceed the absolute maximum input voltage range. For high-precision data conversion applications, the input voltage needs to be fully settled within 1/2 LSB during the input acquisition period (tACQ). The settling time is directly related to the source impedance: A lower impedance source results in faster input settling time. Although the device can be driven directly with a low impedance source, using a low noise input driver is highly recommended. DS20005947B-page 30  2018 Microchip Technology Inc. MCP33131D/MCP33121D/MCP33111D-XX 6.1.2 INPUT VOLTAGE RANGE The differential input (VIN) and common-mode voltage (VCM) at the input pins are defined by: EQUATION 6-1: DIFFERENTIAL INPUT V IN = V IN + – V IN - V + + V IN IN V CM = ---------------------------2 where VIN+ is the input at the AIN+ pin and VIN- is the input at AIN- pin. The input signal swings around an input common-mode voltage (VCM), typically centered at VREF/2 for the best performance. The absolute value of the differential input (VIN) needs to be less than the reference voltage. The device will output saturated output codes (all 0s or all 1s except sign bit) if the absolute value of the input (VIN) is greater than the reference voltage. The differential input full-scale voltage range (FSR) is given by the external reference voltage (VREF) setting: EQUATION 6-2: FSR AND INPUT RANGE Input Full-Scale Range (FSR) = 2V REF Input Range: 6.2 – V REF  V IN   V REF – 1LSB  Analog Input Conditioning Circuits The MCP33131D/MCP33121D/MCP33111D-XX supports various input types, such as: (a) fully-differential inputs, (b) arbitrary waveform inputs and (c) single-ended inputs. 6.2.1 FULLY-DIFFERENTIAL INPUT SIGNALS The MCP33131D/MCP33121D/MCP33111D-XX provides the best linearity performance with fully-differential inputs. Figure 6-2 shows an example of a fully-differential input conditioning circuit with a differential input driver followed by an RC anti-aliasing filter. Figure 6-3 shows its transfer function. The differential input (VIN) between the two differential ADC analog input pins (AIN+, AIN-) swings from -VREF to +VREF centered at the input common-mode voltage (VOCM). The front-end differential driver provides a low output impedance, which provides fast settling of the analog inputs during the acquisition phase and provides isolation between the signal source and the ADC. The RC low-pass anti-aliasing filter band-limits the output noise of the input driver and attenuates the kick-back noise spikes from the ADC during conversion.  2018 Microchip Technology Inc. Figure 6-2 is the reference circuit that is used to collect most of the linearity performance data shown in Table 1-1. The differential input driver shown in Figure 6-2 can be replaced with a low noise dual-channel op-amp. See Section 6.3 “ADC Input Driver Selection” for the driver selection. 6.2.2 ARBITRARY WAVEFORM INPUT SIGNALS The MCP33131D/MCP33121D/MCP33111D-XX can convert input signals with arbitrary waveforms at the inputs AIN+ and AIN-. These inputs can be symmetric, non-symmetric or independent with respect to each other. In the arbitrary input configuration, each ADC analog input is connected to a single ended source ranging from 0V to VREF. In this case, the ADC converts the voltage difference between the two input signals. Figure 6-4 shows the configuration example for the arbitrary input signals. 6.2.3 SINGLE-ENDED INPUT SIGNALS Although the MCP33131D/MCP33121D/MCP33111D-XX is a fully-differential input device, it can also convert single-ended input signals. The most commonly recommended single-ended configurations are: (a) pseudo-differential bipolar configuration and (b) pseudo-differential unipolar configuration. 6.2.3.1 Pseudo-Differential Bipolar Configuration In the pseudo-differential bipolar configuration, one of the ADC analog inputs (typically AIN-) is driven with a fixed DC voltage (typically VREF/2), while the other (AIN+) is connected to a single-ended signal in the range 0V to VREF. In this case, the ADC converts the voltage difference between the single-ended signal and the DC voltage. Figure 6-5 shows the configuration example and Figure 6-6 shows its transfer function. 6.2.3.2 Pseudo-Differential Unipolar Configuration In the pseudo-differential unipolar input configuration, one of the ADC analog inputs (typically AIN-) is connected to ground, while the other (AIN+) is connected to a single ended signal in the range 0V to VREF. In this case, the ADC converts the voltage difference between the single ended signal and ground. Figure 6-7 shows the configuration example and Figure 6-8 shows its transfer function. DS20005947B-page 31 MCP33131D/MCP33121D/MCP33111D-XX Voltage Reference VDC (Note 2) VREF CR 10 F RF1 0V VREF 1.8V to 5.5V VREF Differential Inputs VREF 1.8V RG1 VREF/2 RG2 R1 + (22 ±0.1%) VOCM C1 (1.7nF, NPO) VREF AVDD DVIO AIN+ SDI MCP331x1D-XX CNVST R1 - 0V VREF/2 0V (22 ±0.1%) RF2 Input Driver (Note 1) C1 (1.7nF, NPO) SCLK AINVREF VREF/2 0V GND Host Device (PIC32MZ) SDO fC = 2R1 C 1 1 Note 1: Contact Microchip Technology Inc. for availability of the differential input driver amplifiers. 2: Contact Microchip Technology Inc. for the MCP1501 voltage reference application circuit. FIGURE 6-2: Input Conditional Circuit for Fully-Differential Input. Digital Output Code (Two’s Complement) 2n/2 - 1 -VREF +VREF - 1 LSB 0 VIN Differential Input Voltage - 2n/2 Available VIN range FIGURE 6-3: DS20005947B-page 32 Transfer Function for Figure 6-2.  2018 Microchip Technology Inc. MCP33131D/MCP33121D/MCP33111D-XX VREF Voltage Reference VDC CR (Note 2) 10 F 1.8V 1.8V to 5.5V Arbitrary Waveform Differential Inputs VREF AVDD DVIO AIN+ R1 VREF C1 SDI 0V MCP331x1D-XX CNVST R1 VREF C1 GND fC = 2R1 C (PIC32MZ) SCLK AIN- 0V Host Device SDO 1 1 Low Noise Input Buffer (Note 1) Note 1: Contact Microchip Technology Inc. for availability of the low-noise input driver amplifiers. 2: Contact Microchip Technology Inc. for the MCP1501 voltage reference application circuit. FIGURE 6-4: Input Configuration for Arbitrary Waveform Input Signals. VREF Voltage Reference VDC CR (Note 2) 10 F Low Noise Input Buffer (Note 1) Single-Ended Input VREF VREF/2 0V R1 VREF VREF/2 0V (22 ±0.1%) C1 (1.7nF, NPO) SDI VREF/2 AIN- (22 ±0.1%) C1 (1.7nF, NPO) 1 F 1.8V to 5.5V VREF AVDD DVIO AIN+ MCP331x1D-XX R1 VREF/2 1.8V CNVST Host Device (PIC32MZ) SCLK GND SDO fC = 2R1 C 1 1 Note 1: Contact Microchip Technology Inc. for availability of the low-noise input driver amplifiers. 2: Contact Microchip Technology Inc. for the MCP1501 voltage reference application circuit. FIGURE 6-5: Pseudo-Differential Bipolar-Input Configuration for Single-Ended Input Signal. Digital Output Code (Two’s Complement) n 2 /2 - 1 2n/4 -VREF -VREF/2 0 +VREF/2 +VREF - 1 LSB VIN Analog Input Voltage - 2n/4 Available VIN range - 2n/2 FIGURE 6-6: Transfer Function for Figure 6-5.  2018 Microchip Technology Inc. DS20005947B-page 33 MCP33131D/MCP33121D/MCP33111D-XX VREF Voltage Reference VDC CR (Note 2) Single-Ended Input VREF VREF/2 0V 10 F VREF VREF/2 0V R1 (22 ±0.1%) Low Noise Input Buffer (Note 1) 1.8V 1.8V to 5.5V VREF AVDD DVIO AIN+ C1 (1.7nF, NPO) SDI MCP331x1D-XX CNVST R1 SCLK AIN- (22 ±0.1%) GND C1 (1.7nF, NPO) Host Device (PIC32MZ) SDO Note 1: Contact Microchip Technology Inc. for availability of the low-noise input driver amplifiers. 2: Contact Microchip Technology Inc. for the MCP1501 voltage reference application circuit. FIGURE 6-7: Pseudo-Differential Unipolar-Input Configuration for Single-Ended Input Signal. Digital Output Code (Two’s Complement) 2n/2 - 1 2n/4 -VREF -VREF/2 0 +VREF/2 +VREF VIN Analog Input Voltage Available VIN range - 2n/4 - 2n/2 FIGURE 6-8: DS20005947B-page 34 Transfer Function for Figure 6-7.  2018 Microchip Technology Inc. MCP33131D/MCP33121D/MCP33111D-XX 6.3 ADC Input Driver Selection EQUATION 6-5: The noise and distortion of the ADC input driver can degrade the dynamic performance (SNR, SFDR, and THD) of the overall ADC application system. Therefore, the ADC input driver needs better performance specifications than the ADC itself. The data sheet of the driver typically shows the output noise voltage and harmonic distortion parameters. Figure 6-9 shows a simplified system noise presentation block diagram for the front-end driver and ADC. ADC INPUT-REFERRED NOISE VN_ADC Input-Referred Noise = . = = FSR -----------2 2 10 SNR – ----------20 (V) V REF SNR – ----------20 for differential input V REF SNR – ----------20 for single-ended input -------------- 10 2 -------------- 10 2 2 where FSR is the input full-scale range of ADC. Front-End Driver -+ • Noise Contribution from the Front-End Driver: R -+ ADC C VN_RMS_Driver Noise FIGURE 6-9: Representation. VN_ADC Input-Referred Noise Simplified System Noise • Unity-Gain Bandwidth: An input driver with higher bandwidth usually results in better overall linearity performance. Typically, the driver should have the unity-gain bandwidth greater than 5 times the -3 dB cutoff frequency of the anti-aliasing filter: EQUATION 6-3: BANDWIDTH REQUIREMENT FOR ADC INPUT DRIVER BWInput Driver  5 x f B (Hz) 5  --------------- for a single-pole RC filter 2RC where, fB = -3 dB bandwidth of RC anti-aliasing filter as shown in Figure 6-9. • Distortion: The nonlinearity characteristics of the input driver cause distortions in the ADC output. Therefore, the input driver should have less distortion than the ADC itself. The recommended total harmonic distortion (THD) of the driver is at least 10 dB less than that of the ADC: EQUATION 6-4: THDInput Driver RECOMMENDED THD FOR ADC INPUT DRIVER ≤ THDADC -10 (dB) The noise from the input driver can degrade the ADC’s SNR performance. Therefore, the selected input driver should have the lowest possible broadband noise density and 1/f noise. When an anti-aliasing filter is used after the input driver, the output noise density of the input driver is integrated over the -3 dB bandwidth of the filter. Equation 6-6 shows the RMS output noise voltage calculation using the RC filter’s bandwidth and noise density (eN) of the input driver. GN in Equation 6-6 is the noise gain of the driver amplifier and becomes 1 for a unity gain buffer driver. EQUATION 6-6: VN_RMS_Driver Noise NOISE FROM FRONT-END DRIVER AMPLIFIER  eN G N -------  f B 2 (V) where eN is the broadband noise density (V/√Hz) of the front-end driver amplifier and is typically given in its data sheet. In Equation 6-6, 1/f noise (eNFlicker) is ignored assuming it is very small compared to the broadband noise (eN). For high precision ADC applications, the noise contribution from the front-end input driver amplifier is typically constrained to be less than about 20% (or 1/5 times) of the ADC input-referred noise as shown in Equation 6-7: EQUATION 6-7: RECOMMENDED ADC INPUT DRIVER NOISE VN_RMS_Driver Noise  1--- VN_ADC Input-Referred Noise 5 Using Equation 6-5 to Equation 6-7, the recommended noise voltage density (eN) limit of the ADC input driver is expressed in Equation 6-8: • ADC Input-Referred Noise: When the ADC is operating with a full-scale input range, the ADC input-referred RMS noise is approximated as shown in Equation 6-5.  2018 Microchip Technology Inc. DS20005947B-page 35 MCP33131D/MCP33121D/MCP33111D-XX EQUATION 6-8: eN G N -------  f B 2 NOISE DENSITY FOR ADC INPUT DRIVER 1 1  ------------------- --------------5 GN  fB V REF 10 SNR – ----------20 V   --------- Hz V REF 10 V   --------- Hz Using Equation 6-8, the recommended maximum noise voltage density limit for unity gain input driver for differential input ADC can be estimated. Table 6-1 to Table 6-3 show a few example results with GN = 1. The user may use these tables as a reference when selecting the ADC input driver amplifier. ADC SNR fB Input-Referred (Note 2) (dBFS) Noise 2.5V 3.3V SNR – ----------20 RC Filter (Note 1) VREF (b) eN for single-ended input ADC: 1 1 e N  ---------------------- --------------10 G N  f B Noise Voltage Density (eN) of Input Driver for MCP33121D-XX ADC 1 5  --- VN_ADC Input-Referred Noise (a) eN for differential input ADC: eN TABLE 6-2: 84 139 V 84.5 5V Note 111.5V 198.8 V 85 1: 2: Noise Voltage Density (eN) of Input Driver for MCP33131D-XX TABLE 6-3: ADC (Note 1) VREF ADC SNR fB Input-Referred (Table 2) (dBFS) Noise 2.5V 3.3V 5V Note RC Filter 87 89 92 1: 2: 79.1V 82.8 V 88.8 V ADC Input Driver Amplifier (GN = 1) Noise Voltage Density (eN) 3 MHZ 7.3 nV/√Hz 4 MHz 6.3 nV/√Hz 5 MHZ 5.6 nV/√Hz 3 MHZ 7.6 nV/√Hz 4 MHz 6.6 nV/√Hz 5 MHZ 5.9 nV/√Hz 3 MHZ 8.2 nV/√Hz 4 MHz 7.1 nV/√Hz 5 MHZ 6.3 nV/√Hz 2.5V 3.3V 5V Note ADC SNR Input-Referred (dBFS) Noise 73.8 73.9 74 1: 2: 3 MHZ 10.3 nV/√Hz 4 MHz 8.9 nV/√Hz 5 MHZ 8 nV/√Hz 3 MHZ 12.8 nV/√Hz 4 MHz 11.1 nV/√Hz 5 MHZ 9.9 nV/√Hz 3 MHZ 18.3 nV/√Hz 4 MHz 15.9 nV/√Hz 5 MHZ 14.2 nV/√Hz Noise Voltage Density (eN) of Input Driver for MCP33111D-XX (Note 1) VREF Noise Voltage Density (eN) See Equation 6-5 for the ADC input-referred noise calculation for differential input. fB is -3dB bandwidth of the RC anti-aliasing filter. ADC TABLE 6-1: ADC Input Driver Amplifier (GN = 1) 360.9V 471 V 705.4 V RC Filter ADC Input Driver Amplifier (GN = 1) (Note 2) fB Noise Voltage Density (eN) 3 MHZ 33.3 nV/√Hz 4 MHz 28.8 nV/√Hz 5 MHZ 25.8 nV/√Hz 3 MHZ 43.4 nV/√Hz 4 MHz 37.6 nV/√Hz 5 MHZ 33.6 nV/√Hz 3 MHZ 65 nV/√Hz 4 MHz 56.3 nV/√Hz 5 MHZ 50.3 nV/√Hz See Equation 6-5 for the ADC input-referred noise calculation for differential input. fB is -3dB bandwidth of the RC anti-aliasing filter. See Equation 6-5 for the ADC input-referred noise calculation for differential input. fB is -3dB bandwidth of the RC anti-aliasing filter. DS20005947B-page 36  2018 Microchip Technology Inc. MCP33131D/MCP33121D/MCP33111D-XX 6.4 Device Operation 6.4.2 The start of the conversion is controlled by CNVST. On the rising edge of CNVST, the sampled charge is locked (sample switches are opened) and the ADC performs the conversion. Once a conversion is started, it will not stop until the current conversion is complete. The data conversion time (tCNV) is not user controllable. After the conversion is complete and the host lowers CNVST, the output data is presented on SDO. When the MCP33131D/MCP33121D/MCP33111D-XX is first powered-up, it self-calibrates internal systems and enters input acquisition mode by itself. The device operates in two phases: (a) Input Acquisition (Standby) and (b) Data Conversion. Figure 6-10 shows the ADC operating sequence. 6.4.1 DATA CONVERSION PHASE INPUT ACQUISITION PHASE (STANDBY) Any noise injection during the conversion phase may affect the accuracy of the conversion. To reduce external environment noise, minimize I/O events and running clocks during the conversion time. During the input acquisition phase (tACQ), also called Standby, the two input sampling capacitors, CS+ and CS-, are connected to the AIN+ and AIN- pins, respectively. The input voltage is sampled until a rising edge on CNVST is detected. The input voltage should be fully settled within 1/2 LSB during tACQ. The output data is clocked out MSB first. While the output data is being transferred, the device enters the next input acquisition phase. During this input acquisition time (tACQ), the ADC consumes less than 1 A. The acquisition time (tACQ) is user-controllable. The system designer can increase the acquisition time (tACQ) as long as needed for additional power savings. Note: Transferring output data during the acquisition phase can disturb the next input sample. It is highly recommended to allow at least tQUIET (10 ns, typical) between the last edge on the SPI interface and the rising edge on CNVST. See Figure 1-1 for tQUIET. tCYC = 1/fS Input Acquisition (Standby) Operating Condition IDDAN Data Conversion tACQ MCP331x1D-10: 300 ns (typical) MCP331x1D-05: 800 ns (typical) tCNV MCP331x1D-10: 700 ns (typical) MCP331x1D-05: 1200 ns (typical) Input Acquisition (Standby) tACQ MCP331x1D-10: 300 ns (typical) MCP331x1D-05: 800 ns (typical) (a) ADC acquires input sample #1. (a) Conversion is initiated at the rising edge of CNVST. (a) At the falling edge of CNVST, ADC output is available at SDO. (b) No ADC output is available yet. (b) All circuits are turned-on. (b) ADC output can be clocked out (c) Most analog circuits are (c) ADC output is not available yet. by providing clocks. turned off. (c) ADC acquires input sample #2. MCP331x1D-10: ~1.6 mA (d) Most analog circuits are turned off. MCP331x1D-05: ~1.4 mA I Off ~ 0.8 A (a) Device is first powered-up and (b) Performs a power-up self-calibration. Output Data SDO FIGURE 6-10: Device Operating Sequence.  2018 Microchip Technology Inc. DS20005947B-page 37 MCP33131D/MCP33121D/MCP33111D-XX 6.4.3 SAMPLE (THROUGHPUT) RATE The device completes data conversion within the maximum specification of the data conversion time (tCNV). The continuous input sample rate is the inverse of the sum of input acquisition time (tACQ) and data conversion time (tCNV). Equation 6-9 shows the continuous sample rate calculation using the minimum and maximum specifications of the input acquisition time (tACQ) and data conversion time (tCNV). EQUATION 6-9: the input acquisition time (tACQ). For the continuous sampling rate (fS), the minimum SPI clock frequency requirement is determined by the following equation: EQUATION 6-10: SPI CLOCK FREQUENCY REQUIREMENT t ACQ = N  T SCLK + t QUIET + t EN 1 N f SCLK = --------------- = -----------------------------------------------------T SCLK t ACQ –  t QUIET + t EN  where N is the number of output data bits, given by SAMPLE RATE N = 16-bit for MCP33131D-XX = 14-bit for MCP33121D-XX = 12-bit for MCP33111D-XX 1 Sample Rate = --------------------------------- t ACQ + t CNV  (a) MCP331x1D-10: 1 Sample Rate = ----------------------------------------- = 1 Msps  290ns + 710ns  (b) MCP331x1D-05: 1 Sample Rate = -------------------------------------------- = 500 kSPS  700ns + 1300ns  6.4.4 SERIAL SPI CLOCK FREQUENCY REQUIREMENT The ADC output is collected during the input acquisition time (tACQ). For continuous input sampling and data conversion sequence, the SPI clock frequency should be fast enough to clock out all output data bits during TABLE 6-4: Input Acquisition Time: tACQ (nS) Note: See Figure 1-1 for interface timing diagram. where fSCLK is the minimum SPI serial clock frequency required to transfer all N-bits of the output data during input acquisition time (tACQ). Table 6-4 and Table 6-5 show the examples of calculated minimum SPI clock (fSCLK) requirements for various input acquisition times for 1 Msps and 500 kSPS family devices, respectively. SPI CLOCK SPEED VS. INPUT ACQUISITION TIME (TACQ) FOR MCP331X1D-10 SPI Clock (fSCLK) Speed Requirement Data Conversion Time (nS) (Note 1), (Note 2) Sample Rate: fS (Msps) MCP33131D-10 (16-bit) MCP33121D-10 (14-bit) MCP33111D-10 (12-bit) 250 69.57 MHz 60.87 MHz 52.17 MHz 1 270 64 MHz 56 MHz 48 MHz 0.98 0.97 750 280 61.54 MHz 53.85 MHz 46.15 MHz 290 59.26 MHz 51.85 MHz 44.44 MHz 1 300 57.15 MHz 50 MHz 42.86 MHz 0.99 320 53.33 MHz 46.67 MHz 40 MHz 0.97 400 42.11 MHz 36.84 MHz 30 MHz 0.9 540 30.77 MHz 26.92 MHz 23.08 MHz 0.8 22.86 MHz 20 MHz 17.14 MHz 0.7 720 17.2 MHz 15.05MHz 12.9 MHz 0.6 1290 12.6 MHz 11.02 MHz 9.45 MHz 0.5 1750 9.04 MHz 7.91 MHz 6.78 MHz 0.4 2620 6.15 MHz 5.39 MHz 4.62 MHz 0.3 4290 3.75 MHz 3.28 MHz 2.81 MHz 0.2 9290 1.73 MHz 1.51 MHz 1.3 MHz 0.1 710 720 Note TSCLK = Period of SPI clock N x TSCLK = Output data window tQUIET = Quiet time between the last output bit and beginning of the next conversion start. = 10 ns (min) tEN = Output enable time = 10 ns (max), with DVIO  2.3V 1: 2: 3: Conditions 85°C < TA ≤ 125°C (Note 3) -40°C ≤ TA ≤ 85°C This is the minimum SPI clock speed requirement to collect all N-bits of the ADC output during the input acquisition time (tACQ), when the ADC is operating in continuous input sampling mode. See Equation 6-10 for the calculation of the SPI clock speed requirement. In extended temperature range, the device takes longer data conversion time (tCNV: 750 nS, max). Using a shorter input acquisition time is recommended (tACQ: 250 nS) for 1 Msps throughput rate. DS20005947B-page 38  2018 Microchip Technology Inc. MCP33131D/MCP33121D/MCP33111D-XX TABLE 6-5: SPI CLOCK SPEED VS. INPUT ACQUISITION TIME (TACQ) FOR MCP331X1D-05 SPI Clock (fSCLK) Speed Requirement Input Acquisition Time: tACQ (nS) Data Conversion Time (nS) MCP33131D-05 (16-bit) MCP33121D-05 (14-bit) MCP33111D-05 (12-bit) Sample Rate: fS (kSPS) 700 23.53MHz 20.59 MHz 17.65 MHz 500 740 22.22 MHz 19.44 MHz 16.67 MHz 490 790 20.78 MHz 18.18 MHz 15.58 MHz 480 17.58 MHz 15.39 MHz 13.19 MHz 450 13.56 MHz 11.86 MHz 10.17 MHz 400 1560 10.39 MHz 9.09 MHz 7.79 MHz 350 2030 7.96 MHz 6.97 MHz 5.97 MHz 300 2700 5.97 MHz 5.22MHz 4.48 MHz 250 3700 4.35 MHz 3.8 MHz 3.26 MHz 200 5370 2.99 MHz 2.62 MHz 2.25 MHz 150 8700 1.84 MHz 1.61 MHz 1.38 MHz 100 930 1300 1200 Note (Note 1), (Note 2) 1: 2: 6.5 Conditions -40°C ≤ TA ≤ 125°C This is the minimum SPI clock speed requirement to collect all N-bits of the ADC output during the input acquisition time (tACQ), when the ADC is operating in continuous input sampling mode. See Equation 6-10 for the calculation of the SPI clock speed requirement. Transfer Function Digital Output Code (Two’s Complement) The differential analog input is 011 ...111 VIN = (VIN+) - (VIN-). 011 ...110 The LSB size is given by Equation 6-11. and an example of LSB size vs. reference voltage is summarized in Table 6-6. EQUATION 6-11: LSB SIZE - EXAMPLE 000 ...000 2V REF LSB = --------------N 2 where N is the resolution of the ADC in bits. TABLE 6-6: LSB SIZE VS. REFERENCE LSB Size Reference Voltage MCP33131D-XX MCP33121D-XX MCP33111D-XX (VREF) (16-bit) (14-bit) (12-bit) 2.5V 76.3 V 305.2 V 1.2207 mV 2.7V 82.4 V 329.6 V 1.3184 mV 1.4648 mV 3V 91.6 V 366.2 V 3.3V 100.7 V 402.8 V 1.6113 mV 3.5V 106.8 V 427.3 V 1.7090 mV 4V 122.1 V 488.3 V 1.9531 mV 4.5V 137.3 V 549.3 V 2.1973 mV 5V 152.6 V 610.4 V 2.4414 mV 5.1V 155.6 V 622.6 V 2.4902 mV 100 ...001 100 ...000 0V -VREF + 1 LSB -VREF + 0.5 LSB -VREF +VREF - 1.5 LSB +VREF - 1 LSB Differential Analog Input Voltage FIGURE 6-11: Ideal Transfer Function for Fully-Differential Input Signal. Figure 6-11 shows the ideal transfer function and Table 6-7 shows the digital output codes for the MCP33131D/MCP33121D/MCP33111D-XX.  2018 Microchip Technology Inc. DS20005947B-page 39 MCP33131D/MCP33121D/MCP33111D-XX 6.6 Digital Output Code The digital output code is proportional to the input voltage. The output data is in binary two’s complement format. With this coding scheme the MSB can be considered a sign indicator. When the MSB is a logic ‘0’, the input is positive. When the MSB is a logic ‘1’, the input is negative. The following is an example of the output code: (a) for a negative full-scale input: Analog Input: (VIN+) - (VIN-) = -VREF Output Code: 1000...0000 (b) for a zero differential input: Analog Input: (VIN+) - (VIN-) = 0V Output Code: 0000...0000 (c) for a positive full-scale input: Analog Input: (VIN+) - (VIN-) = +VREF Output Code: 0111...1111 The MSB (sign bit) is always transmitted first through the SDO pin. The code will be locked at 0111...11 for all voltages greater than (VREF - 1 LSB) and 1000...00 for voltages less than -VREF. Table 6-7 shows an example of output codes of various input levels. TABLE 6-7: DIGITAL OUTPUT CODE Input Voltage (V) Digital Output Codes MCP33131D-XX (16-bit) MCP33121D-XX (14-bit) MCP33111D-XX (12-bit) VREF 0111-1111-1111-1111 01-1111-1111-1111 0111-1111-1111 VREF - 1 LSB 0111-1111-1111-1111 01-1111-1111-1111 0111-1111-1111 . . . . . . . . 2 LSB 0000-0000-0000-0010 00-0000-0000-0010 0000-0000-0010 1 LSB 0000-0000-0000-0001 00-0000-0000-0001 0000-0000-0001 0V 0000-0000-0000-0000 00-0000-0000-0000 0000-0000-0000 -1 LSB 1111-1111-1111-1111 11-1111-1111-1111 1111-1111-1111 -2 LSB 1111-1111-1111-1110 11-1111-1111-1110 1111-1111-1110 . . . . . . . . - VREF 1000-0000-0000-0000 10-0000-0000-0000 1000-0000-0000 < -VREF 1000-0000-0000-0000 10-0000-0000-0000 1000-0000-0000 DS20005947B-page 40  2018 Microchip Technology Inc. MCP33131D/MCP33121D/MCP33111D-XX 7.0 DIGITAL SERIAL INTERFACE SDO returns to high-Z state after the last data bit is clocked out or when CNVST goes high, whichever occurs first. The device has a SPI-compatible serial digital interface using four digital pins: CNVST, SDI, SDO and SCLK. Figure 7-1 shows the connection diagram with the host device and Figure 7-2 shows the SPI-compatible serial interface timing diagram. CS DVIO DVIO The SDI pin can be tied to the digital I/O interface supply voltage (DVIO) or just maintain logic “High” level by the host. The CNVST pin is used for both chip select (CS) and conversion-start control. CNVST SDI SDO SCLK A rising edge on CNVST initiates the conversion process. Once the conversion is initiated, the device will complete the conversion regardless of the state of CNVST. This means the CNVST pin can be used for other purposes during tCNV. SDI 10 k (Note 1) SCLK (b) Host Device (Master) (a) MCP33131D/21D/11D-XX Note 1: Adding this pull-up is needed when monitoring status of Recalibrate. When the conversion is complete, the output is available at SDO by lowering CNVST. Data is sent MSB-first and changes on the falling edge of SCLK. FIGURE 7-1: Diagram. Output data can be sampled on either edge of SCLK. However, a digital host capturing data on the falling edge of SCLK can achieve a faster read out rate. Digital Interface Connection tCYC = 1/fS SDI = DVIO (Note 1) tCNVH (a) Exit input acquisition mode and (b) Enter new conversion mode tSU_SDIH_CNV CNVST tSCLK (Note 2) 1 SCLK 2 (Note 5) 3 4 tDO 14 tSCLK_L 15 tSCLK_H 16 tQUIET tDIS Hi-Z SDO tCNV (MAX) D14 D13 D12 D2 D1 D0 Hi-Z tEN (Note 3) tEN (Note 4) ADC State Input Acquisition (tACQ) D15 (MSB) Conversion (tCNV) Input Acquisition (tACQ) Note 1: SDI must maintain “High” during the entire tCYC. 2: Any SCLK toggling events (dummy clocks) before CNVST is changed to “Low” are ignored. 3: tEN when CNVST is lowered after tCNV (Max). 4: tEN when CNVST is lowered before tCNV (Max). 5: Recommended data detection: Detect SDO on the falling edge of SCLK. FIGURE 7-2: SPITMCompatible Serial Interface Timing Diagram (16-bit device).  2018 Microchip Technology Inc. DS20005947B-page 41 MCP33131D/MCP33121D/MCP33111D-XX 7.1 Recalibrate Command A self-calibration is initiated by sending the recalibrate command. The host device sends a recalibrate command by transmitting 1024 SCLK pulses (including the clocks for data bits) while the device is in the acquisition phase (Standby). The user may use the recalibrate command in the following cases: • When the reference voltage was not fully settled during the first-power sequence. • During operation, to ensure optimum performance across varying environment conditions, such as reference voltage and temperature. The device drives SDO low during the recalibration procedure, and returns to high-Z once completed. The status of the recalibration procedure can be monitored by placing a pull-up on SDO, so that SDO goes high when the recalibration is complete. Figure 7-3 shows the recalibrate command timing diagram. The calibration takes approximately 500 ms (tCAL). (Note 1) SDI = DVIO Start recalibration Complete data reading Finish recalibration Device Recalibration CNVST 1024 clocks (SPITM Recalibrate command) 1 2 3 1024 15 16 SCLK tCAL (Note 2) “High” with Pull-up SDO “High” with Pull-up “Low” ADC Output Data Stream Hi-Z Hi-Z Hi-Z (Note 3) ADC State (Note 4) tCNV Note 1: SDI must remain “High” during the entire recalibration cycle. 2: The 1024 clocks include the clocks for data bits. 3: SDO outputs “Low” during calibration, and Hi-Z when exiting the calibration. 4: After finishing the recalibration procedure, the device is ready for a new input sampling immediately. FIGURE 7-3: Note: Recalibrate Command Timing Diagram. When the device performs a self-calibration, it is important to note that both AVDD and the reference voltage (VREF) must be stabilized for a correct calibration. This is also true when the device is first powered-up, the reference voltage (VREF) must be stabilized before self-calibration begins. This means the VREF must be provided prior to supplying AVDD or within about 64 ms after supplying AVDD. DS20005947B-page 42  2018 Microchip Technology Inc. MCP33131D/MCP33121D/MCP33111D-XX 8.0 DEVELOPMENT SUPPORT 8.1 Device Evaluation Board Microchip offers a high speed/high precision SAR ADC evaluation platform which can be used to evaluate Microchip’s latest high speed/high resolution SAR ADC products. The platform consists of an MCP331x1D-XX evaluation board, a data capture board (PIC32MZ EF Curiosity Board), and a PC-based Graphical User Interface (GUI) software. Figure 8-1 and Figure 8-2 show this evaluation tool. This evaluation platform allows users to quickly evaluate the ADC's performance for their specific application requirements. Note: Contact Microchip Technology Inc. for the PIC32 MCU firmware and the MCP331x1D-XX Evaluation Kit. (a) MCP331x1D-XX Evaluation Board (b) PIC32 MZ EF Curiosity Board FIGURE 8-1: MCP331x1D-XX Evaluation Kit. FIGURE 8-2: PC-Based Graphical User Interface Software.  2018 Microchip Technology Inc. DS20005947B-page 43 MCP33131D/MCP33121D/MCP33111D-XX 8.2 PCB Layout Guidelines: ers are recommended: (a) Top Layer: Most of the noise-sensitive analog components are populated on the top layer. Use all unused surface area as ground planes: analog ground plane in analog circuit section and digital ground in digital circuit section. These ground planes need to be tied to the corresponding ground planes in the second and bottom layers using multiple vias. Microchip provides the schematics and PCB layout of the MCP331x1D-XX Evaluation Board. It is strongly recommended that the user references the example circuits and PCB layouts. A good schematic with low noise PCB layout is critical for high performing ADC application system designs. A few guidelines are listed below: • Use low noise supplies (AVDD, DVIO, and VREF). • All supply voltage pins, including reference voltage, need decoupling capacitors. Decoupling capacitor requirements for each supply pin are shown in Table 5-1. • Use NPO or COG type capacitor for the RC antialiasing filters in the analog input network. • Keep the analog circuit section (analog input driver amplifiers, filters, voltage reference, ADC, etc.) with an analog ground plane, and the digital circuit section (MCU, digital I/O interface) with a digital ground plane. Keep these sections as much apart as possible. This will minimize any digital switching noise coupling into the analog section. • Connect the analog and digital ground planes at a single point (away from the sensitive analog sections) with a 0 resistor or with a ferrite bead. See Figure 8-3 as an example of separated ground planes. • Keep the clock and digital output data lines short and away from the sensitive analog sections as much as possible. • PCB material and Layers: Low loss FR-4 material is most commonly used. The following 4 lay- (b) 2nd Layer: Use this layer as the ground plane: Analog ground plane under the analog circuit section of the top layer and digital ground plane under the digital circuit section on the top layer. Each ground plane is tied to its corresponding ground plane of top and bottom layers using multiple vias. (c) 3rd Layer: This layer is used to distribute various power supplies of the circuits. Use separate trace paths for the power supplies of analog and digital sections. Do not use the same power supply source for both analog and digital circuits. (d) Bottom Layer: This layer is mostly used as a solid ground plane: Analog ground plane under the analog circuit section of the top layer and digital ground plane under the digital circuit section on the top layer. Each ground plane is tied to its corresponding ground plane of all layers using multiple vias. Figure 8-3 and Figure 8-4 show brief examples of the PCB layout. See more details of the schematics and PCB layout in the MCP331x1D-XX Evaluation Board User’s Guide. Analog Ground Plane (GND) MCP331x1D-XX SCLK Analog Ground Plane (GND) SDO R56 Note: Analog and digital ground planes are connected via R56. Digital Interface Connectors for MCU Digital Ground Plane (DGND) FIGURE 8-3: DS20005947B-page 44 (DGND) Digital Ground Plane PCB Layout Example: Analog and Digital Ground Planes  2018 Microchip Technology Inc. C7 C9 C59 C6 C10 MCP33131D/MCP33121D/MCP33111D-XX AVDD VREF AIN+ AIN- VIO SDI SCLK SDO GND MCP331x1D-XX CNVST (a) PCB layout example VREF VIN+ R3 22R C7 C35 1.7nF (NPO) MCP331x1D-XX R8 VIN- 22R 100pF C6 10uF (Tantalum) C37 1.7nF (NPO) 33R 33R 33R R24 = 0  for Single-Ended Configuration CNVST SDI SCLK SDO 33R (b) Schematic example from the MCP331x1D-XX Evaluation Board FIGURE 8-4: PCB Layout Example: See more details in the MCP331x1D-XX EV Kit User’s Guide.  2018 Microchip Technology Inc. DS20005947B-page 45 MCP33131D/MCP33121D/MCP33111D-XX NOTES: DS20005947B-page 46  2018 Microchip Technology Inc. MCP33131D/MCP33121D/MCP33111D-XX 9.0 TERMINOLOGY Analog Input Bandwidth (Full-Power Bandwidth) The analog input frequency at which the spectral power of the fundamental frequency (as determined by FFT analysis) is reduced by 3 dB. Aperture Delay or Sampling Delay This is the time delay between the rising edge of the CNVST input and when the input signal is held for a conversion. Differential Nonlinearity (DNL, No Missing Codes) An ideal ADC exhibits code transitions that are exactly 1 LSB apart. DNL is the deviation from this ideal value. No missing codes to 16-bit resolution indicates that all 65,536 codes (16,384 codes for 14-bit, 4096 codes for 12-bit) must be present over all the operating conditions. EQUATION 9-2:  PS  SINAD = 10 log  ----------------------  P D + P N = – 10 log 10 – SNR ----------10 – 10 – THD -----------10 SINAD is either given in units of dBc (dB to carrier), when the absolute power of the fundamental is used as the reference, or dBFS (dB to full-scale), when the power of the fundamental is extrapolated to the converter full-scale range. Effective Number of Bits (ENOB) The effective number of bits for a sine wave input at a given input frequency can be calculated directly from its measured SINAD using the following formula: EQUATION 9-3: – 1.76 ENOB = SINAD ---------------------------------6.02 Integral Nonlinearity (INL) Gain Error INL is the maximum deviation of each individual code from an ideal straight line drawn from negative full scale through positive full scale. Gain error is the deviation of the ADC’s actual input full-scale range from its ideal value. The gain error is given as a percentage of the ideal input full-scale range. Gain error is usually expressed in LSB or as a percentage of full-scale range (%FSR). Signal-to-Noise Ratio (SNR) SNR is the ratio of the power of the fundamental (PS) to the noise floor power (PN), below the Nyquist frequency and excluding the power at DC and the first nine harmonics. EQUATION 9-1:  PS  SNR = 10 log  -------  P N SNR is either given in units of dBc (dB to carrier), when the absolute power of the fundamental is used as the reference, or dBFS (dB to full-scale), when the power of the fundamental is extrapolated to the converter full-scale range. Signal-to-Noise and Distortion (SINAD) SINAD is the ratio of the power of the fundamental (PS) to the power of all the other spectral components including noise (PN) and distortion (PD) below the Nyquist frequency, but excluding DC:  2018 Microchip Technology Inc. Offset Error The major carry transition should occur for an analog value of ½ LSB below AIN+ = AIN−. Offset error is defined as the deviation of the actual transition from that point. Temperature Drift The temperature drift for offset error and gain error specifies the maximum change from the initial (+25°C) value to the value at across the TMIN to TMAX range. The value is normalized by the reference voltage and expressed in V/oC or ppm/oC. Maximum Conversion Rate The maximum clock rate at which parametric testing is performed. Spurious-Free Dynamic Range (SFDR) SFDR is the ratio of the power of the fundamental to the highest other spectral component (either spur or harmonic). SFDR is typically given in units of dBc (dB to carrier) or dBFS. DS20005947B-page 47 MCP33131D/MCP33121D/MCP33111D-XX Total Harmonic Distortion (THD) THD is the ratio of the power of the fundamental (PS) to the summed power of the first 13 harmonics (PD). EQUATION 9-4:  PS  THD = 10 log  --------  P D THD is typically given in units of dBc (dB to carrier). THD is also shown by: EQUATION 9-5: 2 2 2 2 V2 + V3 + V4 +  + Vn THD = – 20 log -----------------------------------------------------------------2 V1 Where: V1 = RMS amplitude of the fundamental frequency V1 through Vn = Amplitudes of the second through nth harmonics Common-Mode Rejection Ratio (CMRR) Common-mode rejection is the ability of a device to reject a signal that is common to both sides of a differential input pair. The common-mode signal can be an AC or DC signal or a combination of the two. CMRR is measured using the ratio of the differential signal gain to the common-mode signal gain and expressed in dB with the following equation: EQUATION 9-6: Where:  A DIFF CMRR = 20 log  ------------------  A CM  ADIFF = Output Code/Differential Voltage ADIFF = Output Code/Common-Mode Voltage DS20005947B-page 48  2018 Microchip Technology Inc. MCP33131D/MCP33121D/MCP33111D-XX 10.0 PACKAGING INFORMATION 10.1 Package Marking Information Example 10-Lead MSOP (3x3 mm) Corresponding Part Number: 31D-10 = MCP33131D-10 31D-05 = MCP33131D-05 21D-10 = MCP33121D-10 31D-10 839256 21D-05 = MCP33121D-05 11D-10 = MCP33111D-10 11D-05 = MCP33111D-05 10-Lead TDFN (3x3x0.9 mm) Example Corresponding Part Number: XXXX YYWW NNN PIN 1 31D0 = MCP33131D-05 21D1 = MCP33121D-10 31D1 1839 256 21D0 = MCP33121D-05 11D1 = MCP33111D-10 11D0 = MCP33111D-05 PIN 1 Legend: XX...X Y YY WW NNN e3 * Note: 31D1 = MCP33131D-10 Customer-specific information Year code (last digit of calendar year) Year code (last 2 digits of calendar year) Week code (week of January 1 is week ‘01’) Alphanumeric traceability code Pb-free JEDEC® designator for Matte Tin (Sn) This package is Pb-free. The Pb-free JEDEC designator ( e3 ) can be found on the outer packaging for this package. In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information.  2018 Microchip Technology Inc. DS20005947B-page 49 MCP33131D/MCP33121D/MCP33111D-XX 10-Lead Plastic Micro Small Outline Package (MS) [MSOP] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging 0.20 H D D 2 A N E 2 E1 2 E1 E 0.20 H 1 0.25 C 2 e B 8X b 0.13 C A B TOP VIEW H C SEATING PLANE A2 A 8X A1 0.10 C SEE DETAIL A SIDE VIEW END VIEW Microchip Technology Drawing C04-021D Sheet 1 of 2 DS20005947B-page 50  2018 Microchip Technology Inc. MCP33131D/MCP33121D/MCP33111D-XX 10-Lead Plastic Micro Small Outline Package (MS) [MSOP] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging 4X Ĭ1 c C SEATING PLANE L Ĭ (L1) 4X Ĭ1 DETAIL A Units Dimension Limits Number of Pins N e Pitch Overall Height A Molded Package Thickness A2 Standoff A1 Overall Width E Molded Package Width E1 Overall Length D Foot Length L Footprint L1 Mold Draft Angle Ĭ Foot Angle Ĭ1 c Lead Thickness b Lead Width MIN 0.75 0.00 0.40 0° 5° 0.08 0.15 MILLIMETERS NOM 10 0.50 BSC 0.85 4.90 BSC 3.00 BSC 3.00 BSC 0.60 0.95 REF - MAX 1.10 0.95 0.15 0.80 8° 15° 0.23 0.33 Notes: 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.15mm per side. 3. Dimensioning and tolerancing per ASME Y14.5M. BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only. Microchip Technology Drawing C04-021D Sheet 2 of 2  2018 Microchip Technology Inc. DS20005947B-page 51 MCP33131D/MCP33121D/MCP33111D-XX 10-Lead Plastic Micro Small Outline Package (MS) [MSOP] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging G SILK SCREEN Z C G1 Y1 X1 E RECOMMENDED LAND PATTERN Units Dimension Limits E Contact Pitch Contact Pad Spacing C Overall Width Z Contact Pad Width (X10) X1 Contact Pad Length (X10) Y1 Distance Between Pads (X5) G1 Distance Between Pads (X8) G MIN MILLIMETERS NOM 0.50 BSC 4.40 MAX 5.80 0.30 1.40 3.00 0.20 Notes: 1. Dimensioning and tolerancing per ASME Y14.5M BSC: Basic Dimension. Theoretically exact value shown without tolerances. Microchip Technology Drawing No. C04-2021B DS20005947B-page 52  2018 Microchip Technology Inc. MCP33131D/MCP33121D/MCP33111D-XX Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2018 Microchip Technology Inc. DS20005947B-page 53 MCP33131D/MCP33121D/MCP33111D-XX Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS20005947B-page 54  2018 Microchip Technology Inc. MCP33131D/MCP33121D/MCP33111D-XX APPENDIX A: REVISION HISTORY Revision B (November 2018) • Added TDFN-10 package release • Added AEC-Q100 qualification • Added 500 kSPS family devices (MCP33131D/ MCP33121D/MCP33111D-05) • Minor typographical corrections Revision A (March 2018) • Original release of this document  2018 Microchip Technology Inc. DS20005947B-page 55 MCP33131D/MCP33121D/MCP33111D-XX NOTES:  2018 Microchip Technology Inc. DS20005947B-page 56 MCP33131D/MCP33121D/MCP33111D-XX PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. ─XX PART NO. X Device Input Type Device: X Sample Rate Tape and Reel ─X /XX Temperature Package Range Examples: a) MCP33131D-10-I/MS: b) MCP33131D-10T-I/MS: 1 Msps, 10LD MSOP, Tape and Reel, 16-bit device c) MCP33131D-10-I/MN: 1 Msps, 10LD TDFN, 16-bit device d) MCP33131D-10T-I/MN: 1 Msps, 10LD TDFN, Tape and Reel, 16-bit device e) MCP33121D-10-I/MS: f) MCP33121D-10T-I/MS: 1 Msps, 10LD MSOP, Tape and Reel, 14-bit device g) MCP33121D-10-I/MN: MCP33131D-10: 1 Msps 16-Bit Differential Input SAR ADC MCP33121D-10: 1 Msps 14-Bit Differential Input SAR ADC MCP33111D-10: 1 Msps 12-Bit Differential Input SAR ADC MCP33131D-05: 500 kSPS 16-Bit Differential Input SAR ADC MCP33121D-05: 500 kSPS 14-Bit Differential Input SAR ADC MCP33111D-05: Input Type 500 kSPS 12-Bit Differential Input SAR ADC D: Differential Input 1 Msps, 10LD MSOP, 16-bit device 1 Msps, 10LD MSOP, 14-bit device 1 Msps, 10LD TDFN, 14-bit device Sample Rate: 10 05 = 1 Msps = 500 kSPS h) MCP33121D-10T-I/MN: 1 Msps, 10LD TDFN, Tape and Reel, 14-bit device Tape and Reel Option: Blank T = Standard packaging (tube or tray) = Tape and Reel i) MCP33111D-10-I/MS: j) MCP33111D-10T-I/MS: 1 Msps, 10LD MSOP, Tape and Reel, 12-bit device k) MCP33111D-10-I/MN: l) MCP33111D-10T-I/MN: 1 Msps, 10LD TDFN, Tape and Reel, 12-bit device m) MCP33131D-05-I/MS: n) MCP33131D-05T-I/MS: 500 kSPS, 10LD MSOP, Tape and Reel, 16-bit device o) MCP33131D-05-I/MN: p) MCP33131D-05T-I/MN: 500 kSPS, 10LD TDFN, Tape and Reel, 16-bit device q) MCP33121D-05-I/MS: r) MCP33121D-05T-I/MS: 500 kSPS, 10LD MSOP, Tape and Reel, 14-bit device s) MCP33121D-05-I/MN: t) MCP33121D-05T-I/MN: 500 kSPS, 10LD TDFN, Tape and Reel, 14-bit device u) MCP33111D-10-I/MS: v) MCP33111D-10T-I/MS: 500 kSPS, 10LD MSOP, Tape and Reel, 12-bit device w) MCP33111D-10-I/MN: x) MCP33111D-10T-I/MN: 500 kSPS, 10LD TDFN, Tape and Reel, 12-bit device Temperature Range: E I = -40C to +125C (Extended) = -40C to +85C (Industrial) Package: MS MN = = Note: Plastic Micro Small Outline Package (MSOP), 10-Lead Thin Plastic Dual Flat No Lead Package (TDFN), 10-Lead Tape and Reel identifier appears only in the catalog part number description. This identifier is used for ordering purposes and is not printed on the device package. Check with your Microchip Sales Office for package availability with the Tape and Reel option. DS20005947B-page 57 1 Msps, 10LD MSOP, 12-bit device 1 Msps, 10LD TDFN, 12-bit device 500 kSPS, 10LD MSOP, 16-bit device 500 kSPS, 10LD TDFN, 16-bit device 500 kSPS, 10LD MSOP, 14-bit device 500 kSPS, 10LD TDFN, 14-bit device 500 kSPS, 10LD MSOP, 12-bit device 500 kSPS, 10LD TDFN, 12-bit device  2018 Microchip Technology Inc. Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. • Microchip is willing to work with the customer who is concerned about the integrity of their code. • Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer’s risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights unless otherwise stated. Microchip received ISO/TS-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company’s quality system processes and procedures are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified. QUALITY MANAGEMENT SYSTEM CERTIFIED BY DNV == ISO/TS 16949 ==  2018 Microchip Technology Inc. Trademarks The Microchip name and logo, the Microchip logo, AnyRate, AVR, AVR logo, AVR Freaks, BitCloud, chipKIT, chipKIT logo, CryptoMemory, CryptoRF, dsPIC, FlashFlex, flexPWR, Heldo, JukeBlox, KeeLoq, Kleer, LANCheck, LINK MD, maXStylus, maXTouch, MediaLB, megaAVR, MOST, MOST logo, MPLAB, OptoLyzer, PIC, picoPower, PICSTART, PIC32 logo, Prochip Designer, QTouch, SAM-BA, SpyNIC, SST, SST Logo, SuperFlash, tinyAVR, UNI/O, and XMEGA are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. ClockWorks, The Embedded Control Solutions Company, EtherSynch, Hyper Speed Control, HyperLight Load, IntelliMOS, mTouch, Precision Edge, and Quiet-Wire are registered trademarks of Microchip Technology Incorporated in the U.S.A. Adjacent Key Suppression, AKS, Analog-for-the-Digital Age, Any Capacitor, AnyIn, AnyOut, BodyCom, CodeGuard, CryptoAuthentication, CryptoAutomotive, CryptoCompanion, CryptoController, dsPICDEM, dsPICDEM.net, Dynamic Average Matching, DAM, ECAN, EtherGREEN, In-Circuit Serial Programming, ICSP, INICnet, Inter-Chip Connectivity, JitterBlocker, KleerNet, KleerNet logo, memBrain, Mindi, MiWi, motorBench, MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach, Omniscient Code Generation, PICDEM, PICDEM.net, PICkit, PICtail, PowerSmart, PureSilicon, QMatrix, REAL ICE, Ripple Blocker, SAM-ICE, Serial Quad I/O, SMART-I.S., SQI, SuperSwitcher, SuperSwitcher II, Total Endurance, TSHARC, USBCheck, VariSense, ViewSpan, WiperLock, Wireless DNA, and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. Silicon Storage Technology is a registered trademark of Microchip Technology Inc. in other countries. GestIC is a registered trademark of Microchip Technology Germany II GmbH & Co. KG, a subsidiary of Microchip Technology Inc., in other countries. All other trademarks mentioned herein are property of their respective companies. © 2018, Microchip Technology Incorporated, All Rights Reserved. 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