MCP3462T-E/ST

MCP3461/2/4 Two/Four/Eight-Channel, 153.6 ksps, Low Noise, 16-Bit Delta-Sigma ADC Features General Description • One/Two/Four Differential or Two/Four/Eight Single-Ended Input Channels • 16-Bit Resolution • Programmable Data Rate: Up to 153.6 ksps • Programmable Gain: 0.33x to 64x • 97.2 dB SINAD, -116 dBc THD, 120 dBc SFDR (Gain = 1x, 4800 SPS) • Low-Temperature Drift: - Offset error drift: 4/Gain nV/°C (AZ_MUX = 1) - Gain error drift: 0.5 ppm/°C (Gain = 1x) • Low Noise: 3.2 µVRMS (Gain = 16x, 9600 SPS) • RMS Effective Resolution: 15.5 Bits Minimum (All gains, all OSR combinations) • Wide Input Voltage Range: 0V to AVDD • Differential Voltage Reference Inputs • Internal Oscillator or External Clock Selection • Ultra-Low Full Shutdown Current Consumption (< 5 µA) • Internal Temperature Sensor • Burnout Current Sources for Sensor Open/Short Detection • 16-Bit Digital Offset and Gain Error Calibration Registers • Internal Conversions Sequencer (SCAN Mode) for Automatic Multiplexing • Dedicated IRQ Pin for Easy Synchronization • Advanced Security Features: - 16-bit CRC for secure SPI communications - 16-bit CRC and IRQ for securing configuration - Register map lock with 8-bit secure key - Monitor controls for system diagnostics • 20 MHz SPI-Compatible Interface with Mode 0,0 and 1,1 • AVDD: 2.7V-3.6V • DVDD: 1.8V-3.6V • Extended Temperature Range: -40°C to +125°C • Package: 3 mm x 3 mm 20-Lead UQFN and 6.5 mm x 4.4 mm x 1 mm 20-Lead TSSOP The MCP3461/2/4 devices are 1/2/4-channel, 16-bit Delta-Sigma Analog-to-Digital Converters (ADCs) with programmable data rate of up to 153.6 ksps. They offer integrated features, such as internal oscillator, temperature sensor and burnout sensor detection, in order to reduce system component count and total solution cost.  2019-2021 Microchip Technology Inc. The MCP3461/2/4 ADCs are fully configurable with Oversampling Ratio (OSR) from 32 to 98304 and gain from 1/3x to 64x. These devices include an internal sequencer (SCAN mode) with multiple monitor channels and a 24-bit timer to be able to automatically create conversion loop sequences without needing MCU communications. Advanced security features, such as CRC and register map lock, can ensure configuration locking and integrity, as well as communication data integrity for secure environments. These devices come with a 20 MHz SPI-compatible serial interface. Communication is largely simplified with 8-bit commands, including various continuous Read/Write modes and 16/32-bit multiple data formats that can be accessed by the Direct Memory Access (DMA) of an 8-bit, 16-bit or 32-bit MCU. The MCP3461/2/4 devices are available in a leaded 20-lead TSSOP package, as well as in an ultra-small 3 mm x 3 mm 20-lead UQFN package and are specified over an extended temperature range, from -40°C to +125°C. Applications • Precision Sensor Transducers and Transmitters: Pressure, Strain, Flow and Force Measurement • Factory Automation and Process Controls • Portable Instrumentation • Temperature Measurements DS20006180D-page 1 MCP3461/2/4 Package Types Package Type for All Devices: 20-Lead UQFN (3 mm x 3 mm)* MCLK DGND DVDD AVDD AGND A. MCP3461: Single Channel Device 20 19 18 17 16 REFIN- 1 15 IRQ/MDAT REFIN+ 2 14 SDO EP 21 CH0 3 CH1 4 13 SDI 12 SCK NC 5 11 CS NC NC NC NC DVDD DGND MCLK 9 10 NC 8 AVDD 7 AGND 6 B. MCP3462: Dual Channel Device 20 19 18 17 16 REFIN- 1 15 IRQ/MDAT REFIN+ 2 14 SDO EP 21 CH0 3 CH1 4 13 SDI 12 SCK CH2 5 6 7 8 CH3 NC NC NC NC AGND AVDD DVDD DGND MCLK 11 CS 9 10 C. MCP3464: Quad Channel Device 20 19 18 17 16 REFIN- 1 15 IRQ/MDAT REFIN+ 2 14 SDO EP 21 CH0 3 CH1 4 13 SDI 12 SCK CH2 5 8 9 10 CH6 CH7 7 CH5 CH3 6 CH4 11 CS *Includes Exposed Thermal Pad (EP); see Table 3-1. DS20006180D-page 2  2019-2021 Microchip Technology Inc. MCP3461/2/4 Package Types Package Types for All Devices: 20-Lead TSSOP (6.5 mm x 4.4 mm x 1 mm) A. MCP3461: Single Channel Device AVDD 1 20 DVDD AGND 2 19 DGND REFIN- 3 18 MCLKIN REFIN+ 4 17 IRQ/MDAT CH0 5 16 SDO CH1 6 15 SDI NC 7 14 SCK NC 8 13 CS NC 9 12 NC NC 10 11 NC AVDD 1 20 DVDD AGND 2 19 DGND B. MCP3462: Dual Channel Device REFIN- 3 18 MCLKIN REFIN+ 4 17 IRQ/MDAT CH0 5 16 SDO CH1 6 15 SDI CH2 7 14 SCK CH3 8 13 CS NC 9 12 NC NC 10 11 NC AVDD 1 20 DVDD AGND 2 19 DGND C. MCP3464: Quad Channel Device Note: REFIN- 3 18 MCLKIN REFIN+ 4 17 IRQ/MDAT CH0 5 16 SDO CH1 6 15 SDI CH2 7 14 SCK CH3 8 13 CS CH4 9 12 CH7 CH5 10 11 CH6 NC is a Not Connected pin. The NC pin is recommended to be tied to AGND for a better susceptibility to electromagnetic fields.  2019-2021 Microchip Technology Inc. DS20006180D-page 3 MCP3461/2/4 Block Diagram of MCP3461/2/4 Devices AVDD REFIN+ DVDD AMCLK MCLK DMCLK/DRCLK REFIN- Clock Generation (RC Oscillator) IRQ/MDAT VREF- VREF+ DMCLK CH0 VIN+ + CH1 VIN- CH2 MCP3462/3464 Only CH3 Analog Differential Multiplexer CH4 CH5 MCP3464 Only ¨—Ȉ 2nd Order Modulator with Analog Gain OSR[3:0] PRE[1:0] + x SINC3 Filter with Digital Gain SINC1 Filter Offset/Gain Calibration SDO Digital SPI Interface and Control SDI SCK CS ¨—Ȉ A/D Converter CH6 CH7 Burnout Current Sources TEMP Diodes DS20006180D-page 4 AGND AVDD POR AVDD Monitoring AGND ANALOG POR DVDD Monitoring DIGITAL DGND  2019-2021 Microchip Technology Inc. MCP3461/2/4 1.0 ELECTRICAL CHARACTERISTICS 1.1 Electrical Specifications Absolute Maximum Ratings(†) DVDD, AVDD ......................................................................................................................................................-0.3 to 4.0V Digital Inputs and Outputs w.r.t. DGND ............................................................................................ -0.3V to DVDD + 0.3V Analog Inputs w.r.t. AGND .................................................................................................................-0.3V to AVDD + 0.3V Current at Input Pins ..............................................................................................................................................±5 mA Current at Output and Supply Pins ...................................................................................................................... ±20 mA Storage Temperature .............................................................................................................................. -65°C to +150°C Ambient Temperature with Power Applied .............................................................................................. -65°C to +125°C Soldering Temperature of Leads (10 seconds) ..................................................................................................... +300°C Maximum Junction Temperature (TJ) ........................................................................................... .........................+150°C ESD on the Analog Inputs (HBM)   6.0 kV ESD on All Other Pins (HBM)  6.0 kV † Notice: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions, above those indicated in the operational listings of this specification, is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.  2019-2021 Microchip Technology Inc. DS20006180D-page 5 MCP3461/2/4 ELECTRICAL CHARACTERISTICS Electrical Specifications: Unless otherwise indicated, all parameters apply at AVDD = 2.7V to 3.6V, DVDD = 1.8V to AVDD + 0.1V, MCLK = 4.9152 MHz, VREF = AVDD, ADC_MODE[1:0] = 11. All other register map bits to their default conditions. TA = -40°C to +125°C, VIN = -0.5 dBFS at 50 Hz. Parameter Sym. Min. Typ. Max. Units Operating Voltage, Analog AVDD 2.7 Operating Voltage, Digital DVDD 1.8 Operating Current, Analog AIDD Test Conditions — 3.6 V — AVDD + 0.1 V — 0.56 0.81 mA BOOST[1:0] = 00, 0.5x — 0.69 0.96 mA BOOST[1:0] = 01, 0.66x — 0.93 1.3 mA BOOST[1:0] = 10, 1x Supply Requirements DVDD ≤ 3.6V — 1.65 2.2 mA BOOST[1:0] = 11, 2x Operating Current, Digital DIDD — 0.25 0.37 mA Note 8 Analog Partial Shutdown Current AIDDS_PS — — 22 µA Digital Partial Shutdown Current DIDDS_PS — — 158 µA Analog Full Shutdown Current AIDDS_FS — — 0.83 µA CONFIG0 = 0x00, TA = +105°C, MCLK input in Idle mode (Note 2) Analog Full Shutdown Current AIDDS_FS — — 1.1 µA CONFIG0 = 0x00, TA = +125°C, MCLK input in Idle mode Digital Full Shutdown Current DIDDS_FS — — 2.4 µA CONFIG0 = 0x00, TA = +105°C, MCLK input in Idle mode (Note 2) Digital Full Shutdown Current DIDDS_FS — — 5 µA CONFIG0 = 0x00, TA = +125°C, MCLK input in Idle mode VPOR_A — 1.75 — V For analog circuits For digital circuits Power-on Reset Threshold Voltage VPOR_D — 1.2 — V POR Hysteresis VPOR_HYS — 150 — mV POR Reset Time tPOR — 1 — µs Note 1: 2: 3: 4: 5: 6: 7: 8: This parameter is ensured by design and not 100% tested. This parameter is ensured by characterization and not 100% tested. REFIN- should be connected to ground for single-ended measurements. Full Scale Range (FSR) = 2 * VREF/GAIN. This input impedance is due to the internal input sampling capacitor and frequency. This impedance is measured between the two input pins of the channel selected with the input multiplexer. Applies to all analog gains. Offset and gain errors depend on gain settings. See Section 2.0 “Typical Performance Curves”. INL is the difference between the endpoints line and the measured code at the center of the quantization band. DIDD is measured while no transfer is present on the SPI bus. DS20006180D-page 6  2019-2021 Microchip Technology Inc. MCP3461/2/4 ELECTRICAL CHARACTERISTICS (CONTINUED) Electrical Specifications: Unless otherwise indicated, all parameters apply at AVDD = 2.7V to 3.6V, DVDD = 1.8V to AVDD + 0.1V, MCLK = 4.9152 MHz, VREF = AVDD, ADC_MODE[1:0] = 11. All other register map bits to their default conditions. TA = -40°C to +125°C, VIN = -0.5 dBFS at 50 Hz. Parameter Sym. Min. Typ. Max. Units Test Conditions Input Voltage at Input Pin CHN AGND – 0.1 — AVDD + 0.1 V Analog inputs are measured with respect to AGND Differential Input Range VIN -VREF/GAIN — +VREF/GAIN V Differential Input Impedance (Note 5) ZIN — 510 — k GAIN = 0.33x, proportional to 1/AMCLK — 260 — k GAIN = 1x, proportional to 1/AMCLK — 150 — k GAIN = 2x, proportional to 1/AMCLK — 80 — k GAIN = 4x, proportional to 1/AMCLK — 40 — k GAIN = 8x, proportional to 1/AMCLK — 20 — k GAIN ≥ 16x, proportional to 1/AMCLK — ±10 — nA Analog Inputs Analog Input Leakage Current During ADC Shutdown ILI_A External Voltage Reference Input Reference Voltage Range (VREF+ – VREF-) VREF 0.6 — AVDD V External Noninverting Input Voltage Reference VREF+ VREF- + 0.6 — AVDD V External Inverting Input Voltage Reference VREF- AGND — VREF+ – 0.6 V Resolution 16 — — Bits Note 1 µV AZ_MUX = 0 (Note 6) DC Performance No Missing Code Resolution Offset Error VOS Offset Error Temperature Coefficient Gain Error Gain Error Temperature Coefficient Note 1: 2: 3: 4: 5: 6: 7: 8: VOS_DRIFT -900/GAIN — 900/GAIN -(0.05 + 0.8/ GAIN) — (0.05 + 0.8/ GAIN) — 70/GAIN 300/GAIN nV/°C AZ_MUX = 0 (Notes 2, 6) — 4/GAIN 16/GAIN — AZ_MUX = 1 (Notes 2, 6) % Note 6 AZ_MUX = 1 (Notes 2, 6) GE -3 — +3 GE_DRIFT — 0.5 2 1 4 GAIN: 8x (Note 2) 2 8 GAIN: 0.33x, 16x (Note 2) ppm/oC GAIN: 1x, 2x, 4x (Note 2) This parameter is ensured by design and not 100% tested. This parameter is ensured by characterization and not 100% tested. REFIN- should be connected to ground for single-ended measurements. Full Scale Range (FSR) = 2 * VREF/GAIN. This input impedance is due to the internal input sampling capacitor and frequency. This impedance is measured between the two input pins of the channel selected with the input multiplexer. Applies to all analog gains. Offset and gain errors depend on gain settings. See Section 2.0 “Typical Performance Curves”. INL is the difference between the endpoints line and the measured code at the center of the quantization band. DIDD is measured while no transfer is present on the SPI bus.  2019-2021 Microchip Technology Inc. DS20006180D-page 7 MCP3461/2/4 ELECTRICAL CHARACTERISTICS (CONTINUED) Electrical Specifications: Unless otherwise indicated, all parameters apply at AVDD = 2.7V to 3.6V, DVDD = 1.8V to AVDD + 0.1V, MCLK = 4.9152 MHz, VREF = AVDD, ADC_MODE[1:0] = 11. All other register map bits to their default conditions. TA = -40°C to +125°C, VIN = -0.5 dBFS at 50 Hz. Parameter Integral Nonlinearity (Note 7) Sym. Min. Typ. Max. INL -10 — +10 Units Test Conditions ppm FSR GAIN = 0.33 (Note 2) -7 — +7 GAIN = 1 (Note 2) -7 — +7 GAIN = 2 (Note 2) 10 — +10 GAIN = 4 (Note 2) -20 — +20 GAIN = 8 (Note 2) -32 — +32 GAIN = 16 (Note 2) — -76 – 20 * LOG (GAIN) — dB AVDD varies from 2.7V to 3.6V, VIN = 0V — -110 — dB DVDD varies from 1.8V to 3.6V, VIN = 0V DC CMRR — -126 — dB VINCOM varies from 0V to AVDD, VIN = 0V SINAD 96.9 97.2 — dB AVDD = DVDD = VREF = 3.3V and TA = +25°C (Note 2) Signal-to-Noise Ratio SNR 97 97.3 — dBc AVDD = DVDD = VREF = 3.3V and TA = +25°C (Note 2) Total Harmonic Distortion THD — -116 -110 dB AVDD = DVDD = VREF = 3.3V and TA = +25°C. Includes the first 10 harmonics (Note 2) Spurious-Free Dynamic Range SFDR 110 120 — dBc AVDD = DVDD = VREF = 3.3V and TA = +25°C (Note 2) Input Channel Crosstalk CTALK — -130 — dB VIN = 0V, perturbation = 0 dB at 50 Hz, applies for all perturbation channels and all input channels AC Power Supply Rejection Ratio AC PSRR — -75 – 20 * LOG (GAIN) — dB VIN = 0V, DVDD = 3.3V, AVDD = 3.3V + 0.3 VP at 50 Hz AC Common-Mode Rejection Ratio AC CMRR — -122 — dB VINCOM = 0 dB at 50 Hz, VIN = 0V AVDD Power Supply Rejection Ratio DC PSRR DVDD Power Supply Rejection Ratio DC Common-Mode Rejection AC Performance Signal-to-Noise and Distortion Ratio ADC Timing Parameters Sampling Frequency DMCLK See Table 5-6 MHz See Figure 4-1 Output Data Rate DRCLK See Table 5-6 ksps See Figure 4-1 Data Conversion Time TCONV See Table 5-6 ms See Figure 4-1 Note 1: 2: 3: 4: 5: 6: 7: 8: This parameter is ensured by design and not 100% tested. This parameter is ensured by characterization and not 100% tested. REFIN- should be connected to ground for single-ended measurements. Full Scale Range (FSR) = 2 * VREF/GAIN. This input impedance is due to the internal input sampling capacitor and frequency. This impedance is measured between the two input pins of the channel selected with the input multiplexer. Applies to all analog gains. Offset and gain errors depend on gain settings. See Section 2.0 “Typical Performance Curves”. INL is the difference between the endpoints line and the measured code at the center of the quantization band. DIDD is measured while no transfer is present on the SPI bus. DS20006180D-page 8  2019-2021 Microchip Technology Inc. MCP3461/2/4 ELECTRICAL CHARACTERISTICS (CONTINUED) Electrical Specifications: Unless otherwise indicated, all parameters apply at AVDD = 2.7V to 3.6V, DVDD = 1.8V to AVDD + 0.1V, MCLK = 4.9152 MHz, VREF = AVDD, ADC_MODE[1:0] = 11. All other register map bits to their default conditions. TA = -40°C to +125°C, VIN = -0.5 dBFS at 50 Hz. Parameter Sym. Min. Typ. Max. TADC_SETUP — 256 — DMCLK ADC_MODE[1:0] = change periods from ‘0x’ to ‘1x’ — 0 — DMCLK ADC_MODE[1:0] = change periods from ‘10’ to ‘11’ TSTP — 1 — DMCLK periods TDLY_SCAN 0 — 512 TTIMER_SCAN 0 — 16777215 Data Ready Pulse Low Time TDRL — — OSR-16 DMCLK See Figure 5-15 periods Data Ready Pulse High Time TDRH 16 — — DMCLK See Figure 5-15 periods Data Transfer Time to DR (Data Ready) tDODR — — 50 ns tDOMDAT — — 100 ns 2.7V ≤ DVDD ≤ 3.6V 200 ns 1.8V ≤ DVDD ≤ 2.7V ADC Start-up Delay Conversion Start Pulse Low Time Scan Mode Time Delays Modulator Output Valid from AMCLK High Units Test Conditions DMCLK Time delay between periods sampling channels DMCLK Time interval between periods scan cycles External Master Clock Input (CLK_SEL[1] = 0) Master Clock, Input Frequency Range fMCLK_EXT Master Clock Input Duty Cycle 1 — 20 MHz DVDD ≥ 2.7V 1 — 10 MHz DVDD < 2.7V fMCLK_DUTY 45 — 55 % fMCLK_INT 3.3 — 6.6 MHz tOSC_STARTUP — 10 — µs CLK_SEL[1] changes from ‘0’ to ‘1’, time to stabilize the clock frequency to ±1 kHz of the final value IDDOSC — 30 — µA Should be added to DIDD when CLK_SEL[1:0] = 1x TACC — ±5 — °C See Section 5.1.2 Internal Clock Oscillator Internal Master Clock Frequency Internal Oscillator Start-up Time Internal Oscillator Current Consumption CLK_SEL[1] = 1 Internal Temperature Sensor Temperature Measurement Accuracy “Internal Temperature Sensor” for accuracy calculation Note 1: 2: 3: 4: 5: 6: 7: 8: This parameter is ensured by design and not 100% tested. This parameter is ensured by characterization and not 100% tested. REFIN- should be connected to ground for single-ended measurements. Full Scale Range (FSR) = 2 * VREF/GAIN. This input impedance is due to the internal input sampling capacitor and frequency. This impedance is measured between the two input pins of the channel selected with the input multiplexer. Applies to all analog gains. Offset and gain errors depend on gain settings. See Section 2.0 “Typical Performance Curves”. INL is the difference between the endpoints line and the measured code at the center of the quantization band. DIDD is measured while no transfer is present on the SPI bus.  2019-2021 Microchip Technology Inc. DS20006180D-page 9 MCP3461/2/4 TEMPERATURE CHARACTERISTICS(1) Electrical Specifications: Unless otherwise specified, all parameters apply for TA = -40°C to +125°C, AVDD = 2.7V to 3.6V, DVDD = 1.8V to AVDD + 0.1V, DGND = AGND = 0V. Parameters Sym. Min. Typ. Max. Units Specified Temperature Range TA -40 — +125 °C Operating Temperature Range TA -40 — +125 °C Storage Temperature Range TA -65 — +150 °C Thermal Resistance, 20-Lead TSSOP JA — 44 — °C/W Thermal Resistance, 20-Lead UQFN JA — 50 — °C/W Conditions Temperature Ranges Thermal Package Resistance Note 1: The internal Junction Temperature (TJ) must not exceed the absolute maximum specification of +150°C. TABLE 1-1: SPI SERIAL INTERFACE TIMING SPECIFICATIONS FOR DVDD = 2.7V TO 3.6V Electrical Specifications: DVDD = 2.7V to 3.6V, TA = -40°C to +125°C, CLOAD = 30 pF. See Figure 1-1. Parameters Symbol Min. Typ. Max. Units Serial Clock Frequency fSCK — — 20 MHz CS Setup Time tCSS 25 — — ns CS Hold Time tCSH 50 — — ns CS Disable Time tCSD 50 — — ns Data Setup Time tSU 5 — — ns Data Hold Time tHD 10 — — ns Serial Clock High Time tHI 20 — — ns Serial Clock Low Time tLO 20 — — ns Serial Clock Delay Time tCLD 50 — — ns Serial Clock Enable Time tCLE 50 — — ns Output Valid from SCK Low tDO — — 25 ns Conditions Output Hold Time tHO 0 — — ns Output Disable Time tDIS — — 25 ns Measured with 1.5 mA pull-up current source on SDO pin POR IRQ Disable Time tCSIRQ — — 52 ns Measured with 1.5 mA pull-up current source on IRQ pin Output Valid from CS Low tCSSDO — — 25 ns SDO toggles to logic low at each communication start (CS falling edge) DS20006180D-page 10  2019-2021 Microchip Technology Inc. MCP3461/2/4 TABLE 1-2: SPI SERIAL INTERFACE TIMING SPECIFICATIONS FOR DVDD = 1.8V TO 2.7V (10 MHz MAXIMUM SCK FREQUENCY) Electrical Specifications: DVDD = 1.8V to 2.7V, TA = -40°C to +125°C, CLOAD = 30 pF. See Figure 1-1. Parameters Serial Clock Frequency Sym. Min. Typ. Max. Units fSCK — — 10 MHz Conditions CS Setup Time tCSS 50 — — ns CS Hold Time tCSH 100 — — ns CS Disable Time tCSD 100 — — ns Data Setup Time tSU 10 — — ns Data Hold Time tHD 20 — — ns Serial Clock High Time tHI 40 — — ns Serial Clock Low Time tLO 40 — — ns Serial Clock Delay Time tCLD 100 — — ns Serial Clock Enable Time tCLE 100 — — ns Output Valid from SCK Low tDO — — 50 ns Output Hold Time tHO 0 — — ns Output Disable Time tDIS — — 50 ns Measured with 1.5 mA pull-up current source on SDO pin POR IRQ Disable Time tCSIRQ — — 60 ns Measured with 1.5 mA pull-up current source on IRQ pin Output Valid From CS Low tCSSDO — — 50 ns SDO toggles to logic low at each communication start (CS falling edge) TABLE 1-3: DIGITAL I/O DC SPECIFICATIONS Electrical Specifications: Unless otherwise indicated, all parameters apply at DVDD = 1.8V to 3.6V, TA = -40°C to +125°C. Parameters Sym. Min. Typ. Max. Units Schmitt Trigger High-Level Input Voltage VIH 0.7 * DVDD — — V Schmitt Trigger Low-Level Input Voltage VIL — — 0.3 * DVDD V VHYS — 200 — mV 0.2 * DVDD Hysteresis of Schmitt Trigger Inputs Low-Level Output Voltage VOL — — High-Level Output Voltage VOH 0.8 * DVDD — Input Leakage Current ILI_D — —  2019-2021 Microchip Technology Inc. 1 Conditions V IOL = +1.5 mA V IOH = -1.5 mA µA Pins configured as inputs or high-impedance outputs DS20006180D-page 11 MCP3461/2/4 FIGURE 1-1: DS20006180D-page 12 Serial Output Timing Diagram.  2019-2021 Microchip Technology Inc. MCP3461/2/4 2.0 TYPICAL PERFORMANCE CURVES Note: The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore outside the warranted range. Note: Unless otherwise indicated, AVDD = 3.3V, DVDD = 3.3V, TA = +25°C, MCLK = 4.9152 MHz, VIN = -0.5 dBFS at 50 Hz, VREF = AVDD, ADC_MODE = 11. All other registers are set to default value. Histogram ticks are centered at their bin center. 6 VIN = -0.5 dBFS @ 50 Hz FFT 16384 samples -20 Integral Non-Linearity (ppm of 2*VREF) Output Amplitude (dBFS) 0 -40 -60 -80 -100 -120 -140 -160 -180 0 500 FIGURE 2-1: Input). 1000 1500 Frequency (Hz) 2000 0 -2 -4 -6 -100 Intrinsic Noise (ppm of 2*VREF) VIN = -0.5 dBFS @ 1 kHz FFT 16384 samples -50 0 50 Differential Input Voltage (% of VREF) -40 5 AVDD=VREF=2.7V, -40°C AVDD=VREF=2.7V, +125°C AVDD=VREF=3.6V, -40°C AVDD=VREF=3.6V, +125°C Gain = 1x Intrinsic noise means before 16-bit Rounding/quantization 4 3.5 -60 -80 3 2.5 -100 -120 100 INL vs. Input Voltage. 4.5 2 1.5 -140 1 0.5 -160 -180 0 500 1000 1500 2000 2500 0 -100 Frequency (Hz) FIGURE 2-2: Input). 50000 40000 30000 20000 100 Output Noise vs. Input 20 Maximum INL (ppm of 2*VREF) 60000 -50 0 50 Differential Input Voltage (% of VREF) FIGURE 2-5: Voltage. Output Spectrum (1 kHz 70000 Occurrence (Counts) AVDD=VREF=2.7V, -40°C AVDD=VREF=2.7V, +125°C AVDD=VREF=3.6V, -40°C AVDD=VREF=3.6V, +125°C Gain = 1x FIGURE 2-4: 0 Output Amplitude (dBFS) 2 2500 Output Spectrum (50 Hz -20 4 VIN = 0V CONV_MODE[1:0] = 11 64000 samples Bin size = 1 LSE Histograms may show up to 2 bins equally distributed if offset is close to a round LSE value (Intrinsic noise 512), the thermal noise is largely dominant and increases proportionally to the square root of the absolute temperature. The performance on the following tables has been measured with AVDD = DVDD = VREF = 3.3V and with the device placed in Continuous Conversion mode, with the differential input voltage equal to VIN = 0V, default conditions for the register map and MCLK = 4.9152 MHz. The noise performance is also a function of the measurement duration. For short duration measurements (low number of consecutive samples), the peak-to-peak noise is usually reduced because the crest factor (ratio between the RMS noise and peak-to-peak noise) is reduced. This is only a consequence of the noise distribution being Gaussian by nature (see Figure 2-3 for noise histogram example and fitting with an ideal Gaussian distribution). The noise specifications have been measured with a sample size of 16384 samples for low OSR values and have been capped to approximately 80 seconds for the 16384 samples, leading to a larger duration. The noise specifications are expressed in two different values which lead to the same quantity. It may be more practical to choose one of these representations depending on the desired application. In Table 2-1, the RMS (Root Mean Square) noise is the variance of the ADC output code, expressed in µVRMS and input referred with Equation 5-5. The peak-to-peak noise values are under parentheses. The peak-to-peak noise is the difference between the maximum and minimum code observed during the complete time of the measurement (see Equation 5-5). In Table 2-2, the noise is expressed in Effective Resolution (ER). The Effective Resolution is a ratio of the full-scale range of the ADC (that depends on VREF and GAIN) and the noise performance of the device. The Effective Resolution can be determined from the RMS or peak-to-peak noise with the following equations. DS20006180D-page 20 EQUATION 2-1: 2  V REF In  ------------------------------------------------------ GAIN  RMS  Noise  ER RMS = ---------------------------------------------------------------In  2  EQUATION 2-2: 2  V REF In  --------------------------------------------------------------------- GAIN  Peak-to-Peak Noise ER pk – pk = ------------------------------------------------------------------------------In  2  Due to the nature of the noise, the performance detailed in the noise tables can vary significantly from one measurement to another. They present an averaging of the performance over a large distribution of parts over multiple lots. They give the typical expectation of the noise performance, but performance can be better or worse if a limited number of measurements is performed. For large GAIN and OSR combinations, if the noise performance is comparable to the quantization step (1 LSb), the performance is limited to 0.5 LSb for the RMS noise and 1 LSb for the peak-to-peak noise (same limits for Effective Resolution values). These figures correspond to the resolution limit of the device as peak-to-peak noise cannot be better than 1 LSb. Similarly, if the intrinsic RMS noise of the device is much smaller than 0.5 LSb, it may lead to histogram with either one or two bins depending on the relative position of the input voltage versus the possible quantized outputs of the ADC. If the position is exactly in between two quantization steps, the histogram of output noise will have two bins with exactly 50% occurrence on each. This case gives an RMS noise of a 0.5 LSb value, which is therefore used as a cap of the performance for the sake of clarity and a better representation on the noise tables. The noise specifications are improved by a ratio of approximately √2 (or 0.5-bit Effective Resolution) when the AZ_MUX setting is enabled. However, the output data rate is significantly reduced (see Figure 5-5 and Table 5-6). The digital gain added for GAIN = 32x and 64x settings is not significant for the noise performance. Therefore, the noise values can be extracted from the GAIN = 16x columns. Effective Resolution performance is degraded by 1 bit for GAIN = 32x and 2 bits for GAIN = 64x compared to the GAIN = 16x performance.  2019-2021 Microchip Technology Inc. MCP3461/2/4 TABLE 2-1: NOISE RMS LEVEL VS. GAIN VS. OSR (AVDD = DVDD = VREF = 3.3V, TA = +25°C) RMS (Peak-to-Peak) Noise (µV) Total OSR GAIN = 0.33 GAIN = 1 GAIN = 2 GAIN = 4 GAIN = 8 GAIN = 16 32 388.9 (2829.9) 130.2 (950) 65.7 (481.7) 33.2 (240.9) 17 (125.5) 8.9 (66.9) 64 151.1 (564) 50.4 (184.6) 25.2 (102.4) 12.6 (56.2) 6.3 (34.8) 3.4 (22.5) 128 151.1 (302.1) 50.4 (107.4) 25.2 (57.1) 12.6 (33.6) 6.3 (21.4) 3.2 (14.3) 256 151.1 (302.1) 50.4 (100.7) 25.2 (50.4) 12.6 (25.2) 6.3 (15.9) 3.2 (10.5) 512 151.1 (302.1) 50.4 (100.7) 25.2 (50.4) 12.6 (25.2) 6.3 (12.6) 3.2 (6.9) 1024 151.1 (302.1) 50.4 (100.7) 25.2 (50.4) 12.6 (25.2) 6.3 (12.6) 3.2 (6.3) 2048 151.1 (302.1) 50.4 (100.7) 25.2 (50.4) 12.6 (25.2) 6.3 (12.6) 3.2 (6.3) 4096 151.1 (302.1) 50.4 (100.7) 25.2 (50.4) 12.6 (25.2) 6.3 (12.6) 3.2 (6.3) 8192 151.1 (302.1) 50.4 (100.7) 25.2 (50.4) 12.6 (25.2) 6.3 (12.6) 3.2 (6.3) 16384 151.1 (302.1) 50.4 (100.7) 25.2 (50.4) 12.6 (25.2) 6.3 (12.6) 3.2 (6.3) 20480 151.1 (302.1) 50.4 (100.7) 25.2 (50.4) 12.6 (25.2) 6.3 (12.6) 3.2 (6.3) 24576 151.1 (302.1) 50.4 (100.7) 25.2 (50.4) 12.6 (25.2) 6.3 (12.6) 3.2 (6.3) 40960 151.1 (302.1) 50.4 (100.7) 25.2 (50.4) 12.6 (25.2) 6.3 (12.6) 3.2 (6.3) 49152 151.1 (302.1) 50.4 (100.7) 25.2 (50.4) 12.6 (25.2) 6.3 (12.6) 3.2 (6.3) 81920 151.1 (302.1) 50.4 (100.7) 25.2 (50.4) 12.6 (25.2) 6.3 (12.6) 3.2 (6.3) 98304 151.1 (302.1) 50.4 (100.7) 25.2 (50.4) 12.6 (25.2) 6.3 (12.6) 3.2 (6.3) TABLE 2-2: Total OSR EFFECTIVE RESOLUTION VS. GAIN VS. OSR (AVDD = DVDD = VREF = 3.3V, TA = +25°C) Effective Resolution RMS (Peak-to-Peak) (bits) GAIN = 0.33 GAIN = 1 GAIN = 2 GAIN = 4 GAIN = 8 GAIN = 16 32 15.6 (12.8) 15.6 (12.8) 15.6 (12.7) 15.6 (12.7) 15.6 (12.7) 15.5 (12.6) 64 17 (15.2) 17 (15.2) 17 (15) 17 (14.9) 17 (14.5) 16.9 (14.2) 128 17 (16) 17 (15.9) 17 (15.9) 17 (15.6) 17 (15.3) 17 (14.9) 256 17 (16) 17 (16) 17 (16) 17 (16) 17 (15.7) 17 (15.4) 512 17 (16) 17 (16) 17 (16) 17 (16) 17 (16) 17 (15.9) 1024 17 (16) 17 (16) 17 (16) 17 (16) 17 (16) 17 (16) 2048 17 (16) 17 (16) 17 (16) 17 (16) 17 (16) 17 (16) 4096 17 (16) 17 (16) 17 (16) 17 (16) 17 (16) 17 (16) 8192 17 (16) 17 (16) 17 (16) 17 (16) 17 (16) 17 (16) 16384 17 (16) 17 (16) 17 (16) 17 (16) 17 (16) 17 (16) 20480 17 (16) 17 (16) 17 (16) 17 (16) 17 (16) 17 (16) 24576 17 (16) 17 (16) 17 (16) 17 (16) 17 (16) 17 (16) 40960 17 (16) 17 (16) 17 (16) 17 (16) 17 (16) 17 (16) 49152 17 (16) 17 (16) 17 (16) 17 (16) 17 (16) 17 (16) 81920 17 (16) 17 (16) 17 (16) 17 (16) 17 (16) 17 (16) 98304 17 (16) 17 (16) 17 (16) 17 (16) 17 (16) 17 (16) Note: To calculate noise RMS level and Effective Resolution (Bits) for a given GAIN and data rate, please refer to the OSR setting and associated data rate relationship shown in Table 5-6.  2019-2021 Microchip Technology Inc. DS20006180D-page 21 MCP3461/2/4 NOTES: DS20006180D-page 22  2019-2021 Microchip Technology Inc. MCP3461/2/4 3.0 PIN DESCRIPTION TABLE 3-1: MCP3461/2/4 PIN FUNCTION TABLE MCP3461 MCP3462 MCP3464 MCP3461 MCP3462 MCP3464 Symbol 20-Lead UQFN 20-Lead TSSOP 1 3 REFIN- 2 4 REFIN+ 3 5 CH0 4 — 6 Noninverting Reference Input Pin Analog Input 0 Pin CH1 Analog Input 1 Pin 7 CH2 Analog Input 2 Pin — 8 8 CH3 Analog Input 3 Pin — — 9 CH4 Analog Input 4 Pin 8 — — 10 CH5 Analog Input 5 Pin — 9 — — 11 CH6 Analog Input 6 Pin — 10 — — 12 CH7 Analog Input 7 Pin 5 — — 6 6 — — 7 — — — 5, 6, 7, 8, 9, 10 Inverting Reference Input Pin 7 5 — Description Serial Interface Chip Select Digital Input Pin 11 13 CS 12 14 SCK 13 15 SDI Serial Interface Digital Data Input Pin 14 16 SDO Serial Interface Digital Data Output Pin 15 17 IRQ/MDAT Interrupt Output Pin or Modulator Output Pin 16 18 MCLK Master Clock Input or Analog Master Clock Output Pin 17 19 DGND Digital Ground Pin 18 20 DVDD Digital Supply Voltage Pin 19 1 AVDD Analog Supply Voltage Pin 20 2 AGND 7, 8, 9, 10 — 7, 8, 9, 9, 10, 11, 10, 11, 12 12 21  2019-2021 Microchip Technology Inc. — — Serial Interface Digital Clock Input Pin Analog Ground Pin — NC Not Connected — EP Exposed Thermal Pad, internally connected to AGND DS20006180D-page 23 MCP3461/2/4 3.1 Differential Reference Voltage Inputs: REFIN+, REFIN- REFIN+ pin is the noninverting differential reference input (VREF+). REFIN- pin is the inverting differential reference input (VREF-). For single-ended reference applications, the REFINpin should be directly connected to AGND. The differential reference voltage pins must respect this condition at all times: 0.6V ≤ VREF ≤ AVDD. The differential reference voltage input is given by Equation 3-1: EQUATION 3-1: V REF = V REF+ – V REFFor optimal ADC accuracy, appropriate bypass capacitors should always be placed between REFIN+ and AGND. Using 0.1 µF and 10 µF ceramic capacitors helps with decoupling the reference voltage around the sampling frequency (which would lead to aliasing noise in the base band). These bypass capacitors are not mandatory for correct ADC operation, but removing these capacitors may degrade accuracy of the ADC. 3.2 Analog Inputs (CHn): Differential or Single-Ended The CHn pins are the analog input signal pins for the ADC. Two analog multiplexers are used to connect the CHn pins to the VIN+/VIN- analog inputs of the ADC. Each multiplexer independently selects one input to be connected to an ADC input (VIN+ or VIN-). Each CHn pin can either be connected to the VIN+ or VIN- inputs of the ADC. This multiplexer selection is controlled by either the MUX register in MUX mode or the SCAN register in SCAN mode. See Figure 5-1 for more details on the multiplexer structure. When the input is selected by the multiplexer, the differential (VIN) and Common-Mode Voltage (VINCOM) at the ADC inputs are defined by Equation 3-2. EQUATION 3-2: V IN = V IN+ – V INV IN+ + V INV INCOM = --------------------------------2 The input signal level is multiplied by the internal programmable analog gain at the front end of the  modulator. For single-ended input measurements, the user can select VIN- to be internally connected to AGND. The differential input voltage should not exceed an absolute of ±VREF/GAIN for accurate measurement. If the input is out of range, the converter output code will be saturated or overloaded depending on how the DS20006180D-page 24 output data format (DATA_FORMAT[1:0]) is selected. See Section 5.6 “ADC Output Data Format” for further information on the ADC output coding. The absolute voltage range on each of the analog signal input pins is from AGND – 0.1V to VDD + 0.1V. Any voltage above or below this range will cause leakage currents through the Electrostatic Discharge (ESD) diodes at the input pins. This ESD current can cause unexpected performance of the device. The Common-mode of the analog inputs should be chosen such that both the differential analog input range and the absolute voltage range on each pin are within the specified operating range defined in the Electrical Characteristics table. 3.3 SPI Serial Interface Communication pins The SPI interface is compatible with both SPI Mode 0,0 and 1,1. 3.3.1 CHIP SELECT (CS) This is the SPI chip select pin that enables/disables the SPI serial communication. The CS falling edge initiates the serial communication and the rising edge terminates the communication. No communication can take place when this pin is in Logic High state. This input is Schmitt Triggered. 3.3.2 SERIAL DATA CLOCK (SCK) This is the serial clock input pin for SPI communication. This input has Schmitt Trigger structure. The maximum SPI clock speed is 20 MHz. Data are clocked into the device on the rising edge of SCK. Data are clocked out of the device on the falling edge of SCK. The device interface is compatible with both SPI Mode 0,0 and 1,1. SPI modes can be changed when CS is in Logic High state. SCK and MCLK are two different and asynchronous clocks; SCK is only required when a communication happens, while MCLK is continuously required when the part is converting analog inputs. 3.3.3 SERIAL DATA OUTPUT PIN (SDO) This pin is used for the SPI Data Output (SDO). The SDO data are clocked out on the falling edge of SCK. This pin stays high-impedance under the following conditions: • When CS pin is logic high. • During the whole SPI write or Fast command communication period, after the SPI COMMAND byte has been transmitted. • After the two device address bits in the command have been transmitted if the device address in the command is not matching an internal chip device address.  2019-2021 Microchip Technology Inc. MCP3461/2/4 3.3.4 SERIAL DATA INPUT PIN (SDI) This is the SPI data input pin and it uses Schmitt Trigger structure. When CS is logic low, this pin is used to send a COMMAND byte just after the CS falling edge, which can be followed by data words of various lengths. Data are clocked into the device on the rising edge of SCK. Toggling SDI while reading a register has no effect. 3.4 IRQ/MDAT This is the digital output pin. This pin can be configured for Interrupt (IRQ) or Modulator Data (MDAT) output using the IRQ_MODE[1] bit setting. When IRQ_MODE[1] = 0 (default), this pin can output all four possible interrupts (see Section 6.8 “Interrupts Description”). The inactive state of the pin is selectable through the IRQ_MODE[0] bit setting (high-Z or logic high). When IRQ_MODE[1] = 1, this pin outputs the modulator output synchronously with AMCLK (that can be selected as an output on the MCLK pin). In this mode, the POR and CRC interrupts can still be generated as they are high-level interrupts and will lock the IRQ/MDAT pin to logic low until they are cleared. When the IRQ pin is in High-Z mode, an external pull-up resistor must be connected between DVDD and the IRQ pin. The device needs to be able to detect a Logic High state when no interrupt occurs in order to function properly (the pad has a Schmitt Trigger input to detect the state of the IRQ pin just like the user is seeing it). The pull-up value can be equal to 100-200 k for a weak pull-up using the typical clock frequency. The pull-up resistor value needs to be chosen in relation with the load capacitance of the IRQ output, the MCLK frequency and the DVDD supply voltage, so that all interrupts can be detected correctly by the SPI host device. 3.5 MCLK This pin is either the MCLK digital input pin for the ADC or the AMCLK digital output pin, depending on the CLK_SEL[1:0] bits setting in the CONFIG0 register. The typical clock frequency specified is 4.9152 MHz. To optimize the ADC for accuracy and ensure proper operation, AMCLK should be limited to a certain range depending on BOOST and GAIN settings. The higher GAIN settings require higher BOOST settings to maintain high bandwidth, as the input sampling capacitors have a larger value. Figure 2-20 to Figure 2-24 represent the typical accuracy (SINAD) expected with the different combinations of BOOST and GAIN settings, and can be used to determine an optimal set for the application depending on the sampling speed (AMCLK) chosen. MCLK can take  2019-2021 Microchip Technology Inc. larger values as long as the prescaler settings (PRE[1:0]) limit AMCLK = MCLK/PRESCALE in the defined range in typical performance curves. 3.6 Digital Ground (DGND) DGND is the ground connection to internal digital circuitry. To ensure accuracy and noise cancellation, DGND must be connected to the same ground as AGND, preferably with a star connection. If a digital ground plane is available, it is recommended for this pin to be tied to this plane of the PCB. This plane should also reference all other digital circuitry in the system. DGND is not connected internally to AGND and must be connected externally. 3.7 Digital Power Supply (DVDD) DVDD is the power supply pin for the digital circuitry within the device. The voltage on this pin must be maintained in the range specified by the Electrical Characteristics table. For optimal performance, it is recommended to connect appropriate bypass capacitors (typically a 10 µF ceramic in parallel with a 0.1 µF ceramic). DVDD is monitored by the DVDD POR monitoring circuit for the digital section. 3.8 Analog Power Supply (AVDD) AVDD is the power supply pin for the analog circuitry within the device. The voltage on this pin must be maintained in the range specified by the Electrical Characteristics table. For optimal performance, it is recommended to connect appropriate bypass capacitors (typically a 10 µF ceramic in parallel with a 0.1 µF ceramic). AVDD is monitored by the AVDD POR monitoring circuit for the analog section. 3.9 Analog Ground (AGND) AGND is the ground connection to internal analog circuitry. To ensure accuracy and noise cancellation, this pin must be connected to the same ground as DGND, preferably with a star connection. If an analog ground plane is available, it is recommended that this pin be tied to this plane of the PCB. This plane should also reference all other analog circuitry in the system. AGND is the biasing voltage for the substrate of the die and is not connected internally to DGND. 3.10 Exposed Pad (EP) This pad is internally connected to AGND. It must be connected to the analog ground of the PCB for optimal accuracy and thermal performance. This pad can also be left floating if necessary. DS20006180D-page 25 MCP3461/2/4 NOTES: DS20006180D-page 26  2019-2021 Microchip Technology Inc. MCP3461/2/4 4.0 TERMINOLOGY AND FORMULAS • • • • • • • • • • • This section defines the terms and formulas used throughout this document. The following terminology is defined: • • • • • MCLK – Master Clock AMCLK – Analog Master Clock DMCLK – Digital Master Clock DRCLK – Data Rate Clock OSR – Oversampling Ratio Offset Error Gain Error Integral Nonlinearity Error (INL) Signal-to-Noise Ratio (SNR) Signal-to-Noise and Distortion Ratio (SINAD) Total Harmonic Distortion (THD) Spurious-Free Dynamic Range (SFDR) MCP3461/2/4 Delta-Sigma Architecture Power Supply Rejection Ratio (PSRR) Common-Mode Rejection Ratio (CMRR) Digital Pins’ Output Current Consumption PRE[1:0] CLK_SEL[1] OSR[3:0] CLK_SEL[1] = 0 MCLK Pad 0 OU T MCLK 1/ PRESCALE AMCLK 1/4 DMCLK 1/OSR DRCLK 1 Intern al Oscillator Multiplexer Clock Divider Clock Divider Clock Divider CLK_SEL[1:0] = 11 AMCLKOUT FIGURE 4-1: 4.1 System Clock Details. MCLK – Master Clock This is either the master clock frequency at the MCLK input pin when an external clock source is selected or the internal clock frequency when an internal clock is selected. 4.2 AMCLK – Analog Master Clock EQUATION 4-2: DIGITAL MASTER CLOCK MCLK DMCLK = AMCLK --------------------- = -------------------------------4 4  Prescale 4.4 DRCLK – Data Rate Clock This is the clock frequency that is present on the analog portion of the device after prescaling has occurred via the PRE[1:0] bits. This is the output data rate in Continuous mode, which is the rate at which the ADC outputs new data. Each new data are signaled by a data ready pulse on the IRQ pin. This data rate depends on the OSR and the prescaler, as shown in Equation 4-3. EQUATION 4-1: EQUATION 4-3: ANALOG MASTER CLOCK MCLK AMCLK = ---------------------Prescale 4.3 DMCLK – Digital Master Clock This is the clock frequency that is present on the digital portion of the device. This is also the sampling frequency or the rate at which the modulator outputs are refreshed. Each period of this clock corresponds to one sample and one modulator output. See Equation 4-2.  2019-2021 Microchip Technology Inc. DATA RATE AMCLK = -------------------------------------------------MCLK DRCLK = DMCLK ---------------------- = --------------------OSR 4  OSR 4  OSR  Prescale Since this is the output data rate, and since the decimation filter is a sinc (or notch) filter, there is a notch in the filter transfer function at each integer multiple of this rate. DS20006180D-page 27 MCP3461/2/4 4.5 OSR – Oversampling Ratio The ratio of the sampling frequency to the output data rate. OSR = DMCLK/(DRCLK) in Continuous mode. See Table 5-6 for the OSR setting effect on sinc filter parameters. 4.6 Offset Error This is the error induced by the ADC when the inputs are shorted together (VIN = 0V). This error varies based on gain settings, OSR settings and from chip to chip. It can easily be calibrated out by a MCU with a subtraction. 4.7 Gain Error 4.10 Signal-to-Noise and Distortion Ratio (SINAD) Signal-to-Noise and Distortion Ratio is similar to Signal-to-Noise Ratio, with the exception that you must include the harmonics power in the noise power calculation. The SINAD specification depends mainly on the OSR and GAIN settings. EQUATION 4-5: SINAD EQUATION SignalPower SINAD  dB  = 10 log  ---------------------------------------------------------------------  Noise + HarmonicsPower The calculated combination of SNR and THD per Equation 4-6 also yields SINAD: This is the error induced by the ADC on the slope of the transfer function. It is the deviation expressed in percentage compared to the ideal transfer function defined by Equation 5-5. The specification incorporates ADC gain error contributions, but not the VREF contribution. This error varies with GAIN and OSR settings. EQUATION 4-6: The gain error of this device has a low-temperature coefficient. 4.11 4.8 The Total Harmonic Distortion is the ratio of the output harmonics’ power to the fundamental signal power for a sine wave input and is defined by Equation 4-7. Integral Nonlinearity Error (INL) Integral nonlinearity error is the maximum deviation of an ADC transition point from the corresponding point of an ideal transfer function, with the offset and gain errors removed, or with the end points equal to zero. It is the maximum remaining static error after calibration of offset and gain errors for a DC input signal. 4.9 Signal-to-Noise Ratio (SNR) For this device family, the Signal-to-Noise ratio is a ratio of the output fundamental signal power to the noise power (not including the harmonics of the signal) when the input is a sine wave at a predetermined frequency. It is measured in dB. Usually, only the maximum Signal-to-Noise Ratio is specified. The SNR figure depends mainly on the OSR and GAIN settings of the device as well as temperature (due to thermal noise being dominant for high OSR). EQUATION 4-4: SIGNAL-TO-NOISE RATIO SignalPower SNR  dB  = 10 log  ----------------------------------  NoisePower  SINAD, THD AND SNR RELATIONSHIP SINAD  dB  = 10 log 10  SNR -----------  10  + 10  THD ------------  10  Total Harmonic Distortion (THD) EQUATION 4-7: HarmonicsPower THD  dB  = 10 log  ----------------------------------------------------- FundamentalPower The THD is usually only measured with respect to the ten first harmonics. THD is sometimes expressed in percentage (%). For converting the THD from “dB” to “%”, apply the formula in Equation 4-8. EQUATION 4-8: THD  %  = 100  10 4.12 THD  dB  -----------------------20 Spurious-Free Dynamic Range (SFDR) The ratio between the output power of the fundamental and the highest spur in the frequency spectrum. The spur frequency is not necessarily a harmonic of the fundamental, even though it is usually the case. This figure represents the dynamic range of the ADC when a full-scale signal is used at the input. This specification depends mainly on the OSR and GAIN setting. EQUATION 4-9: FundamentalPower SFDR  dB  = 10 log  -----------------------------------------------------  HighestSpurPower  DS20006180D-page 28  2019-2021 Microchip Technology Inc. MCP3461/2/4 4.13 MCP3461/2/4 Delta-Sigma Architecture A Delta-Sigma ADC is an oversampling converter that incorporates a built-in modulator, which digitizes the quantity of charge integrated by the modulator loop. The quantizer is the block that performs the Analogto-Digital conversion. The quantizer is typically 1-bit or a simple comparator that helps to maintain the linearity performance of the ADC (the DAC structure, is in this case, inherently linear). Multibit quantizers help to lower the quantization error (the error fed back in the loop can be very large with 1-bit quantizers) without changing the order of the modulator or the OSR that leads to better SNR figures. However, typically, the linearity of such architectures is more difficult to achieve since the DAC is no more simple to realize and its linearity limits the THD of such ADC. The modulator 5-level quantizer is a Flash ADC composed of four comparators arranged with equally spaced thresholds and a thermometer coding. The device also includes proprietary 5-level DAC architecture that is inherently linear for improved THD figures. 4.14 Power Supply Rejection Ratio (PSRR) This is the ratio between a change in the power supply voltage and the ADC output codes. It measures the influence of the power supply voltage on the ADC outputs. The PSRR specification can be DC (the power supply is taking multiple DC values) or AC (the power supply is a sine wave at a certain frequency with a certain Common-mode). In AC, the amplitude of the sine wave represents the change in the power supply. EQUATION 4-10:  V OUT PSRR  dB  = 20 log  -------------------   AV DD Where VOUT is the equivalent input voltage that the output code translates to with the ADC transfer function. 4.15 Common-Mode Rejection Ratio (CMRR) This is the ratio between a change in the Common-mode input voltage and the change in ADC output codes. It measures the influence of the Common-mode input voltage on the ADC outputs. The CMRR specification can be DC (Common-mode input voltage is taking multiple DC values) or AC (the Common-mode input voltage is a sine wave at a certain frequency with a certain Common-mode). In AC, the amplitude of the sine wave represents the change in the input Common-mode voltage. CMRR is defined in Equation 4-11. EQUATION 4-11:  V OUT CMRR  dB  = 20 log  ------------------------   V INCOM Where VINCOM = (VIN+ + VIN-)/2 is the Common-mode input voltage and VOUT is the equivalent input voltage that the output code translates to with the ADC transfer function. 4.16 Digital Pins’ Output Current Consumption The digital current consumption, shown in the Electrical Characteristics table, does not take into account the current consumption generated by the digital output pins and the charge of their capacitive loading. The specification is intended with all output pins left floating and no communication. In order to estimate the additional current consumption due to the output pins, refer to Equation 4-2. This equation specifies the amount of additional current due to each pin when its output is connected to a Cload capacitance, with respect to DGND and submitted to an output signal toggling at an fout frequency. If a typical 10 MHz SPI frequency is used, with a 30 pF load and DVDD = 3.3V, the SDO output generates an additional maximum current consumption of 500 µA (the maximum toggling frequency of SDO is 5 MHz here, since fSCK = 10 MHz and this maximum happens when the ADC output code is a succession of ‘1’s and ‘0’s). The Cload value includes internal digital output driver capacitance, but this one can generally be neglected with respect to the external loading capacitance. EQUATION 4-12: DIDD SPI = C load  DV DD  f out Where: Cload = Capacitance on the Output Pin DVDD = Digital Supply Voltage fout = Output Frequency on the Output Pin  2019-2021 Microchip Technology Inc. DS20006180D-page 29 MCP3461/2/4 NOTES: DS20006180D-page 30  2019-2021 Microchip Technology Inc. MCP3461/2/4 5.0 DEVICE OVERVIEW 5.1 Analog Input Multiplexer input selection, so that any required combination of input voltages can be converted by the ADC. The analog multiplexer is composed of parallel low-resistance input switches, turned on or off, depending on the input channel selection. Their resistance is negligible compared to the input impedance of the ADC (caused by the charge and discharge of the input sampling capacitors on the VIN+/VIN- ADC inputs). The block diagram of the analog multiplexer is shown in Figure 5-1. The device includes a fully configurable analog input dual multiplexer that can select which input is connected to each of the two differential input pins (VIN+/VIN-) of the Delta-Sigma ADC. The dual multiplexer is divided into two single-ended multiplexers that are completely independent. Each of these multiplexers include the same possibilities for the MUX[7:4] CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 AGND AVDD AVDD REFIN+ REFIN- CS_SEL[1:0] TEMP Diode P AVDD ISOURCE AVDD ITEMP+ ITEMP- TEMP Diode M MUX[7:4] = 1101 VCM MUX[3:0] = 1101 VIN+ Analog Multiplexer MUX[3:0] =1110 VIN+ AGND MUX[3:0] VIN- CH0 CS_SEL[1:0] CH1 MUX[7:4] = 1110 ISINK Delta-Sigma ADC CH2 CH3 CH4 AGND CH5 CH6 CH7 AGND AVDD REFIN+ REFINTEMP Diode P TEMP Diode M VCM VIN- Analog Multiplexer AGND Analog Input Dual Multiplexer FIGURE 5-1: Simplified Analog Input Multiplexer Schematic.  2019-2021 Microchip Technology Inc. DS20006180D-page 31 MCP3461/2/4 The possible selections are described in Table 5-1 and can be set with the MUX[7:0] register during the MUX mode. The MUX[7:4] bits define the selection for the VIN+ (noninverting analog input of the ADC). The MUX[3:0] bits define the selection for the VIN- (inverting analog input of the ADC). TABLE 5-1: ANALOG INPUT MUX DECODING TABLE MUX[7:4] (VIN+) or MUX[3:0] (VIN-) Code Selected Channel 0000 CH0 0001 CH1 0010 CH2 Not Connected (NC) for MCP3461 0011 CH3 Not Connected (NC) for MCP3461 0100 CH4 Not Connected (NC) for MCP3461, MCP3462 0101 CH5 Not Connected (NC) for MCP3461, MCP3462 0110 CH6 Not Connected (NC) for MCP3461, MCP3462 0111 CH7 Not Connected (NC) for MCP3461, MCP3462 1000 AGND 1001 AVDD 1010 Reserved 1011 REFIN+ 1100 REFIN- 1101 TEMP Diode P 1110 TEMP Diode M 1111 Internal VCM Comment Do not use Internal Common-mode voltage for modulator biasing During SCAN mode, the two single-ended input multiplexers are automatically set to a certain position depending on the SCAN sequence and on which channel has been selected by the user. The SCAN sequence channels’ configuration corresponds to a certain code in the MUX[7:0] register, as defined in Table 5-14. In order to monitor the digital power supply (DVDD), it is necessary to externally connect DVDD to one of the CHn analog inputs, since DVDD is not one of the possible selections of the analog multiplexer. A similar setup can be implemented to monitor DGND if DGND is not connected externally to AGND. For MCP3461 and MCP3462, some codes are not available in the selection since the pins are not bonded out on these devices. These codes should then be avoided in the application, as the input they connect to is effectively a high-impedance node. The TEMP Diodes P and M are two internal diodes that are biased by a current source and that can be used to perform a temperature measurement. If TEMP Diode P is connected to VIN+ and TEMP Diode M to VIN-, then the ADC output code is a function of the temperature using Equation 5-1 (see Section 5.1.2 “Internal Temperature Sensor” for more details). DS20006180D-page 32 The “VCM” selection measures the internal Common-mode voltage source that biases the Sigma-Delta modulator (this voltage is not provided at any output of the part). The possible inputs of the analog multiplexer include not only the analog input channels, but also the REFIN+/- inputs, AVDD and AGND, as well as temperature sensor outputs and VCM internal Common-mode. This large selection offers many possibilities for measuring internal or external data resources of the system and can serve as diagnostic purposes to increase the security of the applications. Some monitor channels are already predefined in SCAN mode to further help users to integrate diagnostics to their applications (for example, the analog power supply or the temperature can be constantly monitored in SCAN mode; see Section 5.14.3 “SCAN Mode Internal Resource Channels” for more details of the different resources that can be monitored in SCAN mode).  2019-2021 Microchip Technology Inc. MCP3461/2/4 5.1.1 BURNOUT CURRENT SOURCES FOR SENSOR OPEN/SHORT DETECTION The ADC inputs, VIN-/VIN+, feature a selectable burnout current source that enables open or short-circuit detection, as well as biasing very low current external sensors. The bias current is sourced on the VIN+ pin of the ADC (noninverting output of the analog multiplexer) and sunk on the VIN- pin of the ADC (inverting output of the analog multiplexer). Since the same current flows at the VIN-/VIN+ pins of the ADC, it can sense the impedance of an externally connected sensor that would be connected between the selected inputs of the multiplexer. When the sensor is in short circuit, the ADC will convert signals that are close to 0V. When the sensor is an open circuit, the ADC will convert signals that are close to the AVDD voltage. The current source is an independent peripheral of the ADC. It does not need the ADC to be in Conversion mode to be present. Once enabled, the current source provides current even when the ADC is in Reset or ADC Shutdown modes. The current source can be configured at any time by programming the CS_SEL[1:0] bits in the CONFIG0 register (see Table 5-2). Since the amount of current selected can be very small, it may be necessary to diminish the MCLK master clock frequency to be able to reach full desired accuracy during conversions (the settling time of the input structure, including the sensor, can be large if the sensor is very resistive, which will limit the bandwidth of the Sample-and-Hold input circuit). The accuracy of the current sources is around ±20% and it is not controlled well internally. However, the mismatch between sink and source is typically around ±1%. This relatively low accuracy on the current is generally sufficient for open/short detection applications. 5.1.2 INTERNAL TEMPERATURE SENSOR The device includes an on-board temperature sensor that is made of two typical P-N junction diodes biased by fixed current sources (TEMP Diodes P and M). The TEMP Diode P has a current density of 4x of the TEMP Diode M. The difference in the current densities of the diodes yields a voltage, which is a function of the absolute temperature. Once the ADC inputs (VIN+/VIN-) are connected to the temperature sensor diodes (MUX[7:0] = 0xDE), the ADC will see a VIN differential input that is the function of the temperature. The transfer function of the temperature sensor can be approximated by a linear equation or a third-order equation for more accuracy. When the internal temperature sensor is selected for the MUX or SCAN input, the input sink/source current source controlled by the CS_SEL[1:0] bits (see Section 5.1 “Analog Input Multiplexer”) is disabled internally (even though the CS_SEL[1:0] bits are not modified by the temperature sensor selection). In this case, the input current source is replaced by a specific internal current source that will only be sourced to the diode temperature sensor (see Figure 5-1). The bias current of the diodes is not calibrated internally and can lead to a relatively large gain and offset error in the transfer function of the temperature sensor. Typical graphs showing the typical error in the temperature measurement are provided in Section 2.0 “Typical Performance Curves” (see Figure 2-32 first-order and Figure 2-33 for third-order fitting). The accuracy can also be optimized by using proper digital gain and offset error calibration schemes. Figure 2-35 shows how the ADC output code is varying when the burnout current sources are enabled (with GAIN = 1x) and the input sensor impedance is swept with a large dynamic range. This permits the users to use the ADC as an open/short detection circuit that is practical when manufacturing complex remote sensor systems. TABLE 5-2: BURNOUT CURRENT SOURCE SETTINGS CS_SEL[1:0] (Source/Sink) Burnout Current Amplitude 00 0 µA 01 0.9 µA 10 3.7 µA 11 15 µA  2019-2021 Microchip Technology Inc. DS20006180D-page 33 MCP3461/2/4 EQUATION 5-1: TEMPERATURE SENSOR TRANSFER FUNCTION First-order (linear) fitting: GAIN = 1, VREF = 3.3V TEMP (  C) = 0.00133  ADCDATA (LSb) – 267.146 V IN  mV  = 0.2964  TEMP (  C) + 79.32 Third-order fitting: GAIN = 1, VREF = 3.3V TEMP (  C  = – 3.904  10 – 15 V IN (mV) = 4.727  10 5.1.3 3  ADCDATA (LSb) + 3.814  10 –7 3 –9  TEMP (  C  – 2.51288  10 –4 ADC OFFSET CANCELLATION ALGORITHM The input multiplexer and the ADC include an offset cancellation algorithm that cancels the offset contribution of the ADC. This offset cancellation algorithm is controlled by the AZ_MUX bit in the CONFIG2 register. When AZ_MUX = 0 (default), the offset cancellation algorithm is disabled and the conversions are not affected by this EQUATION 5-2: 2  ADCDATA (LSb) + 0.0002  ADCDATA (LSb) – 163.978 2  T EMP (  C  + 0.31294  TEMP (  C  + 79.547 setting. When AZ_MUX = 1, the algorithm is enabled. When the offset cancellation algorithm is enabled, ADC takes two conversions, one with the differential input as VIN+/VIN-, one with VIN+/VIN- inverted. Equation 5-2 calculates the ADC output code. When AZ_MUX = 1, the Conversion Time, TCONV, is multiplied by two, compared to the default case, where AZ_MUX = 0. AZ_MUX CONVERSION RESULT  ADC Output at +V IN  –  ADC Output at -V IN  ADC Output Code (AZ_MUX=1) = ------------------------------------------------------------------------------------------------------------------2 This technique allows the cancellation of the ADC offset error and the achievement of ultra-low offset without any digital calibration. The resulting offset is the residue of the difference of the two conversions, which is on the same order of magnitude as the noise floor. This offset is effectively canceled at every conversion, so the residual offset error temperature drift is extremely low. DS20006180D-page 34 For One-Shot mode, the conversion time is simply multiplied by two. Enabling the AZ_MUX bit is not compatible with the Continuous Conversion mode (because it effectively multiplexes the inputs in between each conversion). If AZ_MUX = 1 and CONV_MODE = 11 (Continuous Conversion mode), the device will reset the digital filter in between each conversion and will therefore have an output data rate of 1/(2 * TCONV). The Continuous mode is replaced by a series of One-Shot mode conversions with no delay in between each conversion (see Section 5.13 “Conversion Modes” and Figure 5-5 for more details about the Conversion modes).  2019-2021 Microchip Technology Inc. MCP3461/2/4 5.2 Input Impedance This anti-aliasing filter can be a simple first-order RC network with low time constant that will provide a high rejection at DMCLK frequency (see Figure 5.6 for more details). The RC network usually uses small R and large C to avoid additional offset due to IR drop in the signal path. This anti-aliasing filter will induce a small systematic gain error on the AC input signals that can be compensated in the digital section with the Digital Gain Error Calibration register (GAINCAL). The ADC inputs (VIN-/VIN+) are directly tied to the analog multiplexer outputs and are not routed to external pins. The multiplexer input stage contribution to the input impedance is negligible. The conversion accuracy can be affected by the input signal source impedance when any external circuit is connected to the input pins. The source impedance adds to the internal impedance and directly affects the time required to charge the internal sampling capacitor. Therefore, a large input source impedance connected to the input pins can increase the system performance errors, such as offset, gain and Integral Nonlinearity (INL). Ideally, the input source impedance should be near zero. This can be achievable by using an operational amplifier with a closed-loop output impedance of tens of ohms. 5.3 The gain of the converter is programmable and controlled by the GAIN[2:0] bits in the CONFIG2 register. The ADC programmable gain is divided in two gain stages: one in the analog domain, one in the digital domain as per Table 5-3. After the multiplexer, the analog input signals are routed to the Delta-Sigma ADC inputs and are amplified by the analog gain stage (see Section 5.3.1 “Analog Gain” for more details). The digital gain stage is placed inside the digital decimation filter (see Section 5.3.2 “Digital Gain” for more details). A proper anti-aliasing filter must be placed at the ADC inputs. This will attenuate the frequency contents around DMCLK and keep the desired accuracy over the baseband (DRCLK) of the converter. TABLE 5-3: ADC Programmable Gain SIGMA-DELTA ADC GAIN SETTINGS GAIN[2:0] Total Gain (V/V) Analog Gain (V/V) Digital Gain (V/V) Total Gain (dB) 0 0 0 0.333 0.333 1 -9.5 0 0 1 1 1 1 0 VIN Range (V) ±Min (AVDD, 3 * VREF) ±VREF 0 1 0 2 2 1 6 ±VREF/2 0 1 1 4 4 1 12 ±VREF/4 1 0 0 8 8 1 18 ±VREF/8 1 0 1 16 16 1 24 ±VREF/16 1 1 0 32 16 2 30 ±VREF/32 1 1 1 64 16 4 36 ±VREF/64 5.3.1 ANALOG GAIN The gain settings, from 0.33x to 16x, are done in the analog domain. This analog gain is placed on each ADC differential input. Each doubling of the gain improves the thermal noise due to sampling by approximately 3 dB, which means the lowest noise configuration is obtained when using the highest analog gain. The SNR, however, is degraded since doubling the gain factor reduces the maximum allowable input signal amplitude by approximately 6 dB.  2019-2021 Microchip Technology Inc. If the gain is set to 0.33x, the differential input range becomes theoretically ±3 * VREF; however, the device does not support input voltages outside of the power supply voltage range. If large reference voltages are used with this gain, the input voltage range will be clipped between AGND and AVDD, and therefore, the output code span will be limited. This gain is useful when the reference voltage is small and when the input signal voltage is large. The analog gain stage can be used to amplify very low signals, but the differential input range of the Delta-Sigma modulator must not be exceeded. DS20006180D-page 35 MCP3461/2/4 5.3.2 5.4.2 DIGITAL GAIN When the gain setting is chosen from 16x to 64x, the analog gain stays constant at 16x and the additional gain is done in the digital domain by a simple shift and round of the output code. The digital gain range is 1x to 4x. The output noise is approximately unchanged (outside from the quantization noise that is slightly decreased). The SNR is thus degraded by 6 dB per octave from the 16x to 64x setting. This digital gain is useful to scale-up the signals without using the host device (MCU) operations, but they degrade SNR and resolution (1 bit per octave) and do not significantly improve the noise performance, except for very large OSR settings. 5.4 Delta-Sigma Modulator 5.4.1 ARCHITECTURE The Sigma-Delta ADC includes a second-order modulator with a multibit DAC architecture. Its 5-level quantizer is a Flash ADC composed of four comparators with equally spaced thresholds and a thermometer output coding. The proprietary 5-level architecture ensures minimum quantization noise at the outputs of the modulators without disturbing linearity or inducing additional distortion. Unlike most multibit DAC architectures, the 5-level DAC used in this architecture is inherently linear, and therefore, does not degrade the ADC linearity and THD performance. The sampling frequency is DMCLK; therefore, the modulator outputs are refreshed at a DMCLK rate. Figure 5-2 represents a simplified block diagram of the Delta-Sigma modulator. Delta-Sigma 2nd Order 5-Level Modulator Quantizer Differential Input Voltage (from Analog Mux) Analog 2nd Order Loop Filter 4 5-Level Flash ADC Output Bitstream Thermometer Coding (to Digital Filter) 5-Level DAC Analog FIGURE 5-2: Block Diagram. DS20006180D-page 36 Digital Simplified Delta-Sigma ADC MODULATOR OUTPUT BLOCK The modulator output option allows users to apply their own digital filtering on the output bit stream. By setting IRQ_MODE[1] = 1 in the IRQ register, the modulator output is available at the IRQ/MDAT pin, at the AMCLK rate and through the ADCDATA register (0x0) with DMCLK rate. With this configuration, the digital decimation filter is disabled in order to reduce the current consumption and no data ready interrupt is generated on any of the IRQ mechanisms. The IRQ/MDAT pin is never placed in high-impedance during the Modulator Output mode. Since the Delta-Sigma modulator has a 5-level output given by the state of four comparators with thermometer coding, the output is represented using four bits, each bit represents the state of the corresponding comparator (see Table 5-4). The comparator output bits are arranged serially at the AMCLK rate on the IRQ/MDAT output pin (see Figure 5-3). This 1-bit serial bit stream is considered to be the same one as it is produced by a 1-bit DAC modulator with a sampling frequency of AMCLK. The modulator can either be considered as a 5 level-output at DMCLK rate or as 1-bit output at AMCLK rate. These two representations are interchangeable. The MDAT outputs can therefore be used in any application that requires 1-bit modulator outputs. This application can be integrated with an external sinc filter or more advanced decimation filters that are computed in the MCU or DSP device. When CLK_SEL[1:0] = 11 (internal oscillator with external clock output), the AMCLK clock is present on the MCLK pin. This configuration permits correctly synchronizing the bit stream when the internal oscillator is used as the master clock source. When CLK_SEL[1:0] = 00, the modulator outputs are also synchronized with the MCLK input, but the ratio between MCLK and AMCLK needs to be taken into account in the user applications to correctly retrieve the desired bit stream. The default value of the bit stream after a Reset or a power-up is ‘0011’. It is equivalent to a 0V input for the ADC. After each ADC Reset and restart (see Section 5.15 “A/D Conversions Automatic Reset and Restart Feature”), the bit stream output is also reset and restarted and the IRQ/MDAT is kept equal to logic high during the two MCLK clock periods needed for the synchronization. After these two clock periods, the bit stream will be provided on the IRQ/MDAT pin and the first value will be the default value.  2019-2021 Microchip Technology Inc. MCP3461/2/4 TABLE 5-4: DELTA-SIGMA MODULATOR OUTPUT BIT STREAM CODING COMP[3:0] Code Modulator Output Code (Decimal) MDAT Serial Stream Equivalent VREF Voltage 1111 +2 1111 +VREF 0111 +1 0111 +VREF/2 0011 0 0011 0 0001 -1 0001 -VREF/2 0000 -2 0000 -VREF tD OMD AT tD OMD AT tD OMD AT tD OMD AT tD OMD AT AMCLK 5.4.3 BOOST MODES The Delta-Sigma modulator includes a programmable biasing circuit in order to further adjust the power consumption to the sampling speed applied through the MCLK. This can be programmed through the BOOST[1:0] bits in the CONFIG2 register. The different BOOST settings are applied to the whole modulator circuit, including the voltage reference buffers. The settings of the BOOST[1:0] bits are described in Table 5-5. TABLE 5-5: BOOST SETTINGS DESCRIPTION BOOST[1:0] Bias Current 00 x0.5 01 x0.66 10 x1 (default) 11 x2 The maximum achievable Analog Master Clock (AMCLK) speed, the maximum sampling frequency (DMCLK) and the maximum achievable data rate (DRCLK) are highly dependent on the BOOST[1:0] and GAIN[2:0] settings. A higher BOOST setting will allow the circuits’ bandwidth to be increased and will allow a higher analog master clock rate that will then increase the baseband of the input signals to be converted. The digital gain (that is enabled at 32x and 64x gains) has no influence on the achievable bandwidth. MDAT (code = +2) MDAT (code = +1) MDAT (code = 0) A typical dependency of the bandwidth in relation to the GAIN for each BOOST setting combination is shown in Figure 2-20 to Figure 2-23. Typically, a larger GAIN setting requires a higher BOOST setting in order to achieve the same bandwidth performance. MDAT (code = -1) Figure 2-24 shows the behavior of the achievable bandwidth at BOOST = 1x with AVDD corner cases. Since the BOOST settings vary, the internal slew rate of the modulator components using a lower VREF value will improve the bandwidth if low BOOST settings are used and are showing a limited bandwidth behavior. MDAT (code = -2) C OMP[3] C OMP[2] C OMP[1] C OMP[0] FIGURE 5-3: MDAT Serial Outputs in Function of the Modulator Output Code.  2019-2021 Microchip Technology Inc. DS20006180D-page 37 MCP3461/2/4 5.5 Digital Decimation Filter The decimation filter decimates the output bit stream of the modulator to produce 16-bit ADC output data. The decimation filter present in the device is a cascade of two filters: a third-order sinc filter with a decimation ratio of OSR3 (third-order moving an average of 3 x OSR3 values), followed by a first-order sinc filter with a decimation ratio of OSR1 (moving an average of OSR values (third-order moving an average of 3 x OSR3 values). Figure 5-6 represents the decimation filter architecture. OSR 1 = 1 Modulator Output (Thermometer Coding) SINC 3 SINC 1 4 OSR 3 OSR 1 Decimation Filter Output ADC Resolution Decimation Filter FIGURE 5-4: Diagram. Decimation Filter Block The following equation is the transfer function of the decimation filter: EQUATION 5-3: FILTER TRANSFER FUNCTION -OSR 3 3 -OSR 1  OSR 3 1 – z  1 – z      H  z  = ---------------------------------------------  ----------------------------------------------------3 – 1 – OSR  OSR  1 – z   3 3 OSR  1 – z  1 Where: 2  fj z = exp  ----------------------  DMCLK The resolution (number of possible output codes expressed in powers of two or in bits) of the digital filter is 16-bit maximum for any OSR (OSR3 x OSR1) and data format choice. The resolution depends only on the OSR through the OSR[3:0] settings in the CONFIG1 per Table 5-6. Once the OSR is chosen, the resolution is fixed and the output code of the ADC is encoded with the data format defined by the DATA_FORMAT[1:0] setting in the CONFIG3 register. DS20006180D-page 38 The transfer function of this filter has a unity gain at each multiple of DMCLK. A proper anti-aliasing filter must be placed at the ADC inputs. This will attenuate the frequency contents around each multiple of DMCLK and keep the desired accuracy over the baseband of the converter. This anti-aliasing filter can be a simple first-order RC network with low time constant to provide a high rejection at DMCLK frequency. The conversion time is a function of the OSR settings with the DMCLK frequency: EQUATION 5-4: CONVERSION TIME FOR OSR = OSR3 x OSR1  3  OSR 3 +  OSR 1 – 1   OSR 3  T CONV = ----------------------------------------------------------------------------------DMCLK In One-Shot mode, each conversion is launched individually, so the maximum data rate is effectively 1/TCONV if each conversion is launched with no delay. The digital filter is reset in between each conversion. However, due to the nature of the digital filter (which memorizes the sum of the incoming bit stream), the data rate at the filter output can be maximized if the filter is never reset. Because of the internal resampling of the digital filter, the output data rate can be equal to DMCLK/OSR = DRCLK; this is the case in Continuous mode. In this case, the first conversion still happens in the TCONV time, as this is the settling time of the filter. The subsequent conversions are pipelined and give their output at a data rate of DRCLK. The Continuous Conversion mode can optimize the data rate while consuming the same power as One-Shot mode, which is advantageous in applications that require a continuous sampling of the analog inputs. The Continuous mode is not compatible with multiplexing the inputs (see Section 5.14 “SCAN Mode” for more details about the Conversion mode settings in MUX and SCAN modes). Figure 5-5 shows the fundamental difference between One-Shot mode and Continuous mode in a simplified diagram.  2019-2021 Microchip Technology Inc. MCP3461/2/4 Analog Input Signal One-Shot mode Conversions are Serialized, IRQ Filter is Reset After Each ADC Conversion Status Group Delay = TCONV Data Rate: 1/(TCONV) Conversion1 Conversion2 Conversion3 TCONV TCONV TCONV IRQ ADC Continuous mode Status Conversions are Pipelined, Filter is Never Reset Group Delay : TCONV Data Rate: DRCLK Conversion1 TCONV = Settling Time 1/DRCLK Conversion2 TCONV Conversion3 TCONV FIGURE 5-5: One-Shot Mode vs. Continuous Mode. Since the converter is effectively doing two conversions when the AZ_MUX bit is enabled, the conversion time is equal to 2 x TCONV in this mode. As described in Section 5.1.3 “ADC Offset Cancellation Algorithm”, this selection is not compatible with the Continuous Conversion mode, therefore, the output data rate is equal to 1/(2 x TCONV) in this mode. When OSR is larger than 20480 for typical master clock frequency, MCLK = 4.9152 MHz, the device includes an additional 50/60 Hz rejection by aligning decimation filter notches with a multiple of 50 or 60 Hz depending on the OSR setting. The rejection band depends strongly on the master clock accuracy and corresponds to a first-order decimation filter rejection rate. Table 5-6 summarizes the possible filter settings and their associated Conversion Time, TCONV, as well as their output data rate (DRCLK) in Continuous mode. The high OSR settings can be used for applications requiring very low noise and slow data rates.  2019-2021 Microchip Technology Inc. Figure 5-6 shows the frequency response of the decimation filter with default settings. Figure 5-7 represents the frequency response of the filter with the highest OSR settings and a line rejection at 60 Hz. DS20006180D-page 39 MCP3461/2/4 TABLE 5-6: OVERSAMPLING RATIO AND SINC FILTER RELATIONSHIP ADC Resolution Total in Bits OSR[3:0] OSR3 OSR1 OSR (No Missing Codes) Conversion Time (TCONV) Data Rate in Continuous Conversion Mode Data Rate (Hz) Fastest Data Rate (Hz) with MCLK = 4.9152 MHz with MCLK = 19.6608 MHz 0 0 0 0 32 1 32 16 96/DMCLK 38400 153600 0 0 0 1 64 1 64 16 192/DMCLK 19200 76800 0 0 1 0 128 1 128 16 384/DMCLK 9600 38400 0 0 1 1 256 1 256 16 768/DMCLK 4800 19200 0 1 0 0 512 1 512 16 1536/DMCLK 2400 9600 0 1 0 1 512 2 1024 16 2048/DMCLK 1200 4800 0 1 1 0 512 4 2048 16 3072/DMCLK 600 2400 0 1 1 1 512 8 4096 16 5120/DMCLK 300 1200 1 0 0 0 512 16 8192 16 9216/DMCLK 150 600 1 0 0 1 512 32 16384 16 17408/DMCLK 75 300 1 0 1 0 512 40 20480 16 21504/DMCLK 60 240 1 0 1 1 512 48 24576 16 25600/DMCLK 50 200 1 1 0 0 512 80 40960 16 41984/DMCLK 30 120 1 1 0 1 512 96 49152 16 50176/DMCLK 25 100 1 1 1 0 512 160 81920 16 82944/DMCLK 15 60 1 1 1 1 512 192 98304 16 99328/DMCLK 12.5 50 DS20006180D-page 40  2019-2021 Microchip Technology Inc. MCP3461/2/4 FIGURE 5-6: Decimation Filter Frequency Response (OSR = 256, PRE = 1:1, MCLK = 4.9152 MHz). FIGURE 5-7: Decimation Filter Frequency Response (OSR = 81920, PRE = 1:1, MCLK = 4.9152 MHz).  2019-2021 Microchip Technology Inc. DS20006180D-page 41 MCP3461/2/4 5.6 ADC Output Data Format The ADC Output Data register (ADCDATA) is located at the address: 0x0. The default length of the register is 16-bit (15-bit + SIGN). Output data are calculated in the digital decimation filter with a larger resolution and are rounded to the closest LSb value. EQUATION 5-5: The rounding ensures a maximum 1/2 LSb error instead of a simple truncation that ensures a 1 LSb maximum error. Equation 5-5 calculates ADC output code as a function of the input and reference signals for DC inputs. ADC OUTPUT CODE FOR DC INPUT (DATA_FORMAT[1:0] = 00)  V IN+ – V IN-  ADC_OUTPUT(LSb) =  -----------------------------------------  32768  GAIN  V REF+ – V REF- For AC sine wave inputs, the decimation filter transfer function (see Equation 5-3) induces an additional gain on the ADC output code, which depends on the input frequency (roll-off of the decimation filter). For any inputs, the VIN+/VIN- voltages are averaged out during the whole conversion time, since the ADC is an oversampling converter. The ADC output format is set by the DATA_FORMAT[1:0] bits in the CONFIG3 register. These bits define four different possible formats for the ADC Data Output register: three 32-bit formats and one 16-bit format for MCP3461/2/4. All possible data formats are described in Figure 5-8. DATA_FORMAT[1:0] 00 SGN + DATA[14:0] 01 SGN + DATA[14:0] 0x0000 10 SGN ext (16-bit) DATA[15:0] 11 CH_ID[3:0] FIGURE 5-8: SGN ext (12-bit) ADC Output Format Selection. When DATA_FORMAT[1:0] = 0x, the ADC resolution is 16-bit. The ADC output code is represented with MSb first, signed two’s complement coding. With these two data formats, the coding does not allow overrange; the equivalent analog input range is [-VREF; +VREF – 1 LSb]. When VIN * Gain > VREF – 1 LSb, the 16-bit ADC code (SGN + DATA[14:0]) will saturate and be locked at 0x7FFF. When VIN * Gain < -VREF, the 16-bit ADC code will saturate and be locked at 0x8000. Using these data formats does not permit correctly evaluating full-scale errors in case of a positive full-scale error. DS20006180D-page 42 DATA[15:0] When DATA_FORMAT[1:0 = 00, the output register shows only the 16-bit value. When DATA_FORMAT[1:0] = 01, the output register is 32 bits long and the output code is padded with additional zeros on the last two bytes. The output code is left justified in this case. This format is useful for 32-bit MCU applications.  2019-2021 Microchip Technology Inc. MCP3461/2/4 When DATA_FORMAT[1:0] = 1x, the ADC data are represented on 17 bits. For these two data formats, the output register is 32 bits long. With these two data formats, the coding allows overrange; the equivalent analog input range is [-2 * VREF; +2 * VREF – 1 LSb]. When VIN * Gain > 2 VREF – 1 LSb, the 17-bit ADC code (SIGN + DATA[15:0]) saturates and locks at 0x0FFFF. When VIN * Gain < -2 VREF, the 17-bit ADC code will saturate and be locked at 0x10000. Using these data formats allows a correct evaluation of the full-scale errors in case of a positive full-scale error, since they allow inputs that can be greater than VREF or less than -VREF. The ADC accuracy is not maintained on the full extended [-2 * VREF; +2 * VREF – 1 LSb] range, but only on a smaller range, which is approximately equal to ±1.05 * VREF. This overrange can be useful in high-side measurements and gain error cancellation algorithms. The overrange-capable formatting on 17 bits is fully compatible with the standard code locked formatting on 16 bits: both coding formats produce the same 16-bit TABLE 5-7: codes for the [-VREF; +VREF – 1 LSb] range and the MSb on the 17-bit coding can be considered as a simple Sign bit extension. When DATA_FORMAT[1:0] = 10, the 17-bit (16-bit plus SGN) value is right justified. The first two bytes of the 32-bit ADC output code will repeat the Sign bit (SGN). In DATA_FORMAT[1:0] = 11, the output code is similar to the DATA_FORMAT[1:0] = 10. The only difference resides in the four MSbs of the first byte, which are no longer repeats of the Sign bit (SGN). They are the Channel ID data (CH_ID[3:0]) that are defined in Table 5-14. This CH_ID[3:0] word can be used to verify that the right channel has been converted in SCAN mode, and can serve easy data retrieval and logging (see Section 5.14 “SCAN Mode” for more details about the SCAN mode). In MUX mode, this 4-bit word is defaulted to ‘0000’ and does not vary with the MUX[7:0] selection. This format is useful for 32-bit MCU applications. DATA_FORMAT[1:0] = 0x (16-BIT CODING) Equivalent Input Voltage ADC Output Code (SGN + DATA[14:0]) Hexadecimal Decimal > VREF – 1 LSb 0111111111111111 0x7FFF +32767 VREF – 2 LSbs 0111111111111110 0x7FFE +32766 1 LSb 0000000000000001 0x0001 +1 0 0000000000000000 0x0000 0 -1 LSb -1 1111111111111111 0xFFFF -VREF + 1 LSb 1000000000000001 0xFFFF -32767 < -VREF 1000000000000000 0x8000 -32768 TABLE 5-8: DATA_FORMAT[1:0] = 1x (17-BIT CODING) Equivalent Input Voltage ADC Output Code (SGN + DATA[15:0]) Hexadecimal Decimal > 2 VREF – 1 LSb 01111111111111111 0x0FFFF +65535 2 VREF – 2 LSbs 01111111111111110 0x0FFFE +65534 VREF + 1 LSb 01000000000000001 0x08001 +32769 VREF 01000000000000000 0x08000 +32768 VREF – 1 LSb 00111111111111111 0x07FFF +32767 VREF – 2 LSbs 00111111111111110 0x07FFE +32766 1 LSb 00000000000000001 0x00001 +1 0 00000000000000000 0x00000 0 -1 LSb 11111111111111111 0x1FFFF -1 -VREF + 1 LSb 11000000000000001 0x18001 -32767 -VREF 11000000000000000 0x18000 -32768 -VREF – 1 LSb 10111111111111111 0x17FFF -32769 -2 VREF – 1 LSb 10000000000000001 0x10001 -65535 < -2 VREF 10000000000000000 0x10000 -65536  2019-2021 Microchip Technology Inc. DS20006180D-page 43 MCP3461/2/4 5.7 Power-on Reset During Full Shutdown mode, the power supply voltages are not monitored to be able to reach ultra-low power consumption. The device cannot generate a POR event interrupt in this mode, except in cases of extremely low-power supply voltages. The analog and digital power supplies are monitored separately by two Power-on-Reset (POR) monitoring circuits at all times, except during Full Shutdown mode (see Section 5.9 “Low-Power Shutdown Modes”). The DVDD and AVDD monitoring thresholds are different since their respective voltage ranges are different. The AVDD rising threshold is approximately 1.75V, ±10% and the DVDD is 1.2V, ±10%. The hysteresis is approximately 150 mV (typical). Proper decoupling ceramic capacitors (0.1 µF and 10 µF ceramic) should be placed as close as possible to the power supply pins (AVDD, DVDD), to provide additional transient immunity. Each POR circuit has two separate thresholds, one for the rising voltage supply and one for the falling voltage supply. They both include hysteresis (the rising threshold is superior to the falling threshold), so that the device is tolerant to a certain degree of transient noise on each power supply. If any of the two power supply voltages is below its respective threshold, the POR state is forced internally. In this state, the SPI interface is disabled and no command can be executed by the chip. All registers are cleared and set to their default values. In order to ensure a proper power-up sequence, the ramp rate of DVDD should not exceed 3V/µs when coming out of the POR state. At power-up, when both power supply voltages are above the rising thresholds, the device powers up and the SPI interface is enabled and can handle communications. Since both thresholds need to be crossed for the power-up, the power-up sequence is not important and any power supply voltage can ramp up first. The detection time for the monitoring circuits (tPOR) is about 1 µs for relatively fast power-up ramp rates. The normal operation is stopped when any of the falling thresholds of the two POR monitoring circuits are crossed. Figure 5-9 illustrates the power-up and power-down sequences. Additionally, the user needs to lower the DVDD residual voltage as much as possible, close to 0V, when the device is kept for a long time in a POR state (below DVDD POR threshold) in order to ensure a proper power-up sequence. The user can verify if the power-up sequence has been correctly performed by reading the default state of all the registers in the register map, just after powering up the device. If one or more of the registers do not show the proper default setting, a new power-up cycle should be launched to recover from this condition. If the CS pin is kept logic low during a POR state, a logic high pulse is necessary to start the first communication sequence. The CS rising edge will properly reset the SPI interface and the falling edge will clear the POR interrupt on the IRQ pin (see Figure 6-16). Voltage (AVDD, DVDD) POR Threshold Up POR Threshold Down tPOR Time POR State FIGURE 5-9: DS20006180D-page 44 Normal Operation POR State Power-on Reset Timing Diagram.  2019-2021 Microchip Technology Inc. MCP3461/2/4 5.8 ADC Operating Modes The ADC can be placed into three different operating modes: ADC Shutdown, Standby and Conversion. The ADC operating mode is controlled directly by the user using the ADC_MODE[1:0] bits in the CONFIG0 register. The user can directly launch conversions or place the ADC into ADC Shutdown or Standby mode by writing directly to these bits. Additional Fast commands are available for each of the three possible states of these bits to allow faster programming in case of time-sensitive applications (see Section 6.2.4 “Command-Type Bits (CMD[1:0])”). The different ADC_MODE[1:0] bits settings available are described in Table 5-9. The ADC_MODE[1:0] bits do not give an instantaneous representation of the state of the ADC. Writing the ADC_MODE[1:0] bits sets the desired state of the ADC, but this state is only attained after a start-up time depending on the current state of the ADC. See Section 5.10 “ADC Start-up Timer” for details about the start-up timer. Typically, the device starts in ADC Shutdown mode after a POR (ADC_MODE[1:0] = 00 by default). To launch conversions in the desired configuration, the user should program the part in the desired configuration and then set the ADC_MODE[1:0] bits to ‘11’. In this case, the first conversion will start after TADC_SETUP = 256 DMCLK periods. This time is necessary for the part to adjust to the new programmed settings and settle in to its operating point to accurately convert the input signals. Internally, the device tracks the current state of the ADC, as well as the start-up timer counter to be able to optimize the start-up time, depending on the desired transitions and internal configurations required and set by the user. TABLE 5-9: In MUX mode, overwriting the ADC_MODE[1:0] bits to ‘11’ when the ADC is already in conversion, resets and restarts the current conversion immediately. The conversion start pulse will also be regenerated in this case if the EN_STP bit was enabled. In SCAN mode (see Section 5.14 “SCAN Mode”), writing the ADC_MODE[1:0] bits to ‘11’ starts the conversion SCAN cycle. During the whole cycle, even when the scan timer is enabled, reading the ADC_MODE[1:0] bits will give a ‘11’ code output, meaning that the SCAN cycle is ongoing. Rewriting ADC_MODE[1:0] = 11 during SCAN mode will immediately reset and restart the whole SCAN sequence, from the beginning of the sequence. The conversion start pulse will also be regenerated in this case if the EN_STP bit was enabled. The restart of the SCAN sequence may induce a TADC_SETUP additional delay if the ADC was effectively in ADC Shutdown mode when the ADC_MODE bits are overwritten (this can happen if the ADC_MODE bits are overwritten during the timer delay period, where the ADC is placed into ADC Shutdown mode in between two SCAN cycles). The ADCDATA register is always updated with the last conversion results only. The ADCDATA register cannot provide incomplete conversion results. The A/D conversion needs to be completed to be able to provide a result in the ADCDATA register. Each end of conversion generates a data ready interrupt on all three IRQ mechanisms (see Section 6.8.1 “Conversion Data Ready Interrupt”). The ADCDATA register is never cleared when the device transitions from one mode to another. The only way to clear the ADC Output register is a POR event or a full Reset Fast command. See Section 6.2.5 “Fast Commands Description”. ADC OPERATING MODES DESCRIPTION ADC_MODE[1:0] ADC Mode Description 11 Conversion The ADC is placed into Conversion mode and consumes the specified current (see the Electrical Characteristics table). A/D conversions can be reset and restarted immediately once this mode is effectively reached. This mode may be reached after a maximum of TADC_SETUP time, depending on the current state of the ADC. 10 Standby 0x Conversions are stopped. ADC is placed into Reset but consumes almost as much current as in Conversion mode. A/D conversions can start immediately once this mode is effectively reached. This mode may be reached after a maximum of TADC_SETUP time, depending of the current state of the ADC. ADC Shutdown Conversions are stopped. ADC is placed into ADC Shutdown mode consuming no current. A/D conversions can start only after TADC_SETUP start-up time. This mode is effective immediately after being programmed.  2019-2021 Microchip Technology Inc. DS20006180D-page 45 MCP3461/2/4 5.9 Low-Power Shutdown Modes The Full Shutdown mode stops all internal timers and resets them. Sending a Fast CMD to change the operating mode exits the Full Shutdown mode. The device incorporates two low-power modes that can be activated in order to limit power consumption of the device when ADC is not used. These two modes are called Partial Shutdown and Full Shutdown modes. 5.9.1 The user should place all digital inputs to a static value (logic low or high) in order to optimize power consumption during Full Shutdown mode. The current consumption specifications during Full Shutdown mode are intended without any digital pin toggling during the measurement. In this case, only leakage current is consumed throughout the device and this current varies exponentially with respect to absolute temperature. FULL SHUTDOWN MODE The Full Shutdown mode can be enabled by two means: • Writing CONFIG0 to ‘0x00’ • Sending a Fast Command Full Shutdown (Fast Command code: ‘1101’) 5.9.2 Full Shutdown mode is the lowest power mode of the device. None of the circuits consuming static power are active in this mode. Partial Shutdown mode is achieved when CONFIG0 is set to ‘xx000000’ where ‘xx’ is not equal to ‘00’ (CONFIG0 = 0x00 puts the device in Full Shutdown mode). In this mode, most of the internal circuits are shut down, with the exception of the POR monitoring and internal biasing circuits. During the Partial Shutdown mode, the power supply is continuously monitored, whereas in Full Shutdown mode, the POR monitoring circuits are powered down. The power consumption is also much higher in Partial Shutdown mode due to different biases and the POR monitoring circuits being active. Partial Shutdown mode allows the device to be restarted and put back in Conversion mode faster than Full Shutdown mode. Table 5-10 describes the differences between Partial and Full Shutdown modes. If the current consumption of Partial Shutdown mode is acceptable for the application, it is recommended that it is used as an alternative to Full Shutdown mode, where the POR monitoring circuits are shut down, and no longer monitoring the AVDD and DVDD power supplies. As stated in Section 5.7 “Power-on Reset”, the AVDD/DVDD POR monitoring circuits are not active while in Full Shutdown mode. For this reason, the Full Shutdown mode is not recommended for applications where an AVDD/DVDD power-down (whether expected or unexpected) voltage level of 100 mV (approx.) or less cannot be ensured before reapplying power. The part can still be accessed through the SPI interface during this mode and will accept incoming SPI commands. The ADCDATA register is not cleared during Full Shutdown mode and still holds previous conversion results. The other Configuration register settings are not modified or reset due to entering in Full Shutdown mode. When the ADC_MODE[1:0] bits are temporarily set internally to ‘00’, during SCAN mode, in between SCAN cycles, the part does not go into Full Shutdown mode, even if all the other bits in the CONFIG0 register are set to ‘0’. TABLE 5-10: PARTIAL SHUTDOWN MODE LOW-POWER MODES(1) Device CONFIG0[7:6] CLK_SEL[1:0] CS_SEL[1:0] ADC_MODE[1:0] Low-Power Mode Description Partial-Shutdown 11 00 00 0x All peripherals, except the POR monitoring and clock biasing circuits, are shut down and consume no static current. The SPI interface remains active in this mode and consumes no current while the bus is Idle. Full-Shutdown 00 00 00 0x All analog and digital circuits are shut down and consume no static current. The SPI interface remains active in this mode and consumes no current while the bus is Idle. Note 1: x = Don’t Care DS20006180D-page 46  2019-2021 Microchip Technology Inc. MCP3461/2/4 5.10 ADC Start-up Timer The device includes an intelligent start-up timer circuit for the ADC, which ensures that the ADC is properly biased and that internal nodes are properly settled before each conversion. This timer ensures the proper conditions for the ADC to convert with its full accuracy for each conversion. The ADC can operate in three different modes: ADC Shutdown, Standby and Conversion, as described in Section 5.8 “ADC Operating Modes”. The ADC start-up timer manages the time for the transitions between each mode. These transitions can be instantaneous or can take a maximum of 256 DMCLK periods, depending on the type of transition and the current status of the ADC and of the internal start-up timer. The timer will always try to reduce the transition time from one state to another, but will also allow enough time for the internal circuitry to settle to the proper internal operating points. The transitions from Standby or Conversion mode to ADC Shutdown mode are always immediate. They reset the internal start-up timer to 256 DMCLK periods (TADC_SETUP). The transitions from ADC Shutdown to Standby or Conversion mode start the internal start-up timer that decrements from 256 to 0. The timer only decrements after a small delay of two MCLK periods in case of a transition caused by an SPI command. This small delay is necessary to overcome any possible synchronization issues between the two asynchronous clocks, MCLK and SCK. The timer will immediately decrement (without the synchronization delay) if the transitions are generated by the internal state machine (for example, when the transitions are generated by the SCAN sequence). Once the timer reaches 0 (when the user has clocked 256 DMCLK periods), the device reaches its internal proper operating points and will either stay in Standby mode (if ADC_MODE[1:0] = 10) or start the Conversion mode (if ADC_MODE[1:0] = 11). The transition from Standby to Conversion mode and vice versa is immediate once the timer has reached 0 (if ADC_MODE[1:0] = 11). If the transition from Standby to Conversion mode occurs, and if the timer has not yet reached 0, the timer will continue to decrement to 0 TABLE 5-11: before effectively starting the conversion. The timer cannot decrement faster than 256 DMCLK periods when the ADC transitions from ADC Shutdown mode to Conversion mode (from ADC Shutdown mode, the ADC is allowed 256 DMCLK periods to power-up and settle to its desired operating point before starting conversions). The start-up time has been sized at 256 DMCLK clock periods for the part to be able to settle in all conditions and with all possible clock frequencies as specified. Table 5-11 summarizes the behavior of the internal start-up timer as a function of the ADC_MODE[1:0] settings. Rewriting the ADC_MODE[1:0] bits without changing the bit settings does not modify the internal timer and cannot shorten the start-up delay necessary to start accurate conversions. A synchronization delay of two MCLK periods occurs after each rewrite if ADC_MODE[1:0] = 1x. In SCAN mode, when CONV_MODE[1:0] = 11 (Continuous mode), the ADC may be placed in ADC Shutdown and restarted in between each SCAN cycle, depending on the TIMER[23:0] settings (see Section 5.14.5 “Delay Between Each SCAN Cycle (TIMER[23:0])”). If the TIMER register is programmed with a decimal code greater than TADC_SETUP = 256, the internal timer will automatically place the part in ADC Shutdown mode at the end of the cycle and will start to transition to the next cycle 256 DMCLK periods before the end of the TIMER delay. This lowers the power consumed during the TIMER delay as much as possible. If the value of the TIMER delay is less than 256 DMCLK periods, the part will not enter ADC Shutdown mode and stay in Standby mode during the TIMER delay (in this case, the power consumed is equivalent to the Conversion mode power consumption). In order to catch the start of the conversion in case of complex sequences of transitions, it can be useful to enable the EN_STP bit so that the part will generate a pulse on the IRQ pin to indicate a conversion start. Figure 5-10 shows different cases of transitions between modes and shows the internal state of the start-up timer for each step. Table 5-11 summarizes the behavior of the internal start-up timer as a function of the ADC_MODE[1:0] settings. ADC START-UP TIMER BEHAVIOR AS A FUNCTION OF ADC_MODE[1:0] SETTINGS ADC_MODE[1:0] ADC State 11 Conversion 10 Standby 0x ADC Shutdown  2019-2021 Microchip Technology Inc. ADC Start-up Timer Behavior The ADC start-up timer decrements to 0. The conversion starts when it reaches 0. The ADC start-up timer decrements to 0. The ADC is ready to convert when it reaches 0. ADC start-up timer is reset to TADC_SETUP = 256. DS20006180D-page 47 MCP3461/2/4 DMCLK Continuous Clocking SPI Wri te AD C_MODE = 1x Wri te AD C_MODE = 0x Wri te AD C_MODE = 1x 0x 1x 0x 1x Timer Reset Switching Between ADC_MODE = 10 and 11 has no Effect on the Timer ADC_MODE Timer Reset ADC Start-up Timer Decimal Code Timer Countdown Wri te 1X AD C_MODE = 1x 256 ADC Ready to Convert 0 FIGURE 5-10: 5.11 ADC Start-up Timer Timing Diagram. Master Clock Selection/Internal Oscillator The device includes three possible clock modes for the master clock generation. The Master Clock (MCLK) is used by the ADC to perform conversions and is also used by the digital portion to generate the different digital timers. The clock mode selection is made through the CLK_SEL[1:0] bits located in the CONFIG0 register. The possible selections are described in Table 5-12. The master clock is not propagated in the chip when the chip is placed into the Full Shutdown mode (see Section 5.9 “Low-Power Shutdown Modes”). Any change to the CLK_SEL bits creates a Reset and restart for the currently running conversions, and a restart of the ADC setup timer. Each Reset and restart will reset all internal phases to their default values and can lead to a possible temporary duty cycle change at the clock output pin. TABLE 5-12: CLK_SEL[1:0] CLOCK SELECTION BITS Clock Mode MCLK Pin 00 or 01 External clock MCLK digital input 10 Internal RC Oscillator, no clock output High-Z 11 Internal RC Oscillator with clock output AMCLK digital output DS20006180D-page 48 5.11.1 EXTERNAL MASTER CLOCK MODE (CLK_SEL[1:0] = 0x) The External Clock mode is used to input the MCLK clock necessary for the ADC conversions and can accept duty cycles with a large range since the clock is redivided internally to generate the different internal phases. The external clock can be provided on the MCLK pin for the MCP3461/2/4 devices. 5.11.2 INTERNAL OSCILLATOR The device includes an internal RC-type oscillator powered by the digital power supply (DVDD/DGND).The frequency of this internal oscillator ranges from 3.3 to 6.6 MHz. The oscillator is not trimmed in production, therefore, the precision of the center frequency is approximately ±30% from chip-to-chip. The duty cycle of the internal oscillator is centered around 50% and varies very slightly from chip-to-chip. The internal oscillator has no Reset feature and keeps running once selected.  2019-2021 Microchip Technology Inc. MCP3461/2/4 5.11.3 INTERNAL MASTER CLOCK MODES (CLK_SEL[1:0] = 1x) When CLK_SEL[1] = 1, the internal oscillator is selected and the master clock is generated internally. The internal oscillator has no Reset feature and is always running once selected. The master clock generation is independent of the ADC, as the clock can still be generated even if the ADC is in ADC Shutdown mode. The internal oscillator is only disabled when CLK_SEL[1:0] = 0x. The clock can be distributed to the dedicated output pin depending on the CLK_SEL[0] bit. When the clock output is selected (CLK_SEL[0] = 1), the AMCLK clock derived from the MCLK (AMCLK = MCLK/PRESCALE) is available on the output pin. The AMCLK output can serve as the clock pin to synchronize either the modulator output or other MCP3461/2/4 devices that would be configured with CLK_SEL[1:0] = 00 or 01. The AMCLK output is available on the MCLK clock output pin as soon as the Write command (CLK_SEL[1:0] = 11) is finished. 5.12 Digital System Offset and Gain Calibrations The MCP3461/2/4 devices include a digital calibration feature for offset and gain errors. The calibration scheme for offset error consists of the addition of a fixed offset value to the ADC output code (ADCDATA at address 0x0). The offset value added (OFFSETCAL) is determined in the OFFSETCAL register (address: 0x9). The calibration scheme for gain error consists of the multiplication of a fixed gain value to the ADC output code. The gain value (GAINCAL) multiplied is determined in the GAINCAL register (address 0xA). The digital offset and gain calibration schemes are enabled or disabled via the EN_OFFCAL and EN_GAINCAL control bits of the CONFIG3 register. When both calibration control bits are enabled (EN_OFFCAL = EN_GAINCAL = 1), the ADCDATA register contents are modified with the digital offset and gain calibration schemes, as described in Equation 5-6. When a calibration enable bit is off, its corresponding register becomes a don’t care register and the corresponding calibration is not performed. EQUATION 5-6: ADCDATA OUTPUT AFTER DIGITAL GAIN AND OFFSET ERROR CALIBRATION ADCDATA (post-calibration) = [ADCDATA (pre-calibration) + OFFSETCAL] x GAINCAL  2019-2021 Microchip Technology Inc. The calculations are performed internally with proper management of overloading, so that the overload detection is done on the output result only and not on the intermediate results. A sufficient number of additional overload bits are maintained and propagated internally to overcome all possible overload and/or overload recovery situations. For example, if ADCDATA (pre-calibration) + OFFSETCAL is out of bounds but (ADCDATA (pre-calibration) + OFFSETCAL) * GAINCAL is still in the right range (possible with 0 < GAINCAL < 1), then the result is not saturated. 5.12.1 DIGITAL OFFSET ERROR CALIBRATION The Offset Calibration register (OFFSETCAL, address: 0x9) is a signed MSb first, two’s complement coding, 24-bit register that holds the digital offset calibration value, OFFSETCAL. The OFFSETCAL equivalent input voltage value is calculated with Equation 5-7. EQUATION 5-7: OFFSETCAL CALIBRATION VALUE (EQUIVALENT INPUT VOLTAGE) OFFSETCAL (V) = VREF * (OFFSETCAL[23:8])/(32768 * GAIN) For the MCP3461/2/4 devices, the offset calibration is done by adding bit-by-bit the OFFSETCAL[23:8] calibration value to the ADCDATA code. The last byte of the OFFSETCAL register (OFFSETCAL[7:0]) is ignored and internally reset to 0x00 during the calibration, therefore the addition just takes into account the OFFSETCAL[23:8] bits and is done bit-by-bit with the ADC output code. The offset calibration value range in equivalent voltage is [-VREF/GAIN; (+VREF – 1 LSb)/GAIN], which permits cancellation of any possible offset in the ADC, but also in the system. The offset calibration is realized with a simple 16-bit signed adder and is instantaneous (no pipeline delay). Enabling the offset calibration will affect the next conversion result; the conversion result already held in the ADCDATA Output register (0x0) is not modified when the EN_OFFCAL is set to ‘1’, but the next one will take in account the offset calibration. Changing the OFFSETCAL register to a new value will not affect the current ADCDATA value, but the next one (after a data ready interrupt) will take into account the new OFFSETCAL value. Figure 5-11 shows the different cases and their implication on the ADCDATA register, as well as on the IRQ output. DS20006180D-page 49 MCP3461/2/4 Wri te OFFSETCAL[2 3 :] = OFFSETCAL1 SPI ADC STATUS Data 2 Conversion Data 3 Conversion Data 4 Conversion DATA0 DATA1 DATA2 + OFFSETCAL1 DATA3 + OFFSETCAL2 FIGURE 5-11: ADC Output and IRQ Behavior with Digital Offset Calibration Enabled. DIGITAL GAIN ERROR CALIBRATION The Gain Error Calibration register (GAINCAL, address: 0xA) is an unsigned 24-bit register that holds the digital gain error calibration value, GAINCAL. The GAINCAL multiplier is calculated with Equation 5-8. EQUATION 5-8: GAINCAL CALIBRATION VALUE (MULTIPLIER VALUE) GAINCAL (V/V) = (GAINCAL[23:8] unsigned decimal code)/32768 For the MCP3461/2/4 devices, the gain error calibration is done by multiplying the GAINCAL value to the ADC output code. The last byte of the GAINCAL register (GAINCAL[7:0]) is ignored and internally reset to 0x00 during the calibration, therefore, the multiplication just takes into account the GAINCAL[23:8] bits. The gain error calibration value range in equivalent voltage is Wri te GAINCAL[2 3 :] = GAINCAL1 SPI ADC STATUS Wri te OFFSETCAL[2 3 :] = OFFSETCAL2 Data 1 Conversion IRQ ADC DATA REGISTER VALUE 5.12.2 Wri te EN _OFFC AL = 1 Data 1 Conversion Wri te EN _GAIN C AL = 1 [0; 2-2-15], which permits the cancellation of any possible gain error in the ADC, but also in the system. The gain error calibration is realized with a simple add-and-shift circuit clocked on DMCLK and induces a pipeline delay of TGCAL = 15 DMCLK periods. This pipeline delay acts as a delay on the data ready interrupt position that is shifted by TGCAL = 15 DMCLK periods. During this delay, the converter can process the next conversion, the delay does not shift the next conversion and does not change the Conversion Time, TCONV. Enabling the gain error calibration will affect the next conversion result; the conversion result already held in the ADCDATA Output register (0x0) is not modified when the EN_GAINCAL is set to ‘1’, but the next one will take into account the offset calibration. Changing the GAINCAL register to a new value will not affect the current ADCDATA value, but the next one (after a data ready interrupt) will take into account the new GAINCAL value. Figure 5-12 details the different cases and their associated effects to the ADCDATA register and the IRQ output. Wri te GAINCAL[2 3 :] = GAINCAL2 Data 2 Conversion Data 3 Conversion Data 4 Conversion IRQ ADCDATA DATA0 DATA1 DATA2 x GAINCAL1 TGCAL FIGURE 5-12: DS20006180D-page 50 DATA3 x GAINCAL2 TGCAL ADC Output and IRQ Behavior with Digital Gain Error Calibration Enabled.  2019-2021 Microchip Technology Inc. MCP3461/2/4 5.13 Conversion Modes The ADC includes several Conversion modes that can be selected through the CONV_MODE[1:0] bits located in the CONFIG3 register. The behavior of the ADC with respect to these bits depends on whether the ADC is in MUX or SCAN mode. Table 5-13 summarizes the possible configurations. TABLE 5-13: ADC CONVERSION MODES IN MUX OR SCAN MODES CONV_MODE[1:0] 5.13.1 ADC Behavior (MUX Mode) ADC Behavior (SCAN Mode) ADC_MODE[1:0] Bits Settings 0x Performs a one-shot conversion Performs one complete SCAN and returns automatically to cycle and returns automatically ADC Shutdown mode. to ADC Shutdown mode. Returns to ‘0x’ after one conversion (MUX mode) or one SCAN cycle (SCAN mode). 10 Performs a one-shot conversion Performs one complete SCAN and returns automatically to cycle and returns automatically Standby mode. to Standby mode. Returns to ‘10’ after one conversion (MUX mode) or one SCAN cycle (SCAN mode). 11 Performs continuous conversions. Stays at ‘11’. CONVERSION MODES IN MUX MODE In MUX mode, the user can choose between one-shot and continuous conversions. A one-shot conversion is a single conversion and takes a certain Conversion Time, TCONV (or 2 x TCONV when AZ_MUX = 1, see Section 5.1.3 “ADC Offset Cancellation Algorithm”). Once this conversion is performed, the part returns automatically to a Standby or ADC Shutdown state depending on the CONV_MODE[1:0] bits setting. The Conversion mode determined by the CONV_MODE[1:0] bits setting will also affect the state of the ADC_MODE[1:0], as described in Table 5-13. The conversion can be preceded by a start-up time that depends on the ADC state (see Section 5.10 “ADC Start-up Timer”). In One-Shot mode, the ADC data have to be completely read with the SPI interface for the interrupt to be cleared on the IRQ pin (the IRQ pin cannot be automatically cleared like in the Continuous Conversion mode). This mode is recommended for low-power, low bandwidth applications, requiring a once in a while A/D conversion. Performs continuous SCAN cycles with TIMER[23:0] delay between each cycle. mode, the output data rate of the ADC is defined by DRCLK (see Figure 5-5). The digital decimation filter induces a pipeline or group delay of TCONV for the first data ready and is structured to give a continuous stream of data at the DRCLK rate after this first data ready (the internal registers of the filter are never reset in this mode, thus the decimation filter acts as a moving average). Each data ready interrupt corresponds to a valid and complete conversion that has processed through the digital filter (the digital filter has no latency in this respect). This mode allows a much faster data rate than the One-Shot mode, and is therefore, recommended for higher bandwidth applications. The pipeline delay should be carefully determined and adapted to user needs, especially in closed-loop, low-latency applications. This mode is recommended for applications requiring continuous sampling/averaging of the input signals. If AZ_MUX = 1, the Continuous Conversion mode is replaced by a series of subsequent One-Shot mode conversions, with a Reset between each conversion. This makes the group delay equal to 2 * TCONV and the data rate equal to 1/(2 * TCONV). Figure 5-13 and Figure 5-14 detail One-Shot and Continuous Conversion modes for MUX mode. In the Continuous Conversion mode, the ADC is never placed in Standby or ADC Shutdown mode and converts continuously without any internal Reset. In this  2019-2021 Microchip Technology Inc. DS20006180D-page 51 MCP3461/2/4 ADC Data Read can be tDODR Performed During this Time SPI Write Write ADC_MODE = 11 CONV_MODE = 0x or 10 MCLK ADC_MODE ADC STATUS Read ADC Data Don’t Care Continuous Clocking Don’t Care 00 11 ‘0x’ or ‘10’ Depending on CONV_MODE[1:0] Shutdown Start-up Conversion TADC_SETU P TCONV Shutdown or Reset Depending on CONV_MODE[1:0] TS TP IRQ Conversion Start (Generates Pulse if EN_STP = 1) FIGURE 5-13: IRQ is Cleared at First SCK Falling Edge After ADC Read Start MUX One-Shot Conversion Mode Timing Diagram. SPI MCLK ADC_MODE ADC STATUS Wri te Wri te C ONV_MODE = 11 AD C_MODE = 11 R ea d A DC D ata 1 Don’t Care Continuous Clocking 00 11 Shutdown R ea d A DC D ata 2 Start-up Data 1 Conversion Data 2 Conversion Data 3 Conversion TA DC_S ET UP TCONV 1/DRCLK 1/DRCLK IRQ TDRH FIGURE 5-14: DS20006180D-page 52 TDRH MUX Continuous Conversion Mode Timing Diagram.  2019-2021 Microchip Technology Inc. MCP3461/2/4 5.13.2 CONVERSION MODES IN SCAN MODE If CONV_MODE[1:0] = 11, the ADC runs in a SCAN Cycle mode with a TIMER[23:0] delay between each cycle. In SCAN mode, the device takes one conversion per channel and multiplexes the input to the next channel in the SCAN sequence. Therefore, all conversions are One-Shot mode conversions, regardless of what the CONV_MODE[1:0] bits are set to. Each conversion takes the same time, TCONV (or 2 x TCONV when AZ_MUX = 1, see Section 5.1.3 “ADC Offset Cancellation Algorithm”), to be performed. If CONV_MODE[1:0] = 00, 01 or 10, the SCAN cycle is executed once and then the ADC is placed into Standby or ADC Shutdown mode. SPI Writ e CONV_MODE = 0x/10 MCLK Writ e A DC_MODE = 11 Writing the CONV_MODE[1:0] bits with the SPI interface within a conversion does not create an internal Reset. It is recommended not to wait for the end of a conversion to change the CONV_MODE[1:0] bits to the desired value, but to change to the desired value just after a data ready to avoid possible glitches. Figure 5-15 and Figure 5-16, respectively, detail the ADC timing behavior in One-Shot and Continuous Conversion modes, when configured for SCAN mode, with N channels chosen among 16 SCAN possibilities. R ea d A DC D ata 1 Don’t Care ADC STATUS Sta rt-u p C ha n ne l 1 C on ve rsi on TA DC_S ET UP TCONV ADC STATUS C ha n ne l N Co nv ers io n (L ast i n C ycl e) TCONV TDLY_S CAN TCONV TDRH Sh u td o wn or R e set D ep e nd in g o n C ON V_MOD E T DRH SCAN One-Shot Conversion Mode Timing Diagram. Writ e CONV_MODE = 11 ADC_MODE R es et R es et C ha n ne l 2 C on ve rsi on T DLY_S CAN IRQ MCLK ‘0x’ or ‘10’ D ep e nd in g o n C ON V_MOD E 11 Sh u td o wn FIGURE 5-15: R ea d A DC D ata N Continuous Clocking 00 ADC_MODE SPI R ea d A DC D ata N -1 Writ e A DC_MODE = 11 R ea d A DC D ata 1 R ea d A DC D ata N -1 Don’t Care Read ADC Data1 (New Cycle) R ea d A DC D ata N Continuous Clocking 00 11 TA DC_S ET UP Sh u td o wn Sta rt-u p C ha n ne l 1 C on ve rsi on TAD C_SE TUP TC ONV IRQ R es et C ha n ne l N Co nv ers io n (L ast i n C ycl e) TD LY _SC AN TC ONV R es et C ha n ne l 2 C on ve rsi on TD LY _SC AN TC ONV TD RH Sh u td o wn or R e set de pe nd i ng on TIMER [2 3:0] se tti n gs TTIME R_SC AN Sta rt-u p C ha n ne l 1 C on ve rsi on (N ew C ycle ) TC ONV R es et TD RH TD RH C ha n ne l 2 C on ve rsi on (N ew C ycle ) TD LY _SC AN TC ONV TD RH Start-up Time is Reduced to 0 if TTIMER_SCAN < 256 DMCLK Periods FIGURE 5-16: SCAN Continuous Conversion Mode Timing Diagram.  2019-2021 Microchip Technology Inc. DS20006180D-page 53 MCP3461/2/4 5.14 SCAN Mode 5.14.1 5.14.2 SCAN MODE PRINCIPLE In SCAN mode, the device sequentially and automatically converts a list of predefined differential inputs (also referred to as input channels) in a defined order. After this series of conversions, the ADC can be placed in Standby or ADC Shutdown mode, or can wait a certain time in order to perform the same sequence of conversions periodically. This mode is useful for applications that require constant monitoring of defined channels or internal resources (like AVDD or REFIN+/REFIN-) and allow minimal and simplified communication. When in SCAN mode, the MUX register (address: 0x6) becomes a Don’t Care register. SCAN mode includes a configurable delay between each SCAN cycle, as well as a configurable delay between each conversion within a SCAN cycle. Each conversion within the SCAN cycle leads to a data ready interrupt and to an update of the ADCDATA register as soon as the current conversion is finished. The device does not include additional memory to retain all SCAN cycle A/D conversion results. Therefore, each result has to be read when it is available and before it is overwritten by the next conversion result. TABLE 5-14: The ADC is, by default, in MUX mode at power-up. The ADC enters SCAN mode as soon as one of the SCAN[15:0] bits in the SCAN register is set to ‘1’. MUX mode and SCAN mode cannot be enabled at the same time. When SCAN[15:0] = 0x0000, SCAN mode is disabled and the part returns to MUX mode, where the input channel selection is defined by the MUX[7:0] bits. The SCAN cycle conversions are effectively started as soon as the ADC_MODE[1:0] bits are programmed through the SPI interface to ‘11’ (Direct Write or Fast command, ADC Reset and restart). After the ADC_MODE[1:0] bits have been set to ‘11’, they keep the same value until SCAN mode is completed or aborted. Each of the SCAN[15:0] bits defines a possible input channel for the SCAN cycle, which corresponds to a certain selection of the analog multiplexer input channel and possibly a certain predefined gain of the ADC. The SCAN cycle processes and converts each channel that has been enabled (SCAN[n] = 1) with a defined order of priority, from MSb to LSb (SCAN[15] to SCAN[0]). The list of channels with their corresponding inputs is defined in Table 5-14. When using DATA_FORMAT[1:0] = 11, each channel conversion result in the SCAN sequence can be identified with a Channel ID (CH_ID[3:0]) code that will appear in the 4 MSbs of the ADCDATA register output value (Section 5.6 “ADC Output Data Format”). The Channel ID permits retrieval of which channel the output data came from. Table 5-14 shows each possible Channel ID value and its associated channel. ADC CHANNEL SELECTION SCAN[n] Bit(1,2) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Note 1: 2: SCAN MODE ENABLE AND SCAN CHANNEL SELECTION Channel Name Channel ID MUX[7:0] Corresponding Setting Specific ADC Gain OFFSET 1111 0x88 None 1110 0xF8 1x VCM AVDD 1101 0x98 0.33x TEMP 1100 0xDE 1x Differential Channel D (CH6-CH7) 1011 0x67 None Differential Channel C (CH4-CH5) 1010 0x45 None Differential Channel B (CH2-CH3) 1001 0x23 None Differential Channel A (CH0-CH1) 1000 0x01 None Single-Ended Channel CH7 0111 0x78 None Single-Ended Channel CH6 0110 0x68 None Single-Ended Channel CH5 0101 0x58 None Single-Ended Channel CH4 0100 0x48 None Single-Ended Channel CH3 0011 0x38 None Single-Ended Channel CH2 0010 0x28 None Single-Ended Channel CH1 0001 0x18 None Single-Ended Channel CH0 0000 0x08 None SCAN[11:10] and SCAN[7:4] are not available for MCP3462. Writing to these bits has no effect. SCAN[11:9] and SCAN[7:2] are not available for MCP3461. Writing to these bits has no effect. DS20006180D-page 54  2019-2021 Microchip Technology Inc. MCP3461/2/4 5.14.3 5.14.3.1 SCAN MODE INTERNAL RESOURCE CHANNELS Analog Supply Voltage Reading (AVDD) During the conversion that reads AVDD in SCAN mode, the multiplexer selection becomes 0x98 (AVDD-AGND), which is equal to the analog power supply voltage. Since AVDD is the highest voltage available in the chip, when reading AVDD in SCAN mode, the gain of the ADC is automatically set to 0.33x, which maximizes the input full-scale range, regardless of the GAIN[2:0] settings. This temporary internal configuration does not change the register settings, but just for the gain of the device during this conversion. With this fixed 0.33x gain, the ADC can measure the maximum specified analog supply voltage (AVDD = 3.6V) with a reference voltage as low as 1.2V. 5.14.3.2 Temperature Reading (TEMP) During the conversion that reads TEMP in SCAN mode, the multiplexer selection becomes 0xDE, which enables the two temperature diode sensors at each input of the ADC. During the temperature reading, the gain of the ADC is automatically set to ‘1x’, regardless of the GAIN[2:0] settings. This temporary internal configuration does not change the register setting, but just for the gain of the device during this conversion. During the VCM reading, the gain of the ADC is set to 1x regardless of the GAIN[2:0] settings. This temporary internal configuration does not change the register setting, but just the gain of the device during this conversion. The VCM reading is susceptible to the gain error and offset error of the ADC, which should be calibrated out to obtain a precise internal Common-mode measurement. 5.14.4 DELAY BETWEEN EACH CONVERSION WITHIN A SCAN CYCLE (DLY[2:0]) While the ADC and multiplexer are optimized to switch from one channel to another instantaneously, it may not be the case of an application that requires additional settling time to overcome the transition. The device can insert an additional delay between each conversion of the SCAN cycle. The delay value is controlled by the DLY[2:0] bits located in the SCAN register (SCAN[23:20]). See Table 5-15. TABLE 5-15: DELAY BETWEEN CONVERSIONS WITH A SCAN CYCLE DLY[2:0] Delay Value (DMCLK Periods) 111 512 During the conversion that reads OFFSET in SCAN mode, the differential MUX output is shorted to AGND (internally). The Offset Reading varies from part to part, over AVDD and temperature. The reading of this offset value can be used for the device offset calibration or tracking of the offset value in applications. 110 256 101 128 100 64 011 32 010 16 There is no automatic offset calibration in the device, so the user has to manually write the opposite signed value of the offset measured into the OFFSETCAL register to effectively cancel the offset on the subsequent outputs. 001 8 000 0 5.14.3.3 5.14.3.4 Offset Reading (OFFSET) VCM Reading (VCM) During the conversion that reads VCM, the device monitors the internal Common-mode voltage of the device in order to ensure proper operation. The VCM voltage of the device should be located at 1.2V, ±2%, to ensure proper accuracy. In this setting, the internal multiplexer setting becomes 0xF8h (VCM – AGND). In order to properly measure VCM, the voltage reference at the inputs needs to be larger than 1.2V.  2019-2021 Microchip Technology Inc. The delay is only added in between two conversions of the same SCAN cycle. There is no delay added at the end or the beginning of each SCAN cycle as a result of the DLY[2:0] bits setting. During this delay, the ADC is internally kept in Standby mode (ADC_MODE[1:0] = 10 internally, but the ADC_MODE[1:0] bits are always read as ‘11’ through the SPI interface). The analog multiplexer switches to the next selected input at the end of each conversion, which means at the beginning of the added delay so that the application can have additional time to settle properly. DS20006180D-page 55 MCP3461/2/4 5.14.5 DELAY BETWEEN EACH SCAN CYCLE (TIMER[23:0]) During Continuous mode, SCAN cycles are processed continuously, one after another, separated by a time delay (TTIMER_SCAN), which is defined by the TIMER register (address: 0x8) value. During this delay, the ADC is automatically placed into a power-saving mode (Standby or ADC Shutdown). The TTIMER_SCAN delay offers better power efficiency for applications that run a SCAN sequence periodically. Since the delay can be very long, it allows synchronous applications with very slow update rates without having to use an external timer. The TIMER register defines the time, TTIMER_SCAN, between each cycle with a 24-bit unsigned value going from 0 to 16777215 DMCLK periods. Table 5-16 details the TIMER possible values with respect to the TIMER[23:0] code. TABLE 5-16: TIMER DELAY VALUE BETWEEN SCAN CYCLES TIMER[23:0] TTIMER_SCAN Delay Value (DMCLK Periods) 111111111111111111111111 16777215 111111111111111111111110 16777214 100000000000000000000000 8388608 000000000000000000000001 1 000000000000000000000000 0 The internal TIMER counter will decrement from the TTIMER_SCAN value to 0 and launch the new SCAN cycle. If the TTIMER_SCAN value is greater than TADC_SETUP (256 DMCLK periods), the device will be placed in ADC Shutdown mode (ADC_MODE is set internally to ‘00’) at each end of a SCAN cycle. When the internal TIMER counter reaches 256, the device will start up the ADC during a TADC_SETUP time to be ready to convert when the internal counter reaches 0. If the TTIMER_SCAN value is less than TADC_SETUP, the part will be placed in Standby mode between each SCAN cycle (ADC_MODE is internally set to ‘10’). ADC_MODE[1:0] bits in the CONFIG0 can only be read as ‘11’ by the SPI interface during the whole SCAN cycle and in between SCAN cycles. 5.15 A/D Conversions Automatic Reset and Restart Feature When the A/D conversions are running, the user can change the device configuration through the SPI interface by writing any register. Some register settings directly impact the conversion results and would lead to invalid ADC data if they were changed within a conversion. The device incorporates an automatic Reset and restart feature for the A/D conversions to avoid these invalid data DS20006180D-page 56 to be generated. Some register writes with the SPI interface during a conversion will automatically reset and restart the A/D conversion with the new settings. The automatic Reset and restart feature behavior depends on the register bits that are written by the SPI interface. 5.15.1 REGISTER BITS’ MODIFICATIONS NOT CAUSING RESET/RESTART The first group of bits does not generate any Reset and restart. This group is composed of all the unused bits, all the read-only bits and some digital settings, such as CONV_MODE[1:0], DATA_FORMAT[1:0], CRC_FORMAT, EN_CRCCOM, IRQ_MODE[0], EN_FASTCMD, EN_STP and LOCK[7:0] bits. 5.15.2 REGISTER BITS’ MODIFICATIONS CAUSING IMMEDIATE RESET/RESTART The second group of bits generates immediate Reset and restart. The Reset is immediate, the restart is only valid after a period of two MCLK periods (necessary to handle the Reset and ensures that the restart is synchronous with the master clock). This group is composed of settings that do not induce an analog operating point change. This group includes ADC_MODE[1:0], PRE[1:0], OSR[3:0], GAIN[2:0], AZ_MUX, EN_OFFCAL, EN_GAINCAL, IRQ_MODE[1:0], MUX[7:0] and DLY[2:0] bits. The EN_OFFCAL, EN_GAINCAL and IRQ_MODE[1:0] bits generate the Reset and restart only if they are changed to a new value. An overwrite of the same value has no effect. In SCAN mode, the Reset and restart feature will just restart the current conversion for this group of bits; the SCAN cycle is not modified and not restarted. The MUX[7:0] bits can be changed within SCAN mode without generating a Reset and restart, since this register is a don’t care during SCAN mode. The DLY[2:0] bits can be changed during the MUX mode without generating a Reset and restart, since these bits are don’t care during the MUX mode. The OFFSETCAL[23:0] and GAINCAL[23:0] bits will only generate a Reset and restart when written if their corresponding enable bit (EN_OFFCAL, EN_GAINCAL) is enabled. The ADC_MODE[1:0] bits generate an immediate reset and restart but only if they are overwritten with ‘11’ (in any other case, the conversions are stopped). Depending on the part being in MUX or SCAN mode, the reset and restart feature resets either the conversion or the complete SCAN cycle.  2019-2021 Microchip Technology Inc. MCP3461/2/4 5.15.3 REGISTER BITS’ MODIFICATIONS CAUSING DELAYED RESET/RESTART A third group of bits will generate a Reset and restart that induces a new start-up delay (TADC_SETUP) so that the internal analog operating points can be settled with the new settings before the new conversion is started. The Reset is immediate; the start-up timer is only restarted after a period of two MCLK periods (necessary to handle the Reset and ensures that the restart is synchronous with the master clock). Overall, the delay from Reset to actual restart of the conversion with the new settings is then two MCLK periods plus TADC_SETUP. This group includes CONFIG0[7:6], CLK_SEL[1:0], CS_SEL[1:0], BOOST[1:0] and the RESERVED Address registers (0xB and 0xC). The CS_SEL[1:0], CLK_SEL[1:0] and BOOST[1:0] bits will induce a start-up timer delay only if they are changed to a new value. If they are overwritten with the same value, they will generate an immediate Reset and restart. In SCAN mode, the Reset and restart feature will just restart the current conversion for this group of bits; the SCAN cycle is not modified and not restarted. This third group of bits will induce a start-up timer delay, even when ADC_MODE[1:0] = 10 or if the ADC is in Standby mode. In MUX mode, the TIMER and SCAN registers do not generate a Reset and restart when written, except if the SCAN register is modified to effectively enter in SCAN mode. In this case, the MUX mode is superseded by the SCAN mode immediately. In SCAN mode, a write access of the SCAN register, during or between conversions within the SCAN cycle, will create a Reset and restart of the whole SCAN sequence. Within the same conditions, a write access on the TIMER register will not create a Reset and restart of the whole SCAN sequence. However, during the TTIMER_SCAN delay between each SCAN cycle, a write on the SCAN register will not generate a Reset and restart of the whole sequence. Within the same conditions, a write on the TIMER register will generate a Reset and restart of the whole sequence. Depending on the phase between AMCLK and the SPI commands, the two MCLK period delay can become a four MCLK delay to ensure the proper synchronization of the device. If very precise synchronization is required, it is recommended to either not change dynamically the register configurations (i.e., not during conversions), or to use the EN_STP = 1 setting so that the start of the conversions can be clearly determined. During the Reset and restart sequence, the Reset is immediate and resets the internal phases to the original state, which can lead to a discontinuity in the clock output frequency if the AMCLK clock output is enabled. The restart is synchronous with the AMCLK generation and is effective only after two MCLK periods. The restart will also generate a conversion start pulse (only after the two MCLK periods or the 2 MCLK + TADC_SETUP necessary for the restart) if enabled for the user to be able to align the system with the exact start of the new conversion.  2019-2021 Microchip Technology Inc. DS20006180D-page 57 MCP3461/2/4 NOTES: DS20006180D-page 58  2019-2021 Microchip Technology Inc. MCP3461/2/4 6.0 SPI SERIAL INTERFACE AND DEVICE OPERATION 6.1 Overview The MCP3461/2/4 devices use an SPI interface for reading and writing the internal registers. The SPI interface includes a four-wire (CS, SCK, SDI, SDO) serial SPI interface that is compatible with SPI Modes 0,0 and 1,1. Data are clocked out of the device on the falling edge of SCK and data are clocked into the device on the rising edge of SCK. In these modes, the SCK clock can Idle either high (1,1) or low (0,0). The digital interface is asynchronous with the MCLK clock that controls the ADC sampling and digital filtering. All digital input pins are Schmitt Triggered to avoid system noise perturbations on the communications. The SPI interface is maintained in a Reset state during POR. Each SPI communication starts with a CS falling edge and stops with the CS rising edge. Each SPI communication is independent. When CS is logic high, SDO is in high-impedance; the transitions on SCK and SDI have no effect. Changing from SPI Mode 1,1 to an SPI Mode 0,0 and vice-versa is possible and must be done while the CS pin is logic high. Any CS rising edge clears the communication and resets the SPI digital interface. See Figure 1-1 for the SPI timing details. The MCP3461/2/4 digital interface is capable of handling various Continuous Read and Write modes, which allows for ADC data streaming or full register map writing within only one communication (and therefore, with only one unique COMMAND byte). It also includes single-byte Fast commands that allow faster access to common and useful configurations. The device does not include a Master Reset pin, but it includes an SPI Fast command to be able to fully reset the part at any time and place it back in a default configuration. The device family also includes advanced security features to secure communication and alert users of unwanted Write commands which change the desired configuration. To secure the entire configuration of the device, the device includes an 8-bit lock code (LOCK[7:0]), which blocks all write commands to the full register map if the value of the lock code is not equal to a defined password (0xA5). The user can protect its configuration by changing the LOCK[7:0] value to 0x00 after full programming, so that any unwanted Write command will not result in a change in the configuration. Each SPI read communication can be secured through a selectable CRC-16 checksum provided on the SDO pin at the end of every communication sequence. This checksum computation is compatible with the DMA CRC hardware of the PIC24 and PIC32 MCUs, as well as many other MCU references, resulting in no additional overhead for the added security.  2019-2021 Microchip Technology Inc. Once the part is locked (write-protected), an additional checksum calculation is also running continuously in the background to ensure the integrity of the full register map. All writable registers of the register map are processed through a CRC-16 calculation engine and give a CRC-16 checksum that depends on the configuration. This checksum is readable from the CRC register and updated at all times when MCLK is running. If a change in this checksum happens, a CRC interrupt generates a flag to warn the user that the configuration has been corrupted. The MCP3461/2/4 devices also include additional digital signal pins, such as a dedicated IRQ interrupt output pin and a Master Clock (MCLK) input/output pin, which allow easier synchronization and faster interrupt handling, facilitating the implementation of the device in many different applications. 6.2 SPI Communication Structure The MCP3461/2/4 interface has a simple communication structure. Every communication starts with a CS falling edge and stops with a CS rising edge. After the communication start, the communication is always started by the COMMAND byte (8 bits) clocking on the SDI input. The COMMAND byte defines the command that will be executed by the digital interface. It includes the device address, the register address bits and the command-type bits. The COMMAND byte is typically followed by data bytes clocked on SDI if the command type is a write, and on SDO if the command type is a read. The COMMAND byte can also define a Fast command, in which case, it is not followed by any other byte. The following subsections detail the COMMAND byte structure and all possible commands. During the COMMAND byte clocking on SDI, a STATUS byte is also propagated on the SDO output to enable easy polling of the device status. During this time, the interface is full-duplex, but the part can still be used by MCUs handling only half-duplex communications if the STATUS byte is ignored. 6.2.1 COMMAND BYTE STRUCTURE The COMMAND byte fully defines the command that is executed by the part. This byte is divided into three parts: the Device Address bits (CMD[7:6]), the Command Address bits (CMD[5:2]) and the Command Type bits (CMD[1:0]). A representation of this COMMAND byte is available in Figure 6-1. CMD[7] CMD[6] Device Address Bits CMD[5] CMD[4] CMD[3] CMD[2] Register Address / Fast Command bits FIGURE 6-1: CMD[1] CMD[0] Command Type Bits COMMAND Byte. DS20006180D-page 59 MCP3461/2/4 6.2.2 DEVICE ADDRESS BITS (CMD[7:6]) The SPI interface of the MCP3461/2/4 devices is addressable, which means that multiple devices can communicate on the same SPI bus with only one chip select line for all devices. Each device communication starts by a CS falling edge, followed by the clocking of the device address (CMD[7:6]). Each device contains an internal device address which the device can respond to. This device address is coded on two bits, so four possible addresses are available. The address is hard-coded within the device and should be determined at the ordering of the device. The device address is part of the device markings to avoid potential confusion (see Section 9.1 “Package Marking Information(2)”). When the CMD[7:6] bits match the device address, the communication proceeds and the part will execute the commands defined in the control byte and its subsequent data bytes. When the CMD[7:6] bits do not correspond to the device address hard-coded in the device, the command is ignored. In this case, the SDO output will become high-impedance, which prevents bus contention errors when multiple devices are connected on the same SPI bus (see Figure 6-3). The user has to exit from this communication through a CS rising edge to be able to launch another command. TABLE 6-1: 6.2.3 COMMAND ADDRESS BITS (CMD[5:2]) The COMMAND byte contains four address bits (CMD[5:2]) that can serve two purposes. In case of a register write or read access, they define at which register address the first read/write is performed. In case of a Fast command, they determine which Fast command is executed by the device. In case of a Write command on a read-only register, the command is not executed and the communication should be aborted (CS rising edge) to place another command. All registers can be read; there is no undefined address in the register map. 6.2.4 COMMAND-TYPE BITS (CMD[1:0]) The last two bits of the COMMAND byte define the command type. These bits are an extension of the typical read/write bits present in most SPI communication protocols. The two bits define four possible command types: Incremental Write, Incremental Read, Static Read and Fast command. Changing command type within the same communication (while CS is logic low) is not possible. The communication has to be stopped (CS rising edge) and restarted (CS falling edge) to change its command type. The list of possible commands, their type and their possible command addresses are described in Table 6-1. COMMAND TYPES DESCRIPTION TABLE CMD[5:2] CMD[1:0] 0xxx 00 Don’t Care 100x 00 Don’t Care 1010 00 ADC Conversion Start/Restart Fast Command (Overwrites ADC_MODE[1:0] = 11) 1011 00 ADC Standby Mode Fast Command (Overwrites ADC_MODE[1:0] = 10) 1100 00 ADC Shutdown Mode Fast Command (Overwrites ADC_MODE[1:0] = 00) 1101 00 Full Shutdown Mode Fast Command (Overwrites CONFIG0[7:0] = 0x00) 1110 00 Device Full Reset Fast Command (Resets Whole Register Map to Default Value) 1111 00 Don’t Care ADDR 01 Static Read of Register Address, ADDR ADDR 10 Incremental Write Starting at Register Address, ADDR ADDR 11 Incremental Read Starting at Register Address, ADDR DS20006180D-page 60 Command Description  2019-2021 Microchip Technology Inc. MCP3461/2/4 6.2.5 FAST COMMANDS DESCRIPTION There are five possible Fast commands available in the MCP3461/2/4 devices. For each command, only the COMMAND byte has to be provided on the SPI port and the command will be executed right after the COMMAND byte has been clocked. The Fast command codes are detailed in Table 6-1. All undefined command address codes for Fast commands will be ignored and will have no effect. SDO will stay in high-impedance after the COMMAND byte for a Fast command until a CS rising edge is provided. The Fast commands can be enabled or disabled by placing the EN_FASTCMD bit in the IRQ register to ‘1’ (default). Disabling Fast commands can increase the security of the device because it can avoid unwanted Fast commands to be executed, which can be useful in harsh environments. The ADC Start/Restart command (command address: ‘1010’) overwrites the ADC_MODE[1:0] bits to ‘11’, creating a conversion start (or a restart if the conversion was already running). The ADC Standby mode command (command address: ‘1011’) overwrites the ADC_MODE[1:0] bits to ‘10’, and is therefore, placing the ADC in Standby mode. The ADC Shutdown mode command (command address: ‘1100’) overwrites the ADC_MODE[1:0] bits to ‘00’, and is therefore, placing the ADC in ADC Shutdown mode. The Full Shutdown mode command (command address: ‘1101’) is overwriting the CONFIG0 register to 0x00h, which places the device in full ADC Shutdown mode. (see Section 5.9 “Low-Power Shutdown Modes” for a full description of this mode). The Full Reset command (command address: ‘1110’) resets the whole device and places the whole register map into its default state condition, including the non-writable registers. The only difference with a POR event is that the POR_STATUS bit in the IRQ register is set to ‘1’ after a full Reset and is reset to ‘0’ after a POR event. The Full Reset command is the only way with POR to clear the ADC Data Output register to its default value. 6.2.6 DEVICE ADDRESS AND STATUS BYTE DURING CONTROL BYTE During the clocking of the COMMAND byte on the SDI pin, the SDO pin displays a STATUS byte to help the user to quickly retrieve interrupt status information. The STATUS byte structure is described in Figure 6-2. STAT[7] STAT[6] STAT[5] STAT[4] STAT[3] STAT[2] STAT[1] STAT[0] 0 0 DEV_ADDR [1] DEV_ADDR [0] DEV_ADDR [0] DR_ST ATUS CRCCFG_ ST ATUS POR_ST ATUS Device Address Acknowledge bits FIGURE 6-2: Interrupt Status bits STATUS Byte. The first two bits are always equal to ‘0’ and SDO toggles to ‘0’ as soon as a CS pin falling edge is performed. This allows the application of multiple devices with different device addresses sharing one common SPI bus and avoiding bus contention during STATUS byte clocking. The next three bits of the STATUS byte give a confirmation (Acknowledge) of the hard-coded device address. If the device address of the COMMAND byte and the internal device address of the chip match, these three bits will be transmitted and they are equal to: • STAT[5:4] = DEV_ADDR[1:0] • STAT[3] = DEV_ADDR[0] The STAT[3] bit permits the user to distinguish the SDO output from a High-Impedance state (device address is not matched) as the bits, STAT[4] and STAT[3], are complementary and will induce a toggle on the SDO output. If the two device address bits are not matched with the internally hard-coded device address bits, SDO is maintained in a High-Impedance state during the rest of the communication and the command is ignored. This behavior avoids potential bus contention errors if multiple devices with different device addresses are sharing the same SPI bus, as after the transmission of the first two bits, only one device is responding to the command (all other devices with non-matching device addresses have SDO kept in high-impedance). In this case, the user needs to abort the communication (CS rising edge) to be able to perform another command. The three LSbs of the STATUS byte are the three interrupt status bits: • STAT[2] = DR_STATUS ADC (Data Ready Interrupt Status) • STAT[1] = CRCCFG_STATUS (CRC Checksum Error on the Register Map Interrupt Status) • STAT[0] = POR_STATUS (POR Interrupt Status) The STATUS byte permits fast polling of the different interrupts without having to read the IRQ register. However, it requires a MCU that can communicate in Full-Duplex mode (SDI and SDO are clocked at the same time). For MCUs that are only half-duplex, and for devices that do not incorporate a separate IRQ pin, or for applications that do not connect the existing IRQ pin, the polling of the IRQ status can still be done by reading the IRQ register continuously.  2019-2021 Microchip Technology Inc. DS20006180D-page 61 MCP3461/2/4 These three interrupt status bits are independent of the two other interrupt mechanisms (IRQ pin and IRQ register) and are cleared each time the STATUS byte is fully clocked. This enables the polling on the STATUS byte as a possible interrupt management solution without requiring to connect the IRQ pin in the system. All status bit values are latched together just after the device address has been correctly recognized by the chip. Any interrupt happening after the two first status bits have been clocked out will appear on the STATUS byte of the next communication sequence. Figure 6-3 represents the beginning of each communication with both COMMAND and STATUS bytes depicted. After the STATUS byte is propagated, the SDO pin will be placed in high-impedance for Fast commands or Write commands and will transfer data bytes for Read commands as long as the CS pin stays logic low. Device Latches SDI on Rising Edge CS Device Latches SDO on Falling Edge SPI Mode 1,1 SCK SDO High-Z Device Address does not Match CMD[7:6] CMD[0] CMD[1] CMD[2] CMD[3] Device Address ACK DR_ STATUS 0 CMD[6] Device Address Matches CMD[7:6] CMD[6] High-Z CMD[7] SDO Command Type Register Address CRCREG_ STATUS POR_ STATUS Device Address CMD[4] CMD[5] Don’t Care CMD[6] SDI CMD[7] SPI Mode 0,0 Interrupts Status High-Z 0 FIGURE 6-3: SPI Communication Start (COMMAND on SDI and STATUS on SDO) in Cases of a Device Address Match and Not Matched. DS20006180D-page 62  2019-2021 Microchip Technology Inc. MCP3461/2/4 6.3 Writing to the Device When the command type is “Incremental Write” (CMD[1:0] = 10), the device enters Write mode and starts writing the first data byte to the address given in the CMD[5:2] bits. CONFIG0 (0x1) CONFIG1 (0x2) After the STATUS byte has been transferred, SDO is always in a High-Impedance state during an incremental write communication. Writing to a read-only address (such as addresses, 0x0 or 0xF) has no effect and does not increment the Address Pointer. In this case, the user needs to stop the communication and restart a communication with a COMMAND byte pointing to a writable address (0x1 to 0xD). CONFIG2 (0x3) CONFIG3 (0x4) IRQ (0x5) MUX (0x6) Each register is effectively written after receiving the last bit for the register (SCK last rising edge). Any CS rising edge during a write communication aborts the current writing. In this case, the register being written will not be updated and will keep its old value. The registers may need 8, 16 or 24 bits to be effectively written depending on their address (see Table 8-1). After each register is written, the Address Pointer is automatically incremented as long as CS stays logic low. Attempted data writes to read-only registers will result in the data byte being written to the next sequential writable register/address in the register map. When the Address Pointer reaches 0xD, the next register to write is the register 0x1 (see Figure 6-4 for a graphical representation of the address looping). The incremental write feature can be used to fully configure the part by using a unique communication, which can save time in the application. This unique communication can end at address 0xD so that the user can also lock the configuration when written, providing additional security in the application (see Section 6.6 “Locking/Unlocking Register Map Write Access”). SCAN (0x7) TIMER (0x8) OF FSETCAL (0x9) GAINCAL (0xA) Reserved (0xB) Reserved (0xC) LOCK (0xD) Reserved (0xE) FIGURE 6-4: Incremental Write Loop. Internal registers, located at addresses 0xB, 0xC and 0xE, should be kept to their default state at all times for proper operation. These are reserved registers and should not be modified. Figure 6-5 and Figure 6-6 show an example of a write communication in detail with a single register incremental write communication.  2019-2021 Microchip Technology Inc. DS20006180D-page 63 MCP3461/2/4 CS Device Latches SDI on Rising Edge DATA[0] DATA[1] DATA[3] DATA[2] DATA[4] DATA[5] DATA[6] DATA[7] DATA[9] DATA[8] DATA[11] DATA[10] DATA[12] DATA[13] DATA[15] DATA[14] DATA[16] DATA[17] DATA[18] DATA[19] DATA[21] DATA[20] DATA[22] 0 1 DATA[23] Don’t Care High-Z POR _ STA TUS CMD[2] CMD[3] C RC C FG_ STA TUS CMD[4] CMD[6] 0 D R_ STA TUS CMD[5] 0 0 CMD[7] High-Z SDO CMD[6] Don’t Care CMD[6] SDI CMD[7] SCK SPI Mode 0,0; Example with a 24-Bit Wide Register Located at Address CMD[5:2] CS Device Latches SDI on Rising Edge DATA[1] DATA[2] DATA[3] DATA[4] DATA[5] DATA[6] DATA[7] DATA[8] DATA[9] DATA[10] DATA[11] DATA[12] DATA[13] DATA[14] DATA[15] DATA[16] DATA[17] DATA[18] DATA[19] DATA[20] DATA[21] DATA[22] DATA[23] 0 DATA[0] Don’t Care High-Z POR _ STA TUS 1 CMD[2] D R_ STA TUS C RC C FG_ STA TUS CMD[3] CMD[5] CMD[4] CMD[6] 0 0 0 CMD[6] High-Z CMD[7] SDO Don’t Care CMD[6] SDI CMD[7] SCK A[6] SPI Mode 1,1; Example with a 24-Bit Wide Register Located at Address CMD[5:2] FIGURE 6-5: Single Register Write Communication (CMD[1:0] = 10) Timing Diagram. CS ADDRESS SET 0x1 SCK Depends on ADDR 8x Depends on ADDR + 1 ... 8x 8x 8x ... 8x ... ADDR SDI Don’t Care COMMAND BYTE CMD[7:6] + ADDR +10 ADDR ADDR + 1 ... ADDR = 0xD ADDR = 0x1 Complete Write Sequence ADDR = 0x2 ... Complete Write Sequence ADDR = 0xD ... Complete Write Sequence 0xD Rollover SDO High-Z 00xxxxxx High-Z 0 Depends on IRQ Status and Device Address FIGURE 6-6: DS20006180D-page 64 Multiple Register Write Within One Communication Using Incremental Write Feature.  2019-2021 Microchip Technology Inc. MCP3461/2/4 6.4 Reading from the Device When the Command bit, CMD[0], is equal to ‘1’, the command is a read communication. After the STATUS byte has been transferred, the first register to be read on the SDO pin is the one with the address defined by the Command Address bits (CMD[5:2]). Any CS rising edge during a read communication aborts the current reading. The registers may need 4, 8, 16, 24 or 32 bits to be fully read, depending on their address (see Table 8-1). If the CMD[1:0] bits are equal to ‘11’, the command type is incremental read. In this case, after each register is read, the Address Pointer is automatically incremented as long as CS stays logic low. The following data bytes are read from the next address sequentially defined in the register map. When the Address Pointer reaches 0xF (last register in the register map for reading), the next register to read is the register 0x0. See Figure 6-7 for a graphical representation of the address looping. If the CMD[1:0] bits are equal to ‘01’, the command type is static read. In this case, the register address defined in the COMMAND byte is read continuously. The Address Pointer is not incremented automatically. Continuously clocking SCK while CS stays logic low will continuously read the same register. Reading another register is only possible by aborting the current communication sequence by raising CS and issuing another command. In both Static and Incremental modes, the registers will be updated after each register read is fully performed. If the value of the register changes internally during the read, it will only be updated after the end of the read. The value of each register is latched in the SDO Output Shift register at the first rising edge of SCK of each individual register reading. Figure 6-8 shows the details, bit by bit, of a single register read communication. Figure 6-9 shows the examples of static and incremental read communications. ADCDATA (0x0) CONFIG0 (0x1) CONFIG1 (0x2) CONFIG2 (0x3) CONFIG3 (0x4) IRQ (0x5) MUX (0x6) SCAN (0x7) TIMER (0x8) OF FSETCAL (0x9) GAINCAL (0xA) Reserved (0xB) Reserved (0xC) LOCK (0xD) Reserved (0xE) CRCREG (0xF) FIGURE 6-7: Incremental Read Loop.  2019-2021 Microchip Technology Inc. DS20006180D-page 65 SDO High-Z 0 0 0 FIGURE 6-8: DS20006180D-page 66 A[6] DATA[1] DATA[2] DATA[3] DATA[4] DATA[5] DATA[6] DATA[7] DATA[8] DATA[9] DATA[10] 1 DATA[11] DATA[12] DATA[13] DATA[14] DATA[15] DATA[16] DATA[17] DATA[18] DATA[19] Device Latches SDI on Rising Edge DATA[20] CMD[3] CMD[2] CMD[0] CMD[6] DR_ ST ATUS C RC C FG_ STA TUS POR _ STA TUS DATA[0] DATA[1] DATA[2] DATA[3] DATA[4] DATA[5] DATA[6] DATA[7] DATA[8] DATA[9] DATA[10] DATA[11] DATA[12] DATA[13] DATA[14] DATA[15] DATA[16] DATA[17] DATA[18] DATA[19] DATA[20] DATA[21] DATA[22] DATA[23] DATA[21] CMD[4] CMD[6] Device Latches SDI on Rising Edge DATA[22] DATA[23] CMD[0] CMD[2] CMD[3] CMD[4] CMD[6] CMD[5] 0 0 CMD[7] CMD[7] 1 POR _ STA TUS C RC C FG_ STA TUS DR_ ST ATUS CMD[6] Don’t Care CMD[5] 0 CMD[6] SDI High-Z CMD[7] SDO Don’t Care CMD[7] SDI CMD[6] MCP3461/2/4 CS Device Latches SDO on Falling Edge SCK Don’t Care Don’t Care DATA[0] High-Z SPI Mode 0,0; Example with a 24-Bit Wide Register Located at Address CMD[5:2] CS Device Latches SDO on Falling Edge SCK Don’t Care High-Z SPI Mode 1,1; Example with a 24-Bit Wide Register Located at Address CMD[5:2] Single Register Read SPI Communication.  2019-2021 Microchip Technology Inc. MCP3461/2/4 CS SCK SDI Depends on ADDR 8x Don’t Care Depends on ADDR COMMAND BYTE ... Depends on ADDR ... ADDR Don’t Care CMD[7:6] + ADDR + 01 SDO High-Z 00XXXXXX ADDR Depends on IRQ status and device address Complete READ sequence ADDR 0 Static Read Sequence CS ADDRESS SET 0x0 Depends on ADDR SCK 8x SDI COMMAND BYTE Depends on ADDR+1 ... Depends on Data Format 16x 8x ... 16x ... ADDR Don’t Care Don’t Care ... CMD[7:6] + ADDR + 11 Complete READ sequence 0xF Roll-over SDO High-Z 00XXXXXX ADDR ADDR + 1 ... ADDR = 0xF ADDR = 0x0 ADDR = 0x1 ... ADDR = 0xF 0 Depends on IRQ status and device address Complete READ sequence Complete READ sequence Incremental Read Sequence FIGURE 6-9: Static and Incremental Read SPI Communications.  2019-2021 Microchip Technology Inc. DS20006180D-page 67 MCP3461/2/4 If the COMMAND byte defines a static read of the ADCDATA register (address: 0x0), the ADC data will be present on SDO and will be updated continuously at each read. In this case, when a data ready interrupt happens within a read, the data are not corrupted and will be updated to a new value after the old value has been completely read. The ADC register contains a double buffer that prevents data from being corrupted while reading them. The part will be able to stream output data continuously, with no additional command, if the communication is not stopped with a CS rising edge. Figure 6-10 represents the continuous streaming of incoming ADCDATA, through the SPI port, with both SPI Modes 0,0 and 1,1. CS The Falling Edge After Read Start Clears the DR Interrupt on IRQ Pin Device Latches SDI on Rising Edge The Falling Edge After Read Start Clears the DR Interrupt on IRQ Pin Device Latches SDO on Falling Fdge Don’t Care D ATA1[3 1] D ATA1[2 8] D ATA0[3 1] D ATA1[2 9] D ATA0[0] D ATA0[1] D ATA0[2] D ATA0[3] D ATA0[4] D ATA0[5] D ATA0[8] D ATA0[6] D ATA0[7] D ATA0[9] D ATA0[1 1] D ATA0[1 0] D ATA0[1 3] D ATA0[1 2] D ATA0[1 4] D ATA0[1 5] D ATA0[1 6] D ATA0[1 7] D ATA0[1 8] D ATA0[1 9] D ATA0[2 2] D ATA0[2 0] D ATA0[2 1] D ATA0[2 3] D ATA0[2 4] D ATA0[2 5] D ATA0[2 6] D ATA0[2 7] D ATA0[2 8] D ATA0[3 1] D ATA0[2 9] D ATA0[3 0] Read Start 1 1 0 CMD[6] CMD[6] Hi-Z 0 0 SDO CMD[7] Read Start D ATA1[3 0] A[0] 0 R/W 1 A[3] 0 A[1] 0 A[2] 0 A[4] 0 Don’t Don’t Care care CMD[6] A[5] SDI CMD[7] A[6] SCK SD OChanges Synchronously with the IRQ Falling Edge (DR interrupt flag) only when MS b is Present on SDO timing> tDOD R IRQ DR Interrupt (DATA1 is ready) SPI Mode 0,0; ADC Data Format: 32-Bit CS The Falling Edge After Read Start Clears the DR Interrupt on IRQ Pin Device Latches SDI on Rising Edge The Falling Edge After Read Start Clears the DR Interrupt on IRQ Pin Device Latches SDO on Falling Edge Don’t Care R/W 1 D ATA1[2 8] D ATA1[2 9] D ATA0[0] D ATA1[3 0] D ATA0[1] D ATA0[2] D ATA0[3] D ATA0[5] D ATA0[4] D ATA0[6] D ATA0[7] D ATA0[8] D ATA0[9] D ATA0[1 0] D ATA0[1 1] D ATA0[1 2] D ATA0[1 3] D ATA0[1 4] D ATA0[1 5] D ATA0[1 6] D ATA0[1 7] D ATA0[1 8] D ATA0[1 9] D ATA0[2 0] D ATA0[2 1] D ATA0[2 2] D ATA0[2 3] D ATA0[2 4] D ATA0[2 5] D ATA0[2 6] D ATA0[2 7] D ATA0[2 8] D ATA0[2 9] D ATA0[3 0] Read Start D ATA0[3 1] 1 1 0 CMD[6] Hi-Z CMD[6] 0 CMD[7] SDO 0 Read Start D ATA1[3 1] A[0] 0 A[1] 0 A[2] 0 A[3] 0 A[4] 0 Don’t Don’t Care care CMD[6] A[5] SDI CMD[7] A[6] SCK timing> tDOD R IRQ DR Interrupt (DATA1 is ready) SPI Mode 1,1; ADC Data Format: 32-Bit FIGURE 6-10: DS20006180D-page 68 Continuous ADC Read (Data Streaming) with SPI Mode 0,0 and 1,1.  2019-2021 Microchip Technology Inc. MCP3461/2/4 For continuous reading of ADCDATA in SPI Mode (0,0), once the data have been completely read after a data ready interrupt, the SDO pin will take the MSb value of the previous data at the end of the reading (falling edge of the last SCK clock). If SCK stays Idle at logic low (by definition of Mode 0,0), the SDO pin will be updated at the falling edge of the next data ready pulse (synchronously with the IRQ pin falling edge with an output timing of tDODR) with the new MSb of the data corresponding to the data ready pulse. This mechanism allows the device to continuously read ADC data outputs seamlessly, even in SPI Mode (0,0). In SPI Mode (1,1), the SDO pin stays in the last state (LSb of previous data) after a complete reading, which also allows seamless Continuous Read mode. ADC output data can only be properly read after a tDODR time, after the data ready interrupt is coming on the IRQ pin. The tDODR timing is shorter than the time necessary to input a command on the SDI pin, which ensures proper reading in the case a new read command is triggered by the data ready interrupt. In case of continuous reading (with CS pin kept logic low), the tDODR timing must be carefully taken care of by the MCU, but in general, the interrupt service time is longer than the tDODR timing. Retrieving a data ready interrupt by reading the STATUS byte or reading the IRQ register automatically ensures that the tDODR timing is respected. 6.5 Securing Read Communications through CRC-16 Checksum Since some applications can generate or receive large EMI/EMC interferences and large transient spikes, it is helpful to secure SPI communications as much as possible to maintain data integrity and desired configurations during the lifetime of the application. The communication data on the SDO pin can be secured through the insertion of a Cyclic Redundancy Check (CRC) checksum at the end of each read sequence. The CRC checksum on communications can be enabled or disabled through the EN_CRCCOM bit in the CONFIG3 register. The CRC message ensures the integrity of the read sequence bits transmitted on the SDO pin. The CRC checksum in the MCP3461/2/4 devices uses the 16-bit CRC-16 ANSI polynomial as defined in the IEEE 802.3 standard: x16 + x15 + x2 + 1.  2019-2021 Microchip Technology Inc. This polynomial can also be noted as 0x8005. CRC-16 detects all single and double-bit errors, all errors with an odd number of bits, all burst errors of 16 bits in length or less and most errors for longer bursts. This allows an excellent coverage of the SPI communication errors that can happen in the system, and heavily reduces the risk of a miscommunication, even under noisy environments. When enabled, the CRC checksum (CRCCOM[15:0]) is propagated on SDO after each read communication sequence. In case of a Static Read command, the checksum is propagated after each register read. In case of an Incremental Read command, the checksum is propagated after the last register read in the register map (address 0xF). Figure 6-12 and Figure 6-13 show typical read communications in Static and Incremental Read modes when the EN_CRCCOM bit is enabled. Since the STATUS byte is propagated on SDO, it is part of the first message, and therefore, it is included in the calculation of the first checksum. For subsequent checksum calculations, the message only contains the registers that are effectively read between two checksums. The CRC-16 format displayed on the SDO pin depends on the CRC_FORMAT bit in the CONFIG3 register (see Figure 6-11). It can either be 16-bit or 32-bit format to be compatible with both 16-bit and 32-bit MCUs. The CRCCOM[15:0] bits calculated by the device are not dependent on the format (the device always calculates a 16-bit only CRC checksum). CRC_FORMAT = 0: 16-bit (Default) CRCCOM[15:0] CRC_FORMAT = 1: 32-bit CRCCOM[15:0] FIGURE 6-11: Communications. 0x0000 CRC Format Table for Read The CRC calculation computed by the device is fully compatible with CRC hardware contained in the Direct Memory Access (DMA) of the PIC24 and PIC32 MCU product lines. The CRC message that should be considered in the PIC® device’s DMA is the concatenation of the read sequence and its associated checksum. When the DMA CRC hardware computes this extended message, the resulted checksum should be 0x0000. Any other result indicates that a miscommunication has happened and that the current communication sequence should be stopped and restarted. DS20006180D-page 69 MCP3461/2/4 CS 16x or 32x Depending on CRC Format Depends on ADDR SCK 8x SDI COMMAND BYTE Depends on ADDR 16x or 32x Depending on CRC Format ... ADDRESS SET ADDR Rollover Don’t Care Don’t Care CRC Checksum CMD[7:6] + ADDR + 01 STATUS BYTE High-Z SDO 0 ADDR CRC Checksum Complete Read Sequence Including STATUS Byte = First Message for CRC Calculation FIGURE 6-12: First Checksum ADDR CRC Checksum New Message New Checksum ... SPI Static Read with Communication CRC Enabled. CS ADDRESS SET 0x0 SCK 8x Depends on ADDR Depending on ADDR+1 ... 16x 16x or 32x Depending on CRC Format Depends on Data Format 8x ... 16x 16x or 32x Depending on CRC format ... ADDR SDI Don’t Care COMMAND BYTE Don’t Care ... CMD[7:6] + ADDR + 11 Complete Read Sequence 0xF Rollover SDO High-Z 0 STATUS BYTE ADDR ADDR + 1 ... Complete Read Sequence Including STATUS Byte = First Message for CRC Calculation FIGURE 6-13: DS20006180D-page 70 ADDR = 0xF CRC Checksum ADDR = 0x0 First Checksum ADDR = 0x1 New Message ... ADDR = 0xF CRC Checksum CRC Checksum (not part of register map) New Checksum SPI Incremental Read with Communication CRC Enabled.  2019-2021 Microchip Technology Inc. MCP3461/2/4 6.6 Locking/Unlocking Register Map Write Access The MCP3461/2/4 digital interface includes an advanced security feature that permits locking or unlocking the register map write access. This feature prevents the miscommunication that can corrupt the desired configuration of the device, especially an SPI read becoming an SPI write because of the noisy environment. The last register address of the incremental write loop (0xD: LOCK) contains the LOCK[7:0] bits. If these bits are equal to the password value (0xA5), the register map write access is not locked. Any write can take place and the communications are not protected. The devices are, by default after POR, in an unlocked state (LOCK[7:0] = 0xA5). When the LOCK[7:0] bits are not equal to 0xA5, the register map write access is locked. The register map, and therefore, the full device configuration is writeprotected. Any write to an address other than 0xD will yield no result. All the register addresses, except the address 0xD, become read-only. In this case, if the user wants to change the configuration, the LOCK[7:0] bits have to be reprogrammed back to 0xA5 before sending the desired write command. The LOCK[7:0] bits are located in the last register of the incremental write address loop, so the user can program the whole register map, starting from 0x1 to 0xD, within one continuous write sequence and then lock the configuration at the end of the sequence by writing all zeros (for example) in the address 0xD. 6.7 Detecting Configuration Change Through CRC-16 Checksum on Register Map and its Associated Interrupt Flag In order to prevent internal corruption and to provide additional security on the register map configuration, the MCP3461/2/4 devices include an automatic and continuous CRC checksum calculation on the full register map Configuration bits. This calculation is not the same as the communication CRC checksum described in Section 6.5 “Securing Read Communications through CRC-16 Checksum”. This calculation takes the contents of the register map from addresses, 0x1 to 0xE, and produces a checksum which is held in the CRCCFG[15:0] bits located in the CRCCFG register (address: 0xF). The CRC checksum for the register map uses the 16-bit CRC-16 ANSI polynomial, as defined in the IEEE 802.3 standard: x16+x15+x2+1.  2019-2021 Microchip Technology Inc. Since this feature is intended for protecting the configuration of the device, this calculation is run continuously only when the register map is locked (LOCK[7:0], which is different than 0xA5; see Section 6.6 “Locking/Unlocking Register Map Write Access”). If the register map is unlocked (for example, after POR), the CRCCFG[15:0] bits are cleared and no CRC is calculated. CRCCFG_STATUS and The DR_STATUS, POR_STATUS bits are set to ‘1’ (default) and the CRCCFG[15:0] bits are set to ‘0’ (default) for this calculation as they could vary and lead to unwanted CRC errors. After the DR_STATUS, CRCCFG_STATUS and POR_STATUS bits are cleared (with a read on the IRQ register), the CRC checksum on the register map can be verified by reading all registers in an incremental read sequence and by using the CRC communication. At the second incremental read loop, the checksum provided by the communication CRC should be equal to all zeros if the checksum on the register map is correct. The checksum will be calculated for the first time in 11 DMCLK periods. This first value will then be the reference checksum value and will be latched internally, until an unlocking of the register map happens. The checksum will then be calculated continuously every 11 DMCLK periods and checked against the reference checksum. If the checksum is different than the reference, an interrupt flag will be generated on the CRCCFG_STATUS bit within the STATUS byte on SDO, on the CRCCFG_STATUS bit in the IRQ register and on the IRQ output pin. The interrupt flag is maintained on all three mechanisms until the register map write access is unlocked. When the part write access is unlocked, the interrupt on the IRQ pin will clear immediately and the two other interrupt mechanisms will be cleared when the interrupt has been read (read STATUS byte or read IRQ register). The CRC interrupt can happen even if the IRQ pin is configured as the MDAT modulator output. In this case, the interrupt stays present and forces a logic low output on this pin as long as the LOCK[7:0] register is locked (LOCK[7:0] 0xA5). At power-up, the interrupt is not present and the register map is unlocked. As soon as the user finishes writing its configuration, the user needs to lock the register map (for example, by writing 0x00 in the LOCK bits) to be able to use the interrupt flag and to calculate the checksum of the register map. DS20006180D-page 71 MCP3461/2/4 6.8 Interrupts Description The MCP3461/2/4 devices incorporate multiple interrupt mechanisms to be able to synchronize the device with an MCU and to warn against external perturbations. There are four events that can generate interrupt flags: • • • • Additionally, there are three independent interrupt mechanisms that allow the devices to be implemented in many different applications and many different configurations. A summary of the different mechanisms is available in Table 6-2. Conversion Start Data Ready Power-on Reset CRC Error on the Register Map Configuration TABLE 6-2: INTERRUPT DESCRIPTION SUMMARY TABLE Interrupt Flag Type Description Clearing Procedure STATUS Byte Cleared when STATUS byte clocking is finished Three status bits (DR_STATUS, CRCCFG_STATUS, POR_STATUS) are (on the last SCK falling edge). latched together after device address detection and are clocked out during each command on the SDO STATUS byte. IRQ Register Status Bits IRQ register Status bits can be read when Cleared when the IRQ register reading is finished (on the last SCK falling edge). reading the address 0x5 (IRQ register). IRQ latching happens at the beginning of the IRQ register reading. IRQ Pin State DS20006180D-page 72 • When IRQ_MODE[1] = 0: The IRQ pin can be asserted to logic low by any of the interrupts. • When IRQ_MODE[1] = 1: Only POR and CRC interrupts can assert the IRQ pin to logic-low. • Conversion start interrupt is cleared automatically at the beginning of a new conversion cycle after a TSTP timing. • DR interrupt is cleared by the first SCK falling edge of an ADC read or automatically 16 DMCLK periods before a new data ready in Continuous Conversion mode or in SCAN mode. • POR interrupt is cleared on the first CS falling edge when both AVDD and DVDD monitoring circuits are detecting their power supply to be over their respective thresholds. • CRCCFG interrupt is cleared when the device is unlocked (writing 0xA5 to LOCK register) or when a Fast command ADC start/restart conversion is performed.  2019-2021 Microchip Technology Inc. MCP3461/2/4 6.8.1 CONVERSION DATA READY INTERRUPT The data ready interrupt happens when a new conversion is ready to be read on the ADCDATA register. This event happens synchronously with DMCLK and at each end of conversion. This interrupt is implemented with three different and independent mechanisms: STATUS byte on SDO, IRQ register Status bit and IRQ pin state. 1. 2. STATUS byte on SDO. When the interrupt happens, on the next STATUS byte transmitted on SDO, the DR_STATUS bit is logic low. Once the STATUS byte has been transmitted, the DR_STATUS bit appears as ‘1’ until a new interrupt will be present. If between two STATUS byte transmissions, the interrupt happens once again, the DR_STATUS bit on SDO will appear as ‘0’ on the second reading. IRQ register Status bit. When the interrupt happens, the DR_STATUS bit in the IRQ register will be set to ‘0’. Once the IRQ register has been fully read, this DR_STATUS bit is reset again to ‘1’. If between two readings of the IRQ register, the interrupt happens once again, the IRQ register Status bit will appear as equal to ‘0’ on the second reading. 3. IRQ pin state. The interrupt generates an IRQ pin falling edge (transition to logic low) as soon as it happens. The data ready interrupt is cleared by the first event of the following two events: • First falling edge of SCK during an ADC Output Data register read • 16 DMCLK clock periods before current conversion ends If the user does not read the ADCDATA register in time in Continuous Conversion mode or in SCAN mode, the IRQ pin will automatically reset to its inactive state 16 DMCLK periods prior to the new data ready interrupt. This feature is designed to avoid the case in which the IRQ pin output would always be logic low if the reading of the ADC data were not performed. The user can determine exactly when to expect new data and can respect the tDODR timing in all cases to ensure proper reading of the ADC data. See Figure 6-14 for more details. Transition Time Transition Time tDOD R tDOD R DATA1 can be Read During this Time DATA2 can be Read During this Time SPI ADCDATA REGISTER C OMM AN D By te R ea d A DC D ATA1 R ea d A DC D ATA DATA0 DATA2 DATA1 TCON V 1/DRCLK 1/DRCLK TDRH TDRH IRQ Data Ready Interrupt IRQ is Cleared at First SCK Falling Edge After ADCDATA Read Start FIGURE 6-14: C OMM AN D By te Read ADC DATA2 R ea d A DC D ATA IRQ is Cleared if ADCDATA has Not been Read in Time Data Ready Interrupt IRQ Pin Timing Diagram.  2019-2021 Microchip Technology Inc. DS20006180D-page 73 MCP3461/2/4 6.8.2 CONVERSION CYCLE START INTERRUPT This interrupt is the only one that is selectable and the only one not present in the STATUS byte on SDO and the IRQ register. It is only available on the IRQ pin. The user can enable or disable this output using: • [EN_STP] = 1: Conversion start interrupt output is enabled (default). • [EN_STP] = 0: Conversion start interrupt output is disabled. This interrupt marks the beginning of a conversion cycle. In case of a One-Shot mode or Continuous mode conversion in MUX mode, it marks the start of the sampling in the first conversion (happening after the ADC start-up delay of 256 DMCLK periods). In case of a SCAN mode, it marks the start of the sampling in the first conversion of the first SCAN mode cycle. The host MCU can utilize this interrupt to synchronize the start of the ADC conversion and manage synchronous events together with the conversion process. See Figure 6-15 for more details. This interrupt output generates a falling edge on the IRQ pin and is cleared automatically after a short time, TSTP. ADC_MODE 00 ADC STATUS 11 ADC Shutdown Sta rt-u p 1st C on ve rsi on in e ithe r MU X o r SC AN mo de TADC_SETU P TCON V TST P IRQ Conversion Start IRQ (EN_STP = 1) FIGURE 6-15: 6.8.3 Conversion Start IRQ Timing Diagram. POR INTERRUPT The POR interrupt provides information to the user that either a POR event has happened previously or if the part is in a POR state when the IRQ pin is used. This interrupt is implemented with three different and independent mechanisms: STATUS byte on SDO, IRQ register Status bit and IRQ pin state. 6.8.3.1 STATUS Byte on SDO When the device powers up, on the first STATUS byte transmitted on SDO (first communication), the POR_STATUS is logic low. Once the STATUS byte has been transmitted, the POR_STATUS bit appears as ‘1’ until the part is powered down. If between two STATUS byte transmissions, a POR event happens once again, and if the part is properly repowered up, the POR_STATUS bit on SDO will appear as equal to ‘0’ on the latter reading. This mechanism can only work when the power supplies are back above the POR thresholds, on the analog and digital cores, as retrieving data from the SPI port is not possible when the device is in a POR state. DS20006180D-page 74 Data Ready IRQ 6.8.3.2 IRQ Register Status Bit When the device is powered up, the POR_STATUS bit in the IRQ register will be reset to ‘0’. Once the IRQ register has been fully read, this POR_STATUS bit is reset again to ‘1’. If, between two readings of the IRQ register, a POR event happens once again, the IRQ register Status bit will appear as equal to ‘0’ on the second reading. This mechanism can only work when the power supplies are back above the POR thresholds on the analog and digital cores.  2019-2021 Microchip Technology Inc. MCP3461/2/4 6.8.3.3 IRQ Pin State A logic low state is generated on the IRQ pin as soon as the AVDD or DVDD monitoring circuits detect a power supply drop below their specified threshold. This POR interrupt can only be cleared when both AVDD and DVDD are above their monitoring voltage thresholds. When this condition is met, the POR threshold is cleared by the CS falling edge. This means that if a CS falling edge does not clear the IRQ pin state, the POR event is still in effect. DVDD AVDD This feature can be used by the user to know exactly when the chip has powered up by polling with the CS pin and checking the IRQ pin state at power-up. See Figure 6-16 for more details. Since this is a high-level priority interrupt, this POR interrupt can happen at all times, even when MDAT is enabled. In this case, having a constant logic low bit stream can indicate in this case a probable POR event (or a fully negative ADC saturation output code induced by a large negative input voltage). V POR_A, V POR_D tPOR POR Internal State High-Z IRQ 0 tC SIR Q CS Don’t Care Chip Select Starts Low Clears POR Interrupt FIGURE 6-16: POR IRQ Timing Diagram.  2019-2021 Microchip Technology Inc. DS20006180D-page 75 MCP3461/2/4 6.8.4 CRCCFG ERROR INTERRUPT The CRCCFG interrupt happens when an error in the CRC-16 checksum has been detected in the register map CRC calculation. This interrupt is implemented with three different and independent mechanisms: STATUS byte on SDO, IRQ register Status bit and IRQ pin state. 6.8.4.1 STATUS Byte on SDO When the CRCCFG error happens, on the next STATUS byte transmitted on SDO, the CRCCFG_STATUS bit will be logic low. Once the STATUS byte has been transmitted, the CRCCFG_STATUS bit will then appear as ‘1’ until a new interrupt occurs. If between two STATUS byte transmissions, the error is detected once again, the CRCCFG_STATUS bit on SDO will appear as equal to ‘0’ on the second reading. 6.8.4.2 IRQ Register Status Bit When the CRCCFG error happens, the CRCCFG_STATUS bit in the IRQ register will be set to ‘0’. Once the IRQ register has been fully read, this CRCCFG_STATUS bit will be reset back to ‘1’. If between two readings of the IRQ register, the CRCCFG error happens once again, the IRQ register Status bit will appear as ‘0’ on the second reading. DS20006180D-page 76 6.8.4.3 IRQ Pin State The CRCCFG error generates a Logic Low state on the IRQ pin until it is cleared. The clearing of the CRCCFG error can only be made by “unlocking” the device (by writing 0xA5 in the LOCK[7:0] register or by sending a Fast command start/restart ADC conversion). Unlocking the device stops the CRC calculation and clears the associated interrupt. Sending an ADC start/restart conversion Fast command resets the CRC calculation and clears the interrupt as well. This CRCCFG error can only happen in case of an external perturbation (for example, EMI induced) that would cause the continuous calculation of the CRC on the register map to be erroneous or in the case that the chip integrity has been altered. Since both causes are high-priority issues, the CRCCFG error takes priority over all other interrupts (except POR) and over the MDAT output on the IRQ pin. Note: If MCLK is running before the device has been locked, an interrupt can momentarily occur even if registers have not been corrupted. In such a case, the user needs to send a start/restart conversion Fast command, which will clear the unwanted interrupt and correctly restart the CRC calculations.  2019-2021 Microchip Technology Inc. MCP3461/2/4 7.0 BASIC APPLICATION CONFIGURATION The MCP3461/2/4 devices can be used for various precision Analog-to-Digital Converter applications. The flexibility of its usage is given by the possibility of configuring the ADC to fit the required application. FIGURE 7-1: 7.1 Typical Application for Absolute Voltage Measurement One application of MCP3461/2/4 is to measure the signal provided by the sensors with absolute voltage output. For such applications, the MCP3461/2/4 will rely on an external voltage reference. Figure 7-1 provides an example that uses the MCP3464 ADC with MCP1501 external voltage reference. For best performance, an RC filter and operational amplifier have been placed between the OUT pin of the MCP1501 voltage reference and the REFIN+ input of the MCP3464. MCP3464 Application Example Schematic. The ADC can be used either in differential or Single-Ended mode, thanks to the internal dual multiplexer (Figure 5-1). The user can select the input connection settings from the MUX register (Section 8.7 “MUX Register”) by using the different settings available on the positive and negative inputs of the ADC. The single-ended configuration is achieved by selecting AGND for the VIN- input of the ADC (MUX[3:0] = 1000) or by selecting any CHn input channel for VIN- and connecting the corresponding CHn input channel to AGND.  2019-2021 Microchip Technology Inc. 7.1.1 HIGH-SIDE AND LOW-SIDE CURRENT SENSING The ADC has the ability to perform differential measurements with analog input Common-mode equal to or slightly larger than AVDD, or equal to or slightly lower than AGND (see the Electrical Characteristics table). The user must use a differential input structure and Kelvin connection to achieve the most accurate measurements. An anti-aliasing filter is required to avoid aliasing of the oversampling frequency (DMCLK) back into the baseband of the input signal and possible corruption of the output data. Figure 7-1 provides an example of an anti-aliasing filter. DS20006180D-page 77 MCP3461/2/4 For measurement of voltages that can reach AVDD or a few mV higher, a gain setting of 0.33x is useful since it will increase the input range to 3 x VREF value, so a 1.2V VREF will allow a theoretical input range of 3.6V. The maximum voltage that can be measured is always bounded by AVDD + 0.1V in order to limit excess leakage current at the input pins created by the ESD structures. Therefore, in order to properly measure 3.6V with a 1.2V voltage reference, it is recommended to use an AVDD supply voltage as close as possible to 3.6V. Others act as a single resistor with a value dependent on temperature (pure metal Resistance Thermometer, RTD, and Negative Temperature Coefficient resistor, NTC). To accurately measure the signal from these sensors, most often the REFIN+ is connected to the same power supply of the sensor (Figure 7-4) as long as this will respect the Electrical Characteristics table. R1 7.1.2 THERMOCOUPLE CONNECTION One of the most used temperature transducers in the industry is the thermocouple. The thermocouples provide a voltage dependent on the temperature difference between cold junction and hot junction. This voltage is in the order of magnitude of few tens of µV/°C, which require amplification that can be provided by the internal gain stage of the ADC. VIN+ MCP3461 24-Bit ADC VIN- I2C FIGURE 7-2: to MCP3461. Thermocouple Connection The connection of the thermocouple to the ADC requires minimal extra components and it’s recommended to use a differential input structure. The cold junction can be measured using a digital temperature sensor, such as MCP9804 connected to the MCU. If high accuracy is not required, the cold junction temperature can be estimated directly with the internal temperature sensor of the ADC (Figure 7-2). 7.2 Typical Application for Ratiometric Voltage Measurement A wide range of sensors provides an output voltage directly related to the power supply of the sensors. These sensors are known as ratiometric output. These sensors often have Wheatstone bridge structure, like pressure sensors or load cells (Figure 7-3). R2 Vin+ Sensor Anti Aliasing  Filter REFIN + M CP3461 Vin- REFIN- R1 C1 C2 AGND DGND FIGURE 7-3: Wheatstone Bridge Ratiometric Connection. DS20006180D-page 78 RTD In p u t S ig n a l V in + V in - FIGURE 7-4: Connection. 7.3 R E F IN + M CP3461 R E F IN - RTD Ratiometric Power Supply Design and Bypassing In any system, the analog ICs (such as references or operational amplifiers) are always connected to the analog ground plane. The MCP3461/2/4 should also be considered as sensitive analog components and connected to the analog ground plane. The ADC features two pairs of power supply voltage pins: AGND and AVDD, DGND and DVDD. For best performance, it is recommended to keep the two pairs of pins connected to two different networks (Figure 7-5). This way, the design will feature two ground traces and two power supplies (Figure 7-6). The analog circuitry (including MCP3461/2/4) and the digital circuitry (MCU) should have separate power supplies and return paths to the external ground reference, as described in Figure 7-5. An example of a typical power supply circuit, with different paths for analog and digital return circuit, is shown in Figure 7-6. A possible split example is shown in Figure 7-7, where the ground star connection can be located underneath the device with the exposed pad. The split here, between analog and digital, can be done under the device, and AVDD and DVDD can be connected together with lines coming under the ground plane. The two separate return paths eventually share a unique connection point (star connection) in order to minimize coupling between the two power supply domains. Another possibility, sometimes easier to implement in terms of PCB layout, is to consider the MCP3461/2/4 as an analog component, and connect both AVDD and DVDD together, and AGND and DGND together, with a star connection. In this scheme, the decoupling capacitors may be larger, due to the ripple on the digital power supply (caused by the digital filters and the SPI interface of the MCP3461/2/4), now causing glitches on the analog power supply.  2019-2021 Microchip Technology Inc. MCP3461/2/4 Figure 7-6 shows an example of a power supply schematic with separate DVDD and AVDD. A high-current LDO (MCP1825) was used for the DVDD line in order to be able to power the MCU and other peripherals attached to the MCU. A high PSRR LDO is used (MCP1754) for the AVDD that goes to the ADC and a few other components sensitive to noise. The NET tie is used to separate DGND from AGND. ID IA 0.1 μF C 0.1 μF VA AVDD DVDD VD MCP346x MCU DGND AGND IA ID “Star” Point D-= A-= FIGURE 7-5: Separating Digital and Analog Ground by Using a Star Connection. VIN VOUT 3 C44 10—F 5V_USB U4 LM1117-5V MRA4005 VIN GND 2 +5V USB +9V IN 1 U3 MCP1754-3.3V GND GND VIN VOUT 3 3.3A 2 1 C15 10uF TANT-B VOUT 3 1 4 2 3 GND D1 1 3 2 Power Jack 2.5mm GND TANT-B J9 GND 9V J10 C10 0.1—F TANT-B 0603 GND GND 3.3D C45 10—F C11 0.1—F 0603 2 1 U2 MCP1825S-3.3V GND 5V C14 0.1—F 0603 GND Net Tie GND GND GNDA GNDA C12 0.1—F 0603 GNDA GNDA C13 10—F TANT-B GNDA FIGURE 7-6: Power Supply with Separate Lines for Analog and Digital Sections. Note the “Net Tie” Object that Represents the Star Ground Connection. MCLK DGND DVDD DIGITAL AVDD AGND ANALOG 20 19 18 17 16 REFIN- 1 15 REFIN+ 2 14 SDO EP 21 CH0 3 CH1 4 8 CH4 CH5 13 SDI 12 SCK 11 CS 9 10 CH7 7 CH6 6 CH3 CH2 5 IRQ/MDAT When remote sensors are used to reduce sensitivity to external influences, such as EMI, the wires that connect the sensor to the ADC should form a twisted pair. Ferrite beads can be used between the digital and analog ground planes to keep high-frequency noise from entering the device. The ferrite bead is recommended to be low resistance. FIGURE 7-7: Separation of Analog and Digital Circuits on Layout.  2019-2021 Microchip Technology Inc. DS20006180D-page 79 MCP3461/2/4 7.4 SPI Interface Digital Crosstalk The MCP3461/2/4 incorporates a high-speed 20 MHz SPI digital interface. This interface can induce crosstalk, especially with the outer channels closer to the SPI digital pins (CH7, for example), if it is running at full speed without any precautions. The crosstalk is caused by the switching noise created by the digital SPI signals. This crosstalk would negatively impact the SNR in this case. The noise is attenuated if proper separation between the analog and digital power supplies is put in place (see Section 7.3 “Power Supply Design and Bypassing”). In order to further remove the influence of the SPI communication on measurement accuracy, it is recommended to add series resistors on the SPI lines to reduce the current spikes caused by the digital switching noise (see Figure 7-1, where these resistors have been implemented). The resistors also help to keep the level of electromagnetic emissions low. The measurement graphs provided in this MCP3461/2/4 data sheet have been performed with 100 series resistors connected on each SPI I/O pin. Measurement accuracy disturbances have not been observed, even at 20 MHz interfacing. The switching noise is also a linear function of the DVDD supply voltage. In order to reduce further the influence of the switching noise caused by SPI transmissions, the DVDD digital power supply voltage should be kept as low as possible. DS20006180D-page 80  2019-2021 Microchip Technology Inc. MCP3461/2/4 8.0 INTERNAL REGISTERS The device has a total of 16 internal registers, which are made of volatile memory. Table 8-1 shows the summary of the registers. These registers are accessible sequentially. TABLE 8-1: INTERNAL REGISTERS SUMMARY Address Register Name No. of Bits R/W Description 0x0 ADCDATA 4/16/32 R 0x1 CONFIG0 8 R/W 0x2 CONFIG1 8 R/W Prescale and OSR settings. 0x3 CONFIG2 8 R/W ADC boost and gain settings, auto-zeroing settings for analog multiplexer, voltage reference and ADC. 0x4 CONFIG3 8 R/W Conversion mode, data and CRC format settings, enable for CRC on communications, enable for digital offset and gain error calibrations. 0x5 IRQ 8 R/W IRQ Status bits and IRQ mode settings, enable for Fast commands and for conversion start pulse. Latest A/D conversion data output value (16 or 32 bits depending on DATA_FORMAT[1:0]) or modulator output stream (4-bit wide) in MDAT Output mode. ADC Operating mode, Master Clock mode and Input Bias Current Source mode. 0x6 MUX 8 R/W Analog multiplexer input selection (MUX mode only). 0x7 SCAN 24 R/W SCAN mode settings. 0x8 TIMER 24 R/W Delay value for TIMER between each SCAN cycle. 0x9 OFFSETCAL 24 R/W ADC digital offset calibration value. ADC digital gain calibration value. 0xA GAINCAL 24 R/W 0xB RESERVED 24 R/W 0xC RESERVED 8 R/W 0xD LOCK 8 R/W 0xE RESERVED 16 R/W 0xF CRCCFG 16 R  2019-2021 Microchip Technology Inc. Password value for SPI Write mode locking. CRC checksum for the device configuration. DS20006180D-page 81 MCP3461/2/4 8.1 ADCDATA Register Name Bits Address Cof ADCDATA 4/16/32 0x0 R REGISTER 8-1: ADCDATA: ADC CHANNEL DATA OUTPUT REGISTER R-0 ADCDATA[15:0] bit 15 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 23-0 x = Bit is unknown ADCDATA[15:0]: ADC Data Output Code Output code from ADC. The data are post-calibration if the EN_OFFCAL or EN_GAINCAL bits are enabled. The data can be formatted in 16/32-bit modes, depending on the DATA_FORMAT[1:0] settings (see Section 5.6 “ADC Output Data Format”). The ADC Channel Data Output registers always contain the most recent A/D conversion data. The register is updated at each data ready internal signal (depends on OSR and CONV_MODE settings). The register is latched at the start of each SPI Read command. The register is double buffered to avoid loss of data. There is a small time delay, tDODR, after each data ready where the user has to wait for the data to be available. Otherwise, data corruption can happen (when the internal data are refreshed). When the IRQ_MODE[1:0] = 1x, this register becomes a 4-bit wide register containing the MDAT output codes, which are the outputs of the modulator that are represented by four comparator outputs (COMP[3:0], see Section 5.4.2 “Modulator Output Block”). DS20006180D-page 82  2019-2021 Microchip Technology Inc. MCP3461/2/4 8.2 CONFIG0 Register Name Bits Address Cof CONFIG0 8 0x1 R/W REGISTER 8-2: R/W-1 CONFIG0: CONFIGURATION REGISTER 0 R/W-1 R/W-0 CONFIG0[7:6] R/W-0 R/W-0 CLK_SEL[1:0] R/W-0 R/W-0 CS_SEL[1:0] R/W-0 ADC_MODE[1:0] bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-6 CONFIG0[7:6]: Full Shutdown Mode Enable These bits are writable but have no effect except that they force Full Shutdown mode when they are set to ‘00’ and when all other CONFIG0 bits are set to ‘0’. bit 5-4 CLK_SEL[1:0]: Clock Selection 11 = Internal clock is selected and AMCLK is present on the analog master clock output pin 10 = Internal clock is selected and no clock output is present on the CLK pin 01 = External digital clock 00 = External digital clock (default) bit 3-2 CS_SEL[1:0]: Current Source/Sink Selection Bits for Sensor Bias (source on VIN+/Sink on VIN-) 11 = 15 µA is applied to the ADC inputs 10 = 3.7 µA is applied to the ADC inputs 01 = 0.9 µA is applied to the ADC inputs 00 = No current source is applied to the ADC inputs (default) bit 1-0 ADC_MODE[1:0]: ADC Operating Mode Selection 11 = ADC Conversion mode 10 = ADC Standby mode 01 = ADC Shutdown mode 00 = ADC Shutdown mode (default)  2019-2021 Microchip Technology Inc. DS20006180D-page 83 MCP3461/2/4 8.3 CONFIG1 Register Name Bits Address Cof CONFIG1 8 0x2 R/W REGISTER 8-3: R/W-0 CONFIG1: CONFIGURATION REGISTER 1 R/W-0 R/W-0 PRE[1:0] R/W-0 R/W-1 R/W-1 R/W-0 OSR[3:0] R/W-0 RESERVED[1:0] bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 PRE[1:0]: Prescaler Value Selection for AMCLK 11 = AMCLK = MCLK/8 10 = AMCLK = MCLK/4 01 = AMCLK = MCLK/2 00 = AMCLK = MCLK (default) bit 5-2 OSR[3:0]: Oversampling Ratio for Delta-Sigma A/D Conversion 1111 = OSR: 98304 1110 = OSR: 81920 1101 = OSR: 49152 1100 = OSR: 40960 1011 = OSR: 24576 1010 = OSR: 20480 1001 = OSR: 16384 1000 = OSR: 8192 0111 = OSR: 4096 0110 = OSR: 2048 0101 = OSR: 1024 0100 = OSR: 512 0011 = OSR: 256 (default) 0010 = OSR: 128 0001 = OSR: 64 0000 = OSR: 32 bit 1-0 RESERVED[1:0]: Should always be set to ‘00’ DS20006180D-page 84 x = Bit is unknown  2019-2021 Microchip Technology Inc. MCP3461/2/4 8.4 CONFIG2 Register Name Bits Address Cof CONFIG2 8 0x3 R/W REGISTER 8-4: R/W-1 CONFIG2: CONFIGURATION REGISTER 2 R/W-0 R/W-0 BOOST[1:0] R/W-0 R/W-1 GAIN[2:0] R/W-0 R/W-1 AZ_MUX R/W-1 RESERVED[1:0] bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-6 BOOST[1:0]: ADC Bias Current Selection 11 = ADC channel has current x 2 10 = ADC channel has current x 1 (default) 01 = ADC channel has current x 0.66 00 = ADC channel has current x 0.5 bit 5-3 GAIN[2:0]: ADC Gain Selection 111 = Gain is x64 (x16 analog, x4 digital) 110 = Gain is x32 (x16 analog, x2 digital) 101 = Gain is x16 100 = Gain is x8 011 = Gain is x4 010 = Gain is x2 001 = Gain is x1 (default) 000 = Gain is x1/3 bit 2 AZ_MUX: Auto-Zeroing MUX Setting 1 = ADC auto-zeroing algorithm is enabled. This setting multiplies by two the conversion time and does not allow Continuous Conversion mode operation (which is then replaced by a series of consecutive One-Shot mode conversions). 0 = Analog input multiplexer auto-zeroing algorithm is disabled (default) bit 1-0 RESERVED[1:0]: Should always be set to ‘11’  2019-2021 Microchip Technology Inc. DS20006180D-page 85 MCP3461/2/4 8.5 CONFIG3 Register Name Bits Address Cof CONFIG3 8 0x4 R/W REGISTER 8-5: R/W-0 R/W-0 CONV_MODE[1:0] CONFIG3: CONFIGURATION REGISTER 3 R/W-0 R/W-0 DATA_FORMAT[1:0] R/W-0 R/W-0 R/W-0 R-0 CRC_FORMAT EN_CRCCOM EN_OFFCAL EN_GAINCAL bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-6 CONV_MODE[1:0]: Conversion Mode Selection 11 = Continuous Conversion mode or continuous conversion cycle in SCAN mode 10 = One-shot conversion or one-shot cycle in SCAN mode and sets ADC_MODE[1:0] to ‘10’ (Standby) at the end of the conversion or at the end of the conversion cycle in SCAN mode 0x = One-shot conversion or one-shot cycle in SCAN mode and sets ADC_MODE[1:0] to ‘0x’ (ADC Shutdown) at the end of the conversion or at the end of the conversion cycle in SCAN mode (default). bit 5-4 DATA_FORMAT[1:0]: ADC Output Data Format Selection 11 = 32-bit (17-bit right justified data plus Channel ID): CHID[3:0] plus SGN extension (12 bits) plus 16-bit ADC data; allows overrange with the SGN extension 10 = 32-bit (17-bit right justified data): SGN extension (16-bit) plus 16-bit ADC data; allows overrange with the SGN extension 01 = 32-bit (16-bit left justified data): 16-bit ADC data plus 0x0000 (16-bit); does not allow overrange (ADC code locked to 0xFFFF or 0x8000) 00 = 16-bit (default ADC coding): 16-bit ADC data; does not allow overrange (ADC code locked to 0xFFFF or 0x8000) (default) bit 3 CRC_FORMAT: CRC checksum format selection on read communications (does not affect CRCCFG coding) 1 = CRC-16 followed by 16 zeros (32-bit format) 0 = CRC-16 only (16-bit format) (default) bit 2 EN_CRCCOM: CRC Checksum Selection on Read Communications (does not affect CRCCFG calculations) 1 = CRC on communication enabled 0 = CRC on communication disabled (default) bit 1 EN_OFFCAL: Enable Digital Offset Calibration 1 = Enabled 0 = Disabled (default) bit 0 EN_GAINCAL: ADC Operating Mode Selection 1 = Enabled 0 = Disabled (default) DS20006180D-page 86  2019-2021 Microchip Technology Inc. MCP3461/2/4 8.6 IRQ Register Name Bits Address Cof IRQ 8 0x5 R/W REGISTER 8-6: IRQ: INTERRUPT REQUEST REGISTER U-0 R-1 R-1 R-1 — DR_STATUS CRCCFG_STATUS POR_STATUS R/W-0 R/W-0 R/W-1 IRQ_MODE[1:0](1) EN_FASTCMD R/W-1 EN_STP bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 Unimplemented: Read as ‘0’ bit 6 DR_STATUS: Data Ready Status Flag 1 = ADCDATA has not been updated since last reading or last Reset (default) 0 = New ADCDATA ready for reading bit 5 CRCCFG_STATUS: CRC Error Status Flag Bit for Internal Registers 1 = CRC error has not occurred for the Configuration registers (default) 0 = CRC error has occurred for the Configuration registers bit 4 POR_STATUS: POR Status Flag 1 = POR has not occurred since the last reading (default) 0 = POR has occurred since the last reading bit 3-2 IRQ_MODE[1:0]: Configuration for the IRQ/MDAT Pin(1) IRQ_MODE[1]: IRQ/MDAT Selection 1 = MDAT output is selected; only POR and CRC interrupts can be present on this pin and take priority over the MDAT output 0 = IRQ output is selected; all interrupts can appear on the IRQ/MDAT pin (default) IRQ_MODE[0]: IRQ Pin Inactive State Selection 1 = The Inactive state is logic high (does not require a pull-up resistor to DVDD) 0 = The Inactive state is High-Z (requires a pull-up resistor to DVDD) (default) bit 1 EN_FASTCMD: Enable Fast Commands in the COMMAND Byte 1 = Fast commands are enabled (default) 0 = Fast commands are disabled bit 0 EN_STP: Enable Conversion Start Interrupt Output 1 = Enabled (default) 0 = Disabled Note 1: When IRQ_MODE[1:0] = 10 or 11, the modulator output codes (MDAT stream) are available at both the MDAT pin and ADCDATA register (0x0).  2019-2021 Microchip Technology Inc. DS20006180D-page 87 MCP3461/2/4 8.7 MUX Register Name Bits Address Cof MUX 8 0x6 R/W REGISTER 8-7: R/W-0 MUX: MULTIPLEXER REGISTER R/W-0 R/W-0 R/W-0 R/W-0 MUX_VIN+[3:0](2,3) R/W-0 R/W-0 R/W-1 MUX_VIN-[3:0](2,3) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-4 MUX VIN+[3:0]: MUX VIN+ Input Selection(2,3) 1111 = Internal VCM 1110 = Internal Temperature Sensor Diode M (TEMP Diode M)(1) 1101 = Internal Temperature Sensor Diode P (TEMP Diode P)(1) 1100 = REFIN1011 = REFIN+ 1010 = Reserved (do not use) 1001 = AVDD 1000 = AGND 0111 = CH7 0110 = CH6 0101 = CH5 0100 = CH4 0011 = CH3 0010 = CH2 0001 = CH1 0000 = CH0 (default) bit 3-0 MUX VIN-[3:0]: MUX VIN- Input Selection(2,3) 1111 = Internal VCM 1110 = Internal Temperature Sensor Diode M (TEMP Diode M)(1) 1101 = Internal Temperature Sensor Diode P (TEMP Diode P)(1) 1100 = REFIN1011 = REFIN+ 1010 = Reserved (do not use) 1001 = AVDD 1000 = AGND 0111 = CH7 0110 = CH6 0101 = CH5 0100 = CH4 0011 = CH3 0010 = CH2 0001 = CH1 (default) 0000 = CH0 Note 1: 2: 3: x = Bit is unknown Selects the internal temperature sensor diode and forces a fixed current through it. For a correct temperature reading, the MUX[7:0] selection should be equal to 0xDE. For MCP3462, the codes, ‘0111/0110/0101/0100’, correspond to a floating input and should be avoided. For MCP3461, the codes, ‘0111/0110/0101/0100/0011/0010’, correspond to a floating input and should be avoided. DS20006180D-page 88  2019-2021 Microchip Technology Inc. MCP3461/2/4 8.8 SCAN Register Name Bits Address Cof SCAN 24 0x7 R/W REGISTER 8-8: R/W-0 SCAN: SCAN MODES SETTINGS REGISTER R/W-0 R/W-0 DLY[2:0] R/W-0 U-0 RESERVED — bit 23 bit 16 R/W-0 R/W-0 R/W-0 R/W-0 OFFSET VCM AVDD TEMP R/W-0 R/W-0 R/W-0 R/W-0 SCAN_DIFF_CH[D:A] bit 15 R/W-0 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-0 SCAN_SE_CH[7:0] bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 23-21 DLY[1:0]: Delay Time (TDLY_SCAN) Between Each Conversion During a SCAN Cycle 111 = 512 * DMCLK 110 = 256 * DMCLK 101 = 128 * DMCLK 100 = 64 * DMCLK 011 = 32 * DMCLK 010 = 16 * DMCLK 001 = 8 * DMCLK 000 = 0: No Delay (default) bit 20 Reserved: Should be set to ‘0’ bit 19-16 Unimplemented: Read as ‘0’ bit 15-0 SCAN Channel Selection (see Table 5-14 for the complete description of the list)  2019-2021 Microchip Technology Inc. DS20006180D-page 89 MCP3461/2/4 8.9 TIMER Register Name Bits Address Cof TIMER 24 0x8 R/W REGISTER 8-9: TIMER: TIMER DELAY VALUE REGISTER R/W-0 TIMER[23:0] bit 23 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 23-0 x = Bit is unknown TIMER[23:0]: Selection Bits for Time Interval (TTIMER_SCAN) Between Two Consecutive SCAN Cycles (when CONV_MODE[1:0] = 11) 0xFFFFFF: TTIMER_SCAN = 16777215 * DMCLK 0xFFFFFE: TTIMER_SCAN = 16777214 * DMCLK • • • 0x000002: TTIMER_SCAN = 2 * DMCLK 0x000001: TTIMER_SCAN = 1 * DMCLK 0x000000: TTIMER_SCAN = 0: No delay (default) DS20006180D-page 90  2019-2021 Microchip Technology Inc. MCP3461/2/4 8.10 OFFSETCAL Register Name Bits Address Cof OFFSETCAL 24 0x9 R/W REGISTER 8-10: OFFSETCAL: OFFSET CALIBRATION REGISTER R/W-0 OFFSETCAL[23:0] bit 23 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 23-0 8.11 x = Bit is unknown OFFSETCAL[23:0]: Offset Error Digital Calibration Code (two’s complement, MSb first coding) See Section 5.12 “Digital System Offset and Gain Calibrations”. GAINCAL Register Name Bits Address Cof GAINCAL 24 0xA R/W REGISTER 8-11: GAINCAL: GAIN CALIBRATION REGISTER R/W-1 R/W-0 GAINCAL[23:0] bit 23 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 23-0 x = Bit is unknown GAINCAL[23:0]: Gain Error Digital Calibration Code (unsigned, MSb first coding) The GAINCAL[23:0] default value is 800000, which provides a gain of 1x. See Section 5.12 “Digital System Offset and Gain Calibrations”.  2019-2021 Microchip Technology Inc. DS20006180D-page 91 MCP3461/2/4 8.12 RESERVED Register Name Bits Address Cof RESERVED 24 0xB R/W REGISTER 8-12: RESERVED REGISTER R/W-0x900000 RESERVED[23:0] bit 23 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared RESERVED[23:0]: Should be set to 0x900000 Bit 23-0 8.13 x = Bit is unknown RESERVED Register Name Bits Address Cof RESERVED 8 0xC R/W REGISTER 8-13: RESERVED REGISTER R/W-0x50 RESERVED[7:0] bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared Bit 7-0 x = Bit is unknown RESERVED[7:0]: Should be set to 0x50 DS20006180D-page 92  2019-2021 Microchip Technology Inc. MCP3461/2/4 8.14 LOCK Register Name Bits Address Cof LOCK 8 0xD R/W REGISTER 8-14: R/W-1 LOCK: SPI WRITE MODE LOCKING PASSWORD VALUE REGISTER R/W-0 R/W-1 R/W-0 R/W-0 R/W-1 R/W-0 R/W-1 LOCK[7:0] bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 8.15 x = Bit is unknown LOCK[7:0]: Write Access Password Entry Code 0xA5 = Write access is allowed on the full register map. CRC on register map values is not calculated (CRCCFG[15:0] = 0x0000) – Default. Any code except 0xA5 = Write access is not allowed on the full register map. Only the LOCK register is writable. CRC on register map is calculated continuously only when DMCLK is running. RESERVED Register Name Bits Address Cof RESERVED 16 0xE R/W REGISTER 8-15: RESERVED REGISTER R/W (default depends on product denomination) RESERVED[15:0] bit 15 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared Bit 15-0 x = Bit is unknown RESERVED[15:0]: Should be set to: MCP3461: 0x0008 MCP3462: 0x0009 MCP3464: 0x000B  2019-2021 Microchip Technology Inc. DS20006180D-page 93 MCP3461/2/4 8.16 CRCCFG Register Name Bits Address Cof CRCCFG 16 0xF R REGISTER 8-16: CRCCFG: CRC CONFIGURATION REGISTER R/W-0 CRCCFG[15:0] bit 15 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-0 x = Bit is unknown CRCCFG[15:0]: CRC-16 Checksum Value CRC-16 checksum is continuously calculated internally based on the register map configuration settings when the device is locked (LOCK[7:0] is different than 0xA5). DS20006180D-page 94  2019-2021 Microchip Technology Inc. MCP3461/2/4 9.0 PACKAGING INFORMATION 9.1 Package Marking Information(2) 20-Lead UQFN (3 x 3 x 0.55 mm) PIN 1 Example XXX YYWW NNN PIN 1 AAE 2112 256 Part Number Code SPI Device Address MCP3461T-E/NC AAE 01(2) MCP3462T-E/NC AAF 01(2) MCP3464T-E/NC AAG 01(2) 20-Lead TSSOP (6.5 x 4.4 x 1 mm)(3) Example XXXXXXXX XXXXXNNN MCP3464 EST e3 256 YYWW 2112 Legend: XX...X Y YY WW NNN e3 * Note Customer-specific information Year code (last digit of calendar year) Year code (last 2 digits of calendar year) Week code (week of January 1 is week ‘01’) Alphanumeric traceability code Pb-free JEDEC designator for Matte Tin (Sn) This package is Pb-free. The Pb-free JEDEC designator ( e3 ) can be found on the outer packaging for this package. 1: In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. 2: Denotes the device default SPI address option. Device only responds to SPI commands if CMD[7:6] matches the SPI device address for each command (see Section 6.2.2 “Device Address Bits (CMD[7:6])”). 3: The 20-Lead TSSOP package allows up to 8 characters per line as shown here. Currently only 7 characters are being used as shown in the example.  2019-2021 Microchip Technology Inc. DS20006180D-page 95 MCP3461/2/4 20-Lead Ultra Thin Plastic Quad Flat, No Lead Package 1&- 3x3 mm Body [UQFN] (Formerly Q3DE; SST Legacy Package) Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging D NOTE 1 A B N 1 2 E (DATUM B) (DATUM A) 2X 0.075 C 2X TOP VIEW 0.075 C 0.10 C C SEATING PLANE A1 A 20X (A3) SIDE VIEW 0.08 C 0.10 C A B D2 0.10 See Detail A C A B e 2 E2 2 1 NOTE 1 K N 20X b 0.10 0.05 e C A B C BOTTOM VIEW Microchip Technology Drawing C04-264A Sheet 1 of 2 DS20006180D-page 96  2019-2021 Microchip Technology Inc. MCP3461/2/4 20-Lead Ultra Thin Plastic Quad Flat, No Lead Package1&- 3x3 mm Body [UQFN] (Formerly Q3DE; SST Legacy Package) Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging (b) b1 L DETAIL A Units Dimension Limits N Number of Terminals e Pitch A Overall Height Standoff A1 A3 Terminal Thickness Overall Length D Exposed Pad Length D2 E Overall Width E2 Exposed Pad Width b Terminal Width (Inner) b1 Terminal Width (Outer) L Terminal Length K Terminal-to-Exposed-Pad MIN 0.50 0.00 1.60 1.60 0.15 0.35 0.20 MILLIMETERS NOM 20 0.40 BSC 0.55 0.02 0.15 REF 3.00 BSC 1.70 3.00 BSC 1.70 0.15 REF 0.20 0.40 - MAX 0.60 0.05 1.80 1.80 0.25 0.45 - Notes: 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. Package is saw singulated 3. Dimensioning and tolerancing per ASME Y14.5M BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only. Microchip Technology Drawing C04-264A Sheet 2 of 2  2019-2021 Microchip Technology Inc. DS20006180D-page 97 MCP3461/2/4 20-Lead Ultra Thin Plastic Quad Flat, No Lead Package1&- 3x3 mm Body [UQFN] (Formerly Q3DE; SST Legacy Package) Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging C1 X2 EV 20 ØV 1 2 C2 Y2 EV G1 Y1 X1 E SILK SCREEN RECOMMENDED LAND PATTERN Units Dimension Limits Contact Pitch E X2 Optional Center Pad Width Optional Center Pad Length Y2 Contact Pad Spacing C1 Contact Pad Spacing C2 Contact Pad Width (X20) X1 Contact Pad Length (X20) Y1 Contact Pad to Center Pad (X20) G1 Thermal Via Diameter V Thermal Via Pitch EV MIN MILLIMETERS NOM 0.40 BSC MAX 1.80 1.80 3.00 3.00 0.20 0.80 0.20 0.30 1.00 Notes: 1. Dimensioning and tolerancing per ASME Y14.5M BSC: Basic Dimension. Theoretically exact value shown without tolerances. 2. For best soldering results, thermal vias, if used, should be filled or tented to avoid solder loss during reflow process Microchip Technology Drawing C04-2264A DS20006180D-page 98  2019-2021 Microchip Technology Inc. MCP3461/2/4  2019-2021 Microchip Technology Inc. DS20006180D-page 99 MCP3461/2/4 DS20006180D-page 100  2019-2021 Microchip Technology Inc. MCP3461/2/4 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2019-2021 Microchip Technology Inc. DS20006180D-page 101 MCP3461/2/4 NOTES: DS20006180D-page 102  2019-2021 Microchip Technology Inc. MCP3461/2/4 APPENDIX A: REVISION HISTORY Revision D (May 2021) • Updated Electrical Characteristics table Revision C (April 2021) • Updated size for 20-Lead TSSOP package throughout the document • Updated Features • Updated Section 2.1, Noise Specifications • Updated Equation 2-1 and Equation 2-2 • Updated Table 2-1 and Table 2-2 Revision B (March 2020) • Added 20-Lead TSSOP package • Added Section 5.9.2, Partial Shutdown Mode • Updated Electrical Characteristics table: - Added Partial Shutdown Specs - Added Specs for Analog and Digital Full Shutdown at +105°C and +125°C • Updated Figure 2-32 and Figure 2-33 • Updated Equation 5-1 Revision A (March 2019) • Initial release of this document  2019-2021 Microchip Technology Inc. DS20006180D-page 103 MCP3461/2/4 NOTES: DS20006180D-page 104  2019-2021 Microchip Technology Inc. MCP3461/2/4 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. X(1) PART NO. Device Tape and Reel X /XX Temperature Range Package Device: MCP3461/2/4: Tape and Reel: T = Tape and Reel(1) Temperature Range: E = -40C to +125C (Extended) Package: NC = Ultra Small Leadless Package, 3 mm x 3 mm 20-Lead UQFN = Plastic Thin Shrink Small Outline, 6.5 x 4.4 x 1 mm 20-Lead TSSOP ST Examples: a) MCP3461T-E/NC: b) MCP3462T-E/NC: c) MCP3464T-E/NC: d) MCP3461T-E/ST: e) MCP3462T-E/ST: f) MCP3464T-E/ST: Two/Four/Eight-Channel, 153.6 ksps, Low Noise, 16-Bit Delta Sigma ADC Note 1: 2:  2019-2021 Microchip Technology Inc. Single Channel ADC, Tape and Reel, Extended Temperature, 20-Lead UQFN Dual Channel ADC, Tape and Reel, Extended Temperature, 20-Lead UQFN Quad Channel ADC, Tape and Reel, Extended Temperature, 20-Lead UQFN Single Channel ADC, Tape and Reel, Extended Temperature, 20-Lead TSSOP Dual Channel ADC, Tape and Reel, Extended Temperature, 20-Lead TSSOP Quad Channel ADC, Tape and Reel, Extended Temperature, 20-Lead TSSOP Tape and Reel identifier only appears in the catalog part number description. This identifier is used for ordering purposes and is not printed on the device package. Check with your Microchip Sales Office for package availability with the Tape and Reel option. The device SPI Address ‘01’ is the default address option. Contact Microchip Sales Office for other device address option ordering procedure. DS20006180D-page 105 MCP3461/2/4 NOTES: DS20006180D-page 106  2019-2021 Microchip Technology Inc. Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specifications contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is secure when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods being used in attempts to breach the code protection features of the Microchip devices. We believe that these methods require using the Microchip products in a manner outside the operating specifications contained in Microchip's Data Sheets. Attempts to breach these code protection features, most likely, cannot be accomplished without violating Microchip's intellectual property rights. • Microchip is willing to work with any customer who is concerned about the integrity of its code. • Neither Microchip nor any other semiconductor manufacturer can guarantee the security of its code. Code protection does not mean that we are guaranteeing the product is "unbreakable." Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip's code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication is provided for the sole purpose of designing with and using Microchip products. Information regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. THIS INFORMATION IS PROVIDED BY MICROCHIP "AS IS". MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION INCLUDING BUT NOT LIMITED TO ANY IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE OR WARRANTIES RELATED TO ITS CONDITION, QUALITY, OR PERFORMANCE. IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE INFORMATION OR ITS USE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY RELATED TO THE INFORMATION OR ITS USE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THE INFORMATION. Use of Microchip devices in life support and/or safety applications is entirely at the buyer's risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights unless otherwise stated. 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AgileSwitch, APT, ClockWorks, The Embedded Control Solutions Company, EtherSynch, FlashTec, Hyper Speed Control, HyperLight Load, IntelliMOS, Libero, motorBench, mTouch, Powermite 3, Precision Edge, ProASIC, ProASIC Plus, ProASIC Plus logo, QuietWire, SmartFusion, SyncWorld, Temux, TimeCesium, TimeHub, TimePictra, TimeProvider, WinPath, and ZL are registered trademarks of Microchip Technology Incorporated in the U.S.A. Adjacent Key Suppression, AKS, Analog-for-the-Digital Age, Any Capacitor, AnyIn, AnyOut, Augmented Switching, BlueSky, BodyCom, CodeGuard, CryptoAuthentication, CryptoAutomotive, CryptoCompanion, CryptoController, dsPICDEM, dsPICDEM.net, Dynamic Average Matching, DAM, ECAN, Espresso T1S, EtherGREEN, IdealBridge, In-Circuit Serial Programming, ICSP, INICnet, Intelligent Paralleling, Inter-Chip Connectivity, JitterBlocker, maxCrypto, maxView, memBrain, Mindi, MiWi, MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach, Omniscient Code Generation, PICDEM, PICDEM.net, PICkit, PICtail, PowerSmart, PureSilicon, QMatrix, REAL ICE, Ripple Blocker, RTAX, RTG4, SAM-ICE, Serial Quad I/O, simpleMAP, SimpliPHY, SmartBuffer, SMART-I.S., storClad, SQI, SuperSwitcher, SuperSwitcher II, Switchtec, SynchroPHY, Total Endurance, TSHARC, USBCheck, VariSense, VectorBlox, VeriPHY, ViewSpan, WiperLock, XpressConnect, and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. The Adaptec logo, Frequency on Demand, Silicon Storage Technology, and Symmcom are registered trademarks of Microchip Technology Inc. in other countries. GestIC is a registered trademark of Microchip Technology Germany II GmbH & Co. KG, a subsidiary of Microchip Technology Inc., in other countries. All other trademarks mentioned herein are property of their respective companies. © 2019-2021, Microchip Technology Incorporated, All Rights Reserved. For information regarding Microchip’s Quality Management Systems, please visit www.microchip.com/quality.  2019-2021 Microchip Technology Inc. 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