MCP3464RT-E/NC

MCP3461/2/4R Two/Four/Eight-Channel, 153.6 ksps, Low-Noise, 16-Bit Delta-Sigma ADCs with Internal Voltage Reference Features General Description • One/Two/Four Differential or Two/Four/Eight Single-Ended Input Channels • 16-Bit Resolution • Programmable Data Rate: Up to 153.6 ksps • Programmable Gain: 0.33x to 64x • 97.2 dB SINAD, -116 dBc THD, 120 dBc SFDR (Gain = 1x, 4800 SPS) • Low-Temperature Drift: - Offset error drift: 4/Gain nV/°C (AZ_MUX = 1) - Gain error drift: 0.5 ppm/°C (Gain = 1x) • Low Noise: 2.3 µVRMS (Gain = 16x, 9600 SPS) • RMS Effective Resolution: 15.4 Bits Minimum (All Gains, All OSR Combinations) • Wide Input Voltage Range: 0V to AVDD • Selectable Internal 2.4V Voltage Reference with 15 ppm/°C Drift • Differential Voltage Reference Inputs • Internal Oscillator or External Clock Selection • Ultra-Low Full Shutdown Current Consumption (< 2.4 µA) • Internal Temperature Sensor • Burnout Current Sources for Sensor Open/Short Detection • 16-Bit Digital Offset and Gain Error Calibration Registers • Internal Conversions Sequencer (Scan Mode) for Automatic Multiplexing • Dedicated IRQ Pin for Easy Synchronization • Advanced Security Features: - 16-bit CRC for secure SPI communications - 16-bit CRC and IRQ for securing configuration - Register map lock with 8-bit secure key - Monitor controls for system diagnostics • 20 MHz SPI-Compatible Interface with Mode 0,0 and 1,1 • AVDD: 2.7V-3.6V • DVDD: 1.8V-3.6V • Extended Temperature Range: -40°C to +125°C • Packages: 3 mm x 3 mm x 0.55 mm 20-Lead UQFN and 6.5 mm x 4.4 mm x 1 mm 20-Lead TSSOP The MCP3461/2/4R devices are 2/4/8-channel, 16-bit, Delta-Sigma Analog-to-Digital Converters (ADCs) with programmable data rate of up to 153.6 ksps. They offer integrated features, such as internal voltage reference, internal oscillator, temperature sensor and burnout sensor detection, in order to reduce system component count and total solution cost.  2020-2021 Microchip Technology Inc. The MCP3461/2/4R ADCs are fully configurable with Oversampling Ratio (OSR) from 32 to 98304, and gain from 1/3x to 64x. These devices include an internal sequencer (Scan mode) with multiple monitor channels and a 16-bit timer to be able to automatically create conversion loop sequences without needing MCU communications. Advanced security features, such as CRC and register map lock, can ensure configuration locking and integrity, as well as communication data integrity for secure environments. These devices come with a 20 MHz SPI-compatible serial interface. Communication is largely simplified with 8-bit commands, including various Continuous Read/Write modes and 16/32-bit multiple data formats that can be accessed by the Direct Memory Access (DMA) of an 8-bit, 16-bit or 32-bit MCU. The MCP3461/2/4R devices are available in a leaded 20-lead TSSOP package, as well as in an ultra-small, 3 mm x 3 mm x 0.55 mm 20-lead UQFN package and are specified over an extended temperature range from -40°C to +125°C. Applications • Precision Sensor Transducers and Transmitters: Pressure, Strain, Flow and Force Measurement • Factory Automation and Process Controls • Portable Instrumentation • Temperature Measurements DS20006404C-page 1 MCP3461/2/4R Package Types – 20-Lead UQFN Package Type for All Devices: 20-Lead UQFN* (3 mm x 3 mm x 0.55 mm) MCLK DGND DVDD AVDD AGND A. MCP3461R: Single Channel Device 20 19 18 17 16 REFIN- 1 15 IRQ/MDAT REFIN+/OUT 2 CH0 14 SDO EP 21 3 CH1 4 NC 5 13 SDI 12 SCK 11 CS NC NC NC NC DVDD DGND MCLK 9 10 NC 8 AVDD 7 AGND 6 B. MCP3462R: Dual Channel Device 20 19 18 17 16 REFIN- 1 REFIN+/OUT 2 CH0 3 CH1 4 CH2 5 15 IRQ/MDAT 14 SDO EP 21 12 SCK 11 CS NC NC NC NC DVDD DGND MCLK 9 10 CH3 8 AVDD 7 AGND 6 C. MCP3464R: Quad Channel Device 13 SDI 20 19 18 17 16 REFIN- 1 15 IRQ/MDAT REFIN+/OUT 2 14 SDO EP 21 CH0 3 CH1 4 13 SDI 12 SCK CH2 5 9 10 CH7 CH4 8 CH6 7 CH5 6 CH3 11 CS *Includes Exposed Thermal Pad (EP); see Table 3-1. DS20006404C-page 2  2020-2021 Microchip Technology Inc. MCP3461/2/4R Package Types – 20-Lead TSSOP Package Type for All Devices: 20-Lead TSSOP (6.5 mm x 4.4 mm x 1 mm) A. MCP3461R: Single Channel Device AVDD 1 20 DVDD AGND 2 19 DGND REFIN- 3 18 MCLK REFIN+/OUT 4 17 IRQ/MDAT CH0 5 16 SDO CH1 6 15 SDI NC 7 14 SCK NC 8 13 CS NC 9 12 NC NC 10 11 NC DVDD B. MCP3462R: Dual Channel Device AVDD 1 20 AGND 2 19 DGND REFIN- 3 18 MCLK REFIN+/OUT 4 17 IRQ/MDAT CH0 5 16 SDO CH1 6 15 SDI CH2 7 14 SCK CH3 8 13 CS NC 9 12 NC NC 10 11 NC 20 DVDD C. MCP3464R: Quad Channel Device Note: AVDD 1 AGND 2 19 DGND REFIN- 3 18 MCLK REFIN+/OUT 4 17 IRQ/MDAT CH0 5 16 SDO CH1 6 15 SDI CH2 7 14 SCK CH3 8 13 CS CH4 9 12 CH7 CH5 10 11 CH6 The NC is a Not Connected pin. It is recommended for the NC pin to be tied to AGND for a better susceptibility to electromagnetic fields.  2020-2021 Microchip Technology Inc. DS20006404C-page 3 MCP3461/2/4R Functional Block Diagram REFIN+/OUT AVDD Voltage Reference - REFIN- DVDD AMCLK VREF_SEL + 2.4V DMCLK/DRCLK Clock Generation (RC Oscillator) MCLK IRQ/MDAT VREF- VREF+ MCP346/4R only MCP3464R only CH0 CH1 CH CH3 CH4 CH5 VINAnalog Differential Multiplexer CH6 CH7 AGND AVDD + + x - Δ±Ȉ  nd Order Modulator with Analog Gain SINC3 Filter with Digital Gain POR AVDD Monitoring AGND ANALOG SINC1 Filter Offset/Gain Calibration OSR[3:0] PRE[1:0] SDO Digital SPI Interface and control SDI SCK CS '±Ȉ$'  Converter Burnout Current Sources TEMP Diodes DS20006404C-page 4 DMCLK VIN+ POR DVDD Monitoring DIGITAL DGND  2020-2021 Microchip Technology Inc. MCP3461/2/4R 1.0 ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings† DVDD, AVDD ......................................................................................................................................................-0.3 to 4.0V Digital Inputs and Outputs w.r.t. DGND ............................................................................................ -0.3V to DVDD + 0.3V Analog Inputs w.r.t. AGND ............................................................................................................. ....-0.3V to AVDD + 0.3V Current at Input Pins ...............................................................................................................................................±5 mA Current at Output and Supply Pins ...................................................................................................................... ±20 mA Storage Temperature ..............................................................................................................................-65°C to +150°C Ambient Temperature with Power Applied ..............................................................................................-65°C to +125°C Soldering Temperature of Leads (10 seconds) ..................................................................................................... +300°C Maximum Junction Temperature (TJ) ........................................................................................... .........................+150°C ESD on All Pins (HBM)  6.0 kV † Notice: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions, above those indicated in the operational listings of this specification, is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.  2020-2021 Microchip Technology Inc. DS20006404C-page 5 MCP3461/2/4R ELECTRICAL CHARACTERISTICS Electrical Specifications: Unless otherwise indicated, all parameters apply at AVDD = 2.7V to 3.6V, DVDD = 1.8V to AVDD + 0.1V, MCLK = 4.9152 MHz, VREF = AVDD, ADC_MODE[1:0] = 11. All other register map bits to their default conditions, TA = -40°C to +125°C, VIN = -0.5 dBFS at 50 Hz. Parameters Sym. Min. Typ. Max. Units Analog Operating Voltage AVDD 2.7 Digital Operating Voltage DVDD 1.8 Analog Operating Current AIDD Conditions — 3.6 V — AVDD + 0.1 V — 0.56 0.81 mA BOOST[1:0] = 00, 0.5x — 0.69 0.96 mA BOOST[1:0] = 01, 0.66x — 0.93 1.3 mA BOOST[1:0] = 10, 1x — 1.65 2.2 mA BOOST[1:0] = 11, 2x — — 0.96 mA BOOST[1:0] = 00, 0.5x, VREF = 2.4V internal — — 1.2 mA BOOST[1:0] = 01, 0.66x, VREF = 2.4V internal — — 1.6 mA BOOST[1:0] = 10, 1x, VREF = 2.4V internal — — 2.5 mA BOOST[1:0] = 11, 2x, VREF = 2.4V internal Supply Requirements Analog Operating Current AIDD DVDD ≤ 3.6V Digital Operating Current DIDD — 0.25 0.37 mA Note 8 Analog Partial Shutdown Current AIDDS_PS — — 22 µA CONFIG0 = 0x00 Digital Partial Shutdown Current DIDDS_PS — — 17 µA CONFIG0 = 0x00 Analog Full-Shutdown Current AIDDS_FS — — 0.4 µA CONFIG0 = 0x00 with Full-Shutdown Fast-CMD Digital Full-Shutdown Current DIDDS_FS — — 2 µA CONFIG0 = 0x00 with Full-Shutdown Fast-CMD VPOR_A — 1.75 — V For analog circuits VPOR_D — 1.2 — V For digital circuits POR Hysteresis VPOR_HYS — 150 — mV POR Reset Time tPOR — 1 — µs Power-on Reset (POR) Threshold Voltage Note 1: 2: 3: 4: 5: This parameter is ensured by design and not 100% tested. This parameter is ensured by characterization and not 100% tested. REFIN- must be connected to ground for single-ended measurements. Full-Scale Range (FSR) = 2 x VREF/Gain. This input impedance is due to the internal input sampling capacitor and frequency. This impedance is measured between the two input pins of the channel selected with the input multiplexer. 6: Applies to all analog gains. Offset and gain errors depend on analog gain settings. See Section 2.0 “Typical Performance Curves”. 7: INL is the difference between the endpoints line and the measured code at the center of the quantization band. 8: DIDD is measured while no transfer is present on the SPI bus. 9: An external buffer is recommended for external use. 10: Start-up time is the reaction time to the SPI command. 11: Settling time depends on bypass caps on REFIN+/OUT pin. DS20006404C-page 6  2020-2021 Microchip Technology Inc. MCP3461/2/4R ELECTRICAL CHARACTERISTICS (CONTINUED) Electrical Specifications: Unless otherwise indicated, all parameters apply at AVDD = 2.7V to 3.6V, DVDD = 1.8V to AVDD + 0.1V, MCLK = 4.9152 MHz, VREF = AVDD, ADC_MODE[1:0] = 11. All other register map bits to their default conditions, TA = -40°C to +125°C, VIN = -0.5 dBFS at 50 Hz. Parameters Sym. Min. Typ. Max. Units Conditions Input Voltage at Input Pin CHN AGND – 0.1 — AVDD + 0.1 V Differential Input Range VIN -VREF/Gain — +VREF/Gain V Differential Input Impedance (Note 5) ZIN — 510 — k GAIN = 0.33x, proportional to 1/AMCLK — 260 — k GAIN = 1x, proportional to 1/AMCLK — 150 — k GAIN = 2x, proportional to 1/AMCLK — 80 — k GAIN = 4x, proportional to 1/AMCLK — 40 — k GAIN = 8x, proportional to 1/AMCLK — 20 — k GAIN ≥ 16x, proportional to 1/AMCLK ILI_A — ±10 — nA IVREF -2% 2.4 +2% V Internal VREF Temperature Coefficient TCREFE — 15 40 ppm/°C TA = -40°C to +125°C, extended temperature range (Note 2) Internal VREF Temperature Coefficient TCREFI — 9 40 ppm/°C TA = -40°C to +85°C, industrial temperature range (Note 2) Voltage Reference Buffer Short-Circuit Current IREF_SC — — 8 mA REFIN+/OUT shorted to AGND, VREF_SEL = 1 (Note 9) tVREF_SET — 12 — ms Settling to 10 ppm from final value, bypass capacitor 1 µF (Notes 2, 11) VREF_Noise — 14.3 — µV VREF_SEL = 1, AZ_VREF = 1 (chopper on), TA = +25°C only (Note 2) Analog Inputs Analog Input Leakage Current During ADC Shutdown Analog inputs are measured with respect to AGND Internal Voltage Reference Internal VREF Absolute Voltage Internal Reference Settling Time Internal VREF Output Noise VREF_SEL = 1, TA = +25°C only Note 1: 2: 3: 4: 5: This parameter is ensured by design and not 100% tested. This parameter is ensured by characterization and not 100% tested. REFIN- must be connected to ground for single-ended measurements. Full-Scale Range (FSR) = 2 x VREF/Gain. This input impedance is due to the internal input sampling capacitor and frequency. This impedance is measured between the two input pins of the channel selected with the input multiplexer. 6: Applies to all analog gains. Offset and gain errors depend on analog gain settings. See Section 2.0 “Typical Performance Curves”. 7: INL is the difference between the endpoints line and the measured code at the center of the quantization band. 8: DIDD is measured while no transfer is present on the SPI bus. 9: An external buffer is recommended for external use. 10: Start-up time is the reaction time to the SPI command. 11: Settling time depends on bypass caps on REFIN+/OUT pin.  2020-2021 Microchip Technology Inc. DS20006404C-page 7 MCP3461/2/4R ELECTRICAL CHARACTERISTICS (CONTINUED) Electrical Specifications: Unless otherwise indicated, all parameters apply at AVDD = 2.7V to 3.6V, DVDD = 1.8V to AVDD + 0.1V, MCLK = 4.9152 MHz, VREF = AVDD, ADC_MODE[1:0] = 11. All other register map bits to their default conditions, TA = -40°C to +125°C, VIN = -0.5 dBFS at 50 Hz. Parameters Sym. Min. Typ. Max. Units VREF 0.6 — AVDD V External Noninverting Input Voltage Reference VREF+ VREF- + 0.6 — AVDD V External Inverting Input Voltage Reference VREF- AGND — VREF+ – 0.6 V Resolution 16 — — Bits VOS -900/Gain — 900/Gain µV -(0.05 + 0.8/ Gain) — 0.05 + 0.8/ Gain Conditions External Voltage Reference Input Reference Voltage Range (VREF+ – VREF-) VREF_SEL = 0 DC Performance No Missing Code Resolution Offset Error Offset Error Temperature Coefficient Gain Error Gain Error Temperature Coefficient Integral Nonlinearity (Note 7) OSR ≥ 256 (Note 1) AZ_MUX = 0 (Note 6) AZ_MUX = 1 (Notes 2, 6) — 70/Gain 300/Gain — 4/Gain 16/Gain GE -3 — +3 GE_DRIFT — 0.5 2 1 4 2 8 -10 — +10 -7 — +7 -7 — +7 Gain = 2x (Note 2) -10 — +10 Gain = 4x (Note 2) -20 — +20 Gain = 8x (Note 2) VOS_DRIFT INL nV/°C AZ_MUX = 0 (Notes 2, 6) AZ_MUX = 1 (Notes 2, 6) % Note 6 ppm/°C Gain: 1x, 2x, 4x (Note 2) Gain: 8x (Note 2) Gain: 0.33x, 16x (Note 2) ppm FSR Gain = 0.33x (Note 2) Gain = 1x (Note 2) -32 — +32 AVDD Power Supply Rejection Ratio DC PSRR — -76 – 20 x LOG (Gain) — dB Gain = 16x (Note 2) AVDD varies from 2.7V to 3.6V, VIN = 0V DVDD Power Supply Rejection Ratio DC PSRR — -110 — dB DVDD varies from 1.8V to 3.6V, VIN = 0V DC Common-Mode Rejection Ratio DC CMRR — -126 — dB VINCOM varies from 0V to AVDD, VIN = 0V Note 1: 2: 3: 4: 5: This parameter is ensured by design and not 100% tested. This parameter is ensured by characterization and not 100% tested. REFIN- must be connected to ground for single-ended measurements. Full-Scale Range (FSR) = 2 x VREF/Gain. This input impedance is due to the internal input sampling capacitor and frequency. This impedance is measured between the two input pins of the channel selected with the input multiplexer. 6: Applies to all analog gains. Offset and gain errors depend on analog gain settings. See Section 2.0 “Typical Performance Curves”. 7: INL is the difference between the endpoints line and the measured code at the center of the quantization band. 8: DIDD is measured while no transfer is present on the SPI bus. 9: An external buffer is recommended for external use. 10: Start-up time is the reaction time to the SPI command. 11: Settling time depends on bypass caps on REFIN+/OUT pin. DS20006404C-page 8  2020-2021 Microchip Technology Inc. MCP3461/2/4R ELECTRICAL CHARACTERISTICS (CONTINUED) Electrical Specifications: Unless otherwise indicated, all parameters apply at AVDD = 2.7V to 3.6V, DVDD = 1.8V to AVDD + 0.1V, MCLK = 4.9152 MHz, VREF = AVDD, ADC_MODE[1:0] = 11. All other register map bits to their default conditions, TA = -40°C to +125°C, VIN = -0.5 dBFS at 50 Hz. Parameters Sym. Min. Typ. Max. Units Conditions SINAD 96.9 97.2 — dB AVDD = DVDD = VREF = 3.3V and TA = +25°C (Note 2) 95.4 95.8 — dB AVDD = DVDD = 3.3V, VREF = 2.4V internal, bypass capacitor 0.1 µF and TA = +25°C (Note 2) 97 97.3 — dBc AVDD = DVDD = VREF = 3.3V and TA = +25°C (Note 2) 95.7 96 — dBc AVDD = DVDD = 3.3V, VREF = 2.4V internal, bypass capacitor 0.1 µF and TA = +25°C (Note 2) — -116 -110 dB AVDD = DVDD = VREF = 3.3V and TA = +25°C, includes the first 10 harmonics (Note 2) — -110 -105 dB AVDD = DVDD = 3.3V, VREF = 2.4V internal, bypass capacitor 0.1 µF and TA = +25°C, includes the first 10 harmonics (Note 2) 110 120 — dBc AVDD = DVDD = VREF = 3.3V and TA = +25°C (Note 2) 107 112.5 — dBc AVDD = DVDD = 3.3V, VREF = 2.4V internal, bypass capacitor 0.1 µF and TA = +25°C (Note 2) CTALK — -130 — dB VIN = 0V, Perturbation = 0 dB at 50 Hz, applies to all perturbation channels and all input channels AC Power Supply Rejection Ratio AC PSRR — -75 – 20 x LOG (Gain) — dB VIN = 0V, DVDD = 3.3V, AVDD = 3.3V + 0.3VP, 50 Hz AC Common-Mode Rejection Ratio AC CMRR — -122 — dB VINCOM = 0 dB at 50 Hz, VIN = 0V AC Performance Signal-to-Noise and Distortion Ratio Signal-to-Noise Ratio Total Harmonic Distortion Spurious-Free Dynamic Range Input Channel Crosstalk SNR THD SFDR Note 1: 2: 3: 4: 5: This parameter is ensured by design and not 100% tested. This parameter is ensured by characterization and not 100% tested. REFIN- must be connected to ground for single-ended measurements. Full-Scale Range (FSR) = 2 x VREF/Gain. This input impedance is due to the internal input sampling capacitor and frequency. This impedance is measured between the two input pins of the channel selected with the input multiplexer. 6: Applies to all analog gains. Offset and gain errors depend on analog gain settings. See Section 2.0 “Typical Performance Curves”. 7: INL is the difference between the endpoints line and the measured code at the center of the quantization band. 8: DIDD is measured while no transfer is present on the SPI bus. 9: An external buffer is recommended for external use. 10: Start-up time is the reaction time to the SPI command. 11: Settling time depends on bypass caps on REFIN+/OUT pin.  2020-2021 Microchip Technology Inc. DS20006404C-page 9 MCP3461/2/4R ELECTRICAL CHARACTERISTICS (CONTINUED) Electrical Specifications: Unless otherwise indicated, all parameters apply at AVDD = 2.7V to 3.6V, DVDD = 1.8V to AVDD + 0.1V, MCLK = 4.9152 MHz, VREF = AVDD, ADC_MODE[1:0] = 11. All other register map bits to their default conditions, TA = -40°C to +125°C, VIN = -0.5 dBFS at 50 Hz. Parameters Sym. Min. Typ. Max. Units Conditions ADC Timing Parameters Sampling Frequency DMCLK See Table 5-6 MHz See Figure 4-1 Output Data Rate DRCLK See Table 5-6 ksps See Figure 4-1 ms See Figure 4-1 Data Conversion Time See Table 5-6 TCONV — 256 — DMCLK ADC_MODE[1:0] bits change periods from ‘0x’ to ‘1x’ — 0 — DMCLK ADC_MODE[1:0] bits change periods from ‘10’ to ‘11’ TSTP — 1 — DMCLK periods TDLY_SCAN 0 — 512 TTIMER_SCAN 0 — 16777215 Data Ready Pulse Low Time TDRL — — OSR-16 DMCLK See Figure 5-16 periods Data Ready Pulse High Time TDRH 16 — — DMCLK See Figure 5-16 periods Data Transfer Time to DR (Data Ready) tDODR — — 50 ns Modulator Output Valid from AMCLK High tDOMDAT — — 100 ns ADC Start-up Delay Conversion Start Pulse Low Time Scan Mode Time Delays TADC_SETUP DMCLK Time delay between sampling periods channels DMCLK Time interval between Scan periods cycles 2.7V ≤ DVDD ≤ 3.6V 1.8V ≤ DVDD ≤ 2.7V 200 External Master Clock Input (CLK_SEL[1] = 0) 1 — 20 MHz DVDD ≥ 2.7V 1 — 10 MHz DVDD < 2.7V fMCLK_DUTY 45 — 55 % fMCLK_INT 3.3 — 6.6 MHz Internal Oscillator Start-up Time tOSC_STARTUP — 10 — µs CLK_SEL[1] changes from ‘0’ to ‘1’, time to stabilize the clock frequency to ±1 kHz of the final value (Note 10) Internal Oscillator Current Consumption IDDOSC — 30 — µA Should be added to DIDD when CLK_SEL[1:0] = 1x TAcc — ±5 — °C See Section 5.1.2 “Internal Temperature Sensor” Master Clock Input Frequency Range Master Clock Input Duty Cycle fMCLK_EXT Internal Clock Oscillator Internal Master Clock Frequency CLK_SEL[1] = 1 Internal Temperature Sensor Temperature Measurement Accuracy Note 1: 2: 3: 4: 5: This parameter is ensured by design and not 100% tested. This parameter is ensured by characterization and not 100% tested. REFIN- must be connected to ground for single-ended measurements. Full-Scale Range (FSR) = 2 x VREF/Gain. This input impedance is due to the internal input sampling capacitor and frequency. This impedance is measured between the two input pins of the channel selected with the input multiplexer. 6: Applies to all analog gains. Offset and gain errors depend on analog gain settings. See Section 2.0 “Typical Performance Curves”. 7: INL is the difference between the endpoints line and the measured code at the center of the quantization band. 8: DIDD is measured while no transfer is present on the SPI bus. 9: An external buffer is recommended for external use. 10: Start-up time is the reaction time to the SPI command. 11: Settling time depends on bypass caps on REFIN+/OUT pin. DS20006404C-page 10  2020-2021 Microchip Technology Inc. MCP3461/2/4R TEMPERATURE SPECIFICATIONS Electrical Specifications: Unless otherwise specified, all parameters apply for TA = -40°C to +125°C, AVDD = 2.7V to 3.6V, DVDD = 1.8V to AVDD + 0.1V, DGND = AGND = 0V. Parameters Sym. Min. Typ. Max. Units Conditions Temperature Ranges Specified Temperature Range TA -40 — +125 °C Operating Temperature Range TA -40 — +125 °C Storage Temperature Range TA -65 — +150 °C Thermal Resistance, 20-Lead TSSOP JA — 44 — °C/W Thermal Resistance, 20-Lead UQFN JA — 50 — °C/W Thermal Package Resistance Note 1: The internal Junction Temperature (TJ) must not exceed the absolute maximum specification of +150°C.  2020-2021 Microchip Technology Inc. DS20006404C-page 11 MCP3461/2/4R TABLE 1-1: SPI SERIAL INTERFACE TIMING SPECIFICATIONS FOR DVDD = 2.7V TO 3.6V Electrical Specifications: DVDD = 2.7V to 3.6V, TA = -40°C to +125°C, CLOAD = 30 pF. See Figure 1-1. Parameters Sym. Min. Typ. Max. Units fSCK — — 20 MHz CS Setup Time tCSS 25 — — ns CS Hold Time tCSH 50 — — ns CS Disable Time tCSD 50 — — ns Serial Clock Frequency Conditions Data Setup Time tSU 5 — — ns Data Hold Time tHD 10 — — ns Serial Clock High Time tHI 20 — — ns Serial Clock Low Time tLO 20 — — ns Serial Clock Delay Time tCLD 50 — — ns Serial Clock Enable Time tCLE 50 — — ns Output Valid from SCK Low tDO — — 25 ns Output Hold Time tHO 0 — — ns Output Disable Time tDIS — — 25 ns Measured with a 1.5 mA pull-up current source on SDO pin POR IRQ Disable Time tCSIRQ — — 52 ns Measured with a 1.5 mA pull-up current source on IRQ pin Output Valid from CS Low tCSSDO — — 25 ns SDO toggles to logic low at each communication start (CS falling edge) DS20006404C-page 12  2020-2021 Microchip Technology Inc. MCP3461/2/4R TABLE 1-2: SPI SERIAL INTERFACE TIMING SPECIFICATIONS FOR DVDD = 1.8V TO 2.7V (10 MHz MAXIMUM SCK FREQUENCY) Electrical Specifications: DVDD = 1.8V to 2.7V, TA = -40°C to +125°C, CLOAD = 30 pF. See Figure 1-1. Parameters Serial Clock Frequency Sym. Min. Typ. Max. Units fSCK — — 10 MHz Conditions CS Setup Time tCSS 50 — — ns CS Hold Time tCSH 100 — — ns CS Disable Time tCSD 100 — — ns Data Setup Time tSU 10 — — ns Data Hold Time tHD 20 — — ns Serial Clock High Time tHI 40 — — ns Serial Clock Low Time tLO 40 — — ns Serial Clock Delay Time tCLD 100 — — ns Serial Clock Enable Time tCLE 100 — — ns Output Valid from SCK Low tDO — — 50 ns Output Hold Time tHO 0 — — ns Output Disable Time tDIS — — 50 ns Measured with a 1.5 mA pull-up current source on SDO pin POR IRQ Disable Time tCSIRQ — — 60 ns Measured with a 1.5 mA pull-up current source on IRQ pin Output Valid from CS Low tCSSDO — — 50 ns SDO toggles to logic low at each communication start (CS falling edge) TABLE 1-3: DIGITAL I/O DC SPECIFICATIONS Electrical Specifications: Unless otherwise indicated, all parameters apply at DVDD = 1.8V to 3.6V, TA = -40°C to +125°C. Parameters Sym. Min. Typ. Max. Units Schmitt Trigger High-Level Input Voltage VIH 0.7 x DVDD — — V Schmitt Trigger Low-Level Input Voltage VIL — — 0.3 x DVDD V VHYS — 200 — mV Hysteresis of Schmitt Trigger Inputs Conditions Low-Level Output Voltage VOL — — 0.2 x DVDD V IOL = +1.5 mA High-Level Output Voltage VOH 0.8 x DVDD — — V IOH = -1.5 mA Input Leakage Current ILI_D — — 1 µA Pins configured as inputs or high-impedance outputs  2020-2021 Microchip Technology Inc. DS20006404C-page 13 MCP3461/2/4R tCSD CS tSC K tCLE tCSS tH I tLO tC SH tC LD SPI mode 1,1 SPI mode 1,1 SCK SPI mode 0,0 SPI mode 0,0 Device Latches SDI on SCK Rising Edge tSU SDI SDO tH D tDO tHO tC SSD O High-Z DS20006404C-page 14 tD IS High-Z 0 (for first two bits on SDO) FIGURE 1-1: Device Latches SDO on SCK Falling Edge High-Z 0 Serial Output Timing Diagram.  2020-2021 Microchip Technology Inc. MCP3461/2/4R 2.0 TYPICAL PERFORMANCE CURVES Note: The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore outside the warranted range. Note: Unless otherwise indicated, AVDD = 3.3V, DVDD = 3.3V, TA = +25°C, MCLK = 4.9152 MHz, VIN = -0.5 dBFS at 50 Hz, VREF = AVDD, ADC_MODE[1:0] = 11. All other registers are set to default value. Histogram ticks are centered at their bin center. VIN = -0.5 dBFS @ 50 Hz FFT 16384 samples -40 -60 -80 -100 -120 -140 -160 0 -40 -60 -80 -100 -120 -140 -160 -180 -180 0 500 FIGURE 2-1: fin = 50 Hz Input. 1000 1500 Frequency (Hz) 2000 0 2500 1500 2000 2500 70000 VIN = -0.5 dBFS @ 1 kHz FFT 16384 samples Occurrence (Counts) -40 -60 -80 -100 -120 -140 -160 VIN = 0V CONV_MODE[1:0] = 11 64000 samples Bin size = 1 LSE 60000 50000 Histograms may show up to 2 bins equally distributed if offset is close to a round LSE value (Intrinsic noise VREF – 1 LSb, the 16-bit ADC code (SGN + DATA[22:0]) will saturate and be locked at 0x7FFF. When VIN * Gain < -VREF, the 16-bit ADC code will saturate and be locked at 0x8000. Using these data formats does not permit correctly evaluating full-scale errors in case of a positive full-scale error. DS20006404C-page 48 DATA[15:0] When DATA_FORMAT[1:0] = 00, the output register shows only the 16-bit value. When DATA_FORMAT[1:0] = 01, the output register is 32 bits long and the output code is padded with additional zeros on the last byte. The output code is left justified in this case. This format is useful for 32-bit MCU applications.  2020-2021 Microchip Technology Inc. MCP3461/2/4R When DATA_FORMAT[1:0] = 1x, the ADC data are represented on 17 bits. For these two data formats, the output register is 32 bits long. With these two data formats, the coding allows overrange; the equivalent analog input range is [-2 x VREF, +2 x VREF – 1 LSb]. When VIN * Gain > 2VREF – 1 LSb, the 17-bit ADC code (SGN + DATA[15:0]) will saturate and be locked at 0x0FFFF. When VIN * Gain < -2VREF, the 16-bit ADC code will saturate and be locked at 0x10000. Using these data formats allows a correct evaluation of the full-scale errors in case of a positive full-scale error, since they allow inputs that can be greater than VREF or less than -VREF. The ADC accuracy is not maintained on the full extended [-2 x VREF, +2 x VREF – 1 LSb] range, but only on a smaller range, which is approximately equal to ±1.05 x VREF. This overrange can be useful in high-side measurements and gain error cancellation algorithms. The overrange-capable formatting on 17 bits is fully compatible with the standard code locked formatting on 16 bits; both coding formats will produce the same TABLE 5-7: 16-bit codes for the [-VREF; +VREF – 1 LSb] range and the MSb on the 17-bit coding can be considered as a simple Sign bit extension. When DATA_FORMAT[1:0] = 10, the 17-bit (16-bit + SGN) value is right justified. The first byte of the 32-bit ADC output code will repeat the Sign bit (SGN). In DATA_FORMAT[1:0] = 11, the output code is similar to the one in DATA_FORMAT[1:0] = 10. The only difference resides in the four MSbs of the first byte, which are no longer repeats of the Sign bit (SGN). They are the Channel ID data (CH_ID[3:0]) that are defined in Table 5-15. This CH_ID[3:0] word can be used to verify that the right channel has been converted to Scan mode and can serve easy data retrieval and logging (see Section 5.15 “Scan Mode” for more details about the Scan mode). In MUX mode, this 4-bit word is defaulted to ‘0000’ and does not vary with the MUX[7:0] selection. This format is useful for 32-bit MCU applications. DATA_FORMAT[1:0] = 0x (16-BIT CODING) Equivalent Input Voltage ADC Output Code (SGN + DATA[14:0]) > VREF – 1 LSb 0111111111111111 0x7FFF +32767 VREF – 2 LSbs 0111111111111110 0x7FFE +32766 1 LSb 0000000000000001 0x0001 +1 Hexadecimal Decimal 0 0000000000000000 0x0000 0 -1 LSb 1111111111111111 0xFFFF -1 -VREF + 1 LSb 1000000000000001 0xFFFF -32767 < -VREF 1000000000000000 0x8000 -32768 TABLE 5-8: DATA_FORMAT[1:0] = 1x (17-BIT CODING) Equivalent Input Voltage ADC Output Code (SGN + DATA[15:0]) Hexadecimal Decimal > 2 VREF – 1 LSb 01111111111111111 0x0FFFF +65535 2 VREF – 2 LSbs 01111111111111110 0x0FFFE +65534 VREF + 1 LSb 01000000000000001 0x08001 +32769 VREF 01000000000000000 0x08000 +32768 VREF – 1 LSb 00111111111111111 0x07FFF +32767 VREF – 2 LSbs 00111111111111110 0x07FFE +32766 1 LSb 00000000000000001 0x00001 +1 0 00000000000000000 0x00000 0 -1 LSb 11111111111111111 0x1FFFF -1 -VREF + 1 LSb 11000000000000001 0x18001 -32767 -VREF 11000000000000000 0x18000 -32768 -VREF – 1 LSb 10111111111111111 0x17FFF -32769 -2 VREF + 1 LSb 10000000000000001 0x10001 -65535 < -2 VREF 10000000000000000 0x10000 -65536  2020-2021 Microchip Technology Inc. DS20006404C-page 49 MCP3461/2/4R 5.7 Internal/External Voltage Reference 5.7.1 VOLTAGE REFERENCE SELECTION The voltage reference selection for the ADC is controlled by the VREF_SEL bit in the CONFIG0 register, as shown in Table 5-9. TABLE 5-9: The REFIN- pin is set as an input, directly connected to the VREF- input of the ADC. For a better noise immunity, it is recommended to connect this pin to AGND externally when a single-ended voltage reference is used. Figure 6-10 shows more details of the reference selection and reference pins connections. ADC VOLTAGE REFERENCE SELECTION VREF_SEL Description 0 1 Reference Input/Output Pins REFIN- Pin REFIN+/OUT Pin External reference selected. Internal reference buffer is shut down. Internal reference is only generating the internal 1.2V Common-mode voltage for the ADC. VREF- Input VREF+ Input Internal reference selected with 2.4V buffered output. VREF- Input (should be tied to AGND) Internal Reference with 2.4V Buffered Output REFINPAD ADC VREFInput REFIN+/OUT PAD ADC VREF+ Input Chopped at DMCLK Rate if AZ_VREF = 1 VREF_SEL = 0 Off VREF_SEL = 1 On VREF_SEL – 2x + VREF Buffer – 1x ADC Internal VCM Voltage + Internal + Band Gap Voltage - FIGURE 5-9: DS20006404C-page 50 1.2V VCM Buffer Voltage Reference Selection Schematic.  2020-2021 Microchip Technology Inc. MCP3461/2/4R When VREF_SEL = 0, the reference voltage is set to External mode. The REFIN+/OUT pin becomes an input. In this case, the REFIN+/OUT pad is directly tied to the VREF+ input of the ADC. There is no input buffer in the differential input voltage reference path in this mode, so the external voltage reference should include a buffer to be able to charge the internal voltage reference sampling capacitors. When VREF_SEL = 1, the REFIN+/OUT is internally buffered to produce a 2.4V buffered reference voltage at the VREF+ input of the ADC. Section 5.7.2 “Internal Voltage Reference Buffer” details the architecture of the voltage reference buffer. In this mode, the REFIN+/OUT pin becomes an output and the reference voltage is generated internally. The structure of the internal voltage reference is based on a band gap voltage reference source, giving a 1.2V output directly connected to a low-noise chopper buffer, configured with a gain of 2x, to give a 2.4V output on the REFIN+/OUT pad. The internal reference has a very low typical temperature coefficient of 15 ppm/°C for extended temperature range and 9 ppm/°C for industrial temperature range, allowing the ADC output codes to have the least variation corresponding to the temperature ranges, since they are proportional to (1/VREF). 5.7.2 INTERNAL VOLTAGE REFERENCE BUFFER When VREF_SEL = 1, the voltage reference buffer is enabled. It is only powered on when the ADC state is in Reset or in Conversion mode and is powered off in Shutdown mode. The offset induced by the buffer may slightly vary between the two possible gain selections, as well as its temperature dependency and bandwidth; therefore, it has to be characterized separately. The buffer injects a certain quantity of 1/f noise into the system that can be modulated with the incoming input signals and can limit the SNR performance at higher OSR values (OSR > 256). To overcome this limitation, the buffer includes an auto-zeroing algorithm that greatly reduces (cancels out) the 1/f noise and cancels the offset value of the reference buffer. As a result, the SNR of the system is not affected by this 1/f noise component of the reference buffer, even at maximum OSR values. This auto-zeroing algorithm is performed synchronously with the DMCLK and can be enabled or disabled with the AZ_VREF bit setting in the CONFIG2 register. When AZ_VREF = 1 (default), the auto-zeroing is enabled, which cancels out the 1/f noise and improves the SNR while not impacting the THD performance. This mode is recommended for higher OSR values (OSR 256). When AZ_VREF = 0, the reference auto-zeroing algorithm is disabled. This setting should be reserved to lower OSR values, where higher ADC speed is more important than accuracy. If the application is susceptible to high-frequency noise, using AZ_VREF = 0 or a proper low-pass filter at the VREF output pin (to filter out the chopper frequency components from the buffered output) is recommended. The buffer is designed to be able to drive the ADC reference input that is sampling the reference voltage. The REFIN- pin is not buffered and is connected directly to the ADC inverting voltage reference input (VREF-).  2020-2021 Microchip Technology Inc. DS20006404C-page 51 MCP3461/2/4R 5.8 Power-on Reset The analog and digital power supplies are monitored separately by two Power-on Reset (POR) monitoring circuits at all times, except during Full Shutdown mode (see Section 5.10 “Low-Power Shutdown Modes”). If the CS pin is kept logic low during a POR state, a logic high pulse is necessary to start the first communication sequence after power-up. The CS rising edge will reset the SPI interface properly and the falling edge will clear the POR interrupt on the IRQ pin (see Figure 6-15). Each POR circuit has two separate thresholds, one for the rising voltage supply and one for the falling voltage supply. They both include hysteresis (the rising threshold is superior), so that the device is tolerant to a certain degree of transient noise on each power supply. The DVDD and AVDD monitoring thresholds are different since their respective voltage ranges are different. The AVDD rising threshold is approximately 1.75V ±10% and the DVDD is 1.2V ±10%. The hysteresis is approximately 150 mV (typical). If any of the two power supply voltages is below its respective threshold, the POR state is forced internally. In this state, the SPI interface is disabled, no command can be executed by the chip. All registers are cleared and set to their default values. Proper decoupling ceramic capacitors (0.1 µF and 10 µF ceramic) should be placed as close as possible to the power supply pins (AVDD, DVDD) to provide additional transient immunity. During Full Shutdown mode, the power supply voltages are not monitored to be able to reach ultra-low power consumption. The device cannot generate a POR event interrupt in this mode, except for cases of extremely low-power supply voltages. See Section 5.10.1 “Full Shutdown Mode”. At power-up, when both power supply voltages are above the rising thresholds, the device powers up and the SPI interface is enabled and can handle communications. Since both thresholds need to be crossed for the power-up, the power-up sequence is not important and any power supply voltage can ramp up first. The detection time for the monitoring circuits (tPOR) is about 1 µs for relatively fast power-up ramp rates. The normal operation stops when any of the falling thresholds of the two POR monitoring circuits is crossed. Figure 5-10 illustrates the power-up and power-down sequences. In order to ensure a proper power-up sequence, the ramp rate of DVDD must not exceed 3 V/µs when coming out of the POR state. Voltage (AVDD, DVDD) POR Threshold Up POR Threshold Down tPOR Time POR State FIGURE 5-10: DS20006404C-page 52 Normal Operation POR State Power-on Reset Timing Diagram.  2020-2021 Microchip Technology Inc. MCP3461/2/4R 5.9 ADC Operating Modes The ADC can be placed into three different operating modes: ADC Shutdown, Standby and Conversion. The ADC operating mode is controlled by the user through the ADC_MODE[1:0] bits in the CONFIG0 register. The user can directly launch conversions or place the ADC into ADC Shutdown or Standby mode by writing these bits. Additional Fast commands are available for each of the three possible states of these bits to allow faster programming in case of time-sensitive applications (see Section 6.2.4 “Command-Type Bits (CMD[1:0])”). Table 5-10 describes the available ADC_MODE[1:0] bits setting. The ADC_MODE[1:0] bits do not give an instantaneous representation of the ADC state. Writing the ADC_MODE[1:0] bits sets the desired state of the ADC, but this state is only attained after a start-up time depending on the current state of the ADC (see Section 5.11 “ADC Start-up Timer” for details about the start-up timer). Typically, the device starts in ADC Shutdown mode after a POR (ADC_MODE[1:0] = 00 by default). To launch conversions in the desired configuration, the user should program the part in the desired configuration and then set the ADC_MODE[1:0] bits to ‘11’. In this case, the first conversion will start after TADC_SETUP = 256 DMCLK periods. This time is necessary for the part to adjust to the new programmed settings and settle in to its operating point to accurately convert the input signals. Internally, the device tracks the current state of the ADC, as well as the start-up timer counter, to be able to optimize the start-up time depending on the desired transitions and internal configurations required, and set by the user. TABLE 5-10: In MUX mode, overwriting the ADC_MODE[1:0] bits to ‘11’ when the ADC is already in conversion resets and restarts the current conversion immediately. The conversion start pulse will also be regenerated if the EN_STP bit is enabled. In Scan mode (see Section 5.15 “Scan Mode”), writing the ADC_MODE[1:0] bits to ‘11’ starts the conversion Scan cycle. During the complete cycle, even when the scan timer is enabled, reading the ADC_MODE[1:0] bits gives a ‘11’ code output, meaning that the Scan cycle is ongoing. Rewriting ADC_MODE[1:0] = 11 during Scan mode will immediately reset and restart the entire Scan sequence from the beginning of the sequence. The conversion start pulse will also be regenerated if the EN_STP bit is enabled. The restart of the Scan sequence may induce a TADC_SETUP additional delay if the ADC is in ADC Shutdown mode when the ADC_MODE bits are overwritten (this can happen if the ADC_MODE bits are overwritten during the timer delay period, where the ADC is placed into ADC Shutdown mode in between two Scan cycles). The ADCDATA register is always updated with the last conversion results. The ADCDATA register cannot provide incomplete conversion results. The A/D conversion must be completed to be able to provide a result in the ADCDATA register. Each end of conversion generates a data ready interrupt on all three IRQ mechanisms (see Section 6.8.1 “Conversion Data Ready Interrupt”). The ADCDATA register is never cleared when the device transitions from one mode to another. The only way to clear the ADCDATA register is a POR event or a Full Reset Fast command (see Section 6.2.5 “Fast Commands Description”). ADC OPERATING MODES DESCRIPTION ADC_MODE[1:0] ADC Mode Description 11 Conversion The ADC is placed into Conversion mode and consumes the specified current. A/D conversions can be reset and restarted immediately once this mode is effectively reached. This mode may be reached after a maximum of TADC_SETUP time, depending of the current state of the ADC. 10 Standby Conversions are stopped. ADC is placed into Reset but consumes almost as much current as in Conversion mode. A/D conversions can start immediately once this mode is effectively reached. This mode may be reached after a maximum of TADC_SETUP time, depending of the current state of the ADC. 0x ADC Shutdown  2020-2021 Microchip Technology Inc. Conversions are stopped. ADC is placed into ADC Shutdown mode and does not consume any current. A/D conversions can only start after TADC_SETUP start-up time. This mode is effective immediately after being programmed. DS20006404C-page 53 MCP3461/2/4R 5.10 Low-Power Shutdown Modes The device incorporates two low-power modes that can be activated in order to limit power consumption of the device when ADC is not used. These two modes are called Partial Shutdown and Full Shutdown modes. 5.10.1 FULL SHUTDOWN MODE The Full Shutdown mode can only be enabled by sending a Fast Command Full Shutdown (Fast command code: ‘1101’). Note that the execution of this Fast command forces the CONFIG0 to be set to 0x00 (no active block is enabled). Full Shutdown mode is the lowest power mode of the device. None of the circuits consuming static power are active in this mode. As stated in Section 5.8 “Power-on Reset”, the AVDD/DVDD POR monitoring circuits are not active while in Full Shutdown mode. Note: If the digital power supply resides for a long period of time below the POR threshold and to a sufficiently low voltage (typically below 0.6V), some bits previously set to ‘1’ can toggle to ‘0’ and not be set properly. In order to ensure a safe operation after the Full Shutdown mode, follow the sequence of commands: - Write LOCK register to 0xA5 - Write IRQ register to 0x03 - Send a Fast CMD Full Reset (1110) - Reconfigure the chip as desired This sequence ensures a recovery with the desired settings in any loss-of-power scenario. TABLE 5-11: The part can still be accessed through the SPI interface during this mode and will accept incoming SPI commands. The ADCDATA register is not cleared during Full Shutdown mode and still holds previous conversion results. The other register settings are not modified or reset due to entering Full Shutdown mode. The Full Shutdown mode stops all internal timers and resets them. Sending a Fast CMD to change the operating mode exits the Full Shutdown mode. The user should place all digital inputs to a static value (logic low or high) in order to optimize power consumption during Full Shutdown mode. The current consumption specifications during Full Shutdown mode are intended without any digital pin toggling during the measurement. In this case, only leakage current is consumed throughout the device and this current varies exponentially with respect to absolute temperature. 5.10.2 PARTIAL SHUTDOWN MODE Partial Shutdown mode is achieved when CONFIG0 is set to ‘0000000x’. In this mode, most of the internal circuits are shut down, with the exception of the POR monitoring and internal biasing circuits. During the Partial Shutdown mode, the power supply is continuously monitored, whereas in Full Shutdown mode, the POR monitoring circuits are powered down. The power consumption is also much higher in Partial Shutdown mode due to the POR monitoring circuits being active. Partial Shutdown mode allows the device to be restarted and put back in Conversion mode faster than Full Shutdown mode. Table 5-11 describes the differences between Partial and Full Shutdown modes. If the current consumption of Partial Shutdown mode is acceptable for the application, it is recommended that it is used as an alternative to Full Shutdown mode, where the POR monitoring circuits are shut down and no longer monitoring the AVDD and DVDD power supplies. LOW-POWER MODES(1) Device VREF_SEL CONFIG0[6] CLK_SEL[1:0] CS_SEL[1:0] ADC_MODE[1:0] Low-Power Mode Description Partial Shutdown 0 0 00 00 0x All peripherals, except the POR monitoring circuits and clock biasing circuits, are shut down and consume no static current.The SPI interface remains active in this mode and consumes no current while the bus is Idle. Full Shutdown 0 0 00 00 00 All analog and digital circuits are shut down and consume no static current. The SPI interface remains active in this mode and consumes no current while the bus is Idle. Note 1: x = Don’t Care DS20006404C-page 54  2020-2021 Microchip Technology Inc. MCP3461/2/4R 5.11 ADC Start-up Timer The device includes an intelligent start-up timer circuit for the ADC, which ensures that the ADC is properly biased and that internal nodes are properly settled before each conversion. This timer ensures the proper conditions for the ADC to convert with its full accuracy for each conversion. The ADC can operate in three different modes: ADC Shutdown, Standby and Conversion, as described in Section 5.9 “ADC Operating Modes”. The ADC start-up timer manages the time for the transitions between each mode. These transitions can be instantaneous or can take a maximum of 256 DMCLK periods, depending on the type of transition, and the current status of the ADC and of the internal start-up timer. The timer will always try to reduce the transition time from one state to another, but will also allow enough time for the internal circuitry to settle to the proper internal operating points. The transitions from Standby or Conversion mode to ADC Shutdown mode are always immediate. They reset the internal start-up timer to 256 DMCLK periods (TADC_SETUP). The transitions from ADC Shutdown to Standby or Conversion mode start the internal start-up timer that decrements from 256 to 0. The timer only decrements after a small delay of two MCLK periods in case of a transition caused by an SPI command. This small delay is necessary to overcome any possible synchronization issue between the two asynchronous clocks: MCLK and SCK. The timer will immediately decrement (without the synchronization delay) if the transitions are generated by the internal state machine (for example, when the transitions are generated by the Scan sequence). Once the timer reaches 0 (when the user has clocked 256 DMCLK periods), the device reaches its internal proper operating points and will either stay in Standby mode (if ADC_MODE[1:0] = 10) or start the Conversion mode (if ADC_MODE[1:0] = 11). The transition from Standby to Conversion mode and vice versa is immediate once the timer has reached 0 (if ADC_MODE[1:0] = 11). If the transition from Standby to Conversion mode occurs, and if the timer has not yet reached 0, the timer will continue to decrement to 0 before effectively starting the conversion. The timer cannot decrement faster than 256 DMCLK periods when the ADC transitions from ADC Shutdown mode to Conversion mode (from ADC Shutdown mode, the ADC is allowed 256 DMCLK periods to power-up and settle to its desired operating point before starting conversions). The start-up time has been sized at 256 DMCLK clock periods for the part to be able to settle in all conditions and with all possible clock frequencies as specified. Table 5-12 summarizes the behavior of the internal start-up timer as a function of the ADC_MODE[1:0] bits setting. Rewriting ADC_MODE[1:0] bits without changing the bit settings does not modify the internal timer and cannot shorten the start-up delay necessary to start accurate conversions. A synchronization delay of two MCLK periods occurs after each rewrite if ADC_MODE[1:0] = 1x. In Scan mode, when CONV_MODE[1:0] = 11 (Continuous mode), the ADC may be placed in ADC Shutdown mode and restarted in between each Scan cycle depending on the TIMER[23:0] bits setting (see Section 5.15.5 “Delay Between Scan Cycles (TIMER[23:0])”). If the TIMER register is programmed with a decimal code greater than TADC_SETUP = 256, the internal timer will automatically place the part in ADC Shutdown mode at the end of the cycle and will start to transition to the next cycle 256 DMCLK periods before the end of the TIMER delay. This lowers the power consumed during the TIMER delay as much as possible. If the value of the TIMER delay is less than 256 DMCLK periods, the part will not enter ADC Shutdown mode and stay in Standby during the TIMER delay (in this case, the power consumed is equivalent to the Conversion mode power consumption). In order to catch the start of the conversion in case of complex sequences of transitions, it can be useful to enable the EN_STP bit so that the part will generate a pulse on the IRQ pin to indicate a conversion start. Figure 5-11 shows different cases of transitions between modes and shows the internal state of the start-up timer for each step. TABLE 5-12: ADC START-UP TIMER BEHAVIOR AS A FUNCTION OF ADC_MODE[1:0] SETTINGS ADC_MODE[1:0] ADC State 11 Conversion 10 Standby 0x ADC Shutdown  2020-2021 Microchip Technology Inc. ADC Start-up Timer Behavior The ADC start-up timer decrements to 0. The conversion starts when it reaches 0. The ADC start-up timer decrements to 0. The ADC is ready to convert when it reaches 0. ADC start-up timer is reset to TADC_SETUP = 256. DS20006404C-page 55 MCP3461/2/4R DMCLK Continuous Clocking SPI Wri te Wri te Wri te AD C _M ODE = 1x AD C _M ODE = 0x AD C _M ODE = 1x 0x 1x 0x 1x Timer Reset Switching Between ADC_MODE = 10 and 11 has no Effect on the Timer ADC_MODE Timer Reset ADC Start-up Timer Decimal Code Timer Countdown Wri te 1X AD C _M ODE = 1x 256 ADC Ready to Convert 0 FIGURE 5-11: 5.12 ADC Start-up Timer Timing Diagram. Master Clock Selection/Internal Oscillator The device includes three possible clock modes for the master clock generation. The Master Clock (MCLK) is used by the ADC to perform conversions and is also used by the digital portion to generate the different digital timers. The clock mode selection is made through the CLK_SEL[1:0] bits located in the CONFIG0 register. The possible selections are described in Table 5-13. The master clock is not propagated in the chip when the chip enters the Full Shutdown mode (see Section 5.10 “Low-Power Shutdown Modes”). Any change to the CLK_SEL bits creates a Reset and Restart for the currently running conversions, and a Restart of the ADC setup timer. Each Reset and Restart resets all internal phases to their default values and can lead to a possible temporary duty cycle change at the clock output pin. TABLE 5-13: CLK_SEL[1:0] CLOCK SELECTION BITS Clock Mode MCLK Pin 00 or 01 External Clock MCLK digital input 10 Internal RC Oscillator, no clock output High-Z 11 Internal RC Oscillator with clock output AMCLK digital output DS20006404C-page 56 5.12.1 EXTERNAL MASTER CLOCK MODE (CLK_SEL[1:0] = 0x) The External Clock mode is used to input the MCLK clock necessary for the ADC conversions and can accept duty cycles with a large range since the clock is redivided internally to generate the different internal phases. The external clock can be provided on the MCLK pin for the MCP3461/2/4R devices. 5.12.2 INTERNAL OSCILLATOR The device includes an internal RC-type oscillator powered by the digital power supply (DVDD/DGND). The frequency of this internal oscillator ranges from 3.3 MHz to 6.6 MHz. The oscillator is not trimmed in production, therefore, the precision of the center frequency is approximately ±30% from chip to chip. The duty cycle of the internal oscillator is centered around 50% and varies very slightly from chip to chip. The internal oscillator has no Reset feature and keeps running once selected.  2020-2021 Microchip Technology Inc. MCP3461/2/4R 5.12.3 INTERNAL MASTER CLOCK MODES (CLK_SEL[1:0] = 1x) When CLK_SEL[1] = 1, the internal oscillator is selected and the master clock is generated internally. The internal oscillator has no Reset feature and continues to run once selected. The master clock generation is independent of the ADC as the clock can still be generated, even if the ADC is in ADC Shutdown mode. The internal oscillator is only disabled when CLK_SEL[1:0] = 0x. The clock can be distributed to the dedicated output pin depending on the CLK_SEL[0] bit. When the clock output is selected (CLK_SEL[0] = 1), the AMCLK clock derived from the MCLK (AMCLK = MCLK/PRESCALE) is available on the output pin. The AMCLK output can serve as the clock pin to synchronize the modulator output or other MCP3461/2/4R devices that are configured with CLK_SEL[1:0] = 00 or 01. The AMCLK output is available on the MCLK clock output pin as soon as the Write command (CLK_SEL[1:0] = 11) is finished. 5.13 Digital System Offset and Gain Calibrations The MCP3461/2/4R devices include a digital calibration feature for offset and gain errors. The calibration scheme for offset error consists of the addition of a fixed offset value to the ADC output code (ADCDATA at address: 0x0). The offset value added (OFFSETCAL) is determined in the OFFSETCAL register (address: 0x9). The calibration scheme for gain error consists of the multiplication of a fixed gain value to the ADCDATA code. The gain value (GAINCAL) multiplied is determined in the GAINCAL register (address: 0xA). The digital offset and gain calibration schemes are enabled or disabled via the EN_OFFCAL and EN_GAINCAL control bits of the CONFIG3 register. When both calibration control bits are enabled (EN_OFFCAL = EN_GAINCAL = 1), the ADCDATA register is modified with the digital offset and gain calibration schemes, as described in Equation 5-6. When a calibration enable bit is off, its corresponding register becomes a Don’t Care register and the corresponding calibration is not performed. EQUATION 5-6: ADCDATA OUTPUT AFTER DIGITAL GAIN AND OFFSET ERROR CALIBRATION ADCDATA (post-calibration) = [ADCDATA (pre-calibration) + OFFSETCAL] x GAINCAL  2020-2021 Microchip Technology Inc. The calculations are performed internally with proper management of overloading, so that the overload detection is done on the output result only and not on the intermediate results. A sufficient number of additional overload bits are maintained and propagated internally to overcome all possible overload and/or overload recovery situations. For example, if ADCDATA (pre-calibration) + OFFSETCAL is out of bounds, but (ADCDATA (pre-calibration) + OFFSETCAL) x GAINCAL is still in the right range (possible with 0 < GAINCAL < 1), the result is not saturated. 5.13.1 DIGITAL OFFSET ERROR CALIBRATION The Offset Calibration register (OFFSETCAL, address: 0x9) is a signed MSb first, two’s complement coding, 24-bit register that holds the digital offset calibration value, OFFSETCAL. The OFFSETCAL equivalent input voltage value is calculated with Equation 5-7. EQUATION 5-7: OFFSETCAL CALIBRATION VALUE (EQUIVALENT INPUT VOLTAGE) OFFSETCAL (V) = VREF x (OFFSETCAL[23:8] signed decimal code)/(32768 x GAIN) For the MCP3461/2/4R devices, the offset calibration is done by adding the OFFSETCAL[23:8] calibration value to the ADCDATA output code, bit by bit. The last byte of the OFFSETCAL register (OFFSETCAL[7:0]) is ignored and internally reset to 0x00 during the calibration; therefore, the addition just takes into account the OFFSETCAL[23:8] bits and is done bit-by-bit with the ADC output code. The offset calibration value range in equivalent voltage is [-VREF/GAIN; (+VREF – 1 LSb)/GAIN], which can cancel any possible offset in the ADC but also in the system. The offset calibration is realized with a simple 24-bit signed adder and is instantaneous (no pipeline delay). Enabling the offset calibration will affect the next conversion result; the conversion result already held in the ADCDATA register (0x0) is not modified when the EN_OFFCAL is set to ‘1’, but the next one will take the offset calibration into account. Changing the OFFSETCAL register to a new value will not affect the current ADCDATA value, but the next one (after a data ready interrupt) will take the new OFFSETCAL value into account. Figure 5-12 presents the different cases and their impact on the ADCDATA register and the IRQ output. DS20006404C-page 57 MCP3461/2/4R Wri te OFFSETCAL[2 3 :] = OFFSETCAL1 SPI ADC STATUS Wri te OFFSETCAL[2 3 :] = OFFSETCAL2 Data 1 Conversion Data 2 Conversion Data 3 Conversion Data 4 Conversion DATA0 DATA1 DATA2 + OFFSETCAL1 DATA3 + OFFSETCAL2 IRQ ADC DATA REGISTER VALUE FIGURE 5-12: 5.13.2 Wri te EN _OFFC AL = 1 ADC Output and IRQ Behavior with Digital Offset Calibration Enabled. DIGITAL GAIN ERROR CALIBRATION The Gain Error Calibration register (GAINCAL, address: 0xA) is an unsigned 24-bit register that holds the digital gain error calibration value, GAINCAL. Equation 5-8 calculates the GAINCAL multiplier. EQUATION 5-8: GAINCAL CALIBRATION VALUE (MULTIPLIER VALUE) GAINCAL (V/V) = (GAINCAL[23:8] unsigned decimal code)/32768 For the MCP3461/2/4R devices, the gain error calibration is done by multiplying the GAINCAL value to the ADC output code. The last byte of the GAINCAL register (GAINCAL[7:0]) is ignored and internally reset to 0x00 during the calibration; therefore, the multiplication just takes into account the GAINCAL[23:8] bits. error calibration is made with a simple add-and-shift circuit clocked on DMCLK and induces a pipeline delay of TGCAL = 15 DMCLK periods. This pipeline delay acts as a delay on the data ready interrupt position that is shifted by TGCAL = 15 DMCLK periods. During this delay, the converter can process the next conversion, the delay does not shift the next conversion and does not change the Conversion Time, TCONV. Enabling the gain error calibration will affect the next conversion result. The conversion result already held in the ADCDATA register (0x0) is not modified when the EN_GAINCAL is set to ‘1’, but the next one will take the offset calibration into account. Changing the GAINCAL register to a new value will not affect the current ADCDATA value, but the next one (after a data ready interrupt) will take the new GAINCAL value into account. Figure 5-13 shows the different cases and their associated effects on the ADCDATA register and the IRQ output. The gain error calibration value range in equivalent voltage is [0; 2-2-15], which can cancel any possible gain error in the ADC and in the system. The gain Wri te GAINCAL[2 3 :] = GAINCAL1 SPI ADC STATUS Data 1 Conversion Wri te EN _GAIN C AL = 1 Wri te GAINCAL[2 3 :] = GAINCAL2 Data 2 Conversion Data 3 Conversion Data 4 Conversion IRQ ADCDATA DATA0 DATA1 DATA2 x GAINCAL1 TGCAL FIGURE 5-13: DS20006404C-page 58 DATA3 x GAINCAL2 TGCAL ADC Output and IRQ Behavior with Digital Gain Error Calibration Enabled.  2020-2021 Microchip Technology Inc. MCP3461/2/4R 5.14 Conversion Modes The ADC includes several Conversion modes that can be selected through the CONV_MODE[1:0] bits located in the CONFIG3 register. The ADC behavior, with respect to these bits, depends on whether the ADC is in MUX or Scan mode. Table 5-14 summarizes the possible configurations. TABLE 5-14: ADC CONVERSION MODES IN MUX OR SCAN MODES CONV_MODE[1:0] 5.14.1 ADC Behavior (MUX Mode) ADC Behavior (Scan Mode) ADC_MODE[1:0] Bits Setting 0x Performs a one-shot conversion Performs one complete and automatically returns to Scan cycle and ADC Shutdown mode. automatically returns to ADC Shutdown mode. Returns to ‘0x’ after one conversion (MUX mode) or one Scan cycle (Scan mode). 10 Performs a one-shot conversion Performs one complete and automatically returns to Scan cycle and Standby mode. automatically returns to Standby mode. Returns to ‘10’ after one conversion (MUX mode) or one Scan cycle (Scan mode). 11 Performs continuous conversions. Stays at ‘11’. CONVERSION MODES IN MUX MODE In MUX mode, the user can choose between one-shot and continuous conversions. A one-shot conversion is a single conversion and takes a certain Conversion Time, TCONV (or 2 x TCONV when AZ_MUX = 1, see Section 5.1.3 “ADC Offset Cancellation Algorithm”). Once this conversion is performed, the part automatically returns to a Standby or ADC Shutdown state, depending on the CONV_MODE[1:0] bits setting. The Conversion mode determined by the CONV_MODE[1:0] bits setting will also affect the state of the ADC_MODE[1:0] as described in Table 5-14. The conversion can be preceded by a start-up time that depends on the ADC state (see Section 5.11 “ADC Start-up Timer”). In One-Shot mode, the ADC data have to be read completely with the SPI interface for the interrupt to be cleared on the IRQ pin (the IRQ pin cannot be automatically cleared like in the Continuous Conversion mode). This mode is recommended for low-power, low bandwidth applications, requiring a once in a while A/D conversion.  2020-2021 Microchip Technology Inc. Performs continuous Scan cycles with TIMER[23:0] delay between each cycle. In Continuous Conversion mode, the ADC is never placed in Standby or ADC Shutdown mode and converts continuously without any internal Reset. In this mode, the output data rate of the ADC is defined by DRCLK (see Figure 5-5). The digital decimation filter induces a pipeline or group delay of TCONV for the first data ready and is structured to give a continuous stream of data at the DRCLK rate after these first data (the internal registers of the filter are never reset in this mode, thus the decimation filter acts as a moving average). Each data ready interrupt corresponds to a valid and complete conversion that was processed through the digital filter (the digital filter has no latency in this respect). This mode allows a faster data rate than the One-Shot mode, and is therefore, recommended for higher bandwidth applications. The pipeline delay should be carefully determined and adapted to the user needs, especially in closed-loop, low-latency applications. This mode is recommended for applications requiring continuous sampling/averaging of the input signals. If AZ_MUX = 1, the Continuous Conversion mode is replaced by a series of subsequent One-Shot mode conversions with a reset in between each conversion. This makes the group delay equal to 2 x TCONV and the data rate equal to 1/(2 x TCONV). Figure 5-14 and Figure 5-15 detail One-Shot and Continuous Conversion modes for MUX mode. DS20006404C-page 59 MCP3461/2/4R ADC Data Read can be tDODR Performed During this Time SPI Write CONV _MOD E = 0x o r 10 MCLK ADC_MODE ADC STATUS Wri te ADC_MOD E = 11 Read ADC Data Don’t Care Continuous Clocking Don’t Care 00 11 ‘0x’ or ‘10’ Depending on CONV_MODE[1:0] Partial Shutdown IRQ Start-up Conversion TADC_SETU P TCONV Conversion Start (Generates Pulse if EN_STP = 1) FIGURE 5-14: Partial Shutdown or Reset Depending on CONV_MODE[1:0] TS TP IRQ is Cleared at First SCK Falling Edge After ADC Read Start MUX One-Shot Conversion Mode Timing Diagram. SPI MCLK ADC_MODE ADC STATUS Read A DC Data 1 Write Write CONV_ MOD E = 11 ADC _MODE = 11 Don’t Care Continuous Clocking 00 11 Partial Shutdown Start-up Data 1 Conversion Data 2 Conversion Data 3 Conversion T A DC_S E TUP TCONV 1/DRCLK 1/DRCLK IRQ FIGURE 5-15: DS20006404C-page 60 R ea d A DC Data 2 T DRH TDRH MUX Continuous Conversion Mode Timing Diagram.  2020-2021 Microchip Technology Inc. MCP3461/2/4R 5.14.2 CONVERSION MODES IN SCAN MODE If CONV_MODE[1:0] = 11, the ADC runs in a Scan Cycle mode with a TIMER[23:0] delay between cycles. Writing the CONV_MODE[1:0] bits with the SPI interface within a conversion does not create an internal Reset. It is recommended not to wait for the end of a conversion to change the CONV_MODE[1:0] bits to the desired value, but to change to the desired value just after the data are ready to avoid possible glitches. Figure 5-16 and Figure 5-17, respectively, detail the ADC timing behavior in One-Shot and Continuous Conversion modes, when configured for Scan mode, with N channels chosen among 16 Scan possibilities. In Scan mode, the device takes one conversion per channel and multiplexes the input to the next channel in the Scan sequence. Therefore, all conversions are One-Shot mode conversions, no matter how the CONV_MODE[1:0] bits are set. Each conversion takes the same time, TCONV (or 2 x TCONV when AZ_MUX = 1, see Section 5.1.3 “ADC Offset Cancellation Algorithm”), to be performed. If CONV_MODE[1:0] = 00, 01 or 10, the Scan cycle is executed once and then the ADC is placed into Standby or ADC Shutdown mode. SPI Write CONV_MODE = 0x/10 MCLK Write ADC_MODE = 11 Don’t Care ADC STATUS Start-up Channel 1 Conversion Reset Channel 2 Conversion Reset Channel N Conversion (Last in Cycle) TDLY_SCAN TCONV TADC_SETUP TCONV TDLY_SCAN TCONV IRQ Scan One-Shot Conversion Mode Timing Diagram. Write CONV_MODE = 11 Write ADC_MODE = 11 Read ADC Data 1 Read ADC Data N-1 Don’t Care ADC_MODE ADC Shutdown or Reset Depending on CONV_MODE TDRH TDRH MCLK ADC STATUS ‘0x’ or ‘10’ Depending on CONV_MODE 11 ADC Shutdown FIGURE 5-16: Read ADC Data N Continuous Clocking 00 ADC_MODE SPI Read ADC Data N-1 Read ADC Data 1 Read ADC Data1 (New Cycle) Read ADC Data N Continuous Clocking 00 11 TADC_SETUP ADC Shutdown Start-up Channel 1 Conversion Reset Channel 2 Conversion Reset Channel N Conversion (Last in Cycle) TDLY_SCAN TCONV TADC_SETUP TCONV IRQ TCONV TDLY_SCAN TDRH ADC Shutdown or Reset Depending on TIMER[23:0] Settings TTIMER_SCAN Start-up Channel 2 Conversion Channel 1 Conversion Reset (New Cycle) (New Cycle) TCONV TDLY_SCAN TDRH TDRH TCONV TDRH Start-up Time is Reduced to 0 if TTIMER_SCAN < 256 DMCLK Periods FIGURE 5-17: Scan Continuous Conversion Mode Timing Diagram.  2020-2021 Microchip Technology Inc. DS20006404C-page 61 MCP3461/2/4R 5.15 Scan Mode 5.15.1 5.15.2 SCAN MODE PRINCIPLE The ADC is, by default, in MUX mode at power-up. The ADC enters Scan mode as soon as one of the SCAN[15:0] bits in the SCAN register is set to ‘1’. MUX mode and Scan mode cannot be enabled at the same time. When SCAN[15:0] = 0x0000, Scan mode is disabled and the part returns to MUX mode, where the input channel selection is defined by the MUX[7:0] bits. In Scan mode, the device sequentially and automatically converts a list of predefined differential inputs (also referred to as input channels) in a defined order. After this series of conversions, the ADC can be placed in Standby or ADC Shutdown mode, or it can wait a certain time in order to perform the same sequence of conversions periodically. The Scan cycle conversions are effectively started as soon as the ADC_MODE[1:0] bits are programmed through the SPI interface to ‘11’ (direct Write or Fast command, ADC Reset and Restart). After the ADC_MODE[1:0] bits are set to ‘11’, they keep the same value until the Scan mode is completed or aborted. This mode is useful for applications that require constant monitoring of defined channels or internal resources (like AVDD or VCM), and allow a minimal and simplified communication. When in Scan mode, the MUX register (address: 0x6) becomes a Don’t Care register. Each SCAN[15:0] bit defines a possible input channel for the Scan cycle, which corresponds to a certain selection of the analog multiplexer input channel and possibly a certain predefined gain of the ADC. The Scan cycle will process and convert each channel that has been enabled (SCAN[n] = 1) with a defined order of priority, from MSb to LSb (SCAN[15] to SCAN[0]). The list of channels with their corresponding inputs is defined in Table 5-15. Scan mode includes a configurable delay between each Scan cycle, as well as a configurable delay between each conversion within a Scan cycle. Each conversion within the Scan cycle leads to a data ready interrupt and to an update of the ADCDATA register as soon as the current conversion is finished. The device does not include additional memory to retain all Scan cycle A/D conversion results. Therefore, each result has to be read when it is available and before it is overwritten by the next conversion result. TABLE 5-15: SCAN MODE ENABLE AND SCAN CHANNEL SELECTION When using DATA_FORMAT[1:0] = 11, each channel conversion result in the Scan sequence can be identified with a Channel ID (CH_ID[3:0]) code that will appear in the four MSbs of the ADCDATA register output value (Section 5.6 “ADC Output Data Format”). The Channel ID indicates the channel that sends the output data. Table 5-15 shows each possible Channel ID value and its associated channel. ADC CHANNEL SELECTION SCAN[n] Bit(1) Channel Name 15 OFFSET 14 13 VCM AVDD 12 11 TEMP Differential Channel D (CH6-CH7) 10 9 MUX[7:0] Corresponding Setting Specific ADC Gain 1111 0x88 None 1110 1101 0xF8 0x98 1x 0.33x 1100 1011 0xDE 0x67 1x None Differential Channel C (CH4-CH5) Differential Channel B (CH2-CH3) 1010 1001 0x45 0x23 None None 8 7 Differential Channel A (CH0-CH1) Single-Ended Channel CH7 1000 0111 0x01 0x78 None None 6 5 Single-Ended Channel CH6 Single-Ended Channel CH5 0110 0101 0x68 0x58 None None 4 3 Single-Ended Channel CH4 Single-Ended Channel CH3 0100 0011 0x48 0x38 None None 2 1 Single-Ended Channel CH2 Single-Ended Channel CH1 0010 0001 0x28 0x18 None None 0 Note 1: Channel ID Single-Ended Channel CH0 0000 0x08 None SCAN[11:9] and SCAN[7:2] are not available for MCP3461R. Writing these bits has no effect. SCAN[11:10] and SCAN[7:4] are not available for MCP3462R. Writing these bits has no effect. DS20006404C-page 62  2020-2021 Microchip Technology Inc. MCP3461/2/4R 5.15.3 5.15.3.1 SCAN MODE INTERNAL RESOURCE CHANNELS Analog Supply Voltage Reading (AVDD) During the conversion that reads AVDD in Scan mode, the multiplexer selection becomes 0x98 (AVDD – AGND), which is equal to the analog power supply voltage. Since AVDD is the highest voltage available in the chip, when reading AVDD in Scan mode, the gain of the ADC is automatically set to 1/3x, which maximizes the input full-scale range regardless of the GAIN[2:0] bits setting. This temporary internal configuration does not change the register settings, it only impacts the gain of the device during this conversion. With this fixed 1/3x gain, the ADC can measure the maximum specified analog supply voltage (AVDD = 3.6V) with a reference voltage as low as 1.2V. 5.15.3.2 Offset Reading (OFFSET) During the conversion that reads OFFSET in Scan mode, the differential MUX output is shorted to AGND (internally). The offset reading varies from part to part, and over AVDD and temperature. The reading of this offset value can be used for the device offset calibration or tracking of the offset value in applications. There is no automatic offset calibration in the device, so the user has to manually write the opposite (signed value) of the offset measured into the OFFSETCAL register to effectively cancel the offset on the subsequent outputs. 5.15.3.4 5.15.4 DELAY BETWEEN CONVERSIONS WITHIN A SCAN CYCLE (DLY[2:0]) While the ADC and multiplexer are optimized to switch from one channel to another instantaneously, it may not be the case of an application that requires additional settling time to overcome the transition. The device can insert an additional delay between each conversion of the Scan cycle. The delay value is controlled by the DLY[2:0] bits located in the SCAN register (SCAN[23:20]). See Table 5-16. TABLE 5-16: Temperature Reading (TEMP) During the conversion that reads TEMP in Scan mode, the multiplexer selection becomes 0xDE, which enables the two temperature diode sensors at each input of the ADC. During the temperature reading, the ADC gain is automatically set to 1x regardless of the GAIN[2:0] bits setting. This temporary internal configuration does not change the register setting, it only impacts the gain of the device during this conversion. 5.15.3.3 The VCM reading is susceptible to the gain and offset errors of the ADC, which should be calibrated to obtain a precise internal Common-mode measurement. VCM Reading (VCM) During the conversion that reads VCM, the device monitors the internal Common-mode voltage of the device in order to ensure proper operation. DELAY BETWEEN CONVERSIONS WITHIN A SCAN CYCLE DLY[2:0] Delay Value (DMCLK Periods) 111 512 110 256 101 128 100 64 011 32 010 16 001 8 000 0 The delay is only added in between two conversions of the same Scan cycle. There is no delay added at the end or the beginning of each Scan cycle due to the DLY[2:0] bits setting. During this delay, the ADC is internally kept in Standby mode (ADC_MODE[1:0] = 10 internally, but the ADC_MODE[1:0] bits are always read as ‘11’ through the SPI interface). The analog multiplexer switches to the next selected input at the end of each conversion (i.e., at the beginning of the added delay, so that the application has additional time to settle properly). The VCM voltage of the device should be located at 1.2V ± 2% to ensure proper accuracy. With this setting, the internal multiplexer setting becomes 0xF8 (VCM – AGND). In order to properly measure VCM, the reference voltage must be larger than 1.2V. During the VCM reading, the gain of the ADC is set to 1x regardless of the GAIN[2:0] bits setting. This temporary internal configuration does not change the register setting, it impacts the gain of the device during this conversion.  2020-2021 Microchip Technology Inc. DS20006404C-page 63 MCP3461/2/4R 5.15.5 DELAY BETWEEN SCAN CYCLES (TIMER[23:0]) The device incorporates an automatic Reset and Restart feature for the A/D conversions to avoid these invalid data. Some register writes with the SPI interface during a conversion will automatically reset and restart the A/D conversion with the new settings. During Continuous mode, Scan cycles are processed continuously, one after another, separated by a time delay (TTIMER_SCAN), which is defined by the TIMER register (address: 0x8) value. During this delay, the ADC is automatically placed into a power-saving mode (Standby or ADC Shutdown). The TTIMER_SCAN delay offers better power efficiency for applications which run a scan sequence periodically. Since the delay can be very long, it allows synchronous applications with very slow update rates without having to use an external timer. The TIMER register defines the time, TTIMER_SCAN, between cycles with a 24-bit unsigned value going from 0 to 16777215 DMCLK periods. Table 5-17 details the TIMER values with respect to the TIMER[23:0] code. 5.16.1 TABLE 5-17: 5.16.2 TIMER DELAY VALUE BETWEEN SCAN CYCLES TIMER[23:0] TTIMER_SCAN Delay Value (DMCLK Periods) 111111111111111111111111 16777215 111111111111111111111110 16777214 100000000000000000000000 8388608 000000000000000000000001 1 000000000000000000000000 0 The internal TIMER counter will decrement from the TTIMER_SCAN value to 0 and launch the new Scan cycle. If the TTIMER_SCAN value is greater than TADC_SETUP (256 DMCLK periods), the device will enter ADC Shutdown mode (ADC_MODE is set to ‘00’ internally) at each end of a Scan cycle. When the internal TIMER counter reaches 256, the device will start the ADC during a TADC_SETUP time to be ready to convert when the internal counter reaches 0. If the TTIMER_SCAN value is less than TADC_SETUP, the part will be placed in Standby mode between Scan cycles (ADC_MODE is set to ‘10’ internally). ADC_MODE[1:0] bits in the CONFIG0 register can only be read as ‘11’ by the SPI interface during the entire Scan cycle and between Scan cycles. 5.16 A/D Conversion Automatic Reset and Restart Feature When the A/D conversions are running, the user can change the device configuration through the SPI interface by writing any register. Some register settings directly impact the conversion results and lead to invalid ADC data if they are changed within a conversion. DS20006404C-page 64 The automatic Reset and Restart feature behavior depends on the register bits that are written by the SPI interface. REGISTER BIT MODIFICATIONS NOT CAUSING RESET/RESTART The first group of bits will not generate any Reset and Restart. This group is composed of all the unused bits, all the read-only bits and some digital settings, such as the CONV_MODE[1:0], DATA_FORMAT[1:0], CRC_FORMAT, EN_CRCCOM, IRQ_MODE[0], EN_FASTCMD, EN_STP and LOCK[7:0] bits. REGISTER BIT MODIFICATIONS CAUSING IMMEDIATE RESET/RESTART The second group of bits generates a Reset and a Restart. The Reset is immediate, the Restart is only valid after a period of two MCLK periods (necessary to handle the Reset and ensures that the Restart is synchronous with the master clock). This group is composed of settings that do not induce an analog operating point change. This group includes: ADC_MODE[1:0], PRE[1:0], OSR[3:0], GAIN[2:0], AZ_MUX, EN_OFFCAL, EN_GAINCAL, IRQ_MODE[1:0], MUX[7:0] and DLY[2:0] bits. The EN_OFFCAL, EN_GAINCAL and IRQ_MODE[1:0] bits generate the Reset and Restart only if they are changed to a new value. An overwrite of the same value has no effect. In Scan mode, the Reset and Restart feature will just restart the current conversion for this group of bits; the Scan cycle is not modified and not restarted. The MUX[7:0] bits can be changed within Scan mode without generating a Reset and a Restart, since this register is a Don’t Care during Scan mode. The DLY[2:0] bits can be changed during the MUX mode without generating a Reset and Restart since these bits are Don’t Care during the MUX mode. The OFFSETCAL[23:0] and GAINCAL[23:0] bits only generate a Reset and a Restart when written if their corresponding enable bit (EN_OFFCAL, EN_GAINCAL) is enabled. The ADC_MODE[1:0] bits generate an immediate Reset and Restart, but only if they are overwritten with ‘11’ (in any other case, the conversions are stopped). Depending on the part being in MUX or Scan mode, the Reset and Restart feature will reset the conversion or the complete Scan cycle.  2020-2021 Microchip Technology Inc. MCP3461/2/4R 5.16.3 REGISTER BIT MODIFICATIONS CAUSING DELAYED RESET/RESTART A third group of bits will generate a Reset and a Restart that induce a new start-up delay (TADC_SETUP), so that the internal analog operating points can be settled with the new settings before the new conversion is started. The Reset is immediate; the start-up timer is only restarted after a period of two MCLK periods (necessary to handle the Reset and to ensure that the Restart is synchronous with the master clock). Overall, the delay from the Reset to the actual Restart of the conversion with the new settings is then 2 MCLK + TADC_SETUP. This group includes: CONFIG0 and the RESERVED registers at addresses: 0xB and 0xC. The CONFIG0 bits induce a start-up timer delay only if they are changed to a new value. If they are overwritten with the same value, they will generate an immediate Reset and Restart. In Scan mode, the Reset and Restart feature will just restart the current conversion for this group of bits, the Scan cycle is not modified and not restarted. This third group of bits will induce a start-up timer delay, even when ADC_MODE[1:0] = 10 or if the ADC is in Standby mode. Depending on the phase between the AMCLK and the SPI commands, the 2-MCLK delay can turn into a 4-MCLK delay to ensure the proper synchronization of the device. If very precise synchronization is required, it is recommended to not change the register configurations (i.e., not during conversions) or to use the EN_STP = 1 setting so that the start of the conversions can be clearly determined. In MUX mode, the TIMER and SCAN registers do not generate a Reset and Restart when written, except if the SCAN register is modified to effectively enter into Scan mode. In this case, the MUX mode is superseded by the Scan mode immediately. In Scan mode, a write access of the SCAN register, during or between conversions within the Scan cycle, will create a Reset and Restart of the whole Scan sequence. Within the same conditions, a write access on the TIMER register will not create a Reset and Restart of the entire Scan sequence. However, during the TTIMER_SCAN delay between Scan cycles, a write on the SCAN register does not generate a Reset and a Restart of the entire sequence. Within the same conditions, a write on the TIMER register generates a Reset and a Restart of the entire sequence. During the Reset and Restart sequence, the Reset is immediate and resets the internal phases to the original state, which can lead to a discontinuity in the clock output frequency if the AMCLK clock output is enabled. The Restart is synchronous with the AMCLK generation and is effective only after two MCLK periods. The Restart also generates a conversion start pulse (only after the two MCLK periods or the two MCLK + TADC_SETUP necessary for the Restart) if enabled, for the user to be able to align the system with the exact start of the new conversion.  2020-2021 Microchip Technology Inc. DS20006404C-page 65 MCP3461/2/4R NOTES: DS20006404C-page 66  2020-2021 Microchip Technology Inc. MCP3461/2/4R 6.0 SPI SERIAL INTERFACE AND DEVICE OPERATION 6.1 Overview The MCP3461/2/4R devices use an SPI interface to read and write the internal registers. The device includes a four-wire (CS, SCK, SDI, SDO) serial SPI interface that is compatible with SPI Modes 0,0 and 1,1. Data are clocked out of the device on the falling edge of SCK and data are clocked into the device on the rising edge of SCK. In these modes, the SCK clock can Idle either high (1,1) or low (0,0). The digital interface is asynchronous with the MCLK clock that controls the ADC sampling and digital filtering. All digital input pins are Schmitt Triggered to avoid system noise perturbations on the communications. The SPI interface is maintained in a Reset state during POR. Each SPI communication starts with a CS falling edge and stops with the CS rising edge. Each SPI communication is independent. When CS is logic high, SDO is in high-impedance, the transitions on SCK and SDI have no effect. Changing from SPI Mode 1,1 to an SPI Mode 0,0 and vice versa is possible and must be done while the CS pin is logic high. Any CS rising edge clears the communication and resets the SPI digital interface. See Figure 1-1 for the SPI timing details. The MCP3461/2/4R digital interface is capable of handling various Continuous Read and Write modes, which allows for ADC data streaming or full register map writing within only one communication (and therefore, with only one unique COMMAND byte). It also includes single byte Fast commands. The device does not include a Host Reset pin, but it includes an SPI Fast command to be able to fully reset the part at any time and place it back in a default configuration. The device family also includes advanced security features to secure communication and alert users of unwanted Write commands that change the desired configuration. To secure the entire configuration, the device includes an 8-bit lock code (LOCK[7:0]), which blocks all Write commands to the full register map if the value of the lock code is not equal to a defined password (0xA5). The user can protect its configuration by changing the LOCK[7:0] value to 0x00 after full programming, so that any unwanted Write command will not result in a change in the configuration. Each SPI read communication can be secured through a selectable CRC-16 checksum provided on the SDO pin at the end of every communication sequence. This checksum computation is compatible with the DMA CRC hardware of the PIC24 and PIC32 MCUs, as well as many other MCU references, resulting in no additional overhead for the added security.  2020-2021 Microchip Technology Inc. Once the part is locked (write-protected), an additional checksum calculation also runs continuously in the background to ensure the integrity of the full register map. All writable registers of the register map are processed through a CRC-16 calculation engine and give a CRC-16 checksum that depends on the configuration. This checksum is readable from the CRC register and updated when MCLK is running. If there is a change in the checksum, a CRC interrupt generates a flag to warn the user that the configuration has been corrupted. The MCP3461/2/4R devices also include additional digital signal pins, such as a dedicated IRQ interrupt output pin and a Master Clock (MCLK) input/output pin, which allow easier synchronization and faster interrupt handling, facilitating the implementation of the device in many different applications. 6.2 SPI Communication Structure The MCP3461/2/4R devices’ interface has a simple communication structure. Every communication starts with a CS falling edge and stops with a CS rising edge. The communication is always started by the COMMAND byte (8 bits) clocking on the SDI input. The COMMAND byte defines the command that will be executed by the digital interface. It includes the device address, the register address bits and the command-type bits. The COMMAND byte is typically followed by data bytes clocked on SDI if the command type is a write and on SDO if the command type is a read. The COMMAND byte can also define a Fast command, and in this case, it is not followed by any other byte. The following subsections detail the COMMAND byte structure and all possible commands. During the COMMAND byte clocking on SDI, a STATUS byte is also propagated on the SDO output to enable easy polling of the device status. During this time, the interface is full-duplex, but the part can still be used by MCUs handling only half-duplex communications if the STATUS byte is ignored. 6.2.1 COMMAND BYTE STRUCTURE The COMMAND byte fully defines the command that will be executed by the part. This byte is divided into three parts: the device address bits (CMD[7:6]), the command address bits (CMD[5:2]) and the command-type bits (CMD[1:0]). See Table 6-1. TABLE 6-1: COMMAND BYTE CMD[7] CMD[6] CMD[5] CMD[4] CMD[3] CMD[2] CMD[1] CMD[0] Device Address Bits Register Address/Fast Command Bits Command Type Bits DS20006404C-page 67 MCP3461/2/4R 6.2.2 DEVICE ADDRESS BITS (CMD[7:6]) The SPI interface of the MCP3461/2/4R devices is addressable, which means that multiple devices can communicate on the same SPI bus with only one Chip Select line for all devices. Each device communication starts by a CS falling edge, followed by the clocking of the device address (CMD[7:6]). Each device contains an internal device address which the device can respond to. This address is coded on two bits, so four possible addresses are available. Device address is hard-coded within the device and should be determined when ordering the device. The device address is part of the device markings to avoid potential confusion (see Sections 9.1 “Package Marking Information(1)”). When the CMD[7:6] bits match the device address, the communication will proceed and the part will execute the commands defined in the control byte and its subsequent data bytes. When the CMD[7:6] bits do not correspond to the address hard-coded in the device, the command is ignored. In this case, the SDO output will become high-impedance, which prevents bus contention errors when multiple devices are connected on the same SPI bus (see Figure 6-2). The user has to exit from this communication through a CS rising edge to be able to launch another command. TABLE 6-2: 6.2.3 COMMAND ADDRESS BITS (CMD[5:2]) The COMMAND byte contains four address bits (CMD[5:2]) that can serve two purposes. In case of a register write or read access, they define at which register address the first read/write is performed. In case of a Fast command, they determine which Fast command is executed by the device. In case of a Write command on a read-only register, the command is not executed and the communication should be aborted (CS rising edge) to place another command. All registers can be read; there is no undefined address in the register map. 6.2.4 COMMAND-TYPE BITS (CMD[1:0]) The last two bits of the COMMAND register byte define the command type. These bits are an extension of the typical read/write bits present in most SPI communication protocols. The two bits define four possible command types: Incremental Write, Incremental Read, Static Read and Fast command. Changing the command type within the same communication (while CS is logic low) is not possible. The communication has to be stopped (CS rising edge) and restarted (CS falling edge) to change its command type. The list of possible commands, their type and their possible command addresses are described in Table 6-2. COMMAND TYPES TABLE CMD[5:2] CMD[1:0] Command Description 0xxx 00 Don’t Care 100x 00 Don’t Care 1010 00 ADC Conversion Start/Restart Fast Command (overwrites ADC_MODE[1:0] = 11) 1011 00 ADC Standby Mode Fast Command (overwrites ADC_MODE[1:0] = 10) 1100 00 ADC Shutdown Mode Fast Command (overwrites ADC_MODE[1:0] = 00) 1101 00 Full Shutdown Mode Fast Command (overwrites CONFIG0[7:0] = 0x00 and places the part in Full Shutdown mode) 1110 00 Device Full Reset Fast Command (resets the entire register map to default value) 1111 00 Don’t Care ADDR 01 Static Read of Register Address, ADDR ADDR 10 Incremental Write Starting at Register Address, ADDR ADDR 11 Incremental Read Starting at Register Address, ADDR DS20006404C-page 68  2020-2021 Microchip Technology Inc. MCP3461/2/4R 6.2.5 FAST COMMANDS DESCRIPTION There are five possible Fast commands available for the MCP3461/2/4R devices. For each command, only the COMMAND byte has to be provided on the SPI port and the command is executed right after the COMMAND byte has been clocked. The Fast command codes are detailed in Table 6-2. All undefined command address codes for Fast commands will be ignored and will have no effect. SDO will stay in high-impedance after the COMMAND byte for a Fast command until a CS rising edge is provided. The Fast commands can be enabled or disabled by placing the EN_FASTCMD bit in the IRQ register to ‘1’ (default). Disabling Fast commands can increase the security of the device because it can avoid the execution of unwanted Fast commands, which can be useful in harsh environments. The ADC Start/Restart command (command address: ‘1010’) overwrites the ADC_MODE[1:0] bits to ‘11’, creating a conversion start (or a restart if the conversion was already running). The ADC Standby mode command (command address: ‘1011’) overwrites the ADC_MODE[1:0] bits to ‘10’ and places the ADC in Standby mode. The ADC Shutdown mode command (command address: ‘1100’) overwrites the ADC_MODE[1:0] bits to ‘00’ and places the ADC in ADC Shutdown mode. The Full Shutdown mode command (command address: ‘1101’) overwrites the CONFIG0 register to 0x00 and places the device in Full Shutdown mode (see Section 5.10 “Low-Power Shutdown Modes” for a full description of this mode). The Full Reset command (command address: ‘1110’) resets the device and places the entire register map into its default state condition, including the nonwritable registers. The only difference with a POR event is that the POR_STATUS bit in the IRQ register is set to ‘1’ after a Full Reset and is reset to ‘0’ after a POR event. The user can only clear the ADC Data Output register to its default value by using the Full Reset command. 6.2.6 DEVICE ADDRESS AND STATUS BYTE DURING CONTROL BYTE During the COMMAND byte clocking on the SDI pin, the SDO pin displays a STATUS byte to help the user retrieve quick interrupt status information. The STATUS byte structure is described in Figure 6-1. STAT[7] STAT[6] STAT[5] STAT[4] STAT[3] STAT[2] STAT[1] STAT[0] 0 0 DEV_ADDR [1] DEV_ADDR [0] DEV_ADDR [0] DR_ST ATUS CRCCFG_ ST ATUS POR_ST ATUS Device Address Acknowledge bits FIGURE 6-1: Interrupt Status bits STATUS Byte. The first two bits are always equal to ‘0’ and SDO toggles to ‘0’ as soon as a CS pin falling edge is performed. This allows having an application with multiple devices, with different device addresses, sharing one common SPI bus and avoiding bus contention during STATUS byte clocking. The next three bits of the STATUS byte give a confirmation (Acknowledge) of the hard-coded device address. If the device address of the COMMAND byte and the internal device address of the chip match, these three bits will be transmitted and they are equal to: • STAT[5:4] = DEV_ADDR[1:0] • STAT[3] = DEV_ADDR[0] The STAT[3] bit allows the user to distinguish the SDO output from a High-Impedance state (device address not matched), as the bits, STAT[4] and STAT[3], are complementary and will induce a deterministic toggle on the SDO output. If the two device address bits are not matched with the internally hard-coded device address bits, SDO is maintained in a High-Impedance state during the rest of the communication and the command is ignored. This behavior avoids potential bus contention errors if multiple devices with different device addresses share the same SPI bus. After the transmission of the first two bits, only one device responds to the command (all other devices with non-matching device addresses keep the SDO in high-impedance). In this case, the user needs to abort the communication (CS rising edge) in order to perform another command. The three LSbs of the STATUS byte are the three Interrupt Status bits: • STAT[2] = DR_STATUS (ADC data ready interrupt status) • STAT[1] = CRCCFG_STATUS (CRC checksum error on the register map interrupt status) • STAT[0] = POR_STATUS (POR interrupt status) The STATUS byte allows fast polling of the different interrupts without having to read the IRQ register. However, it requires an MCU that can communicate in Full-Duplex mode (SDI and SDO are clocked at the same time). For MCUs that are only half-duplex, and for devices that do not incorporate a separate IRQ pin, or for applications that do not connect the existing IRQ pin, the polling of the IRQ status can still be done by reading the IRQ register continuously.  2020-2021 Microchip Technology Inc. DS20006404C-page 69 MCP3461/2/4R These three Interrupt Status bits are independent of the two other interrupt mechanisms (IRQ pin and IRQ register) and are cleared each time the STATUS byte is fully clocked. This enables the polling on the STATUS byte as a possible interrupt management solution without requiring to connect the IRQ pin in the system. All Status bit values are latched together just after the device address has been correctly recognized by the chip. Any interrupt happening after the two first Status bits have been clocked out will appear in the STATUS byte of the subsequent communication sequence. Figure 6-2 represents the beginning of each communication with both COMMAND and STATUS bytes depicted. After the STATUS byte is propagated, the SDO pin will be placed in high-impedance for Fast commands or Write commands and will transfer data bytes for Read commands as long as the CS pin stays logic low. Device Latches SDI on Rising Edge CS Device Latches SDO on Falling Edge SPI Mode 1,1 SCK SDO High-Z Device Address does not Match CMD[7:6] CMD[0] CMD[1] CMD[2] CMD[3] Device Address ACK DR_ STATUS 0 CMD[6] Device Address Matches CMD[7:6] CMD[6] High-Z CMD[7] SDO Command Type Register Address CRCREG_ STATUS POR_ STATUS Device Address CMD[4] CMD[5] Don’t Care CMD[6] SDI CMD[7] SPI Mode 0,0 Interrupts Status High-Z 0 FIGURE 6-2: SPI Communication Start (COMMAND Byte on SDI and STATUS Byte on SDO) when the Device Address Matches/Does Not Match CMD[7:6]. DS20006404C-page 70  2020-2021 Microchip Technology Inc. MCP3461/2/4R 6.3 Writing to the Device When the command type is Incremental Write (CMD[1:0] = 10), the device enters Write mode and starts writing the first data byte to the address given in the CMD[5:2] bits. CONFIG0 (0x1) CONFIG1 (0x2) CONFIG2 (0x3) After the STATUS byte has been transferred, SDO stays in a High-Impedance state during an Incremental Write communication. Writing to a read-only address (such as addresses: 0x0 or 0xF) has no effect and does not increment the Address Pointer. The user must stop the communication and restart a communication with a COMMAND byte pointing to a writable address (0x1 to 0xD). CONFIG3 (0x4) IRQ (0x5) MUX (0x6) SCAN (0x7) TIMER (0x8) Each register is effectively written after receiving the last bit for the register (SCK last rising edge). Any CS rising edge during a write communication aborts the current writing. In this case, the register being written will not be updated and will keep its old value. OFFSETCAL (0x9) GAINCAL (0xA) Reserved (0xB) The registers may need 8, 16 or 24 bits to be effectively written, depending on their address (see Table 8-1). After each register is written, the Address Pointer is automatically incremented as long as CS stays logic low. When the Address Pointer reaches 0xD, the next register to be written is the 0x1 register (see Figure 6-3 for a graphical representation of the address looping). Internal registers located at addresses, 0xB, 0xC and 0xE, should be kept to their default state at all times for proper operation. These are reserved registers and should not be modified. Reserved (0xC) LOCK (0xD) Reserved (0xE) FIGURE 6-3: Incremental Write Loop. The Incremental Write feature can be used in order to fully configure the part using a unique communication which can save time in the application. This unique communication can end at address 0xD so that the user can also lock the configuration when written, providing additional security in the application (see Section 6.6 “Locking/Unlocking Register Map Write Access”). Figure 6-4 shows an example of a write communication in detail with a single register write. Figure 6-5 shows an example of an Incremental Write communication.  2020-2021 Microchip Technology Inc. DS20006404C-page 71 MCP3461/2/4R CS Device Latches SDI on Rising Edge DATA DATA DATA DATA DATA DATA DATA DATA DATA DATA DATA DATA DATA DATA DATA DATA DATA DATA 0 POR _ STA TUS DATA 1 C RC R EG_ STA TUS DATA CMD D R_ STA TUS DATA CMD CMD DATA DATA CMD 0 0 0 DATA CMD High-Z CMD SDO CMD Don’t care CMD SDI CMD SCK Don’t care High-Z SPI Mode 0,0; Example with a 24-Bit Wide Register Located at Address CMD CS Device Latches SDI on Rising Edge DATA DATA DATA DATA DATA DATA DATA DATA DATA DATA DATA DATA DATA DATA DATA DATA DATA DATA DATA DATA DATA POR _ STA TUS DATA DATA 0 1 C RC R EG_ STA TUS CMD CMD CMD CMD D R_ STA TUS 0 0 0 CMD High-Z CMD SDO CMD Don’t care CMD SDI CMD SCK DATA Don’t care High-Z A SPI Mode 1,1; Example with a 24-Bit Wide Register Located at Address CMD FIGURE 6-4: Single Register Write Communication (CMD[1:0] = 10) Timing Diagram. CS ADDRESS SET 0x1 Depends on ADDR SCK 8x SDI COMMAND BYTE Depends on ADDR + 1 ... 8x 8x 8x ... 8x ... ADDR Don’t care CMD + ADDR +10 ADDR ADDR + 1 ... ADDR = 0xD ADDR = 0x1 Complete WRITE Sequence ADDR = 0x2 ... Complete WRITE Sequence ADDR = 0xD ... Complete WRITE Sequence 0xD Roll-over SDO Hi-Z 00xxxxxx Hi-Z 0 Depends on IRQ Status and Device Address FIGURE 6-5: DS20006404C-page 72 Multiple Register Write Within One Communication Using Incremental Write Feature.  2020-2021 Microchip Technology Inc. MCP3461/2/4R 6.4 Reading from the Device When the Command bit, CMD[0], is equal to ‘1’, the command is a read communication. After the STATUS byte has been transferred, the first register to be read on the SDO pin is the one with the address defined by the Command Address bits (CMD[5:2]). ADCDATA (0x0) CONFIG0 (0x1) CONFIG1 (0x2) Any CS rising edge during a read communication aborts the current reading. CONFIG2 (0x3) CONFIG3 (0x4) The registers may need 4, 8, 16, 24 or 32 bits to be fully read depending on their address (see Table 8-1). IRQ (0x5) If the CMD[1:0] bits are equal to ‘11’, the command type is Incremental Read. In this case, after each register is read, the Address Pointer is automatically incremented as long as CS stays logic low. The following data bytes are read from the next address sequentially defined in the register map. When the Address Pointer reaches 0xF (last register in the register map for reading), the next register to read is register 0x0 (see Figure 6-6 for a graphical representation of the address looping). MUX (0x6) SCAN (0x7) TIMER (0x8) OFFSETCAL (0x9) GAINCAL (0xA) Reserved (0xB) Reserved (0xC) LOCK (0xD) Reserved (0xE) CRCREG (0xF) FIGURE 6-6:  2020-2021 Microchip Technology Inc. Incremental Read Loop. DS20006404C-page 73 MCP3461/2/4R If the CMD[1:0] bits are equal to ‘01’, the command type is Static Read. In this case, the register address defined in the COMMAND byte is read continuously. The Address Pointer is automatically incremented. Continuously clocking SCK while CS stays logic low will continuously read the same register. Reading another register is only possible by aborting the current communication sequence by raising CS and issuing another command. In both Static and Incremental modes, the registers are updated after each register read is fully performed. If the value of the register changes internally during the read, it will only be updated after the end of the read. The value of each register is latched in the SDO Output Shift register at the first rising edge of SCK of each individual register reading. Figure 6-7 shows the bit by bit details of a single register Read communication. Figure 6-8 shows the examples of Static and Incremental Read communications. CS Device Latches SDI on Rising Edge Device Latches SDO on Falling Edge DATA DATA DATA DATA DATA DATA DATA DATA DATA DATA DATA DATA DATA DATA DATA DATA DATA DATA POR _ STA TUS DATA CMD C RC REG_ STA TUS DATA CMD DR_ STATUS DATA CMD CMD DATA DATA CMD 0 0 0 Don’t Care DATA CMD 1 CMD High-Z CMD SDO Don’t Care CMD SDI CMD SCK Don’t Care High-Z SPI Mode 0,0 ; Example with a 24-Bit Wide Register Located at Address CMD CS Device Latches SDI on Rising Edge Device Latches SDO on Falling Edge 1 DATA DATA DATA DATA DATA DATA DATA DATA DATA DATA DATA DATA DATA DATA DATA DATA DATA DATA DATA DATA DATA DATA A Don’t Care DATA POR _ STA TUS CMD CMD CMD CMD CMD C RC R EG_ STA TUS DR_ ST ATUS CMD 0 0 0 CMD High-Z CMD SDO Don’t Care CMD SDI CMD SCK DATA High-Z SPI Mode 1,1; Example with a 24-Bit Wide Register Located at Address CMD FIGURE 6-7: DS20006404C-page 74 Single Read SPI Communication (Static or Incremental Read).  2020-2021 Microchip Technology Inc. MCP3461/2/4R CS SCK SDI Depends on ADDR 8x Don’t Care Depends on ADDR COMMAND BYTE ... Depends on ADDR ... ADDR Don’t Care CMD[7:6] + ADDR + 01 SDO High-Z 00XXXXXX ADDR Depends on IRQ status and device address Complete READ sequence ADDR 0 Static Read Sequence CS ADDRESS SET 0x0 SCK Depends on ADDR 8x Depends on ADDR+1 ... Depends on Data Format 16x 8x ... 16x ... ADDR SDI Don’t Care COMMAND BYTE Don’t Care ... CMD[7:6] + ADDR + 11 Complete READ sequence 0xF Roll-over SDO High-Z 00XXXXXX ADDR ADDR + 1 ... ADDR = 0xF ADDR = 0x0 ADDR = 0x1 ... ADDR = 0xF 0 Depends on IRQ status and device address Complete READ sequence Complete READ sequence Incremental Read Sequence FIGURE 6-8: Static and Incremental Read SPI Communications.  2020-2021 Microchip Technology Inc. DS20006404C-page 75 MCP3461/2/4R If the COMMAND byte defines a Static Read of the ADCDATA register (address: 0x0), the ADC data will be present on SDO and will be updated continuously at each read. In this case, when a data ready interrupt occurs within a read, the data are not corrupted and will be updated to a new value after the old value has been completely read. The ADC register contains a double buffer that prevents data from being corrupted while reading it. The part is able to stream output data continuously with no additional command if the communication is not stopped with a CS rising edge. Figure 6-9 represents the continuous streaming of incoming ADCDATA through the SPI port with both SPI Modes 0,0 and 1,1. CS The falling edge after Read Start clears the DR interrupt on IRQ pin Device latches SDI on rising edge The falling edge after Read Start clears the DR interrupt on IRQ pin Device latches SDO on falling edge R/W 1 D ATA1 DATA1 D ATA0 DATA1 D ATA0 D ATA0 D ATA0 D ATA0 D ATA0 D ATA0 D ATA0 D ATA0 D ATA0 D ATA0 DATA0 DATA0 DATA0 DATA0 DATA0 DATA0 DATA0 DATA0 DATA0 DATA0 DATA0 DATA0 DATA0 DATA0 DATA0 DATA0 DATA0 DATA0 DATA0 DATA0 DATA0 DATA0 Read Start 1 1 0 CMD CMD Hi-Z 0 0 SDO CMD Read Start DATA1 A 0 A 0 A 0 A 0 A 0 Don’t care CMD A SDI CMD A SCK SDO changes synchronously with the IRQ falling edge (DR interrupt flag) only when MSB is present on SDO IRQ DR Interrupt (DATA1 is ready) SPI Mode 0,0; ADC Data Format: 32-Bit CS The falling edge after Read Start clears the DR interrupt on IRQ pin Device latches SDI on rising edge The falling edge after Read Start clears the DR interrupt on IRQ pin Device latches SDO on falling edge R/W Don’t care 1 IRQ D ATA1 D ATA1 DATA0 D ATA1 DATA0 DATA0 DATA0 DATA0 DATA0 DATA0 DATA0 DATA0 DATA0 D ATA0 D ATA0 D ATA0 D ATA0 D ATA0 D ATA0 D ATA0 D ATA0 D ATA0 D ATA0 D ATA0 D ATA0 D ATA0 D ATA0 D ATA0 D ATA0 D ATA0 D ATA0 D ATA0 D ATA0 D ATA0 Read Start D ATA0 1 1 0 CMD Hi-Z CMD 0 CMD SDO 0 Read Start D ATA1 A 0 A 0 A 0 A 0 A 0 Don’t care CMD A SDI CMD A SCK DR Interrupt (DATA1 is ready) SPI Mode 1,1; ADC Data Format: 32-Bit FIGURE 6-9: DS20006404C-page 76 Continuous ADC Read (Data Streaming) with SPI Mode 0,0 and 1,1.  2020-2021 Microchip Technology Inc. MCP3461/2/4R For continuous reading of ADCDATA in SPI Mode 0,0, once the data have been completely read after a data ready interrupt, the SDO pin takes the MSb value of the previous data at the end of the reading (falling edge of the last SCK clock). If SCK stays Idle at logic low (by definition of Mode 0,0), the SDO pin will be updated at the falling edge of the next data ready pulse (synchronously with the IRQ pin falling edge with an output timing of tDODR) with the new MSb of the data corresponding to the data ready pulse. This mechanism allows the device to continuously read ADC data outputs seamlessly, even in SPI Mode (0,0). In SPI Mode (1,1), the SDO pin stays in the last state (LSb of previous data) after a complete reading, which also allows seamless Continuous Read mode. The ADC output data can only be properly read after a tDODR time, after the data ready interrupt comes on the IRQ pin. The tDODR timing is shorter than the time necessary to input a command on the SDI pin, which ensures proper reading when a new Read command is triggered by the data ready interrupt. In case of continuous reading (with CS pin kept logic low), the tDODR timing must be carefully handled by the MCU, but in general, the interrupt service time is much longer than the tDODR timing. Retrieving a data ready interrupt by reading the STATUS byte or reading the IRQ register automatically ensures that the tDODR timing is respected. 6.5 Securing Read Communications through CRC-16 Checksum Since some applications can generate or receive large EMI/EMC interferences and large transient spikes, it is helpful to secure SPI communications as much as possible, to maintain data integrity and desired configurations during the application’s lifetime. The communication data on the SDO pin can be secured through the insertion of a Cyclic Redundancy Check (CRC) checksum at the end of each read sequence. The CRC checksum on communications can be enabled or disabled through the EN_CRCCOM bit in the CONFIG3 register. The CRC message ensures the integrity of the read sequence bits transmitted on the SDO pin. When enabled, the CRC checksum (CRCCOM[15:0]) is propagated on SDO after each read communication sequence. In case of a Static Read command, the checksum is propagated after each register read. In case of an Incremental Read command, the checksum is propagated after the last register read in the register map (address: 0xF). Figure 6-11 and Figure 6-12 show typical read communications in Static Read and Incremental Read modes, respectively, when the EN_CRCCOM bit is enabled. Since the STATUS byte is propagated on SDO, it is part of the first message, and therefore, it is included in the calculation of the first checksum. For subsequent checksum calculations, the message only contains the registers that are effectively read in between two checksums. The CRC-16 format displayed on the SDO pin depends on the CRC_FORMAT bit in the CONFIG3 register (see Figure 6-10). It can have a 16-bit or 32-bit format to be compatible with both 16-bit and 32-bit MCUs. The CRCCOM[15:0] bits calculated by the device do not depend on the format (the device always calculates a 16-bit only CRC checksum). CRC_FORMAT = 0: 16-Bit (Default) CRCCOM[15:0] CRC_FORMAT = 1: 32-Bit CRCCOM[15:0] FIGURE 6-10: Communications. 0x0000 CRC Format Table for Read The CRC calculation computed by the device is fully compatible with the CRC hardware contained in the Direct Memory Access (DMA) of the PIC24 and PIC32 MCU product lines. The CRC message that should be considered in the PIC® device DMA is the concatenation of the read sequence and its associated checksum. When the DMA CRC hardware computes this extended message, the resulted checksum should be 0x0000. Any other result indicates that a miscommunication has occurred and that the current communication sequence should be stopped and restarted. The CRC checksum in the MCP3461/2/4R devices uses the 16-bit CRC-16 ANSI polynomial as defined in the IEEE 802.3 Standard: x16 + x15 + x2 + 1. This polynomial can also be noted as 0x8005. CRC-16 detects all single and double-bit errors, all errors with an odd number of bits, all burst errors of 16 bits in length or less and most errors for longer bursts. This allows an excellent coverage of the SPI communication errors that can occur in the system, and heavily reduces the risk of a miscommunication, even under noisy environments.  2020-2021 Microchip Technology Inc. DS20006404C-page 77 MCP3461/2/4R CS SCK Depends on ADDR 8x 16x or 32x Depending on CRC format Depends on ADDR 16x or 32x Depending on CRC format ... ADDRESS SET ADDR Roll-over SDI Don’t Care COMMAND BYTE Don’t Care CRC Checksum CMD[7:6] + ADDR + 01 SDO High-Z 0 STATUS BYTE ADDR Complete READ sequence including STATUS Byte = First Message for CRC Calculation FIGURE 6-11: CRC Checksum ADDR CRC Checksum First checksum New message New checksum ... SPI Static Read with Communication CRC Enabled. CS ADDRESS SET 0x0 SCK 8x Depends on ADDR Depending on ADDR+1 ... 16x 16x or 32x Depending on CRC format Depends on Data Format 8x ... 24x 16x or 32x Depending on CRC format ... ADDR SDI Don’t Care COMMAND BYTE Don’t Care ... CMD[7:6] + ADDR + 11 Complete READ sequence 0xF Roll-over SDO High-Z 0 STATUS BYTE ADDR ADDR + 1 ... Complete READ sequence including STATUS Byte = First Message for CRC Calculation FIGURE 6-12: DS20006404C-page 78 ADDR = 0xF CRC Checksum ADDR = 0x0 First Checksum ADDR = 0x1 New Message ... ADDR = 0xF CRC Checksum CRC Checksum (not part of register map) New Checksum SPI Incremental Read with Communication CRC Enabled.  2020-2021 Microchip Technology Inc. MCP3461/2/4R 6.6 Locking/Unlocking Register Map Write Access The MCP3461/2/4R digital interface includes an advanced security feature that allows locking or unlocking the register map write access. This feature prevents the miscommunication that can corrupt the desired configuration of the device, especially an SPI read becoming an SPI write because of the noisy environment. The last register address of the incremental write loop (0xD: LOCK) contains the LOCK[7:0] bits. If these bits are equal to the password value (0xA5), the register map write access is not locked. Any write can take place and the communications are not protected. The devices are, by default after POR, in an unlocked state (LOCK[7:0] = 0xA5). When the LOCK[7:0] bits are not equal to 0xA5, the register map write access is locked. The register map, and therefore, the full device configuration is writeprotected. Any write to an address other than 0xD will yield no result. All the register addresses, except the address 0xD, become read-only. In this case, if the user wants to change the configuration, the LOCK[7:0] bits have to be reprogrammed back to 0xA5 before sending the desired Write command. The LOCK[7:0] bits are located in the last register of the Incremental Write address loop, so the user can program the entire register map, starting from 0x1 to 0xD, within one continuous write sequence and then lock the configuration at the end of the sequence by writing all zeros (for example) in the 0xD address. 6.7 Detecting a Configuration Change through CRC-16 Checksum on the Register Map and its Associated Interrupt Flag In order to prevent internal corruption and to provide additional security on the register map configuration, the MCP3461/2/4R devices include an automatic and continuous CRC checksum calculation on the full register map Configuration bits. This calculation is not the same as the communication CRC checksum described in Section 6.5 “Securing Read Communications through CRC-16 Checksum”. This calculation takes the contents of the register map, from addresses 0x1 to 0xF, and produces a checksum which is held in the CRCCFG[15:0] bits located in the CRCCFG register (address: 0xF). The CRC checksum for the register map uses the 16-bit CRC-16 ANSI polynomial as defined in the IEEE 802.3 Standard: x16 + x15 + x2 + 1.  2020-2021 Microchip Technology Inc. Since this feature is intended to protect the configuration of the device, this calculation is run continuously only when the register map is locked (LOCK[7:0]), which is different than 0xA5 (see Section 6.6 “Locking/Unlocking Register Map Write Access”). If the register map is unlocked (for example, after POR), the CRCCFG[15:0] bits are cleared and no CRC is calculated. The DR_STATUS, CRCCFG_STATUS and POR_STATUS bits are set to ‘1’ (default) and the CRCCFG[15:0] bits are set to ‘0’ (default) for this calculation, as they could vary and lead to unwanted CRC errors. After the DR_STATUS, CRCCFG_STATUS and POR_STATUS bits are cleared (with a read on the IRQ register), the CRC checksum on the register map can be verified by reading all registers in an Incremental Read sequence and by using the CRC communication. At the second incremental read loop, the checksum provided by the CRC communication must be equal to all zeros if the checksum on the register map is correct. The checksum will be calculated for the first time in 11 DMCLK periods. This first value will then be the reference checksum value and will be latched internally until an unlocking of the register map occurs. The checksum will then be calculated continuously every 11 DMCLK periods and checked against the reference checksum. If the checksum is different than the reference, an interrupt flag will be generated on the CRCCFG_STATUS bit within the STATUS byte on SDO, on the CRCCFG_STATUS bit in the IRQ register and on the IRQ output pin. The interrupt flag is maintained on all three mechanisms until the register map write access is unlocked. When the part write access is unlocked, the interrupt on the IRQ pin clears immediately and the two other interrupt mechanisms are cleared when the interrupt is read (read STATUS byte or read IRQ register). The CRC interrupt can occur even if the IRQ pin is configured as the MDAT modulator output. In this case, the interrupt stays present and forces a logic low output on this pin as long as the LOCK[7:0] register is locked (LOCK[7:0] 0xA5). At power-up, the interrupt is not present and the register map is unlocked. As soon as the user finishes writing its configuration, the user needs to lock the register map (for example, by writing 0x00 in the LOCK bits) to be able to use the interrupt flag and to calculate the checksum of the register map. DS20006404C-page 79 MCP3461/2/4R 6.8 Interrupts Description The MCP3461/2/4R devices incorporate multiple interrupt mechanisms to be able to synchronize the device with an MCU and to warn against external perturbations. There are four events that can generate interrupt flags: • • • • Additionally, there are three independent interrupt mechanisms that allow the devices to be implemented in many different applications and configurations. A summary of the different mechanisms is available in Table 6-3. Conversion Start Data Ready POR CRC Error on the Register Map Configuration TABLE 6-3: INTERRUPT DESCRIPTION SUMMARY TABLE Interrupt Flag Type Description Clearing Procedure STATUS Byte Three Status bits (DR_STATUS, CRCCFG_STATUS, POR_STATUS) are latched together after device address detection and clocked out during each command on the SDO STATUS byte. IRQ Register Status Bits IRQ register Status bits can be read when Cleared when the IRQ register reading is reading the address 0x5 (IRQ register). finished (on the last SCK falling edge). The IRQ latching occurs at the beginning of the IRQ register reading. IRQ Pin State • When IRQ_MODE[1] = 0, the IRQ pin can be asserted to logic low by any of the interrupts. • When IRQ_MODE[1] = 1, only POR and CRC interrupts can assert the IRQ pin to logic low. DS20006404C-page 80 Cleared when STATUS byte clocking is finished (on the last SCK falling edge). • Conversion start interrupt is automatically cleared at the beginning of a new conversion cycle after a TSTP timing. • DR interrupt is cleared by the first SCK falling edge of an ADC read, or automatically 16 DMCLKs before a new data ready in Continuous Conversion mode or in Scan mode. • POR interrupt is cleared on the first CS falling edge when both AVDD and DVDD monitoring circuits detect that their power supply is over their respective thresholds. • CRCCFG interrupt is cleared when the device is unlocked (writing 0xA5 to LOCK register) or when a Fast command ADC start/restart conversion is performed.  2020-2021 Microchip Technology Inc. MCP3461/2/4R 6.8.1 CONVERSION DATA READY INTERRUPT 3. The data ready interrupt happens when a new conversion is ready to be read on the ADCDATA register. This event happens synchronously with DMCLK and at each end of conversion. This interrupt is implemented with three different and independent mechanisms: STATUS byte on SDO, IRQ register Status bit and IRQ pin state. 1. 2. STATUS byte on SDO. When the interrupt occurs on the next STATUS byte transmitted on SDO, the DR_STATUS bit will be logic low. Once the STATUS byte has been transmitted, the DR_STATUS bit appears as ‘1’ until a new interrupt is present. If the interrupt occurs between two STATUS byte transmissions, the DR_STATUS bit on SDO will appear as equal to ‘0’ on the second reading. IRQ register Status bit. When the interrupt occurs, the DR_STATUS bit in the IRQ register is set to ‘0’. Once the IRQ register has been fully read, this DR_STATUS bit is reset to ‘1’. If the interrupt occurs between two readings of the IRQ register, the IRQ register Status bit appears as equal to ‘0’ on the second reading. IRQ pin state. The interrupt generates an IRQ pin falling edge (transition to logic low) as soon as it happens. The data ready interrupt is cleared by the first of the following two events: • First falling edge of SCK during an ADC Output Data register read • 16 DMCLK clock periods before current conversion ends If the user does not read the ADCDATA register in time in Continuous Conversion mode or in Scan mode, the IRQ pin will automatically reset to its Inactive state 16 DMCLKs prior to the new data ready interrupt. This feature is designed in order to avoid the case where the IRQ pin is logic low if the reading of ADC data is not performed. The user can then determine exactly when to expect the new data and can respect the tDODR timing in all cases to ensure a proper reading of the ADC data. See Figure 6-13 for more details. Transition time tDOD R DATA1 can be read during this time SPI ADCDATA REGISTER C OMM AN D By te R ea d A DC D ATA1 R ea d A DC D ATA DATA0 C OMM AN D By te R ea d A DC D ATA2 R ea d A DC D ATA DATA2 DATA1 TCON V 1/DRCLK 1/DRCLK TDRH TDRH IRQ Data Ready Interrupt Interrupt is cleared at first SCK falling edge after ADCDATA read start FIGURE 6-13: Transition time tDOD R DATA2 can be read during this time Interrupt is cleared automatically if ADCDATA has not been read in time Data Ready Interrupt IRQ Pin Timing Diagram.  2020-2021 Microchip Technology Inc. DS20006404C-page 81 MCP3461/2/4R 6.8.2 CONVERSION CYCLE START INTERRUPT This interrupt is the only selectable one and the only one not present in the STATUS byte on the SDO and IRQ registers. It is only available on the IRQ pin. The user can enable or disable this output by using: • [EN_STP] = 1: The conversion start interrupt output is enabled (default). • [EN_STP] = 0: The conversion start interrupt output is disabled. ADC_MODE ADC STATUS This interrupt marks the beginning of a conversion cycle. In case of a One-Shot mode or Continuous mode conversion in MUX mode, it marks the start of the sampling in the first conversion (after the ADC start-up delay of 256 DMCLK periods). In case of a Scan mode, it marks the start of the sampling in the first conversion of the first Scan mode cycle. The host MCU can utilize this interrupt to synchronize the start of the ADC conversion and manage synchronous events together with the conversion process (see Figure 6-14 for more details). 00 11 Sh u td o wn Sta rt-u p 1 st C o nv ers io n i n e ithe r MU X o r SC AN mo de TA DC_ SET UP TCON V TST P IRQ Conversion Start IRQ (EN_STP = 1) FIGURE 6-14: Conversion Start IRQ Timing Diagram. This interrupt output generates a falling edge on the IRQ pin and is automatically cleared after a short period of time, TSTP. 6.8.3 POR INTERRUPT The POR interrupt informs the user if a POR event has happened or if the part is in a POR state when the IRQ pin is used. This interrupt is implemented with three different and independent mechanisms: STATUS byte on SDO, IRQ register Status bit and IRQ pin state. 6.8.3.1 STATUS Byte on SDO When the device has just powered up, on the first STATUS byte transmitted on SDO (first communication), the POR_STATUS bit is logic low. Once the STATUS byte has been transmitted, the POR_STATUS bit appears as ‘1’ until the part is powered down. If a POR event occurs between two STATUS byte transmissions, and if the part is properly repowered up, the POR_STATUS bit on SDO will appear as equal to ‘0’ on the latter reading. This mechanism can only work when the power supplies are back above the POR thresholds on the analog and digital cores, as retrieving data from the SPI port is not possible when the device is in a POR state. DS20006404C-page 82 Data Ready IRQ 6.8.3.2 IRQ Register Status Bit When the device has just powered up, the POR_STATUS bit in the IRQ register is set to ‘0’. Once the IRQ register has been fully read, this POR_STATUS bit is once again reset to ‘1’. If a POR event occurs between two readings of the IRQ register, the IRQ register Status bit will appear as equal to ‘0’ on the second reading. This mechanism can only work when the power supplies are back above the POR thresholds on the analog and digital cores. 6.8.3.3 IRQ Pin State A Logic Low state is generated on the IRQ pin as soon as the AVDD or DVDD monitoring circuits detect a power supply drop below their specified threshold. This POR interrupt can only be cleared when both AVDD and DVDD are above their monitoring voltage thresholds. When this condition is met, the POR threshold is cleared by the CS falling edge. Therefore, it means that if a CS falling edge does not clear the IRQ pin state, the POR event is still in effect.  2020-2021 Microchip Technology Inc. MCP3461/2/4R This feature helps the user to know exactly when the chip has powered up by polling with the CS pin and checking the IRQ pin state at power-up (see Figure 6-15 for more details). DVDD AVDD Since this is a high-level priority interrupt, the POR interrupt can happen at all times, even when MDAT is enabled. In this case, having a constant logic low bitstream can indicate a probable POR event (or a fully negative ADC saturation output code induced by a large negative input voltage). VPOR_A, V POR_D tPOR POR Internal State High-Z IRQ 0 tC SIRQ CS Don’t Care Chip Select Starts Low Clears POR interrupt FIGURE 6-15: 6.8.4 POR IRQ Timing Diagram. CRCCFG ERROR INTERRUPT The CRCCFG interrupt happens when an error in the CRC-16 checksum has been detected in the register map CRC calculation. This interrupt is implemented with three different and independent mechanisms: STATUS byte on SDO, IRQ register Status bit and IRQ pin state. 6.8.4.1 STATUS Byte on SDO In case of a CRCCFG error on the next STATUS byte transmitted on SDO, the CRCCFG_STATUS bit is logic low. Once the STATUS byte has been transmitted, the CRCCFG_STATUS bit appears as ‘1’ until a new interrupt occurs. If the error is detected again between two STATUS byte transmissions, the CRCCFG_STATUS bit on SDO will appear as equal to ‘0’ on the second reading. 6.8.4.2 IRQ Register Status Bit In case of a CRCCFG error, the CRCCFG_STATUS bit in the IRQ register is set to ‘0’. Once the IRQ register is fully read, the CRCCFG_STATUS bit is reset to ‘1’. If the CRCCFG error happens again between two readings of the IRQ register, the IRQ register Status bit will appear as ‘0’ on the second reading.  2020-2021 Microchip Technology Inc. 6.8.4.3 IRQ Pin State The CRCCFG error generates a Logic Low state on the IRQ pin until it is cleared. The clearing of the CRCCFG error can only be made by “unlocking” the device (write 0xA5 in the LOCK[7:0] register) or by sending a Fast command start/restart ADC conversion. Unlocking the device stops the CRC calculation, and therefore, clears the associated interrupt. Sending an ADC start/restart conversion Fast command resets the CRC calculation and clears the interrupt. This CRCCFG error can only occur in case of an external perturbation (for example, EMI induced) that causes the continuous calculation of the CRC on the register map to be erroneous or in case the chip integrity has been altered. Since both causes are high-priority issues, the CRCCFG error has priority over all other interrupts (except POR) and over the MDAT output on the IRQ pin. Note: If MCLK starts running before the device is locked, an interrupt can momentarily occur, even if registers have not been corrupted. In such a case, the user must send a start/restart conversion Fast command, which will clear the unwanted interrupt and correctly restart the CRC calculations. DS20006404C-page 83 MCP3461/2/4R NOTES: DS20006404C-page 84  2020-2021 Microchip Technology Inc. MCP3461/2/4R 7.0 BASIC APPLICATION CONFIGURATION 7.1 The MCP3461/2/4R devices can be used for various precision Analog-to-Digital Converter applications. The flexibility of its usage is given by the possibility of configuring the ADC to fit the required application. R12 100 5% 0603 CH0 CH1 1 2 J1 Typical Application for Absolute Voltage Measurement The MCP3461/2/4R devices are able to measure the signal provided by sensors with absolute voltage output. For such applications, the MCP3461/2/4R family typically uses its internal voltage reference. For the best performance, an external capacitor is recommended on the REFIN+/OUT pin for noise filtering and to provide more stability for the internal voltage reference (See Section 3.1 “Differential Reference Voltage Inputs: REFIN+/OUT, REFIN-”). Anti-Aliasing Filters C6 0.1 μF 16V 0603 GNDA C9 R6 100 0603 R5 5% 0603 5% CH2 CH3 100 100 R7 0603 5% 1 2 J5 CH4 CH5 100 0603 5% IRQ Pull-up 0603 5% R9 5% 100 0603 C11 0.1 μF GNDA 16V C2 19 0.1 μF 16V 0603 16V 3 GNDA 4 0.1 μF 16V 0603 100 5% 5 6 7 C7 C8 R11 0603 C12 0.1 μF 0.1 μF 16V 0603 1 2 J7 CH6 CH7 100 R17 0.1 μF 16V 0603 C5 R10 3.3D 10R 5% 0603 C3 C4 R8 ADC 3.3A R14 0.1 μF 16V 0603 1 2 J3 0.1 μF 16V 0603 8 9 GNDA 10 0.1 μF 16V 0603 0603 GNDA AVDD 20 3.3D 16V 0603 C14 0.1 μF GND 16V 0603 DVDD R22 10k 5% 0603 18 RA14/ADC_IRQ CH0 CH1 CH2 CH3 CH4 CH5 CH6 16 MCLK 15 IRQ/MDAT 0603 R18 0603 R19 13 0603 R21 SDI 14 R16 10R5% SDO 12 0603 R20 SCK 11 R15 10R CS 5% 0603 10R 5% 10R 5% 10R 5% 10R 5% 0603 RD3/ADC_CLKIN RA14/ADC_IRQ RG8/ADC_MOSI2 RG7/ADC_MISO2 RG6/ADC_SCK2 RG9/ADC_CS2 CH7 2 REFIN+/OUT 1 REFIN- 0603 C13 0.1 μF 10R 5% 0603 AGND EP DGND 21 17 GNDA GND MCP3464R GNDA C10 10uF 10V 0603 GNDA FIGURE 7-1: MCP3464R Application Example.  2020-2021 Microchip Technology Inc. DS20006404C-page 85 MCP3461/2/4R The ADC can be used in Differential or Single-Ended mode due to the internal dual multiplexer (Figure 5-1). The user can select the input connection settings from the MUX register (Section 8.7 “Multiplexer (MUX) Register”) by using the different settings available on the positive and negative inputs of the ADC. The single-ended configuration is achieved by selecting AGND for the VIN- input of the ADC (MUX[3:0] = 1000) or by selecting any CHn input channel for VIN- and connecting the corresponding CHn input channel to AGND. The connection of the thermocouple to the ADC requires minimal extra components. A differential input structure is recommended. The cold junction can be measured by using a digital temperature sensor, such as MCP9804, connected to the MCU. If high accuracy is not required, the cold junction temperature can be estimated directly with the internal temperature sensor of the ADC (see Figure 7-2). 7.1.1 A wide range of sensors provides an output voltage directly related to the power supply of the sensors. These sensors are known as ratiometric output. These sensors often have a Wheatstone bridge structure, such as pressure sensors or load cells (Figure 7-3). HIGH-SIDE AND LOW-SIDE CURRENT SENSING The ADC has the ability to perform differential measurements with an analog input Common-mode equal to or slightly larger than AVDD, or equal to or slightly lower than AGND (see the Electrical Characteristics table). A differential input structure and a Kelvin connection are required in order to achieve the most accurate measurements. An anti-aliasing filter is required to avoid aliasing of the oversampling frequency (DMCLK) back into the baseband of the input signal and possible corruption of the output data. Figure 7-1 provides an example of an anti-aliasing filter. For the measurement of voltages that can reach AVDD or a few mV higher, a gain setting of 0.33x is useful since it increases the input range to a 3 x VREF value, so a 1.2V VREF will allow a theoretical input range of 3.6V. However, the maximum voltage that can be measured is always bounded by AVDD + 0.1V in order to limit excess leakage current at the input pins created by the ESD structures. Therefore, in order to properly measure 3.6V with a 1.2V voltage reference, it is recommended to use an AVDD supply voltage as close as possible to 3.6V. 7.1.2 THERMOCOUPLE CONNECTION One of the most used temperature transducers in the industry is the thermocouple. Thermocouples provide a voltage dependent on the temperature difference between cold junction and hot junction. This voltage is in the order of magnitude of tens of µV/°C, which requires amplification that can be provided by the internal gain stage of the ADC. 7.2 Typical Application for Ratiometric Voltage Measurement R1 RTD VIN+ Input Signal MCP3461R VIN- Others act as a single resistor with a value dependent on temperature (pure metal resistance thermometer RTD and negative temperature coefficient resistor NTC). To accurately measure the signal from these sensors, REFIN+/OUT is usually connected to the same power supply of the sensor (Figure 7-4), as long as this respects the specified voltage range on the REFIN+/OUT pin (see the Electrical Characteristics table. R2 Sensor VIN+ Anti-aliasing Filter REFIN+/OUT MCP3461R VIN- REFIN- R1 FIGURE 7-4: DS20006404C-page 86 REFIN- FIGURE 7-3: Wheatstone Bridge Ratiometric Connection. C1 FIGURE 7-2: to MCP3461R. REFIN+/OUT C2 AGND DGND RTD Ratiometric Connection. Thermocouple Connection  2020-2021 Microchip Technology Inc. MCP3461/2/4R 7.3 Power Supply Design and Bypassing Another possibility, sometimes easier to implement in terms of PCB layout, is to consider the MCP3461/2/4R as an analog component, and therefore, connect AVDD to DVDD and AGND to DGND with a star connection. In this scheme, the decoupling capacitors may be larger, due to the ripple on the digital power supply (caused by the digital filters and the SPI interface of the MCP3461/2/4R) now causing glitches on the analog power supply. In any system, the analog ICs (such as references or operational amplifiers) are always connected to the analog ground plane. The MCP3461/2/4R devices should also be considered sensitive analog components and connected to the analog ground plane. The ADC features two pairs of power supply voltage pins: AGND and AVDD, DGND and DVDD. For best performance, it is recommended to keep the two pairs of pins connected to two different networks (see Figure 7-5), so that the design will feature two ground traces and two power supplies (see Figure 7-6). Figure 7-6 shows an example of a power supply schematic with separate DVDD and AVDD. A high-current LDO (MCP1825) was used for the DVDD line to be able to power the MCU and other peripherals attached to the MCU. A high PSRR LDO (MCP1754) is used for the AVDD that goes to the ADC and a few other components sensitive to noise. The Net tie is used to separate DGND from AGND. The analog circuitry (including MCP3461/2/4R) and the digital circuitry (MCU) should have separate power supplies and return paths to the external ground reference, as described in Figure 7-5. An example of a typical power supply circuit, with different paths for analog and digital return currents, is shown in Figure 7-6. A possible split example is shown in Figure 7-7, where the ground star connection can be located underneath the device with the exposed pad. The split between analog and digital can be done under the device, and AVDD and DVDD can be connected with lines coming under the ground plane. The two separate return paths will eventually share a unique connection point (star connection) in order to minimize coupling between the two power supply domains. ID IA 0.1 ȝF C 0.1 ȝF VA AV DD DVDD VD MCP365 MCU DGND AGND IA ID “Star” Point D-= A-= FIGURE 7-5: Separating Digital and Analog Ground by Using a Star Connection. U2 MCP1825S-3.3V VIN VOUT 3 C44 10 μF 5V_USB C15 10 μF TANT-B GND VOUT GND TANT-B GND GND 2 +5V USB +9V IN 1 U3 MCP1754-3.3V VIN VOUT 3 3.3A 2 MRA4005 VIN 3 1 4 2 3 GND D1 C45 10 μF J9 1 1 3 2 Power Jack 2.5 mm U4 LM1117-5V GND 9V J10 C10 0.1 μF TANT-B 0603 GND GND 3.3D C11 0.1 μF 0603 2 1 GND 5V C14 0.1 μF 0603 GND GND Net Tie GND GNDA GNDA C12 0.1 μF 0603 GNDA GNDA C13 10 μF TANT-B GNDA FIGURE 7-6: Power Supply with Separate Lines for Analog and Digital Sections (the “Net Tie” Object Represents the Star Ground Connection).  2020-2021 Microchip Technology Inc. DS20006404C-page 87 MCP3461/2/4R 7.4 SPI Interface Digital Crosstalk The MCP3461/2/4R devices incorporate a high-speed 20 MHz SPI digital interface. This interface can induce crosstalk, especially with the outer channels closer to the SPI digital pins (for example, CH7), if it is run at full speed without any precautions. The crosstalk is caused by the switching noise created by the digital SPI signals. This crosstalk would negatively impact the SNR in this case. The noise is attenuated if proper separation between the analog and the digital power supplies is put in place (see Sections 7.3 “Power Supply Design and Bypassing”). FIGURE 7-7: Separation of Analog and Digital Circuits on the Layout (Shown on the UQFN Package). When remote sensors are used to reduce the sensitivity to external influences, such as EMI, the wires that connect the sensor to the ADC should form a twisted pair. Ferrite beads can be used between the digital and analog ground planes to keep high-frequency noise from entering the device. A low-resistance ferrite bead is recommended. DS20006404C-page 88 In order to further remove the influence of the SPI communication on measurement accuracy, it is recommended to add series resistors on the SPI lines to reduce the current spikes caused by the digital switching noise (see Figure 7-1 where these resistors have been implemented). The resistors also help to keep the level of electromagnetic emissions low. The switching noise is also a linear function of the DVDD supply voltage. In order to further reduce the influence of the switching noise caused by SPI transmissions, the DVDD digital power supply voltage should be kept as low a value as possible. The measurement graphs provided in this “MCP3461/2/4R Data Sheet” have been performed with 10 series resistors connected on each SPI I/O pin. Measurement accuracy disturbances have not been observed, even at 20 MHz interfacing.  2020-2021 Microchip Technology Inc. MCP3461/2/4R 8.0 INTERNAL REGISTERS The MCP3461/2/4R devices have a total of 16 internal registers made of volatile memory. Table 8-1 includes a summary of the registers. These registers are sequentially accessible. TABLE 8-1: INTERNAL REGISTERS SUMMARY Address Register Name No. of Bits R/W Description Latest A/D conversion data output value (16 or 32 bits depending on DATA_FORMAT[1:0]) or modulator output stream (4-bit wide) in MDAT Output mode 0x0 ADCDATA 4/16/32 R 0x1 CONFIG0 8 R/W 0x2 CONFIG1 8 R/W Prescale and OSR settings 0x3 CONFIG2 8 R/W ADC boost and gain settings, auto-zeroing settings for analog multiplexer, voltage reference and ADC 0x4 CONFIG3 8 R/W Conversion mode, data and CRC format settings; enable for CRC on communications, enable for digital offset and gain error calibrations 0x5 IRQ 8 R/W IRQ Status bits and IRQ mode settings; enable for Fast commands and for conversion start pulse ADC Operating mode, Master Clock mode and Input Bias Current Source mode 0x6 MUX 8 R/W Analog multiplexer input selection (MUX mode only) 0x7 SCAN 24 R/W Scan mode settings 0x8 TIMER 24 R/W Delay value for TIMER between Scan cycles 0x9 OFFSETCAL 24 R/W ADC digital offset calibration value ADC digital gain calibration value 0xA GAINCAL 24 R/W 0xB RESERVED 24 R/W 0xC RESERVED 8 R/W 0xD LOCK 8 R/W 0xE RESERVED 16 R/W 0xF CRCCFG 16 R  2020-2021 Microchip Technology Inc. Password value for SPI Write mode locking CRC checksum for device configuration DS20006404C-page 89 MCP3461/2/4R 8.1 ADCDATA REGISTER Name Bits Address Cof ADCDATA 4/16/32 0x0 R REGISTER 8-1: ADCDATA: ADC CHANNEL DATA OUTPUT REGISTER R-0 ADCDATA[15:0] bit 15 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-0 x = Bit is unknown ADCDATA[15:0]: ADC Output Code The data are post-calibration if the EN_OFFCAL or EN_GAINCAL bits are enabled. The data can be formatted in 16/32-bit modes depending on the DATA_FORMAT[1:0] bits setting (see Section 5.6 “ADC Output Data Format”). The ADC Channel Data Output registers always contain the most recent A/D conversion data. The register is updated at each data ready internal signal (it depends on the OSR and CONV_MODE settings). The register is latched at the start of each SPI Read command. The register is double buffered to avoid data loss. There is a small time delay, tDODR, after each data ready, where the user has to wait for the data to be available. Otherwise, data corruption can occur (when the internal data are refreshed). When IRQ_MODE[1:0] = 1x, this register becomes a 4-bit wide register containing the MDAT output codes, which are the outputs of the modulator that are represented by four comparator outputs (COMP[3:0], see Section 5.4.2 “Modulator Output Block”). DS20006404C-page 90  2020-2021 Microchip Technology Inc. MCP3461/2/4R 8.2 CONFIG0 REGISTER Name Bits Address Cof CONFIG0 8 0x1 R/W REGISTER 8-2: CONFIG0 REGISTER R/W-1 R/W-1 VREF_SEL CONFIG0[6] R/W-0 R/W-0 R/W-0 CLK_SEL[1:0] R/W-0 R/W-0 CS_SEL[1:0] R/W-0 ADC_MODE[1:0] bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 VREF_SEL: Internal Voltage Reference 1 = Internal voltage reference is selected and buffered internally; REFIN+/OUT pin voltage is set at 2.4V (default) 0 = External voltage reference is selected and not buffered internally; the internal voltage reference buffer is shut down bit 6 CONFIG0[6]: If CONFIG0 = 0x0, the device goes into Partial Shutdown mode. This bit does not have any other function. bit 5-4 CLK_SEL[1:0]: Clock Selection 11 = Internal clock is selected and AMCLK is present on the analog master clock output pin 10 = Internal clock is selected and no clock output is present on the CLK pin 01 = External digital clock 00 = External digital clock (default) bit 3-2 CS_SEL[1:0]: Current Source/Sink Selection Bits for Sensor Bias (source on VIN+/sink on VIN-) 11 = 15 µA is applied to the ADC inputs 10 = 3.7 µA is applied to the ADC inputs 01 = 0.9 µA is applied to the ADC inputs 00 = No current source is applied to the ADC inputs (default) bit 1-0 ADC_MODE[1:0]: ADC Operating Mode Selection 11 = ADC Conversion mode 10 = ADC Standby mode 01 = ADC Shutdown mode 00 = ADC Shutdown mode (default)  2020-2021 Microchip Technology Inc. DS20006404C-page 91 MCP3461/2/4R 8.3 CONFIG1 REGISTER Name Bits Address Cof CONFIG1 8 0x2 R/W REGISTER 8-3: R/W-0 CONFIG1: CONFIGURATION REGISTER 1 R/W-0 R/W-0 PRE[1:0] R/W-0 R/W-1 R/W-1 R/W-0 OSR[3:0] R/W-0 RESERVED[1:0] bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 PRE[1:0]: Prescaler Value Selection for AMCLK 11 = AMCLK = MCLK/8 10 = AMCLK = MCLK/4 01 = AMCLK = MCLK/2 00 = AMCLK = MCLK (default) bit 5-2 OSR[3:0]: Oversampling Ratio for Delta-Sigma A/D Conversion 1111 = OSR: 98304 1110 = OSR: 81920 1101 = OSR: 49152 1100 = OSR: 40960 1011 = OSR: 24576 1010 = OSR: 20480 1001 = OSR: 16384 1000 = OSR: 8192 0111 = OSR: 4096 0110 = OSR: 2048 0101 = OSR: 1024 0100 = OSR: 512 0011 = OSR: 256 (default) 0010 = OSR: 128 0001 = OSR: 64 0000 = OSR: 32 bit 1-0 RESERVED[1:0]: Should always be set to ‘00’ DS20006404C-page 92 x = Bit is unknown  2020-2021 Microchip Technology Inc. MCP3461/2/4R 8.4 CONFIG2 REGISTER Name Bits Address Cof CONFIG2 8 0x3 R/W REGISTER 8-4: R/W-1 CONFIG2: CONFIGURATION REGISTER 2 R/W-0 R/W-0 BOOST[1:0] R/W-0 GAIN[2:0] R/W-1 R/W-0 R/W-1 R/W-1 AZ_MUX AZ_REF RESERVED bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-6 BOOST[1:0]: ADC Bias Current Selection 11 = ADC channel has current x 2 10 = ADC channel has current x 1 (default) 01 = ADC channel has current x 0.66 00 = ADC channel has current x 0.5 bit 5-3 GAIN[2:0]: ADC Gain Selection 111 = Gain is x64 (x16 analog, x4 digital) 110 = Gain is x32 (x16 analog, x2 digital) 101 = Gain is x16 100 = Gain is x8 011 = Gain is x4 010 = Gain is x2 001 = Gain is x1 (default) 000 = Gain is x1/3 bit 2 AZ_MUX: Auto-Zeroing MUX Setting 1 = ADC auto-zeroing algorithm is enabled; this setting multiplies the conversion time by two and does not allow Continuous Conversion mode operation (which is then replaced by a series of consecutive One-Shot mode conversions) 0 = Analog input multiplexer auto-zeroing algorithm is disabled (default). bit 1 AZ_REF: Auto-Zeroing Reference Buffer Setting 1 = Internal voltage reference buffer chopping algorithm is enabled; this setting has no effect when external voltage reference is selected (VREF_SEL = 0) (default) 0 = Internal voltage reference buffer chopping auto-zeroing algorithm is disabled bit 0 RESERVED: Should always be equal to ‘1’  2020-2021 Microchip Technology Inc. DS20006404C-page 93 MCP3461/2/4R 8.5 CONFIG3 REGISTER Name Bits Address Cof CONFIG3 8 0x4 R/W REGISTER 8-5: R/W-0 R/W-0 CONV_MODE[1:0] CONFIG3: CONFIGURATION REGISTER 3 R/W-0 R/W-0 DATA_FORMAT[1:0] R/W-0 R/W-0 R/W-0 R/W-0 CRC_FORMAT EN_CRCCOM EN_OFFCAL EN_GAINCAL bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-6 CONV_MODE[1:0]: Conversion Mode Selection 11 = Continuous Conversion mode or continuous conversion cycle in Scan mode 10 = One-shot conversion or one-shot cycle in Scan mode; it sets ADC_MODE[1:0] to ‘10’ (standby) at the end of the conversion or at the end of the conversion cycle in Scan mode 0x = One-shot conversion or one-shot cycle in Scan mode’ it sets ADC_MODE[1:0] to ‘0x’ (ADC shutdown) at the end of the conversion or at the end of the conversion cycle in Scan mode (default) bit 5-4 DATA_FORMAT[1:0]: ADC Output Data Format Selection 11 = 32-bit (17-bit right justified data + Channel ID): CHID[3:0] + SGN extension (12 bits) + 16-bit ADC data; it allows overrange with the SGN extension 10 = 32-bit (17-bit right justified data): SGN extension (8-bit) + 16-bit ADC data; it allows overrange with the SGN extension 01 = 32-bit (16-bit left justified data): 16-bit ADC data + 0x0000 (16 bit); it does not allow overrange (ADC code locked to 0xFFFF or 0x8000) 00 = 16-bit (default ADC coding): 16-bit ADC data; it does not allow overrange (ADC code locked to 0xFFFF or 0x8000) bit 3 CRC_FORMAT: CRC Checksum Format Selection on Read Communications (it does not affect CRCCFG coding) 1 = 32-bit wide (CRC-16 followed by 16 zeros) 0 = 16-bit wide (CRC-16 only) (default) bit 2 EN_CRCCOM: CRC Checksum Selection on Read Communications (it does not affect CRCCFG calculations) 1 = CRC on communications enabled 0 = CRC on communications disabled (default) bit 1 EN_OFFCAL: Enable Digital Offset Calibration 1 = Enabled 0 = Disabled (default) bit 0 EN_GAINCAL: Enable Digital Gain Calibration 1 = Enabled 0 = Disabled (default) DS20006404C-page 94  2020-2021 Microchip Technology Inc. MCP3461/2/4R 8.6 IRQ REGISTER Name Bits Address Cof IRQ 8 0x5 R/W REGISTER 8-6: U-0 — R-1 IRQ: INTERRUPT REQUEST REGISTER R-1 R-1 DR_STATUS CRCCFG_STATUS POR_STATUS R/W-0 R/W-0 IRQ_MODE[1:0] (1) R/W-1 R/W-1 EN_FASTCMD EN_STP bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 Unimplemented: Read as ‘0’ bit 6 DR_STATUS: Data Ready Status Flag 1 = ADCDATA has not been updated since last reading or last Reset (default) 0 = New ADCDATA ready for reading bit 5 CRCCFG_STATUS: CRC Error Status Flag Bit for Internal Registers 1 = CRC error has not occurred for the Configuration registers (default) 0 = CRC error has occurred for the Configuration registers bit 4 POR_STATUS: POR Status Flag 1 = POR has not occurred since the last reading (default) 0 = POR has occurred since the last reading bit 3-2 IRQ_MODE[1:0]: Configuration for the IRQ/MDAT Pin(1) IRQ_MODE[1]: IRQ/MDAT Selection 1 = MDAT output is selected. Only POR and CRC interrupts can be present on this pin and take priority over the MDAT output 0 = IRQ output is selected. All interrupts can appear on the IRQ/MDAT pin IRQ_MODE[0]: IRQ Pin Inactive State Selection 1 = The Inactive state is logic high (does not require a pull-up resistor to DVDD) 0 = The Inactive state is High-Z (requires a pull-up resistor to DVDD) (default) bit 1 EN_FASTCMD: Enable Fast Commands in the COMMAND Byte 1 = Fast commands are enabled (default) 0 = Fast commands are disabled bit 0 EN_STP: Enable Conversion Start Interrupt Output 1 = Enabled (default) 0 = Disabled Note 1: When IRQ_MODE[1:0] = 10 or 11, the modulator output codes (MDAT stream) are available at both the MDAT pin and ADCDATA register (0x0).  2020-2021 Microchip Technology Inc. DS20006404C-page 95 MCP3461/2/4R 8.7 MULTIPLEXER (MUX) REGISTER Name Bits Address Cof MUX 8 0x6 R/W REGISTER 8-7: R/W-0 MUX: MULTIPLEXER REGISTER R/W-0 R/W-0 R/W-0 R/W-0 MUX_VIN+[3:0](2,3) R/W-0 R/W-0 R/W-1 MUX_VIN-[3:0](2,3) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared Bit 7-4 MUX_VIN+[3:0]: Input Selection(2,3) 1111 = Internal VCM 1110 = Internal Temperature Sensor Diode M (Temp Diode M)(1) 1101 = Internal Temperature Sensor Diode P (Temp Diode P)(1) 1100 = REFIN1011 = REFIN+/OUT 1010 = Reserved (do not use) 1001 = AVDD 1000 = AGND 0111 = CH7 0110 = CH6 0101 = CH5 0100 = CH4 0011 = CH3 0010 = CH2 0001 = CH1 0000 = CH0 (default) Bit 3-0 MUX_VIN-[3:0]: Input Selection(2,3) 1111 = Internal VCM 1110 = Internal Temperature Sensor Diode M (Temp Diode M)(1) 1101 = Internal Temperature Sensor Diode P (Temp Diode P)(1) 1100 = REFIN1011 = REFIN+/OUT 1010 = Reserved (do not use) 1001 = AVDD 1000 = AGND 0111 = CH7 0110 = CH6 0101 = CH5 0100 = CH4 0011 = CH3 0010 = CH2 0001 = CH1 (default) 0000 = CH0 Note 1: 2: 3: x = Bit is unknown Selects the internal temperature sensor diode and forces a fixed current through it. For a correct temperature reading, the MUX[7:0] selection should be equal to 0xDE. For MCP3462R, the codes, ‘0111/0110/0101/0100’, correspond to a floating input and should be avoided. For MCP3461R, the codes, ‘0111/0110/0101/0100/0011/0010’, correspond to a floating input and should be avoided. DS20006404C-page 96  2020-2021 Microchip Technology Inc. MCP3461/2/4R 8.8 SCAN REGISTER Name Bits Address Cof SCAN 24 0x7 R/W REGISTER 8-8: R/W-0 SCAN: SCAN MODE SETTINGS REGISTER R/W-0 R/W-0 DLY[2:0] R/W-0 U-0 RESERVED — bit 23 bit 16 R/W-0 R/W-0 R/W-0 R/W-0 OFFSET VCM AVDD TEMP R/W-0 R/W-0 R/W-0 R/W-0 SCAN_DIFF_CH[D:A] bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 SCAN_SE_CH[7:0] bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared Bit 23-21 x = Bit is unknown DLY[2:0]: Delay Time (TDLY_SCAN) Between Each Conversion During a Scan Cycle 111 = 512 * DMCLK 110 = 256 * DMCLK 101 = 128 * DMCLK 100 = 64 * DMCLK 011 = 32 * DMCLK 010 = 16 * DMCLK 001 = 8 * DMCLK 000 = 0: No delay (default) Bit 20 RESERVED: Should be set to ‘0’ Bit 19-16 Unimplemented: Read as ‘0’ Bit 15-0 SCAN Channel Selection (see Table 5-15 for a complete description)  2020-2021 Microchip Technology Inc. DS20006404C-page 97 MCP3461/2/4R 8.9 TIMER REGISTER Name Bits Address Cof TIMER 24 0x8 R/W REGISTER 8-9: TIMER: TIMER DELAY VALUE REGISTER R/W-0 TIMER[23:0] bit 23 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared Bit 23-0 x = Bit is unknown TIMER[23:0]: Selection Bits for the Time Interval (TTIMER_SCAN) Between Two Consecutive Scan Cycles (when CONV_MODE[1:0] = 11) 0xFFFF: TTIMER_SCAN = 16777215 * DMCLK periods 0xFFFFFE: TTIMER_SCAN = 16777214 * DMCLK periods • • • 0x000002: TTIMER_SCAN = 2 * DMCLK periods 0x000001: TTIMER_SCAN = 1 * DMCLK periods 0x000000: TTIMER_SCAN = 0 (no delay) – default DS20006404C-page 98  2020-2021 Microchip Technology Inc. MCP3461/2/4R 8.10 OFFSETCAL REGISTER Name Bits Address Cof OFFSETCAL 24 0x9 R/W REGISTER 8-10: OFFSETCAL: OFFSET CALIBRATION REGISTER R/W-0 OFFSETCAL[23:16] bit 23 bit 16 R/W-0 OFFSETCAL[15:8] bit 15 bit 8 U-0 — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown Bit 23-8 OFFSETCAL[23:8]: Offset Error Digital Calibration Code (two’s complement, MSb first coding) See Section 5.13 “Digital System Offset and Gain Calibrations”. Bit 7-0 Unimplemented[7:0]: 0x00  2020-2021 Microchip Technology Inc. DS20006404C-page 99 MCP3461/2/4R 8.11 GAINCAL REGISTER Name Bits Address Cof GAINCAL 24 0xA R/W REGISTER 8-11: GAINCAL: GAIN CALIBRATION REGISTER R/W-0 GAINCAL[23:16] bit 23 bit 16 R/W-0 GAINCAL[15:8] bit 15 bit 8 U-0 — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown Bit 23-8 GAINCAL[23:8]: Gain Error Digital Calibration Code (unsigned, MSb first coding) The GAINCAL default value is 800000, which provides a gain of 1x. See Section 5.13 “Digital System Offset and Gain Calibrations”. Bit 7-0 Unimplemented[7:0]: 0x00 DS20006404C-page 100  2020-2021 Microchip Technology Inc. MCP3461/2/4R 8.12 RESERVED REGISTER Name Bits Address Cof RESERVED 24 0xB R/W REGISTER 8-12: RESERVED REGISTER R/W-0x900000 RESERVED[23:0] bit 23 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared Bit 23-0 8.13 x = Bit is unknown RESERVED[23:0]: Should be set to 0x900000 RESERVED REGISTER Name Bits Address Cof RESERVED 8 0xC R/W REGISTER 8-13: RESERVED REGISTER R/W-0x30 RESERVED[7:0] bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared Bit 7-0 x = Bit is unknown RESERVED[7:0]: Should be set to 0x30  2020-2021 Microchip Technology Inc. DS20006404C-page 101 MCP3461/2/4R 8.14 LOCK REGISTER Name Bits Address Cof LOCK 8 0xD R/W REGISTER 8-14: R/W-1 LOCK: SPI WRITE MODE LOCKING PASSWORD VALUE REGISTER R/W-0 R/W-1 R/W-0 R/W-0 R/W-1 R/W-0 R/W-1 LOCK[7:0] bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared Bit 7-0 8.15 x = Bit is unknown LOCK[7:0]: Write Access Password Entry Code 0xA5 = Write access is allowed on the full register map. CRC on register map values is not calculated (CRCCFG[15:0] = 0x0000) – default. Any code, except 0xA5 = Write access, is not allowed on the full register map. Only the LOCK register is writable. CRC on register map is calculated continuously only when DMCLK is running. RESERVED REGISTER Name Bits Address Cof RESERVED 16 0xE R/W REGISTER 8-15: RESERVED REGISTER R/W (default depends on product denomination) RESERVED[15:0] bit 15 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared Bit 15-0 x = Bit is unknown RESERVED[15:0]: Should be set to MCP3461R: 0x0008 MCP3462R: 0x0009 MCP3464R: 0x000B DS20006404C-page 102  2020-2021 Microchip Technology Inc. MCP3461/2/4R 8.16 CRCCFG REGISTER Name Bits Address Cof CRCCFG 16 0xF R REGISTER 8-16: CRCCFG: CRC CONFIGURATION REGISTER R-0 CRCCFG[15:0] bit 15 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared Bit 15-0 x = Bit is unknown CRCCFG[15:0]: CRC-16 Checksum Value CRC-16 checksum is continuously calculated internally based on the register map configuration settings when the device is locked (LOCK[7:0] ≠ 0xA5).  2020-2021 Microchip Technology Inc. DS20006404C-page 103 MCP3461/2/4R NOTES: DS20006404C-page 104  2020-2021 Microchip Technology Inc. MCP3461/2/4R 9.0 PACKAGING INFORMATION 9.1 Package Marking Information(1) 20-Lead UQFN (3 x 3 x 0.55 mm) PIN 1 Example XXX YYWW NNN PIN 1 AAM 2112 256 Part Number Code SPI Device Address MCP3461RT-E/NC AAM 01(2) MCP3462RT-E/NC AAN 01(2) MCP3464RT-E/NC AAP 01(2) (3) 20-Lead TSSOP (6.5 x 4.4 x 1 mm) Example XXXXXXXX XXXXXNNN MCP464R EST e3 256 YYWW 2112 Legend: XX...X Y YY WW NNN e3 * Customer-specific information Year code (last digit of calendar year) Year code (last 2 digits of calendar year) Week code (week of January 1 is week ‘01’) Alphanumeric traceability code Pb-free JEDEC designator for Matte Tin (Sn) This package is Pb-free. The Pb-free JEDEC designator ( e3 ) can be found on the outer packaging for this package. Note 1: In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. 2: Denotes the device default SPI address option. The device only responds to SPI commands if CMD[7:6] matches the SPI device address for each command (see Section 6.2.2 “Device Address Bits (CMD[7:6])”). Contact Microchip Sales for other device address option ordering procedure. 3: The 20-Lead TSSOP package allows up to 8 characters per line as shown here. Currently only 7 characters are being used as shown in the example.  2020-2021 Microchip Technology Inc. DS20006404C-page 105 MCP3461/2/4R 20-Lead Ultra Thin Plastic Quad Flat, No Lead Package 1&- 3x3 mm Body [UQFN] (Formerly Q3DE; SST Legacy Package) Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging D NOTE 1 A B N 1 2 E (DATUM B) (DATUM A) 2X 0.075 C 2X TOP VIEW 0.075 C 0.10 C C SEATING PLANE A1 A 20X (A3) SIDE VIEW 0.08 C 0.10 C A B D2 0.10 See Detail A C A B e 2 E2 2 1 NOTE 1 K N 20X b 0.10 0.05 e C A B C BOTTOM VIEW Microchip Technology Drawing C04-264A Sheet 1 of 2 DS20006404C-page 106  2020-2021 Microchip Technology Inc. MCP3461/2/4R 20-Lead Ultra Thin Plastic Quad Flat, No Lead Package1&- 3x3 mm Body [UQFN] (Formerly Q3DE; SST Legacy Package) Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging (b) b1 L DETAIL A Units Dimension Limits N Number of Terminals e Pitch A Overall Height Standoff A1 A3 Terminal Thickness Overall Length D Exposed Pad Length D2 E Overall Width E2 Exposed Pad Width b Terminal Width (Inner) b1 Terminal Width (Outer) L Terminal Length K Terminal-to-Exposed-Pad MIN 0.50 0.00 1.60 1.60 0.15 0.35 0.20 MILLIMETERS NOM 20 0.40 BSC 0.55 0.02 0.15 REF 3.00 BSC 1.70 3.00 BSC 1.70 0.15 REF 0.20 0.40 - MAX 0.60 0.05 1.80 1.80 0.25 0.45 - Notes: 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. Package is saw singulated 3. Dimensioning and tolerancing per ASME Y14.5M BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only. Microchip Technology Drawing C04-264A Sheet 2 of 2  2020-2021 Microchip Technology Inc. DS20006404C-page 107 MCP3461/2/4R 20-Lead Ultra Thin Plastic Quad Flat, No Lead Package1&- 3x3 mm Body [UQFN] (Formerly Q3DE; SST Legacy Package) Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging C1 X2 EV 20 ØV 1 2 C2 Y2 EV G1 Y1 X1 E SILK SCREEN RECOMMENDED LAND PATTERN Units Dimension Limits Contact Pitch E X2 Optional Center Pad Width Optional Center Pad Length Y2 Contact Pad Spacing C1 Contact Pad Spacing C2 Contact Pad Width (X20) X1 Contact Pad Length (X20) Y1 Contact Pad to Center Pad (X20) G1 Thermal Via Diameter V Thermal Via Pitch EV MIN MILLIMETERS NOM 0.40 BSC MAX 1.80 1.80 3.00 3.00 0.20 0.80 0.20 0.30 1.00 Notes: 1. Dimensioning and tolerancing per ASME Y14.5M BSC: Basic Dimension. Theoretically exact value shown without tolerances. 2. For best soldering results, thermal vias, if used, should be filled or tented to avoid solder loss during reflow process Microchip Technology Drawing C04-2264A DS20006404C-page 108  2020-2021 Microchip Technology Inc. MCP3461/2/4R  2020-2021 Microchip Technology Inc. DS20006404C-page 109 MCP3461/2/4R DS20006404C-page 110  2020-2021 Microchip Technology Inc. MCP3461/2/4R Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2020-2021 Microchip Technology Inc. DS20006404C-page 111 MCP3461/2/4R NOTES: DS20006404C-page 112  2020-2021 Microchip Technology Inc. MCP3461/2/4R APPENDIX A: REVISION HISTORY Revision C (April 2021) • Updated size for 20-Lead TSSOP package throughout the document • Updated Features • Updated Section 2.1, Noise Specifications • Updated Equation 2-1 and Equation 2-2 • Updated Table 2-2 and Table 2-4 • Updated Section 9.0, Packaging Information Revision B (December 2020) The following is the list of modifications: • Corrected Table 5-11 • Corrected Register 8-2 Note: The SPI standard uses the terminology “Master” and “Slave”. The equivalent Microchip terminology used in this document is “Host” and “Client”, respectively. Revision A (August 2020) • Initial release of this document.  2020-2021 Microchip Technology Inc. DS20006404C-page 113 MCP3461/2/4R NOTES:  2020-2021 Microchip Technology Inc. DS20006404C-page 114 MCP3461/2/4R PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. X(1) PART NO. Device Tape and Reel X /XX Temperature Range Package Device: MCP3461/2/4R: Two/Four/Eight Differential Channel, 16-bit Delta-Sigma ADCs with Internal Voltage Reference. Tape and Reel: T = Tape and Reel Blank = Standard packaging (tube or tray) Temperature Range: E = -40°C to +125°C (Extended) Package: NC = Ultra Small, No Lead Package (UQFN), 3 x 3 x 0.55 mm, 20-Lead = Plastic Thin Shrink Small Outline (TSSOP), 6.5 x 4.4 x 1 mm, 20-Lead ST Examples: a) MCP3461RT-E/NC: Single Channel ADC, Tape and Reel, Extended Temperature, 20-Lead UQFN. b) MCP3462RT-E/NC: Dual Channel ADC, Tape and Reel, Extended Temperature, 20-Lead UQFN. c) MCP3464RT-E/NC: Quad Channel ADC, Tape and Reel, Extended Temperature, 20-Lead UQFN. d) MCP3461RT-E/ST: Single Channel ADC, Tape and Reel, Extended Temperature, 20-Lead TSSOP. e) MCP3462R-E/ST: Dual Channel ADC, Standard Packaging, Extended Temperature, 20-Lead TSSOP. f) MCP3464R-E/ST: Quad Channel ADC, Standard Packaging, Extended Temperature, 20-Lead TSSOP. Note  2020-2021 Microchip Technology Inc. 1: Tape and Reel identifier only appears in the catalog part number description. This identifier is used for ordering purposes and is not printed on the device package. Check with your Microchip Sales Office for package availability with the Tape and Reel option. 2: Device SPI Address ‘01’ is the default address option. Contact Microchip Sales for other device address option ordering procedure. DS20006404C-page 115 MCP3461/2/4R NOTES: DS20006404C-page 116  2020-2021 Microchip Technology Inc. Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specifications contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is secure when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods being used in attempts to breach the code protection features of the Microchip devices. We believe that these methods require using the Microchip products in a manner outside the operating specifications contained in Microchip's Data Sheets. Attempts to breach these code protection features, most likely, cannot be accomplished without violating Microchip's intellectual property rights. • Microchip is willing to work with any customer who is concerned about the integrity of its code. • Neither Microchip nor any other semiconductor manufacturer can guarantee the security of its code. Code protection does not mean that we are guaranteeing the product is "unbreakable." Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip's code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication is provided for the sole purpose of designing with and using Microchip products. Information regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. THIS INFORMATION IS PROVIDED BY MICROCHIP "AS IS". MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION INCLUDING BUT NOT LIMITED TO ANY IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE OR WARRANTIES RELATED TO ITS CONDITION, QUALITY, OR PERFORMANCE. IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE INFORMATION OR ITS USE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY RELATED TO THE INFORMATION OR ITS USE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THE INFORMATION. Use of Microchip devices in life support and/or safety applications is entirely at the buyer's risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights unless otherwise stated. Trademarks The Microchip name and logo, the Microchip logo, Adaptec, AnyRate, AVR, AVR logo, AVR Freaks, BesTime, BitCloud, chipKIT, chipKIT logo, CryptoMemory, CryptoRF, dsPIC, FlashFlex, flexPWR, HELDO, IGLOO, JukeBlox, KeeLoq, Kleer, LANCheck, LinkMD, maXStylus, maXTouch, MediaLB, megaAVR, Microsemi, Microsemi logo, MOST, MOST logo, MPLAB, OptoLyzer, PackeTime, PIC, picoPower, PICSTART, PIC32 logo, PolarFire, Prochip Designer, QTouch, SAM-BA, SenGenuity, SpyNIC, SST, SST Logo, SuperFlash, Symmetricom, SyncServer, Tachyon, TimeSource, tinyAVR, UNI/O, Vectron, and XMEGA are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. AgileSwitch, APT, ClockWorks, The Embedded Control Solutions Company, EtherSynch, FlashTec, Hyper Speed Control, HyperLight Load, IntelliMOS, Libero, motorBench, mTouch, Powermite 3, Precision Edge, ProASIC, ProASIC Plus, ProASIC Plus logo, QuietWire, SmartFusion, SyncWorld, Temux, TimeCesium, TimeHub, TimePictra, TimeProvider, WinPath, and ZL are registered trademarks of Microchip Technology Incorporated in the U.S.A. Adjacent Key Suppression, AKS, Analog-for-the-Digital Age, Any Capacitor, AnyIn, AnyOut, Augmented Switching, BlueSky, BodyCom, CodeGuard, CryptoAuthentication, CryptoAutomotive, CryptoCompanion, CryptoController, dsPICDEM, dsPICDEM.net, Dynamic Average Matching, DAM, ECAN, Espresso T1S, EtherGREEN, IdealBridge, In-Circuit Serial Programming, ICSP, INICnet, Intelligent Paralleling, Inter-Chip Connectivity, JitterBlocker, maxCrypto, maxView, memBrain, Mindi, MiWi, MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach, Omniscient Code Generation, PICDEM, PICDEM.net, PICkit, PICtail, PowerSmart, PureSilicon, QMatrix, REAL ICE, Ripple Blocker, RTAX, RTG4, SAM-ICE, Serial Quad I/O, simpleMAP, SimpliPHY, SmartBuffer, SMART-I.S., storClad, SQI, SuperSwitcher, SuperSwitcher II, Switchtec, SynchroPHY, Total Endurance, TSHARC, USBCheck, VariSense, VectorBlox, VeriPHY, ViewSpan, WiperLock, XpressConnect, and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. The Adaptec logo, Frequency on Demand, Silicon Storage Technology, and Symmcom are registered trademarks of Microchip Technology Inc. in other countries. GestIC is a registered trademark of Microchip Technology Germany II GmbH & Co. KG, a subsidiary of Microchip Technology Inc., in other countries. All other trademarks mentioned herein are property of their respective companies. © 2020-2021, Microchip Technology Incorporated, All Rights Reserved. For information regarding Microchip’s Quality Management Systems, please visit www.microchip.com/quality.  2020-2021 Microchip Technology Inc. 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