MCP3561/2/4R
Two/Four/Eight-Channel, 153.6 ksps, Low Noise
24-Bit Delta-Sigma ADCs with Internal Voltage Reference
Features
General Description
• One/Two/Four Differential or Two/Four/Eight
Single-Ended Input Channels
• 24-Bit Resolution
• Programmable Data Rate: Up to 153.6 ksps
• Programmable Gain: 0.33x to 64x
• 106.7 dB SINAD, -116 dBc THD, 120 dBc SFDR
(Gain = 1x, 4800 SPS)
• Low-Temperature Drift:
- Offset error drift: 4/Gain nV/°C (AZ_MUX = 1)
- Gain error drift: 0.5 ppm/°C (Gain = 1x)
• Low Noise: 90 nVRMS (Gain = 16x,12.5 SPS)
• RMS ENOB: Up to 23.3 Bits
• Wide Input Voltage Range: 0V to AVDD
• Selectable Internal 2.4V Voltage Reference with
15 ppm/°C drift
• Differential Voltage Reference Inputs
• Internal Oscillator or External Clock Selection
• Ultra-Low Full Shutdown Current Consumption
( 512), the
thermal noise is largely dominant and increases
proportionally to the square root of the absolute
temperature. The performance in the following tables
has been measured with the device placed in Continuous Conversion mode, with the differential input voltage equal to VIN = 0V, default conditions for the register
map and MCLK = 4.9152 MHz.
The noise performance is also a function of the
measurement duration. For short duration measurements (low number of consecutive samples), the
peak-to-peak noise is usually reduced because the
crest factor (ratio between the RMS noise and
peak-to-peak noise) is reduced. This is only a consequence of the noise distribution being Gaussian by
nature (see Figure 2-5 for noise histogram example
and fitting with an ideal Gaussian distribution). The
noise specifications have been measured with a
sample size of 16384 samples for low OSR values and
have been capped to approximately 80 seconds for the
16384 samples leading to a larger duration. The noise
specifications are expressed in two different values,
which lead to the same quantity. It may be more practical to choose one of these representations depending
on the desired application.
In Table 2-1, the RMS (Root Mean Square) noise is the
variance of the ADC output code, expressed in µVRMS
and input referred with Equation 5-5. The peak-to-peak
noise values are in parentheses. The peak-to-peak
noise is the difference between the maximum and
minimum code observed during the complete time of
the measurement (see Equation 5-5).
In Table 2-2, the noise is expressed in ENOB (Effective
Number of Bits). The ENOB is a ratio of the full-scale
range of the ADC (that depends on VREF and gain) and
the noise performance of the device. The ENOB can be
determined from the RMS or peak-to-peak noise with
the following equations.
DS20006391A-page 26
EQUATION 2-1:
ENOBRMS
2 V REF
ln -----------------------------------------------------
GAIN RMS (Noise)
= ---------------------------------------------------------------ln 2
EQUATION 2-2:
ENOB pk – pk
2 V REF
ln ----------------------------------------------------------------------
GAIN Peak-to-Peak Noise
= --------------------------------------------------------------------------------ln 2
Due to the nature of the noise, the performance
detailed in the noise tables can vary significantly from
one measurement to another. They present an
averaging of the performance over a large distribution
of parts over multiple lots. They give the typical
expectation of the noise performance, but performance
can be better or worse if a limited number of
measurements is performed. For large gain and OSR
combinations, if the noise performance is comparable
to the quantization step (1 LSb), the performance is
limited to 0.5 LSb for the RMS noise and 1 LSb for the
peak-to-peak noise (same limits for ENOB values).
These figures correspond to the resolution limit of the
device as peak-to-peak noise cannot be better than
1 LSb. Similarly, if the intrinsic RMS noise of the device
is much smaller than 0.5 LSb, it may lead to histogram
with either one or two bins, depending on the relative
position of the input voltage versus the possible quantized outputs of the ADC. If the position is exactly in
between two quantization steps, the histogram of
output noise will have two bins with exactly 50% occurrence on each. This case gives an RMS noise of a
0.5 LSb value, which is therefore, used as a cap of the
performance for the sake of clarity and a better
representation on the noise tables.
The noise specifications are improved by a ratio of
approximately √2 (or 0.5-bit ENOB) when the AZ_MUX
setting is enabled. However, the output data rate is
significantly reduced (see Figure 5-5 and Table 5-6).
The digital gain added for GAIN = 32x and 64x settings
is not significant for the noise performance, and therefore, the noise values can be extracted from the
GAIN = 16x columns. ENOB performance is degraded
by 1 bit for GAIN = 32x and 2 bits for GAIN = 64x
compared to GAIN = 16x performance.
Note:
All Output Noise performance-related
tables and figures are with reference to
the input, i.e. Input Referred.
2020 Microchip Technology Inc.
MCP3561/2/4R
TABLE 2-1:
OUTPUT NOISE VS. GAIN VS. OSR (AVDD = DVDD = VREF = 3.3V, TA = 25°C)
RMS (Peak-to-Peak) Noise (µV)
TOTAL
OSR
GAIN = 0.33
GAIN = 1
GAIN = 2
GAIN = 4
GAIN = 8
GAIN = 16
32
365.02 (2932.55)
120.80 (981.90)
60.79 (489.77)
30.70 (243.71)
15.69 (125.98)
8.23 (65.94)
64
68.06 (566.05)
23.56 (189.40)
12.54 (101.97)
7.06 (55.09)
4.25 (34.15)
2.77 (22.05)
128
35.21 (313.00)
12.68 (108.08)
7.03 (57.36)
4.19 (33.51)
2.68 (21.43)
1.83 (14.47)
256
24.83 (212.31)
8.94 (73.35)
4.94 (40.62)
2.94 (23.38)
1.88 (15.17)
1.29 (10.11)
512
17.99 (150.04)
6.43 (52.02)
3.53 (28.51)
2.09 (17.02)
1.34 (10.58)
0.92 (7.32)
1024
15.12 (123.74)
5.40 (43.95)
2.97 (23.54)
1.75 (14.05)
1.12 (8.82)
0.77 (6.20)
2048
11.47 (91.51)
4.08 (32.01)
2.26 (18.04)
1.34 (10.69)
0.86 (6.79)
0.59 (4.57)
4096
8.32 (64.97)
2.98 (23.59)
1.66 (13.10)
0.98 (7.85)
0.63 (4.97)
0.43 (3.45)
8192
5.88 (44.39)
2.11 (15.61)
1.18 (8.99)
0.70 (5.39)
0.45 (3.37)
0.31 (2.30)
16384
4.16 (30.56)
1.50 (10.80)
0.84 (6.12)
0.50 (3.65)
0.32 (2.28)
0.22 (1.60)
20480
3.71 (26.82)
1.34 (9.65)
0.75 (5.29)
0.44 (3.27)
0.28 (2.06)
0.19 (1.41)
24576
3.40 (24.24)
1.23 (8.88)
0.69 (4.88)
0.41 (2.94)
0.26 (1.92)
0.18 (1.29)
40960
2.70 (18.79)
0.98 (6.53)
0.55 (3.83)
0.32 (2.22)
0.20 (1.41)
0.14 (0.96)
49152
2.52 (17.44)
0.90 (6.08)
0.50 (3.47)
0.30 (2.07)
0.19 (1.25)
0.13 (0.87)
81920
2.05 (13.19)
0.74 (4.64)
0.40 (2.56)
0.24 (1.52)
0.15 (0.96)
0.10 (0.63)
98304
1.94 (12.20)
0.68 (4.37)
0.38 (2.39)
0.22 (1.37)
0.14 (0.89)
0.09 (0.59)
TABLE 2-2:
EFFECTIVE NUMBER OF BITS VS. GAIN VS. OSR (AVDD = DVDD = VREF = 3.3V,
TA = 25°C)
ENOB RMS (Peak-to-Peak) (bits)
TOTAL
OSR
GAIN = 0.33
GAIN = 1
GAIN = 2
GAIN = 4
GAIN = 8
GAIN = 16
32
15.7 (12.7)
15.7 (12.7)
15.7 (12.7)
15.7 (12.7)
15.7 (12.7)
15.6 (12.6)
64
18.2 (15.1)
18.1 (15.1)
18.0 (15.0)
17.8 (14.9)
17.6 (14.6)
17.2 (14.2)
128
19.1 (16.0)
19.0 (15.9)
18.8 (15.8)
18.6 (15.6)
18.2 (15.2)
17.8 (14.8)
256
19.6 (16.5)
19.5 (16.5)
19.4 (16.3)
19.1 (16.1)
18.7 (15.7)
18.3 (15.3)
512
20.1 (17.0)
20.0 (17.0)
19.8 (16.8)
19.6 (16.6)
19.2 (16.3)
18.8 (15.8)
1024
20.3 (17.3)
20.2 (17.2)
20.1 (17.1)
19.8 (16.8)
19.5 (16.5)
19.0 (16.0)
2048
20.7 (17.7)
20.6 (17.7)
20.5 (17.5)
20.2 (17.2)
19.9 (16.9)
19.4 (16.5)
4096
21.2 (18.2)
21.1 (18.1)
20.9 (17.9)
20.7 (17.7)
20.3 (17.3)
19.9 (16.9)
8192
21.7 (18.8)
21.6 (18.7)
21.4 (18.5)
21.2 (18.2)
20.8 (17.9)
20.4 (17.5)
16384
22.2 (19.3)
22.1 (19.2)
21.9 (19.0)
21.6 (18.8)
21.3 (18.5)
20.9 (18.0)
20480
22.4 (19.5)
22.2 (19.4)
22.1 (19.2)
21.8 (18.9)
21.5 (18.6)
21.0 (18.2)
24576
22.5 (19.7)
22.4 (19.5)
22.2 (19.4)
21.9 (19.1)
21.6 (18.7)
21.1 (18.3)
40960
22.8 (20.0)
22.7 (20.0)
22.5 (19.7)
22.3 (19.5)
21.9 (19.2)
21.5 (18.7)
49152
22.9 (20.1)
22.8 (20.1)
22.7 (19.9)
22.4 (19.6)
22.1 (19.3)
21.6 (18.9)
81920
23.2 (20.5)
23.1 (20.4)
23.0 (20.3)
22.7 (20.1)
22.4 (19.7)
22.0 (19.3)
98304
23.3 (20.6)
23.2 (20.5)
23.1 (20.4)
22.8 (20.2)
22.5 (19.8)
22.1 (19.4)
Note:
To calculate noise RMS level and effective number of bits for a given GAIN and data rate, refer to the OSR
setting and associated data rate relationship shown in Table 5-6.
2020 Microchip Technology Inc.
DS20006391A-page 27
MCP3561/2/4R
TABLE 2-3:
OUTPUT NOISE VS. GAIN VS. OSR (AVDD = DVDD = 3.3V, VREF = 2.4V INTERNAL,
TA = 25°C)
RMS (Peak-to-Peak) Noise (µV)
TOTAL
OSR
GAIN = 0.33
GAIN = 1
GAIN = 2
GAIN = 4
GAIN = 8
GAIN = 16
32
275.92 (2169.18)
91.57 (746.73)
46.26 (373.37)
23.50 (187.97)
12.16 (97.85)
6.52 (55.04)
64
65.13 (536.40)
22.54 (184.73)
12.04 (98.83)
6.76 (55.04)
4.05 (34.12)
2.64 (21.65)
128
38.21 (309.86)
13.47 (109.15)
7.35 (58.99)
4.27 (34.47)
2.66 (21.26)
1.79 (14.39)
256
26.60 (217.70)
9.38 (75.24)
5.14 (42.71)
2.99 (23.78)
1.88 (15.13)
1.27 (10.14)
512
18.94 (149.55)
6.65 (54.08)
3.65 (29.73)
2.13 (17.38)
1.33 (10.46)
0.89 (7.33)
1024
15.90 (126.06)
5.58 (44.03)
3.05 (24.21)
1.78 (14.33)
1.11 (8.98)
0.75 (6.06)
2048
12.06 (93.72)
4.25 (35.36)
2.33 (19.23)
1.35 (11.06)
0.85 (6.87)
0.57 (4.54)
4096
8.75 (68.40)
3.09 (24.49)
1.70 (13.25)
0.98 (7.98)
0.62 (4.85)
0.42 (3.33)
8192
6.31 (47.08)
2.22 (16.88)
1.22 (9.54)
0.71 (5.39)
0.44 (3.51)
0.30 (2.28)
16384
4.55 (35.03)
1.61 (11.70)
0.88 (6.41)
0.51 (3.77)
0.32 (2.32)
0.21 (1.53)
20480
4.11 (29.82)
1.45 (10.76)
0.79 (5.85)
0.46 (3.23)
0.28 (2.06)
0.19 (1.39)
24576
3.79 (27.14)
1.34 (9.87)
0.73 (5.28)
0.42 (3.03)
0.26 (1.85)
0.17 (1.27)
40960
3.02 (21.15)
1.06 (7.24)
0.57 (4.06)
0.33 (2.27)
0.20 (1.43)
0.14 (0.96)
49152
2.79 (19.51)
0.98 (6.58)
0.53 (3.61)
0.30 (2.15)
0.19 (1.32)
0.12 (0.87)
81920
2.27 (14.91)
0.79 (5.01)
0.43 (2.89)
0.24 (1.62)
0.15 (0.99)
0.10 (0.63)
98304
2.09 (14.04)
0.72 (4.49)
0.39 (2.52)
0.22 (1.45)
0.14 (0.93)
0.09 (0.59)
TABLE 2-4:
EFFECTIVE NUMBER OF BITS VS. GAIN VS. OSR (AVDD = DVDD = 3.3V, VREF = 2.4V
INTERNAL, TA = 25°C)
ENOB RMS (Peak-to-Peak) (bits)
TOTAL
OSR
GAIN = 0.33
32
15.2 (12.7)
15.2 (12.7)
15.2 (12.6)
64
17.3 (14.8)
17.2 (14.7)
17.1 (14.6)
128
18.0 (15.5)
17.9 (15.4)
17.8 (15.3)
256
18.6 (16.1)
18.5 (16.0)
512
19.1 (16.6)
19.0 (16.4)
1024
19.3 (16.8)
2048
GAIN = 8
GAIN = 16
15.1 (12.6)
15.1 (12.6)
15.00 (12.5)
16.9 (14.5)
16.7 (14.2)
16.3 (13.8)
17.6 (15.1)
17.3 (14.8)
16.9 (14.4)
18.3 (15.8)
18.1 (15.6)
17.8 (15.3)
17.4 (14.9)
18.8 (16.3)
18.6 (16.1)
18.3 (15.8)
17.9 (15.4)
19.2 (16.7)
19.1 (16.6)
18.9 (16.4)
18.5 (16.1)
18.1 (15.6)
19.7 (17.2)
19.6 (17.1)
19.5 (17.0)
19.3 (16.8)
18.9 (16.4)
18.5 (16.0)
4096
20.2 (17.7)
20.1 (17.6)
19.9 (17.4)
19.7 (17.2)
19.4 (16.9)
19.0 (16.5)
8192
20.6 (18.2)
20.5 (18.1)
20.4 (18.0)
20.2 (17.8)
19.9 (17.4)
19.4 (17.0)
16384
21.1 (18.7)
21.0 (18.7)
20.9 (18.5)
20.7 (18.3)
20.4 (18.0)
19.9 (17.6)
20480
21.3 (18.9)
21.2 (18.8)
21.0 (18.7)
20.8 (18.5)
20.5 (18.2)
20.1 (17.7)
24576
21.4 (19.0)
21.3 (18.9)
21.2 (18.8)
21.0 (18.6)
20.6 (18.3)
20.2 (17.9)
40960
21.7 (19.4)
21.6 (19.3)
21.5 (19.2)
21.3 (19.0)
21.0 (18.7)
20.6 (18.3)
49152
21.8 (19.5)
21.7 (19.5)
21.6 (19.3)
21.4 (19.1)
21.1 (18.8)
20.7 (18.4)
81920
22.1 (19.9)
22.0 (19.8)
21.9 (19.8)
21.8 (19.5)
21.5 (19.3)
21.0 (18.9)
98304
22.2 (20.0)
22.2(20.0)
22.0 (19.9)
21.9 (19.7)
21.6 (19.4)
21.2 (19.0)
Note:
GAIN = 1
GAIN = 2
GAIN = 4
To calculate noise RMS level and effective number of bits for a given GAIN and data rate, refer to the OSR
setting and associated data rate relationship shown in Table 5-6.
DS20006391A-page 28
2020 Microchip Technology Inc.
MCP3561/2/4R
3.0
PIN DESCRIPTIONS
TABLE 3-1:
PIN FUNCTION TABLE
MCP3561 MCP3562 MCP3564
MCP3561 MCP3562 MCP3564
R
R
R
Symbol
Description
20-Lead UQFN
20-Lead TSSOP
1
3
2
4
3
5
CH0
4
6
CH1
Analog Input 1 Pin
—
5
5
—
—
6
6
—
—
7
—
—
—
—
5, 6, 7, 8,
9, 10
REFIN-
Inverting Reference Input Pin
REFIN+/OUT Non-inverting Reference Input Pin or
Internal Voltage Reference output
Analog Input 0 Pin
7
7
CH2
Analog Input 2 Pin
—
8
8
CH3
Analog Input 3 Pin
—
—
9
CH4
Analog Input 4 Pin
8
—
—
10
CH5
Analog Input 5 Pin
—
9
—
—
11
CH6
Analog Input 6 Pin
—
10
—
—
12
CH7
Analog Input 7 Pin
Serial Interface Chip Select Digital Input
Pin
11
13
CS
12
14
SCK
13
15
SDI
Serial Interface Digital Data Input Pin
14
16
SDO
Serial Interface Digital Data Output Pin
15
17
IRQ/MDAT
16
18
MCLK
Master Clock Input or Analog Master Clock
Output Pin
17
19
DGND
Digital Ground Pin
18
20
DVDD
Digital Supply Voltage Pin
19
1
AVDD
Analog Supply Voltage Pin
20
2
AGND
7, 8, 9, 10
—
21
2020 Microchip Technology Inc.
Serial Interface Digital Clock Input Pin
Interrupt Output Pin or Modulator Output
Pin
Analog Ground Pin
7, 8, 9,
10, 11, 12
9, 10, 11,
12
—
NC
Not Connected
—
—
—
EP
Exposed Thermal Pad, internally connected
to AGND
DS20006391A-page 29
MCP3561/2/4R
3.1
Differential Reference Voltage
Inputs: REFIN+/OUT, REFIN-
The REFIN+/OUT pin is the non-inverting differential
reference input (VREF+) when VREF_SEL = 0. When
VREF_SEL = 1, it is the internal voltage reference output voltage as well as the ADC voltage non-inverting
reference pin.
The REFIN- pin is the inverting differential reference
input (VREF-).
For single-ended reference applications, the REFINpin should be directly connected to AGND.
The differential reference voltage pins must respect
this condition at all times: 0.6V ≤ VREF ≤ AVDD. The
differential reference voltage input is given by the
following equation:
EQUATION 3-1:
VREF = V REF+ – VREFFor optimal ADC accuracy, appropriate bypass
capacitors should be placed between REFIN+/OUT
and AGND at all times. Using a 0.1 µF and a 10 µF
ceramic capacitor can help to decouple the reference
voltage around the sampling frequency (which would
lead to aliasing noise in the base band). These bypass
capacitors are not mandatory for correct ADC operation, but removing these capacitors may degrade the
accuracy of the ADC.
3.2
Analog Inputs (CHn): Differential
or Single-Ended
The CHn pins are the analog input signal pins for the
ADC. Two analog multiplexers are used to connect the
CHn pins to the VIN+/VIN- analog inputs of the ADC.
Each multiplexer independently selects one input to be
connected to an ADC input (VIN+ or VIN-). Each CHn
pin can either be connected to the VIN+ or VIN- inputs
of the ADC. This multiplexer selection is controlled by
either the MUX register in MUX mode or the SCAN
register in SCAN mode. See Figure 5-1 for more details
on the multiplexer structure.
When the input is selected by the multiplexer, the differential (VIN) and Common-Mode Voltage (VINCOM) at
the ADC inputs are defined by:
EQUATION 3-2:
V IN = V IN+ – V INVIN+ + VINV INCOM = ---------------------------------2
DS20006391A-page 30
The input signal level is multiplied by the internal
programmable analog gain at the front end of the
Delta-Sigma modulator. For single-ended input
measurements, the user can select VIN- to be internally
connected to AGND.
The differential input voltage should not exceed an
absolute of ±VREF/GAIN for accurate measurement. If
the input is out of range, the converter output code will
be saturated or overloaded depending on how the output data format (DATA_FORMAT[1:0]) is selected. See
Section 5.6 “ADC Output Data Format” for further
information on the ADC output coding.
The absolute voltage on each of the analog signal
input pins can range from AGND – 0.1V to VDD + 0.1V.
Any voltage above or below this range will cause
leakage currents through the Electrostatic Discharge
(ESD) diodes at the input pins. This ESD current can
cause unexpected performance of the device. The
Common-mode of the analog inputs should be chosen
such that both the differential analog input range and
the absolute voltage range on each pin are within the
specified operating range defined in the Electrical
Characteristics table.
3.3
SPI Serial Interface
Communication Pins
The SPI interface is compatible with both SPI 0,0 and
1,1 modes.
3.3.1
CHIP SELECT (CS)
This is the SPI Chip Select pin that enables/disables
the SPI serial communication. The CS falling edge
initiates the serial communication and the rising edge
terminates the communication. No communication can
take place when this pin is in a Logic High state. This
input is Schmitt Triggered.
3.3.2
SERIAL DATA CLOCK (SCK)
This is the serial clock input pin for SPI communication.
This input has a Schmitt Trigger structure. The maximum SPI clock speed is 20 MHz. Data are clocked into
the device on the rising edge of SCK. Data are clocked
out of the device on the falling edge of SCK. The device
interface is compatible with both SPI 0,0 and 1,1
modes. SPI modes can be changed when CS is in
Logic High status.
SCK and MCLK are two different and asynchronous
clocks; SCK is only required during a communication,
while MCLK is continuously required when the part
converts analog inputs.
2020 Microchip Technology Inc.
MCP3561/2/4R
3.3.3
SERIAL DATA OUTPUT PIN (SDO)
This pin is used for the SPI Data Output (SDO). The
SDO data are clocked out on the falling edge of SCK.
This pin stays high-impedance under the following
conditions:
• When CS pin is logic high.
• During the entire SPI write or Fast command
communication period after the SPI command
byte has been transmitted.
• After the two device address bits in the command
are transmitted, if the device address in the command does not match the internal chip device
address.
3.3.4
SERIAL DATA INPUT PIN (SDI)
This is the SPI Data Input (SDI) pin and it uses a
Schmitt Trigger structure. When CS is logic low, this
pin is used to send a command byte just after the CS
falling edge, which can be followed by data words of
various lengths. Data are clocked into the device on
the rising edge of SCK. Toggling SDI while reading a
register has no effect.
3.4
IRQ/MDAT
This is the digital output pin. This pin can be configured for
Interrupt (IRQ) or Modulator Data (MDAT) output using
the IRQ_MODE[1] bit setting. When IRQ_MODE[1] = 0
(default), this pin can output all four possible interrupts
(see Section 6.8 “Interrupts Description”). The
Inactive state of the pin is selectable through the
IRQ_MODE[0] bit setting (high-Z or logic high).
When IRQ_MODE[1] = 1, this pin outputs the modulator
output synchronously with AMCLK (that can be
selected as an output on the MCLK pin). In this mode,
the POR and CRC interrupts can still be generated, as
they are high-level interrupts, and will lock the
IRQ/MDAT pin to logic low until they are cleared.
When the IRQ pin is in High-Z mode, an external
pull-up resistor must be connected between DVDD and
the IRQ pin. The device needs to be able to detect a
Logic High state when no interrupt occurs in order to
function properly (the pad has an input Schmitt Trigger
to detect the state of the IRQ pin just like the user sees
it). The pull-up value can be equal to 100-200 k for a
weak pull-up using the typical clock frequency. The
pull-up resistor value must be selected in relation with
the load capacitance of the IRQ output, the MCLK
frequency and the DVDD supply voltage, so that all
interrupts can be correctly detected by the SPI master
device.
2020 Microchip Technology Inc.
3.5
MCLK
This pin is either the MCLK digital input pin for the ADC
or the AMCLK digital output pin, depending on the
CLK_SEL[1:0] bit settings in the CONFIG0 register.
The typical clock frequency specified is 4.9152 MHz.
To optimize the ADC for accuracy and ensure proper
operation, AMCLK should be limited to a certain range
depending on the BOOST and GAIN settings. The
higher GAIN settings require higher BOOST settings
to maintain high bandwidth, as the input sampling
capacitors have a larger value. Figure 2-35, Figure 2-36,
Figure 2-37, Figure 2-38 and Figure 2-43 represent the
typical accuracy (SINAD) expected with the different
combinations of BOOST and GAIN settings, and can
be used to determine an optimal set for the application
depending on the sampling speed (AMCLK) chosen.
MCLK can take larger values as long as the prescaler
settings (PRE[1:0]) limit AMCLK = MCLK/PRESCALE in
the range shown in Section 2.0 “Typical Performance
Curves”.
3.6
Digital Ground (DGND)
DGND is the ground connection to internal digital
circuitry. To ensure accuracy and noise cancellation,
DGND must be connected to the same ground as
AGND, preferably with a star connection. If a digital
ground plane is available, it is recommended that this
pin be tied to this plane of the Printed Circuit Board
(PCB). This plane should also reference all other
digital circuitry in the system. DGND is not internally
connected to AGND and must be connected externally.
3.7
Digital Power Supply (DVDD)
DVDD is the power supply pin for the digital circuitry
within the device. The voltage on this pin must be
maintained in the range specified by the Electrical
Characteristics table. For optimal performance, it is
recommended to connect appropriate bypass
capacitors (typically a 10 µF ceramic in parallel with a
0.1 µF ceramic). DVDD is monitored by the DVDD POR
monitoring circuit for the digital section.
3.8
Analog Power Supply (AVDD)
AVDD is the power supply pin for the analog circuitry
within the device. The voltage on this pin must be
maintained in the range specified by the Electrical
Characteristics table. For optimal performance, it is
recommended to connect appropriate bypass
capacitors (typically a 10 µF ceramic in parallel with a
0.1 µF ceramic). AVDD is monitored by the AVDD POR
monitoring circuit for the analog section.
DS20006391A-page 31
MCP3561/2/4R
3.9
Analog Ground (AGND)
AGND is the ground connection to internal analog
circuitry. To ensure accuracy and noise cancellation,
this pin must be connected to the same ground as
DGND, preferably with a star connection. If an analog
ground plane is available, it is recommended that this
pin be tied to this plane of the PCB. This plane should
also reference all other analog circuitry in the system.
AGND is the biasing voltage for the substrate of the die
and is not internally connected to DGND.
DS20006391A-page 32
3.10
Exposed Pad (EP)
This pad is only available on the UQFN package. The
pad is internally connected to AGND. It must be
connected to the analog ground of the PCB for optimal
accuracy and thermal performance. This pad can also
be left floating if necessary.
2020 Microchip Technology Inc.
MCP3561/2/4R
4.0
TERMINOLOGY AND
FORMULAS
This section defines the terms and formulas used
throughout this document. The following terms are
defined:
•
•
•
•
•
MCLK – Master Clock
AMCLK – Analog Master Clock
DMCLK – Digital Master Clock
DRCLK – Data Rate Clock
OSR – Oversampling Ratio
•
•
•
•
•
•
•
•
•
•
•
Offset Error
Gain Error
Integral Nonlinearity Error (INL)
Signal-to-Noise Ratio (SNR)
Signal-to-Noise and Distortion Ratio (SINAD)
Total Harmonic Distortion (THD)
Spurious-Free Dynamic Range (SFDR)
MCP3561/2/4R Delta-Sigma Architecture
Power Supply Rejection Ratio (PSRR)
Common-Mode Rejection Ratio (CMRR)
Digital Pins Output Current Consumption
PRE[1:0]
CLK_SEL[1]
OSR[3:0]
CLK_SEL[1] = 0
MCLK
Pad
0
OU T
MCLK
1/
PRESCALE
AMCLK
1/4
DMCLK
1/OSR
DRCLK
1
Internal Oscillator Multiplexer
Clock Divider
Clock Divider
Clock Divider
CLK_SEL[1:0] = 11
AMCLKOUT
FIGURE 4-1:
4.1
System Clock Details.
MCLK – Master Clock
EQUATION 4-2:
This is the master clock frequency at the MCLK input pin
when an external clock source is selected or internal
clock frequency when the internal clock is selected.
4.2
AMCLK – Analog Master Clock
This is the clock frequency that is present on the analog
portion of the device after prescaling has occurred via
the PRE[1:0] bits.
EQUATION 4-1:
ANALOG MASTER
CLOCK
MCLK
AMCLK = ----------------------Prescale
4.3
DMCLK – Digital Master Clock
This is the clock frequency that is present on the digital
portion of the device. This is also the sampling frequency or the rate at which the modulator outputs are
refreshed. Each period of this clock corresponds to one
sample and one modulator output. See Equation 4-2.
2020 Microchip Technology Inc.
DIGITAL MASTER CLOCK
AMCLK
MCLK
DMCLK = --------------------- = -------------------------------4
4 Prescale
4.4
DRCLK – Data Rate Clock
This is the output data rate in Continuous mode or the
rate at which the ADC outputs new data. Any new data
are signaled by a data ready pulse on the IRQ pin.
This data rate depends on the OSR and the prescaler
as shown in Equation 4-3.
EQUATION 4-3:
DATA RATE
DMCLK
AMCLK
MCLK
DRCLK = ---------------------- = --------------------- = --------------------------------------------------OSR
4 OSR
4 OSR Prescale
Since this is the output data rate, and since the
decimation filter is a sinc (or notch) filter, there is a
notch in the filter transfer function at each integer
multiple of this rate.
DS20006391A-page 33
MCP3561/2/4R
4.5
OSR – Oversampling Ratio
The ratio of the sampling frequency to the output data
rate. OSR = DMCLK/DRCLK in Continuous mode. See
Table 5-6 for the OSR setting effect on sinc filter
parameters.
4.6
Offset Error
EQUATION 4-5:
SignalPower
SINAD dB = 10 log ---------------------------------------------------------------------
Noise + HarmonicsPower
The calculated combination of SNR and THD per the
following formula also yields SINAD:
EQUATION 4-6:
This is the error induced by the ADC when the inputs
are shorted together (VIN = 0V). This error varies based
on gain settings, OSR settings and from chip to chip. It
can easily be calibrated out by an MCU with a
subtraction.
4.7
Gain Error
This is the error induced by the ADC on the slope of the
transfer function. It is the deviation expressed in percentage compared to the ideal transfer function defined
by Equation 5-5. The specification incorporates ADC
gain error contributions, but not the VREF contribution.
This error varies with GAIN and OSR settings. The gain
error of this device has a low-temperature coefficient.
4.8
Integral Nonlinearity Error (INL)
Integral nonlinearity error is the maximum deviation of
an ADC transition point from the corresponding point of
an ideal transfer function, with the offset and gain
errors removed, or with the end points equal to zero. It
is the maximum remaining static error after offset and
gain errors calibration for a DC input signal.
4.9
EQUATION 4-4:
SIGNAL-TO-NOISE RATIO
SignalPower
SNR dB = 10 log ----------------------------------
NoisePower
4.10
Signal-to-Noise and Distortion
Ratio (SINAD)
SINAD, THD AND SNR
RELATIONSHIP
SINAD dB = 10 log 10
4.11
SNR
-
---------10
+ 10
THD
-----------10
Total Harmonic Distortion (THD)
The THD is the ratio of the output harmonics power to
the fundamental signal power for a sine wave input and
is defined by the following equation.
EQUATION 4-7:
HarmonicsPower
THD dB = 10 log -----------------------------------------------------
FundamentalPower
The THD is usually measured only with respect to the
first ten harmonics. THD is sometimes expressed in
percentage (%). This formula converts the THD from
dB to percentage:
EQUATION 4-8:
THD % = 100 10
Signal-to-Noise Ratio (SNR)
For this device family, the Signal-to-Noise Ratio is a
ratio of the output fundamental signal power to the
noise power (not including the harmonics of the signal)
when the input is a sine wave at a predetermined
frequency. It is measured in dB. Usually, only the
maximum Signal-to-Noise Ratio is specified. The SNR
figure depends mainly on the OSR and gain settings of
the device, as well as the temperature (due to thermal
noise being dominant for high OSR).
SINAD EQUATION
4.12
THD dB
-----------------------20
Spurious-Free Dynamic Range
(SFDR)
SFDR is the ratio between the output power of the
fundamental and the highest spur in the frequency
spectrum. The spur frequency is not necessarily a harmonic of the fundamental, even though that is usually
the case. This figure represents the dynamic range of
the ADC when a full-scale signal is used at the input.
This specification depends mainly on the OSR and gain
settings.
EQUATION 4-9:
FundamentalPower
SFDR dB = 10 log -----------------------------------------------------
HighestSpurPower
Signal-to-Noise and Distortion Ratio is similar to
Signal-to-Noise Ratio, with the exception that you must
include the harmonics power in the noise power
calculation. The SINAD specification depends mainly
on the OSR and gain settings.
DS20006391A-page 34
2020 Microchip Technology Inc.
MCP3561/2/4R
4.13
MCP3561/2/4R Delta-Sigma
Architecture
A Delta-Sigma ADC is an oversampling converter that
incorporates a built-in modulator which digitizes the
quantity of charge integrated by the modulator loop.
The quantizer is the block that performs the
Analog-to-Digital conversion. The quantizer is typically
1-bit or a simple comparator which helps to maintain
the linearity performance of the ADC (the DAC
structure is in this case, inherently linear).
Multibit quantizers help to lower the quantization error
(the error fed back in the loop can be very large with
1-bit quantizers) without changing the order of the
modulator or the OSR, which leads to better SNR
figures. However, typically the linearity of such
architectures is more difficult to achieve since the DAC
is no more simple to realize and its linearity limits the
THD of such ADC.
The modulator 5-level quantizer is a Flash ADC
composed of four comparators arranged with equally
spaced thresholds and a thermometer coding. The
device also includes proprietary 5-level DAC
architecture that is inherently linear for improved THD
figures.
4.14
Power Supply Rejection Ratio
(PSRR)
This is the ratio between a change in the power supply
voltage and the change in the ADC output codes. It
measures the influence of the power supply voltage on
the ADC outputs. PSRR is defined in Equation 4-10.
The PSRR specification can be DC (the power supply
is taking multiple DC values) or AC (the power supply
is a sine wave at a certain frequency with a certain
Common-mode). In AC, the amplitude of the sine wave
represents the change in the power supply.
EQUATION 4-10:
VOUT
PSRR dB = 20 log -------------------
AV DD
Where VOUT is the equivalent input voltage that the
output code translates to with the ADC transfer
function.
4.15
Common-Mode Rejection Ratio
(CMRR)
This is the ratio between a change in the
Common-mode input voltage and the change in the
ADC output codes. It measures the influence of the
Common-mode input voltage on the ADC outputs.
The CMRR specification can be DC (the Common-mode
input voltage takes multiple DC values) or AC (the
Common-mode input voltage is a sine wave at a certain
frequency with a certain Common-mode). In AC, the
amplitude of the sine wave represents the change in
the Common-mode input voltage. CMRR is defined in
Equation 4-11.
EQUATION 4-11:
V OUT
CMRR dB = 20 log ------------------------
V INCOM
Where VINCOM = (VIN+ + VIN-)/2 is the Common-mode
input voltage and VOUT is the equivalent input voltage
that the output code translates to with the ADC transfer
function.
4.16
Digital Pins Output Current
Consumption
The digital current consumption shown in the Electrical
Characteristics table does not take into account the
current consumption generated by the digital output
pins and the charge of their capacitive loading. The
specification is intended with all output pins left floating
and no communication.
In order to estimate the additional current consumption
due to the output pins, see Equation 4-12. This equation specifies the amount of additional current due to
each pin when its output is connected to a Cload
capacitance, with respect to DGND, and submitted to an
output signal toggling at an fout frequency.
If a typical 10 MHz SPI frequency is used, with a 30 pF
load and DVDD = 3.3V, the SDO output generates an
additional maximum current consumption of 500 µA
(the maximum toggling frequency of SDO is 5 MHz,
since fSCK = 10 MHz, and this is reached when the ADC
output code is a succession of ‘1’s and ‘0’s). The Cload
value includes internal digital output driver capacitance, but this can generally be neglected with respect
to the external loading capacitance.
EQUATION 4-12:
Where:
DIDD SPI = C load DV DD f
out
Cload = Capacitance on the Output Pin
DVDD = Digital Supply Voltage
fout = Output Frequency on the Output Pin
2020 Microchip Technology Inc.
DS20006391A-page 35
MCP3561/2/4R
NOTES:
DS20006391A-page 36
2020 Microchip Technology Inc.
MCP3561/2/4R
5.0
DEVICE OVERVIEW
5.1
Analog Input Multiplexer
Each of these multiplexers includes the same
possibilities for the input selection, so that any required
combination of input voltages can be converted by the
ADC. The analog multiplexer is composed of parallel
low-resistance input switches turned on or off depending on the input channel selection. Their resistance is
negligible compared to the input impedance of the ADC
(caused by the charge and discharge of the input
sampling capacitors on the VIN+/VIN- ADC inputs). The
block diagram of the analog multiplexer is shown in
Figure 5-1.
The device includes a fully configurable analog input
dual multiplexer that can select which input is connected to each of the two differential input pins
(VIN+/VIN-) of the Delta-Sigma ADC.
The dual multiplexer is divided into two single-ended
multiplexers that are totally independent.
MUX
CH0
CH1
AGND
AVDD
AVDD
REFIN+/OUT
REFIN-
TEMP diode P
AVDD
ISOURCE
CS_SEL
AVDD
ITEMP+
ITEMP-
TEMP diode M
VCM
MUX
=1101
MUX
=1101
VIN+ Analog Multiplexer
MUX
=1110
VIN+
AGND
MUX
VIN-
CH0
CS_SEL
CH1
AGND
MUX
=1110
ISINK
Sigma-Delta ADC
AVDD
REFIN+/OUT
REFIN-
AGND
TEMP diode P
TEMP diode M
VCM
VIN- Analog Multiplexer
AGND
Analog Input Dual Multiplexer
FIGURE 5-1:
Simplified Analog Input Multiplexer Schematic.
2020 Microchip Technology Inc.
DS20006391A-page 37
MCP3561/2/4R
The possible selections are described in Table 5-1 and
can be set with the MUX[7:0] register during the MUX
mode. The MUX[7:4] bits define the selection for the
VIN+ (noninverting analog input of the ADC). The
MUX[3:0] bits define the selection for the VIN- (inverting
analog input of the ADC).
TABLE 5-1:
ANALOG INPUT MUX DECODING
MUX[7:4] (VIN+) or
MUX[3:0] (VIN-) Code
Selected
Channel
0000
CH0
0001
CH1
0010
CH2
Not Connected (NC) for MCP3561R
0011
CH3
Not Connected (NC) for MCP3561R
0100
CH4
Not Connected (NC) for MCP3561R/MCP3562R
0101
CH5
Not Connected (NC) for MCP3561R/MCP3562R
0110
CH6
Not Connected (NC) for MCP3561R/MCP3562R
0111
CH7
Not Connected (NC) for MCP3561R/MCP3562R
1000
AGND
1001
AVDD
1010
Reserved
1011
REFIN+/OUT
1100
REFIN-
1101
TEMP Diode P
1110
TEMP Diode M
1111
Internal VCM
During SCAN mode, the two single-ended input multiplexers are automatically set to a certain position,
depending on the SCAN sequence and which channel
has been selected by the user. The SCAN sequence
channels’ configuration corresponds to a certain code
in the MUX[7:0] register, as defined in Table 5-15.
In order to monitor the digital power supply (DVDD), it is
necessary to connect DVDD externally to one of the
CHn analog inputs, since DVDD is not one of the possible selections of the analog multiplexer. A similar
setup can be implemented to monitor DGND if DGND is
not connected externally to AGND.
For MCP3561R and MCP3562R, some codes are not
available in the selection since the pins are not bonded
out on these devices. These codes should then be
avoided in the application, as the input they connect to
is effectively a high-impedance node.
The TEMP Diodes P and M are two internal diodes that
are biased by a current source and that can be used to
perform a temperature measurement. If TEMP Diode P
is connected to VIN+ and TEMP Diode M to VIN-, then
the ADC output code is a function of the temperature
using Equation 5-1 (see Section 5.1.2, Internal Temperature Sensor for more details). The VCM selection
measures the internal Common-mode voltage source
that biases the Delta-Sigma modulator (this voltage is
not provided at any output of the part).
DS20006391A-page 38
Comment
Do not use
Internal Common-mode voltage for modulator biasing
The possible inputs of the analog multiplexer include,
not only the analog input channels, but also REFIN+/inputs, AVDD and AGND, as well as temperature sensor
outputs and the VCM internal Common-mode. This
large selection offers many possibilities for measuring
internal or external data resources of the system and
can serve as diagnostic purposes to increase the
security of the applications. Some monitor channels
are already predefined in SCAN mode to further help
users to integrate diagnostics to their applications (for
example, the analog power supply or the temperature
can be constantly monitored in SCAN mode, see
Section 5.15.3 “SCAN Mode Internal Resource
Channels” for more details of the different resources
that can be monitored in SCAN mode).
Note:
When VREF_SEL = 0 (external VREF)
and REFIN+/OUT and REFIN- are
selected as analog inputs for the ADC, the
same REFIN+/OUT and REF- pin voltages are used as the reference for the
ADC. This diagnostic mode is useful for
determining the full-scale GAIN error of
the ADC when a GAIN setting of 1/3x or
1x is used.
2020 Microchip Technology Inc.
MCP3561/2/4R
5.1.1
BURNOUT CURRENT SOURCES
FOR SENSOR OPEN/SHORT
DETECTION
The ADC inputs, VIN-/VIN+, feature a selectable burnout current source, which enables open or short-circuit
detection, as well as biasing very low-current external
sensors. The bias current is sourced on the VIN+ pin of
the ADC (noninverting output of the analog multiplexer)
and sunk on the VIN- pin of the ADC (inverting output of
the analog multiplexer). Since the same current flows
at the VIN-/VIN+ pins of the ADC, it can sense the
impedance of an externally connected sensor that
would be connected between the selected inputs of the
multiplexer. When the sensor is in short circuit, the
ADC converts signals that are close to 0V. When the
sensor is an open circuit, the ADC converts signals that
are close to the AVDD voltage.
The current source is an independent peripheral of the
ADC. It does not need the ADC to be in Conversion
mode to be present. Once enabled, the source provides current even when the ADC is in reset or ADC
Shutdown mode. The current source can be configured
at any time through programming the CS_SEL[1:0] bits
in the CONFIG0 register (see Table 5-2).
Since the amount of current selected can be very small,
it may be necessary to diminish the MCLK master clock
frequency to be able to reach the full desired accuracy
during conversions (the settling time of the input
structure, including the sensor, can be large if the
sensor is very resistive, which will limit the bandwidth of
the Sample-and-Hold input circuit).
TABLE 5-2:
BURNOUT CURRENT
SOURCE SETTINGS
CS_SEL[1:0]
(Source/Sink)
Burnout Current
Amplitude
00
0 µA
01
0.9 µA
10
3.7 µA
11
15 µA
5.1.2
INTERNAL TEMPERATURE
SENSOR
The device includes an on-board temperature sensor,
which is made of two typical P-N junction diodes biased
by fixed current sources (TEMP Diode P and M). The
TEMP Diode P has a current density of 4x of the TEMP
Diode M.
The difference in the current densities of the diodes yields
a voltage that is a function of the absolute temperature.
Once the ADC inputs (VIN-/VIN+) are connected to the
temperature sensor diodes (MUX[7:0] = 0xDE), the
ADC will see a VIN differential input that is the function
of the temperature. The transfer function of the
temperature sensor can be approximated by a linear
equation or a third-order equation for more accuracy.
When the internal temperature sensor is selected for
the MUX or SCAN input, the input sink/source current
source, controlled by the CS_SEL[1:0] bits (see
Section 5.1, Analog Input Multiplexer), is disabled
internally (even though the CS_SEL[1:0] bits are not
modified by the temperature sensor selection). In this
case, the input current source is replaced by a specific
internal current source that will only be sourced to the
diode temperature sensor (see Figure 5-1).
The bias current of the diodes is not calibrated internally
and can lead to a relatively large gain and offset error in
the transfer function of the temperature sensor. Typical
graphs showing the typical error in the temperature
measurement are provided in Section 2.0, Typical
Performance Curves (see Figure 2-51 for first-order).
The accuracy can also be optimized by using proper
digital gain and offset error calibration schemes.
The accuracy of the current sources is on the order of
magnitude of ±20% and not very well controlled
internally. However, the mismatch between sink and
source is typically around ±1%.
This relatively low accuracy on the current is generally
sufficient for open/short detection applications.
Figure 2-53 shows how the ADC output code varies
when the burnout current sources are enabled (with
Gain = 1x) and the input sensor impedance is swept
with a large dynamic range. This allows the use of the
ADC as an open/short-detection circuit, which is
practical when manufacturing complex remote sensor
systems.
2020 Microchip Technology Inc.
DS20006391A-page 39
MCP3561/2/4R
EQUATION 5-1:
TEMPERATURE SENSOR TRANSFER FUNCTION
First-order (linear) fitting: Gain = 1, MCLK = 4.9152 MHz
TEMP (°C) = 4.0096 10(– 4) ADCDATA(LSB) VREF(V) – 269.13, where VREF = VREF+ – VREFVIN(mV) = 0.2973 TEMP (°C) + 80
5.1.3
ADC OFFSET CANCELLATION
ALGORITHM
The input multiplexer and the ADC include an offset
cancellation algorithm that cancels the offset contribution
of the ADC. This offset cancellation algorithm is
controlled by the AZ_MUX bit in the CONFIG2 register.
When AZ_MUX = 0 (default), the offset cancellation
algorithm is disabled and the conversions are not
EQUATION 5-2:
affected by this setting. When AZ_MUX = 1, the
algorithm is enabled. When the offset cancellation
algorithm is enabled, ADC takes two conversions, one
with the differential input as VIN+/VIN-, one with VIN+/VINinverted. Equation 5-2 calculates the ADC output code.
When AZ_MUX = 1, the Conversion Time, TCONV, is
multiplied by two, compared to the default case where
AZ_MUX = 0.
AZ_MUX CONVERSION RESULT
ADC Output at + VIN – ADC Output at -V IN
ADC Output Code (AZ_MUX = 1) = ------------------------------------------------------------------------------------------------------------------------2
This technique allows the cancellation of the ADC
offset error and the achievement of ultra-low offset
without any digital calibration. The resulting offset is the
residue of the difference between the two conversions,
which is on the order of magnitude of the noise floor.
This offset is effectively canceled at every conversion,
so the residual offset error temperature drift is
extremely low.
DS20006391A-page 40
For One-Shot mode, the conversion time is simply
multiplied by two. Enabling the AZ_MUX bit is not
compatible with the Continuous Conversion mode
(because it effectively multiplexes the inputs in
between each conversion). If AZ_MUX = 1 and
CONV_MODE = 11 (Continuous Conversion mode),
the device will reset the digital filter in between each
conversion, and will therefore, have an output data rate
of 1/(2 * TCONV). The Continuous mode is replaced by
a series of One-Shot mode conversions with no delay
in between each conversion (see Section 5.14 “Conversion Modes” and Figure 5-5 for more details about
the Conversion modes).
2020 Microchip Technology Inc.
MCP3561/2/4R
5.2
Input Impedance
This anti-aliasing filter can be a simple first-order RC
network with low time constant, which will provide a
high rejection at the DMCLK frequency (see Figure 5-6
for more details). The RC network usually uses small R
and large C to avoid additional offset due to IR drop in
the signal path. This anti-aliasing filter will induce a
small systematic gain error on the AC input signals that
can be compensated in the digital section with the
Digital Gain Error Calibration register (GAINCAL).
The ADC inputs (VIN+/VIN-) are directly tied to the
analog multiplexer outputs and are not routed to external pins. The multiplexer input stage contribution to the
input impedance is negligible.
The conversion accuracy can be affected by the input
signal source impedance when any external circuit is
connected to the input pins. The source impedance
adds to the internal impedance and directly affects the
time required to charge the internal sampling capacitor.
Therefore, a large input source impedance connected
to the input pins can increase the system performance
errors, such as offset, gain and Integral Nonlinearity
(INL). Ideally, the input source impedance should be
near zero. This can be achieved by using an operational amplifier with a closed-loop output impedance of
tens of ohms.
5.3
The gain of the converter is programmable and controlled by the GAIN[2:0] bits in the CONFIG2 register.
The ADC programmable gain is divided in two gain
stages: one in the analog domain, one in the digital
domain, as per Table 5-3.
After the multiplexer, the analog input signals are
routed to the Delta-Sigma ADC inputs and are
amplified by the analog gain stage (see Section 5.3.1
“Analog Gain” for more details). The digital gain stage
is placed inside the digital decimation filter (see
Section 5.3.2 “Digital Gain” for more details).
A proper anti-aliasing filter must be placed at the ADC
inputs. This will attenuate the frequency contents
around DMCLK and keep the desired accuracy over
the baseband (DRCLK) of the converter.
TABLE 5-3:
ADC Programmable Gain
DELTA-SIGMA ADC GAIN SETTINGS
GAIN[2:0]
Total Gain
(V/V)
Analog Gain
(V/V)
Digital Gain
(V/V)
Total Gain
(dB)
VIN Range (V)
±Min (AVDD, 3 * VREF)
0
0
0
0.333
0.333
1
-9.5
0
0
1
1
1
1
0
0
1
0
2
2
1
6
±VREF/2
0
1
1
4
4
1
12
±VREF/4
1
0
0
8
8
1
18
±VREF/8
1
0
1
16
16
1
24
±VREF/16
1
1
0
32
16
2
30
±VREF/32
1
1
1
64
16
4
36
±VREF/64
2020 Microchip Technology Inc.
±VREF
DS20006391A-page 41
MCP3561/2/4R
5.3.1
ANALOG GAIN
The gain settings from 0.33x to 16x are done in the
analog domain. This analog gain is placed on each ADC
differential input. Each doubling of the gain improves the
thermal noise due to sampling by approximately 3 dB,
which means the lowest noise configuration is obtained
when using the highest analog gain. The SNR, however,
is degraded, since doubling the gain factor reduces the
maximum allowable input signal amplitude by
approximately 6 dB.
If the gain is set to 0.33x, the differential input range
theoretically becomes ±3 * VREF. However, the device
does not support input voltages outside of the power
supply voltage range. If large reference voltages are
used with this gain, the input voltage range will be
clipped between AGND and AVDD, and therefore, the
output code span will be limited. This gain is useful
when the reference voltage is small and when the
input signal voltage is large.
The analog gain stage can be used to amplify very low
signals, but the differential input range of the
Delta-Sigma modulator must not be exceeded.
5.3.2
DIGITAL GAIN
When the gain setting is chosen from 16x to 64x, the
analog gain stays constant at 16x and the additional
gain is done in the digital domain by a simple shift and
round of the output code. The digital gain range is
between 1x and 4x.
The output noise is approximately unchanged (except
for the quantization noise, which is slightly decreased).
The SNR is thus degraded by 6 dB per octave from 16x
to 64x settings.
This digital gain is useful for scaling up the signals without using the host device (MCU) operations, but they
degrade the SNR and resolution (1 bit per octave), and
do not significantly improve the noise performance,
except for very large OSR settings.
5.4
5.4.1
Delta-Sigma Modulator
ARCHITECTURE
The Delta-Sigma ADC includes a second-order
modulator with a multibit DAC architecture. Its 5-level
quantizer is a Flash ADC composed of four
comparators with equally spaced thresholds and a
thermometer output coding. The proprietary 5-level
architecture ensures minimum quantization noise at
the outputs of the modulators without disturbing the
linearity or inducing additional distortion.
Unlike most multibit DAC architectures, the 5-level
DAC used in this architecture is inherently linear, and
therefore, does not degrade the ADC linearity and THD
performance.
The sampling frequency is DMCLK; therefore, the
modulator outputs are refreshed at a DMCLK rate.
DS20006391A-page 42
Figure 5-2 represents a simplified block diagram of the
Delta-Sigma modulator.
Delta-Sigma 2nd Order 5-Level Modulator
Quantizer
Differential Input
Voltage
(from Analog Mux)
Analog
2nd Order
Loop
Filter
4
5-Level Flash
ADC
Output
Bitstream
Thermometer Coding
(to Digital Filter)
5-Level DAC
Analog
FIGURE 5-2:
Block Diagram.
5.4.2
Digital
Simplified Delta-Sigma ADC
MODULATOR OUTPUT BLOCK
The modulator output option enables users to apply
their own digital filtering on the output bit stream. By
setting IRQ_MODE[1] = 1 in the IRQ register, the modulator output is available at the IRQ/MDAT pin, at
AMCLK rate and also through the ADCDATA register
(0x0) with DMCLK rate. With this configuration, the
digital decimation filter is disabled in order to reduce
the current consumption and no data ready interrupt is
generated on any of the IRQ mechanisms. The
IRQ/MDAT pin is never placed in high-impedance
during the Modulator Output mode.
Since the Delta-Sigma modulator has a 5-level output
given by the state of four comparators with thermometer coding, the output is represented using four bits,
each bit representing the state of the corresponding
comparator (see Table 5-4).
The comparator output bits are arranged serially at the
AMCLK rate on the IRQ/MDAT output pin (see
Figure 5-3).
This 1-bit serial bit stream is considered to be the same
one as it is produced by a 1-bit DAC modulator with a
sampling frequency of AMCLK. The modulator can
either be considered as a 5-level output at DMCLK rate
or as 1-bit output at AMCLK rate. These two representations are interchangeable. The MDAT outputs can,
therefore, be used in any application that requires 1-bit
modulator outputs. This application can be integrated
with an external sinc filter or more advanced decimation filters that are computed in the MCU or DSP
device.
When CLK_SEL[1:0] = 11 (internal oscillator with
external clock output), the AMCLK clock is present on
the MCLK pin. This configuration allows a correct
synchronization of the bit stream when the internal
oscillator is used as the master clock source.
When CLK_SEL[1:0] = 00, the modulator outputs are
also synchronized with the MCLK input but the ratio
between MCLK and AMCLK must to be taken into
account in the user applications to correctly retrieve the
desired bit stream.
2020 Microchip Technology Inc.
MCP3561/2/4R
The default value of the bit stream after a reset or a
power-up is ‘0011’; it is equivalent to a 0V input for the
ADC. After each ADC reset and restart (see
Section 5.16 “A/D Conversion Automatic Reset and
Restart Feature”), the bit stream output is also reset
and restarted, and the IRQ/MDAT is kept equal to logic
high during the two MCLK clock periods needed for the
synchronization. After these two clock periods, the bit
stream will be provided on the IRQ/MDAT pin and the
first value will be the default value.
TABLE 5-4:
DELTA-SIGMA MODULATOR
OUTPUT BIT STREAM CODING
COMP[3:0]
Code
Modulator
Output Code
(Decimal)
MDAT
Serial
Stream
Equivalent
VREF
Voltage
1111
+2
1111
+VREF
0111
+1
0111
+VREF/2
0011
0
0011
0
0001
-1
0001
-VREF/2
0000
-2
0000
-VREF
tD OMD AT tD OMD AT tD OMD AT tD OMD AT tD OMD AT
AMCLK
MDAT
(code = +2)
5.4.3
BOOST MODES
The Delta-Sigma modulator includes a programmable
biasing circuit in order to further adjust the power
consumption to the sampling speed applied through
the MCLK. This can be programmed through the
BOOST[1:0] bits in the CONFIG2 register. The
different BOOST settings are applied to the entire
modulator circuit, including the voltage reference
buffers. The settings of the BOOST[1:0] bits are
described in Table 5-5.
TABLE 5-5:
BOOST SETTINGS
DESCRIPTION
BOOST[1:0]
Bias Current
00
x0.5
01
x0.66
10
x1 (default)
11
x2
The maximum achievable Analog Master Clock
(AMCLK) speed, the maximum sampling frequency
(DMCLK) and the maximum achievable data rate
(DRCLK) are highly dependent on the BOOST[1:0] and
GAIN[2:0] settings. A higher BOOST setting allows the
circuit’s bandwidth to be increased and allows a higher
analog master clock rate which will then increase the
baseband of the input signals to be converted. The
digital gain (which is enabled at 32x and 64x gains) has
no influence on the achievable bandwidth.
A typical dependency of the bandwidth depending on
the gain for each BOOST setting combination is shown
from Figure 2-35 to Figure 2-38. Typically, a larger gain
setting requires a higher BOOST setting in order to
achieve the same bandwidth performance.
MDAT
(code = +1)
Figure 2-43 shows the behavior of the achievable
bandwidth at BOOST = 1x with AVDD corner cases.
Since the BOOST settings vary, the internal slew rate
of the modulator components, using a lower VREF
value, will improve the bandwidth if low BOOST settings are used and show a bandwidth behavior that is
too limited.
MDAT
(code = 0)
MDAT
(code = -1)
MDAT
(code = -2)
C OMP[3]
C OMP[2]
C OMP[1]
C OMP[0]
FIGURE 5-3:
MDAT Serial Outputs
Depending on the Modulator Output Code.
2020 Microchip Technology Inc.
DS20006391A-page 43
MCP3561/2/4R
5.5
Digital Decimation Filter
The decimation filter decimates the output bit stream of
the modulator to produce 24-bit ADC output data. The
decimation filter present in the device is a cascade of
two filters: a third-order sinc filter with a decimation
ratio of OSR3 (third-order moving an average of
3 x OSR3 values), followed by a first-order sinc filter
with a decimation ratio of OSR1, moving an average of
OSR values (third-order moving average of 3 x OSR3
values).
Figure 5-4 represents the decimation filter architecture.
OSR 1 = 1
Modulator
Output
(Thermometer
Coding)
SINC 3
SINC 1
4
OSR 3
OSR 1
Decimation
Filter
Output
ADC
Resolution
Decimation Filter
FIGURE 5-4:
Diagram.
Decimation Filter Block
The following equation is the transfer function of the
decimation filter:
EQUATION 5-3:
FILTER TRANSFER
FUNCTION
3
1 – z -OSR 3
1 – z -OSR 1 OSR 3
H z = -------------------------------------------- -----------------------------------------------------3
–
1
OSR
–
OSR 3 1 – z
3
OSR 1 1 – z
Where:
2 fj
z = exp ----------------------
DMCLK
The resolution (number of possible output codes
expressed in powers of two or in bits) of the digital
filter is 24-bit maximum for any OSR = OSR3 x OSR1
and data format choice. The resolution only depends
on the OSR through the OSR[3:0] settings in the
CONFIG1 register per Table 5-6. Once the OSR is
chosen, the resolution is fixed and the output code of
the ADC is encoded with the data format defined by
the DATA_FORMAT[1:0] setting in the CONFIG3
register.
DS20006391A-page 44
The transfer function of this filter has a unity gain at
each multiple of DMCLK. A proper anti-aliasing filter
must be placed at the ADC inputs. This will attenuate
the frequency contents around each multiple of
DMCLK and keep the desired accuracy over the baseband of the converter. This anti-aliasing filter can be a
simple first-order RC network with low time constant to
provide a high rejection at DMCLK frequency.
The conversion time is a function of the OSR settings
and the DMCLK frequency.
EQUATION 5-4:
CONVERSION TIME FOR
OSR = OSR3 x OSR1
T CONV = 3 OSR3 + OSR 1 – 1 OSR3 DMCLK
In One-Shot mode, each conversion is launched
individually, so the maximum data rate is effectively
1/TCONV if each conversion is launched with no delay.
The digital filter is reset in between each conversion.
However, due to the nature of the digital filter (which
memorizes the sum of the incoming bit stream), the
data rate at the filter output can be maximized if the
filter is never reset. Because of the internal resampling
of the digital filter, the output data rate can be equal to
DMCLK/OSR = DRCLK; this is the case in Continuous
mode. In this case, the first conversion still happens in
the TCONV time, as this is the settling time of the filter.
The subsequent conversions are pipelined and give
their output at a data rate of DRCLK. The Continuous
Conversion mode can optimize the data rate, while
consuming the same power as One-Shot mode, which
is advantageous in applications that require a continuous sampling of the analog inputs. The Continuous
mode is not compatible with multiplexing the inputs
(see Section 5.15 “SCAN Mode” for more details
about the Conversion mode settings in MUX and SCAN
modes).
Figure 5-5 shows the fundamental difference between
One-Shot mode and Continuous mode in a simplified
diagram.
2020 Microchip Technology Inc.
MCP3561/2/4R
Analog Input
Signal
One-Shot mode
Conversions are Serialized,
IRQ
Filter is Reset After Each
ADC
Conversion
Status
Group Delay: T CONV
Data Rate: 1/(TCONV)
Conversion1
Conversion2
Conversion3
TCONV
TCONV
TCONV
IRQ
ADC
Continuous mode
Status
Conversions are Pipelined,
Filter is Never Reset
Group Delay: TCONV
Data Rate: DRCLK
Conversion1
TCONV = Settling Time
1/DRCLK
Conversion2
T CONV
Conversion3
T CONV
FIGURE 5-5:
One-Shot Mode vs. Continuous Mode.
Since the converter is effectively doing two conversions
when the AZ_MUX bit is enabled, the conversion time
is equal to 2 * TCONV in this mode. As described in
Section 5.1.3 “ADC Offset Cancellation Algorithm”,
this selection is not compatible with the Continuous
Conversion mode, and therefore, the output data rate
is equal to 1/(2 * TCONV) in this mode.
When OSR is larger than 20480 for typical master clock
frequency, MCLK = 4.9152 MHz, the device includes
an additional 50/60 Hz rejection by aligning decimation
filter notches with a multiple of 50/60 Hz depending on
the OSR setting. The rejection band strongly depends
on the master clock accuracy and corresponds to a
first-order decimation filter rejection rate.
Table 5-6 summarizes the possible filter settings and
their associated Conversion Time, TCONV, as well as
their output data rate (DRCLK) in Continuous mode.
The high OSR settings can be used for applications
requiring very low noise and slow data rates.
2020 Microchip Technology Inc.
Figure 5-6 shows the frequency response of the decimation filter with default settings. Figure 5-7 represents
the frequency response of the filter with the highest
OSR settings and a line rejection at 60 Hz.
DS20006391A-page 45
MCP3561/2/4R
TABLE 5-6:
OVERSAMPLING RATIO AND SINC FILTER RELATIONSHIP
OSR
Total
OSR
ADC Resolution
in Bits
(No Missing
Codes)
Conversion
Time
(TCONV)
OSR[3:0]
OSR3
0 0 0 0
32
1
32
16
0 0 0 1
64
1
64
19
0 0 1 0
128
1
128
22
384/DMCLK
0 0 1 1
256
1
256
24
0 1 0 0
512
1
512
24
0 1 0 1
512
2
1024
24
0 1 1 0
512
4
2048
24
0 1 1 1
512
8
4096
24
1 0 0 0
512
16
8192
24
1 0 0 1
512
32
16384
24
1 0 1 0
512
40
20480
1 0 1 1
512
48
1 1 0 0
512
80
1 1 0 1
512
1 1 1 0
1 1 1 1
Data Rate in Continuous
Conversion Mode
Data Rate (Hz)
with MCLK =
4.9152 MHz
Fastest Data Rate (Hz)
with MCLK =
19.6608 MHz
96/DMCLK
38400
153600
192/DMCLK
19200
76800
9600
38400
768/DMCLK
4800
19200
1536/DMCLK
2400
9600
2048/DMCLK
1200
4800
3072/DMCLK
600
2400
5120/DMCLK
300
1200
9216/DMCLK
150
600
17408/DMCLK
75
300
24
21504/DMCLK
60
240
24576
24
25600/DMCLK
50
200
40960
24
41984/DMCLK
30
120
96
49152
24
50176/DMCLK
25
100
512
160
81920
24
82944/DMCLK
15
60
512
192
98304
24
99328/DMCLK
12.5
50
1
DS20006391A-page 46
2020 Microchip Technology Inc.
MCP3561/2/4R
FIGURE 5-6:
Decimation Filter Frequency Response (OSR = 256, PRE = 1:1, MCLK = 4.9152 MHz).
FIGURE 5-7:
Decimation Filter Frequency Response (OSR = 81920, PRE = 1:1,
MCLK = 4.9152 MHz).
2020 Microchip Technology Inc.
DS20006391A-page 47
MCP3561/2/4R
5.6
ADC Output Data Format
The ADC Output Data (ADCDATA) register is located at
the address: 0x0. The default length of the register is
24-bit (23-bit + sign).
Output data are calculated in the digital decimation
filter with a much larger resolution and rounded to the
closest LSb value.
EQUATION 5-5:
The rounding ensures a maximum 1/2 LSb error
instead of a simple truncation that ensures a 1 LSb
maximum error.
Equation 5-5 calculates the ADC output code as a
function of the input and reference signals for DC
inputs.
ADC OUTPUT CODE FOR DC INPUT (DATA_FORMAT[1:0] = 00)
V IN+ – VIN-
ADC_OUTPUT(LSb) = ----------------------------------------- 8,388,608 GAIN
V REF+ – VREF-
For AC sine wave inputs, the decimation filter transfer
function (see Equation 5-3) induces an additional gain
on the ADC output code, which depends on the input
frequency (roll-off of the decimation filter).
For any inputs, the VIN+/VIN- voltages are averaged out
during the whole conversion time as the ADC is an
oversampling converter.
00
ADC output format is set by the DATA_FORMAT[1:0]
bits in the CONFIG3 register. These bits define four
different possible formats for the ADC Data Output
register: three 32-bit formats and one 24-bit format for
the MCP3561/2/4R.
Figure 5-8 describes all possible data formats.
SGN + DATA[22:0]
SGN+ DATA[22:0]
01
0x00
10
SGN ext (8-bit)
DATA[23:0]
11
CH_ID[3:0] SGN ext (4-bit)
DATA[23:0]
FIGURE 5-8:
ADC Output Format Selection.
When DATA_FORMAT[1:0] = 0x, the ADC data are
represented on 24 bits (23-bit plus sign). The ADC
output code is represented with MSb first signed two’s
complement coding. With these two data formats, the
coding does not allow overrange; the equivalent analog
input range is [-VREF; +VREF – 1 LSb]. When
VIN * Gain > VREF – 1 LSb, the 24-bit ADC code
(SGN+DATA[22:0]) will saturate and be locked at
0x7FFFFF. When VIN * Gain < -VREF, the 24-bit ADC
code will saturate and be locked at 0x800000. Using
these data formats does not permit correctly evaluating
full-scale errors in case of a positive full-scale error.
DS20006391A-page 48
When DATA_FORMAT[1:0] = 00, the output register
shows
only
the
24-bit
value.
When
DATA_FORMAT[1:0] = 01, the output register is 32 bits
long and the output code is padded with additional
zeros on the last byte. The output code is left justified
in this case. This format is useful for 32-bit MCU
applications.
2020 Microchip Technology Inc.
MCP3561/2/4R
When DATA_FORMAT[1:0] = 1x, the ADC data are
represented on 25 bits. For these two data formats, the
output register is 32 bits long. With these two data
formats, the coding allows overrange; the equivalent
analog input range is [-2 x VREF, +2 x VREF – 1 LSb].
When VIN * Gain > 2VREF – 1 LSb, the 25-bit ADC code
(SGN+DATA[23:0]) will saturate and be locked at
0x0FFFFFF. When VIN * Gain < -2VREF, the 24-bit ADC
code will saturate and be locked at 0x1000000. Using
these data formats allows a correct evaluation of the
full-scale errors in case of a positive full-scale error,
since they allow inputs that can be greater than VREF or
less than -VREF.
The ADC accuracy is not maintained on the full
extended [-2 x VREF, +2 x VREF – 1 LSb] range, but only
on a smaller range, which is approximately equal to
±1.05 x VREF. This overrange can be useful in high-side
measurements and gain error cancellation algorithms.
The overrange-capable formatting on 25 bits is fully
compatible with the standard code locked formatting on
24 bits; both coding formats will produce the same
TABLE 5-7:
24-bit codes for the [-VREF; +VREF – 1 LSb] range and
the MSb on the 25-bit coding can be considered as a
simple Sign bit extension.
When DATA_FORMAT[1:0] = 10, the 25-bit
(24-bit + SGN) value is right justified. The first byte of
the 32-bit ADC output code will repeat the Sign bit
(SGN).
In DATA_FORMAT[1:0] = 11, the output code is similar
to the one in DATA_FORMAT[1:0] = 10. The only difference resides in the four MSbs of the first byte, which
are no longer repeats of the Sign bit (SGN). They are
the Channel ID data (CH_ID[3:0]) that are defined in
Table 5-15. This CH_ID[3:0] word can be used to verify
that the right channel has been converted to SCAN
mode and can serve easy data retrieval and logging
(see Section 5.15 “SCAN Mode” for more details
about the SCAN mode). In MUX mode, this 4-bit word
is defaulted to ‘0000’ and does not vary with the
MUX[7:0] selection. This format is useful for 32-bit
MCU applications.
DATA_FORMAT[1:0] = 0x (24-BIT CODING)
Equivalent Input Voltage
ADC Output Code (SGN + DATA[22:0])
Hexadecimal
Decimal
> VREF – 1 LSb
011111111111111111111111
0x7FFFFF
+8388607
VREF – 2 LSb
011111111111111111111110
0x7FFFFE
+8388606
1 LSb
000000000000000000000001
0x000001
+1
0
000000000000000000000000
0x000000
0
-1 LSb
111111111111111111111111
0xFFFFFF
-1
-VREF + 1 LSb
100000000000000000000001
0xFFFFFF
-8388607
< -VREF
100000000000000000000000
0x800000
-8388608
Hexadecimal
Decimal
TABLE 5-8:
DATA_FORMAT[1:0] = 1x (25-BIT CODING)
Equivalent Input Voltage
ADC Output Code (SGN + DATA[21:0])
> 2 VREF – 1 LSb
0111111111111111111111111
0x0FFFFFF
+16777215
2 VREF – 2 LSb
0111111111111111111111110
0x0FFFFFE
+16777214
VREF + 1 LSb
0100000000000000000000001
0x0800001
+8388609
VREF
0100000000000000000000000
0x0800000
+8388608
VREF – 1 LSb
0011111111111111111111111
0x07FFFFF
+8388607
VREF – 2 LSb
0011111111111111111111110
0x07FFFFE
+8388606
1 LSb
0000000000000000000000001
0x0000001
+1
0
0000000000000000000000000
0x0000000
0
-1 LSb
1111111111111111111111111
0x1FFFFFF
-1
-VREF + 1 LSb
1100000000000000000000001
0x1800001
-8388607
-VREF
1100000000000000000000000
0x1800000
-8388608
-VREF – 1 LSb
1011111111111111111111111
0x17FFFFF
-8388609
-2VREF + 1 LSb
1000000000000000000000001
0x1000001
-16777215
< -2 VREF
1000000000000000000000000
0x1000000
-16777216
2020 Microchip Technology Inc.
DS20006391A-page 49
MCP3561/2/4R
5.7
Internal/External Voltage
Reference
5.7.1
VOLTAGE REFERENCE
SELECTION
The voltage reference selection for the ADC is
controlled by the VREF_SEL bit in the CONFIG0
register, as shown in Table 5-9.
TABLE 5-9:
The REFIN- pin is set as an input, directly connected to
the VREF- input of the ADC. For a better noise immunity,
it is recommended to connect this pin to AGND externally when a single-ended voltage reference is used.
Figure 6-10 shows more details of the reference
selection and reference pins connections.
ADC VOLTAGE REFERENCE SELECTION
VREF_SEL
Reference Input/Output Pins
Description
REFIN- Pin
REFIN+/OUT Pin
0
External reference selected.
Internal reference buffer is shut
down.
Internal reference is only
generating the internal 1.2V
common-mode voltage for the
ADC.
VREF- Input
VREF+ Input
1
Internal reference selected with
2.4V buffered output.
VREF- Input
(should be tied to AGND)
Internal reference with 2.4V
buffered output.
REFINPAD
ADC VREFInput
REFIN+/OUT
PAD
ADC VREF+
Input
Chopped at DMCLK rate if AZ_VREF=1
VREF_SEL=0 Off
VREF_SEL=1 On
VREF_SEL
2x
+
VREF Buffer
1x
ADC Internal
VCM Voltage
+
Internal
Bandgap
Voltage
FIGURE 5-9:
DS20006391A-page 50
+
-
1.2V
VCM Buffer
Voltage Reference Selection Schematic.
2020 Microchip Technology Inc.
MCP3561/2/4R
When VREF_SEL = 0, the reference voltage is set to
external mode. The REFIN+/OUT pin becomes an
input. In this case, the REFIN+/OUT pad is directly tied
to the VREF+ input of the ADC. There is no input buffer
in the differential input voltage reference path in this
mode, so the external voltage reference should include
a buffer to be able to charge the internal voltage
reference sampling capacitors.
When VREF_SEL = 1, the REFIN+/OUT is internally
buffered to produce a 2.4V buffered reference voltage
at the VREF+ input of the ADC. Section 5.7.2 “Internal
Voltage Reference Buffer” details the architecture of
the voltage reference buffer.
In this mode the REFIN+/OUT pin becomes an output
and the reference voltage is generated internally.
The structure of the internal voltage reference is based
on a band gap voltage reference source, giving a 1.2V
output directly connected to a low-noise chopper buffer
configured with a gain of 2x to give a 2.4V output on the
REFIN+/OUT pad. The internal reference has a very
low typical temperature coefficient of 15 ppm/°C for
extended temperature range and 9 ppm/°C for industrial temperature range, allowing the ADC output codes
to have the least variation corresponding to the temperature ranges, since they are proportional to
(1/VREF).
2020 Microchip Technology Inc.
5.7.2
INTERNAL VOLTAGE REFERENCE
BUFFER
When VREF_SEL = 1, the voltage reference buffer is
enabled. It is only powered on when the ADC state is
in reset or in Conversion mode and is powered off in
Shutdown mode.
The buffer is designed to be able to drive the ADC
reference input that is sampling the reference voltage.
The REFIN- pin is not buffered and is connected
directly to the ADC inverting voltage reference input
(VREF-).
The offset induced by the buffer may slightly vary
between the two possible gain selections as well as its
temperature dependency and bandwidth, therefore it
has to be characterized separately. The buffer injects a
certain quantity of 1/f noise into the system, that can
be modulated with the incoming input signals and can
limit the SNR performance at higher OSR values
(OSR > 256).
To overcome this limitation, the buffer includes an
auto-zeroing algorithm that greatly reduces (cancels
out) the 1/f noise and cancels the offset value of the
reference buffer. As a result, the SNR of the system is
not affected by this 1/f noise component of the
reference buffer, even at maximum OSR values. This
auto-zeroing algorithm is performed synchronously
with the DMCLK, and can be enabled or disabled with
the AZ_VREF bit setting in the CONFIG2 register.
When AZ_VREF = 1 (Default), the auto-zeroing is
enabled, which cancels out the 1/f noise and
improves the SNR while not impacting the THD
performance. This mode is recommended for higher
OSR values (OSR 256).
When AZ_VREF = 0, the reference auto-zeroing
algorithm is disabled. This setting should be reserved
to lower OSR values, where higher ADC speed is
more important than accuracy.
If the application is susceptible to high frequency
noise, using AZ_VREF = 0 or a proper low pass filter
at the VREF output pin (to filter out the chopper
frequency components from the buffered output) is
recommended.
DS20006391A-page 51
MCP3561/2/4R
5.8
Power-on Reset
The analog and digital power supplies are monitored
separately by two Power-on Reset (POR) monitoring
circuits at all times, except during Full Shutdown mode
(see Section 5.10, Low-Power Shutdown Modes).
If the CS pin is kept logic low during a POR state, a
logic high pulse is necessary to start the first communication sequence after power-up. The CS rising edge
will reset the SPI interface properly and the falling edge
will clear the POR interrupt on the IRQ pin (see
Figure 6-15).
Each POR circuit has two separate thresholds, one for
the rising voltage supply and one for the falling voltage
supply. They both include hysteresis (the rising threshold is superior), so that the device is tolerant to a certain
degree of transient noise on each power supply.
The DVDD and AVDD monitoring thresholds are different
since their respective voltage ranges are different. The
AVDD rising threshold is approximately 1.75V ± 10% and
the DVDD is 1.2V ± 10%. The hysteresis is approximately
150 mV (typical).
If any of the two power supply voltages is below its
respective threshold, the POR state is forced internally.
In this state, the SPI interface is disabled, no command
can be executed by the chip. All registers are cleared
and set to their default values.
Proper decoupling ceramic capacitors (0.1 µF and
10 µF ceramic) should be placed as close as possible
to the power supply pins (AVDD, DVDD) to provide
additional transient immunity.
During Full Shutdown mode, the power supply voltages
are not monitored to be able to reach ultra-low power
consumption. The device cannot generate a POR
event interrupt in this mode, except for cases of
extremely
low-power
supply
voltages.
See
Section 5.10.1 “Full Shutdown Mode”.
At power-up, when both power supply voltages are
above the rising thresholds, the device powers up and
the SPI interface is enabled and can handle communications. Since both thresholds need to be crossed for
the power-up, the power-up sequence is not important
and any power supply voltage can ramp up first. The
detection time for the monitoring circuits (tPOR) is about
1 µs for relatively fast power-up ramp rates. The normal
operation stops when any of the falling thresholds of
the two POR monitoring circuits is crossed. Figure 5-10
illustrates the power-up and power-down sequences.
In order to ensure a proper power-up sequence, the
ramp rate of DVDD must not exceed 3V/µs when
coming out of the POR state.
Voltage
(AVDD, DVDD)
POR Threshold Up
POR Threshold Down
tPOR
Time
POR State
FIGURE 5-10:
DS20006391A-page 52
Normal Operation
POR State
Power-on Reset Timing Diagram.
2020 Microchip Technology Inc.
MCP3561/2/4R
5.9
ADC Operating Modes
The ADC can be placed into three different operating
modes: ADC Shutdown, Standby and Conversion. The
ADC operating mode is controlled by the user through
the ADC_MODE[1:0] bits in the CONFIG0 register. The
user can directly launch conversions or place the ADC
into ADC Shutdown or Standby mode by writing these
bits. Additional Fast commands are available for each
of the three possible states of these bits to allow faster
programming in case of time-sensitive applications
(see Section 6.2.4 “Command-Type Bits (CMD[1:0])”).
Table 5-10 describes the available ADC_MODE[1:0]
settings.
The ADC_MODE[1:0] bits do not give an instantaneous
representation of the ADC state. Writing the
ADC_MODE[1:0] bits sets the desired state of the
ADC, but this state is only attained after a start-up time
depending on the current state of the ADC (see
Section 5.11 “ADC Start-up Timer” for details about
the start-up timer). Typically, the device starts in ADC
Shutdown mode after a POR (ADC_MODE[1:0] = 00
by default). To launch conversions in the desired
configuration, the user should program the part in the
desired
configuration
and
then
set
the
ADC_MODE[1:0] bits to ‘11’. In this case, the first
conversion will start after TADC_SETUP = 256 DMCLK
periods. This time is necessary for the part to adjust to
the new programmed settings and settle in to its
operating point to accurately convert the input signals.
Internally, the device tracks the current state of the
ADC, as well as the start-up timer counter, to be able to
optimize the start-up time depending on the desired
transitions and internal configurations required, and set
by the user.
TABLE 5-10:
In MUX mode, overwriting the ADC_MODE[1:0] bits to
‘11’ when the ADC is already in conversion resets and
restarts the current conversion immediately. The
conversion start pulse will also be regenerated if the
EN_STP bit is enabled.
In SCAN mode (see Section 5.15 “SCAN Mode”),
writing the ADC_MODE[1:0] bits to ‘11’ starts the
conversion SCAN cycle. During the complete cycle,
even when the scan timer is enabled, reading the
ADC_MODE[1:0] bits gives a ‘11’ code output,
meaning that the SCAN cycle is ongoing. Rewriting
ADC_MODE[1:0] = 11 during SCAN mode will
immediately reset and restart the entire SCAN
sequence from the beginning of the sequence. The
conversion start pulse will also be regenerated if the
EN_STP bit is enabled. The restart of the SCAN
sequence may induce a TADC_SETUP additional delay if
the ADC is in ADC Shutdown mode when the
ADC_MODE bits are overwritten (this can happen if the
ADC_MODE bits are overwritten during the timer delay
period, where the ADC is placed into ADC Shutdown
mode in between two SCAN cycles).
The ADCDATA register is always updated with the last
conversion results. The ADCDATA register cannot
provide incomplete conversion results. The A/D
conversion must be completed to be able to provide a
result in the ADCDATA register. Each end of
conversion generates a data ready interrupt on all three
IRQ mechanisms (see Section 6.8.1 “Conversion
Data Ready Interrupt”). The ADCDATA register is
never cleared when the device transitions from one
mode to another. The only way to clear the ADCDATA
register is a POR event or a Full Reset Fast command
(see Section 6.2.5, Fast Commands Description).
ADC OPERATING MODES DESCRIPTION
ADC_MODE[1:0]
ADC Mode
Description
11
Conversion
The ADC is placed into Conversion mode and consumes the specified current. A/D conversions can be reset and restarted immediately once this
mode is effectively reached. This mode may be reached after a maximum of
TADC_SETUP time, depending of the current state of the ADC.
10
Standby
Conversions are stopped. ADC is placed into reset but consumes almost as
much current as in Conversion mode. A/D conversions can start immediately once this mode is effectively reached. This mode may be reached after
a maximum of TADC_SETUP time, depending of the current state of the ADC.
0x
ADC Shutdown
2020 Microchip Technology Inc.
Conversions are stopped. ADC is placed into ADC Shutdown mode and
does not consume any current. A/D conversions can only start after
TADC_SETUP start-up time. This mode is effective immediately after being
programmed.
DS20006391A-page 53
MCP3561/2/4R
5.10
Low-Power Shutdown Modes
The device incorporates two low-power modes that can
be activated in order to limit power consumption of the
device when ADC is not used. These two modes are
called Partial Shutdown and Full Shutdown modes.
5.10.1
FULL SHUTDOWN MODE
The Full Shutdown mode can only be enabled by
sending a Fast Command Full Shutdown (Fast
Command code: ‘1101’). Note that the execution of this
fast command forces the CONFIG0 to be set to 0x00
(no active block is enabled).
Full Shutdown mode is the lowest power mode of the
device. None of the circuits consuming static power are
active in this mode.
As stated in Section 5.8 “Power-on Reset”, the
AVDD/DVDD POR monitoring circuits are not active
while in Full Shutdown mode.
Note:
If the digital power supply resides for a
long time period below the POR threshold
and to a sufficiently low voltage (typically
below 0.6V0, some bits previously set to
‘1’ can toggle to ‘0’ and not be set
properly.In order to ensure a safe
operation after the full shutdown mode,
follow the sequence of commands:
- Write LOCK register to 0xA5
- Write IRQ register to 0x03
- Send a fast CMD full reset (1110)
- Reconfigure the chip as desired
This sequence ensures a recovery with
the desired settings in any loss-of-power
scenario.
The part can still be accessed through the SPI interface
during this mode and will accept incoming SPI
commands. The ADCDATA register is not cleared
TABLE 5-11:
Device
Low-Power Mode
during Full Shutdown mode and still holds previous
conversion results. The other register settings are not
modified or reset due to entering in Full Shutdown
mode.
The Full Shutdown mode stops all internal timers and
resets them. Sending a Fast CMD to change the
operating mode exits the Full Shutdown mode.
The user should place all digital inputs to a static value
(logic low or high) in order to optimize power
consumption during Full Shutdown mode. The current
consumption specifications during Full Shutdown
mode are intended without any digital pin toggling
during the measurement. In this case, only leakage
current is consumed throughout the device and this
current varies exponentially with respect to absolute
temperature.
5.10.2
PARTIAL SHUTDOWN MODE
Partial Shutdown mode is achieved when CONFIG0 is
set to ‘0000000x’. In this mode, most of the internal
circuits are shut down, with the exception of the POR
monitoring and internal biasing circuits. During the
Partial Shutdown mode, the power supply is
continuously monitored, whereas in Full Shutdown
mode, the POR monitoring circuits are powered down.
The power consumption is also much higher in Partial
Shutdown mode due to the POR monitoring circuits
being active. Partial Shutdown mode allows the device
to be restarted and put back in Conversion mode faster
than Full Shutdown mode. Table 5-11 describes the
differences between Partial and Full Shutdown modes.
If the current consumption of Partial Shutdown mode is
acceptable for the application, it is recommended that
it is used as an alternative to Full Shutdown mode
where the POR monitoring circuits are shut down and
no longer monitoring the AVDD and DVDD power
supplies.
LOW-POWER MODES(1)
CONFIG0[7]
VREF_SEL
Partial Shutdown
0
0
00
00
0x
All peripherals, except the
POR monitoring circuits and
clock biasing circuits, are shut
down and consume no static
current.The SPI interface
remains active in this mode
and consumes no current
while the bus is Idle.
Full Shutdown
0
0
00
00
00
All analog and digital circuits
are shut down and consume
no static current. The SPI
interface remains active in
this mode and consumes no
current while the bus is Idle.
Note 1:
CLK_SEL[1:0] CS_SEL[1:0] ADC_MODE[1:0]
Description
x = Don’t Care
DS20006391A-page 54
2020 Microchip Technology Inc.
MCP3561/2/4R
5.11
ADC Start-up Timer
The device includes an intelligent start-up timer circuit
for the ADC, which ensures that the ADC is properly
biased and that internal nodes are properly settled
before each conversion. This timer ensures the proper
conditions for the ADC to convert with its full accuracy
for each conversion.
The ADC can operate in three different modes: ADC
Shutdown, Standby and Conversion, as described in
Section 5.9 “ADC Operating Modes”. The ADC
start-up timer manages the time for the transitions
between each mode. These transitions can be
instantaneous or can take a maximum of 256 DMCLK
periods, depending on the type of transition, and the
current status of the ADC and of the internal start-up
timer.
The timer will always try to reduce the transition time
from one state to another, but will also allow enough
time for the internal circuitry to settle to the proper
internal operating points.
The transitions from Standby or Conversion mode to
ADC Shutdown mode are always immediate. They
reset the internal start-up timer to 256 DMCLK periods
(TADC_SETUP).
The transitions from ADC Shutdown to Standby or
Conversion mode start the internal start-up timer that
decrements from 256 to 0. The timer only decrements
after a small delay of two MCLK periods in case of a
transition caused by an SPI command. This small delay
is necessary to overcome any possible synchronization
issue between the two asynchronous clocks: MCLK
and SCK. The timer will immediately decrement
(without the synchronization delay) if the transitions are
generated by the internal state machine (for example,
when the transitions are generated by the SCAN
sequence). Once the timer reaches 0 (when the user
has clocked 256 DMCLK periods), the device reaches
its internal proper operating points and will either stay
in Standby mode (if ADC_MODE[1:0] = 10) or start the
Conversion mode (if ADC_MODE[1:0] = 11).
The transition from Standby to Conversion mode and
vice versa is immediate once the timer has reached 0
(if ADC_MODE[1:0] = 11). If the transition from
Standby to Conversion mode occurs, and if the timer
TABLE 5-12:
has not yet reached 0, the timer will continue to
decrement to 0 before effectively starting the
conversion. The timer cannot decrement faster than
256 DMCLK periods when the ADC transitions from
ADC Shutdown mode to Conversion mode (from ADC
Shutdown mode, the ADC is allowed 256 DMCLK
periods to power-up and settle to its desired operating
point before starting conversions). The start-up time
has been sized at 256 DMCLK clock periods for the
part to be able to settle in all conditions and with all
possible clock frequencies as specified.
Table 5-12 summarizes the behavior of the internal
start-up timer as a function of the ADC_MODE[1:0]
settings.
Rewriting ADC_MODE[1:0] bits without changing the
bit settings does not modify the internal timer and
cannot shorten the start-up delay necessary to start
accurate conversions. A synchronization delay of two
MCLK periods occurs after each rewrite if
ADC_MODE[1:0] = 1x.
In SCAN mode, when CONV_MODE[1:0] = 11 (Continuous mode), the ADC may be placed in ADC Shutdown
mode and restarted in between each SCAN cycle
depending on the TIMER[23:0] settings (see
Section 5.15.5 “Delay Between SCAN Cycles
(TIMER[23:0])”). If the TIMER register is programmed
with a decimal code greater than TADC_SETUP = 256,
the internal timer will automatically place the part in
ADC Shutdown mode at the end of the cycle and will
start to transition to the next cycle 256 DMCLK periods
before the end of the TIMER delay.
This lowers the power consumed during the TIMER
delay as much as possible. If the value of the TIMER
delay is less than 256 DMCLK periods, the part will not
enter ADC Shutdown mode and stay in Standby during
the TIMER delay (in this case the power consumed is
equivalent to the Conversion mode power consumption).
In order to catch the start of the conversion in case of
complex sequences of transitions, it can be useful to
enable the EN_STP bit so that the part will generate a
pulse on the IRQ pin to indicate a conversion start.
Figure 5-11 shows different cases of transitions
between modes and shows the internal state of the
start-up timer for each step.
ADC START-UP TIMER BEHAVIOR AS A FUNCTION OF ADC_MODE[1:0] SETTINGS
ADC_MODE[1:0]
ADC State
11
Conversion
10
Standby
0x
ADC Shutdown
2020 Microchip Technology Inc.
ADC Start-up Timer Behavior
The ADC start-up timer decrements to 0. The conversion
starts when it reaches 0.
The ADC start-up timer decrements to 0. The ADC is ready to
convert when it reaches 0.
ADC start-up timer is reset to TADC_SETUP = 256.
DS20006391A-page 55
MCP3561/2/4R
DMCLK
Continuous Clocking
SPI
Wri te
Wri te
Wri te
AD C _M ODE = 1x
AD C _M ODE = 0x
AD C _M ODE = 1x
0x
1x
0x
1x
Timer Reset
Switching Between ADC_MODE = 10 and 11
has no Effect on the Timer
ADC_MODE
Timer Reset
ADC Start-up
Timer Decimal
Code
Timer
Countdown
Wri te
1X
AD C _M ODE = 1x
256
ADC Ready to Convert
0
FIGURE 5-11:
5.12
ADC Start-up Timer Timing Diagram.
Master Clock Selection/Internal
Oscillator
The device includes three possible clock modes for the
master clock generation. The Master Clock (MCLK) is
used by the ADC to perform conversions and is also used
by the digital portion to generate the different digital
timers. The clock mode selection is made through the
CLK_SEL[1:0] bits located in the CONFIG0 register. The
possible selections are described in Table 5-13.
The master clock is not propagated in the chip when the
chip enters the Full Shutdown mode (see Section 5.10
“Low-Power Shutdown Modes”). Any change to the
CLK_SEL bits creates a reset and restart for the currently
running conversions and a restart of the ADC setup timer.
Each reset and restart resets all internal phases to their
default values and can lead to a possible temporary duty
cycle change at the clock output pin.
TABLE 5-13:
CLK_SEL[1:0]
CLOCK SELECTION BITS
Clock Mode
MCLK Pin
00 or 01
External clock
MCLK digital input
10
Internal RC
Oscillator,
no clock output
High-Z
11
Internal RC
Oscillator with
clock output
AMCLK digital
output
DS20006391A-page 56
5.12.1
EXTERNAL MASTER CLOCK MODE
(CLK_SEL[1:0] = 0x)
The External Clock mode is used to input the MCLK
clock necessary for the ADC conversions and can
accept duty cycles with a large range since the clock is
redivided internally to generate the different internal
phases.
The external clock can be provided on the MCLK pin for
the MCP3561/2/4R devices.
5.12.2
INTERNAL OSCILLATOR
The device includes an internal RC-type oscillator
powered by the digital power supply (DVDD/DGND). The
frequency of this internal oscillator ranges from
3.3 MHz to 6.6 MHz. The oscillator is not trimmed in
production, therefore, the precision of the center
frequency is approximately ±30% from chip to chip.
The duty cycle of the internal oscillator is centered
around 50% and varies very slightly from chip to chip.
The internal oscillator has no reset feature and keeps
running once selected.
2020 Microchip Technology Inc.
MCP3561/2/4R
5.12.3
INTERNAL MASTER CLOCK
MODES (CLK_SEL[1:0] = 1x)
When CLK_SEL[1] = 1, the internal oscillator is
selected and the master clock is generated internally.
The internal oscillator has no reset feature and
continues to run once selected. The master clock
generation is independent of the ADC as the clock can
still be generated even if the ADC is in ADC Shutdown
mode. The internal oscillator is only disabled when
CLK_SEL[1:0] = 0x. The clock can be distributed to the
dedicated output pin depending on the CLK_SEL[0] bit.
When the clock output is selected (CLK_SEL[0] = 1),
the AMCLK clock derived from the MCLK
(AMCLK = MCLK/PRESCALE) is available on the
output pin. The AMCLK output can serve as the clock
pin to synchronize the modulator output or other
MCP3561/2/4R devices that are configured with
CLK_SEL[1:0] = 00 or 01.
The AMCLK output is available on the MCLK clock
output pin as soon as the Write command
(CLK_SEL[1:0] = 11) is finished.
5.13
Digital System Offset and Gain
Calibrations
The MCP3561/2/4R devices include a digital calibration feature for offset and gain errors. The calibration
scheme for offset error consists of the addition of a
fixed offset value to the ADC output code (ADCDATA at
address: 0x0). The offset value added (OFFSETCAL)
is determined in the OFFSETCAL register (address:
0x9). The calibration scheme for gain error consists of
the multiplication of a fixed gain value to the ADCDATA
code. The gain value (GAINCAL) multiplied is
determined in the GAINCAL register (address: 0xA).
The digital offset and gain calibration schemes are
enabled or disabled via the EN_OFFCAL and
EN_GAINCAL control bits of the CONFIG3 register.
When both calibration control bits are enabled
(EN_OFFCAL = EN_GAINCAL = 1), the ADCDATA
register is modified with the digital offset and gain calibration schemes, as described in Equation 5-6. When
a calibration enable bit is off, its corresponding register
becomes a Don’t Care register and the corresponding
calibration is not performed.
2020 Microchip Technology Inc.
EQUATION 5-6:
ADCDATA OUTPUT
AFTER DIGITAL GAIN
AND OFFSET ERROR
CALIBRATION
ADCDATA (post-calibration) =
[ADCDATA (pre-calibration) + OFFSETCAL] x GAINCAL
The calculations are performed internally with proper
management of overloading, so that the overload
detection is done on the output result only and not on
the intermediate results. A sufficient number of additional overload bits are maintained and propagated
internally to overcome all possible overload and/or
overload recovery situations.
For example, if ADCDATA (pre-calibration) + OFFSETCAL
is out of bounds, but (ADCDATA (pre-calibration) +
OFFSETCAL) x GAINCAL is still in the right range
(possible with 0 < GAINCAL < 1), the result is not
saturated.
5.13.1
DIGITAL OFFSET ERROR
CALIBRATION
The Offset Calibration register (OFFSETCAL,
address: 0x9) is a signed MSb first, two’s complement
coding, 24-bit register that holds the digital offset
calibration value, OFFSETCAL. The OFFSETCAL
equivalent input voltage value is calculated with
Equation 5-7.
EQUATION 5-7:
OFFSETCAL
CALIBRATION VALUE
(EQUIVALENT INPUT
VOLTAGE)
OFFSETCAL (V) = VREF x (OFFSETCAL[23:0]
signed decimal code)/(8388608 x GAIN)
For the MCP3561/2/4R devices, the offset calibration
is done by adding the OFFSETCAL[23:0] calibration
value to the ADCDATA code bit-by-bit.
The offset calibration value range in equivalent voltage
is [-VREF/GAIN; (+VREF – 1 LSb)/GAIN], which can
cancel any possible offset in the ADC but also in the
system. The offset calibration is realized with a simple
24-bit signed adder and is instantaneous (no pipeline
delay). Enabling the offset calibration will affect the
next conversion result; the conversion result already
held in the ADCDATA register (0x0) is not modified
when the EN_OFFCAL is set to ‘1’, but the next one
will take the offset calibration into account. Changing
the OFFSETCAL register to a new value will not affect
the current ADCDATA value, but the next one (after a
data ready interrupt) will take the new OFFSETCAL
value into account. Figure 5-12 presents the different
cases and their impact on the ADCDATA register and
the IRQ output.
DS20006391A-page 57
MCP3561/2/4R
Wri te
OFFSE TCA L[2 3:0] = OFFSE TCA L1
SPI
ADC
STATUS
Data 2 Conversion
Data 3 Conversion
Data 4 Conversion
DATA0
DATA1
DATA2 + OFFSETCAL1
DATA3 + OFFSETCAL2
FIGURE 5-12:
ADC Output and IRQ Behavior with Digital Offset Calibration Enabled.
DIGITAL GAIN ERROR
CALIBRATION
The Gain Error Calibration register (GAINCAL,
address: 0xA) is an unsigned 24-bit register that holds
the digital gain error calibration value, GAINCAL.
Equation 5-8 calculates the GAINCAL multiplier.
EQUATION 5-8:
GAINCAL CALIBRATION
VALUE (MULTIPLIER
VALUE)
GAINCAL (V/V) = (GAINCAL[23:0] unsigned decimal
code)/8388608
For the MCP3561/2/4R devices, the gain error
calibration is done by multiplying the GAINCAL value
to the ADC output code.
The gain error calibration value range in equivalent
voltage is [0; 2-2-23], which can cancel any possible
gain error in the ADC and in the system. The gain
error calibration is made with a simple 24-bit
Wri te
GAIN C AL[2 3:0] = GAIN C AL1
SPI
ADC
STATUS
Wri te
OFFSE TCA L[2 3:0] = OFFSE TCA L2
Data 1 Conversion
IRQ
ADC DATA
REGISTER
VALUE
5.13.2
Wri te
EN _OFFC AL = 1
Data 1 Conversion
Wri te
EN _GAIN C AL = 1
add-and-shift circuit clocked on DMCLK and induces a
pipeline delay of TGCAL = 23 DMCLK periods. This
pipeline delay acts as a delay on the data ready
interrupt position that is shifted by TGCAL = 23 DMCLK
periods.
During this delay, the converter can process the next
conversion, the delay does not shift the next
conversion and does not change the Conversion Time,
TCONV. Enabling the gain error calibration will affect
the next conversion result; the conversion result
already held in the ADCDATA register (0x0) is not
modified when the EN_GAINCAL is set to ‘1’, but the
next one will take the offset calibration into account.
Changing the GAINCAL register to a new value will
not affect the current ADCDATA value, but the next
one (after a data ready interrupt) will take the new
GAINCAL value into account. Figure 5-13 shows the
different cases and their associated effects on the
ADCDATA register and the IRQ output.
Wri te
GAIN C AL[2 3:0] = GAIN C AL2
Data 2 Conversion
Data 3 Conversion
Data 4 Conversion
IRQ
ADCDATA
DATA0
DATA1
DATA2 x GAINCAL1
TGCAL
FIGURE 5-13:
DS20006391A-page 58
DATA3 x GAINCAL2
TGCAL
ADC Output and IRQ Behavior with Digital Gain Error Calibration Enabled.
2020 Microchip Technology Inc.
MCP3561/2/4R
5.14
Conversion Modes
The ADC includes several conversion modes that can
be selected through the CONV_MODE[1:0] bits located
in the CONFIG3 register. The ADC behavior, with
respect to these bits, depends on whether the ADC is
in MUX or SCAN mode. Table 5-14 summarizes the
possible configurations.
TABLE 5-14:
ADC CONVERSION MODES IN MUX OR SCAN MODES
CONV_MODE[1:0]
5.14.1
ADC Behavior (MUX Mode)
ADC Behavior
(SCAN Mode)
ADC_MODE[1:0] Bit Settings
0x
Performs a one-shot conversion Performs one complete
and automatically returns to
SCAN cycle and
ADC Shutdown mode.
automatically returns to
ADC Shutdown mode.
Returns to ‘0x’ after one
conversion (MUX mode) or one
SCAN cycle (SCAN mode).
10
Performs a one-shot conversion Performs one complete
and automatically returns to
SCAN cycle and
Standby mode.
automatically returns to
Standby mode.
Returns to ‘10’ after one
conversion (MUX mode) or one
SCAN cycle (SCAN mode).
11
Performs continuous
conversions.
Stays at ‘11’.
CONVERSION MODES IN MUX
MODE
In MUX mode, the user can choose between one-shot
and continuous conversions.
A one-shot conversion is a single conversion and takes
a certain Conversion Time, TCONV (or 2 x TCONV when
AZ_MUX = 1, see Section 5.1.3 “ADC Offset
Cancellation Algorithm”). Once this conversion is
performed, the part automatically returns to a Standby
or ADC Shutdown state, depending on the
CONV_MODE[1:0] bit settings. The Conversion mode
determined by the CONV_MODE[1:0] bits settings will
also affect the state of the ADC_MODE[1:0] as
described in Table 5-14.
The conversion can be preceded by a start-up time that
depends on the ADC state (see Section 5.11 “ADC
Start-up Timer”). In One-Shot mode, the ADC data
have to be read completely with the SPI interface for
the interrupt to be cleared on the IRQ pin (the IRQ pin
cannot be automatically cleared like in the Continuous
Conversion mode).
This mode is recommended for low-power, low
bandwidth applications, requiring a once in a while A/D
conversion.
2020 Microchip Technology Inc.
Performs continuous
SCAN cycles with
TIMER[23:0] delay
between each cycle.
In Continuous Conversion mode, the ADC is never
placed in Standby or ADC Shutdown mode and converts continuously without any internal reset. In this
mode, the output data rate of the ADC is defined by
DRCLK (see Figure 5-5). The digital decimation filter
induces a pipeline or group delay of TCONV for the first
data ready and is structured to give a continuous
stream of data at the DRCLK rate after this first data
(the internal registers of the filter are never reset in this
mode, thus the decimation filter acts as a moving average). Each data ready interrupt corresponds to a valid
and complete conversion that was processed through
the digital filter (the digital filter has no latency in this
respect). This mode allows a faster data rate than the
One-Shot mode, and is therefore, recommended for
higher bandwidth applications. The pipeline delay
should be carefully determined and adapted to the user
needs, especially in closed-loop, low-latency applications. This mode is recommended for applications
requiring continuous sampling/averaging of the input
signals. If AZ_MUX = 1, the Continuous Conversion
mode is replaced by a series of subsequent One-Shot
mode conversions with a reset in between each
conversion. This makes the group delay equal to
2 x TCONV and the data rate equal to 1/(2 x TCONV).
Figure 5-14 and Figure 5-15 detail One-Shot and
Continuous Conversion modes for MUX mode.
DS20006391A-page 59
MCP3561/2/4R
ADC Data Read can be
tDODR Performed During this Time
SPI
Wri te
C ONV _M OD E = 0x o r 10
MCLK
ADC_MODE
ADC
STATUS
___
IRQ
Wri te
ADC _M ODE = 11
Read ADC Data
Don’t Care
Continuous Clocking
Don’t Care
00
11
‘0x’ or ‘10’
Depending on CONV_MODE[1:0]
Partial Shut down
Start-up
Conversion
TA DC_ SET UP
TCONV
Conversion
Start
(Generates
Pulse if
EN_STP = 1)
FIGURE 5-14:
Partial Shutdown or Reset
Depending on CONV_MODE[1:0]
TS TP
IRQ is Cleared
at First SCK Falling Edge
After ADC Read Start
MUX One-Shot Conversion Mode Timing Diagram.
SPI
MCLK
ADC_MODE
ADC
STATUS
Read A DC
Data 1
Write
Write
CONV_ MOD E = 11 ADC _MODE = 11
Don’t Care
Continuous Clocking
00
11
Partial Shutdown
Start-up
Data 1 Conversion
Data 2
Conversion
Data 3
Conversion
T A DC_S E TUP
TCONV
1/DRCLK
1/DRCLK
IRQ
FIGURE 5-15:
DS20006391A-page 60
R ea d A DC
Data 2
T DRH
TDRH
MUX Continuous Conversion Mode Timing Diagram.
2020 Microchip Technology Inc.
MCP3561/2/4R
5.14.2
CONVERSION MODES IN SCAN
MODE
If CONV_MODE[1:0] = 11, the ADC runs in a SCAN
Cycle mode with a TIMER[23:0] delay between cycles.
Writing the CONV_MODE[1:0] bits with the SPI interface within a conversion does not create an internal
reset. It is recommended not to wait for the end of a
conversion to change the CONV_MODE[1:0] bits to the
desired value, but to change to the desired value just
after the data are ready to avoid possible glitches.
Figure 5-16 and Figure 5-17, respectively, detail the
ADC timing behavior in One-Shot and Continuous
Conversion modes when configured for SCAN mode
with N channels chosen among 16 SCAN possibilities.
In SCAN mode, the device takes one conversion per
channel and multiplexes the input to the next channel in
the SCAN sequence. Therefore, all conversions are
One-Shot mode conversions, no matter how the
CONV_MODE[1:0] bits are set. Each conversion takes
the same time, TCONV (or 2 x TCONV when AZ_MUX = 1,
see Section 5.1.3 “ADC Offset Cancellation
Algorithm”), to be performed. If CONV_MODE[1:0] = 00,
01 or 10, the SCAN cycle is executed once and then the
ADC is placed into Standby or ADC Shutdown mode.
SPI
Write
CONV_MODE = 0x/10
MCLK
Write
ADC_MODE = 11
Don’t Care
ADC
STATUS
Start-up Channel 1 Conversion Reset Channel 2 Conversion Reset
Channel N Conversion
(Last in Cycle)
TDLY_SCAN
TCONV
TADC_SETUP
TCONV
TDLY_SCAN
TCONV
IRQ
SCAN One-Shot Conversion Mode Timing Diagram.
Write
CONV_MODE = 11
Write
ADC_MODE = 11
Read ADC Data 1
Read ADC Data N-1
Don’t Care
ADC_MODE
ADC Shutdown or Reset
Depending on CONV_MODE
TDRH
TDRH
MCLK
ADC
STATUS
‘0x’ or ‘10’
Depending on CONV_MODE
11
ADC Shutdown
FIGURE 5-16:
Read ADC Data N
Continuous Clocking
00
ADC_MODE
SPI
Read ADC Data N-1
Read ADC Data 1
Read ADC Data1
(New Cycle)
Read ADC Data N
Continuous Clocking
00
11
TADC_SETUP
ADC Shutdown
Start-up Channel 1 Conversion Reset Channel 2 Conversion Reset
Channel N Conversion
(Last in Cycle)
TDLY_SCAN
TCONV
TADC_SETUP
IRQ
TCONV
TCONV
TDLY_SCAN
TDRH
ADC Shutdown or Reset
Depending on TIMER[23:0] Settings
TTIMER_SCAN
Start-up
Channel 2 Conversion
Channel 1 Conversion
Reset
(New Cycle)
(New Cycle)
TCONV
TDLY_SCAN
TDRH
TDRH
TCONV
TDRH
Start-up Time is Reduced to 0
if TTIMER_SCAN < 256 DMCLK
Periods
FIGURE 5-17:
SCAN Continuous Conversion Mode Timing Diagram.
2020 Microchip Technology Inc.
DS20006391A-page 61
MCP3561/2/4R
5.15
SCAN Mode
5.15.1
5.15.2
SCAN MODE PRINCIPLE
The ADC is, by default, in MUX mode at power-up. The
ADC enters SCAN mode as soon as one of the
SCAN[15:0] bits in the SCAN register is set to ‘1’. MUX
mode and SCAN mode cannot be enabled at the same
time. When SCAN[15:0] = 0x0000, SCAN mode is disabled and the part returns to MUX mode, where the
input channel selection is defined by the MUX[7:0] bits.
In SCAN mode, the device sequentially and
automatically converts a list of predefined differential
inputs (also referred to as input channels) in a defined
order. After this series of conversions, the ADC can be
placed in Standby or ADC Shutdown mode, or it can
wait a certain time in order to perform the same
sequence of conversions periodically.
The SCAN cycle conversions are effectively started as
soon as the ADC_MODE[1:0] bits are programmed
through the SPI interface to ‘11’ (direct Write or Fast
command, ADC reset and restart). After the
ADC_MODE[1:0] bits are set to ‘11’, they keep the same
value until the SCAN mode is completed or aborted.
This mode is useful for applications that require
constant monitoring of defined channels or internal
resources (like AVDD or VCM), and allow a minimal and
simplified communication.
When in SCAN mode, the MUX register (address: 0x6)
becomes a Don’t Care register.
Each SCAN[15:0] bit defines a possible input channel for
the SCAN cycle, which corresponds to a certain selection
of the analog multiplexer input channel and possibly a
certain predefined gain of the ADC. The SCAN cycle will
process and convert each channel that has been enabled
(SCAN[n] = 1) with a defined order of priority from MSb to
LSb (SCAN[15] to SCAN[0]). The list of channels with
their corresponding inputs is defined in Table 5-15.
SCAN mode includes a configurable delay between
each SCAN cycle, as well as a configurable delay
between each conversion within a SCAN cycle.
Each conversion within the SCAN cycle leads to a data
ready interrupt and to an update of the ADCDATA register as soon as the current conversion is finished. The
device does not include additional memory to retain all
SCAN cycle A/D conversion results. Therefore, each
result has to be read when it is available and before it
is overwritten by the next conversion result.
TABLE 5-15:
SCAN MODE ENABLE AND SCAN
CHANNEL SELECTION
When using DATA_FORMAT[1:0] = 11, each channel
conversion result in the SCAN sequence can be identified with a Channel ID (CH_ID[3:0]) code that will
appear in the 4 MSbs of the ADCDATA register output
value (Section 5.6 “ADC Output Data Format”). The
Channel ID indicates the channel that sends the output
data. Table 5-15 shows each possible Channel ID
value and its associated channel.
ADC CHANNEL SELECTION
SCAN[n]
Bit
Channel Name
15
OFFSET
14
13
VCM
AVDD
12
11
TEMP
Differential Channel D (CH6-CH7)
10
9
MUX[7:0]
Corresponding Setting
Specific ADC Gain
1111
0x88
None
1110
1101
0xF8
0x98
1x
0.33x
1100
1011
0xDE
0x67
1x
None
Differential Channel C (CH4-CH5)
Differential Channel B (CH2-CH3)
1010
1001
0x45
0x23
None
None
8
7
Differential Channel A (CH0-CH1)
Single-Ended Channel CH7
1000
0111
0x01
0x78
None
None
6
5
Single-Ended Channel CH6
Single-Ended Channel CH5
0110
0101
0x68
0x58
None
None
4
3
Single-Ended Channel CH4
Single-Ended Channel CH3
0100
0011
0x48
0x38
None
None
2
1
Single-Ended Channel CH2
Single-Ended Channel CH1
0010
0001
0x28
0x18
None
None
0
Note 1:
Channel ID
Single-Ended Channel CH0
0000
0x08
None
SCAN[11:9] and SCAN[7:2] are not available for MCP3561R. Writing these bits has no effect.
SCAN[11:10] and SCAN[7:4] are not available for MCP3562R. Writing these bits has no effect.
DS20006391A-page 62
2020 Microchip Technology Inc.
MCP3561/2/4R
5.15.3
5.15.3.1
SCAN MODE INTERNAL
RESOURCE CHANNELS
Analog Supply Voltage Reading
(AVDD)
During the conversion that reads AVDD in SCAN mode,
the multiplexer selection becomes 0x98 (AVDD-AGND),
which is equal to the analog power supply voltage.
Since AVDD is the highest voltage available in the chip,
when reading AVDD in SCAN mode, the gain of the
ADC is automatically set to 1/3x, which maximizes the
input full-scale range regardless of the GAIN[2:0] settings. This temporary internal configuration does not
change the register settings, it only impacts the gain of
the device during this conversion.
With this fixed 1/3x gain, the ADC can measure the
maximum specified analog supply voltage (AVDD = 3.6V)
with a reference voltage as low as 1.2V.
5.15.3.2
Offset Reading (OFFSET)
During the conversion that reads OFFSET in SCAN
mode, the differential MUX output is shorted to AGND
(internally). The Offset Reading varies from part to part,
and over AVDD and temperature. The reading of this
offset value can be used for the device offset calibration
or tracking of the offset value in applications.
There is no automatic offset calibration in the device,
so the user has to manually write the opposite (signed
value) of the offset measured into the OFFSETCAL
register to effectively cancel the offset on the
subsequent outputs.
5.15.3.4
5.15.4
DELAY BETWEEN CONVERSIONS
WITHIN A SCAN CYCLE (DLY[2:0])
While the ADC and multiplexer are optimized to switch
from one channel to another instantaneously, it may not
be the case of an application that requires additional
settling time to overcome the transition. The device can
insert an additional delay between each conversion of
the SCAN cycle.
The delay value is controlled by the DLY[2:0] bits
located in the SCAN register (SCAN[23:20]). See
Table 5-16.
TABLE 5-16:
Temperature Reading (TEMP)
During the conversion that reads TEMP in SCAN
mode, the multiplexer selection becomes 0xDE, which
enables the two temperature diode sensors at each
input of the ADC. During the temperature reading, the
ADC gain is automatically set to 1x regardless of the
GAIN[2:0] settings. This temporary internal configuration does not change the register setting, it only impacts
the gain of the device during this conversion.
5.15.3.3
The VCM reading is susceptible to the gain and offset
errors of the ADC, which should be calibrated to obtain
a precise internal Common-mode measurement.
VCM Reading (VCM)
During the conversion that reads VCM, the device
monitors the internal Common-mode voltage of the
device in order to ensure proper operation.
DELAY BETWEEN
CONVERSIONS WITHIN A
SCAN CYCLE
DLY[2:0]
Delay Value
(DMCLK Periods)
111
512
110
256
101
128
100
64
011
32
010
16
001
8
000
0
The delay is only added in between two conversions of
the same SCAN cycle. There is no delay added at the
end or the beginning of each SCAN cycle due to the
DLY[2:0] settings.
During this delay, the ADC is internally kept in Standby
mode (ADC_MODE[1:0] = 10 internally, but the
ADC_MODE[1:0] bits are always read as ‘11’ through
the SPI interface).
The analog multiplexer switches to the next selected
input at the end of each conversion (i.e., at the beginning of the added delay, so that the application has
additional time to settle properly).
The VCM voltage of the device should be located at
1.2V ± 2% to ensure proper accuracy. With this setting,
the internal multiplexer setting becomes 0xF8
(VCM – AGND). In order to properly measure VCM, the
reference voltage must be larger than 1.2V.
During the VCM reading, the gain of the ADC is set to 1x
regardless of the GAIN[2:0] settings. This temporary internal configuration does not change the register setting, it
impacts the gain of the device during this conversion.
2020 Microchip Technology Inc.
DS20006391A-page 63
MCP3561/2/4R
5.15.5
DELAY BETWEEN SCAN CYCLES
(TIMER[23:0])
During Continuous mode, SCAN cycles are processed
continuously, one after another, separated by a time
delay (TTIMER_SCAN), which is defined by the TIMER
register (address: 0x8) value. During this delay, the
ADC is automatically placed into a power-saving mode
(Standby or ADC Shutdown). The TTIMER_SCAN delay
offers better power efficiency for applications which run
a SCAN sequence periodically. Since the delay can be
very long, it allows synchronous applications with very
slow update rates without having to use an external
timer. The TIMER register defines the time,
TTIMER_SCAN, between cycles with a 24-bit unsigned
value going from 0 to 16777215 DMCLK periods.
Table 5-17 details the TIMER values with respect to the
TIMER[23:0] code.
TABLE 5-17:
TIMER DELAY VALUE
BETWEEN SCAN CYCLES
TIMER[23:0]
TTIMER_SCAN Delay
Value
(DMCLK Periods)
111111111111111111111111
16777215
111111111111111111111110
16777214
100000000000000000000000
8388608
000000000000000000000001
1
000000000000000000000000
0
The internal TIMER counter will decrement from the
TTIMER_SCAN value to 0 and launch the new SCAN cycle.
If the TTIMER_SCAN value is greater than TADC_SETUP
(256 DMCLK periods), the device will enter ADC
Shutdown mode (ADC_MODE is set to ‘00’ internally)
at each end of a SCAN cycle. When the internal TIMER
counter reaches 256, the device will start the ADC
during a TADC_SETUP time to be ready to convert when
the internal counter reaches 0.
If the TTIMER_SCAN value is less than TADC_SETUP, the
part will be placed in Standby mode between SCAN
cycles (ADC_MODE is set to ‘10’ internally).
ADC_MODE[1:0] bits in the CONFIG0 register can only
be read as ‘11’ by the SPI interface during the entire
SCAN cycle and between SCAN cycles.
5.16
A/D Conversion Automatic Reset
and Restart Feature
invalid data. Some register writes with the SPI interface
during a conversion will automatically reset and restart
the A/D conversion with the new settings.
The automatic reset and restart feature behavior
depends on the register bits that are written by the SPI
interface.
5.16.1
REGISTER BIT MODIFICATIONS
NOT CAUSING RESET/RESTART
The first group of bits will not generate any reset and
restart. This group is composed of all the unused bits, all
the read-only bits and some digital settings, such as
CONV_MODE[1:0], DATA_FORMAT[1:0], CRC_FORMAT,
EN_CRCCOM, IRQ_MODE[0], EN_FASTCMD,
EN_STP and LOCK[7:0] bits.
5.16.2
REGISTER BIT MODIFICATIONS
CAUSING IMMEDIATE
RESET/RESTART
The second group of bits generates a reset and a
restart. The reset is immediate, the restart is only valid
after a period of two MCLK periods (necessary to
handle the reset and ensures that the restart is
synchronous with the master clock). This group is composed of settings that do not induce an analog operating
point
change.
This
group
includes:
ADC_MODE[1:0], PRE[1:0], OSR[3:0], GAIN[2:0],
AZ_MUX, EN_OFFCAL, EN_GAINCAL, IRQ_MODE[1:0],
MUX[7:0] and DLY[2:0] bits. The EN_OFFCAL,
EN_GAINCAL and IRQ_MODE[1:0] bits generate the
reset and restart only if they are changed to a new
value. An overwrite of the same value has no effect. In
SCAN mode, the reset and restart feature will just
restart the current conversion for this group of bits; the
SCAN cycle is not modified and not restarted. The
MUX[7:0] bits can be changed within SCAN mode without generating a reset and a restart since this register
is a Don’t Care during SCAN mode. The DLY[2:0] bits
can be changed during the MUX mode without generating a reset and restart since these bits are Don’t Care
during the MUX mode. The OFFSETCAL[23:0] and
GAINCAL[23:0] only generate a reset and a restart
when written if their corresponding enable bit
(EN_OFFCAL, EN_GAINCAL) is enabled.
The ADC_MODE[1:0] bits generate an immediate
reset and restart but only if they are overwritten with
‘11’ (in any other case, the conversions are stopped).
Depending on the part being in MUX or SCAN mode,
the reset and restart feature will reset the conversion
or the complete SCAN cycle.
When the A/D conversions are running, the user can
change the device configuration through the SPI interface by writing any register. Some register settings
directly impact the conversion results and lead to
invalid ADC data if they are changed within a conversion. The device incorporates an automatic reset and
restart feature for the A/D conversions to avoid these
DS20006391A-page 64
2020 Microchip Technology Inc.
MCP3561/2/4R
5.16.3
REGISTER BIT MODIFICATIONS
CAUSING DELAYED
RESET/RESTART
A third group of bits will generate a reset and a restart
that induce a new start-up delay (TADC_SETUP), so that
the internal analog operating points can be settled with
the new settings before the new conversion is started.
The reset is immediate; the start-up timer is only
restarted after a period of two MCLK periods (necessary
to handle the reset and to ensure that the restart is synchronous with the master clock). Overall, the delay from
the reset to the actual restart of the conversion with the
new settings is then 2 MCLK + TADC_SETUP. This group
includes: CONFIG0 and the RESERVED registers at
addresses 0xB and 0xC. The CONFIG0 bits induce a
start-up timer delay only if they are changed to a new
value. If they are overwritten with the same value, they
will generate an immediate reset and restart. In SCAN
mode, the reset and restart feature will just restart the
current conversion for this group of bits, the SCAN
cycle is not modified and not restarted.
This third group of bits will induce a start-up timer delay,
even when ADC_MODE[1:0] = 10 or if the ADC is in
Standby mode.
Depending on the phase between the AMCLK and the
SPI commands, the 2-MCLK delay can turn into a
4-MCLK delay to ensure the proper synchronization of
the device. If very precise synchronization is required,
it is recommended to not change the register configurations (i.e., not during conversions) or to use the
EN_STP = 1 setting so that the start of the conversions
can be clearly determined.
In MUX mode, the TIMER and SCAN registers do not
generate a reset and restart when written, except if the
SCAN register is modified to effectively enter in SCAN
mode. In this case, the MUX mode is superseded by
the SCAN mode immediately.
In SCAN mode, a write access of the SCAN register,
during or between conversions within the SCAN cycle,
will create a reset and restart of the whole SCAN
sequence. Within the same conditions, a write access
on the TIMER register will not create a reset and restart
of the entire SCAN sequence. However, during the
TTIMER_SCAN delay between SCAN cycles, a write on
the SCAN register does not generate a reset and a
restart of the entire sequence. Within the same conditions, a write on the TIMER register generates a reset
and a restart of the entire sequence.
During the reset and restart sequence, the reset is
immediate and resets the internal phases to the original
state, which can lead to a discontinuity in the clock output frequency if the AMCLK clock output is enabled.
The restart is synchronous with the AMCLK generation
and is effective only after two MCLK periods. The restart
also generates a conversion start pulse (only after the
two MCLK periods or the 2 MCLK + TADC_SETUP necessary for the restart) if enabled, for the user to be able to
align the system with the exact start of the new
conversion.
2020 Microchip Technology Inc.
DS20006391A-page 65
MCP3561/2/4R
NOTES:
DS20006391A-page 66
2020 Microchip Technology Inc.
MCP3561/2/4R
6.0
SPI SERIAL INTERFACE AND
DEVICE OPERATION
6.1
Overview
The MCP3561/2/4R devices use an SPI interface to
read and write the internal registers. The device
includes a four-wire (CS, SCK, SDI, SDO) serial SPI
interface that is compatible with SPI Modes 0,0 and
1,1. Data are clocked out of the device on the falling
edge of SCK and data are clocked into the device on
the rising edge of SCK. In these modes, the SCK clock
can Idle either high (1,1) or low (0,0). The digital interface is asynchronous with the MCLK clock that controls
the ADC sampling and digital filtering. All digital input
pins are Schmitt Triggered to avoid system noise perturbations on the communications. The SPI interface is
maintained in a reset state during POR.
Each SPI communication starts with a CS falling edge
and stops with the CS rising edge. Each SPI communication is independent. When CS is logic high, SDO is
in high-impedance, the transitions on SCK and SDI
have no effect. Changing from SPI Mode 1,1 to an SPI
Mode 0,0 and vice versa is possible and must be done
while the CS pin is logic high. Any CS rising edge clears
the communication and resets the SPI digital interface.
See Figure 1-1 for the SPI timing details.
The MCP3561/2/4R digital interface is capable of
handling various Continuous Read and Write modes,
which allows for ADC data streaming or full register
map writing within only one communication (and therefore, with only one unique command byte). It also
includes single byte Fast commands. The device does
not include a Master Reset pin, but it includes an SPI
Fast command to be able to fully reset the part at any
time and place it back in a default configuration.
The device family also includes advanced security
features to secure communication and alert users of
unwanted Write commands that change the desired
configuration. To secure the entire configuration, the
device includes an 8-bit lock code (LOCK[7:0]), which
blocks all Write commands to the full register map if the
value of the lock code is not equal to a defined password (0xA5). The user can protect its configuration by
changing the LOCK[7:0] value to 0x00 after full
programming, so that any unwanted Write command
will not result in a change in the configuration. Each SPI
read communication can be secured through a selectable CRC-16 checksum provided on the SDO pin at the
end of every communication sequence. This checksum
computation is compatible with the DMA CRC hardware of the PIC24 and PIC32 MCUs, as well as many
other MCU references, resulting in no additional
overhead for the added security.
processed through a CRC-16 calculation engine and
give a CRC-16 checksum that depends on the configuration. This checksum is readable from the CRC
register and updated when MCLK is running. If there is
a change in the checksum, a CRC interrupt generates
a flag to warn the user that the configuration has been
corrupted.
The MCP3561/2/4R devices also include additional
digital signal pins, such as a dedicated IRQ interrupt
output pin and a Master Clock (MCLK) input/output pin,
which allow easier synchronization and faster interrupt
handling, facilitating the implementation of the device in
many different applications.
6.2
SPI Communication Structure
The MCP3561/2/4R interface has a simple communication structure. Every communication starts with a CS
falling edge and stops with a CS rising edge.
The communication is always started by the
COMMAND byte (8 bits) clocking on the SDI input. The
COMMAND byte defines the command that will be
executed by the digital interface. It includes the device
address, the register address bits and the
command-type bits.
The COMMAND byte is typically followed by data bytes
clocked on SDI if the command type is a write and on
SDO if the command type is a read. The COMMAND
byte can also define a Fast command, and in this case,
it is not followed by any other byte. The following subsections detail the COMMAND byte structure and all
possible commands.
During the COMMAND byte clocking on SDI, a
STATUS byte is also propagated on the SDO output to
enable easy polling of the device status. During this time,
the interface is full-duplex, but the part can still be used
by MCUs handling only half-duplex communications if
the STATUS byte is ignored.
6.2.1
COMMAND BYTE STRUCTURE
The COMMAND byte fully defines the command that
will be executed by the part. This byte is divided into
three parts: the device address bits (CMD[7:6]), the
command address bits (CMD[5:2]) and the
command-type bits (CMD[1:0]). See Table 6-1.
TABLE 6-1:
COMMAND BYTE
CMD[7] CMD[6] CMD[5] CMD[4] CMD[3] CMD[2] CMD[1] CMD[0]
Device Address
Bits
Register Address/Fast Command
Bits
Command Type
Bits
Once the part is locked (write-protected), an additional
checksum calculation also runs continuously in the
background to ensure the integrity of the full register
map. All writable registers of the register map are
2020 Microchip Technology Inc.
DS20006391A-page 67
MCP3561/2/4R
6.2.2
DEVICE ADDRESS BITS (CMD[7:6])
The SPI interface of the MCP3561/2/4R devices is
addressable, which means that multiple devices can
communicate on the same SPI bus with only one Chip
Select line for all devices. Each device communication
starts by a CS falling edge, followed by the clocking of
the device address (CMD[7:6]). Each device contains
an internal device address which the device can
respond to.
This address is coded on two bits, so four possible
addresses are available. Device address is hard-coded
within the device and should be determined when
ordering the device. The device address is part of the
device markings to avoid potential confusion (see
Sections 9.1 “Package Marking Information(1)”).
When the CMD[7:6] bits match the device address, the
communication will proceed and the part will execute
the commands defined in the control byte and its
subsequent data bytes.
When the CMD[7:6] bits do not correspond to the
address hard-coded in the device, the command is
ignored. In this case, the SDO output will become
high-impedance, which prevents bus contention errors
when multiple devices are connected on the same SPI
bus (see Figure 6-2). The user has to exit from this
communication through a CS rising edge to be able to
launch another command.
TABLE 6-2:
6.2.3
COMMAND ADDRESS BITS
(CMD[5:2])
The COMMAND byte contains four address bits
(CMD[5:2]) that can serve two purposes. In case of a
register write or read access, they define at which
register address the first read/write is performed. In
case of a Fast command, they determine which Fast
command is executed by the device.
In case of a Write command on a read-only register, the
command is not executed and the communication
should be aborted (CS rising edge) to place another
command. All registers can be read; there is no
undefined address in the register map.
6.2.4
COMMAND-TYPE BITS (CMD[1:0])
The last two bits of the COMMAND register byte define
the command type. These bits are an extension of the
typical read/write bits present in most SPI communication protocols. The two bits define four possible
command types: Incremental Write, Incremental Read,
Static Read and Fast command. Changing the command type within the same communication (while CS is
logic low) is not possible. The communication has to be
stopped (CS rising edge) and restarted (CS falling
edge) to change its command type. The list of possible
commands, their type and their possible command
addresses are described in Table 6-2.
COMMAND TYPES TABLE
CMD[5:2]
CMD[1:0]
Command Description
0xxx
00
Don’t Care
100x
00
Don’t Care
1010
00
ADC Conversion Start/Restart Fast Command (overwrites ADC_MODE[1:0] = 11)
1011
00
ADC Standby Mode Fast Command (overwrites ADC_MODE[1:0] = 10)
1100
00
ADC Shutdown Mode Fast Command (overwrites ADC_MODE[1:0] = 00)
1101
00
Full Shutdown Mode Fast Command (overwrites CONFIG0[7:0] = 0x00 and
places the part in Full shutdown Mode)
1110
00
Device Full Reset Fast Command (resets the entire register map to default value)
1111
00
Don’t Care
ADDR
01
Static Read of Register Address, ADDR
ADDR
10
Incremental Write Starting at Register Address, ADDR
ADDR
11
Incremental Read Starting at Register Address, ADDR
DS20006391A-page 68
2020 Microchip Technology Inc.
MCP3561/2/4R
6.2.5
FAST COMMANDS DESCRIPTION
There are five possible Fast commands available for
the MCP3561/2/4R devices. For each command, only
the COMMAND byte has to be provided on the SPI port
and the command is executed right after the COMMAND byte has been clocked. The Fast command
codes are detailed in Table 6-2. All undefined
command address codes for Fast commands will be
ignored and will have no effect. SDO will stay in
high-impedance after the COMMAND byte for a Fast
command until a CS rising edge is provided. The Fast
commands can be enabled or disabled by placing the
EN_FASTCMD bit in the IRQ register to ‘1’ (default).
Disabling Fast commands can increase the security of
the device because it can avoid the execution of
unwanted Fast commands, which can be useful in
harsh environments.
The ADC Start/Restart command (command address:
‘1010’) overwrites the ADC_MODE[1:0] bits to ‘11’,
creating a conversion start (or a restart if the
conversion was already running).
The ADC Standby mode command (command
address: ‘1011’) overwrites the ADC_MODE[1:0] bits
to ‘10’ and places the ADC in Standby mode.
The ADC Shutdown mode command (command
address: ‘1100’) overwrites the ADC_MODE[1:0] bits
to ‘00’ and places the ADC in ADC Shutdown mode.
The Full Shutdown mode command (command
address: ‘1101’) overwrites the CONFIG0 register to
0x00 and places the device in Full Shutdown mode
(see Section 5.10 “Low-Power Shutdown Modes”
for a full description of this mode).
The Full Reset command (command address: ‘1110’)
resets the device and places the entire register map
into its default state condition, including the non writable registers. The only difference with a POR event is
that the POR_STATUS bit in the IRQ register is set to
‘1’ after a Full Reset and is reset to ‘0’ after a POR
event. The user can only clear the ADC Data Output
register to its default value by using the Full Reset
command.
6.2.6
DEVICE ADDRESS AND STATUS
BYTE DURING CONTROL BYTE
During the COMMAND byte clocking on the SDI pin,
the SDO pin displays a STATUS byte to help the user
retrieve quick interrupt status information.
The STATUS byte structure is described in Figure 6-1.
STAT[7]
STAT[6]
STAT[5]
STAT[4]
STAT[3]
STAT[2]
STAT[1]
STAT[0]
0
0
DEV_ADDR
[1]
DEV_ADDR
[0]
DEV_ADDR
[0]
DR_ST ATUS
CRCCFG_
ST ATUS
POR_ST ATUS
Device Address
Acknowledge bits
FIGURE 6-1:
Interrupt Status bits
STATUS Byte.
The first two bits are always equal to ‘0’ and SDO
toggles to ‘0’ as soon as a CS pin falling edge is performed. This allows having an application with multiple
devices, with different device addresses, sharing one
common SPI bus and avoiding bus contention during
STATUS byte clocking.
The next three bits of the STATUS byte give a confirmation (Acknowledge) of the hard-coded device address.
If the device address of the command byte and the
internal device address of the chip match, these three
bits will be transmitted and they are equal to:
• STAT[5:4] = DEV_ADDR[1:0]
• STAT[3] = DEV_ADDR[0]
The STAT[3] bit allows the user to distinguish the SDO
output from a High-Impedance state (device address
not matched), as the bits, STAT[4] and STAT[3], are
complementary and will induce a deterministic toggle
on the SDO output.
If the two device address bits are not matched with the
internally hard-coded device address bits, SDO is
maintained in a High-Impedance state during the rest
of the communication and the command is ignored.
This behavior avoids potential bus contention errors if
multiple devices with different device addresses share
the same SPI bus. After the transmission of the first two
bits, only one device responds to the command (all
other devices with non-matching device addresses
keep the SDO in high-impedance). In this case, the
user needs to abort the communication (CS rising
edge) in order to perform another command.
The three LSbs of the STATUS byte are the three
Interrupt Status bits:
• STAT[2] = DR_STATUS (ADC data ready interrupt
status)
• STAT[1] = CRCCFG_STATUS (CRC checksum
error on the register map interrupt status)
• STAT[0] = POR_STATUS (POR interrupt status)
The STATUS byte allows fast polling of the different
interrupts without having to read the IRQ register. However, it requires an MCU that can communicate in
Full-Duplex mode (SDI and SDO are clocked at the
same time). For MCUs that are only half-duplex, and
for devices that do not incorporate a separate IRQ pin,
or for applications that do not connect the existing IRQ
pin, the polling of the IRQ status can still be done by
reading the IRQ register continuously.
2020 Microchip Technology Inc.
DS20006391A-page 69
MCP3561/2/4R
These three Interrupt Status bits are independent of the
two other interrupt mechanisms (IRQ pin and IRQ
register) and are cleared each time the STATUS byte is
fully clocked. This enables the polling on the STATUS
byte as a possible interrupt management solution without requiring to connect the IRQ pin in the system. All
Status bit values are latched together just after the
device address has been correctly recognized by the
chip. Any interrupt happening after the two first Status
bits have been clocked out will appear in the STATUS
byte of the subsequent communication sequence.
Figure 6-2 represents the beginning of each
communication with both COMMAND and STATUS
bytes depicted. After the STATUS byte is propagated,
the SDO pin will be placed in high-impedance for Fast
commands or Write commands and will transfer data
bytes for Read commands as long as the CS pin stays
logic low.
Device Latches SDI on Rising Edge
CS
Device Latches SDO on Falling Edge
SPI Mode 1,1
SCK
SDO
High-Z
Device Address
does not Match
CMD[7:6]
CMD[0]
CMD[1]
CMD[2]
CMD[3]
Device
Address ACK
DR_
STATUS
0
CMD[6]
Device Address
Matches CMD[7:6]
CMD[6]
High-Z
CMD[7]
SDO
Command
Type
Register
Address
CRCREG_
STATUS
POR_
STATUS
Device
Address
CMD[4]
CMD[5]
Don’t Care
CMD[6]
SDI
CMD[7]
SPI Mode 0,0
Interrupts
Status
High-Z
0
FIGURE 6-2:
SPI Communication Start (COMMAND on SDI and STATUS on SDO) when the
Device Address Matches/Does Not Match CMD[7:6].
DS20006391A-page 70
2020 Microchip Technology Inc.
MCP3561/2/4R
6.3
Writing to the Device
When the command type is Incremental Write
(CMD[1:0] = 10), the device enters Write mode and
starts writing the first data byte to the address given in
the CMD[5:2] bits.
CONFIG0 (0x1)
CONFIG1 (0x2)
CONFIG2 (0x3)
After the STATUS byte has been transferred, SDO
stays in a High-Impedance state during an Incremental
Write communication. Writing to a read-only address
(such as addresses 0x0 or 0xF) has no effect and does
not increment the Address Pointer. The user must stop
the communication and restart a communication with a
COMMAND byte pointing to a writable address (0x1 to
0xD).
CONFIG3 (0x4)
IRQ (0x5)
MUX (0x6)
SCAN (0x7)
TIMER (0x8)
Each register is effectively written after receiving the
last bit for the register (SCK last rising edge). Any CS
rising edge during a write communication aborts the
current writing. In this case, the register being written
will not be updated and will keep its old value.
OFFSETCAL (0x9)
GAINCAL (0xA)
Reserved (0xB)
The registers may need 8, 16 or 24 bits to be effectively
written, depending on their address (see Table 8-1).
After each register is written, the Address Pointer is
automatically incremented as long as CS stays logic
low. When the Address Pointer reaches 0xD, the next
register to be written is the 0x1 register (see Figure 6-3
for a graphical representation of the address looping).
Internal registers located at addresses, 0xB, 0xC and
0xE, should be kept to their default state at all times for
proper operation. These are reserved registers and
should not be modified.
Reserved (0xC)
LOCK (0xD)
Reserved (0xE)
FIGURE 6-3:
Incremental Write Loop.
The Incremental Write feature can be used in order to
fully configure the part using a unique communication
which can save time in the application. This unique
communication can end at address 0xD so that the
user can also lock the configuration when written,
providing additional security in the application (see
Sections 6.6 “Locking/Unlocking Register Map
Write Access”).
Figure 6-4 shows an example of a write communication
in detail with a single register write. Figure 6-5 shows an
example of an Incremental Write communication.
2020 Microchip Technology Inc.
DS20006391A-page 71
MCP3561/2/4R
CS
Device Latches SDI on Rising Edge
DATA
DATA
DATA
DATA
DATA
DATA
DATA
DATA
DATA
DATA
DATA
DATA
DATA
DATA
DATA
DATA
DATA
DATA
0
POR _
STA TUS
DATA
1
C RC R EG_
STA TUS
DATA
CMD
D R_
STA TUS
DATA
CMD
CMD
DATA
DATA
CMD
0 0
0
DATA
CMD
High-Z
CMD
SDO
CMD
Don’t care
CMD
SDI
CMD
SCK
Don’t care
High-Z
SPI Mode 0,0; Example with a 24-Bit Wide Register Located at Address CMD
CS
Device Latches SDI on Rising Edge
DATA
DATA
DATA
DATA
DATA
DATA
DATA
DATA
DATA
DATA
DATA
DATA
DATA
DATA
DATA
DATA
DATA
DATA
DATA
DATA
DATA
POR _
STA TUS
DATA
DATA
0
1
C RC R EG_
STA TUS
CMD
CMD
CMD
CMD
D R_
STA TUS
0 0
0
CMD
High-Z
CMD
SDO
CMD
Don’t care
CMD
SDI
CMD
SCK
DATA
Don’t
care
High-Z
A
SPI Mode 1,1; Example with a 24-Bit Wide Register Located at Address CMD
FIGURE 6-4:
Single Register Write Communication (CMD[1:0] = 10) Timing Diagram.
CS
ADDRESS SET
0x1
Depends on
ADDR
SCK
8x
SDI
COMMAND
BYTE
Depends on
ADDR + 1
...
8x
8x
8x
...
8x
...
ADDR
Don’t care
CMD + ADDR +10
ADDR
ADDR + 1
...
ADDR = 0xD
ADDR = 0x1
Complete WRITE Sequence
ADDR = 0x2
...
Complete WRITE Sequence
ADDR = 0xD
...
Complete
WRITE
Sequence
0xD
Roll-over
SDO
Hi-Z
00xxxxxx
Hi-Z
0
Depends on IRQ Status
and Device Address
FIGURE 6-5:
DS20006391A-page 72
Multiple Register Write within One Communication Using Incremental Write Feature.
2020 Microchip Technology Inc.
MCP3561/2/4R
6.4
Reading from the Device
When the Command bit, CMD[0], is equal to ‘1’, the
command is a read communication. After the STATUS
byte has been transferred, the first register to be read
on the SDO pin is the one with the address defined by
the Command Address bits (CMD[5:2]).
Any CS rising edge during a read communication
aborts the current reading.
The registers may need 4, 8, 16, 24 or 32 bits to be fully
read depending on their address (see Table 8-1).
If the CMD[1:0] bits are equal to ‘11’, the command
type is Incremental Read. In this case, after each
register is read, the Address Pointer is automatically
incremented as long as CS stays logic low. The
following data bytes are read from the next address
sequentially defined in the register map. When the
Address Pointer reaches 0xF (last register in the register map for reading), the next register to read is register
0x0 (see Figure 6-6 for a graphical representation of
the address looping).
will continuously read the same register. Reading
another register is only possible by aborting the current
communication sequence by raising CS and issuing
another command.
In both Static and Incremental modes, the registers
are updated after each register read is fully performed.
If the value of the register changes internally during
the read, it will only be updated after the end of the
read. The value of each register is latched in the SDO
Output Shift register at the first rising edge of SCK of
each individual register reading. Figure 6-7 shows the
bit by bit details of a single register Read
communication. Figure 6-8 shows the examples of
Static and Incremental Read communications.
ADCDATA (0x0)
CONFIG0 (0x1)
CONFIG1 (0x2)
CONFIG2 (0x3)
CONFIG3 (0x4)
IRQ (0x5)
MUX (0x6)
SCAN (0x7)
TIMER (0x8)
OFFSETCAL (0x9)
GAINCAL (0xA)
Reserved (0xB)
Reserved (0xC)
LOCK (0xD)
Reserved (0xE)
CRCREG (0xF)
FIGURE 6-6:
Incremental Read Loop.
If the CMD[1:0] bits are equal to ‘01’, the command
type is Static Read. In this case, the register address
defined in the COMMAND byte is read continuously.
The Address Pointer is automatically incremented.
Continuously clocking SCK while CS stays logic low
2020 Microchip Technology Inc.
DS20006391A-page 73
MCP3561/2/4R
CS
Device Latches SDI on Rising Edge
Device Latches SDO on Falling Edge
DATA
DATA
DATA
DATA
DATA
DATA
DATA
DATA
DATA
DATA
DATA
DATA
DATA
DATA
DATA
DATA
DATA
DATA
POR _
STA TUS
DATA
CMD
C RC REG_
STA TUS
DATA
CMD
DR_
STATUS
DATA
CMD
CMD
DATA
DATA
CMD
0 0
0
Don’t Care
DATA
CMD
1
CMD
High-Z
CMD
SDO
Don’t Care
CMD
SDI
CMD
SCK
Don’t Care
High-Z
SPI Mode 0,0 ; Example with a 24-Bit Wide Register Located at Address CMD
CS
Device Latches SDI on Rising Edge
Device Latches SDO on Falling Edge
1
DATA
DATA
DATA
DATA
DATA
DATA
DATA
DATA
DATA
DATA
DATA
DATA
DATA
DATA
DATA
DATA
DATA
DATA
DATA
DATA
DATA
DATA
A
Don’t Care
DATA
POR _
STA TUS
CMD
CMD
CMD
CMD
CMD
C RC R EG_
STA TUS
DR_
ST ATUS
CMD
0 0
0
CMD
High-Z
CMD
SDO
Don’t Care
CMD
SDI
CMD
SCK
DATA
High-Z
SPI Mode 1,1; Example with a 24-Bit Wide Register Located at Address CMD
FIGURE 6-7:
DS20006391A-page 74
Single Read SPI Communication (Static or Incremental Read).
2020 Microchip Technology Inc.
MCP3561/2/4R
CS
SCK
SDI
Depends on
ADDR
8x
Don’t Care
COMMAND
BYTE
Depends on
ADDR
...
Depends on
ADDR
...
ADDR
Don’t Care
CMD[7:6] + ADDR + 01
SDO
High-Z
00XXXXXX
ADDR
Depends on IRQ status
and device address
Complete READ
sequence
ADDR
0
Static Read Sequence
CS
ADDRESS SET
0x0
SCK
Depends on
ADDR
8x
Depends on
ADDR+1
...
Depends on
Data Format
16x
8x
...
16x
...
ADDR
SDI
Don’t Care
COMMAND
BYTE
Don’t Care
...
CMD[7:6] + ADDR + 11
Complete
READ
sequence
0xF
Roll-over
SDO
High-Z
00XXXXXX
ADDR
ADDR + 1
...
ADDR = 0xF
ADDR = 0x0
ADDR = 0x1
...
ADDR = 0xF
0
Depends on IRQ status
and device address
Complete READ sequence
Complete READ sequence
Incremental Read Sequence
FIGURE 6-8:
Static and Incremental Read SPI Communications.
2020 Microchip Technology Inc.
DS20006391A-page 75
MCP3561/2/4R
If the COMMAND byte defines a static read of the
ADCDATA register (address: 0x0), the ADC data will be
present on SDO and will be updated continuously at
each read. In this case, when a data ready interrupt
occurs within a read, the data are not corrupted and will
be updated to a new value after the old value has been
completely read. The ADC register contains a double
buffer that prevents data from being corrupted while
reading it. The part is able to stream output data
continuously with no additional command if the communication is not stopped with a CS rising edge.
Figure 6-9 represents the continuous streaming of
incoming ADCDATA through the SPI port with both SPI
Modes 0,0 and 1,1.
CS
The falling edge after Read___
Start
clears the DR interrupt on IRQ pin
Device latches SDI on rising edge
The falling edge after Read Start
clears the DR interrupt on IRQ pin
Device latches SDO on falling edge
R/W
1
DATA1
DATA1
DATA0< 31>
DATA1
DATA0
DATA0
DATA0
DATA0
DATA0
DATA0
DATA0
DATA0
DATA0
DATA0
DATA0
DATA0
DATA0
DATA0
DATA0
DATA0
DATA0
DATA0
DATA0
DATA0
DATA0
DATA0
DATA0
DATA0
DATA0
DATA0
DATA0
DATA0
DATA0
D ATA0< 31 >
DATA0
DATA0
Read Start
1
1
0
CMD
CMD
Hi-Z
CMD
0
SDO
0
Read Start
DATA1
A
0
A
0
A
0
A
0
A
0
Don’t care
CMD
A
SDI
CMD
A
SCK
SDO changes synchronously with the IRQ
falling edge (DR interrupt flag)
only when MSB is present on SDO
IRQ
DR Interrupt
(DATA1 is ready)
SPI Mode 0,0; ADC Data Format: 32-Bit
CS
___
The falling edge after Read
Start
clears the DR interrupt on IRQ pin
Device latches SDI on rising edge
The falling edge after Read Start
clears the DR interrupt on IRQ pin
Device latches SDO on falling edge
R/W
Don’t care
1
IRQ
D ATA1< 28>
D ATA1< 29>
D ATA0< 0>
D ATA1< 30>
DATA0
DATA0
DATA0
DATA0
DATA0
DATA0
DATA0
DATA0
DATA0
D ATA0< 10>
D ATA0< 11>
D ATA0< 12>
D ATA0< 13>
D ATA0< 14>
D ATA0< 15>
D ATA0< 16>
D ATA0< 17>
D ATA0< 18>
D ATA0< 19>
D ATA0< 20>
D ATA0< 21>
D ATA0< 22>
D ATA0< 23>
D ATA0< 24>
D ATA0< 25>
D ATA0< 26>
D ATA0< 27>
D ATA0< 28>
D ATA0< 29>
D ATA0< 30>
Read Start
D ATA0< 31>
1
1
0
CMD
Hi-Z
CMD
CMD
0
SDO
0
Read Start
D ATA1< 31>
A
0
A
0
A
0
A
0
A
0
Don’t care
CMD
A
SDI
CMD
A
SCK
DR Interrupt
(DATA1 is ready)
SPI Mode 1,1; ADC Data Format: 32-Bit
FIGURE 6-9:
DS20006391A-page 76
Continuous ADC Read (Data Streaming) with SPI Mode 0,0 and 1,1.
2020 Microchip Technology Inc.
MCP3561/2/4R
For continuous reading of ADCDATA in SPI Mode 0,0,
once the data have been completely read after a data
ready interrupt, the SDO pin takes the MSb value of the
previous data at the end of the reading (falling edge of
the last SCK clock). If SCK stays Idle at logic low (by
definition of Mode 0,0), the SDO pin will be updated at
the falling edge of the next data ready pulse (synchronously with the IRQ pin falling edge with an output
timing of tDODR) with the new MSb of the data corresponding to the data ready pulse. This mechanism
allows the device to continuously read ADC data
outputs seamlessly, even in SPI Mode (0,0).
In SPI Mode (1,1), the SDO pin stays in the last state
(LSb of previous data) after a complete reading, which
also allows seamless Continuous Read mode.
The ADC output data can only be properly read after a
tDODR time, after the data ready interrupt comes on the
IRQ pin. The tDODR timing is shorter than the time
necessary to input a command on the SDI pin, which
ensures proper reading when a new Read command is
triggered by the data ready interrupt. In case of continuous reading (with CS pin kept logic low), the tDODR
timing must be carefully handled by the MCU, but in
general, the interrupt service time is much longer than
the tDODR timing. Retrieving a data ready interrupt by
reading the STATUS byte or reading the IRQ register
automatically ensures that the tDODR timing is
respected.
6.5
Securing Read Communications
through CRC-16 Checksum
Since some applications can generate or receive large
EMI/EMC interferences and large transient spikes, it is
helpful to secure SPI communications as much as
possible, to maintain data integrity and desired
configurations during the application’s lifetime.
The communication data on the SDO pin can be
secured through the insertion of a Cyclic Redundancy
Check (CRC) checksum at the end of each read
sequence. The CRC checksum on communications
can be enabled or disabled through the EN_CRCCOM
bit in the CONFIG3 register. The CRC message
ensures the integrity of the read sequence bits
transmitted on the SDO pin.
When enabled, the CRC checksum (CRCCOM[15:0])
is propagated on SDO after each read communication
sequence.
In case of a Static Read command, the checksum is
propagated after each register read. In case of an
Incremental Read command, the checksum is propagated after the last register read in the register map
(address: 0xF). Figure 6-11 and Figure 6-12 show
typical read communications in Static Read and
Incremental Read modes, respectively, when the
EN_CRCCOM bit is enabled. Since the STATUS byte
is propagated on SDO, it is part of the first message,
and therefore, it is included in the calculation of the first
checksum. For subsequent checksum calculations, the
message only contains the registers that are effectively
read in between two checksums.
The CRC-16 format displayed on the SDO pin depends
on the CRC_FORMAT bit in the CONFIG3 register (see
Figure 6-10). It can have a 16-bit or 32-bit format to be
compatible with both 16-bit and 32-bit MCUs. The
CRCCOM[15:0] bits calculated by the device do not
depend on the format (the device always calculates a
16-bit only CRC checksum).
CRC_FORMAT = 0: 16-Bit
(Default)
CRCCOM[15:0]
CRC_FORMAT = 1: 32-Bit
CRCCOM[15:0]
FIGURE 6-10:
Communications.
0x0000
CRC Format Table for Read
The CRC calculation computed by the device is fully
compatible with the CRC hardware contained in the
Direct Memory Access (DMA) of the PIC24 and PIC32
MCU product lines. The CRC message that should be
considered in the PIC® device DMA is the concatenation of the read sequence and its associated
checksum. When the DMA CRC hardware computes
this extended message, the resulted checksum should
be 0x0000. Any other result indicates that a
miscommunication has occurred and that the current
communication sequence should be stopped and
restarted.
The CRC checksum in the MCP3561/2/4R devices
uses the 16-bit CRC-16 ANSI polynomial as defined in
the IEEE 802.3 standard: x16 + x15 + x2 + 1.
This polynomial can also be noted as 0x8005. CRC-16
detects all single and double-bit errors, all errors with
an odd number of bits, all burst errors of 16 bits in
length or less and most errors for longer bursts. This
allows an excellent coverage of the SPI communication
errors that can occur in the system, and heavily
reduces the risk of a miscommunication, even under
noisy environments.
2020 Microchip Technology Inc.
DS20006391A-page 77
MCP3561/2/4R
CS
SCK
Depends on
ADDR
8x
16x or 32x
Depending on
CRC format
Depends on
ADDR
16x or 32x
Depending on
CRC format
...
ADDRESS SET
ADDR
Roll-over
SDI
Don’t Care
COMMAND
BYTE
Don’t Care
CRC Checksum
CMD[7:6] + ADDR + 01
SDO
High-Z
0
STATUS
BYTE
ADDR
Complete READ sequence including STATUS Byte
= First Message for CRC Calculation
FIGURE 6-11:
CRC Checksum
ADDR
CRC Checksum
First checksum
New message
New checksum
...
SPI Static Read with Communication CRC Enabled.
CS
ADDRESS SET
0x0
SCK
8x
Depends on
ADDR
Depending on
ADDR+1
...
16x
16x or 32x
Depending on
CRC format
Depends on
Data Format
8x
...
24x
16x or 32x
Depending on
CRC format
...
ADDR
SDI
Don’t Care
COMMAND
BYTE
Don’t Care
...
CMD[7:6] + ADDR + 11
Complete
READ
sequence
0xF
Roll-over
SDO
High-Z
0
STATUS
BYTE
ADDR
ADDR + 1
...
Complete READ sequence including STATUS Byte
= First Message for CRC Calculation
FIGURE 6-12:
DS20006391A-page 78
ADDR = 0xF CRC Checksum ADDR = 0x0
First Checksum
ADDR = 0x1
New Message
...
ADDR = 0xF CRC Checksum
CRC Checksum
(not part of register map)
New Checksum
SPI Incremental Read with Communication CRC Enabled.
2020 Microchip Technology Inc.
MCP3561/2/4R
6.6
Locking/Unlocking Register Map
Write Access
The MCP3561/2/4R digital interface includes an
advanced security feature that allows locking or unlocking the register map write access. This feature prevents
the miscommunication that can corrupt the desired
configuration of the device, especially an SPI read
becoming an SPI write because of the noisy
environment.
The last register address of the incremental write loop
(0xD: LOCK) contains the LOCK[7:0] bits. If these bits
are equal to the password value (0xA5), the register
map write access is not locked. Any write can take
place and the communications are not protected. The
devices are, by default after POR, in an unlocked state
(LOCK[7:0] = 0xA5).
When the LOCK[7:0] bits are not equal to 0xA5, the
register map write access is locked. The register map,
and therefore, the full device configuration is writeprotected. Any write to an address other than 0xD will
yield no result. All the register addresses, except the
address 0xD, become read-only. In this case, if the user
wants to change the configuration, the LOCK[7:0] bits
have to be reprogrammed back to 0xA5 before sending
the desired Write command.
The LOCK[7:0] bits are located in the last register of the
Incremental Write address loop, so the user can program the entire register map, starting from 0x1 to 0xD,
within one continuous write sequence and then lock the
configuration at the end of the sequence by writing all
zeros (for example) in the 0xD address.
6.7
Detecting a Configuration Change
through CRC-16 Checksum on the
Register Map and its Associated
Interrupt Flag
In order to prevent internal corruption and to provide
additional security on the register map configuration, the
MCP3561/2/4R devices include an automatic and continuous CRC checksum calculation on the full register
map Configuration bits. This calculation is not the same
as the communication CRC checksum described in
Section 6.5 “Securing Read Communications
through CRC-16 Checksum”.
This calculation takes the contents of the register map,
from addresses 0x1 to 0xF, and produces a checksum
which is held in the CRCCFG[15:0] bits located in the
CRCCFG register (address: 0xF). The CRC checksum
for the register map uses the 16-bit CRC-16 ANSI polynomial as defined in the IEEE 802.3 standard:
x16 + x15 + x2 + 1.
2020 Microchip Technology Inc.
Since this feature is intended to protect the configuration of the device, this calculation is run continuously
only when the register map is locked (LOCK[7:0]),
which is different than 0xA5 (see Section 6.6
“Locking/Unlocking
Register
Map
Write
Access”). If the register map is unlocked (for example
after POR), the CRCCFG[15:0] bits are cleared and no
CRC is calculated.
The
DR_STATUS,
CRCCFG_STATUS
and
POR_STATUS bits are set to ‘1’ (default) and the
CRCCFG[15:0] bits are set to ‘0’ (default) for this calculation, as they could vary and lead to unwanted CRC
errors.
After the DR_STATUS, CRCCFG_STATUS and
POR_STATUS bits are cleared (with a read on the IRQ
register), the CRC checksum on the register map can
be verified by reading all registers in an incremental
read sequence and by using the CRC communication.
At the second incremental read loop, the checksum
provided by the CRC communication must be equal to
all zeros if the checksum on the register map is correct.
The checksum will be calculated for the first time in
11 DMCLK periods. This first value will then be the
reference checksum value and will be latched internally
until an unlocking of the register map occurs. The
checksum will then be calculated continuously every
11 DMCLK periods and checked against the reference
checksum.
If the checksum is different than the reference, an interrupt flag will be generated on the CRCCFG_STATUS
bit within the STATUS byte on SDO, on the
CRCCFG_STATUS bit in the IRQ register and on the
IRQ output pin. The interrupt flag is maintained on all
three mechanisms until the register map write access
is unlocked.
When the part write access is unlocked, the interrupt on
the IRQ pin clears immediately and the two other interrupt mechanisms are cleared when the interrupt is read
(read STATUS byte or read IRQ register). The CRC
interrupt can occur even if the IRQ pin is configured as
the MDAT modulator output. In this case, the interrupt
stays present and forces a logic low output on this pin
as long as the LOCK[7:0] register is locked (LOCK[7:0]
0xA5).
At power-up, the interrupt is not present and the
register map is unlocked. As soon as the user finishes
writing its configuration, the user needs to lock the register map (for example, by writing 0x00 in the LOCK
bits) to be able to use the interrupt flag and to calculate
the checksum of the register map.
DS20006391A-page 79
MCP3561/2/4R
6.8
Interrupts Description
The MCP3561/2/4R devices incorporate multiple
interrupt mechanisms to be able to synchronize the
device with an MCU and to warn against external perturbations. There are four events that can generate
interrupt flags:
•
•
•
•
Additionally, there are three independent interrupt
mechanisms that allow the devices to be implemented
in many different applications and configurations. A
summary of the different mechanisms is available in
Table 6-3.
Conversion Start
Data Ready
POR
CRC Error on the Register Map Configuration
TABLE 6-3:
INTERRUPT DESCRIPTION SUMMARY TABLE
Interrupt Flag Type
STATUS Byte
IRQ Register Status
Bits
IRQ Pin State
DS20006391A-page 80
Description
Clearing Procedure
Three Status bits (DR_STATUS,
Cleared when STATUS byte clocking is finished
CRCCFG_STATUS, POR_STATUS) are (on the last SCK falling edge).
latched together after device address
detection and clocked out during each
command on the SDO STATUS byte.
IRQ register Status bits can be read when Cleared when the IRQ register reading is
reading the address 0x5 (IRQ register). finished (on the last SCK falling edge).
The IRQ latching occurs at the beginning
of the IRQ register reading.
• When IRQ_MODE[1] = 0, the IRQ pin
can be asserted to logic low by any of
the interrupts.
• When IRQ_MODE[1] = 1, only POR
and CRC interrupts can assert the
IRQ pin to logic low.
• Conversion start interrupt is automatically
cleared at the beginning of a new
conversion cycle after a TSTP timing.
• DR interrupt is cleared by the first SCK
falling edge of an ADC read or
automatically 16 DMCLKs before a new
data ready in Continuous Conversion mode
or in SCAN mode.
• POR interrupt is cleared on the first CS
falling edge when both AVDD and DVDD
monitoring circuits detect that their power
supply is over their respective thresholds.
• CRCCFG interrupt is cleared when the
device is unlocked (writing 0xA5 to LOCK
register) or when a Fast command ADC
start/restart conversion is performed.
2020 Microchip Technology Inc.
MCP3561/2/4R
6.8.1
CONVERSION DATA READY
INTERRUPT
3.
The data ready interrupt happens when a new
conversion is ready to be read on the ADCDATA register.
This event happens synchronously with DMCLK and at
each end of conversion. This interrupt is implemented
with three different and independent mechanisms:
STATUS byte on SDO, IRQ register Status bit, and IRQ
pin state.
1.
2.
STATUS byte on SDO. When the interrupt
occurs on the next STATUS byte transmitted on
SDO, the DR_STATUS bit will be logic low. Once
the STATUS byte has been transmitted, the
DR_STATUS bit appears as ‘1’ until a new
interrupt is present. If the interrupt occurs
between two STATUS byte transmissions, the
DR_STATUS bit on SDO will appear as equal to
‘0’ on the second reading.
IRQ register Status bit. When the interrupt
occurs, the DR_STATUS bit in the IRQ register
is set to ‘0’. Once the IRQ register has been fully
read, this DR_STATUS bit is reset to ‘1’. If the
interrupt occurs between two readings of the
IRQ register, the IRQ register Status bit appears
as equal to ‘0’ on the second reading.
IRQ pin state. The interrupt generates an IRQ
pin falling edge (transition to logic low) as soon
as it happens.
The data ready interrupt is cleared by the first of the
following two events:
• First falling edge of SCK during an ADC Output
Data register read
• 16 DMCLK clock periods before current
conversion ends
If the user does not read the ADCDATA register in time
in Continuous Conversion mode or in SCAN mode, the
IRQ pin will automatically reset to its Inactive state
16 DMCLKs periods prior to the new data ready interrupt. This feature is designed in order to avoid the case
where the IRQ pin is logic low if the reading of ADC
data is not performed. The user can then determine
exactly when to expect the new data and can respect
the tDODR timing in all cases to ensure a proper reading
of the ADC data. See Figure 6-13 for more details.
Transition time
tDOD R
DATA1 can be read during this time
SPI
C OMM AN D By te
R ea d A DC D ATA1
R ea d A DC D ATA
ADCDATA
REGISTER
DATA0
C OMM AN D By te
R ea d A DC D ATA2
R ea d A DC D ATA
DATA2
DATA1
TCON V
1/DRCLK
1/DRCLK
TDRH
TDRH
IRQ
Data Ready Interrupt
Interrupt is cleared
at first SCK falling edge
after ADCDATA read start
FIGURE 6-13:
Transition time
tDOD R
DATA2 can be read during this time
Interrupt is cleared
automatically if ADCDATA
has not been read in time
Data Ready Interrupt IRQ Pin Timing Diagram.
2020 Microchip Technology Inc.
DS20006391A-page 81
MCP3561/2/4R
6.8.2
CONVERSION CYCLE START
INTERRUPT
This interrupt is the only selectable one and the only
one not present in the STATUS byte on the SDO and
IRQ registers. It is only available on the IRQ pin. The
user can enable or disable this output by using:
• [EN_STP] = 1: The conversion start interrupt
output is enabled (default).
• [EN_STP] = 0: The conversion start interrupt
output is disabled.
ADC_MODE
ADC STATUS
This interrupt marks the beginning of a conversion
cycle. In case of a One-Shot mode or Continuous mode
conversion in MUX mode, it marks the start of the
sampling in the first conversion (after the ADC start-up
delay of 256 DMCLK periods). In case of a SCAN
mode, it marks the start of the sampling in the first conversion of the first SCAN mode cycle. The host MCU
can utilize this interrupt to synchronize the start of the
ADC conversion and manage synchronous events
together with the conversion process (see Figure 6-14
for more details).
00
11
Sh u td o wn
Sta rt-u p
1 st C o nv ers io n i n
e ithe r MU X o r SC AN mo de
TA DC_ SET UP
TCON V
TST P
IRQ
Conversion
Start IRQ
(EN_STP = 1)
FIGURE 6-14:
Conversion Start IRQ Timing Diagram.
This interrupt output generates a falling edge on the
IRQ pin and is automatically cleared after a short
period of time, TSTP.
6.8.3
POR INTERRUPT
The POR interrupt informs the user if a POR event has
happened or if the part is in a POR state when the IRQ
pin is used.
This interrupt is implemented with three different and
independent mechanisms: STATUS byte on SDO, IRQ
register Status bit and IRQ pin state.
6.8.3.1
Data Ready
IRQ
6.8.3.2
IRQ Register Status Bit
When the device has just powered up, the
POR_STATUS bit in the IRQ register is set to ‘0’. Once
the IRQ register has been fully read, this
POR_STATUS bit is once again reset to ‘1’. If a POR
event occurs between two readings of the IRQ register,
the IRQ register Status bit will appear as equal to ‘0’ on
the second reading. This mechanism can only work
when the power supplies are back above the POR
thresholds on the analog and digital cores.
STATUS Byte on SDO
When the device has just powered up, on the first
STATUS byte transmitted on SDO (first communication), the POR_STATUS bit is logic low. Once the
STATUS byte has been transmitted, the POR_STATUS
bit appears as ‘1’ until the part is powered down. If a
POR event occurs between two STATUS byte transmissions, and if the part is properly repowered up, the
POR_STATUS bit on SDO will appear as equal to ‘0’ on
the latter reading. This mechanism can only work when
the power supplies are back above the POR thresholds
on the analog and digital cores, as retrieving data from
the SPI port is not possible when the device is in POR
state.
DS20006391A-page 82
2020 Microchip Technology Inc.
MCP3561/2/4R
6.8.3.3
IRQ Pin State
A Logic Low state is generated on the IRQ pin as soon
as the AVDD or DVDD monitoring circuits detect a power
supply drop below their specified threshold.
This POR interrupt can only be cleared when both
AVDD and DVDD are above their monitoring voltage
thresholds. When this condition is met, the POR
threshold is cleared by the CS falling edge. Therefore,
it means that if a CS falling edge does not clear the IRQ
pin state, the POR event is still in effect.
DVDD
AVDD
This feature helps the user to know exactly when the
chip has powered up by polling with the CS pin and
checking the IRQ pin state at power-up (see
Figure 6-15 for more details).
Since this is a high-level priority interrupt, the POR
interrupt can happen at all times, even when MDAT is
enabled. In this case, having a constant logic low bitstream can indicate a probable POR event (or a fully
negative ADC saturation output code induced by a
large negative input voltage).
VPOR_A, V POR_D
tPOR
POR
Internal State
High-Z
IRQ
0
tC SIRQ
CS
Don’t Care
Chip Select
Starts Low
Clears POR interrupt
FIGURE 6-15:
6.8.4
POR IRQ Timing Diagram.
CRCCFG ERROR INTERRUPT
The CRCCFG interrupt happens when an error in the
CRC-16 checksum has been detected in the register
map CRC calculation.
This interrupt is implemented with three different and
independent mechanisms: STATUS byte on SDO, IRQ
register Status bit and IRQ pin state.
6.8.4.1
STATUS Byte on SDO
In case of a CRCCFG error on the next STATUS byte
transmitted on SDO, the CRCCFG_STATUS bit is logic
low. Once the STATUS byte has been transmitted, the
CRCCFG_STATUS bit appears as ‘1’ until a new interrupt occurs. If the error is detected again between two
STATUS byte transmissions, the CRCCFG_STATUS
bit on SDO will appear as equal to ‘0’ on the second
reading.
6.8.4.2
IRQ Register Status Bit
In case of a CRCCFG error, the CRCCFG_STATUS bit
in the IRQ register is set to ‘0’. Once the IRQ register is
fully read, the CRCCFG_STATUS bit is reset to ‘1’. If
the CRCCFG error happens again between two readings of the IRQ register, the IRQ register Status bit will
appear as ‘0’ on the second reading.
2020 Microchip Technology Inc.
6.8.4.3
IRQ Pin State
The CRCCFG error generates a Logic Low state on the
IRQ pin until it is cleared. The clearing of the CRCCFG
error can only be made by “unlocking” the device (write
0xA5 in the LOCK[7:0] register) or by sending a Fast
command start/restart ADC conversion. Unlocking the
device stops the CRC calculation, and therefore, clears
the associated interrupt. Sending an ADC start/restart
conversion Fast command resets the CRC calculation
and clears the interrupt.
This CRCCFG error can only occur in case of an
external perturbation (for example, EMI induced) that
causes the continuous calculation of the CRC on the
register map to be erroneous or in case the chip
integrity has been altered. Since both causes are
high-priority issues, the CRCCFG error has priority
over all other interrupts (except POR) and over the
MDAT output on the IRQ pin.
Note:
If MCLK starts running before the device is
locked, an interrupt can momentarily occur,
even if registers have not been corrupted. In
such a case, the user must send a
start/restart conversion Fast command
which will clear the unwanted interrupt and
correctly restart the CRC calculations.
DS20006391A-page 83
MCP3561/2/4R
NOTES:
DS20006391A-page 84
2020 Microchip Technology Inc.
MCP3561/2/4R
7.0
BASIC APPLICATION
CONFIGURATION
7.1
The MCP3561/2/4R devices can be used for various
precision Analog-to-Digital Converter applications. The
flexibility of its usage is given by the possibility of configuring the ADC to fit the required application.
R12
100
5%
0603
CH0
CH1
The MCP3561/2/4R is able to measure the signal
provided by sensors with absolute voltage output. For
such applications, the MCP3561/2/4R typically uses its
internal voltage reference. For the best performance,
an external capacitor is recommended on the
REFIN+/OUT pin for noise filtering and to provide more
stability for the internal voltage reference (See
Section 3.1 “Differential Reference Voltage Inputs:
REFIN+/OUT, REFIN-”).
Anti Aliasing Filters
1 2
J1
Typical Application for Absolute
Voltage Measurement
C6
0.1uF
16V
0603
GNDA
C9
R6
100
0603
R5
5%
0603
5%
CH2
CH3
100
100
R7
0603
5%
1 2
J5
CH4
CH5
100
0603
5%
IRQ Pull-UP
16V
0603
5%
R9
5%
100
100
0603
16V
19
3
GNDA
4
0.1uF
16V
0603
5
6
7
C7
0.1uF
16V
0603
1 2
J7
CH6
CH7
8
9
GNDA
C8
R11
100
5%
0603
C12 0.1uF
C2
0.1uF
16V
0603
R17
C11 0.1uF
GNDA
0.1uF
16V
0603
C5
R10
3.3D
10R
5%
0603
C3
C4
R8
ADC
3.3A
R14
0.1uF
16V
0603
1 2
J3
0.1uF
16V
0603
10
0.1uF
16V
0603
0603
GNDA
AVDD
20
3.3D
16V 0603
C14 0.1uF
GND
16V
0603
DVDD
R22
10k
5%
0603
18
RA14/ADC_IRQ
CH0
CH1
CH2
CH3
CH4
CH5
CH6
16
MCLK
15
IRQ/MDAT
0603 R18
0603 R19
13
0603 R21
SDI
14 R16
10R5%
SDO
12 0603
R20
SCK
11 R15
10R
CS
5%
0603
10R 5%
10R 5%
10R 5%
10R 5%
0603
RD3/ADC_CLKIN
RA14/ADC_IRQ
RG8/ADC_MOSI2
RG7/ADC_MISO2
RG6/ADC_SCK2
RG9/ADC_CS2
CH7
2
REFIN+/OUT
1
REFIN-
0603
C13 0.1uF
10R
5%
0603
AGND
EP
DGND
21
17
GNDA
GND
0&35
GNDA
C10
10uF
10V
0603
GNDA
FIGURE 7-1:
MCP3564R Application Example.
The ADC can be used in Differential or Single-Ended
mode due to the internal dual multiplexer (Figure 5-1).
The user can select the input connection settings from
the MUX register (Section 8.7 “Multiplexer (MUX)
Register”) by using the different settings available on
the positive and negative inputs of the ADC. The
single-ended configuration is achieved by selecting
AGND for the VIN- input of the ADC (MUX[3:0] = 1000)
or by selecting any CHn input channel for VIN- and
connecting the corresponding CHn input channel to
AGND.
2020 Microchip Technology Inc.
DS20006391A-page 85
MCP3561/2/4R
7.1.1
HIGH-SIDE AND LOW-SIDE
CURRENT SENSING
The ADC has the ability to perform differential
measurements with analog input Common-mode equal
to or slightly larger than AVDD, or equal to or slightly lower
than AGND (see the Electrical Characteristics table).
A differential input structure and a Kelvin connection
are required in order to achieve the most accurate
measurements. An anti-aliasing filter is required to
avoid aliasing of the oversampling frequency (DMCLK)
back into the baseband of the input signal and possible
corruption of the output data. Figure 7-1 provides an
example of an anti-aliasing filter.
For the measurement of voltages that can reach AVDD
or a few mV higher, a gain setting of 0.33x is useful
since it increases the input range to a 3 x VREF value,
so a 1.2V VREF will allow a theoretical input range of
3.6V. However, the maximum voltage that can be
measured is always bounded by AVDD + 0.1V in order
to limit excess leakage current at the input pins created
by the ESD structures. Therefore, in order to properly
measure 3.6V with a 1.2V voltage reference, it is recommended to use an AVDD supply voltage as close as
possible to 3.6V.
7.1.2
THERMOCOUPLE CONNECTION
One of the most used temperature transducers in the
industry is the thermocouple. Thermocouples provide a
voltage dependent on the temperature difference
between cold junction and hot junction. This voltage is
in the order of magnitude of tens of µV/°C, which
requires amplification that can be provided by the
internal gain stage of the ADC.
7.2
Typical Application for
Ratiometric Voltage Measurement
A wide range of sensors provides an output voltage
directly related to the power supply of the sensors.
These sensors are known as ratiometric output. These
sensors often have a Wheatstone bridge structure,
such as pressure sensors or load cells (Figure 7-3).
R1
RTD
VIN+
Input
Signal
REFIN+/OUT
MCP3561R
VIN-
REFIN-
FIGURE 7-3:
Wheatstone Bridge
Ratiometric Connection.
Others act as a single resistor with a value dependent
on temperature (pure metal resistance thermometer
RTD and negative temperature coefficient resistor
NTC). To accurately measure the signal from these
sensors, REFIN+/OUT is usually connected to the
same power supply of the sensor (Figure 7-4), as long
as this respects the specified voltage range on the
REFIN+/OUT pin (see the Electrical Characteristics
table.
R2
Sensor
VIN+
Anti-aliasing
Filter
REFIN+/OUT
MCP3561R
VIN-
REFIN-
R1
C1
FIGURE 7-4:
FIGURE 7-2:
to MCP3561R.
C2
AGND
DGND
RTD Ratiometric Connection.
Thermocouple Connection
The connection of the thermocouple to the ADC
requires minimal extra components. A differential input
structure is recommended. The cold junction can be
measured by using a digital temperature sensor like
MCP9804 connected to the MCU. If high accuracy is
not required, the cold junction temperature can be
estimated directly with the internal temperature sensor
of the ADC (see Figure 7-2).
DS20006391A-page 86
2020 Microchip Technology Inc.
MCP3561/2/4R
7.3
Power Supply Design and
Bypassing
Another possibility, sometimes easier to implement in
terms of PCB layout, is to consider the MCP3561/2/4R
as an analog component, and therefore, connect AVDD
to DVDD and AGND to DGND with a star connection. In
this scheme, the decoupling capacitors may be larger,
due to the ripple on the digital power supply (caused by
the digital filters and the SPI interface of the
MCP3561/2/4R) now causing glitches on the analog
power supply.
In any system, the analog ICs (such as references or
operational amplifiers) are always connected to the
analog ground plane. The MCP3561/2/4R should also
be considered a sensitive analog component and connected to the analog ground plane. The ADC features
two pairs of power supply voltage pins: AGND and
AVDD, DGND and DVDD. For best performance, it is
recommended to keep the two pairs of pins connected
to two different networks (see Figure 7-5), so that the
design will feature two ground traces and two power
supplies (see Figure 7-6).
Figure 7-6 shows an example of a power supply
schematic with separate DVDD and AVDD. A high-current
LDO (MCP1825) was used for the DVDD line to be able
to power the MCU and other peripherals attached to the
MCU. A high PSRR LDO (MCP1754) is used for the
AVDD that goes to the ADC and a few other components
sensitive to noise. The NET tie is used to separate DGND
from AGND.
The analog circuitry (including MCP3561/2/4R) and the
digital circuitry (MCU) should have separate power
supplies and return paths to the external ground reference, as described in Figure 7-5. An example of a
typical power supply circuit, with different paths for
analog and digital return currents, is shown in
Figure 7-6. A possible split example is shown in
Figure 7-7, where the ground star connection can be
located underneath the device with the exposed pad.
The split between analog and digital can be done under
the device, and AVDD and DVDD can be connected with
lines coming under the ground plane. The two separate
return paths will eventually share a unique connection
point (star connection) in order to minimize coupling
between the two power supply domains.
ID
IA
0.1 ȝF
0.1 ȝF
C
VA
AV DD DVDD
VD
MCP356;5
MCU
DGND
AGND
IA
ID
“Star” Point
D-=
A-=
FIGURE 7-5:
Separating Digital and
Analog Ground by Using a Star Connection.
U2
MCP1825S-3.3V
VIN
VOUT
3
C44
10 µF
5V_USB
C15
10 µF
TANT-B
GND
VOUT
GND
GND
2
U3
MCP1754-3.3V
+5V USB
+9V IN
1
VIN
VOUT
3
3.3A
2
MRA4005
VIN
3 1
4 2
3
GND
D1
GND
TANT-B
J9
1
1
3
2
Power Jack 2.5 mm
U4
LM1117-5V
GND
9V
J10
C10
0.1 µF
TANT-B
0603
GND
GND
3.3D
C45
10 µF
C11
0.1 µF
0603
2
1
GND
5V
C14
0.1 µF
0603
GND
Net Tie
GND
GND
GNDA
GNDA
C12
0.1 µF
0603
GNDA
GNDA
C13
10 µF
TANT-B
GNDA
FIGURE 7-6:
Power Supply with Separate Lines for Analog and Digital Sections (the “Net Tie”
Object Represents the Star Ground Connection).
2020 Microchip Technology Inc.
DS20006391A-page 87
MCP3561/2/4R
7.4
SPI Interface Digital Crosstalk
The MCP3561/2/4R devices incorporate a high-speed
20 MHz SPI digital interface. This interface can induce
crosstalk, especially with the outer channels closer to
the SPI digital pins (for example, CH7), if it is run at full
speed without any precautions. The crosstalk is caused
by the switching noise created by the digital SPI
signals. This crosstalk would negatively impact the
SNR in this case. The noise is attenuated if proper
separation between the analog and the digital power
supplies is put in place (see Sections 7.3 “Power
Supply Design and Bypassing”).
FIGURE 7-7:
Separation of Analog and
Digital Circuits on the Layout (Shown on the
UQFN Package).
When remote sensors are used to reduce the sensitivity
to external influences, such as EMI, the wires that
connect the sensor to the ADC should form a twisted
pair. Ferrite beads can be used between the digital and
analog ground planes to keep high-frequency noise
from entering the device. A low-resistance ferrite bead
is recommended.
DS20006391A-page 88
In order to further remove the influence of the SPI
communication on measurement accuracy, it is recommended to add series resistors on the SPI lines to
reduce the current spikes caused by the digital switching noise (see Figure 7-1 where these resistors have
been implemented). The resistors also help to keep the
level of electromagnetic emissions low.
The switching noise is also a linear function of the
DVDD supply voltage. In order to further reduce the
influence of the switching noise caused by SPI transmissions, the DVDD digital power supply voltage should
be kept as low value as possible.
The measurement graphs provided in this
MCP3561/2/4R data sheet have been performed with
10 series resistors connected on each SPI I/O pin.
Measurement accuracy disturbances have not been
observed, even at 20 MHz interfacing.
2020 Microchip Technology Inc.
MCP3561/2/4R
8.0
INTERNAL REGISTERS
The MCP3561/2/4R devices have a total of 16 internal
registers made of volatile memory. Table 8-1 includes a
summary of the registers. These registers are
sequentially accessible.
TABLE 8-1:
INTERNAL REGISTERS SUMMARY
Address Register Name
No. of
Bits
R/W
Description
Latest A/D conversion data output value (24 or 32 bits depending on
DATA_FORMAT[1:0]) or modulator output stream (4-bit wide) in MDAT
Output mode
0x0
ADCDATA
4/24/32
R
0x1
CONFIG0
8
R/W
0x2
CONFIG1
8
R/W
Prescale and OSR settings
0x3
CONFIG2
8
R/W
ADC boost and gain settings, auto-zeroing settings for analog
multiplexer, voltage reference and ADC
0x4
CONFIG3
8
R/W
Conversion mode, data and CRC format settings; enable for CRC on
communications, enable for digital offset and gain error calibrations
0x5
IRQ
8
R/W
IRQ Status bits and IRQ mode settings; enable for Fast commands and
for conversion start pulse
ADC Operating mode, Master Clock mode and Input Bias Current
Source mode
0x6
MUX
8
R/W
Analog multiplexer input selection (MUX mode only)
0x7
SCAN
24
R/W
SCAN mode settings
0x8
TIMER
24
R/W
Delay value for TIMER between SCAN cycles
0x9
OFFSETCAL
24
R/W
ADC digital offset calibration value
0xA
GAINCAL
24
R/W
ADC digital gain calibration value
0xB
RESERVED
24
R/W
Reserved
0xC
RESERVED
8
R/W
Reserved
0xD
LOCK
8
R/W
Password value for SPI Write mode locking
0xE
RESERVED
16
R/W
0xF
CRCCFG
16
R
2020 Microchip Technology Inc.
Reserved
CRC checksum for device configuration
DS20006391A-page 89
MCP3561/2/4R
8.1
ADCDATA REGISTER
Name
Bits
Address
Cof
ADCDATA
4/24/32
0x0
R
REGISTER 8-1:
ADCDATA: ADC CHANNEL DATA OUTPUT REGISTER
R-0
ADCDATA[23:0]
bit 23
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 23-0
x = Bit is unknown
ADCDATA[23:0]: ADC Output code
The data are post-calibration if the EN_OFFCAL or EN_GAINCAL bits are enabled. The data can be
formatted in 24/32-bit modes depending on the DATA_FORMAT[1:0] settings (see Section 5.6 “ADC
Output Data Format”).
The ADC Channel Data Output registers always contain the most recent A/D conversion data. The
register is updated at each data ready internal signal (it depends on the OSR and CONV_MODE
settings). The register is latched at the start of each SPI Read command. The register is double
buffered to avoid data loss. There is a small time delay, tDODR, after each data ready, where the user
has to wait for the data to be available. Otherwise, data corruption can occur (when the internal data
are refreshed).
When IRQ_MODE[1:0] = 1x, this register becomes a 4-bit wide register containing the MDAT output
codes, which are the outputs of the modulator that are represented by four comparator outputs
(COMP[3:0], see Section 5.4.2 “Modulator Output Block”).
DS20006391A-page 90
2020 Microchip Technology Inc.
MCP3561/2/4R
8.2
CONFIG0 REGISTER
Name
Bits
Address
Cof
CONFIG0
8
0x1
R/W
REGISTER 8-2:
CONFIG0 REGISTER
R/W-1
R/W-1
CONFIG0[7]
VREF_SEL
R/W-0
R/W-0
R/W-0
CLK_SEL[1:0]
R/W-0
R/W-0
CS_SEL[1:0]
R/W-0
ADC_MODE[1:0]
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
CONFIG0[7]: If CONFIG0 = 0x00, the device goes into partial shutdown Mode. This bit does not have
any other function.
bit 6
VREF_SEL: Internal Voltage Reference Bit
1 = Internal voltage reference is selected and buffered internally. REFIN+/OUT pin voltage is set at
2.4V (default).
0 = External Voltage reference is selected and not buffered internally. The internal voltage reference
buffer is shut down.
bit 5-4
CLK_SEL[1:0]: Clock Selection
11 = Internal clock is selected and AMCLK is present on the analog master clock output pin.
10 = Internal clock is selected and no clock output is present on the CLK pin.
01 = External digital clock
00 = External digital clock (default)
bit 3-2
CS_SEL[1:0]: Current Source/Sink Selection Bits for Sensor Bias (source on VIN+/Sink on VIN-)
11 = 15 A is applied to the ADC inputs
10 = 3.7 A is applied to the ADC inputs
01 = 0.9 A is applied to the ADC inputs
00 = No current source is applied to the ADC inputs (default)
bit 1-0
ADC_MODE[1:0]: ADC Operating Mode Selection
11 = ADC Conversion mode
10 = ADC Standby mode
01 = ADC Shutdown mode
00 = ADC Shutdown mode (default)
2020 Microchip Technology Inc.
DS20006391A-page 91
MCP3561/2/4R
8.3
CONFIG1 REGISTER
Name
Bits
Address
Cof
CONFIG1
8
0x2
R/W
REGISTER 8-3:
R/W-0
CONFIG1: CONFIGURATION REGISTER 1
R/W-0
R/W-0
PRE[1:0]
R/W-0
R/W-1
R/W-1
R/W-0
OSR[3:0]
R/W-0
RESERVED[1:0]
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-6
PRE[1:0]: Prescaler Value Selection for AMCLK
11 = AMCLK = MCLK/8
10 = AMCLK = MCLK/4
01 = AMCLK = MCLK/2
00 = AMCLK = MCLK (default)
bit 5-2
OSR[3:0]: Oversampling Ratio for Delta-Sigma A/D Conversion
1111 = OSR: 98304
1110 = OSR: 81920
1101 = OSR: 49152
1100 = OSR: 40960
1011 = OSR: 24576
1010 = OSR: 20480
1001 = OSR: 16384
1000 = OSR: 8192
0111 = OSR: 4096
0110 = OSR: 2048
0101 = OSR: 1024
0100 = OSR: 512
0011 = OSR: 256 (default)
0010 = OSR: 128
0001 = OSR: 64
0000 = OSR: 32
bit 1-0
RESERVED[1:0]: Should always be set to ‘00’
DS20006391A-page 92
x = Bit is unknown
2020 Microchip Technology Inc.
MCP3561/2/4R
8.4
CONFIG2 REGISTER
Name
Bits
Address
Cof
CONFIG2
8
0x3
R/W
REGISTER 8-4:
R/W-1
CONFIG2: CONFIGURATION REGISTER 2
R/W-0
R/W-0
BOOST[1:0]
R/W-0
R/W-1
GAIN[2:0]
R/W-0
R/W-1
R/W-1
AZ_MUX
AZ_REF
RESERVED
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7-6
BOOST[1:0]: ADC Bias Current Selection
11 = ADC channel has current x 2
10 = ADC channel has current x 1 (default)
01 = ADC channel has current x 0.66
00 = ADC channel has current x 0.5
bit 5-3
GAIN[2:0]: ADC Gain Selection
111 = Gain is x64 (x16 analog, x4 digital)
110 = Gain is x32 (x16 analog, x2 digital)
101 = Gain is x16
100 = Gain is x8
011 = Gain is x4
010 = Gain is x2
001 = Gain is x1 (default)
000 = Gain is x1/3
bit 2
AZ_MUX: Auto-Zeroing MUX Setting
1 = ADC auto-zeroing algorithm is enabled. This setting multiplies the conversion time by two and
does not allow Continuous Conversion mode operation (which is then replaced by a series of
consecutive One-Shot mode conversions).
0 = Analog input multiplexer auto-zeroing algorithm is disabled (default).
bit 1
AZ_REF: Auto-Zeroing Reference Buffer Setting
1 = Internal voltage reference buffer chopping algorithm is enabled. This setting has no effect
when external voltage reference is selected (VREF_SEL = 0) (default).
0 = Internal voltage reference buffer chopping auto-zeroing algorithm is disabled.
bit 0
RESERVED: Should always be equal to ‘1’
2020 Microchip Technology Inc.
DS20006391A-page 93
MCP3561/2/4R
8.5
CONFIG3 REGISTER
Name
Bits
Address
Cof
CONFIG3
8
0x4
R/W
REGISTER 8-5:
R/W-0
R/W-0
CONV_MODE[1:0]
CONFIG3: CONFIGURATION REGISTER 3
R/W-0
R/W-0
DATA_FORMAT[1:0]
R/W-0
R/W-0
R/W-0
R/W-0
CRC_FORMAT
EN_CRCCOM
EN_OFFCAL
EN_GAINCAL
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7-6
CONV_MODE[1:0]: Conversion Mode Selection
11 = Continuous Conversion mode or continuous conversion cycle in SCAN mode
10 = One-shot conversion or one-shot cycle in SCAN mode. It sets ADC_MODE[1:0] to ‘10’ (standby) at
the end of the conversion or at the end of the conversion cycle in SCAN mode.
0x = One-shot conversion or one-shot cycle in SCAN mode. It sets ADC_MODE[1:0] to ‘0x’ (ADC
Shutdown) at the end of the conversion or at the end of the conversion cycle in SCAN mode (default).
bit 5-4
DATA_FORMAT[1:0]: ADC Output Data Format Selection
11 = 32-bit (25-bit right justified data + Channel ID): CHID[3:0] + SGN extension (4 bits) + 24-bit ADC
data. It allows overrange with the SGN extension.
10 = 32-bit (25-bit right justified data): SGN extension (8-bit) + 24-bit ADC data. It allows overrange with
the SGN extension.
01 = 32-bit (24-bit left justified data): 24-bit ADC data + 0x00 (8-bit). It does not allow overrange (ADC
code locked to 0xFFFFFF or 0x800000).
00 = 24-bit (default ADC coding): 24-bit ADC data. It does not allow overrange (ADC code locked to
0xFFFFFF or 0x800000).
bit 3
CRC_FORMAT: CRC Checksum Format Selection on Read Communications
(it does not affect CRCCFG coding)
1 = 32-bit wide (CRC-16 followed by 16 zeros)
0 = 16-bit wide (CRC-16 only) (default)
bit 2
EN_CRCCOM: CRC Checksum Selection on Read Communications
(it does not affect CRCCFG calculations)
1 = CRC on communications enabled
0 = CRC on communications disabled (default)
bit 1
EN_OFFCAL: Enable Digital Offset Calibration
1 = Enabled
0 = Disabled (default)
bit 0
EN_GAINCAL: Enable Digital Gain Calibration
1 = Enabled
0 = Disabled (default)
DS20006391A-page 94
2020 Microchip Technology Inc.
MCP3561/2/4R
8.6
IRQ REGISTER
Name
Bits
Address
Cof
IRQ
8
0x5
R/W
REGISTER 8-6:
U-0
—
IRQ: INTERRUPT REQUEST REGISTER
R-1
R-1
R-1
DR_STATUS CRCCFG_STATUS POR_STATUS
R/W-0
R/W-0
IRQ_MODE[1:0]
(1)
R/W-1
R/W-1
EN_FASTCMD
EN_STP
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
Unimplemented: Read as ‘0’
bit 6
DR_STATUS: Data Ready Status Flag
1 = ADCDATA has not been updated since last reading or last reset (default)
0 = New ADCDATA ready for reading
bit 5
CRCCFG_STATUS: CRC Error Status Flag Bit for Internal Registers
1 = CRC error has not occurred for the Configuration registers (default)
0 = CRC error has occurred for the Configuration registers
bit 4
POR_STATUS: POR Status Flag
1 = POR has not occurred since the last reading (default)
0 = POR has occurred since the last reading
bit 3-2
IRQ_MODE[1:0]: Configuration for the IRQ/MDAT Pin(1)
IRQ_MODE[1]: IRQ/MDAT Selection
1 = MDAT output is selected. Only POR and CRC interrupts can be present on this pin and take priority
over the MDAT output.
0 = IRQ output is selected. All interrupts can appear on the IRQ/MDAT pin.
IRQ_MODE[0]: IRQ Pin Inactive State Selection
1 = The Inactive state is logic high (does not require a pull-up resistor to DVDD)
0 = The Inactive state is high-Z (requires a pull-up resistor to DVDD) (default)
bit 1
EN_FASTCMD: Enable Fast Commands in the COMMAND Byte
1 = Fast commands are enabled (default)
0 = Fast commands are disabled
bit 0
EN_STP: Enable Conversion Start Interrupt Output
1 = Enabled (default)
0 = Disabled
Note 1:
When IRQ_MODE[1:0] = 10 or 11, the modulator output codes (MDAT stream) are available at both the
MDAT pin and ADCDATA register (0x0).
2020 Microchip Technology Inc.
DS20006391A-page 95
MCP3561/2/4R
8.7
MULTIPLEXER (MUX) REGISTER
Name
Bits
Address
Cof
MUX
8
0x6
R/W
REGISTER 8-7:
R/W-0
MUX: MULTIPLEXER REGISTER
R/W-0
R/W-0
R/W-0
R/W-0
MUX_VIN+[3:0](2,3)
R/W-0
R/W-0
R/W-1
MUX_VIN-[3:0](2,3)
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
Bit 7-4
MUX_VIN+ Input Selection(2,3)
1111 = Internal VCM
1110 = Internal Temperature Sensor Diode M (Temp Diode M)(1)
1101 = Internal Temperature Sensor Diode P (Temp Diode P)(1)
1100 = REFIN1011 = REFIN+/OUT
1010 = Reserved (do not use)
1001 = AVDD
1000 = AGND
0111 = CH7
0110 = CH6
0101 = CH5
0100 = CH4
0011 = CH3
0010 = CH2
0001 = CH1
0000 = CH0 (default)
Bit 3-0
MUX_VIN- Input Selection(2,3)
1111 = Internal VCM
1110 = Internal Temperature Sensor Diode M (Temp Diode M)(1)
1101 = Internal Temperature Sensor Diode P (Temp Diode P)(1)
1100 = REFIN1011 = REFIN+/OUT
1010 = Reserved (do not use)
1001 = AVDD
1000 = AGND
0111 = CH7
0110 = CH6
0101 = CH5
0100 = CH4
0011 = CH3
0010 = CH2
0001 = CH1 (default)
0000 = CH0
Note 1:
2:
3:
x = Bit is unknown
Selects the internal temperature sensor diode and forces a fixed current through it. For a correct
temperature reading, the MUX[7:0] selection should be equal to 0xDE.
For MCP3562R, the codes, ‘0111/0110/0101/0100’, correspond to a floating input and should be
avoided.
For MCP3561R, the codes, ‘0111/0110/0101/0100/0011/0010’, correspond to a floating input and
should be avoided.
DS20006391A-page 96
2020 Microchip Technology Inc.
MCP3561/2/4R
8.8
SCAN REGISTER
Name
Bits
Address
Cof
SCAN
24
0x7
R/W
REGISTER 8-8:
R/W-0
SCAN: SCAN MODE SETTINGS REGISTER
R/W-0
R/W-0
DLY[2:0]
R/W-0
U-0
RESERVED
—
bit 23
bit 16
R/W-0
R/W-0
R/W-0
R/W-0
OFFSET
VCM
AVDD
TEMP
R/W-0
R/W-0
R/W-0
R/W-0
SCAN_DIFF_CH[D:A]
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
SCAN_SE_CH[7:0]
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
Bit 23-21
x = Bit is unknown
DLY[2:0]: Delay Time (TDLY_SCAN) Between Each Conversion During a SCAN Cycle
111 = 512 * DMCLK
110 = 256 * DMCLK
101 = 128 * DMCLK
100 = 64 * DMCLK
011 = 32 * DMCLK
010 = 16 * DMCLK
001 = 8 * DMCLK
000 = 0: No delay (default)
Bit 20
RESERVED: Should be set to ‘0’
Bit 19-16
Unimplemented: Read as ‘0’
Bit 15-0
SCAN Channel Selection (see Table 5-15 for a complete description)
2020 Microchip Technology Inc.
DS20006391A-page 97
MCP3561/2/4R
8.9
TIMER REGISTER
Name
Bits
Address
Cof
TIMER
24
0x8
R/W
REGISTER 8-9:
TIMER: TIMER DELAY VALUE REGISTER
R/W-0
TIMER[23:0]
bit 23
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
Bit 23-0
x = Bit is unknown
TIMER[23:0]: Selection Bits for the Time Interval (TTIMER_SCAN) Between Two Consecutive SCAN Cycles
(when CONV_MODE[1:0] = 11):
0xFFFFFF: TTIMER_SCAN = 16777215 * DMCLK periods
0xFFFFFE: TTIMER_SCAN = 16777214 * DMCLK periods
•
•
•
0x000002: TTIMER_SCAN = 2 * DMCLK periods
0x000001: TTIMER_SCAN = 1 * DMCLK periods
0x000000: TTIMER_SCAN = 0 (No delay) – default
DS20006391A-page 98
2020 Microchip Technology Inc.
MCP3561/2/4R
8.10
OFFSETCAL REGISTER
Name
Bits
Address
Cof
OFFSETCAL
24
0x9
R/W
REGISTER 8-10:
OFFSETCAL: OFFSET CALIBRATION REGISTER
R/W-0
OFFSETCAL[23:0]
bit 23
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
Bit 23-0
8.11
x = Bit is unknown
OFFSETCAL[23:0]: Offset Error Digital Calibration Code (two’s complement, MSb first coding)
See Sections 5.13 “Digital System Offset and Gain Calibrations”.
GAINCAL REGISTER
Name
Bits
Address
Cof
GAINCAL
24
0xA
R/W
REGISTER 8-11:
GAINCAL: GAIN CALIBRATION REGISTER
R/W-1
R/W-0
GAINCAL[23:0]
bit 23
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
Bit 23-0
x = Bit is unknown
GAINCAL[23:0]: Gain Error Digital Calibration Code (unsigned, MSb first coding)
The GAINCAL default value is 800000, which provides a gain of 1x. See Section 5.13 “Digital
System Offset and Gain Calibrations”.
2020 Microchip Technology Inc.
DS20006391A-page 99
MCP3561/2/4R
8.12
RESERVED REGISTER
Name
Bits
Address
Cof
RESERVED
24
0xB
R/W
REGISTER 8-12:
RESERVED REGISTER
R/W-0x900000
RESERVED[23:0]
bit 23
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
Bit 23-0
8.13
x = Bit is unknown
RESERVED[23:0]: Should be set to 0x900000
RESERVED REGISTER
Name
Bits
Address
Cof
RESERVED
8
0xC
R/W
REGISTER 8-13:
RESERVED REGISTER
R/W-0x30
RESERVED[7:0]
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
Bit 7-0
x = Bit is unknown
RESERVED[7:0]: Should be set to 0x30
DS20006391A-page 100
2020 Microchip Technology Inc.
MCP3561/2/4R
8.14
LOCK REGISTER
Name
Bits
Address
Cof
LOCK
8
0xD
R/W
REGISTER 8-14:
R/W-1
LOCK: SPI WRITE MODE LOCKING PASSWORD VALUE REGISTER
R/W-0
R/W-1
R/W-0
R/W-0
R/W-1
R/W-0
R/W-1
LOCK[7:0]
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
Bit 7-0
8.15
x = Bit is unknown
LOCK[7:0]: Write Access Password Entry Code
0xA5 = Write access is allowed on the full register map. CRC on register map values is not calculated
(CRCCFG[15:0] = 0x0000) – Default.
Any code except 0xA5 = Write access is not allowed on the full register map. Only the LOCK register
is writable. CRC on register map is calculated continuously only when DMCLK is running.
RESERVED REGISTER
Name
Bits
Address
Cof
RESERVED
16
0xE
R/W
REGISTER 8-15:
RESERVED REGISTER
R/W (default depends on product denomination)
RESERVED[15:0]
bit 15
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
Bit 15-0
x = Bit is unknown
RESERVED[15:0]: Should be set to
MCP3561R: 0x000C
MCP3562R: 0x000D
MCP3564R: 0x000F
2020 Microchip Technology Inc.
DS20006391A-page 101
MCP3561/2/4R
8.16
CRCCFG REGISTER
Name
Bits
Address
Cof
CRCCFG
16
0xF
R
REGISTER 8-16:
CRCCFG: CRC CONFIGURATION REGISTER
R-0
CRCCFG[15:0]
bit 15
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
Bit 15-0
x = Bit is unknown
CRCCFG[15:0]: CRC-16 Checksum Value
CRC-16 checksum is continuously calculated internally based on the register map configuration
settings when the device is locked (LOCK[7:0] ≠ 0xA5).
DS20006391A-page 102
2020 Microchip Technology Inc.
MCP3561/2/4R
9.0
PACKAGING INFORMATION
9.1
Package Marking Information(1)
20-Lead UQFN (3x3x0.55 mm)
PIN 1
Example
XXX
YYWW
NNN
PIN 1
AAJ
2053
256
Part Number
Code
SPI Device Address
MCP3561RT-E/NC
AAJ
01(2)
MCP3562RT-E/NC
AAK
01(2)
MCP3564RT-E/NC
AAL
01(2)
20-Lead TSSOP (6.4x6.4x1 mm)
Example
XXXXXXXX
XXXXXNNN
MCP3564R
EST e3 256
YYWW
2053
Legend: XX...X
Y
YY
WW
NNN
e3
*
Customer-specific information
Year code (last digit of calendar year)
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code
Pb-free JEDEC designator for Matte Tin (Sn)
This package is Pb-free. The Pb-free JEDEC designator ( e3 )
can be found on the outer packaging for this package.
Note 1: In the event the full Microchip part number cannot be marked on one line, it
will be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
2: Denotes the device default SPI Address option. The device only responds
to SPI commands if CMD[7:6] matches the SPI device address for each
command (see Section 6.2.2, Device Address Bits (CMD[7:6])). Contact
Microchip Sales for other device address option ordering procedure.
2020 Microchip Technology Inc.
DS20006391A-page 103
MCP3561/2/4R
20-Lead Ultra Thin Plastic Quad Flat, No Lead Package 1& - 3x3 mm Body [UQFN]
(Formerly Q3DE; SST Legacy Package)
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
D
NOTE 1
A
B
N
1
2
E
(DATUM B)
(DATUM A)
2X
0.075 C
2X
TOP VIEW
0.075 C
0.10 C
C
SEATING
PLANE
A1
A
20X
(A3)
SIDE VIEW
0.08 C
0.10
C A B
D2
0.10
See
Detail A
C A B
e
2
E2
2
1
NOTE 1
K
N
20X b
0.10
0.05
e
C A B
C
BOTTOM VIEW
Microchip Technology Drawing C04-264A Sheet 1 of 2
DS20006391A-page 104
2020 Microchip Technology Inc.
MCP3561/2/4R
20-Lead Ultra Thin Plastic Quad Flat, No Lead Package 1& - 3x3 mm Body [UQFN]
(Formerly Q3DE; SST Legacy Package)
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
(b) b1
L
DETAIL A
Units
Dimension Limits
N
Number of Terminals
e
Pitch
A
Overall Height
Standoff
A1
A3
Terminal Thickness
Overall Length
D
Exposed Pad Length
D2
E
Overall Width
E2
Exposed Pad Width
b
Terminal Width (Inner)
b1
Terminal Width (Outer)
L
Terminal Length
K
Terminal-to-Exposed-Pad
MIN
0.50
0.00
1.60
1.60
0.15
0.35
0.20
MILLIMETERS
NOM
20
0.40 BSC
0.55
0.02
0.15 REF
3.00 BSC
1.70
3.00 BSC
1.70
0.15 REF
0.20
0.40
-
MAX
0.60
0.05
1.80
1.80
0.25
0.45
-
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. Package is saw singulated
3. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
Microchip Technology Drawing C04-264A Sheet 2 of 2
2020 Microchip Technology Inc.
DS20006391A-page 105
MCP3561/2/4R
20-Lead Ultra Thin Plastic Quad Flat, No Lead Package 1& - 3x3 mm Body [UQFN]
(Formerly Q3DE; SST Legacy Package)
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
C1
X2
EV
20
ØV
1
2
C2 Y2
EV
G1
Y1
X1
E
SILK SCREEN
RECOMMENDED LAND PATTERN
Units
Dimension Limits
Contact Pitch
E
X2
Optional Center Pad Width
Optional Center Pad Length
Y2
Contact Pad Spacing
C1
Contact Pad Spacing
C2
Contact Pad Width (X20)
X1
Contact Pad Length (X20)
Y1
Contact Pad to Center Pad (X20)
G1
Thermal Via Diameter
V
Thermal Via Pitch
EV
MIN
MILLIMETERS
NOM
0.40 BSC
MAX
1.80
1.80
3.00
3.00
0.20
0.80
0.20
0.30
1.00
Notes:
1. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
2. For best soldering results, thermal vias, if used, should be filled or tented to avoid solder loss during
reflow process
Microchip Technology Drawing C04-2264A
DS20006391A-page 106
2020 Microchip Technology Inc.
MCP3561/2/4R
2020 Microchip Technology Inc.
DS20006391A-page 107
MCP3561/2/4R
DS20006391A-page 108
2020 Microchip Technology Inc.
MCP3561/2/4R
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2020 Microchip Technology Inc.
DS20006391A-page 109
MCP3561/2/4R
NOTES:
DS20006391A-page 110
2020 Microchip Technology Inc.
MCP3561/2/4 R
APPENDIX A:
REVISION HISTORY
Revision A (August 2020)
• Initial release of this document.
2020 Microchip Technology Inc.
DS20006391A-page 111
MCP3561/2/4 R
NOTES:
2020 Microchip Technology Inc.
DS20006391A-page 112
MCP3561/2/4 R
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
X (1)
PART NO.
X
/XX
Temperature
Range
Package
Examples:
a) MCP3561RT-E/NC:
Device
Tape and
Reel
Device:
MCP3561/2/4 R: One/Two/Four Differential Channel,
High-Precision 24-bit Delta-Sigma ADCs
with SPI device address ‘01’.
Tape and Reel:
T
=
Tape and Reel
Blank = Standard packaging (tube or tray)
Temperature
Range:
E
Package:
NC =
b) MCP3562RT-E/NC:
c) MCP3564RT-E/NC:
ST
=
=
-40°C to +125°C (Extended)
Ultra Small, No Lead Package (UQFN),
3 x 3 x 0.55 mm, 20-Lead
Plastic Thin Shrink Small Outline (TSSOP),
6.4 x 6.4 x 1 mm, 20-Lead
d) MCP3561RT-E/ST:
e) MCP3562R-E/ST:
f) MCP3564R-E/ST:
Note
2020 Microchip Technology Inc.
Single-Channel ADC
Tape and Reel,
Extended Temperature,
20LD UQFN.
Dual-Channel ADC
Tape and Reel,
Extended Temperature,
20LD UQFN.
Quad-Channel ADC
Tape and Reel,
Extended Temperature,
20LD UQFN.
Single-Channel ADC
Tape and Reel,
Extended Temperature,
20LD TSSOP.
Dual-Channel ADC
Standard Packaging,
Extended Temperature,
20LD TSSOP.
Quad-Channel ADC
Standard Packaging,
Extended Temperature,
20LD TSSOP.
1:
Tape and Reel identifier only appears in the
catalog part number description. This identifier is used for ordering purposes and is not
printed on the device package. Check with
your Microchip Sales Office for package
availability with the Tape and Reel option.
2:
Device SPI Address ‘01’ is the default
address option. Contact Microchip Sales for
other device address option ordering
procedure.
DS20006391A-page 113
MCP3561/2/4 R
NOTES:
DS20006391A-page 114
2020 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
•
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights unless otherwise stated.
Trademarks
The Microchip name and logo, the Microchip logo, Adaptec,
AnyRate, AVR, AVR logo, AVR Freaks, BesTime, BitCloud, chipKIT,
chipKIT logo, CryptoMemory, CryptoRF, dsPIC, FlashFlex,
flexPWR, HELDO, IGLOO, JukeBlox, KeeLoq, Kleer, LANCheck,
LinkMD, maXStylus, maXTouch, MediaLB, megaAVR, Microsemi,
Microsemi logo, MOST, MOST logo, MPLAB, OptoLyzer,
PackeTime, PIC, picoPower, PICSTART, PIC32 logo, PolarFire,
Prochip Designer, QTouch, SAM-BA, SenGenuity, SpyNIC, SST,
SST Logo, SuperFlash, Symmetricom, SyncServer, Tachyon,
TempTrackr, TimeSource, tinyAVR, UNI/O, Vectron, and XMEGA
are registered trademarks of Microchip Technology Incorporated in
the U.S.A. and other countries.
APT, ClockWorks, The Embedded Control Solutions Company,
EtherSynch, FlashTec, Hyper Speed Control, HyperLight Load,
IntelliMOS, Libero, motorBench, mTouch, Powermite 3, Precision
Edge, ProASIC, ProASIC Plus, ProASIC Plus logo, Quiet-Wire,
SmartFusion, SyncWorld, Temux, TimeCesium, TimeHub,
TimePictra, TimeProvider, Vite, WinPath, and ZL are registered
trademarks of Microchip Technology Incorporated in the U.S.A.
Adjacent Key Suppression, AKS, Analog-for-the-Digital Age, Any
Capacitor, AnyIn, AnyOut, BlueSky, BodyCom, CodeGuard,
CryptoAuthentication, CryptoAutomotive, CryptoCompanion,
CryptoController, dsPICDEM, dsPICDEM.net, Dynamic Average
Matching, DAM, ECAN, EtherGREEN, In-Circuit Serial
Programming, ICSP, INICnet, Inter-Chip Connectivity, JitterBlocker,
KleerNet, KleerNet logo, memBrain, Mindi, MiWi, MPASM, MPF,
MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach,
Omniscient Code Generation, PICDEM, PICDEM.net, PICkit,
PICtail, PowerSmart, PureSilicon, QMatrix, REAL ICE, Ripple
Blocker, SAM-ICE, Serial Quad I/O, SMART-I.S., SQI,
SuperSwitcher, SuperSwitcher II, Total Endurance, TSHARC,
USBCheck, VariSense, ViewSpan, WiperLock, Wireless DNA, and
ZENA are trademarks of Microchip Technology Incorporated in the
U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated in
the U.S.A.
The Adaptec logo, Frequency on Demand, Silicon Storage
Technology, and Symmcom are registered trademarks of Microchip
Technology Inc. in other countries.
GestIC is a registered trademark of Microchip Technology Germany
II GmbH & Co. KG, a subsidiary of Microchip Technology Inc., in
other countries.
All other trademarks mentioned herein are property of their
respective companies.
© 2020, Microchip Technology Incorporated, All Rights Reserved.
For information regarding Microchip’s Quality Management Systems,
please visit www.microchip.com/quality.
2020 Microchip Technology Inc.
ISBN: 978-1-5224-6672-7
DS20006391A-page 115
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DS20006391A-page 116
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2020 Microchip Technology Inc.
02/28/20
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