MCP3910A1T-E/ML

MCP3910 3V Two-Channel Analog Front End Features: Description: • Two Synchronous Sampling 24-Bit Resolution Delta-Sigma A/D Converters • 93.5 dB SINAD, -107 dBc Total Harmonic Distortion (THD) (up to 35th harmonic), 112 dB Spurious-Free Dynamic Range (SFDR) for Each Channel • Flexible Serial Interface that Includes Both SPI and a Simple Two-Wire Interface Ideal for Polyphase Shunt Energy Meters • Enables 0.1% Typical Active Power Measurement Error Over a 10,000:1 Dynamic Range • Advanced Security Features: - 16-Bit Cyclic Redundancy Check (CRC) Checksum on All Communications for Secure Data Transfers - 16-Bit Cyclic Redundancy Check (CRC) Checksum and Interrupt Alert for Register Map Configuration - Register Map Lock with 8-Bit Secure Key • 2.7V-3.6V AVDD, DVDD • Programmable Data Rate, Up to 125 ksps: - 4 MHz Maximum Sampling Frequency - 16 MHz Maximum Master Clock • Oversampling Ratio, Up to 4096 • Ultra Low-Power Shutdown Mode with < 10 µA • -122 dB Crosstalk between Channels • Low-Drift 1.2V Internal Voltage Reference: 9 ppm/°C • Differential Voltage Reference Input Pins • High-Gain Programmable Gain Amplifier (PGA) on Each Channel (up to 32 V/V) • Phase Delay Compensation with 1 µs Time Resolution • Separate Data Ready Pin for Easy Synchronization • Individual 24-Bit Digital Offset and Gain Error Correction for Each Channel • High-Speed 20 MHz SPI Interface with Mode 0,0 and 1,1 Compatibility • Continuous Read/Write Modes for Minimum Communication with Dedicated 16-/32-Bit Modes • Available in 20-Lead QFN and SSOP Packages • Extended Temperature Range: -40°C to +125°C (All Specifications are Valid Down to -45°C Operation) The MCP3910 is a 3V two-channel Analog Front End (AFE), containing two synchronous sampling Delta-Sigma, Analog-to-Digital Converters (ADC), two Programmable Gain Amplifiers (PGA), phase delay compensation block, low-drift internal voltage reference, Digital Offset and Gain Errors Calibration registers and high-speed 20 MHz SPI-compatible serial interface. The MCP3910 ADCs are fully configurable with features such as: 16-/24-bit resolution, Oversampling Ratio (OSR) from 32 to 4096, gain from 1x to 32x, independent shutdown and Reset, dithering and auto-zeroing. Communication is largely simplified with 8-bit commands, including various continuous Read/ Write modes and 16-/24-/32-bit data formats that can be accessed by the Direct Memory Access (DMA) of an 8, 16 or 32-bit MCU. It also includes a separate Data Ready pin that can directly be connected to an Interrupt Request (IRQ) input of an MCU. The MCP3910 includes advanced security features to secure the communications and the configuration settings, such as a CRC-16 checksum on both serial data outputs and on the static register map configuration. It also includes a register map lock through an 8-bit password to stop unwanted WRITE commands from processing. For polyphase shunt-based energy meters, the MCP3910 two-wire serial interface greatly reduces system cost, requiring only a single bidirectional isolator per phase. The MCP3910 is capable of interfacing a variety of voltage and current sensors, including shunts, current transformers, Rogowski coils and Hall effect sensors.  2012-2020 Microchip Technology Inc. Applications: • • • • • • • Single-Phase and Polyphase Energy Meters Energy Metering and Power Measurement Automotive Portable Instrumentation Medical and Power Monitoring Audio/Voice Recognition Isolated Sensor Applications DS20005116D-page 1 MCP3910 Package Type SDO SDI/OSR1 RESET/OSR0 20 19 18 17 16 CH0+ 1 15 SCK/MCLK CH0- 2 14 CS/BOOST EP 21 CH1- 3 13 OSC2/MODE 12 OSC1/CLKI/GAIN0 AGND 5 11 DR/GAIN1 * Includes Exposed Thermal Pad (EP); see Table 3-1. 8 9 10 MDAT0 7 MDAT1 6 DGND CH1+ 4 REFIN- REFIN+/OUT REFIN- SDI/OSR1 SDO SCK/MCLK CS/BOOST OSC2/MODE OSC1/CLKI/GAIN0 DR/GAIN1 MDAT0 MDAT1 DGND AVDD CH0+ CH0CH1CH1+ AGND 20 19 18 17 16 15 14 13 12 11 1 2 3 4 5 6 7 8 9 10 REFIN+/OUT RESET/OSR0 DVDD AVDD MCP3910 4 x 4 QFN* DVDD MCP3910 SSOP Functional Block Diagram REFIN+/OUT REFIN- DVDD AVDD Voltage Reference + – AMCLK VREFEXT V REF DMCLK/DRCLK VREF- VREF+ ANALOG DIGITAL DMCLK SINC 3+ SINC 1 CH0+ + CH0- – PGA CH1+ + CH1- – PGA MOD Modulator DUAL OFFCAL_CH0 [23:0] GAINCAL_CH0 [23:0] + X Phase Shifter MOD Modulator OFFCAL_CH1 [23:0] GAINCAL_CH1 [23:0] + X MCLK OSC1/CLKI/GAIN0 OSC2/MODE OSR[2:0] PRE[1:0] DATA_CH0 [23:0] PHASE [11:0] DR/GAIN1 SDO Digital Interfaces (SPI & Two-Wire) DATA_CH1 [23:0] RESET/OSR0 SDI/OSR1 SCK CS/BOOST SINC 3+ SINC 1 EN_MDAT ADC Modulator Output Block MOD[7:0] POR AVDD Monitoring MDAT0 MDAT1 POR DVDD Monitoring A GND DS20005116D-page 2 Xtal Oscillator Clock Generation D GND  2012-2020 Microchip Technology Inc. MCP3910 1.0 † Notice: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions, above those indicated in the operational listings of this specification, is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings† VDD ..................................................................... -0.3V to 4.0V Digital inputs and outputs w.r.t. AGND ................ --0.3V to 4.0V Analog input w.r.t. AGND ..................................... ....-2V to +2V VREF input w.r.t. AGND .............................. -0.6V to VDD + 0.6V Storage temperature .....................................-65°C to +150°C Ambient temp. with power applied ................-65°C to +125°C Soldering temperature of leads (10 seconds) ............. +300°C ESD on the analog inputs (HBM,MM) ................. 4.0 kV, 200V ESD on all other pins (HBM,MM) ........................ 4.0 kV, 200V 1.1 Electrical Specifications TABLE 1-1: ANALOG SPECIFICATIONS Electrical Specifications: Unless otherwise indicated, all parameters apply at AVDD = DVDD = 3V, MCLK = 4 MHz; PRE[1:0] = 00; OSR = 256; GAIN = 1; VREFEXT = 0, CLKEXT = 1, DITHER[1:0] = 11; BOOST[1:0] = 10, VCM = 0V; TA = -40°C to +125°C (Note 1); VIN = 1.2 VPP = -0.5 dBFS @ 50/60 Hz on all channels. Characteristic Sym. Min. Typ. Max. Units Conditions 24 — — bits OSR = 256 or greater ADC Performance Resolution (No Missing Codes) Sampling Frequency fS(DMCLK) — 1 4 MHz For maximum condition, BOOST[1:0] = 11 Output Data Rate fD(DRCLK) — 4 125 ksps For maximum condition, BOOST[1:0] = 11, OSR = 32 CHn+/- -1 — +1 V All analog input channels measured to AGND IIN — ±1 — nA RESET[1:0] = 11, MCLK running continuously — +600/GAIN mV VREF = 1.2V, proportional to VREF -2 0.2 2 mV Note 5 — 0.5 — µV/°C Analog Input Absolute Voltage on CHn+/-, n Between 0 and 1 Pins Analog Input Leakage Current Differential Input Voltage Range Offset Error (CHn+ – CHn-) -600/GAIN VOS Offset Error Drift Note 1: 2: 3: 4: 5: 6: 7: All specifications are valid down to -45°C operation. This specification implies that the ADC output is valid over this entire differential range and that there is no distortion or instability across this input range. Dynamic Performance specified at -0.5 dB below the maximum signal range, VIN = 1.2 VPP = 424 mVRMS, VREF = 1.2V @ 50/60 Hz. See Section 4.0 “Terminology and Formulas” for definition. This parameter is established by characterization and not 100% tested. For these operating currents, the following Configuration bit settings apply: SHUTDOWN[1:0] = 00, RESET[1:0] = 00, VREFEXT = 0, CLKEXT = 0. For these operating currents, the following Configuration bit settings apply: SHUTDOWN[1:0] = 11, VREFEXT = 1, CLKEXT = 1. Applies to all gains. Offset and gain errors depend on PGA gain setting. See Section 2.0 “Typical Performance Curves” for typical performance. Outside this range, the ADC accuracy is not specified. An extended input range of ±2V can be applied continuously to the part with no damage. For proper operation and for optimizing the ADC accuracy, AMCLK should be limited to the maximum frequency, defined in Table 5-2, as a function of the BOOST and PGA setting chosen. MCLK can take larger values as long as the prescaler settings (PRE[1:0]) limit AMCLK = MCLK/PRESCALE within the defined range in Table 5-2.  2012-2020 Microchip Technology Inc. DS20005116D-page 3 MCP3910 TABLE 1-1: ANALOG SPECIFICATIONS (CONTINUED) Electrical Specifications: Unless otherwise indicated, all parameters apply at AVDD = DVDD = 3V, MCLK = 4 MHz; PRE[1:0] = 00; OSR = 256; GAIN = 1; VREFEXT = 0, CLKEXT = 1, DITHER[1:0] = 11; BOOST[1:0] = 10, VCM = 0V; TA = -40°C to +125°C (Note 1); VIN = 1.2 VPP = -0.5 dBFS @ 50/60 Hz on all channels. Characteristic Gain Error Sym. Min. Typ. Max. Units GE -6 — +6 % — 1 — ppm/°C Gain Error Drift Conditions Note 5 Integral Nonlinearity INL — 5 — ppm Measurement Error ME — 0.1 — % Measured with a 10,000:1 dynamic range (from 600 mVPeak to 60 µVPeak), AVDD= DVDD = 3V, measurement points averaging time: 20 seconds Differential Input Impedance ZIN 232 — — k G = 1, proportional to 1/AMCLK 142 — — k G = 2, proportional to 1/AMCLK 72 — — k G = 4, proportional to 1/AMCLK 38 — — k G = 8, proportional to 1/AMCLK 36 — — k G = 16, proportional to 1/AMCLK 33 — — k G = 32, proportional to 1/AMCLK Signal-to-Noise and Distortion Ratio (Note 2) SINAD 92 93.5 — dB Total Harmonic Distortion (Note 2) THD — -107 -103 dBc Signal-to-Noise Ratio (Note 2) SNR 92 94 — dB SFDR — 112 — dBFS Spurious-Free Dynamic Range (Note 2) Crosstalk (50, 60 Hz) Includes the first 35 harmonics CTALK — -122 — dB AC Power Supply Rejection AC PSRR — -73 — dB AVDD = DVDD = 3V + 0.6VPP, 50/60 Hz, 100/120 Hz DC Power Supply Rejection DC PSRR — -73 — dB AVDD = DVDD = 2.7V to 3.6V DC Common-Mode Rejection DC CMRR — -105 — dB VCM from -1V to +1V Note 1: 2: 3: 4: 5: 6: 7: All specifications are valid down to -45°C operation. This specification implies that the ADC output is valid over this entire differential range and that there is no distortion or instability across this input range. Dynamic Performance specified at -0.5 dB below the maximum signal range, VIN = 1.2 VPP = 424 mVRMS, VREF = 1.2V @ 50/60 Hz. See Section 4.0 “Terminology and Formulas” for definition. This parameter is established by characterization and not 100% tested. For these operating currents, the following Configuration bit settings apply: SHUTDOWN[1:0] = 00, RESET[1:0] = 00, VREFEXT = 0, CLKEXT = 0. For these operating currents, the following Configuration bit settings apply: SHUTDOWN[1:0] = 11, VREFEXT = 1, CLKEXT = 1. Applies to all gains. Offset and gain errors depend on PGA gain setting. See Section 2.0 “Typical Performance Curves” for typical performance. Outside this range, the ADC accuracy is not specified. An extended input range of ±2V can be applied continuously to the part with no damage. For proper operation and for optimizing the ADC accuracy, AMCLK should be limited to the maximum frequency, defined in Table 5-2, as a function of the BOOST and PGA setting chosen. MCLK can take larger values as long as the prescaler settings (PRE[1:0]) limit AMCLK = MCLK/PRESCALE within the defined range in Table 5-2. DS20005116D-page 4  2012-2020 Microchip Technology Inc. MCP3910 TABLE 1-1: ANALOG SPECIFICATIONS (CONTINUED) Electrical Specifications: Unless otherwise indicated, all parameters apply at AVDD = DVDD = 3V, MCLK = 4 MHz; PRE[1:0] = 00; OSR = 256; GAIN = 1; VREFEXT = 0, CLKEXT = 1, DITHER[1:0] = 11; BOOST[1:0] = 10, VCM = 0V; TA = -40°C to +125°C (Note 1); VIN = 1.2 VPP = -0.5 dBFS @ 50/60 Hz on all channels. Characteristic Sym. Min. Typ. Max. Units Conditions VREF 1.176 1.2 1.224 V TCVREF — 9 — ZOUTVREF — 0.6 — k VREFEXT = 0 AIDDVREF — 54 — µA VREFEXT = 0, SHUTDOWN[1:0] = 11 — — 10 pF Differential Input Voltage Range (VREF+ – VREF-) VREF 1.1 — 1.3 V VREFEXT = 1 Absolute Voltage on REFIN+ Pin VREF+ VREF- + 1.1 — VREF- + 1.3 V VREFEXT = 1 Absolute Voltage on REFIN- Pin VREF- -0.1 — +0.1 V REFIN- should be connected to AGND when VREFEXT = 0 — 20 MHz CLKEXT = 1 (Note 7) Internal Voltage Reference Tolerance Temperature Coefficient Output Impedance Internal Voltage Reference Operating Current VREFEXT = 0, TA = +25°C only ppm/°C TA = -45°C to +125°C, VREFEXT = 0 Voltage Reference Input Input Capacitance Master Clock Input Master Clock Input Frequency Range fMCLK Crystal Oscillator Operating Frequency Range fXTAL 1 — 20 MHz CLKEXT = 0 (Note 7) AMCLK — — 16 MHz Note 7 DIDDXTAL — 80 — µA Operating Voltage, Analog AVDD 2.7 — 3.6 V Operating Voltage, Digital DVDD 2.7 — 3.6 V Operating Current, Analog (Note 3) IDD,A — 1.5 1.95 mA BOOST[1:0] = 00 — 1.8 2.3 mA BOOST[1:0] = 01 — 2.5 3.2 mA BOOST[1:0] = 10 — 4.4 5.5 mA BOOST[1:0] = 11 Analog Master Clock Crystal Oscillator Operating Current CLKEXT = 0 Power Supply Note 1: 2: 3: 4: 5: 6: 7: All specifications are valid down to -45°C operation. This specification implies that the ADC output is valid over this entire differential range and that there is no distortion or instability across this input range. Dynamic Performance specified at -0.5 dB below the maximum signal range, VIN = 1.2 VPP = 424 mVRMS, VREF = 1.2V @ 50/60 Hz. See Section 4.0 “Terminology and Formulas” for definition. This parameter is established by characterization and not 100% tested. For these operating currents, the following Configuration bit settings apply: SHUTDOWN[1:0] = 00, RESET[1:0] = 00, VREFEXT = 0, CLKEXT = 0. For these operating currents, the following Configuration bit settings apply: SHUTDOWN[1:0] = 11, VREFEXT = 1, CLKEXT = 1. Applies to all gains. Offset and gain errors depend on PGA gain setting. See Section 2.0 “Typical Performance Curves” for typical performance. Outside this range, the ADC accuracy is not specified. An extended input range of ±2V can be applied continuously to the part with no damage. For proper operation and for optimizing the ADC accuracy, AMCLK should be limited to the maximum frequency, defined in Table 5-2, as a function of the BOOST and PGA setting chosen. MCLK can take larger values as long as the prescaler settings (PRE[1:0]) limit AMCLK = MCLK/PRESCALE within the defined range in Table 5-2.  2012-2020 Microchip Technology Inc. DS20005116D-page 5 MCP3910 TABLE 1-1: ANALOG SPECIFICATIONS (CONTINUED) Electrical Specifications: Unless otherwise indicated, all parameters apply at AVDD = DVDD = 3V, MCLK = 4 MHz; PRE[1:0] = 00; OSR = 256; GAIN = 1; VREFEXT = 0, CLKEXT = 1, DITHER[1:0] = 11; BOOST[1:0] = 10, VCM = 0V; TA = -40°C to +125°C (Note 1); VIN = 1.2 VPP = -0.5 dBFS @ 50/60 Hz on all channels. Characteristic Operating Current, Digital Sym. Min. Typ. Max. Units Conditions IDD,D — 0.2 0.4 mA MCLK = 4 MHz, proportional to MCLK — 0.7 — mA MCLK = 16 MHz, proportional to MCLK — 1 µA AVDD pin only (Note 4) Shutdown Current, Analog IDDS,A — Shutdown Current, Digital IDDS,D — — 2 µA DVDD pin only (Note 4) Pull-Down Current on OSC2 Pin (External Clock mode) IOSC2 — 35 — µA CLKEXT = 1 Note 1: 2: 3: 4: 5: 6: 7: 1.2 All specifications are valid down to -45°C operation. This specification implies that the ADC output is valid over this entire differential range and that there is no distortion or instability across this input range. Dynamic Performance specified at -0.5 dB below the maximum signal range, VIN = 1.2 VPP = 424 mVRMS, VREF = 1.2V @ 50/60 Hz. See Section 4.0 “Terminology and Formulas” for definition. This parameter is established by characterization and not 100% tested. For these operating currents, the following Configuration bit settings apply: SHUTDOWN[1:0] = 00, RESET[1:0] = 00, VREFEXT = 0, CLKEXT = 0. For these operating currents, the following Configuration bit settings apply: SHUTDOWN[1:0] = 11, VREFEXT = 1, CLKEXT = 1. Applies to all gains. Offset and gain errors depend on PGA gain setting. See Section 2.0 “Typical Performance Curves” for typical performance. Outside this range, the ADC accuracy is not specified. An extended input range of ±2V can be applied continuously to the part with no damage. For proper operation and for optimizing the ADC accuracy, AMCLK should be limited to the maximum frequency, defined in Table 5-2, as a function of the BOOST and PGA setting chosen. MCLK can take larger values as long as the prescaler settings (PRE[1:0]) limit AMCLK = MCLK/PRESCALE within the defined range in Table 5-2. Serial Interface Characteristics TABLE 1-2: SERIAL DC CHARACTERISTICS Electrical Specifications: Unless otherwise indicated, all parameters apply at DVDD = 2.7 to 3.6 V, TA = -40°C to +125°C (Note 1), CLOAD = 30 pF, applies to all digital I/Os. Characteristic Sym. Min. Typ. Max. Units High-Level Input Voltage Low-Level Input Voltage VIH VIL 0.7 DVDD — — — — 0.3 DVDD V V Schmitt triggered Schmitt triggered Input Leakage Current ILI — — ±1 µA CS = DVDD, VIN = DGND to DVDD Output Leakage Current ILO — — ±1 µA CS = DVDD, VOUT = DGND or DVDD VHYS — 300 — mV DVDD = 3.3V only (Note 3) VOL — — 0.4 V Hysteresis of Schmitt Trigger Inputs Low-Level Output Voltage Conditions IOL = +1.7 mA, DVDD = 3.3V DVDD – 0.5 — — V IOH = -1.7 mA, DVDD = 3.3V High-Level Output Voltage VOH Internal Capacitance CINT — — 7 pF TA = +25°C, SCK = 1.0 MHz, (All Inputs and Outputs) DVDD = 3.3V (Note 2) Note 1: All specifications are valid down to -45°C operation. 2: This parameter is periodically sampled and not 100% tested. 3: This parameter is established by characterization and not production tested. DS20005116D-page 6  2012-2020 Microchip Technology Inc. MCP3910 TABLE 1-3: SERIAL AC CHARACTERISTICS Electrical Specifications: Unless otherwise indicated, all parameters apply at DVDD = 2.7 to 3.6 V, TA = -40°C to +125°C, GAIN = 1, CLOAD = 30 pF. Characteristic Sym. Min. Typ. Max. Units fSCK — — 20 MHz Serial Clock Frequency CS Setup Time tCSS 25 — — ns CS Hold Time tCSH 50 — — ns CS Disable Time tCSD 50 — — ns Data Setup Time tSU 5 — — ns Data Hold Time tHD 10 — — ns Serial Clock High Time tHI 20 — — ns Serial Clock Low Time tLO 20 — — ns Serial Clock Delay Time tCLD 50 — — ns Serial Clock Enable Time tCLE 50 — — ns Output Valid from SCK Low tDO — — 25 ns Output Hold Time tHO 0 — — ns Output Disable Time tDIS — — 25 ns Reset Pulse Width (RESET) tMCLR 100 — — ns Data Transfer Time to DR (Data Ready) tDODR — — 25 ns Modulator Mode Entry to Modulator Data Present tMODSU — — 100 ns Data Ready Pulse Low Time tDRP — 1/(2 x DMCLK) — µs Two-Wire Mode Enable Time tMODE — — 50 ns Two-Wire Mode Watchdog Timer tWATCH 3.6 — 35 µs Note 1: Conditions Note 1 This parameter is established by characterization and not production tested. TABLE 1-4: TEMPERATURE SPECIFICATIONS Electrical Specifications: Unless otherwise indicated, all parameters apply at AVDD = 2.7 to 3.6V, DVDD = 2.7 to 3.6V. Parameters Sym. Min. Typ. Max. Units Operating Temperature Range TA -40 — +125 °C Storage Temperature Range TA -65 — +150 °C Thermal Resistance, 20-Lead 4x4x0.9 QFN JA — 46.2 — °C/W Thermal Resistance, 20-Lead 5.30 mm SSOP JA — 87.3 — °C/W Conditions Temperature Ranges Notes 1, 2 Thermal Package Resistances Note 1: 2: The internal junction temperature (TJ) must not exceed the absolute maximum specification of +150°C. All specifications are valid down to -45°C operation.  2012-2020 Microchip Technology Inc. DS20005116D-page 7 MCP3910 CS fSCK tHI tCSH tLO Mode 1,1 SCK Mode 0,0 tDO tDIS tHO MSB Out SDO LSB Out Don’t Care SDI FIGURE 1-1: Serial Output Timing Diagram. tCSD CS fSCK tCSS tHI Mode 1,1 tCSH tLO tCLE tCLD SCK Mode 0,0 tSU tHD MSB In SDI LSB In High-Z SDO FIGURE 1-2: Serial Input Timing Diagram. 1/fD tDRP DR tDODR SCK SDO FIGURE 1-3: DS20005116D-page 8 Data Ready Pulse/Sampling Timing Diagram.  2012-2020 Microchip Technology Inc. MCP3910 Timing Waveform for tDO Waveform for tDIS SCK CS VIH tDO 90% SDO SDO tDIS High-Z 10% FIGURE 1-4: Timing Waveforms. AVDD, DVDD OSC2/MODE SPI Mode Two-Wire Mode 0 SCK/MCLK 0 High-Z SDO 0 tMODE FIGURE 1-5: Entering Two-Wire Interface Mode Timing Diagram.  2012-2020 Microchip Technology Inc. DS20005116D-page 9 MCP3910 NOTES: DS20005116D-page 10  2012-2020 Microchip Technology Inc. MCP3910 2.0 TYPICAL PERFORMANCE CURVES Note: The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore outside the warranted range. Note: Unless otherwise indicated, AVDD = 3V, DVDD = 3V; TA = +25°C, MCLK = 4 MHz; PRESCALE = 1; OSR = 256; GAIN = 1; Dithering = Maximum; VIN = -0.5 dBFS @ 60 Hz on all channels, VREFEXT = 0; CLKEXT = 1; BOOST[1:0] = 10. 0 Amplitude (dB) -40 -60 Am mplitud de (dB)) Vin = -0.5 dBFS @ 60 Hz fD = 3.9 ksps OSR = 256 Dithering = Off 16 ksamples FFT -20 -80 -100 -120 -140 140 -160 -180 0 500 1000 1500 2000 0 -20 -40 -60 -80 -100 -120 -140 -160 -180 0 Frequency (Hz) FIGURE 2-1: 500 FIGURE 2-4: Spectral Response. 1000 Frequency (Hz) 1500 2000 Spectral Response. 1.0% 0 -40 -60 Measurement Error (%) Vin = -60 dBFS @ 60 Hz fD = 3.9 ksps OSR = 256 Dithering = Off 16 ksamples FFT 20 -20 Amplitude (dB B) Vin = -60 dBFS @ 60 Hz fD = 3.9 ksps OSR = 256 Dithering = Maximum 16 ksamples FFT -80 -100 -120 -140 -160 -180 0 500 FIGURE 2-2: 1000 1500 Frequency (Hz) 2000 0.5% % Error Channel 0, 1 0.0% -0.5% -1.0% 0.01 0.1 1 10 100 1000 Current Channel Input Amplitude (mVPeak) FIGURE 2-5: Measurement Error with 1-Point Calibration. Spectral Response. Vin = -0.5 dBFS @ 60 Hz fD = 3.9 ksps OSR = 256 Dithering = Maximum 16 ksamples FFT Amplitude (dB) -20 -40 -60 -80 -100 -120 -140 140 Measurement Error (%) 1.0% 0 0.5% % Error Channel 0, 1 0.0% -0.5% -160 -180 0 FIGURE 2-3: 500 1000 Frequency (Hz) 1500 Spectral Response.  2012-2020 Microchip Technology Inc. 2000 -1.0% 0.01 0.1 1 10 100 1000 Current Channel Input Amplitude (mVPeak) FIGURE 2-6: Measurement Error with 2-Point Calibration. DS20005116D-page 11 MCP3910 Unless otherwise indicated, AVDD = 3V, DVDD = 3V; TA = +25°C, MCLK = 4 MHz; PRESCALE = 1; OSR = 256; GAIN = 1; Dithering = Maximum; VIN = -0.5 dBFS @ 60 Hz on all channels, VREFEXT = 0; CLKEXT = 1; BOOST[1:0] = 10. Standar deviation = 78 LSB Noise = 7.4ȝVrms 16 ksamples -108.2 -107.8 -107.4 -107.0 -106.6 Total Harmonic Distortion (-dBc) ( dBc) Output Noise (LSB) FIGURE 2-10: THD Repeatability Freq quency of Occurrence Total Harmonic Distortion (dBc) FIGURE 2-7: Histogram. -106.2 448 481 514 548 581 614 647 680 714 747 780 813 846 880 913 946 979 1,012 1,046 1,079 1,112 F Freque ency off Occurrence e Frequ uency of Occurrence Note: Output Noise Histogram. -90 Dithering=Maximum Dithering=Medium Dithering=Minimum Dithering=Off -95 -100 -105 -110 -115 -120 -125 -130 111.7 112.3 112.9 113.5 114.1 114.7 115.3 Spurious Free Dynamic Range (dBFS) 115.9 FIGURE 2-8: Spurious-Free Dynamic Range Repeatability Histogram. 32 64 128 256 512 1024 2048 4096 Oversampling Ratio (OSR) FIGURE 2-11: THD vs.OSR. Signal-to-N Noise and Disto ortion R Ratio (d dB) Frequency o of Occu urrence e 110 105 100 95 90 85 80 75 70 65 60 93.3 93.4 93.5 93.6 93.7 Signal to Noise and Distortion (dB) FIGURE 2-9: Histogram. DS20005116D-page 12 SINAD Repeatability 93.8 Dithering Maximu Dithering=Maximu m Dithering=Medium 32 FIGURE 2-12: 64 128 256 512 1024 2048 4096 Oversampling Ratio (OSR) SINAD vs. OSR.  2012-2020 Microchip Technology Inc. MCP3910 Unless otherwise indicated, AVDD = 3V, DVDD = 3V; TA = +25°C, MCLK = 4 MHz; PRESCALE = 1; OSR = 256; GAIN = 1; Dithering = Maximum; VIN = -0.5 dBFS @ 60 Hz on all channels, VREFEXT = 0; CLKEXT = 1; BOOST[1:0] = 10. Note: 110 105 100 95 90 85 80 75 70 65 60 100 32 64 Spurio ous Fre ee Dyn namic Range ((dBFS)) R 90 85 80 75 70 SNR vs. OSR. 60 2 100 115 95 110 105 100 95 g Dithering=Maximum Dithering=Medium Dithering=Minimum Dithering=Off Dithering Off 85 4 6 8 10 12 14 MCLK Frequency (MHz) FIGURE 2-16: 120 90 Boost = 00 Boost = 01 Boost = 10 65 128 256 512 1024 2048 4096 Oversampling O li Ratio R ti (OSR) FIGURE 2-13: 80 64 SFDR vs. OSR. 18 90 85 80 75 70 Boost = 00 Boost = 01 Boost = 10 Boost = 11 65 128 256 512 1024 2048 4096 O Oversampling li Ratio R ti (OSR) FIGURE 2-14: 16 SINAD vs. MCLK. 60 32 2 4 6 FIGURE 2-17: 8 10 12 14 16 MCLK Frequency (MHz) 18 SNR vs. MCLK. 120 -60 -65 -70 -75 -80 -85 -90 -95 100 -100 -105 -110 Boost = 00 Boost = 01 Boost = 10 Boost = 11 2 4 FIGURE 2-15: 6 8 10 12 14 16 MCLK Frequency (MHz) THD vs. MCLK.  2012-2020 Microchip Technology Inc. 18 Spurio ous Fre ee Dynamic Range (dBF FS) Tota al Harmonic Distortion (dB) 95 Sig gnal-to o-Noise e and Disttortion (dB) Dithering Maximum Dithering=Maximum Dithering=Medium Dithering=Minimum Dithering=Off Signal-to-Noise Rattio (dB)) Signal-to--Noise Ratio ((dB) L 20 110 100 90 80 Boost = 00 Boost = 01 Boost = 10 Boost = 11 70 60 2 FIGURE 2-18: 4 6 8 10 12 14 16 MCLK Frequency (MHz) 18 20 SFDR vs. MCLK. DS20005116D-page 13 MCP3910 Note: Unless otherwise indicated, AVDD = 3V, DVDD = 3V; TA = +25°C, MCLK = 4 MHz; PRESCALE = 1; OSR = 256; GAIN = 1; Dithering = Maximum; VIN = -0.5 dBFS @ 60 Hz on all channels, VREFEXT = 0; CLKEXT = 1; BOOST[1:0] = 10. 140 OSR = 32 OSR = 64 OSR = 128 OSR = 256 OSR = 512 OSR = 1024 OSR = 2048 OSR = 4096 -20 -40 -60 -80 -100 -120 SpuriousFree Dynamic Range (dBFS) Total Harmonic DistorWion (dB) 0 120 100 -140 2 FIGURE 2-19: 4 8 Gain (V/V) 16 40 20 32 THD vs. GAIN. 1 2 FIGURE 2-22: 120 Total Harmonic Distortion (dB) -20 100 80 60 OSR = 32 OSR = 64 OSR = 128 OSR = 256 OSR = 512 OSR = 1024 OSR = 2048 OSR = 4096 40 20 0 1 2 FIGURE 2-20: 4 8 Gain (V/V) 16 32 120 100 80 60 OSR = 32 OSR = 64 OSR = 128 OSR = 256 OSR = 512 OSR = 1024 OSR = 2048 OSR = 4096 40 20 0 1 2 FIGURE 2-21: DS20005116D-page 14 4 8 Gain (V/V) SNR vs. GAIN. 16 -60 32 16 32 SFDR vs. GAIN. -80 -100 -120 0.001 0.01 0.1 1 10 100 Input Signal Amplitude (mVPK) FIGURE 2-23: Amplitude. SINAD vs. GAIN. 4 8 Gain (V/V) GAIN = 1x GAIN = 2x GAIN = 4x GAIN = 8x GAIN = 16x GAIN = 32x -40 Signal-to-Noise and Distortion Ratio (dB) Signal-to-Noise and Distortion Ratio (dB) OSR = 32 OSR = 64 OSR = 128 OSR = 256 OSR = 512 OSR = 1024 OSR = 2048 OSR = 4096 60 0 1 Signal-to-Noise Ratio (dB) 80 1000 THD vs. Input Signal 100 80 60 40 GAIN = 1x GAIN = 2x GAIN = 4x GAIN = 8x GAIN = 16x GAIN = 32x 20 0 -20 0.001 0.01 0.1 1 10 100 Input Signal Amplitude (mVPK) FIGURE 2-24: Amplitude. 1000 SINAD vs. Input Signal  2012-2020 Microchip Technology Inc. MCP3910 Unless otherwise indicated, AVDD = 3V, DVDD = 3V; TA = +25°C, MCLK = 4 MHz; PRESCALE = 1; OSR = 256; GAIN = 1; Dithering = Maximum; VIN = -0.5 dBFS @ 60 Hz on all channels, VREFEXT = 0; CLKEXT = 1; BOOST[1:0] = 10. Note: 80 60 40 GAIN = 1x GAIN = 2x GAIN = 4x GAIN = 8x GAIN = 16x GAIN = 32x 20 0 -20 0.001 0.01 0.1 1 10 100 Input Signal Amplitude (mVPK) FIGURE 2-25: Amplitude. 1000 Total Harmonic Distortion (dB) Signal-to-Noise Ratio (dB) 100 -40 -60 -80 -120 -50 -25 0 FIGURE 2-28: SNR vs. Input Signal 25 50 75 Temperature (°C) 100 125 THD vs. Temperature. 120 100 80 GAIN = 1x GAIN = 2x GAIN = 4x GAIN = 8x GAIN = 16x GAIN = 32x 60 40 20 0 0.001 0.01 0.1 1 10 100 Input Signal Amplitude (mVPK) FIGURE 2-26: Amplitude. OSR = 32 OSR = 64 OSR = 128 OSR = 256 OSR = 512 OSR = 1024 OSR = 2048 OSR = 4096 100 80 60 90 80 70 60 50 40 20 0 GAIN = 1x GAIN = 2x GAIN = 4x GAIN = 8x GAIN = 16x GAIN = 32x 40 30 20 10 0 1000 SFDR vs. Input Signal 120 Signal-to-Noise and Distortion Ratio (dB) 100 -50 -25 0 FIGURE 2-29: 25 50 75 Temperature (°C) 100 125 SINAD vs. Temperature. 100 90 Signal-to-Noise Ratio (dB) SpuriousFree Dyanmic Range (dBFS) GAIN = 1x GAIN = 2x GAIN = 4x GAIN = 8x GAIN = 16x GAIN = 32x -20 -100 140 Signal-to-Noise and Distortion Ratio (dB) 0 80 70 60 50 GAIN = 1x GAIN = 2x GAIN = 4x GAIN = 8x GAIN = 16x GAIN = 32x 40 30 20 10 0 10 FIGURE 2-27: 100 1000 10000 Signal Frequency (Hz) 100000 SINAD vs. Input Frequency.  2012-2020 Microchip Technology Inc. -50 -25 FIGURE 2-30: 0 25 50 75 Temperature (°C) 100 125 SNR vs. Temperature. DS20005116D-page 15 MCP3910 Unless otherwise indicated, AVDD = 3V, DVDD = 3V; TA = +25°C, MCLK = 4 MHz; PRESCALE = 1; OSR = 256; GAIN = 1; Dithering = Maximum; VIN = -0.5 dBFS @ 60 Hz on all channels, VREFEXT = 0; CLKEXT = 1; BOOST[1:0] = 10. Internal Voltage Reference (V) SpuriousFree Dyanmic Range (dBFS) 120 100 80 60 GAIN = 1x GAIN = 2x GAIN = 4x GAIN = 8x GAIN = 16x GAIN = 32x 40 20 0 -50 -25 25 50 75 Temperature (°C) 1.1967 1.1966 1.1965 1.1964 1.1963 1.1962 600 400 200 0 -200 -400 -600 -800 -1000 0 FIGURE 2-32: Gain. 20 40 60 80 Temperature (°C) 100 2.5 2.6 2.7 2.8 2.9 3 3.1 3.2 3.3 3.4 3.5 3.6 AVDD (V) 125 GAIN = 1x GAIN = 2x GAIN = 4x GAIN = 8x GAIN = 16x GAIN = 32x 800 Offset (μV) 100 SFDR vs. Temperature. 1000 -20 1.1968 1.1961 0 FIGURE 2-31: -40 1.1969 120 Offset vs. Temperature vs. FIGURE 2-34: Internal Voltage Reference vs. Supply Voltage. 10 Integral NonLinearity Error (ppm) Note: 8 6 4 2 0 -2 -4 -6 -8 -10 -0.6 -0.2 0.0 0.2 Input Voltage (V) 0.4 0.6 FIGURE 2-35: Integral Nonlinearity (Dithering Maximum). 10 800 Channel 0 Channel 1 600 400 200 0 -200 -400 -600 -800 -1000 -40 -20 0 FIGURE 2-33: vs. Temperature. DS20005116D-page 16 20 40 60 80 Temperature (°C) 100 120 Channel Offset Matching Integral NonLinearity Error (ppm) 1000 Channel Offset (μV) -0.4 8 6 4 2 0 -2 -4 -6 -8 -10 -0.6 -0.4 FIGURE 2-36: (Dithering Off). -0.2 0.0 0.2 Input Voltage (V) 0.4 0.6 Integral Nonlinearity  2012-2020 Microchip Technology Inc. MCP3910 Unless otherwise indicated, AVDD = 3V, DVDD = 3V; TA = +25°C, MCLK = 4 MHz; PRESCALE = 1; OSR = 256; GAIN = 1; Dithering = Maximum; VIN = -0.5 dBFS @ 60 Hz on all channels, VREFEXT = 0; CLKEXT = 1; BOOST[1:0] = 10. Note: 4.5 AIDD Boost = 2x 4 3.5 IDD (m mA) 3 AIDD Boost = 1x 2.5 AIDD Boost = 0.66x 2 15 1.5 AIDD Boost = 0.5x 1 DIDD 0.5 0 0 5 10 1 15 20 MCLK Frequency (MHz) 2 25 30 FIGURE 2-37: Operating Current vs. MCLK Frequency vs. Boost, VDD = 3.0V.  2012-2020 Microchip Technology Inc. DS20005116D-page 17 MCP3910 NOTES: DS20005116D-page 18  2012-2020 Microchip Technology Inc. MCP3910 3.0 PIN DESCRIPTION The descriptions of the pins are listed in Table 3-1. TABLE 3-1: TWO-CHANNEL MCP3910 PIN FUNCTION TABLE MCP3910 SSOP MCP3910 QFN Symbol 1 18 RESET/OSR0 2 19 DVDD Digital Power Supply Pin 3 20 AVDD Analog Power Supply Pin 4 1 CH0+ Noninverting Analog Input Pin for Channel 0 5 2 CH0- Inverting Analog Input Pin for Channel 0 6 3 CH1- Inverting Analog Input Pin for Channel 1 7 4 CH1+ Noninverting Analog Input Pin for Channel 1 8 5 AGND Analog Ground Pin, Return Path for Internal Analog Circuitry 9 6 REFIN+/OUT Noninverting Voltage Reference Input and Internal Reference Output Pin 10 7 REFIN- 11 8 DGND 3.1 Function Master Reset Logic Input Pin or OSR0 Logic Input Pin Inverting Voltage Reference Input Pin Digital Ground Pin, Return Path for Internal Digital Circuitry 12 9 MDAT1 Modulator Data Output Pin for Channel 1 13 10 MDAT0 Modulator Data Output Pin for Channel 0 Data Ready Signal Output Pin or GAIN1 Logic Input Pin 14 11 DR/GAIN1 15 12 OSC1/CLKI/GAIN0 Oscillator Crystal Connection Pin or External Clock Input Pin or GAIN0 Logic Input Pin 16 13 OSC2/MODE Oscillator Crystal Connection Pin or Serial Interface Mode Logic Input Pin 17 14 CS/BOOST Serial Interface Chip Select Input Pin or Boost Logic Input Pin Serial Interface Clock Input Pin or Master Clock Input Pin 18 15 SCK/MCLK 19 16 SDO 20 17 SDI/OSR1 — 21 EP Serial Interface Data Input Pin Serial Interface Data Input Pin or OSR1 Logic Input Pin Exposed Thermal Pad. Master Reset/OSR0 Logic Input (RESET/OSR0) In SPI mode, this pin is active-low and places the entire chip in a Reset state when active. When RESET is logic low, all registers are reset to their default value, no communication can take place, no clock is distributed inside the part, except in the input structure if MCLK is applied (if MCLK is Idle, then no clock is distributed). This state is equivalent to a Power-on Reset (POR) state. Since the default state of the ADCs is on, the analog power consumption when RESET is logic low is equivalent to when RESET is logic high. Only the digital power consumption is largely reduced because this current consumption is essentially dynamic and is reduced drastically when there is no clock running.  2012-2020 Microchip Technology Inc. All the analog biases are enabled during a Reset, so that the part is fully operational just after a RESET rising edge, if MCLK is applied when RESET is logic low. If MCLK is not applied, there is a time after a hard Reset when the conversion may not accurately correspond to the start-up of the input structure. This input is Schmitt triggered. In Two-Wire Interface mode, this is the OSR0 logic select pin (see Section 7.0 “Two-Wire Serial Interface Description” for the logic input table for OSR0 and OSR1). The pin state is latched when the MODE changes to Two-Wire Interface mode and is relatched at each Watchdog Timer Reset. DS20005116D-page 19 MCP3910 3.2 Digital VDD (DVDD) DVDD is the power supply voltage for the digital circuitry within the MCP3910. For optimal performance, it is recommended to connect appropriate bypass capacitors (typically a 10 µF in parallel with a 0.1 µF ceramic). DVDD should be maintained between 2.7V and 3.6V for specified operation. 3.3 Analog VDD (AVDD) AVDD is the power supply voltage for the analog circuitry within the MCP3910. For optimal performance, it is recommended to connect appropriate bypass capacitors (typically a 10 µF in parallel with a 0.1 µF ceramic). AVDD should be maintained between 2.7V and 3.6V for specified operation. 3.4 ADC Differential Analog Inputs (CHn+/CHn-) The CHn+/- pins (n comprised between 0 and 1) are the two fully differential analog voltage inputs for the Delta-Sigma ADCs. The linear and specified region of the channels are dependent on the PGA gain. This region corresponds to a differential voltage range of ±600 mV/GAIN with VREF = 1.2V. The maximum absolute voltage, with respect to AGND, for each CHn+/- input pin is ±1V with no distortion and ±2V with no breaking after continuous voltage. This maximum absolute voltage is not proportional to the VREF voltage. 3.5 Analog Ground (AGND) AGND is the ground reference voltage for the analog circuitry within the MCP3910. For optimal performance, it is recommended to connect it to the same ground node voltage as DGND; again preferable with a star connection. If an analog ground plane is available, it is recommended that these pins be tied to this plane of the PCB. This plane should also reference all other analog circuitry in the system. DS20005116D-page 20 3.6 Noninverting Reference Input, Internal Reference Output (REFIN+/OUT) This pin is the noninverting side of the differential voltage reference input for all ADCs or the internal voltage reference output. When VREFEXT = 1, an external voltage reference source can be used and the internal voltage reference is disabled. When using an external differential voltage reference, it should be connected to its VREF+ pin. When using an external single-ended reference, it should be connected to this pin. When VREFEXT = 0, the internal voltage reference is enabled and connected to this pin through a switch. This voltage reference has minimal drive capability and thus needs proper buffering and bypass capacitances (a 0.1 µF ceramic capacitor is sufficient in most cases) if used as a voltage source. If the voltage reference is only used as an internal VREF, adding bypass capacitance on REFIN+/OUT is not necessary for keeping ADC accuracy. To avoid EMI/EMC susceptibility issues due to the antenna created by the REFIN+/OUT pin, if left floating, a minimal 0.1 µF ceramic capacitance can be connected. 3.7 Inverting Reference Input (REFIN-) This pin is the inverting side of the differential voltage reference input for all ADCs. When using an external differential voltage reference, it should be connected to its VREF- pin. When using an external single-ended voltage reference, or when VREFEXT = 0 (default) and using the internal voltage reference, the pin should be directly connected to AGND. 3.8 Digital Ground Connection (DGND) DGND is the ground reference voltage for the digital circuitry within the MCP3910. For optimal performance, it is recommended to connect it to the same ground node voltage as AGND, again preferable with a star connection. If a digital ground plane is available, it is recommended that these pins be tied to this plane of the Printed Circuit Board (PCB). This plane should also reference all other digital circuitry in the system.  2012-2020 Microchip Technology Inc. MCP3910 3.9 Modulator Outputs (MDAT0/MDAT1) MDAT0 and MDAT1 are the output pins for the modulator serial bitstreams of ADC Channels 0 and 1, respectively. These pins are high-impedance when the EN_MDAT bit is logic low. When the EN_MDAT bit is enabled, the modulator bitstream of each channel is present on the MDAT0/1 output pins and updated at the AMCLK frequency (see Section 5.3.5 “Modulator Output Block” for a complete description of the modulator outputs). These pins can be directly connected to an MCU or a DSP when a specific digital filtering is needed. When the MDAT output pins are enabled, the DR output is disabled. In Two-Wire Interface mode, these pins are automatically inactive. Their state is high-impedance during this Two-Wire Interface mode (therefore, these pins can be left grounded in applications using exclusively this mode; this configuration improves the EMI/EMC susceptibility of the device). 3.10 Data Ready Output/GAIN1 Logic Input (DR/GAIN1) In SPI mode, the Data Ready Output pin indicates if a new conversion result is ready to be read. The default state of this pin is logic high when DR_HIZ = 1, and is high-impedance when DR_HIZ = 0 (default). After each conversion is finished, a logic low pulse will take place on the Data Ready pin to indicate the conversion result is ready as an interrupt. This pulse is synchronous with the Master Clock and has a defined and constant width. The Data Ready pin is independent of the SPI interface and acts like an interrupt output. The Data Ready pin state is not latched and the pulse width (and period) are both determined by the MCLK frequency, oversampling rate, and internal clock prescale settings. The data ready pulse width is equal to half a DMCLK period and the frequency of the pulses is equal to DRCLK (see Figure 1-3). In Two-Wire Interface mode, this is the GAIN1 logic select input pin (see Section 7.0 “Two-Wire Serial Interface Description” for the logic input table for GAIN0 and GAIN1). The pin state is latched when the mode changes to Two-Wire Interface mode and is relatched at each Watchdog Timer Reset. Note: This pin should not be left floating when the DR_HIZ bit is low; a 100 k pull-up resistor connected to DVDD is recommended.  2012-2020 Microchip Technology Inc. 3.11 Crystal Oscillator/Master Clock Input/GAIN0 Logic Input (OSC1/CLKI/GAIN0) In SPI mode, OSC1/CLKI and OSC2 provide the Master Clock for the device. When CLKEXT = 0, a resonant crystal or clock source with a similar sinusoidal waveform must be placed across the OSC1 and OSC2 pins to ensure proper operation. The typical clock frequency specified is 4 MHz. For proper operation, and for optimizing ADC accuracy, AMCLK should be limited to the maximum frequency defined in Table 5-2 for the function of the BOOST and PGA setting chosen. MCLK can take larger values as long as the prescaler settings (PRE[1:0]) limit AMCLK = MCLK/PRESCALE in the defined range in Table 5-2. Appropriate load capacitance should be connected to these pins for proper operation. In Two-Wire Interface mode, this is the GAIN0 logic select input pin (see Section 7.0 “Two-Wire Serial Interface Description” for the logic input table for GAIN0 and GAIN1). The pin state is latched when the mode changes to Two-Wire Interface mode and is relatched at each Watchdog Timer Reset. Note: 3.12 When CLKEXT = 1, the crystal oscillator is disabled. OSC1 becomes the Master Clock input, CLKI, a direct path for an external clock source. One example would be a clock source generated by an MCU. Crystal Oscillator Output/ Interface Mode Logic Input (OSC2/MODE) When CLKEXT = 0 (default), a resonant crystal or clock source with a similar sinusoidal waveform must be placed across the OSC1 and OSC2 pins to ensure proper operation. Appropriate load capacitance should be connected to these pins for proper operation. When CLKEXT = 1 (default condition at POR), this pin is the Mode Selection pin for the digital interface. When MODE is logic low, the SPI interface is selected (see Section 6.0 “SPI Serial Interface Description”); when MODE is logic high, the two-wire interface (see Section 7.0 “Two-Wire Serial Interface Description”) is selected. The MODE input is latched after a POR, a Master Reset and/or a Watchdog Timer Reset. DS20005116D-page 21 MCP3910 3.13 Chip Select/ Boost Logic Input (CS/BOOST) In SPI mode, this pin is the SPI Chip Select that enables serial communication. When this pin is logic high, no communication can take place. A chip select falling edge initiates serial communication and a chip select rising edge terminates the communication. No communication can take place, even when CS is logic low, if RESET is also logic low. This input is Schmitt triggered. In Two-Wire Interface mode, this is the Boost Logic Select Input pin (see Section 7.0 “Two-Wire Serial Interface Description” for the logic input table for BOOST). The pin state is latched when the mode changes to Two-Wire Interface mode and is relatched at each Watchdog Timer Reset. 3.14 Serial Data Clock/ Master Clock Input (SCK/MCLK) In SPI mode, this is the Serial Clock pin for SPI communication. Data are clocked into the device on the rising edge of SCK. Data are clocked out of the device on the falling edge of SCK. The MCP3910 SPI interface is compatible with SPI 0,0 and 1,1 modes. SPI modes can be changed during a CS high time. The maximum clock speed specified is 20 MHz. SCK and MCLK are two different and asynchronous clocks; SCK is only required when a communication happens, while MCLK is continuously required when the part is converting analog inputs. This input is Schmitt triggered. In the Two-Wire Interface mode, this pin is defining the Master Clock of the device (MCLK) and simultaneously, as the Serial Clock (SCK) for the interface. In this mode, the clock has to be provided continuously to ensure proper operation. See Section 7.0 “Two-Wire Serial Interface Description” for more information and timing diagrams of the Two-Wire Interface mode protocol. DS20005116D-page 22 3.15 Serial Data Output (SDO) This is the SPI Data Output pin. Data are clocked out of the device on the falling edge of SCK. This pin remains in a high-impedance state during the command byte. It also stays high-impedance during the entire communication for WRITE commands and when the CS pin is logic high, or when the RESET pin is logic low. This pin is active only when a READ command is processed. The interface is half duplex (inputs and outputs do not happen at the same time). In the Two-Wire Interface mode, this pin is the only digital output pin and sends synchronous frames at each data ready event with data bits clocked out on the falling edge of SCK. 3.16 Serial Data/OSR1 Logic Input (SDI/OSR1) This is the SPI Data Input pin. Data are clocked into the device on the rising edge of SCK. When CS is logic low, this pin is used to communicate with a series of 8-bit commands. The interface is half duplex (inputs and outputs do not happen at the same time). Each communication starts with a chip select falling edge, followed by an 8-bit command word, entered through the SDI pin. Each command is either a READ or a WRITE command. Toggling SDI after a READ or a WRITE command, when CS is logic high, has no effect. This input is Schmitt triggered. In Two-Wire Interface mode, this is the OSR1 Logic Select Input pin (see Section 7.0 “Two-Wire Serial Interface Description” for the logic input table for OSR0 and OSR1). The pin state is latched when the mode changes to Two-Wire Interface mode and is relatched at each Watchdog Timer Reset. 3.17 Exposed Pad (EP) This pin is the Exposed Thermal Pad. It must be connected to AGND for optimal accuracy and thermal performance. This pad can also be left floating if necessary. Connecting it to AGND is preferable for the lowest noise performance and best thermal behavior.  2012-2020 Microchip Technology Inc. MCP3910 4.0 TERMINOLOGY AND FORMULAS 4.1 This section defines the terms and formulas used throughout this data sheet. The following terms are defined: • • • • • • • • • • • • • • • • • • • • • • MCLK – Master Clock AMCLK – Analog Master Clock DMCLK – Digital Master Clock DRCLK – Data Rate Clock OSR – Oversampling Ratio Offset Error Gain Error Integral Nonlinearity Error Signal-to-Noise Ratio (SNR) Signal-to-Noise Ratio and Distortion (SINAD) Total Harmonic Distortion (THD) Spurious-Free Dynamic Range (SFDR) MCP3910 Delta-Sigma Architecture Idle Tones Dithering Crosstalk PSRR CMRR ADC Reset Mode Hard Reset Mode (RESET = 0) ADC Shutdown Mode Full Shutdown Mode MCLK – Master Clock This is the fastest clock present on the device. This is the frequency of the crystal placed at the OSC1/OSC2 inputs when CLKEXT = 0 or the frequency of the clock input at the OSC1/CLKI when CLKEXT = 1. In the Two-Wire mode, this is the frequency present at the SCK input pin. See Figure 4-1. 4.2 AMCLK – Analog Master Clock AMCLK is the clock frequency that is present on the analog portion of the device, after prescaling has occurred via the CONFIG0 PRE[1:0] register bits (see Equation 4-1). The analog portion includes the PGAs and the two Delta-Sigma modulators. EQUATION 4-1: MCLK AMCLK = ------------------------------PRESCALE TABLE 4-1: MCP3910 OVERSAMPLING RATIO SETTINGS CONFIG0 Analog Master Clock Prescale PRE[1:0] 0 0 AMCLK = MCLK/1 (default) 0 1 AMCLK = MCLK/2 1 0 AMCLK = MCLK/4 1 1 AMCLK = MCLK/8 MODE SCK CLKEXT PRE OSR 1 OUT 0 1 Multiplexer OSC1 OUT MCLK 1/PRESCALE AMCLK 1/4 DMCLK 1/OSR DRCLK 0 OSC2 Xtal Oscillator FIGURE 4-1: Multiplexer Clock Divider Clock Divider Clock Divider Clock Sub-Circuitry.  2012-2020 Microchip Technology Inc. DS20005116D-page 23 MCP3910 4.3 DMCLK – Digital Master Clock This is the clock frequency that is present on the digital portion of the device, after prescaling and division by four (Equation 4-2). This is also the sampling frequency, which is the rate at which the modulator outputs are refreshed. Each period of this clock corresponds to one sample and one modulator output. See Figure 4-1. EQUATION 4-2: AMCLK MCLK DMCLK = --------------------- = ---------------------------------------4 4  PRESCALE 4.4 DRCLK – Data Rate Clock This is the output data rate (i.e., the rate at which the ADCs output new data). Each new data are signaled by a data ready pulse on the DR pin. This data rate is dependent on the OSR and the prescaler with the formula in Equation 4-3. EQUATION 4-3: DMCLK AMCLK MCLK DRCLK = ---------------------- = --------------------- = ----------------------------------------------------------OSR 4  OSR 4  OSR  PRESCALE Since this is the output data rate, and because the decimation filter is a SINC (or notch) filter, there is a notch in the filter transfer function at each integer multiple of this rate. Table 4-2 describes the various combinations of OSR and PRESCALE, and their associated AMCLK, DMCLK and DRCLK rates. DS20005116D-page 24  2012-2020 Microchip Technology Inc. MCP3910 TABLE 4-2: PRE[1:0] DEVICE DATA RATES IN FUNCTION OF MCLK, OSR AND PRESCALE, MCLK = 4 MHz OSR[2:0] OSR AMCLK DMCLK DRCLK DRCLK (ksps) SINAD (dB)(1) ENOB from SINAD (bits)(1) MCLK/8 MCLK/32 MCLK/131072 .035 102.5 16.7 1 1 1 1 1 4096 1 1 1 1 1 2048 MCLK/8 MCLK/32 MCLK/65536 .061 100 16.3 1 1 1 1 1 1024 MCLK/8 MCLK/32 MCLK/32768 .122 97 15.8 1 1 1 1 1 512 MCLK/8 MCLK/32 MCLK/16384 .244 96 15.6 1 1 0 1 1 256 MCLK/8 MCLK/32 MCLK/8192 0.488 95 15.5 1 1 0 1 0 128 MCLK/8 MCLK/32 MCLK/4096 0.976 90 14.7 1 1 0 0 1 64 MCLK/8 MCLK/32 MCLK/2048 1.95 83 13.5 1 1 0 0 0 32 MCLK/8 MCLK/32 MCLK/1024 3.9 70 11.3 1 0 1 1 1 4096 MCLK/4 MCLK/16 MCLK/65536 .061 102.5 16.7 1 0 1 1 1 2048 MCLK/4 MCLK/16 MCLK/32768 .122 100 16.3 1 0 1 1 1 1024 MCLK/4 MCLK/16 MCLK/16384 .244 97 15.8 1 0 1 1 1 512 MCLK/4 MCLK/16 MCLK/8192 .488 96 15.6 1 0 0 1 1 256 MCLK/4 MCLK/16 MCLK/4096 0.976 95 15.5 1 0 0 1 0 128 MCLK/4 MCLK/16 MCLK/2048 1.95 90 14.7 1 0 0 0 1 64 MCLK/4 MCLK/16 MCLK/1024 3.9 83 13.5 1 0 0 0 0 32 MCLK/4 MCLK/16 MCLK/512 7.8125 70 11.3 0 1 1 1 1 4096 MCLK/2 MCLK/8 MCLK/32768 .122 102.5 16.7 0 1 1 1 1 2048 MCLK/2 MCLK/8 MCLK/16384 .244 100 16.3 0 1 1 1 1 1024 MCLK/2 MCLK/8 MCLK/8192 .488 97 15.8 0 1 1 1 1 512 MCLK/2 MCLK/8 MCLK/4096 .976 96 15.6 0 1 0 1 1 256 MCLK/2 MCLK/8 MCLK/2048 1.95 95 15.5 0 1 0 1 0 128 MCLK/2 MCLK/8 MCLK/1024 3.9 90 14.7 0 1 0 0 1 64 MCLK/2 MCLK/8 MCLK/512 7.8125 83 13.5 0 1 0 0 0 32 MCLK/2 MCLK/8 MCLK/256 15.625 70 11.3 0 0 1 1 1 4096 MCLK MCLK/4 MCLK/16384 .244 102.5 16.7 0 0 1 1 0 2048 MCLK MCLK/4 MCLK/8192 .488 100 16.3 0 0 1 0 1 1024 MCLK MCLK/4 MCLK/4096 .976 97 15.8 0 0 1 0 0 512 MCLK MCLK/4 MCLK/2048 1.95 96 15.6 0 0 0 1 1 256 MCLK MCLK/4 MCLK/1024 3.9 95 15.5 0 0 0 1 0 128 MCLK MCLK/4 MCLK/512 7.8125 90 14.7 0 0 0 0 1 64 MCLK MCLK/4 MCLK/256 15.625 83 13.5 0 0 0 0 0 32 MCLK MCLK/4 MCLK/128 31.25 70 11.3 Note 1: For OSR = 32 and 64, DITHER = None. For OSR = 128 and higher, DITHER = Maximum. The SINAD values are given from GAIN = 1.  2012-2020 Microchip Technology Inc. DS20005116D-page 25 MCP3910 4.5 OSR – Oversampling Ratio 4.8 Integral Nonlinearity Error This is the ratio of the sampling frequency to the output data rate. OSR = DMCLK/DRCLK. The default OSR is 256, or with MCLK = 4 MHz, PRESCALE = 1, AMCLK = 4 MHz, fS = 1 MHz and fD = 3.90625 ksps. The bits in Table 4-3 in the CONFIG0 register are used to change the Oversampling Ratio (OSR). Integral nonlinearity error is the maximum deviation of an ADC transition point from the corresponding point of an ideal transfer function, with the offset and gain errors removed, or with the end points equal to zero. TABLE 4-3: 4.9 MCP3910 OVERSAMPLING RATIO SETTINGS CONFIG0 Oversampling Ratio (OSR) OSR[2:0] 4.6 0 0 0 32 0 0 1 64 0 1 0 128 0 1 1 256 (Default) 1 0 0 512 1 0 1 1024 1 1 0 2048 1 1 1 4096 Offset Error This is the error induced by the ADC when the inputs are shorted together (VIN = 0V). The specification incorporates both PGA and ADC offset contributions. This error varies with PGA and OSR settings. The offset is different on each channel and varies from chip to chip. The offset is specified in µV. The offset error can be digitally compensated independently on each channel through the OFFCAL registers with a 24-bit Calibration Word. The offset on the MCP3910 has a low-temperature coefficient. 4.7 Gain Error This is the error induced by the ADC on the slope of the transfer function. It is the deviation expressed in %, compared to the ideal transfer function defined in Equation 5-3. The specification incorporates both PGA and ADC gain error contributions, but not the VREF contribution (it is measured with an external VREF). This error varies with PGA and OSR settings. The gain error can be digitally compensated independently on each channel through the GAINCAL registers with a 24-bit Calibration Word. It is the maximum remaining error after calibration of offset and gain errors for a DC input signal. Signal-to-Noise Ratio (SNR) For the MCP3910 ADCs, the Signal-to-Noise Ratio is a ratio of the output fundamental signal power to noise power (not including the harmonics of the signal) when the input is a sine wave at a predetermined frequency (see Equation 4-4); it is measured in dB. Usually, only the maximum Signal-to-Noise Ratio is specified. The SNR figure depends mainly on the OSR and DITHER settings of the device. EQUATION 4-4: SIGNAL-TO-NOISE RATIO SignalPower SNR  dB  = 10 log  ----------------------------------  NoisePower  4.10 Signal-to-Noise Ratio and Distortion (SINAD) The most important figure of merit for the analog performance of the ADCs present on the MCP3910 is the Signal-to-Noise and Distortion (SINAD) specification. The Signal-to-Noise and Distortion ratio is similar to the Signal-to-Noise Ratio, with the exception that you must include the harmonics power in the noise power calculation (see Equation 4-5). The SINAD specification depends mainly on the OSR and DITHER settings. EQUATION 4-5: SINAD EQUATION SignalPower SINAD  dB  = 10 log  ---------------------------------------------------------------------  Noise + HarmonicsPower The calculated combination of SNR and THD per the following formula also yields SINAD (see Equation 4-6). EQUATION 4-6: SINAD, THD AND SNR RELATIONSHIP SINAD  dB  = 10 log 10  SNR -----------  10  + 10 THD – ----------------  10  The gain error on the MCP3910 has a low-temperature coefficient. DS20005116D-page 26  2012-2020 Microchip Technology Inc. MCP3910 4.11 Total Harmonic Distortion (THD) The Total Harmonic Distortion is the ratio of the output harmonics power to the fundamental signal power for a sine wave input and is defined in Equation 4-7. EQUATION 4-7: HarmonicsPower THD  dB  = 10 log  -----------------------------------------------------  FundamentalPower The THD calculation includes the first 35 harmonics for the MCP3910 specifications. The THD is usually only measured with respect to the ten first harmonics. THD is sometimes expressed in %. Equation 4-8 converts the THD in %. EQUATION 4-8: THD  %  = 100  10 THD  dB  -----------------------20 This specification depends mainly on the DITHER setting. 4.12 Spurious-Free Dynamic Range (SFDR) SFDR is the ratio between the output power of the fundamental and the highest spur in the frequency spectrum (see Equation 4-9). The spur frequency is not necessarily a harmonic of the fundamental, even though this is usually the case. This figure represents the dynamic range of the ADC when a full-scale signal is used at the input. This specification depends mainly on the DITHER setting. EQUATION 4-9: FundamentalPower SFDR  dB  = 10 log  ----------------------------------------------------- HighestSpurPower 4.13 MCP3910 Delta-Sigma Architecture The MCP3910 incorporates two Delta-Sigma ADCs with a multibit architecture. A Delta-Sigma ADC is an oversampling converter that incorporates a built-in modulator, which digitizes the quantity of charges integrated by the modulator loop (see Figure 5-1). The quantizer is the block that performs the Analog-toDigital conversion. The quantizer is typically 1 bit, or a simple comparator, which helps maintain the linearity performance of the ADC (the DAC structure is, in this case, inherently linear).  2012-2020 Microchip Technology Inc. Multibit quantizers help lower the quantization error (the error fed back in the loop can be very large with 1-bit quantizers) without changing the order of the modulator or the OSR, which leads to better SNR figures. However, typically, the linearity of such architectures is more difficult to achieve since the DAC linearity is as difficult to attain and its linearity limits the THD of such ADCs. The MCP3910 device’s 5-level quantizer is a Flash ADC composed of four comparators, arranged with equally spaced thresholds and a thermometer coding. The MCP3910 also includes proprietary 5-level DAC architecture that is inherently linear for improved THD figures. 4.14 Idle Tones A Delta-Sigma converter is an integrating converter. It also has a finite quantization step (LSB) which can be detected by its quantizer. A DC input voltage that is below the quantization step should only provide an all zeros result, since the input is not large enough to be detected. As an integrating device, any Delta-Sigma will show Idle tones. This means that the output will have spurs in the frequency content that depend on the ratio between the quantization step voltage and the input voltage. These spurs are the result of the integrated sub-quantization step inputs that will eventually cross the quantization steps after a long enough integration. This will induce an AC frequency at the output of the ADC and can be shown in the ADC output spectrum. These Idle tones are residues that are inherent to the quantization process and the fact that the converter is integrating at all times without being reset. They are residues of the finite resolution of the conversion process. They are very difficult to attenuate and they are heavily signal-dependent. They can degrade the SFDR and THD of the converter, even for DC inputs. They can be localized in the baseband of the converter and are thus difficult to filter from the actual input signal. For power metering applications, Idle tones can be very disturbing, because energy can be detected even at the 50 or 60 Hz frequency, depending on the DC offset of the ADCs, while no power is really present at the inputs. The only practical way to suppress or attenuate the Idle tones phenomenon is to apply dithering to the ADC. The amplitudes of the Idle tones are a function of the order of the modulator, the OSR and the number of levels in the quantizer of the modulator. A higher order, a higher OSR or a higher number of levels for the quantizer will attenuate the amplitudes of the Idle tones. DS20005116D-page 27 MCP3910 4.15 Dithering In order to suppress or attenuate the Idle tones present in any Delta-Sigma ADCs, dithering can be applied to the ADC. Dithering is the process of adding an error to the ADC feedback loop in order to “decorrelate” the outputs and “break” the Idle tone’s behavior. Usually a random or pseudorandom generator adds an analog or digital error to the feedback loop of the Delta-Sigma ADC in order to ensure that no tonal behavior can happen at its outputs. This error is filtered by the feedback loop and typically has a zero average value, so that the converter’s static transfer function is not disturbed by the dithering process. However, the dithering process slightly increases the noise floor (it adds noise to the part) while reducing its tonal behavior, and thus, improving SFDR and THD. The dithering process scrambles the Idle tones into baseband white noise and ensures that dynamic specs (SNR, SINAD, THD, SFDR) are less signal-dependent. The MCP3910 incorporates a proprietary dithering algorithm on all ADCs in order to remove Idle tones and improve THD, which is crucial for power metering applications. 4.16 Crosstalk Crosstalk is defined as the perturbation caused by one ADC channel on the other ADC channel. It is a measurement of the isolation between the two ADCs present in the chip. This measurement is a two-step procedure: 1. 2. Measure one ADC input with no perturbation on the other ADC (ADC inputs shorted). Measure the same ADC input with a perturbation sine wave signal on all the other ADCs at a certain predefined frequency. Crosstalk is the ratio between the output power of the ADC when perturbation is and is not present, divided by the power of the perturbation signal. A lower crosstalk value implies more independence and isolation between the two channels. The measurement of this signal is performed under the default conditions of MCLK = 4 MHz: • • • • GAIN = 1 PRESCALE = 1 OSR = 256 MCLK = 4 MHz Step 1 for CH0 Crosstalk Measurement: • CH0+ = CH0- = AGND • CH1+ = CH1- = AGND Step 2 for CH0 Crosstalk Measurement: • CH0+ = CH0- = AGND • CH1+ – CH1- = 1.2 VP-P @ 50/60 Hz (full-scale sine wave) DS20005116D-page 28 The crosstalk is then calculated with the formula in Equation 4-10. EQUATION 4-10:  CH0Power CTalk  dB  = 10 log  ---------------------------------   CH1Power The crosstalk slightly depends on the position of the channels in the MCP3910 device. 4.17 PSRR This is the ratio between a change in the power supply voltage and the ADC output codes. It measures the influence of the power supply voltage on the ADC outputs. The PSRR specification can be DC (the power supply takes multiple DC values) or AC (the power supply is a sine wave at a certain frequency with a certain Common-mode). In AC, the amplitude of the sine wave represents the change in the power supply; it is defined in Equation 4-11. EQUATION 4-11:  VOUT PSRR  dB  = 20 log  -------------------   AV DD Where VOUT is the equivalent input voltage that the output code translates to, with the ADC transfer function. In the MCP3910 specification, AVDD varies from 2.7V to 3.6V and for AC PSRR, a 50/60 Hz sine wave is chosen, centered around 3.0V, with a maximum 300 mV amplitude. The PSRR specification is measured with AVDD = DVDD. 4.18 CMRR CMRR is the ratio between a change in the Common-mode input voltage and the ADC output codes. It measures the influence of the Common-mode input voltage on the ADC outputs. The CMRR specification can be DC (the Common-mode input voltage takes multiple DC values) or AC (the Common-mode input voltage is a sine wave at a certain frequency with a certain Common-mode). In AC, the amplitude of the sine wave represents the change in the power supply; it is defined in Equation 4-12. EQUATION 4-12:  V OUT CMRR  dB  = 20 log  -----------------   V CM  Where VCM = (CHn+ + CHn-)/2 is the Common-mode input voltage and VOUT is the equivalent input voltage that the output code translates to, with the ADC transfer function. In the MCP3910 specification, VCM varies from -1V to +1V.  2012-2020 Microchip Technology Inc. MCP3910 4.19 ADC Reset Mode ADC Reset mode (also called Soft Reset mode) can only be entered in SPI mode through setting the RESET[1:0] bits high in the CONFIG1 register. This mode is defined as the condition where the converters are active, but their output is forced to ‘0’. The registers are not affected in this Reset mode and retain their state, except the data registers of the corresponding channel, which are reset to ‘0’. The ADCs can immediately output meaningful codes after leaving the Reset mode (and after the SINC filter settling time). This mode is both entered and exited through bit settings in the CONFIG1 register. Each converter can be placed in Soft Reset mode independently. The Configuration registers are not modified by the Soft Reset mode. A data ready pulse will not be generated by any ADC in Reset mode. When an ADC exits ADC Reset mode, any phase delay present before Reset was entered will still be present. If one ADC was not in Reset, the ADC leaving the Reset mode will automatically resynchronize the phase delay relative to the other ADC channel per the Phase Delay register block and will give data ready pulses accordingly. If an ADC is placed in Reset mode while the other is converting, it does not shut down the internal clock. When coming out of Reset, it will be automatically resynchronized with the clock, which did not stop during Reset. However, when the two channels are in Soft Reset, the input structure is still clocking if MCLK is applied in order to properly bias the inputs, so that no leakage current is observed. If MCLK is not applied, large analog input leakage currents can be observed for highly negative input voltages (typically, below -0.6V, referred to as AGND). 4.20 Hard Reset Mode (RESET = 0) This mode is only available during a POR or when the RESET pin is pulled low in SPI mode. The RESET pin logic low state places the device in Hard Reset mode. In this mode, all internal registers are reset to their default state. In the Two-Wire Interface mode, the RESET pin functionality is not available and the user must use a Watchdog Timer Reset to be able to fully reset the part (see Section 7.4 “Watchdog Timer Reset, Resetting the Part in Two-Wire Mode”). The DC biases for the analog blocks are still active (i.e., the MCP3910 is ready to convert). However, this pin clears all conversion data in the ADCs. The comparators’ outputs of all ADCs are forced to their Reset state (‘0011’). The SINC filters are all reset, as well as their double-output buffers. See serial timing for minimum pulse low time in Section 1.0 “Electrical Characteristics”. During a Hard Reset, no communication with the part is possible. The digital interface is maintained in a Reset state.  2012-2020 Microchip Technology Inc. During this state, the clock MCLK can be applied to the part in order to properly bias the input structures of all channels. If not applied, large analog input leakage currents can be observed for highly negative input signals and, after removing the Hard Reset state, a certain start-up time is necessary to bias the input structure properly. During this delay, the ADC conversions can be inaccurate. 4.21 ADC Shutdown Mode ADC Shutdown mode is defined as a state where the converters and their biases are off, consuming only leakage current. When the SHUTDOWN bit is reset to ‘0’, the analog biases will be enabled, as well as the clock and the digital circuitry. The ADC will give a data ready pulse after the SINC filter settling time has occurred. However, since the analog biases are not completely settled at the beginning of the conversion, the sampling may not be accurate for about 1 ms (corresponding to the settling time of the biasing under worst-case conditions). In order to ensure accuracy, the data ready pulse within the delay of 1 ms + settling time of the SINC filter should be discarded. Each converter can be placed in Shutdown mode independently. The Configuration registers are not modified by the Shutdown mode. This mode is only available in SPI mode through programming the SHUTDOWN[1:0] bits of the CONFIG1 register. The output data are flushed to all zeros while in ADC Shutdown mode. No data ready pulses are generated by any ADC while in ADC Shutdown mode. When an ADC exits ADC Shutdown mode, any phase delay present before Shutdown was entered will still be present. If one ADC was not in Shutdown, the ADC leaving Shutdown mode will automatically resynchronize the phase delay, relative to the other ADC channel, per the Phase Delay register block and will give data ready pulses accordingly. If an ADC is placed in Shutdown mode while the other is converting, it is not shutting down the internal clock. When coming out of shutdown, it will be automatically resynchronized with the clock that did not stop during Reset. If all ADCs are in ADC Shutdown mode, the clock is not distributed to the input structure or to the digital core for low-power operation. This can potentially cause high analog input leakage currents at the analog inputs if the input voltage is highly negative (typically, below -0.6V, referred to as AGND). Once either of the ADCs is back to normal operation, the clock is automatically distributed again. DS20005116D-page 29 MCP3910 4.22 Full Shutdown Mode The lowest power consumption can be achieved when SHUTDOWN[1:0] = 11, VREFEXT = CLKEXT = 1. This mode is called Full Shutdown mode and no analog circuitry is enabled. In this mode, both AVDD and DVDD POR monitoring are also disabled and no clock is propagated throughout the chip. All ADCs are in Shutdown mode and the internal voltage reference is disabled. This mode can only be entered during SPI mode. The clock is no longer distributed to the input structure either. This can potentially cause high analog input leakage currents at the analog inputs if the input voltage is highly negative (typically, below -0.6V, referred to as AGND). The only circuit that remains active is the SPI interface, but this circuit does not induce any static power consumption. If SCK is Idle, the only current consumption comes from the leakage currents induced by the transistors and is less than 5 µA on each power supply. Once any of the SHUTDOWN, CLKEXT and VREFEXT bits return to ‘0’, the two POR monitoring blocks are operational, and AVDD and DVDD monitoring can take place. 4.23 Measurement Error The measurement error specification is typically used in power metering applications. This specification is a measurement of the linearity of the active energy of a given power meter across its dynamic range. For this measurement, the goal is to measure the active energy of one phase when the voltage Root Mean Square (RMS) value is fixed and the current RMS value is sweeping across the dynamic range specified by the meter. The measurement error is the nonlinearity error of the energy power across the current dynamic range. It is expressed in percent (%). Equation 4-13 shows the formula that calculates the measurement error. This mode can be used to power down the chip completely and to avoid power consumption when there are no data to convert at the analog inputs. Any SCK or MCLK edge occurring while in this mode will induce dynamic power consumption. EQUATION 4-13: Measured Active Energy – Active Energy present at inputs Measurement Error  I RMS = --------------------------------------------------------------------------------------------------------------------------------------------  100% Active Energy present at inputs In the present device, the calculation of the active energy is done externally, as a post-processing step that typically happens in the microcontroller; considering, for example, Channel 0 as the current channel and Channel 1 as the voltage channel. Channel 1 is fed with a full-scale sine wave at 600 mV peak, and is configured with GAIN = 1 and DITHER = Maximum. To obtain the active energy measurement error graphs, Channel 0 is fed with sine waves with amplitudes that vary from 600 mV peak to 60 µV peak, representing a 10,000:1 dynamic range. The offset is removed on both current and voltage channels, and the channels are multiplied together to give instantaneous power. The active energy is calculated by multiplying the current and voltage channel, and averaging the results of this power during 20 seconds to extract the active energy. The sampling frequency is chosen as a multiple integer of line frequency (coherent sampling). Therefore, the calculation does not take into account any residue coming from bad synchronization. DS20005116D-page 30 The measurement error is a function of IRMS, varies with the OSR, averaging time, MCLK frequency, and is tightly coupled with the noise and linearity specifications. The measurement error is a function of the linearity and THD of the ADCs, while the standard deviation of the measurement error is a function of the noise specification of the ADCs. Overall, the low THD specification enables low measurement error on a very large dynamic range (e.g., 10,000:1). A low noise and high SNR specification enables the decrease of the measurement time, and therefore, of the calibration time, to obtain a reliable measurement error specification. Figure 2-5 shows the typical measurement error curves obtained with the samples acquired by the MCP3910, using the default settings with 1-point and 2-point calibration. These calibrations are detailed in Section 8.6 “Energy Measurement Error Considerations”.  2012-2020 Microchip Technology Inc. MCP3910 5.0 DEVICE OVERVIEW 5.1 Analog Inputs (CHn+/CHn-) The MCP3910 analog inputs can be connected directly to current and voltage transducers (such as shunts, current transformers or Rogowski coils). Each input pin is protected by specialized ESD structures that allow bipolar ±2V continuous voltage, with respect to AGND, to be present at their inputs without the risk of permanent damage. All channels have fully differential voltage inputs for better noise performance. The absolute voltage at each pin, relative to AGND, should be maintained in the ±1V range during operation in order to ensure the specified ADC accuracy. The Common-mode signals should be adapted to respect both the previous conditions and the differential input voltage range. For best performance, the Common-mode signals should be maintained to AGND. Note: 5.2 If the analog inputs are held to a potential of -0.6 to -1V for extended periods of time, MCLK must be present inside the device in order to avoid large leakage currents at the analog inputs. This is true even during Hard Reset mode or during the Soft Reset of all ADCs. However, during the Shutdown mode of all the ADCs or during the POR state, the clock is not distributed inside the circuit. During these states, it is recommended to keep the analog input voltages above -0.6V, referred to as AGND, to avoid high analog input leakage currents. Programmable Gain Amplifiers (PGAs) The Programmable Gain Amplifiers (PGAs) reside at the front end of each Delta-Sigma ADC. They have two functions: translate the Common-mode voltage of the input from AGND to an internal level between AGND and AVDD, and amplify the input differential signal. The translation of the Common-mode voltage does not change the differential signal, but re-centers the Common-mode so that the input signal can be properly amplified. The PGA block can be used to amplify very low signals, but the differential input range of the Delta-Sigma modulator must not be exceeded. The PGA for Channel n is controlled by the PGA_CHn[2:0] bits in the GAIN register. Table 5-1 displays the gain settings for the PGA.  2012-2020 Microchip Technology Inc. TABLE 5-1: PGA CONFIGURATION SETTING Gain PGA_CHn[2:0] Gain (V/V) Gain (dB) 0 VIN Range (V) 0 0 0 1 ±0.6 0 0 1 2 6 ±0.3 0 1 0 4 12 ±0.15 0 1 1 8 18 ±0.075 1 0 0 16 24 ±0.0375 1 0 1 32 30 ±0.01875 Note: The two undefined settings are G = 1. This table is defined with VREF = 1.2V. 5.3 5.3.1 Delta-Sigma Modulator ARCHITECTURE All ADCs are identical in the MCP3910 and they include a proprietary second-order modulator with a multibit 5-level DAC architecture (see Figure 5-1). The quantizer is a Flash ADC, composed of four comparators with equally spaced thresholds and a thermometer output coding. The proprietary 5-level architecture ensures minimum quantization noise at the outputs of the modulators, without disturbing linearity or inducing additional distortion. The sampling frequency is DMCLK (typically 1 MHz with MCLK = 4 MHz), so the modulators are refreshed at a DMCLK rate. Figure 5-1 represents a simplified block diagram of the Delta-Sigma ADC present on MCP3910. Loop Filter Differential Voltage Input SecondOrder Integrator Quantizer Output Bitstream 5-Level Flash ADC DAC MCP3910 Delta-Sigma Modulator FIGURE 5-1: Block Diagram. Simplified Delta-Sigma ADC DS20005116D-page 31 MCP3910 5.3.2 MODULATOR INPUT RANGE AND SATURATION POINT 5.3.3 The Delta-Sigma modulators include a programmable biasing circuit in order to further adjust the power consumption to the sampling speed applied through the MCLK. This can be programmed through the BOOST[1:0] bits, which are applied to all channels simultaneously. For a specified voltage reference value of 1.2V, the specified differential input range is ±600 mV. The input range is proportional to VREF and scales according to the VREF voltage. This range ensures the stability of the modulator over amplitude and frequency. Outside of this range, the modulator is still functional; however, its stability is no longer ensured, and therefore, it is not recommended to exceed this limit. The saturation point for the modulator is VREF/1.5, since the transfer function of the ADC includes a gain of 1.5 by default (independent from the PGA setting). See Section 5.5 “ADC Output Coding”. TABLE 5-2: BOOST SETTINGS The maximum achievable Analog Master Clock (AMCLK) speed, the maximum sampling frequency (DMCLK) and the maximum achievable data rate (DRCLK) are highly dependent on the BOOST[1:0] and PGA_CHn[2:0] settings. Table 5-2 specifies the maximum AMCLK possible to keep optimal accuracy in the function of BOOST[1:0] and PGA_CHn[2:0] settings. MAXIMUM AMCLK LIMITS AS A FUNCTION OF BOOST AND PGA GAIN Conditions VDD = 3.0V to 3.6V, TA from -40°C to +125°C VDD = 2.7V to 3.6V, TA from -40°C to +125°C Boost Gain Maximum AMCLK (MHz) (SINAD within -3 dB from its maximum) Maximum AMCLK (MHz) (SINAD within -5 dB from its maximum) Maximum AMCLK (MHz) (SINAD within -3 dB from its maximum) Maximum AMCLK (MHz) (SINAD within -5 dB from its maximum) 0.5x 1 4 4 4 4 0.66x 1 6.4 7.3 6.4 7.3 1x 1 11.4 11.4 10.6 10.6 2x 1 16 16 16 16 0.5x 2 4 4 4 4 0.66x 2 6.4 7.3 6.4 7.3 1x 2 11.4 11.4 10.6 10.6 2x 2 16 16 13.3 14.5 0.5x 4 2.9 2.9 2.9 2.9 0.66x 4 6.4 6.4 6.4 6.4 1x 4 10.7 10.7 9.4 10.7 2x 4 16 16 16 16 0.5x 8 2.9 4 2.9 4 0.66x 8 7.3 8 6.4 7.3 1x 8 11.4 12.3 8 8.9 2x 8 16 16 10 11.4 0.5x 16 2.9 2.9 2.9 2.9 0.66x 16 6.4 7.3 6.4 7.3 1x 16 11.4 11.4 9.4 10.6 2x 16 13.3 16 8.9 11.4 0.5x 32 2.9 2.9 2.9 2.9 0.66x 32 7.3 7.3 7.3 7.3 1x 32 10.6 12.3 9.4 10,6 2x 32 13.3 16 10 11.4 DS20005116D-page 32  2012-2020 Microchip Technology Inc. MCP3910 5.3.4 DITHER SETTINGS All modulators include a dithering algorithm that can be enabled through the DITHER[1:0] bits in the CONFIG0 register. This dithering process improves THD and SFDR (for high OSR settings), while slightly increasing the noise floor of the ADCs. For power metering applications and applications that are distortion-sensitive, it is recommended to keep dither at maximum settings for best THD and SFDR performance. In the case of power metering applications, THD and SFDR are critical specifications. Optimizing SNR (noise floor) is not problematic due to the large averaging factor at the output of the ADCs. Therefore, even for low OSR settings, the dithering algorithm will show a positive impact on the performance of the application. 5.3.5 MODULATOR OUTPUT BLOCK If the user wishes to use the modulator output of the device, the appropriate bits to enable the modulator output must be set in the STATUSCOM register. When EN_MDAT = 1, the modulator output of the corresponding channel is present at the corresponding MDAT output pin as soon as the command is placed. Additionally, the corresponding SINC filter is disabled in order to consume less current. The corresponding data ready pulse is also not present at the DR output pin. The data ready output pin is then placed in highimpedance, regardless of the DR_HIZ setting, so that the user can tie this pin to an external supply or ground for lower noise behavior. When EN_MDAT = 0, the corresponding SINC filters are back to normal operation and the corresponding MDAT outputs are in high-impedance. Since the Delta-Sigma modulators have a 5-level output given by the state of the four comparators with thermometer coding, their outputs can be represented on four bits, each bit giving the state of the corresponding comparator (see Table 5-3). These bits are present on the MOD register and are updated at the DMCLK rate. In order to output the comparators’ result on a separate pin (MDAT0 and MDAT1), these comparator output bits have been arranged to be serially output at the AMCLK rate (see Figure 5-2). This 1-bit serial bitstream is the same as would be produced by a 1-bit DAC modulator with a sampling frequency of AMCLK. The modulator can either be considered as a 5-level output at DMCLK rate or a 1-bit output at AMCLK rate. These two representations are interchangeable. The MDAT outputs can therefore be used in any application that requires 1-bit modulator outputs. Such applications will often integrate and filter the 1-bit output with SINC or more complex decimation filters computed by an MCU or a DSP.  2012-2020 Microchip Technology Inc. TABLE 5-3: DELTA-SIGMA MODULATOR CODING COMP[3:0] Code Modulator Output Code MDAT Serial Stream 1111 +2 1111 0111 +1 0111 0011 0 0011 0001 -1 0001 0000 -2 0000 COMP COMP COMP COMP [0] [1] [3] [2] AMCLK DMCLK MDAT+2 MDAT+1 MDAT+0 MDAT-1 MDAT-2 FIGURE 5-2: MDAT Serial Outputs in Function of the Modulator Output Code. Since the Reset and shutdown SPI commands are asynchronous, the MDAT pins are resynchronized with DMCLK after each time the part goes out of Reset and shutdown. This means that the first output of MDAT, after a Soft Reset or a shutdown, is always ‘0011’ after the first DMCLK rising edge. The two MDAT output pins are high-impedance if the RESET pin is low and they are also in high-impedance state during the Two-Wire Interface mode. DS20005116D-page 33 MCP3910 5.4 SINC3 + SINC1 Filter The decimation filter present in all channels of the MCP3910 is a cascade of two SINC filters (SINC3 + SINC1): a third-order SINC filter with a decimation ratio of OSR3, followed by a first-order SINC filter with a decimation ratio of OSR1 (moving average of OSR1 values). Figure 5-3 represents the decimation filter architecture. OSR1 = 1 Modulator Output SINC3 SINC1 4 Decimation Filter Output 16 (WIDTH = 0) 24 (WIDTH = 1) OSR3 OSR1 Decimation Filter FIGURE 5-3: DS20005116D-page 34 MCP3910 Decimation Filter Block Diagram.  2012-2020 Microchip Technology Inc. MCP3910 Equation 5-1 calculates the filter z-domain transfer function. EQUATION 5-1: SINC FILTER TRANSFER FUNCTION - OSR 1  OSR 3 - OSR 3 3 1 – z  1 – z      H  z  = ----------------------------------------------  --------------------------------------------------------3 – 1 OSR  OSR  1 – z   3 3 OSR   1 – z  1  Where z = EXP   2   j  f in    DMCLK   Equation 5-2 calculates the settling time of the ADC as a function of DMCLK periods. EQUATION 5-2: SettlingTime  DMCLKperiods = 3  OSR +  OSR – 1   OSR 3 1 3 The SINC1 filter following the SINC3 filter is only enabled for the high OSR settings. This SINC1 filter provides additional rejection at a low cost with little modification to the -3 dB bandwidth. The resolution (number of significant bits) of the digital filter is a 24-bit maximum for any OSR and data format choice. The resolution depends only on the OSR[2:0] settings in the CONFIG0 register per Table 5-4. Once the OSR is chosen, the resolution is fixed and the output code TABLE 5-4: 0 0 1 1 0 0 1 1 The gain of the transfer function of this filter is one at each multiple of DMCLK (typically 1 MHz), so a proper anti-aliasing filter must be placed at the inputs. This will attenuate the frequency content around DMCLK and keep the desired accuracy over the baseband of the converter. This anti-aliasing filter can be a simple, first-order RC network, with a sufficiently low time constant to generate high rejection at the DMCLK frequency. Any unsettled data are automatically discarded to avoid data corruption. Each data ready pulse corresponds to fully settled data at the output of the decimation filter. The first data available at the output of the decimation filter are present after the complete settling time of the filter (see Table 5-4). After the first data have been processed, the delay between two data ready pulses is one DRCLK period. The data stream from input to output is delayed by an amount equal to the settling time of the filter (which is the group delay of the filter). The resolution achievable, the -3 dB bandwidth and the settling time at the output of the decimation filter (the output of the ADC) are dependent on the OSR of each SINC filter and are summarized in Table 5-4. OVERSAMPLING RATIO AND SINC FILTER SETTLING TIME OSR[2:0] 0 0 0 0 1 1 1 1 respects the data format defined by the WIDTH_DATA[1:0] setting in the STATUSCOM register (see Section 5.5 “ADC Output Coding”). 0 1 0 1 0 1 0 1 OSR3 OSR1 Total OSR Resolution in Bits (No Missing Code) Settling Time -3 dB Bandwidth 32 64 128 256 512 512 512 512 1 1 1 1 1 2 4 8 32 64 128 256 512 1024 2048 4096 17 20 23 24 24 24 24 24 96/DMCLK 192/DMCLK 384/DMCLK 768/DMCLK 1536/DMCLK 2048/DMCLK 3072/DMCLK 5120/DMCLK 0.26*DRCLK 0.26*DRCLK 0.26*DRCLK 0.26*DRCLK 0.26*DRCLK 0.37*DRCLK 0.42*DRCLK 0.43*DRCLK 0 0 -20 Magnitude (dB) Ma agnitude (dB) -20 -40 -60 -80 -100 -40 -60 -80 -100 -120 -140 -120 1 10 100 1000 10000 100000 -160 1 Input Frequency (Hz) FIGURE 5-4: SINC Filter Frequency Response, OSR = 256, MCLK = 4 MHz, PRE[1:0] = 00.  2012-2020 Microchip Technology Inc. 100 10000 Input Frequency (Hz) 1000000 FIGURE 5-5: SINC Filter Frequency Response, OSR = 4096 (in pink), OSR = 512 (in blue), MCLK = 4 MHz, PRE[1:0] = 00. DS20005116D-page 35 MCP3910 5.5 Equation 5-3 is only true for DC inputs. For AC inputs, this transfer function needs to be multiplied by the transfer function of the SINC3 + SINC1 filter (see Equation 5-1 and Equation 5-3). ADC Output Coding The second-order modulator, SINC3 + SINC1 filter, PGA, VREF and the analog input structure, all work together to produce the device transfer function for the Analog-to-Digital conversion (see Equation 5-3). EQUATION 5-3: Each channel data are calculated on 24 bits (23 bits plus sign) and coded in two’s complement format, MSB first. The output format can then be modified by the WIDTH_DATA[1:0] settings in the STATUSCOM register to allow 16, 24 or 32-bit format compatibility (see Section 9.5 “STATUSCOM Register – Status and Communication Register” for more information). DATA_CHn = (CHn+ – CHn-)  8,388.608  G  1.5  VREF+ – VREF-  For 24-Bit Mode, WIDTH_DATA[1:0] = 01 (Default) For data formats other than the default 24-bit format, Equation 5-3 should be multiplied by a scaling factor, depending on the data format used (defined by WIDTH_DATA[1:0]). The data format and the associated scaling factors are given in Figure 5-6. In case of positive saturation (CHn+ – CHn- > VREF/1.5), the output is locked to 7FFFFF for 24-bit mode. In case of negative saturation (CHn+ – CHn- < -VREF/1.5), the output code is locked to 800000 for 24-bit mode. 23 0 DATA DATA [23:16] [15:8] 15 WIDTH_DATA = 00 16-Bit DATA DATA [23:16] [15:8] Scaling Factor DATA [7:0] 0 DATA Unformatted ADC Data x1/256 Rounded WIDTH_DATA = 01 24-Bit 23 WIDTH_DATA = 10 32-Bit with Zeros Padded 31 WIDTH_DATA = 11 32-Bit with Sign Extension FIGURE 5-6: DS20005116D-page 36 DATA DATA [23:16] [15:8] 0 DATA [7:0] x1 0 DATA DATA [23:16] [15:8] DATA [7:0] DATA DATA DATA [23] [23:16] [15:8] DATA [7:0] 31 0x00 x256 0 x1 Output Data Formats.  2012-2020 Microchip Technology Inc. MCP3910 The ADC resolution is a function of the OSR (Section 5.4 “SINC3 + SINC1 Filter”). The resolution is the same for all channels. No matter what the resolution is, the ADC output data are always calculated in TABLE 5-5: 24-bit words, with added zeros at the end if the OSR is not large enough to produce 24-bit resolution (left justification). OSR = 256 (AND HIGHER) OUTPUT CODE EXAMPLES ADC Output Code (MSB First) 0 0 0 1 1 1 1 1 0 1 0 0 1 1 0 1 0 0 1 1 0 1 0 0 1 1 0 1 0 0 1 1 0 1 0 0 TABLE 5-6: 1 1 0 1 0 0 1 1 0 1 0 0 1 1 0 1 0 0 1 1 0 1 0 0 1 1 0 1 0 0 1 1 0 1 0 0 1 1 0 1 0 0 1 1 0 1 0 0 1 1 0 1 0 0 1 1 0 1 0 0 1 1 0 1 0 0 1 1 0 1 0 0 1 1 0 1 0 0 1 1 0 1 0 0 1 1 0 1 0 0 1 1 0 1 0 0 1 1 0 1 0 0 1 0 0 1 1 0 1 1 0 1 0 0 1 1 0 1 0 0 1 1 0 1 0 0 1 1 0 1 0 0 1 1 0 1 0 0 TABLE 5-7: 1 1 0 1 0 0 1 1 0 1 0 0 1 1 0 1 0 0 1 1 0 1 0 0 1 1 0 1 0 0 1 1 0 1 0 0 1 1 0 1 0 0 1 1 0 1 0 0 1 1 0 1 0 0 1 0 0 1 0 0 1 1 0 1 0 0 1 1 0 1 0 0 1 1 0 1 0 0 1 1 0 1 0 0 1 1 0 1 0 0 1 1 0 1 0 0 1 0 0 1 1 0 0 0 0 0 0 0 1 1 0 1 0 0 1 1 0 1 0 0 1 1 0 1 0 0 1 1 0 1 0 0 1 1 0 1 0 0 TABLE 5-8: 1 1 0 1 0 0 1 1 0 1 0 0 1 1 0 1 0 0 1 1 0 1 0 0 1 1 0 1 0 0 1 1 0 1 0 0 1 1 0 1 0 0 1 1 0 1 0 0 1 1 0 1 0 0 1 1 0 1 0 0 1 1 0 1 0 0 1 1 0 1 0 0 1 1 0 1 0 0 1 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 0 0 1 1 0 1 0 0 1 1 0 1 0 0 + 8,388,607 + 8,388,606 0 -1 - 8,388,607 - 8,388,608 Hexadecimal Decimal, 23-Bit Resolution 0x7FFFFE 0x7FFFFC 0x000000 0xFFFFFE 0x800002 0x800000 + 4,194,303 + 4,194,302 0 -1 - 4,194,303 - 4,194,304 Hexadecimal Decimal, 20-Bit Resolution 0x7FFFF0 0x7FFFE0 0x000000 0xFFFFF0 0x800010 0x800000 + 524, 287 + 524, 286 0 -1 - 524,287 - 524, 288 Hexadecimal Decimal, 17-Bit Resolution 0x7FFF80 0x7FFF00 0x000000 0xFFFF80 0x800080 0x800000 + 65, 535 + 65, 534 0 -1 - 65,535 - 65, 536 OSR = 32 OUTPUT CODE EXAMPLES ADC Output Code (MSB First) 0 0 0 1 1 1 0x7FFFFF 0x7FFFFE 0x000000 0xFFFFFF 0x800001 0x800000 OSR = 64 OUTPUT CODE EXAMPLES ADC Output Code (MSB First) 0 0 0 1 1 1 Decimal, 24-Bit Resolution OSR = 128 OUTPUT CODE EXAMPLES ADC Output Code (MSB First) 0 0 0 1 1 1 Hexadecimal 1 1 0 1 0 0 1 1 0 1 0 0 1 1 0 1 0 0 1 1 0 1 0 0 1 1 0 1 0 0 1 1 0 1 0 0 1 1 0 1 0 0 1 1 0 1 0 0  2012-2020 Microchip Technology Inc. 1 1 0 1 0 0 1 1 0 1 0 0 1 1 0 1 0 0 1 1 0 1 0 0 1 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DS20005116D-page 37 MCP3910 5.6.1 Voltage Reference INTERNAL VOLTAGE REFERENCE The MCP3910 contains an internal voltage reference source specially designed to minimize drift over temperature. In order to enable the internal voltage reference, the VREFEXT bit in the CONFIG1 register must be set to ‘0’ (default mode). This internal VREF supplies reference voltage to all channels. The typical value of this voltage reference is 1.2V, ±2%. The internal reference has a very low typical temperature coefficient of ±9 ppm/°C, allowing the output to have minimal variation with respect to temperature, since it is proportional to (1/VREF). The noise of the internal voltage reference is low enough not to significantly degrade the SNR of the ADC if compared to a precision external low noise voltage reference. The output pin for the internal voltage reference is REFIN+/OUT. If the voltage reference is only used as an internal VREF, adding bypass capacitance on REFIN+/OUT is not necessary for keeping ADC accuracy, but a minimal 0.1 µF ceramic capacitance can be connected to avoid EMI/EMC susceptibility issues due to the antenna created by the REFIN+/OUT pin, if left floating. The bypass capacitors also help in applications where the voltage reference output is connected to other circuits. In this case, additional buffering may be needed, since the output drive capability of this output is low. Adding too much capacitance on the REFIN+/OUT pin may slightly degrade the THD performance of the ADCs. 5.6.2 DIFFERENTIAL EXTERNAL VOLTAGE INPUTS When the VREFEXT bit is set to ‘1’, the two reference pins (REFIN+/OUT, REFIN-) become a differential voltage reference input. The voltage at the REFIN+/OUT is noted VREF+ and the voltage at the REFIN- pin is noted VREF-. The differential voltage input value is given by Equation 5-4. EQUATION 5-4: VREF = VREF+ – VREFThe specified VREF range is from 1.1V to 1.3V. The REFIN- pin voltage (VREF-) should be limited to ±0.1V, with respect to AGND. Typically, for single-ended reference applications, the REFIN- pin should be directly connected to AGND with its own separate track to avoid any spike due to switching noise. DS20005116D-page 38 5.6.3 TEMPERATURE COMPENSATION (VREFCAL[7:0]) The internal voltage reference consists of a proprietary circuit and algorithm to compensate first-order and second-order temperature coefficients. The compensation enables very low-temperature coefficients (typically, 9 ppm/°C) on the entire range of temperatures, from -40°C to +125°C. This temperature coefficient varies from part to part. This temperature coefficient can be adjusted on each part through the VREFCAL[7:0] bits present in the CONFIG0 register (bits 7 to 0). These register settings are only for advanced users. VREFCAL[7:0] should not be modified unless the user wants to calibrate the temperature coefficient of the whole system or application. The default value of this register is set to 0x50. This value was chosen to optimize the standard deviation of the tempco across process variation. The value can be slightly improved to around 7 ppm/°C if the VREFCAL[7:0] are written at 0x42, but this setting degrades the standard deviation of the VREF tempco. The typical variation of the temperature coefficient of the internal voltage reference, with respect to the VREFCAL register code, is given by Figure 5-7. Modifying the value stored in the VREFCAL[7:0] bits may also vary the voltage reference, in addition to the temperature coefficient. 60 50 VREF Drift (ppm) 5.6 40 30 20 10 0 0 64 128 192 VREFCAL Register Trim Code (decimal) 256 FIGURE 5-7: VREF Tempco vs. VREFCAL[7:0] Trim Code Chart. 5.6.4 VOLTAGE REFERENCE BUFFERS Each channel includes a voltage reference buffer tied to the REFIN+/OUT pin, which allows the device to properly charge the internal capacitors with the voltage reference signals, even in the case of an external voltage reference connection with weak load regulation specifications. This ensures that the correct amount of current is sourced to each channel to ensure their accuracy specifications, and diminishes the constraints on the voltage reference load regulation.  2012-2020 Microchip Technology Inc. MCP3910 5.7 Power-on Reset (POR) The MCP3910 contains an internal POR circuit that monitors both analog and digital supply voltages during operation. The typical threshold for a power-up event detection is 2.0V, ±5%, and a typical start-up time (tPOR) of 50 µs. The POR circuit has a built-in hysteresis for improved transient spike immunity that has a typical value of 200 mV. Proper decoupling capacitors (0.1 µF ceramic and 10 µF) should be mounted as close as possible to the AVDD and DVDD pins, providing additional transient immunity. Both AVDD and DVDD are monitored, so either power supply can sequence first. Note: Figure 5-8 illustrates the different conditions at a power-up and a power-down event under typical conditions. All internal DC biases are settled at least 1 ms after system POR, under worst-case conditions. Any data ready pulse occurring within 1 ms, plus the SINC filter settling time after system Reset, should be ignored to ensure proper accuracy. After POR, data ready pulses are present at the pin with all the default conditions in the Configuration registers. In order to ensure a proper power-up sequence, the ramp rate of DVDD should not exceed 3V/µs when coming out of the POR state. Additionally, the user should try to lower the DVDD residual voltage as close to 0V as possible when the device is kept in a POR state (below DVDD POR threshold) for a long time to ensure a proper power-up sequence. The user can verify if the power-up sequence has been correctly performed by reading the default state of all the registers in the register map right after powering up the device. If one or more of the registers do not show the proper default settings when being read, a new power-up cycle should be launched to recover from this condition. Voltage (AVDD, DVDD) Any data read pulse occurring during this time can yield inaccurate output data. It is recommended to discard them. POR Threshold Up (2.0V typical) (1.8V typical) tPOR POR State Analog Biases Settling Time Power-up SINC Filter Settling Time Normal Operation Time POR State Biases are settled. Biases are Conversions started unsettled. here are accurate. Conversions started here may not be accurate. FIGURE 5-8: Power-on Reset Operation.  2012-2020 Microchip Technology Inc. DS20005116D-page 39 MCP3910 5.8 Hard Reset Effect on Delta-Sigma Modulator/SINC Filter EQUATION 5-5: Total Delay = PHASE[11:0] Decimal Code DMCLK In SPI mode, when the RESET pin is logic low, all ADCs will be in Reset and output code, 0x0000h. The RESET pin performs a hard Reset (DC biases are still on, part is ready to convert) and clears all charges contained in the Delta-Sigma modulators. The comparators’ output is ‘0011’ for each ADC. The timing resolution of the phase delay is 1/DMCLK or 1 µs in the default configuration with MCLK = 4 MHz. The SINC filters are all reset, as well as their doubleoutput buffers. This pin is independent of the serial interface. It brings all the registers to the default state. When RESET is logic low, any write with the SPI interface will be disabled and will have no effect. All output pins (SDO, DR) are high-impedance. The data ready signals are affected by the phase delay settings. Typically, the time difference between the data ready pulses of odd and even channels is equal to the associated phase delay setting. If MCLK is applied, the input structure is enabled and is properly biasing the substrate of the input transistors. In this case, the leakage current on the analog inputs is low if the analog input voltages are kept between -1V and +1V. If MCLK is not applied when in Reset mode, the leakage can be high if the analog inputs are below -0.6V, as referred to AGND. 5.9 Given the definition of DMCLK, the phase delay is affected by a change in the prescaler settings (PRE[1:0]) and the MCLK frequency. Each ADC conversion start, and therefore, each data ready pulse is delayed by a timing of OSR/2 x DMCLK periods (equal to half of a DRCLK period). This timing allows for the odd channel data ready signals to be located at a fixed time reference (OSR/2 x DMCLK periods from the Reset), while the even channel can be leading or lagging around this time reference with the corresponding PHASE[11:0] delay value. Note: For a detailed explanation of the Data Ready pin behavior, see Figure 5-9. Phase Delay Block The MCP3910 incorporates a phase delay generator, which ensures that CH0 and CH1 ADC are converting the two analog inputs with a fixed delay between them. The two ADCs are synchronously sampling, but the averaging of modulator outputs is delayed so that the SINC filter outputs (thus the ADC outputs) show a fixed phase delay, as determined by the PHASE register setting. The odd channel (CH1) is the reference channel for the phase delay for the CH0/1 pair; it sets the time reference. Typically, this channel can be the voltage channel for a single-phase energy metering application. The even channel (CH0) is delayed, compared to the time reference (CH1) by a fixed amount of time defined in the PHASE register. The PHASE register contains a 12-bit bank that represents the delay between the two channels. This phase value represents the delay of the even channel, with respect to the associated odd channel, with a 11-bit plus sign, MSB first, two’s complement code. This code indicates how many DMCLK periods there are between each channel in the pair (see Equation 5-5). Since the odd channel is the time reference, when PHASE[11:0] are positive, the even channel of the pair is lagging and the odd channel is leading. When PHASE[11:0] are negative, the even channel of the pair is leading and the odd channel is lagging. DS20005116D-page 40 5.9.1 PHASE DELAY LIMITS The limits of the phase delays are determined by the OSR settings: the phase delays can only go from -OSR/2 to +OSR/2-1 DMCLK periods. If larger delays between the two channels are needed, they can be implemented externally to the chip with an MCU. A FIFO in the MCU can save incoming data from the leading channel for a number N of DRCLK clocks. In this case, DRCLK would represent the coarse timing resolution and DMCLK the fine timing resolution. The total delay will then be equal to: EQUATION 5-6: Total Delay = N/DRCLK + PHASE/DMCLK Note: Rewriting the PHASE registers with the same value automatically resets and restarts all ADCs.  2012-2020 Microchip Technology Inc. MCP3910 The Phase Delay registers can be programmed once with the OSR = 4096 setting and will adjust the OSR automatically afterward without the need to change the value of the PHASE registers. • OSR = 4096: The delay can go from -2048 to +2047. PHASE[11] is the sign bit. PHASE[10] is the MSB and PHASE[0] is the LSB. • OSR = 2048: The delay can go from -1024 to +1023. PHASE[10] is the sign bit. PHASE[9] is the MSB and PHASE[0] is the LSB. • OSR = 1024: The delay can go from -512 to +511. PHASE[9] is the sign bit. PHASE[8] is the MSB and PHASE[0] is the LSB. • OSR = 512: The delay can go from -256 to +255 PHASE[8] is the sign bit. PHASE[7] is the MSB and PHASE[0] is the LSB. • OSR = 256: The delay can go from -128 to +127. PHASE[7] is the sign bit. PHASE[6] is the MSB and PHASE[0] is the LSB. • OSR = 128: The delay can go from -64 to +63. PHASE[6] is the sign bit. PHASE[5] is the MSB and PHASE[0] is the LSB. • OSR = 64: The delay can go from -32 to +31. PHASE[5] is the sign bit. PHASE[4] is the MSB and PHASE[0] is the LSB. • OSR = 32: The delay can go from -16 to +15. PHASE[4] is the sign bit. PHASE[3] is the MSB and PHASE[0] is the LSB. TABLE 5-9: PHASE VALUES WITH MCLK = 4 MHz, OSR = 4096, PRE[1:0] = 00 PHASE[11:0] Hex Delay (CH0 relative to CH1) 0 1 1 1 1 1 1 1 1 1 1 1 0x7FF + 2047 µs 0 1 1 1 1 1 1 1 1 1 1 0 0x7FE + 2046 µs 0 0 0 0 0 0 0 0 0 0 0 1 0x001 + 1 µs 0 0 0 0 0 0 0 0 0 0 0 0 0x000 0 µs 1 1 1 1 1 1 1 1 1 1 1 1 0xFFF – 1 µs 1 0 0 0 0 0 0 0 0 0 0 1 0x801 – 2047 µs 1 0 0 0 0 0 0 0 0 0 0 0 0x800 – 2048 µs  2012-2020 Microchip Technology Inc. 5.10 Crystal Oscillator The MCP3910 includes a Pierce-type crystal oscillator with very high stability, and ensures very low tempco and jitter for the clock generation. This oscillator can handle crystal frequencies up to 20 MHz, provided that proper load capacitances and quartz quality factor are used. The crystal oscillator is enabled when CLKEXT = 0 in the CONFIG1 register, therefore it cannot be enabled during the Two-Wire Interface mode; it is only selectable in the SPI mode. For a proper start-up, the load capacitors of the crystal should be connected between OSC1 and DGND, and between OSC2 and DGND. They should also respect Equation 5-7. EQUATION 5-7: 2 6 1 R M < 1.6  10   -------------------------  f  C LOAD Where: f = Crystal frequency in MHz CLOAD = Load capacitance in pF including parasitics from the PCB RM = Motional resistance of the quartz, in ohms When CLKEXT = 1, the crystal oscillator is bypassed by a digital buffer to allow direct clock input for an external clock (see Figure 4-1). In this case, OSC2 becomes the MODE select input pin for the Interface mode. When MODE = 0, the digital interface stays in SPI mode; when MODE = 1, the digital interface toggles to the Two-Wire mode. A pull-down current forces the MODE to be logic low (SPI mode) by default if the OSC2 pin is floating. The external clock should not be higher than 20 MHz before prescaling (MCLK < 20 MHz) for proper operation. Note: In addition to the conditions defining the maximum MCLK input frequency range, the AMCLK frequency should be maintained inferior to the maximum limits defined in Table 5-2 to ensure the accuracy of the ADCs. If these limits are exceeded, it is recommended to choose either a larger OSR or a larger prescaler value so that AMCLK can respect these limits. DS20005116D-page 41 MCP3910 5.11 Data Ready Status Bits 5.12 In addition to the Data Ready pin indicator, the MCP3910 device includes a separate data ready status bit for each channel. Each ADC channel, CHn, is associated with the corresponding DRSTATUS[n] that can be read at all times in the STATUSCOM register. These status bits can be used to synchronize the data retrieval in case the DR pin is not connected (see Section 6.8 “ADC Channels Latching and Synchronization”). The DRSTATUS[1:0] bits are not writable; writing on them has no effect. They have a default value of ‘1’, which indicates that the data of the corresponding ADC are not ready. This means that the ADC Output register has not been updated since the last reading (or since the last Reset). The DRSTATUS bits take the ‘0’ state once the ADC Channel register is updated (which happens at a DRCLK rate). A simple read of the STATUSCOM register clears all the DRSTATUS bits to their default value (‘1’). In the case of DR_LINK = 1, the DRSTATUS[1:0] bits are all updated synchronously with the most lagging channel; in the same time, the data ready pulse is generated. In case of DR_LINK = 0, each DRSTATUS bit is updated independently and synchronously with its corresponding channel. PHASE < 0 Data Ready Link There are two modes defined with the DR_LINK bit, in the STATUSCOM register, that control the data ready pulses. The position of the data ready pulses varies with respect to this mode, to the OSR[2:0] and to the PHASE register settings. Figure 5-9 represents the behavior of the Data Ready pin with the two DR_LINK configurations. • DR_LINK = 0: Both data ready pulses from ADC Channel 0 and ADC Channel 1 are output on the DR pin. • DR_LINK = 1 (Recommended and Default mode): Only the data ready pulses from the most lagging ADC, between all the active ADCs, are present on the DR pin. The lagging ADC data ready position depends on the PHASE0/1 registers, the PRE[1:0] and the OSR[2:0] settings. In this mode, the active ADCs are linked together, so their data are latched together when the lagging ADC output is ready. For power metering applications, DR_LINK = 1 is recommended (default mode). It allows the host MCU to gather all channels synchronously within a unique interrupt pulse and it ensures that all channels have been latched at the same time, so that no data corruption is happening. PHASE > 0 DR DR_LINK = 0 All channels data ready are present Data ready pulse from CH0 channel if PHASE < 0 Data ready pulse from CH1 channel (reference) PHASE = 0 Data ready pulse from most lagging ADC channel (here CH0 channel lags) Data ready pulse from CH1 Data ready pulse from most lagging ADC channel DR DR_LINK = 1 Only the most lagging data ready is present All channels are latched together at DR falling edge FIGURE 5-9: DS20005116D-page 42 One DRCLK period (OSR times DMCLK periods) DR_LINK Configurations.  2012-2020 Microchip Technology Inc. MCP3910 5.13 Digital System Offset and Gain Errors The MCP3910 incorporates two sets of additional registers per channel to perform system digital offset and gain error calibration. Each channel has its own set of associated registers that will modify the output result of the channel if calibration is enabled. The gain and offset EQUATION 5-8: calibrations can be enabled or disabled through two Configuration bits (EN_OFFCAL and EN_GAINCAL). These two bits enable or disable system calibration on all channels at the same time. When both calibrations are enabled, the output of the ADC is modified per Equation 5-8. These calibrations are not effective in Two-Wire Interface mode. DIGITAL OFFSET AND GAIN ERROR CALIBRATION REGISTERS CALCULATIONS DATA_CHn  post – cal  =  DATA_CHn  pre – cal  + OFFCAL_CHn    1 + GAINCAL_CHn  5.13.1 DIGITAL OFFSET ERROR CALIBRATION The 23-bit OFFCAL_CHn registers are two’s complement registers whose LSB value is the same as the channel ADC data. These two registers are then added, bit by bit, to the ADC output codes if the EN_OFFCAL bit is enabled. Enabling the EN_OFFCAL bit does not create a pipeline delay; the offset addition is instantaneous. For low OSR values, only the significant digits are added to the output (up to the resolution of the ADC; for example, at OSR = 32, only the 17 first bits are added). The offset is not added when the corresponding channel is in Reset or Shutdown mode. The corresponding input voltage offset value added by each LSB in these 24-bit registers is: EQUATION 5-9: OFFSET(1 LSB) = VREF/(PGA_CHn x 1.5 x 8388608) These registers are “Don’t Care” if EN_OFFCAL = 0 (offset calibration disabled), but their value is not cleared by the EN_OFFCAL bit. 5.13.2 DIGITAL GAIN ERROR CALIBRATION This register is a 24-bit signed MSB first coding, with a range of -1x to +0.9999999x (from 0x80000 to 0x7FFFFF). The gain calibration adds 1x to this register and multiplies it to the output code of the channel, bit by bit, after offset calibration. The range of the gain calibration is thus from 0x to 1.9999999x (from 0x80000 to 0x7FFFFF). The LSB corresponds to a 2-23 increment in the multiplier. Enabling EN_GAINCAL creates a pipeline delay of 24 DMCLK periods on all channels. All data ready pulses are delayed by 24 DMCLK periods, starting from data ready following the command enabling the EN_GAINCAL bit. The gain calibration is effective on the next data ready following the command enabling the EN_GAINCAL bit. The digital gain calibration does not function when the corresponding channel is in Reset or Shutdown mode. The gain multiplier value for an LSB in these 24-bit registers is: EQUATION 5-10: GAIN (1 LSB) = 1/8388608 This register is a “Don’t Care” if EN_GAINCAL = 0 (offset calibration disabled), but its value is not cleared by the EN_GAINCAL bit. The output data on each channel are kept to either 7FFF or 8000 (16-bit mode), or 7FFFFF or 800000 (24-bit mode) if the output results are out of bounds after all calibrations are performed.  2012-2020 Microchip Technology Inc. DS20005116D-page 43 MCP3910 NOTES: DS20005116D-page 44  2012-2020 Microchip Technology Inc. MCP3910 6.0 SPI SERIAL INTERFACE DESCRIPTION 6.1 Overview The MCP3910 device includes a four-wire (CS, SCK, SDI, SDO) digital serial interface that is compatible with SPI Modes 0,0 and 1,1. Data are clocked out of the MCP3910 on the falling edge of SCK and data are clocked into the MCP3910 on the rising edge of SCK. In these modes, the SCK clock can Idle either high (1,1) or low (0,0). The digital interface is asynchronous with the MCLK clock that controls the ADC sampling and digital filtering. All the digital input pins are Schmitt triggered to avoid system noise perturbations on the communications. Each SPI communication starts with a CS falling edge and stops with the CS rising edge. Each SPI communication is independent. When CS is logic high, SDO is in high-impedance; transitions on SCK and SDI have no effect. Changing from an SPI Mode 1,1 to an SPI Mode 0,0, and vice-versa, is possible and can be done while the CS pin is logic high. Any CS rising edge clears the communication and resets the SPI digital interface. Additional control pins (RESET, DR) are also provided on separate pins for advanced communication features. The Data Ready pin (DR) outputs pulses when new ADC channel data are available for reading, which can be used as an interrupt for an MCU. The Master Reset pin (RESET) acts like a Hard Reset and can reset the part to its default power-up configuration (equivalent to a POR state). The MCP3910 interface has a simple command structure. Every command is either a READ command from a register or a WRITE command to a register. The MCP3910 device includes 13 registers, defined in the register map in Table 9-1. The register map is fully compatible with the MCP391X family to allow easy porting of MCU code from one design to another inside the MCP391X family. The first byte (8-bit wide) transmitted is always the control byte that defines the address of the register and the type of command (READ or WRITE). It is followed by the register itself, which can be in a 16, 24 or 32-bit format, depending on the multiple format settings defined in the STATUSCOM register. The MCP3910 is compatible with multiple formats that help reduce overhead in the data handling for most MCUs and processors available on the market (8, 16 or 32-bit MCUs) and improve MCU code compaction and efficiency. The MCP3910 digital interface is capable of handling various Continuous Read and Write modes, which allow the device to perform ADC data streaming or full register map writing within only one communication (and therefore, with only one unique control byte). The internal registers can be grouped together with various configurations through the READ[1:0] and WRITE bits. The internal address counter of the serial interface can be automatically incremented with no additional control  2012-2020 Microchip Technology Inc. byte needed in order to loop through the various groups of registers within the register map. The groups are defined in Table 9-2. The MCP3910 device also includes advanced security features to secure each communication, to avoid processing unwanted WRITE commands, in order to change the desired configuration and to alert the user in case of a change in the desired configuration. Each SPI read communication can be secured through a selectable CRC-16 checksum provided on the SDO pin at the end of every communication sequence. This CRC-16 computation is compatible with the DMA and CRC hardware of the PIC24 and PIC32 MCUs, resulting in no additional overhead for added security. In order to secure the entire configuration of the device, the MCP3910 includes an 8-bit lock code (LOCK[7:0]), which blocks all WRITE commands to the full register map if the value of the LOCK[7:0] bits are not equal to a defined password (0xA5). The user can protect its configuration by changing the LOCK[7:0] value to 0x00 after the full programming, so that no unwanted WRITE command will result in a change in the configuration (because the LOCK[7:0] bits are different from the 0xA5 password). An additional CRC-16 calculation is also running continuously in the background to ensure the integrity of the full register map. All writable registers of the register map (except the MOD register) are processed through a CRC-16 calculation engine and give a CRC-16 checksum that depends on the configuration. This checksum is readable on the LOCK/CRC register and updated at all times. If a change in this checksum happens, a selectable interrupt can give a flag on the DR pin (the DR pin becomes logic low) to warn the user that the configuration is corrupted. 6.2 Control Byte The control byte of the MCP3910 contains two device Address bits (A[6:5]), five register Address bits (A[4:0]) and a Read/Write bit (R/W). The first byte transmitted to the MCP3910 in any communication is always the control byte. During the control byte transfer, the SDO pin is always in a high-impedance state. The MCP3910 interface is device addressable (through A[6:5]), so that multiple chips can be present on the same SPI bus with no data bus contention, even if they use the same CS pin. They use a provided half-duplex SPI interface with a different address identifier. This functionality enables, for example, to have a serial EEPROM, such as 24AAXXX/24LCXXX or 24FCXXX, and the MCP3910 to share all the SPI pins and consume less I/O pins in the application processor, since all of these serial EEPROM circuits use A[6:5] = 00. DS20005116D-page 45 MCP3910 . 6.3 A[6] A[5] A[4] Device Address A[3] A[2] A[1] A[0] R/W Register Address FIGURE 6-1: Reading from the Device The first register read on the SDO pin is the one defined by the address (A[4:0]) given in the control byte. After this first register is fully transmitted, if the CS pin is maintained logic low, the communication continues without an additional control byte and the SDO pin transmits another register with the address automatically incremented. Read/ Write Control Byte. The default device Address bits are A[6:5] = 01 (contact the Microchip factory for other available device address bits). For more information, see the Product Identification System section. The register map is defined in Table 9-1. Four different Read mode configurations can be defined through the READ[1:0] bits in the STATUSCOM register for the address increment (see Section 6.5 “Continuous Communications, Looping on Register Sets” and Table 9-2). The data on SDO are clocked out of the MCP3910 on the falling edge of SCK. The reading format for each register is defined in Section 5.5 “ADC Output Coding”. CS Device latches SDI on rising edge Device latches SDO on falling edge DATA DATA DATA DATA DATA DATA DATA DATA DATA DATA DATA DATA DATA DATA DATA DATA DATA DATA DATA DATA DATA DATA High Hi-Z Z SDO Don’t care R/W DATA A A A A A Don’t care A SDI A SCK DATA High Hi-Z Z READ Communication (SPI mode 1,1) FIGURE 6-2: SPI Mode 1,1). Read on a Single Register with 24-Bit Format (WIDTH_DATA[1:0] = 01, CS Device latches SDI on rising edge Device latches SDO on falling edge DATA DATA DATA DATA DATA DATA DATA DATA DATA DATA DATA DATA DATA DATA DATA DATA DATA DATA DATA DATA DATA A A A A R/W DATA DATA HighHi-Z Z Don’t care DATA SDO A Don’t care A SDI A SCK Don’t care High Hi-Z Z READ Communication (SPI mode 0,0) FIGURE 6-3: SPI Mode 0,0). DS20005116D-page 46 Read on a Single Register with 24-Bit Format (WIDTH_DATA[1:0] = 01,  2012-2020 Microchip Technology Inc. MCP3910 6.4 Two different Write mode configurations for the address increment can be defined through the WRITE bit in the STATUSCOM register (see Section 6.5 “Continuous Communications, Looping on Register Sets” and Table 9-2). The SDO pin stays in a high-impedance state during a write communication. The data on SDI are clocked into the MCP3910 on the rising edge of SCK. The writing format for each register is defined in Section 5.5 “ADC Output Coding”. A write on an undefined or non-writable address, such as the ADC channel’s register addresses, will have no effect nor will it increment the address counter. Writing to the Device The first register written from the SDI pin to the device is the one defined by the Address bits (A[4:0]) given in the control byte. After this first register is fully transmitted, if the CS pin is maintained logic low, the communication continues without an additional control byte and the SDI pin transmits another register with the address automatically incremented. CS Device latches SDI on rising edge DATA DATA DATA DATA DATA DATA DATA DATA DATA DATA DATA DATA DATA DATA DATA DATA DATA DATA DATA DATA DATA DATA R/W DATA A A A A A Don’t care A SDI A SCK DATA Don’t care High Z Hi-Z SDO WRITE Communication (SPI mode 1,1) FIGURE 6-4: Write to a Single Register with 24-Bit Format (WIDTH_CRC = 0, SPI Mode 1,1). CS Device latches SDI on rising edge DATA DATA DATA DATA DATA DATA DATA DATA DATA DATA DATA DATA DATA DATA DATA DATA DATA DATA DATA DATA DATA DATA DATA DATA R/W A A A A A Don’t care A SDI A SCK Don’t care High Hi-Z Z SDO WRITE Communication (SPI mode 0,0) FIGURE 6-5: Write to a Single Register with 24-Bit Format (WIDTH_CRC = 0, SPI Mode 0,0).  2012-2020 Microchip Technology Inc. DS20005116D-page 47 MCP3910 6.5 by transmitting/receiving the address defined in the control byte. After this first transmission/reception, the SPI Internal Register Address Pointer automatically increments to the next available address in the register set for each transmission/reception. When it reaches the last address of the set, the communication sequence is finished. The Address Pointer loops automatically back to the first address of the defined set and restarts a new sequence with auto-increment (see Table 6-6). The undefined or unused addresses are automatically jumped by the Address Pointer (they are not considered to be part of the register map by the Address Pointer). This Internal Address Pointer automatic selection allows the following functionality: Continuous Communications, Looping on Register Sets The MCP3910 digital interface can process communications in Continuous mode, without having to enter an SPI command between each read or write to a register. This feature allows the user to reduce communication overhead to the strict minimum, which diminishes EMI emissions and reduces switching noise in the system. The registers can be grouped into multiple sets for continuous communications. The grouping of the registers in the different sets is defined by the READ[1:0] and WRITE bits that control the SPI Internal Communication Address Pointer. For a graphical representation of the register map sets in function of the READ[1:0] and WRITE bits, please see Table 9-2. • Read one ADC channel data or all ADC channels continuously • Continuously read the entire register map • Continuously read or write each separate register • Continuously read or write all Configuration registers In the case of a continuous communication, there is only one control byte on SDI to start the communication after a CS pin falling edge. The part stays within the same communication loop until the CS pin returns logic high. The SPI Internal Register Address Pointer starts CS ADDRESS SET SCK 8x SDI CONTROL BYTE 24x 24x ... 24x 24x 24x ... 24x ADDR ADDR + 1 Don’t care Don’t care ... Starts read sequence at address ADDR High Z Hi-Z SDO Complete READ sequence ADDR + n Roll-over ADDR ADDR + 1 ... ADDR + n ADDR ADDR + 1 Complete READ sequence ... ADDR + n Complete READ sequence Continuous READ communication (24-bit format) CS ADDRESS SET SCK 8x 24x 24x ... 24x 24x 24x ... 24x ADDR ADDR + 1 SDI Don’t care CONTROL BYTE ADDR Starts write sequence at address ADDR SDO ADDR + 1 ... ADDR + n ADDR ADDR + 1 Complete WRITE sequence ... Complete WRITE sequence ADDR + n ... Complete WRITE sequence ADDR + n Roll-over High Z Hi-Z Continuous WRITE communication (24-bit format) FIGURE 6-6: DS20005116D-page 48 Continuous Communication Sequences.  2012-2020 Microchip Technology Inc. MCP3910 6.5.1 CONTINUOUS READ TABLE 6-1: READ[1:0] For continuous reading of ADC data in SPI Mode 0,0 (see Figure 6-7), once the data have been completely read after a data ready, the SDO pin will take the MSB value of the previous data at the end of the reading (falling edge of the last SCK clock). If SCK stays Idle at logic low (by definition of Mode 0,0), the SDO pin will be updated at the falling edge of the next data ready pulse (synchronously with the DR pin falling edge with an output timing of tDODR) with the new MSB of the data corresponding to the data ready pulse. This mechanism allows the MCP3910 to continuously read ADC data outputs seamlessly, even in SPI Mode (0,0). Note: The STATUSCOM register contains the loop settings for the Internal Register Address Pointer (READ[1:0] bits and WRITE bit). For the Continuous Read modes, the address selection can take the four following values: ADDRESS SELECTION IN CONTINUOUS READ Register Address Set Grouping for Continuous Read Communications 00 Static (no incrementation) 01 Groups 10 Types (default) 11 Full Register Map In SPI Mode (1,1), the SDO pin stays in the last state (LSB of previous data) after a complete reading, which also allows seamless Continuous Read mode (see Figure 6-8). No SDI data coming after the control byte are considered during a continuous read communication. The following figures represent a typical, continuous read communication with the default settings (DR_LINK = 1, READ[1:0] = 10, WIDTH_DATA[1:0] = 01) for SPI Mode 0,0 (Figure 6-7) and SPI Mode 1,1 (Figure 6-8). CS SCK 8x SDI Don’t care 24x 24x 24x 24x DATA_CH0 DATA_CH1 Don’t care 0x01 Starts read sequence at address 00000 Hi-Z High Z SDO DATA_CH0 DATA_CH1 Complete READ sequence on ADC outputs channels 0 to 1 Stays at DATA_CH1 Complete READ sequence on new ADC outputs channels 0 to 1 DR FIGURE 6-7: Typical Continuous Read Communication (WIDTH_DATA[1:0] = 01, SPI Mode 0,0). CS SCK SDI 8x Don’t care 24x 24x 24x 24x DATA_CH0 DATA_CH1 Don’t care 0x01 Starts read sequence at address 00000 SDO High Hi-ZZ DATA_CH0 DATA_CH1 DATA_CH0 DATA_CH0 Old data New data DR FIGURE 6-8: Typical Continuous Read Communication (WIDTH_DATA[1:0] = 01, SPI Mode 1,1).  2012-2020 Microchip Technology Inc. DS20005116D-page 49 MCP3910 6.5.2 CONTINUOUS WRITE For the Continuous Write modes, the address selection can take the two following values: TABLE 6-2: WRITE ADDRESS SELECTION IN CONTINUOUS WRITE Register Address Set Grouping for Continuous Write Communications 0 Static (no incrementation) 1 Types (Default) SDO is always in a high-impedance state during a continuous write communication. Writing to a non-writable address (such as addresses: 0x00 to 0x07, or any of the unused register’s addresses) has no effect and does not increment the Address Pointer. In this case, the user needs to stop the communication and restart a communication with a control byte pointing to a writable address (0x08 to 0x1F). Note: 6.6 When the LOCK[7:0] bits are different than 0xA5, all the addresses, except 0x1F, become non-writable (see Section 6.10, Locking/Unlocking Register Map Write Access). Situations that Reset and Restart Active ADCs Immediately after the following actions, the active ADCs (the ones not in Soft Reset or Shutdown modes) are reset and automatically restarted in order to provide proper operation: 1. 2. 3. 4. 5. 6. Change in PHASE register. Overwrite of the same PHASE register value. Change in the OSR[2:0] settings. Change in the PRE[1:0] settings. Change in the CLKEXT setting. Change in the VREFEXT setting. After these temporary Resets, the ADCs go back to normal operation with no need for an additional command. Each ADC Data Output register is cleared during this process. The PHASE register can be used to serially soft reset the ADCs, without using the RESET[1:0] bits in the Configuration register, if the same value is written in the PHASE register. DS20005116D-page 50 6.7 Data Ready Pin (DR) To communicate when channel data are ready for transmission, the data ready signal is available on the Data Ready pin (DR) at the end of a channel conversion. The Data Ready pin outputs an active-low pulse with a pulse width equal to half a DMCLK clock period. After a data ready pulse falling edge has occurred, the ADC output data are updated within the tDODR timing and can then be read through SPI communication. The first data ready pulse after a Hard or a Soft Reset is located after the settling time of the SINC filter (see Table 5-4) plus the phase delay of the corresponding channel (see Section 5.9 “Phase Delay Block”). Each subsequent pulse is then periodic, and the period is equal to a DRCLK clock period (see Equation 4-3 and Figure 1-3). The data ready pulse is always synchronous with the internal DRCLK clock. The DR pin can be used as an interrupt pin when connected to an MCU or DSP, which will synchronize the readings of the ADC data outputs. When not active-low, this pin can either be in high-impedance (when DR_HIZ = 0) or in a defined logic high state (when DR_HIZ = 1). This is controlled through the STATUSCOM register. This allows multiple devices to share the same Data Ready pin (with a pull-up resistor connected between DR and DVDD). If only the MCP3910 device is connected on the interrupt bus, the DR pin does not require a pull-up resistor, and therefore, it is recommended to use the DR_HIZ = 1 configuration for such applications. The CS pin has no effect over the DR pin, which means even if the CS pin is logic high, the data ready pulses coming from the active ADC channels will still be provided; the DR pin behavior is independent from the SPI interface. While the RESET pin is logic low, the DR pin is not active. The DR pin is latched in the logic low state when the interrupt flag on the CRCREG is present to signal that the desired register configuration has been corrupted (see Section 6.11 “Detecting Configuration Change through CRC-16 Checksum on Register Map and its Associated Interrupt Flag”).  2012-2020 Microchip Technology Inc. MCP3910 6.8 ADC Channels Latching and Synchronization The ADC channels’ Data Output registers (addresses: 0x00 to 0x01) have a double-buffer output structure. The two sets of latches in series are triggered by the data ready signal and an internal signal indicating the beginning of a read communication sequence (read start). The first set of latches holds each ADC Channel Data Output register when the data are ready and latches all active outputs together when DR_LINK = 1. This behavior is synchronous with the MCLK clock. The second set of latches ensures that when reading starts on an ADC output, the corresponding data are latched, so that no data corruption can occur within a read. This behavior is synchronous with the SCK clock. If an ADC read has started, in order to read the following ADC output, the current reading needs to be fully completed (all bits must be read on the SDO pin from the ADC Output Data registers). Since the double-output buffer structure is triggered with two events that depend on two asynchronous clocks (data ready with MCLK and read start with SCK), it is recommended to implement one of the three following methods on the MCU, or the processor, in order to synchronize the reading of the channels: 1. 2. 3. The first method is the preferred one, as it can be used without adding additional MCU code space, but requires connecting the DR pin to an I/O pin of the MCU. The last two methods require more MCU code space and execution time, but they allow synchronizing the reading of the channels without connecting the DR pin, which saves one I/O pin on the MCU. 6.9 Securing Read Communications Through CRC-16 Checksum Since power/energy metering systems can generate or receive large EMI/EMC interferences and large transient spikes, it is helpful to secure SPI communications as much as possible to maintain data integrity and desired configurations during the lifetime of the application. The communication data on the SDO pin can be secured through the insertion of a Cyclic Redundancy Check (CRC) checksum at the end of each continuous reading sequence. The CRC checksum on the communications can be enabled or disabled through the EN_CRCCOM bit in the STATUSCOM register. The CRC message ensures the integrity of the read sequence bits transmitted on the SDO pin and the CRC checksum is inserted in between each read sequence (see Figure 6-9). Use the Data Ready Pin Pulses as an Interrupt: Once a falling edge occurs on the DR pin, the data are available for reading on the ADC Output registers after the tDODR timing. If this timing is not respected, data corruption can occur. Use a Timer Clocked with MCLK as a Synchronization Event: Since the data ready is synchronous with MCLK, the user can calculate the position of the data ready depending on the PHASE, the OSR[2:0] and the PRE[1:0] bits settings for each channel. Again, the tDODR timing needs to be added to this calculation to avoid data corruption. Poll the DRSTATUS[1:0] Bits in the STATUSCOM Register: This method consists of continuously reading the STATUSCOM register and waiting for the DRSTATUS bits to be equal to ‘0’. When this event happens, the user can start a new communication to read the desired ADC data. In this case, no additional timing is required.  2012-2020 Microchip Technology Inc. DS20005116D-page 51 MCP3910 CS ADDRESS SET SCK 8x 16x/24x/32x Depending on data format 16x/24x/32x Depending on data format 16x/24x/32x Depending on data format ... 16x/24x/32x Depending on data format 16x/24x/32x Depending on data format 16x/24x/32x Depending on data format ... ADDR ADDR + 1 SDI CONTROL BYTE Don’t care Don’t care ... Starts read sequence at address ADDR SDO High Hi-Z Z Complete READ sequence ADDR + n Roll-over ADDR ADDR + 1 ... ADDR + n ADDR Complete READ sequence ADDR + 1 ... ADDR + n Complete READ sequence Continuous READ communication without CRC checksum (EN_CRCCOM=0) CS ADDRESS SET SCK 8x SDI CONTROL BYTE 16x/24x/32x Depending on data format 16x/24x/32x Depending on data format 16x/24x/32x Depending on data format ... 16x or 32x Depending on CRC format 16x/24x/32x Depending on data format 16x/24x/32x Depending on data format ... 16x/24x/32x Depending on data format 16x or 32x Depending on CRC format ADDR ADDR + 1 Don’t care Don’t care ... Starts read sequence at address ADDR SDO High Z Hi-Z Complete READ sequence ADDR + n ADDR ADDR + 1 ... ADDR + n CRC Checksum ADDR ADDR + 1 ... ADDR + n CRC Checksum CRC Checksum (not part of register map) Roll-over Complete READ sequence = Message for CRC Calculation Checksum New Message New Checksum Continuous READ communication with CRC checksum (EN_CRCCOM=1) FIGURE 6-9: Continuous Read Sequences with and without CRC Checksum Enabled. The CRC checksum in the MCP3910 device uses the 16-bit CRC-16 ANSI polynomial as defined in the IEEE 802.3 standard: x16 + x15 + x2 + 1. This polynomial can also be noted as 0x8005. CRC-16 detects all single and double-bit errors, all errors with an odd number of bits, all burst errors of a length of 16 or less and most errors for longer bursts. This allows an excellent coverage of the SPI communication errors that can happen in the system and heavily reduces the risk of a miscommunication, even in noisy environments. The CRC-16 format displayed on the SDO pin depends on the WIDTH_DATA[1] bit in the STATUSCOM register (see Figure 6-10). It can be either 16-bit or 32-bit format to be compatible with both 16-bit and 32-bit MCUs. The CRCCOM[15:0] bits calculated by the MCP3910 device are not depending on the format (the device always calculates only a 16-bit CRC checksum). It is recommended to keep WIDTH_DATA[1] = WIDTH_CRC when the CRC checksum is enabled. If a 32-bit MCU is used in the application, it is recommended to use 32-bit formats (WIDTH_DATA[1] = WIDTH_CRC = 1) only. WIDTH_DATA = 0 16-bit format WIDTH_DATA = 1 32-bit format FIGURE 6-10: DS20005116D-page 52 15 The CRC calculation made by the MCP3910 device is fully compatible with CRC hardware contained in the Direct Memory Access (DMA) of the PIC24 and PIC32 MCU product lines. The CRC message that should be considered in the PIC® MCU DMA is the concatenation of the read sequence and its associated checksum. When the DMA CRC hardware computes this extended message, the resulting checksum should be 0x0000. Any other result indicates that a miscommunication has happened and that the current communication sequence should be stopped and restarted. Note: The CRC will be generated only at the end of the selected address set, before the rollover of the Address Pointer occurs (see Figure 6-9). 0 CRCCOM CRCCOM 31 CRCCOM CRCCOM 0 0x00 0x00 CRC Checksum Format.  2012-2020 Microchip Technology Inc. MCP3910 6.10 Locking/Unlocking Register Map Write Access The MCP3910 digital interface includes an advanced security feature that permits locking or unlocking the register map write access. This feature prevents the miscommunication that can corrupt the desired configuration of the device, especially an SPI read becoming an SPI write because of the noisy environment. The last register address of the register map (0x1F: LOCK/CRC) contains the LOCK[7:0] bits. If these bits are equal to the password value (which is equal to the default value of 0xA5), the register map write access is not locked. Any write can take place and the communications are not protected. When the LOCK[7:0] bits are different than 0xA5, the register map write access is locked. The register map, and therefore, the full device configuration, is writeprotected. Any write to an address other than 0x1F will yield no result. All the register addresses, except for 0x1F, become read-only. In this case, if the user wants to change the configuration, the LOCK[7:0] bits have to be reprogrammed back to 0xA5 before sending the desired WRITE command. The LOCK[7:0] bits are located in the last register so that the user can program the whole register map, starting from 0x09 to 0x1E within one continuous write sequence, and then lock the configuration at the end of the sequence with writing all zeros, for example, in the 0x1F address. 6.11 Detecting Configuration Change through CRC-16 Checksum on Register Map and its Associated Interrupt Flag In order to prevent internal corruption of the register and to provide additional security on the register map configuration, the MCP3910 device includes an automatic and continuous CRC checksum calculation on the full register map Configuration bits. This calculation is not the same as the communication CRC checksum described in Section 6.9 “Securing Read Communications Through CRC-16 Checksum”. This calculation takes the full register map as the CRC message and outputs a checksum on the CRCREG[15:0] bits located in the LOCK/CRC register (address: 0x1F). Since this feature is intended to protect the configuration of the device, this calculation is run continuously only when the register map is locked (LOCK[7:0] is different from 0xA5, see Section 6.10 “Locking/Unlocking Register Map Write Access”). If the register map is unlocked, the CRCREG[15:0] bits are cleared and no CRC is calculated. The calculation is fully completed in 12 DMCLK periods and refreshed every 12 DMCLK periods continuously. The CRCREG[15:0] bits are reset when a POR or a Hard Reset occurs. All the bits contained in the defined  2012-2020 Microchip Technology Inc. registers, from addresses 0x09 to 0x1F, are processed by the CRC engine to give the CRCREG[15:0] bits. The DRSTATUS[5:0] bits are set to ‘1’ (default) and the CRCREG[15:0] bits are set to ‘0’ (default) for this calculation engine, as they could vary during the calculation. An interrupt flag can be enabled through the EN_INTCRC bit in the STATUSCOM register and provided on the DR pin when the configuration has changed without a WRITE command being processed. This interrupt is a logic low state. This interrupt is cleared when the register map is unlocked (since CRC calculation is not processed anymore). At power-up, the interrupt is not present and the register map is unlocked. As soon as the user finishes writing its configuration, the user needs to lock the register map (writing 0x00, for example, in the LOCK bits) to be able to use the interrupt flag. The CRCREG[15:0] bits will be calculated for the first time in 12 DMCLK periods. This first value will then be the reference checksum value and will be latched internally, until a Hard Reset, a POR or an unlocking of the register map happens. The CRCREG[15:0] bits will then be calculated continuously and checked against the reference checksum. If the CRCREG[15:0] bits are different than the reference, the interrupt sends a flag by setting the DR pin to a logic low state until it is cleared. 6.12 Interface Mode Selection (SPI or Two-Wire) The MCP3910 includes two different digital interfaces: a standard four-wire half-duplex SPI interface (see Section 6.0 “SPI Serial Interface Description”) and a two-wire interface dedicated for digitally isolated applications (see Section 7.0 “Two-Wire Serial Interface Description”). The selection between these two interfaces is possible only when the CLKEXT bit is logic high (CLKEXT = 1). This is the case by default at POR. When the CLKEXT = 1 condition is true, the OSC2/MODE pin becomes the selection input pin for the Interface mode. When OSC2/MODE is logic low during the CLKEXT = 1 condition, the SPI Interface is selected. When OSC2/MODE pin is logic high, the Two-Wire Interface mode is selected (see Figure 1-5 for the Two-Wire Interface mode selection timing diagram). If the OSC2/MODE pin is left floating while CLKEXT = 1, an internal pull-down (35 µA typical current) automatically selects the SPI mode as the default interface. The MODE selection is not combinatorial, it is latched at each POR, Hard Reset and Watchdog Time Reset. In other words, to change from one interface mode to another, the user needs to create one of these three Resets and change the OSC2/MODE logic input state before exiting the applied Reset. DS20005116D-page 53 MCP3910 NOTES: DS20005116D-page 54  2012-2020 Microchip Technology Inc. MCP3910 7.0 TWO-WIRE SERIAL INTERFACE DESCRIPTION 7.1 OVERVIEW one Master Clock for multiple phases, which ensures proper synchronization and constant phase angle between phases, which is important for an energy metering application. The Two-Wire Interface mode is designed for applications that require galvanic isolation. It allows a minimum number of digital isolator channels, specifically one bidirectional or two unidirectional channels, to be connected to the MCP3910 when interfacing through an isolation barrier. This functionality reduces the total system cost in an isolated applications system, such as a polyphase shunt-based energy meter. It is recommended to use the MCP3910 with the Two-Wire mode for digitally isolated applications and with the SPI mode for other applications where galvanic isolation is not required. The principle of this Two-Wire Interface mode is simple: it has a Serial Clock input pin (SCK/MCLK) and a Serial Data Output pin (SDO), and it automatically sends output data in packets (frames) at a DRCLK data rate (every time new data are available on the ADC outputs). It has no serial input pin to diminish the number of isolated channels. At the same time, the Serial Clock pin, SCK, also becomes the Master Clock (MCLK) input pin of the device and the part becomes fully synchronous with SCK = MCLK. The system then becomes fully synchronous and can be driven by only ANALOG The SDO pin becomes the only output of the device and is fully synchronous with the Serial/Master Clock. The SDO pin is never in high-impedance in this mode, and is by default, at logic low when not transmitting data. The SDO pin Idles logic low in this mode because most of the digital isolator devices consume less current in a logic low state than in a logic high state. This effectively reduces the total power consumption of a system with digital isolation devices. When the part has entered Two-Wire mode, the logic pins, RESET, SDI, CS, OSC1 and DR, become logic input pins for the configuration of the device (respectively, OSR0/OSR1/BOOST/GAIN0/GAIN1). These pins need to have well-defined logic states for low-power applications. These pins define the only settings that can be modified in Two-Wire mode. The MDAT0/1 pins are always disabled and kept in a high-impedance state during the Two-Wire Interface mode. These pins can be grounded for applications using exclusively the Two-Wire Interface mode so that the EMI/EMC susceptibility of the part is improved. DIGITAL SDO SINC3 CH0+ CH0- + PGA Isolator MOD '6 Modulator 2-wire Interface CH1+ + CH1- PGA GAIN=1x MOD '6 Modulator To SPI Ports Of an MCU SCK/MCLK SINC 3 MDAT0 MDAT1 GAIN0 GAIN1 BOOST OSR0 OSR1 Optional connections to 2 additional isolators Isolator Logic inputs connected to DVDD or DGND Main MCU/ CPU Board MCP3910 Isolation Barrier FIGURE 7-1: MCP3910 Two-Wire Interface Typical Application Schematic.  2012-2020 Microchip Technology Inc. DS20005116D-page 55 MCP3910 7.2 Two-Wire Mode Configuration Settings When the user wants to exclusively use the Two-Wire Interface mode in digitally isolated applications, the OSC2 pin should always be in a logic high state, starting from the power-up of the part. Otherwise, the user can change the interface mode by toggling the OSC2/MODE pin within a POR, a Hard Reset or a Watchdog Timer Reset; the MODE is latched when exiting one of these three types of Reset. When the part has entered Two-Wire mode, the entire part configuration keeps its default settings (see Section 9.0 “MCP3910 Internal Registers” for the default settings of all internal registers), except for the configuration of the Gain in Channel 0, the OSR and the BOOST settings. In Two-Wire Interface mode, the input pins, OSR0/OSR1/BOOST/GAIN0/GAIN1, are latched on the OSC2/MODE rising edge and should typically be directly connected to DVDD or DGND, depending on the desired configuration. These pins define the only configurable settings in Two-Wire mode. If more settings are required by the application, it is recommended to use the SPI mode. The following tables describe the configuration options for these five pins. 7.2.1 OSR1/OSR0 OSR Setting Logic pins. These inputs are Schmitt triggered. TABLE 7-1: OSR SETTINGS OSR1 OSR0 OSR 0 0 64 0 1 128 1 0 256 1 1 512 7.2.2 BOOST Current Boost Setting Logic pin. This input is Schmitt triggered. TABLE 7-2: CURRENT BOOST SETTINGS BOOST Pin Boost 0 0.5x 1 1x DS20005116D-page 56 7.2.3 GAIN1/GAIN0 Channel 0 Gain Setting Logic pins. These inputs are Schmitt triggered. TABLE 7-3: 7.3 CHANNEL 0 GAIN SETTINGS GAIN1 GAIN0 CH0 PGA GAIN 0 0 1 0 1 8 1 0 16 1 1 32 Two-Wire Communication Protocol In Two-Wire mode, the SCK/MCLK pin needs to be clocked continuously at all times for proper operation. Any change in the clock frequency will lead to degraded THD/SFDR specifications. The part obeys the same timing specifications in both SPI and Two-Wire Interface mode for the SCK/SDO pins. The MCLK maximum input frequency is 10 MHz in Two-Wire mode, since the converter still respects Table 5-2 for maximum AMCLK frequency (provided the part has entered Two-Wire mode at power-up). Since the MCLK is divided internally, the part accepts a wide range of duty cycles for the SCK input, provided the serial interface timings are respected. In Two-Wire Interface mode, communication uses framed data sets on the SDO to output data at a fixed data rate, synchronously with SCK, and using only one output pin. The frame is different depending on the device and the Oversampling Ratio (OSR) selected. When in OSR = 64 mode, the MCP3910 frame contains the sync bytes (16-bit), two channels of 16-bit ADC data and a 16-bit CRC. For OSR = 128 and higher, each frame is a group of ten bytes (80 bits) clocked by the Serial Clock, SCK. Each frame is composed of a sync word (two bytes), 24-bit data output words (three bytes) for both channels and a 16-bit CRC. The sync word comes first, followed by Channel 0 ADC output (DATA_CH0[23:0]), Channel 1 ADC output (DATA_CH1[23:0]) and the 16-bit CRC (see Figure 7-1 and Figure 7-2). As a verification feature, the sync word contains all settings coming from the five logic input pins available (OSR0/1, GAIN0/1, BOOST) in order to provide the user with the information about this configuration. It also provides information about the count of the frame through bits, CNT0/1, which is useful when the SDO is multiplexed at the output of the digital isolators (see next paragraph). The sync word also contains an additional sync byte (fixed at the 0xA5 value) for additional security in synchronization and communication.  2012-2020 Microchip Technology Inc. MCP3910 DATA_CH0 DATA_CH1 CRCCOM CHANNEL 0 ADC DATA (3 Bytes) CHANNEL 1 ADC DATA (3 Bytes) CRCCOM on Entire Frame (2 Bytes) 0 1 1 0 0 1 0 CNT0 1 G0 CNT1 G1 BOOST SDO OSR0 0 OSR1 SCK/ MCLK SYNC WORD (2 Bytes) SDO OUTPUT FRAME (10 Bytes, 80x clocks per Frame) FRAME CLOCKING FOR OSR>64 DATA_CH0 1 0 0 1 0 0 1 1 CNT0 CNT1 BOOST G0 G1 0 OSR0 SDO OSR1 SCK/ MCLK SYNC WORD (2 Bytes) CHANNEL 0 ADC DATA (2 Bytes) DATA_CH1 CRCCOM CHANNEL 1 ADC DATA (2 Bytes) CRCCOM on Entire Frame (2 Bytes) SDO OUTPUT FRAME (8 Bytes, 64x clocks per Frame) FRAME CLOCKING FOR OSR=64 FIGURE 7-2: Frame Word. TABLE 7-4: actually being read. After the four frames have been transmitted, the SDO pin Idles logic low to reduce digital isolator power consumption until the next data are available. If OSR = 64, the SDO never Idles because the data are directly available after the four frames are transmitted. Figure 7-3 displays the timing diagram for Two-Wire Interface mode, showing all OSR possibilities. Note that the first set of frames is sent only when the first data are ready, which means that the settling time of the SINC filter will be elapsed before sending the first set of frames, as represented in Figure 7-3. FRAME COUNTER SETTINGS CNT1 CNT0 FRAME NUMBER 0 0 FRAME0 0 1 FRAME1 1 0 FRAME2 1 1 FRAME3 These four frames can be used to multiplex SDO at the output of the digital isolators. In this case, up to four channels (typically three phases and one neutral for energy metering applications) can be multiplexed. The output data of each individual MCP3910 device can be attributed to a different frame (FRAME0, 1, 2 or 3) and retrieved on a single SDO line after the digital isolators, provided that the isolators have a chip enable or a multiplexing feature. The frame counter can then be used to retrieve the information about which MCP3910 part is OSC2/ MODE 2-Wire Mode 256x 256x clocks clocks 256x 256x clocks clocks 256x clocks 256x clocks 256x 256x clocks clocks 256x clocks 0 DATA=D5 DATA=D6 0 0 DATA=D7 DATA=D8 0 DATA=D9 DATA=D10 DATA=D11 DATA=D12 DATA=D13 DATA=D14 DATA=D15 DATA=D16 DATA=D17 DATA=D18 DATA=D19 DATA=D20 DATA=D21 DATA=D22 DATA=D23 DATA=D24 DATA=D25 DATA=D26 DATA=D27 DATA=D28 DATA=D29 0 0 FRAME0 FRAME1 FRAME2 FRAME3 0 DATA=D4 FRAME0 FRAME1 FRAME2 FRAME3 0 DATA=D3 FRAME0 FRAME1 FRAME2 FRAME3 DATA=D2 FRAME0 FRAME1 FRAME2 FRAME3 0 256x clocks FRAME0 FRAME1 FRAME2 FRAME3 0 -OSR/2 256x 256x clocks clocks FRAME0 FRAME1 FRAME2 FRAME3 0 256x clocks FRAME0 FRAME1 FRAME2 FRAME3 0 0 256x clocks FRAME0 FRAME1 FRAME2 FRAME3 Hi-Z 0 256x 256x clocks clocks FRAME0 FRAME1 FRAME2 FRAME3 SDO (OSR=512) 0 256x clocks FRAME0 FRAME1 FRAME2 FRAME3 Hi-Z 256x 256x clocks clocks FRAME0 FRAME1 FRAME2 FRAME3 SDO (OSR=256) 256x clocks FRAME0 FRAME1 FRAME2 FRAME3 Hi-Z 256x clocks FRAME0 FRAME1 FRAME2 FRAME3 DATA=D1 SDO (OSR=128) 256x 256x clocks clocks FRAME0 FRAME1 FRAME2 FRAME3 0 256x clocks FRAME0 FRAME1 FRAME2 FRAME3 0 256x 256x clocks clocks FRAME0 FRAME1 FRAME2 FRAME3 0 256x clocks FRAME0 FRAME1 FRAME2 FRAME3 0 256x clocks FRAME0 FRAME1 FRAME2 FRAME3 0 256x 256x clocks clocks FRAME0 FRAME1 FRAME2 FRAME3 Hi-Z 256x clocks FRAME0 FRAME1 FRAME2 FRAME3 FRAME0 FRAME1 FRAME2 FRAME3 FRAME0 FRAME1 FRAME2 FRAME3 FRAME0 FRAME1 FRAME2 FRAME3 FRAME0 FRAME1 FRAME2 FRAME3 FRAME0 FRAME1 FRAME2 FRAME3 FRAME0 FRAME1 FRAME2 FRAME3 FRAME0 FRAME1 FRAME2 FRAME3 FRAME0 FRAME1 FRAME2 FRAME3 FRAME0 FRAME1 FRAME2 FRAME3 FRAME0 FRAME1 FRAME2 FRAME3 FRAME0 FRAME1 FRAME2 FRAME3 FRAME0 FRAME1 FRAME2 FRAME3 FRAME0 FRAME1 FRAME2 FRAME3 FRAME0 FRAME1 FRAME2 FRAME3 FRAME0 FRAME1 FRAME2 FRAME3 FRAME0 FRAME1 FRAME2 FRAME3 FRAME0 FRAME1 FRAME2 FRAME3 FRAME0 FRAME1 FRAME2 FRAME3 FRAME0 FRAME1 FRAME2 FRAME3 FRAME0 FRAME1 FRAME2 FRAME3 FRAME0 FRAME1 FRAME2 FRAME3 FRAME0 FRAME1 FRAME2 FRAME3 FRAME0 FRAME1 FRAME2 FRAME3 FRAME0 FRAME1 FRAME2 FRAME3 FRAME0 FRAME1 FRAME2 FRAME3 FRAME0 FRAME1 FRAME2 FRAME3 FRAME0 FRAME1 FRAME2 FRAME3 FRAME0 FRAME1 FRAME2 FRAME3 (2*OSR)x 256x clocks clocks SCK/MCLK SDO (OSR=64) It should also be noted that since the PHASE register is back to its default value in the Two-Wire mode, there is no delay between the two channels in this mode and the conversions start after a delay of OSR/2 DMCLK periods (which corresponds to 2 x OSR MCLK periods). 0 Internal data ready (Data is unsettled). No frame is transmitted FIGURE 7-3: Data Ready. New data is available MCP3910 Two-Wire Communication Protocol.  2012-2020 Microchip Technology Inc. DS20005116D-page 57 MCP3910 7.4 Watchdog Timer Reset, Resetting the Part in Two-Wire Mode When the part has entered the Two-Wire mode, the Hard Reset mode functionality is not available because the RESET pin becomes the logic input for OSR0. If the user wants to execute a full Reset of the part without doing a POR, the Two-Wire mode incorporates an internal Watchdog Timer that automatically performs a full Reset of the part if the timer has elapsed. The Watchdog Timer starts synchronously with each rising edge of SCK/MCLK. If the SCK logic high state is maintained for a time that is larger than tWATCH, the Watchdog Timer circuit forces the full Reset of the chip, which then returns to its default configuration with all ADCs being reset. If the SCK logic high state is maintained for a time shorter than tWATCH and then SCK/MCLK toggles to logic low, the internal timer is cleared, waiting for another rising edge to restart. DS20005116D-page 58 The Watchdog Timer functionality induces a restriction in the usable range of frequencies on SCK/MCLK. In order to avoid intermittent Resets in all cases, the minimum SCK/MCLK frequency in Two-Wire Interface mode is equal to the inverse of the minimum tWATCH time (1/(2 x 3.6 µs) = 138.9 kHz if the duty cycle of the SCK/MCLK is 50%). The Watchdog Timer starts only on the rising edge of SCK/MCLK, not on the falling edge. Maintaining SCK/MCLK at a logic low state for large periods of time does not create any Watchdog Timer Resets. A Watchdog Timer Reset is created only when the SCK/MCLK state is maintained logic high during a long enough period of time. This Watchdog Timer period permits exiting Two-Wire Interface mode, if desired, by toggling OSC2/MODE pin to logic low before creating Watchdog Timer Reset and by maintaining it logic until the Reset happens. the the the low  2012-2020 Microchip Technology Inc. MCP3910 8.0 BASIC APPLICATION CONFIGURATION 8.1 Typical Isolated Power Metering Applications The isolator used between the MCU and ADC needs to be fast enough to support the high-speed clock between the MCU and ADC, and the data coming from the ADC to MCU. Data from the ADC to MCU have the same speed as the clock supplied by the MCU. Since the ADC is isolated from the MCU, it can be placed at any potential area and so shunts can be used as current sensors in three-phase meter designs, even if they do not provide any galvanic isolation. One of the main applications for MCP3910 is energy/power measurements in systems where the ADC needs to be isolated from the rest of the design. Figure 8-1 can be used as a starting point for MCP3910 applications. This is typically the case in a polyphase shunt-based power/energy metering or monitoring application. In this case, each phase needs to be isolated from the rest of the design, and since the sensor is not providing this isolation, the isolation needs to be provided at the output of the analog front end. To power the isolated ADC, an isolated DC/DC Converter (that can be embedded with the isolated data communication channels, as in Figure 8-1) or other structures that provide isolated power supplies (e.g., flyback converter) can be used. For single-phase designs where isolation between the ADC and MCU is not required, the SPI connection is also available. The MCP3910 device is built to work seamlessly with a large variety of 2-channel unidirectional digital isolators (optocouplers, capacitive or inductive integrated digital isolators with or without embedded power supplies). A_3.3D U18 L2 2 MCP1754-3.3V GND ND A_3.3A VOUT VIN 0.1uF 5 U7 VBT1-S5-S5 C63 4.7uF 4 1 C57 3 A_GNDD 5V +Vout +Vin DC This SPI interface could also be used with isolators, but this would require four isolators instead of two (for the Two-Wire mode), and therefore, this configuration is not preferred. DC -Vout -Vin 2 1 C22 C60 4.7uF 0.1uF 0603 8 7 6 5 3910A_SDO 3910A_CLKIN A_GNDD GND NT3 A_3.3D A_3.3D A_GNDD 3.3D U21 VDD2V VDD1 VIA VOA VOB VIB GND2G GND1 FOD8012 1 2 3 4 3.3D 3910A_SDO_MCU/RC3 3910_CLKIN_MCU_A C68 0.1uF 0603 GND GND A_3.3D A_GNDD 1k A_GNDA R80 HIGH J24 A_GNDA A_GNDA R3 CP1 Via_1.6x1 LINE_SHUNT1 LINE_SHUNT2 CP2 Via_1.6x1 C1 C43 0.1uF DNP R4 R100 1k FB2 0.1uF R76 10 0.1uF 1k FB3 4 A_GNDA C5 DNP A_GNDA A_GNDA R8 R9 330k 330k 6 7 0.1uF FB1 2 3 R5 R6 1 5 8 9 C46 0.1uF 10 U3 LOW RESET / OSR0 SDI / OSR1 DVDD SDO HIGH BOOST 3 2 1 AVDD SCK / MCLK LOW CH0+ CS / BOOST HIGH GAIN0 3 2 1 CH0- OSC2 / MODE LOW CH1- OSC1/CLKI HIGH GAIN1 3 2 1 CH1+ DR / GAIN1 LOW AGND MDAT0 RFIN/OUT+ MDAT1 RFIN- DGND J25 20 19 R86 10 18 R87 10 17 16 R79 1k 15 14 3910A_SDO J26 3910A_CLKIN J27 A_3.3D J28 13 12 11 MCP3910A1T/ISS C9 0.1uF R25 1k A_GNDA A_GNDA FIGURE 8-1: Phase. C52 LOW OSR1 3 2 1 HIGH A_GNDD 10 A_GNDA HIGH A_GNDA A_3.3D A_3.3A OSR0 3 2 1 A_GNDA A_GNDA MCP3910 A_GNDD PHASE A MCP3910 Three-Phase Shunt Energy Meter – Typical Application Schematic for Each  2012-2020 Microchip Technology Inc. DS20005116D-page 59 MCP3910 8.2 Power Supply Design and Bypassing The MCP3910 device was designed to measure positive and negative voltages that might be generated by a current-sensing device. This current-sensing device, with a Common-mode voltage close to 0V, is referred to as AGND, which is a shunt or Current Transformer (CT) with burden resistors attached to ground. The high performance and good flexibility that characterize this ADC enable it to be used in other applications, as long as the absolute voltage on each pin, referred to AGND, stays in the -1V to +1V interval. In any system, the analog ICs (such as references or operational amplifiers) are always connected to the analog ground plane. The MCP3910 should also be considered as a sensitive analog component and connected to the analog ground plane. The ADC features two pairs of pins: AGND and AVDD, and DGND and DVDD. For best performance, it is recommended to keep the two pairs connected to two different networks (Figure 8-2). This way, the design will feature two ground traces and two power supplies (Figure 8-3). This means the analog circuitry (including MCP3910) and the digital circuitry (MCU) should have separate power supplies, and return paths to the external ground reference, as described in Figure 8-2. An example of a typical power supply circuit, with different lines for analog and digital power, is shown in Figure 8-3. A possible split example is shown in Figure 8-4, where the ground star connection can be done at the bottom of the device with the exposed pad. The split between analog and digital can be done under the device; AVDD and DVDD can be connected together with lines coming under the ground plane. Another possibility, sometimes easier to implement in terms of PCB layout, is to consider the MCP3910 as an analog component, and therefore, to connect both AVDD and DVDD together, and AGND and DGND together with a star connection. In this scheme, the decoupling capacitors may be larger due to the ripple on the digital power supply (caused by the digital filters and the SPI interface of the MCP3910) now causing glitches on the analog power supply. ID IA 0.1 μF 0.1 μF C VA AVDD DVDD VD MCP39XX MCU AGND DGND IA ID “Star” Point D- = A- = FIGURE 8-2: All Analog and Digital Return Paths Need to Stay Separate with Proper Bypass Capacitors. FIGURE 8-3: Power Supply with Separate Lines for Analog Section and Digital Section. Note the “Net Tie” Object NT2 that Represents the Start Ground Connection. DS20005116D-page 60  2012-2020 Microchip Technology Inc. MCP3910 8.3 SPI Interface Digital Crosstalk The MCP3910 incorporates a high-speed 20 MHz SPI digital interface. This interface can induce a crosstalk if it is running at its full speed without any precautions. The crosstalk is caused by the switching noise created by the digital SPI signals (also called ground bouncing). FIGURE 8-4: Separation of Analog and Digital Circuits on Layout. Figure 8-5 shows a more detailed example with a direct connection to a high-voltage line (e.g., a two-wire 120V or 220V system). A current-sensing shunt is used for current measurement on the high/line side that also supplies the ground for the system. This is necessary as the shunt is directly connected to the channel input pins of the MCP3910. To reduce sensitivity to external influences, such as EMI, these two wires should form a twisted pair, as noted in Figure 8-5. The power supply and MCU are separated on the right side of the PCB, surrounded by the digital ground plane. The MCP3910 is kept on the left side, surrounded by the analog ground plane. There are two separate power supplies going to the digital section of the system and the analog section, including the MCP3910. With this placement, there are two separate current supply paths and current return paths, IA and ID. Analog Ground Plane IA Digital Ground Plane ID This crosstalk would negatively impact the SNR in this case. The noise is attenuated if a proper separation between the analog and digital power supplies is put in place (see Section 8.2 “Power Supply Design and Bypassing”). In order to further remove the influence of the SPI communication on measurement accuracy, it is recommended to add series resistors on the SPI lines to reduce the current spikes caused by the digital switching noise (see Figure 8-1 where these resistors have been implemented). The resistors also help to keep the level of electromagnetic emissions low. The measurement graphs provided in this data sheet have been performed with 100 series resistors connected on each SPI I/O pin. Measurement accuracy disturbances have not been observed, even at the full speed of 20 MHz interfacing. The crosstalk performance is dependent on the package choice, due to the difference in the pin arrangement (dual in-line or quad), and is improved in the 20-Lead QFN package. 8.4 Sampling Speed and Bandwidth If ADC power consumption is not a concern in the design, the boost settings can be increased for best performance so that the OSR is always kept at the maximum settings to improve the SINAD performance (see Table 8-1). If the MCU cannot generate a clock fast enough, it is possible to tap the OSC1/OSC2 pins of the MCP3910 crystal oscillator directly to the crystal of the microcontroller. When the sampling frequency is enlarged, the phase resolution is improved, and with the OSR increased, the phase compensation range can be kept in the same range as the default settings. MCU MCP3910 IA TABLE 8-1: ID VD VA Power Supply Circuitry “Star” Point Twisted Pair LINE SHUNT NEUTRAL FIGURE 8-5: Connection Diagram. The ferrite bead between the digital and analog ground planes helps keep high-frequency noise from entering the device. This ferrite bead is recommended to be low resistance; most often it is a THT component. Ferrite beads are typically placed on the shunt inputs and into the power supply circuit for additional protection.  2012-2020 Microchip Technology Inc. MCLK (MHz) SAMPLING SPEED vs. MCLK AND OSR, ADC PRESCALE 1:1 BOOST[1:0] OSR Sampling Speed (ksps) 16 0b11 1024 3.91 14 0b11 1024 3.42 12 0b11 1024 2.93 10 0b10 1024 2.44 8 0b10 512 3.91 6 0b01 512 2.93 4 0b01 256 3.91 DS20005116D-page 61 MCP3910 8.5 Differential Inputs Anti-Aliasing Filter Due to the nature of the ADCs used in the MCP3910 (oversampling converters), each differential input of the ADC channels requires an anti-aliasing filter so that the oversampling frequency (DMCLK) is largely attenuated and does not generate any disturbances on the ADC accuracy. This anti-aliasing filter also needs to have a gain close to the one in the signal bandwidth of interest. Typically for 50/60 Hz measurement and default settings (DMCLK = 1 MHz), a simple RC filter with 1 k and 100 nF can be used. The anti-aliasing filter used for the measurement graphs is a first-order RC filter with 1 k and 15 nF. The typical schematic for connecting a current transformer to the ADC is shown in Figure 8-6. If wires are involved, twisting them is also recommended. The filter presented in Figure 8-7 is an anti-aliasing filter. The di/dt integrator can be created in firmware as a first-order low-pass filter with corner frequency much lower than the input signal. The MCP3910 is highly recommended in applications using di/dt as current sensors because of the extremely low noise floor at low frequencies. In such applications, a Low-Pass Filter (LPF) with a cutoff frequency much lower than the signal frequency (50-60 Hz for metering) is used to compensate for the 90-degree shift and for the 20 db/decade attenuation induced by the di/dt sensor. Because of this filter, the SNR will be decreased, since the signal will attenuate by a few orders of magnitude, while the low-frequency noise will not be attenuated. Usually, a high-order High-Pass Filter (HPF) is used to attenuate the low-frequency noise in order to prevent a dramatic degradation of the SNR, which can be very important in other parts. A high-order filter will also consume a significant portion of the computation power of the MCU. When using the MCP3910, such a high-order HPF is not required, since this part has a low noise floor at low frequencies. A first-order HPF is enough to achieve very good accuracy. 8.6 FIGURE 8-6: First-Order Anti-Aliasing Filter for CT-Based Designs. The di/dt current sensors, such as Rogowski coils, can be an alternative to current transformers. Since these sensing elements are highly sensitive to highfrequency electromagnetic fields, using a second-order anti-aliasing filter is recommended to increase the attenuation of potential perturbing RF signals. FIGURE 8-7: Second-Order Anti-Aliasing Filter for Rogowski Coil-Based Designs. DS20005116D-page 62 Energy Measurement Error Considerations The measurement error is a typical representation of the nonlinearity of a pair of ADCs (see Section 4.0 “Terminology and Formulas” for the definition of measurement error). The measurement error is dependent on the THD and on the noise floor of the ADCs. Improving the measurement error specification on the MCP3910 can be realized by increasing the OSR (to get a better SINAD and THD performance) and, to some extent, the boost settings (if the bandwidth of the measurements is too limited by the bandwidth of the amplifiers in the Sigma-Delta ADCs). In most of the energy metering AC applications, High-Pass Filters are used to cancel the offset on each ADC channel (current and voltage channels), and therefore, a single-point calibration is necessary to calibrate the system for active energy measurement. This calibration is a system gain calibration and the user can utilize the EN_GAINCAL bit and the GAINCAL_CHn registers to perform this digital calibration. After such calibration, typical measurement error curves, such as in Figure 2-7, can be generated by sweeping the current channel amplitude and measuring the energy at the outputs (the energy calculations here are being realized off-chip). The error is measured using a gain of 1x, as it is commonly used in most CT-based applications.  2012-2020 Microchip Technology Inc. MCP3910 At low signal amplitude values (typically 1000:1 dynamic range and higher), the crosstalk between channels, mainly caused by the PCB, becomes a significant part of the perturbation as the measurement error increases. The 1-point measurement error curves in Figure 2-5 have been performed with a full-scale sine wave on all the inputs that are not measured, which means that these channels induce a maximum amount of crosstalk on the measurement error curve. In order to avoid such behavior, a 2-point calibration can be put in place in the calculation section.  2012-2020 Microchip Technology Inc. This 2-point calibration can be a simple linear interpolation between two calibration points (one at high amplitudes, one at low amplitudes at each end of the dynamic range) and helps to significantly lower the effect of crosstalk between channels. A 2-point calibration is very effective in maintaining the measurement error close to zero on the whole dynamic range, since the nonlinearity and distortion of the MCP3910 is very low. Figure 2-6 shows the measurement error curves obtained with the same ADC data taken for Figure 2-5, but where a 2-point calibration has been applied. The difference is significant only at the low end of the dynamic range, where all the perturbing factors are a bigger part of the ADC output signals. These curves show extremely tight measurement error across the full dynamic range (here, typically 10,000:1), which is required in high-accuracy class meters. DS20005116D-page 63 MCP3910 NOTES: DS20005116D-page 64  2012-2020 Microchip Technology Inc. MCP3910 9.0 MCP3910 INTERNAL REGISTERS The addresses associated with the internal registers are listed in Table 9-1. This section also describes the registers in detail. All registers are 24-bit long registers, which can be addressed and read separately. TABLE 9-1: The format of the data registers (0x00 to 0x01) can be changed with the WIDTH_DATA[1:0] bits in the STATUSCOM register. The READ[1:0] and WRITE bits define the groups and types of registers for continuous read/write communication or looping on address sets, as shown in Table 9-2. MCP3910 REGISTER MAP Address Name Bits R/W Description 0x00 CHANNEL0 24 R Channel 0 ADC Data[23:0], MSB First 0x01 CHANNEL1 24 R Channel 1 ADC Data[23:0], MSB First 0x02 Unused 24 U Unused 0x03 Unused 24 U Unused 0x04 Unused 24 U Unused 0x05 Unused 24 U Unused 0x06 Unused 24 U Unused 0x07 Unused 24 U Unused 0x08 MOD 24 R/W 0x09 Unused 24 U 0x0A PHASE 24 R/W Phase Delay Configuration Register 0x0B GAIN 24 R/W Gain Configuration Register 0x0C STATUSCOM 24 R/W Status and Communication Register 0x0D CONFIG0 24 R/W Configuration Register 0x0E CONFIG1 24 R/W Configuration Register 0x0F OFFCAL_CH0 24 R/W Offset Correction Register – Channel 0 0x10 GAINCAL_CH0 24 R/W Gain Correction Register – Channel 0 0x11 OFFCAL_CH1 24 R/W Offset Correction Register – Channel 1 0x12 GAINCAL_CH1 24 R/W 0x13 Unused 24 U Unused 0x14 Unused 24 U Unused 0x15 Unused 24 U Unused 0x16 Unused 24 U Unused 0x17 Unused 24 U Unused 0x18 Unused 24 U Unused 0x19 Unused 24 U Unused 0x1A Unused 24 U Unused 0x1B Unused 24 U Unused 0x1C Unused 24 U Unused 0x1D Unused 24 U Unused 0x1E Unused 24 U Unused 0x1F LOCKCRC 24 R/W  2012-2020 Microchip Technology Inc. Delta-Sigma Modulators Output Value Unused Gain Correction Register – Channel 1 Security Register (password and CRC-16 on register map) DS20005116D-page 65 MCP3910 REGISTER MAP GROUPING FOR ALL CONTINUOUS READ/WRITE MODES CHANNEL 0 Address = 10 = 01 TYPE GROUP 0x01 MOD 0x08 PHASE 0x0A GAIN 0x0B STATUSCOM 0x0C CONFIG0 0x0D CONFIG1 0x0E OFFCAL_CH0 0x0F GAINCAL_CH0 0x10 OFFCAL_CH1 0x11 GAINCAL_CH1 0x12 LOCKCRC 0x1F WRITE = 00 =1 Static 0x00 CHANNEL 1 DS20005116D-page 66 READ[1:0] = 11 GROUP TYPE Function LOOP ENTIRE REGISTER MAP TABLE 9-2: GROUP Static Not Writable Address Undefined for Write Access Static Static Static Static Static Static Static Static Static Static Static GROUP GROUP GROUP =0 TYPE Static Static Static Static Static Static Static Static Static Static Static  2012-2020 Microchip Technology Inc. MCP3910 9.1 CHANNEL Registers – ADC Channel Data Output Registers Name Bits Address Cof CHANNEL0 24 0x00 R CHANNEL1 24 0x01 R REGISTER 9-1: R-0 The ADC Channel Data Output registers always contain the most recent A/D conversion data for each channel. These registers are read-only. They can be accessed independently or linked together (with the READ[1:0] bits). These registers are latched when an ADC read communication occurs. When a data ready event occurs during a read communication, the most current ADC data are also latched to avoid data corruption issues. These registers are updated and latched together if DR_LINK = 1, synchronously with the data ready pulse (toggling on the most lagging ADC channel data ready event). MCP3910 CHANNEL DATA OUTPUT REGISTERS R-0 R-0 R-0 R-0 R-0 R-0 R-0 DATA_CHn[23:16] bit 23 bit 16 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 DATA_CHn[15:8] bit 15 bit 8 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 DATA_CHn[7:0] bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 23-0 x = Bit is unknown DATA_CHn[23:0]: Output Code from ADC Channel n bits These data are post-calibration if the EN_OFFCAL or EN_GAINCAL bits are enabled. These data can be formatted in 16-/24-/32-bit modes, depending on the WIDTH_DATA[1:0] settings (see Section 5.5 “ADC Output Coding”).  2012-2020 Microchip Technology Inc. DS20005116D-page 67 MCP3910 9.2 MOD Register – Modulators Output Register Name Bits Address Cof MOD 24 0x08 R/W The MOD register contains the most recent modulator data output and is updated at a DMCLK rate. The default value corresponds to an equivalent input of 0V on all ADCs. Each bit in this register corresponds to one comparator output on one of the channels. This register should not be written to ensure each ADC accuracy. . REGISTER 9-2: MOD: MODULATORS OUTPUT REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 23 bit 16 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 R/W-0 R/W-0 R/W-1 R/W-1 R/W-0 R/W-0 R/W-1 R/W-1 COMP3_CH1 COMP2_CH1 COMP1_CH1 COMP0_CH1 COMP3_CH0 COMP2_CH0 COMP1_CH0 COMP0_CH0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 23-8 Unimplemented: Read as ‘0’ bit 7-0 COMPn_CHn: Comparator Outputs from ADC Channel n bits DS20005116D-page 68 x = Bit is unknown  2012-2020 Microchip Technology Inc. MCP3910 9.3 PHASE Register – Phase Configuration Register for Channel Pair 0/1 Name Bits Address Cof PHASE 24 0x0A R/W Any write to this register automatically resets and restarts all active ADCs. REGISTER 9-3: PHASE: PHASE CONFIGURATION REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 23 bit 16 U-0 U-0 U-0 U-0 — — — — R/W-0 R/W-0 R/W-0 R/W-0 PHASE[11:8] bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PHASE[7:0] bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 23-12 Unimplemented: read as ‘0’ bit 11-0 PHASE[11:0]: Phase Delay Between Channels CH0 and CH1 bits (reference) Delay = PHASE[11:0] decimal code/DMCLK.  2012-2020 Microchip Technology Inc. DS20005116D-page 69 MCP3910 9.4 GAIN Register – PGA Gain Configuration Register Name Bits Address Cof GAIN 24 0x0B R/W REGISTER 9-4: GAIN: PGA GAIN CONFIGURATION REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 23 bit 16 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 — — R/W-0 R/W-0 R/W-0 PGA_CH1[2] PGA_CH1[1] PGA_CH1[0] R/W-0 PGA_CH0[2] R/W-0 R/W-0 PGA_CH0[1] PGA_CH0[0] bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 23-6 Unimplemented: Read as ‘0’ bit 5-0 PGA_CHn[2:0]: PGA Setting for Channel n bits 111 = Reserved (Gain = 1) 110 = Reserved (Gain = 1) 101 = Gain is 32 100 = Gain is 16 011 = Gain is 8 010 = Gain is 4 001 = Gain is 2 000 = Gain is 1 (default) DS20005116D-page 70 x = Bit is unknown  2012-2020 Microchip Technology Inc. MCP3910 9.5 STATUSCOM Register – Status and Communication Register Name Bits Address Cof STATUSCOM 24 0x0C R/W REGISTER 9-5: STATUSCOM: STATUS AND COMMUNICATION REGISTER R/W-1 R/W-0 R/W-1 R/W-0 R/W-1 READ[1] READ[0] WRITE DR_HIZ DR_LINK R/W-0 R/W-0 R/W-1 WIDTH_ CRC WIDTH_ DATA[1] WIDTH_ DATA[0] bit 23 bit 16 R/W-0 R/W-0 r-0 r-0 R/W-0 U-0 U-0 U-0 EN_CRCCOM EN_INT — — EN_MDAT — — — bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 R-1 R-1 — — — — — — DRSTATUS[1] DRSTATUS[0] bit 7 bit 0 Legend: r = Reserved bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 23-22 READ[1:0]: Address Counter Increment Setting for Read Communication bits 11 = Address counter auto-increments, loops on the entire register map 10 = Address counter auto-increments, loops on register TYPES (default) 01 = Address counter auto-increments, loops on register GROUPS 00 = Address not incremented, continually reads the same single register address bit 21 WRITE: Address Counter Increment Setting for Write Communication bit 1 = Address counter auto-increments and loops on writable part of the register map (default) 0 = Address not incremented, continually writes to the same single register address bit 20 DR_HIZ: Data Ready Pin Inactive State Control bit 1 = The DR pin state is a logic high when data are NOT ready 0 = The DR pin state is high-impedance when data are NOT ready (default) bit 19 DR_LINK: Data Ready Link Control bit 1 = Data ready link enabled; only one pulse is generated on the DR pin corresponding to the data ready pulse of the most lagging ADC 0 = Data ready link disabled; each ADC produces its own data ready pulse on the DR pin bit 18 WIDTH_CRC: Format for CRC-16 on Communications bit 1 = 32-bit (CRC-16 code is followed by sixteen zeros); this coding is compatible with CRC implementation in most 32-bit MCUs (including PIC32 MCUs) 0 = 16-bit (default) bit 17-16 WIDTH_DATA[1:0]: ADC Data Format Settings for All ADCs bits (see Section 5.5 “ADC Output Coding”) 11 = 32-bit with sign extension 10 = 32-bit with zeros padding 01 = 24-bit (default) 00 = 16-bit (with rounding)  2012-2020 Microchip Technology Inc. DS20005116D-page 71 MCP3910 REGISTER 9-5: STATUSCOM: STATUS AND COMMUNICATION REGISTER (CONTINUED) bit 15 EN_CRCCOM: CRC-16 Checksum on Serial Communications Enable bit 1 = CRC-16 checksum is provided at the end of each communication sequence (therefore, each communication is longer); the CRC-16 message is the complete communication sequence (see Section 6.9 “Securing Read Communications Through CRC-16 Checksum” for more details) 0 = Disabled (default) bit 14 EN_INT: CRCREG Interrupt Function Enable bit 1 = The interrupt flag for the CRCREG checksum verification is enabled, the Data Ready pin (DR) will become logic low and stays logic low if a CRCREG checksum error happens; this interrupt is cleared if the LOCK[7:0] value is made equal to the PASSWORD value (0xA5) 0 = The interrupt flag for the CRCREG checksum verification is disabled (default) bit 13-12 Reserved: Should be kept equal to ‘0’ at all times bit 11 EN_MDAT: Modulator Output Enable bit 1 = MDAT0/1 outputs are enabled 0 = MDAT0/1 outputs are disabled and kept in a high-impedance state (default) bit 10-2 Unimplemented: Read as ‘0’ bit 1-0 DRSTATUS[1:0]: Data Ready Status for Each Individual ADC Channel bits DRSTATUS[n] = 1: Channel CHn data are not ready (default) DRSTATUS[n] = 0: Channel CHn data are ready, the status bit is set back to ‘1’ after reading the STATUSCOM register; the status bit is not set back to ‘1’ by the read of the corresponding channel ADC data DS20005116D-page 72  2012-2020 Microchip Technology Inc. MCP3910 9.6 CONFIG0 Register – Configuration Register 0 Name Bits Address Cof CONFIG0 24 0x0D R/W REGISTER 9-6: CONFIG0: CONFIGURATION REGISTER 0 R/W-0 R/W-0 R/W-1 EN_OFFCAL EN_GAINCAL DITHER[1] R/W-1 R/W-1 R/W-0 R/W-0 R/W-0 DITHER[0] BOOST[1] BOOST[0] PRE[1] PRE[0] bit 23 bit 16 R/W-0 R/W-1 R/W-1 U-0 U-0 U-0 U-0 U-0 OSR[2] OSR[1] OSR[0] — — — — — bit 15 bit 8 R/W-0 VREFCAL[7] R/W-1 R/W-0 R/W-1 R/W-0 R/W-0 VREFCAL[6] VREFCAL[5] VREFCAL[4] VREFCAL[3] VREFCAL[2] R/W-0 R/W-0 VREFCAL[1] VREFCAL[0] bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 23 EN_OFFCAL: 24-Bit Digital Offset Error Calibration on All Channels Enable bit 1 = Enabled, this mode does not add any group delay to the ADC data 0 = Disabled (default) bit 22 EN_GAINCAL: 24-Bit Digital Gain Error Calibration on All Channels Enable/Disable bit 1 = Enabled, this mode adds a group delay on all channels of 24 DMCLK periods; all data ready pulses are delayed by 24 DMCLK clock periods compared to the mode with EN_GAINCAL = 0 0 = Disabled (default) bit 21-20 DITHER[1:0]: Dithering Circuit Control for Idle Tones Cancellation, Improved THD on All Channels bits 11 = Dithering on, Strength = Maximum (default) 10 = Dithering on, Strength = Medium 01 = Dithering on, Strength = Minimum 00 = Dithering turned off bit 19-18 BOOST[1:0]: Bias Current Selection for All ADCs bits (impacts achievable maximum sampling speed, see Table 5-2) 11 = All channels have current x 2 10 = All channels have current x 1 (default) 01 = All channels have current x 0.66 00 = All channels have current x 0.5 bit 17-16 PRE[1:0] Analog Master Clock (AMCLK) Prescaler Value bits 11 = AMCLK = MCLK/8 10 = AMCLK = MCLK/4 01 = AMCLK = MCLK/2 00 = AMCLK = MCLK (default)  2012-2020 Microchip Technology Inc. DS20005116D-page 73 MCP3910 REGISTER 9-6: CONFIG0: CONFIGURATION REGISTER 0 (CONTINUED) bit 15-13 OSR[2:0] Oversampling Ratio for Delta-Sigma A/D Conversion bits (all channels, fd/fS) 111 = 4096 (fd = 244 sps for MCLK = 4 MHz, fs = AMCLK = 1 MHz) 110 = 2048 (fd = 488 sps for MCLK = 4 MHz, fs = AMCLK = 1 MHz) 101 = 1024 (fd = 976 sps for MCLK = 4 MHz, fs = AMCLK = 1 MHz) 100 = 512 (fd = 1.953 ksps for MCLK = 4 MHz, fs = AMCLK = 1 MHz) 011 = 256 (fd = 3.90625 ksps for MCLK = 4 MHz, fs = AMCLK = 1 MHz) (default) 010 = 128 (fd = 7.8125 ksps for MCLK = 4 MHz, fs = AMCLK = 1 MHz) 001 = 64 (fd = 15.625 ksps for MCLK = 4 MHz, fs = AMCLK = 1 MHz) 000 = 32 (fd = 31.25 ksps for MCLK = 4 MHz, fs = AMCLK = 1 MHz) bit 12-8 Unimplemented: Read as ‘0’ bit 7-0 VREFCAL[7:0]: Internal Voltage Temperature Coefficient Value bits (See Section 5.6.3 “Temperature Compensation (VREFCAL[7:0])” for complete description.) DS20005116D-page 74  2012-2020 Microchip Technology Inc. MCP3910 9.7 CONFIG1 Register – Configuration Register 1 Name Bits Address Cof CONFIG1 24 0x0E R/W REGISTER 9-7: CONFIG1: CONFIGURATION REGISTER 1 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 — — — — — — RESET[1] RESET[0] bit 23 bit 16 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — R/W-0 R/W-0 SHUTDOWN[1] SHUTDOWN[0] bit 15 bit 8 R/W-0 R/W-1 U-0 U-0 U-0 U-0 U-0 U-0 VREFEXT CLKEXT — — — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 23-18 Unimplemented: Read as ‘0’ bit 17-16 RESET[1:0]: Soft Reset Mode Setting for Each Individual ADC bits 1 = Channel CHn is in Soft Reset mode 0 = Channel CHn is not in Soft Reset mode bit 15-10 Unimplemented: Read as ‘0’ bit 9-8 SHUTDOWN[1:0]: Shutdown Mode Setting for Each Individual ADC bits 1 = ADC Channel is in Shutdown mode 0 = ADC Channel is not in Shutdown mode bit 7 VREFEXT: Internal Voltage Reference Selection bit 1 = Internal voltage reference disabled; an external reference voltage needs to be applied across the REFIN+/- pins; the analog power consumption (AIDD) is slightly diminished in this mode since the internal voltage reference is placed into Shutdown mode 0 = Internal reference enabled; for optimal accuracy, the REFIN+/OUT pin needs proper decoupling capacitors, REFIN- pin should be connected to AGND when in this mode bit 6 CLKEXT: Internal Clock Selection bit 1 = MCLK is generated externally and should be provided on the OSC1 pin; the crystal oscillator is disabled and consumes no current (default) 0 = Crystal oscillator is enabled; a crystal must be placed between OSC1 and OSC2 with proper decoupling capacitors; the digital power consumption (DIDD) is increased in this mode due to the oscillator bit 5-0 Unimplemented: Read as ‘0’  2012-2020 Microchip Technology Inc. DS20005116D-page 75 MCP3910 9.8 OFFCAL_CHn and GAINCAL_CHn Registers – Digital Offset and Gain Error Calibration Registers Name Bits Address Cof OFFCAL_CH0 24 0x0F R/W GAINCAL_CH0 24 0x10 R/W OFFCAL_CH1 24 0x11 R/W GAINCAL_CH1 24 0x12 R/W REGISTER 9-8: R/W-0 OFFCAL_CHn: DIGITAL OFFSET CALIBRATION REGISTER R/W-0 R/W-0 OFFCAL_CHn[23:21] ... R/W-0 R/W-0 ... R/W-0 R/W-0 OFFCAL_CHn[3:0] bit 23 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 23-0 x = Bit is unknown OFFCAL_CHn[23:0]: Digital Offset Calibration Value for Corresponding Channel CHn bits This register is simply added to the output code of the channel, bit-by-bit. This register is a 24-bit two’s complement MSB first coding. CHn Output Code = OFFCAL_CHn + ADC CHn Output Code. This register is a Don’t Care if EN_OFFCAL = 0 (offset calibration disabled), but its value is not cleared by the EN_OFFCAL bit. REGISTER 9-9: R/W-0 GAINCAL_CHn: GAIN ERROR CALIBRATION REGISTER R/W-0 R/W-0 GAINCAL_CHn[23:21] ... R/W-0 ... R/W-0 R/W-0 R/W-0 GAINCAL_CHn[3:0] bit 23 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 23-0 x = Bit is unknown GAINCAL_CHn: Digital Gain Error Calibration Value for Corresponding Channel CHn bits This register is a 24-bit signed MSB first coding with a range of -1x to +0.9999999x (from 0x80000 to 0x7FFFFF). The gain calibration adds 1x to this register and multiplies it to the output code of the channel, bit-by-bit, after offset calibration. The range of the gain calibration is thus from 0x to 1.9999999x (from 0x80000 to 0x7FFFFF). The LSB corresponds to a 2-23 increment in the multiplier. CHn Output Code = (GAINCAL_CHn + 1) * ADC CHn Output Code. This register is a Don’t Care if EN_GAINCAL = 0 (Gain calibration disabled) but its value is not cleared by the EN_GAINCAL bit. DS20005116D-page 76  2012-2020 Microchip Technology Inc. MCP3910 9.9 SECURITY Register – Password and CRC-16 on Register Map Name Bits Address Cof LOCK/CRC 24 0x1F R/W REGISTER 9-10: R/W-1 SECURITY: LOCK/CRC REGISTER R/W-0 R/W-1 R/W-0 R/W-0 R/W-1 R/W-0 R/W-1 LOCK[7:0] bit 23 bit 16 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CRCREG[15:8] bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CRCREG[7:0] bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 23-16 LOCK[7:0]: Lock Code for Writable Part of Register Map bits LOCK[7:0] = PASSWORD = 0xA5 (default value): The entire register map is writable. The CRCREG[15:0] bits and the CRC interrupt are cleared. No CRC-16 checksum on register map is calculated. LOCK[7:0] are different than 0xA5: The only writable register is the LOCK/CRC register. All other registers will appear as undefined while in this mode. The CRCREG checksum is calculated continuously and can generate interrupts if the CRC interrupt EN_INT bit has been enabled. If a write to a register needs to be performed, the user needs to unlock the register map beforehand by writing 0xA5 to the LOCK[7:0] bits. bit 15-0 CRCREG[15:0]: CRC-16 Checksum Calculated with Writable Part of Register Map as Message bits This is a read-only 16-bit code. This checksum is continuously recalculated and updated every 12 DMCLK periods. It is reset to its default value (0x0000) when LOCK[7:0] = 0xA5.  2012-2020 Microchip Technology Inc. DS20005116D-page 77 MCP3910 NOTES: DS20005116D-page 78  2012-2020 Microchip Technology Inc. MCP3910 10.0 PACKAGING INFORMATION 10.1 Package Marking Information 20-Lead QFN (4x4x.9 mm) PIN 1 XXXXX XXXXXX XXXXXX YWWNNN 20-Lead SSOP (5.30 mm) XXXXXXXXXXX XXXXXXXXXXX YYWWNNN Legend: XX...X Y YY WW NNN e3 * Note: Example PIN 1 3910 A1 E/ML e 906256 3 Example MCP3910A1 E/SS e3 1906256 Customer-specific information Year code (last digit of calendar year) Year code (last 2 digits of calendar year) Week code (week of January 1 is week ‘01’) Alphanumeric traceability code Pb-free JEDEC designator for Matte Tin (Sn) This package is Pb-free. The Pb-free JEDEC designator ( e3 ) can be found on the outer packaging for this package. In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information.  2012-2020 Microchip Technology Inc. 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