MCP3912A1-E/MQ

MCP3912 3V Four-Channel Analog Front End Features: Description: • Four Synchronous Sampling 24-Bit Resolution Delta-Sigma A/D Converters • 93.5 dB SINAD, -107 dBc Total Harmonic Distortion (THD) (up to 35th Harmonic), 112 dBFS SFDR for Each Channel • Enables 0.1% Typical Active Power Measurement Error Over a 10,000:1 Dynamic Range • Advanced Security Features: - 16-Bit Cyclic Redundancy Check (CRC) Checksum on All Communications for Secure Data Transfers - 16-Bit CRC Checksum and Interrupt Alert for Register Map Configuration - Register Map Lock with 8-Bit Secure Key • 2.7V-3.6V AVDD, DVDD • Programmable Data Rate Up to 125 ksps: - 4 MHz Maximum Sampling Frequency - 16 MHz Maximum Master Clock • Oversampling Ratio Up to 4096 • Ultra-Low Power Shutdown Mode with < 10 µA • -122 dB Crosstalk Between Channels • Low Drift 1.2V Internal Voltage Reference: 9 ppm/°C • Differential Voltage Reference Input Pins • High-Gain PGA on Each Channel (up to 32 V/V) • Phase Delay Compensation with 1 µs Time Resolution • Separate Data Ready Pin for Easy Synchronization • Individual 24-Bit Digital Offset and Gain Error Correction for Each Channel • High-Speed 20 MHz SPI Interface with Mode 0,0 and 1,1 Compatibility • Continuous Read/Write Modes for Minimum Communication Time with Dedicated 16/32-Bit Modes • Available in 28-Lead QFN and 28-Lead SSOP Packages • Extended Temperature Range: -40°C to +125°C The MCP3912 is a 3V four-channel Analog Front End (AFE) containing four synchronous sampling DeltaSigma Analog-to-Digital Converters (ADC), four PGAs, phase delay compensation block, low-drift internal voltage reference, Digital Offset and Gain Error Calibration registers, and high-speed 20 MHz SPI-compatible serial interface.  2014-2020 Microchip Technology Inc. The MCP3912 ADCs are fully configurable, with features, such as 16/24-bit resolution, Oversampling Ratio (OSR) from 32 to 4096, gain from 1x to 32x, independent shutdown and Reset, dithering and autozeroing. The communication is largely simplified with 8-bit commands, including various continuous Read/ Write modes and 16/24/32-bit data formats that can be accessed by the Direct Memory Access (DMA) of an 8, 16 or 32-bit MCU. A separate Data Ready pin is also included that can directly be connected to an Interrupt Request (IRQ) input of an MCU. The MCP3912 includes advanced security features to secure the communications and the configuration settings, such as a CRC-16 checksum on both serial data outputs and static register map configuration. It also includes a register map lock through an 8-bit secure key to stop unwanted WRITE commands from processing. The MCP3912 is capable of interfacing with a variety of voltage and current sensors, including shunts, current transformers, Rogowski coils and Hall effect sensors. Applications: • • • • • • Polyphase Energy Meters Energy Metering and Power Measurement Automotive Portable Instrumentation Medical and Power Monitoring Audio/Voice Recognition DS20005348C-page 1 MCP3912 Package Type RESET MCP3912 5x5 QFN* DVDD 27 RESET CH0- 3 26 SDI 28 27 26 25 24 23 22 CH1- 4 25 SDO CH1+ 5 24 SCK CH2+ 6 23 CS CH2- 7 22 OSC2 CH3- 8 21 OSC1/CLKI CH3+ 9 20 DGND NC 10 19 NC NC 11 18 DR NC 12 17 DGND NC 13 16 AGND REFIN+/OUT 14 15 REFIN- AVDD DVDD 28 2 DGND 1 CH0+ AGND AVDD CH0+ CH0- MCP3912 SSOP CH1- 1 21 SDI CH1+ 2 20 SDO CH2+ 3 19 SCK EP 29 CH2- 4 18 CS CH3- 5 17 OSC2 CH3+ 6 16 OSC1/CLKI 15 DGND NC 7 DR DGND AVDD DVDD AGND 9 10 11 12 13 14 REFIN+/ OUT REFIN- 8 *Includes Exposed Thermal Pad (EP); see Table 1-3. Functional Block Diagram REFIN+/OUT AVDD Voltage Reference + DVDD Vref REFIN- Xtal Oscillator AMCLK VREFEXT Clock Generation DMCLK/DRCLK Vref- Vref+ DMCLK OFFCAL_CH0 OSR/2PHASE1 CH0+ + CH0- PGA MOD Phase Shifter Modulator SINC3+ SINC1 OSR/2 CH1+ + CH1- PGA MOD Phase Shifter Modulator SINC3+ SINC1 OSR/2PHASE1 CH2+ + CH2- PGA + CH3- PGA X Gain Cal. OFFCAL_CH1 GAINCAL_CH1 + X Offset Cal. Gain Cal. OFFCAL_CH2 GAINCAL_CH2 Offset Cal. Gain Cal. OFFCAL_CH3 GAINCAL_CH3 X Phase Shifter SINC3+ SINC1 OSR/2 CH3+ + Offset Cal. MOD Modulator X MOD Modulator GAINCAL_CH0 Phase Shifter 3 SINC + SINC1 Offset Cal. Gain Cal. MCLK OSC1 OSC2 OSR PRE DATA_CH0 DATA_CH1 DATA_CH2 DATA_CH3 Digital SPI Interface DR SDO RESET SDI SCK CS POR AVDD Monitoring POR DVDD Monitoring ANALOG AGND DS20005348C-page 2 DIGITAL DGND  2014-2020 Microchip Technology Inc. MCP3912 1.0 † Notice: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions, above those indicated in the operational listings of this specification, is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings† VDD ..................................................................... -0.3V to 4.0V Digital inputs and outputs w.r.t. AGND ................. -0.3V to 4.0V Analog input w.r.t. AGND ..................................... ....-2V to +2V VREF input w.r.t. AGND ............................... -0.6V to VDD +0.6V Storage temperature .....................................-65°C to +150°C Ambient temp. with power applied ................-65°C to +125°C Soldering temperature of leads (10 seconds) ............. +300°C ESD on all pins (HBM,MM) .................................... 4 kV, 300V 1.1 Electrical Specifications TABLE 1-1: ANALOG SPECIFICATIONS Electrical Specifications: Unless otherwise indicated, all parameters apply at AVDD = DVDD = 3V; MCLK = 4 MHz; PRE[1:0] = 00; OSR = 256; GAIN = 1; VREFEXT = 0; CLKEXT = 1; DITHER[1:0] = 11; BOOST[1:0] = 10; VCM = 0V; TA = -40°C to +125°C; VIN = -0.5 dBFS @ 50/60 Hz on all channels. Characteristic Sym. Min. Typ. Max. Units Conditions 24 — — bits OSR = 256 or greater ADC Performance Resolution (No Missing Codes) Sampling Frequency fS(DMCLK) — 1 4 MHz For maximum condition, BOOST[1:0] = 11 Output Data Rate fD(DRCLK) — 4 125 ksps For maximum condition, BOOST[1:0] = 11, OSR = 32 CHn+/- -1 — +1 V All analog input channels measured to AGND IIN — ±1 — nA RESET[3:0] = 1111, MCLK running continuously — +600/GAIN mV VREF = 1.2V, proportional to VREF -2 0.2 2 mV Note 5 — 0.5 — µV/°C -6 — +6 % Analog Input Absolute Voltage on CHn+/- Pins, n between 0 and 3 Analog Input Leakage Current Differential Input Voltage Range Offset Error (CHn+ – CHn-) -600/GAIN VOS Offset Error Drift Gain Error Note 1: 2: 3: 4: 5: 6: 7: 8: GE Note 5 Dynamic performance specified at -0.5 dB below the maximum differential input value, VIN = 1.2 VPP = 424 mVRMS @ 50/60 Hz, VREF = 1.2V. See Section 4.0 “Terminology and Formulas” for definition. This parameter is established by characterization and not 100% tested. For these operating currents, the following Configuration bit settings apply: SHUTDOWN[3:0] = 0000, RESET[3:0] = 0000, VREFEXT = 0, CLKEXT = 0. For these operating currents, the following Configuration bit settings apply: SHUTDOWN[3:0] = 1111, VREFEXT = 1, CLKEXT = 1. Measured on one channel versus all others channels. The average of crosstalk performance over all channels (see Figure 2-32 for individual channel performance). Applies to all gains. Offset and gain errors depend on the PGA gain setting; see typical performance curves for typical performance. Outside of this range, ADC accuracy is not specified. An extended input range of ±2V can be applied continuously to the part with no damage. For proper operation and for optimizing ADC accuracy, AMCLK should be limited to the maximum frequency defined in Table 5-2, as a function of the BOOST and PGA settings chosen. MCLK can take larger values as long as the prescaler settings (PRE[1:0]) limit AMCLK = MCLK/PRESCALE in the defined range in Table 5-2. This parameter is established by characterization and not 100% tested.  2014-2020 Microchip Technology Inc. DS20005348C-page 3 MCP3912 TABLE 1-1: ANALOG SPECIFICATIONS (CONTINUED) Electrical Specifications: Unless otherwise indicated, all parameters apply at AVDD = DVDD = 3V; MCLK = 4 MHz; PRE[1:0] = 00; OSR = 256; GAIN = 1; VREFEXT = 0; CLKEXT = 1; DITHER[1:0] = 11; BOOST[1:0] = 10; VCM = 0V; TA = -40°C to +125°C; VIN = -0.5 dBFS @ 50/60 Hz on all channels. Characteristic Sym. Gain Error Drift Min. Typ. Max. Units — 1 — ppm/°C Conditions Integral Nonlinearity INL — 5 — ppm Measurement Error ME — 0.1 — % Measured with a 10,000:1 dynamic range (from 600 mVPeak to 60 µVPeak), AVDD = DVDD = 3V, measurement points averaging time: 20 seconds, measured on each channel pair (CH0/1, CH2/3) Differential Input Impedance ZIN 232 — — k G = 1, proportional to 1/AMCLK 142 — — k G = 2, proportional to 1/AMCLK 72 — — k G = 4, proportional to 1/AMCLK 38 — — k G = 8, proportional to 1/AMCLK 36 — — k G = 16, proportional to 1/AMCLK 33 — — k G = 32, proportional to 1/AMCLK Signal-to-Noise and Distortion Ratio (Note 1) SINAD 92 93.5 — dB Total Harmonic Distortion (Note 1) THD — -107 -103 dBc Signal-to-Noise Ratio (Note 1) SNR 92 94 — dB Spurious-Free Dynamic Range (Note 1) SFDR — 112 — dBFS Crosstalk (50, 60 Hz) CTALK — -122 — dB Note 4 AC PSRR — -73 — dB AVDD = DVDD = 3V + 0.6 VPP, 50/60 Hz, 100/120 Hz AC Power Supply Rejection Includes the first 35 harmonics DC Power Supply Rejection DC PSRR — -73 — dB AVDD = DVDD = 2.7V to 3.6V DC Common-mode Rejection DC CMRR — -100 — dB VCM from -1V to +1V Note 1: 2: 3: 4: 5: 6: 7: 8: Dynamic performance specified at -0.5 dB below the maximum differential input value, VIN = 1.2 VPP = 424 mVRMS @ 50/60 Hz, VREF = 1.2V. See Section 4.0 “Terminology and Formulas” for definition. This parameter is established by characterization and not 100% tested. For these operating currents, the following Configuration bit settings apply: SHUTDOWN[3:0] = 0000, RESET[3:0] = 0000, VREFEXT = 0, CLKEXT = 0. For these operating currents, the following Configuration bit settings apply: SHUTDOWN[3:0] = 1111, VREFEXT = 1, CLKEXT = 1. Measured on one channel versus all others channels. The average of crosstalk performance over all channels (see Figure 2-32 for individual channel performance). Applies to all gains. Offset and gain errors depend on the PGA gain setting; see typical performance curves for typical performance. Outside of this range, ADC accuracy is not specified. An extended input range of ±2V can be applied continuously to the part with no damage. For proper operation and for optimizing ADC accuracy, AMCLK should be limited to the maximum frequency defined in Table 5-2, as a function of the BOOST and PGA settings chosen. MCLK can take larger values as long as the prescaler settings (PRE[1:0]) limit AMCLK = MCLK/PRESCALE in the defined range in Table 5-2. This parameter is established by characterization and not 100% tested. DS20005348C-page 4  2014-2020 Microchip Technology Inc. MCP3912 TABLE 1-1: ANALOG SPECIFICATIONS (CONTINUED) Electrical Specifications: Unless otherwise indicated, all parameters apply at AVDD = DVDD = 3V; MCLK = 4 MHz; PRE[1:0] = 00; OSR = 256; GAIN = 1; VREFEXT = 0; CLKEXT = 1; DITHER[1:0] = 11; BOOST[1:0] = 10; VCM = 0V; TA = -40°C to +125°C; VIN = -0.5 dBFS @ 50/60 Hz on all channels. Characteristic Sym. Min. Typ. Max. Units Conditions V VREFEXT = 0, TA = +25°C only Internal Voltage Reference Tolerance Temperature Coefficient Output Impedance Internal Voltage Reference Operating Current VREF 1.176 1.2 1.224 TCVREF — 9 — ZOUTVREF — 0.6 — k VREFEXT = 0 AIDDVREF — 54 — µA VREFEXT = 0, SHUTDOWN[3:0] = 1111 — — 10 pF ppm/°C TA = -40°C to +125°C, VREFEXT = 0, VREFCAL[7:0] = 0x50 Voltage Reference Input Input Capacitance Differential Input Voltage Range (VREF+ – VREF-) VREF 1.1 — 1.3 V VREFEXT = 1 Absolute Voltage on REFIN+ Pin VREF+ VREF- + 1.1 — VREF- + 1.3 V VREFEXT = 1 Absolute Voltage REFIN- Pin VREF- -0.1 — +0.1 V REFIN- should be connected to AGND when VREFEXT = 0 Master Clock Input Frequency Range fMCLK — — 20 MHz CLKEXT = 1 (Note 7) Crystal Oscillator Operating Frequency Range fXTAL 1 — 20 MHz CLKEXT = 0 (Note 7) (Note 7) Master Clock Input Analog Master Clock AMCLK — — 16 MHz DIDDXTAL — 80 — µA Operating Voltage, Analog AVDD 2.7 — 3.6 V Operating Voltage, Digital DVDD 2.7 — 3.6 V Operating Current, Analog (Note 2) IDD,A — 2.8 4 mA BOOST[1:0] = 00 — 3.4 4.5 mA BOOST[1:0] = 01 — 4.7 6.4 mA BOOST[1:0] = 10 — 8.1 11.8 mA BOOST[1:0] = 11 Crystal Oscillator Operating Current CLKEXT = 0 Power Supply Note 1: 2: 3: 4: 5: 6: 7: 8: Dynamic performance specified at -0.5 dB below the maximum differential input value, VIN = 1.2 VPP = 424 mVRMS @ 50/60 Hz, VREF = 1.2V. See Section 4.0 “Terminology and Formulas” for definition. This parameter is established by characterization and not 100% tested. For these operating currents, the following Configuration bit settings apply: SHUTDOWN[3:0] = 0000, RESET[3:0] = 0000, VREFEXT = 0, CLKEXT = 0. For these operating currents, the following Configuration bit settings apply: SHUTDOWN[3:0] = 1111, VREFEXT = 1, CLKEXT = 1. Measured on one channel versus all others channels. The average of crosstalk performance over all channels (see Figure 2-32 for individual channel performance). Applies to all gains. Offset and gain errors depend on the PGA gain setting; see typical performance curves for typical performance. Outside of this range, ADC accuracy is not specified. An extended input range of ±2V can be applied continuously to the part with no damage. For proper operation and for optimizing ADC accuracy, AMCLK should be limited to the maximum frequency defined in Table 5-2, as a function of the BOOST and PGA settings chosen. MCLK can take larger values as long as the prescaler settings (PRE[1:0]) limit AMCLK = MCLK/PRESCALE in the defined range in Table 5-2. This parameter is established by characterization and not 100% tested.  2014-2020 Microchip Technology Inc. DS20005348C-page 5 MCP3912 TABLE 1-1: ANALOG SPECIFICATIONS (CONTINUED) Electrical Specifications: Unless otherwise indicated, all parameters apply at AVDD = DVDD = 3V; MCLK = 4 MHz; PRE[1:0] = 00; OSR = 256; GAIN = 1; VREFEXT = 0; CLKEXT = 1; DITHER[1:0] = 11; BOOST[1:0] = 10; VCM = 0V; TA = -40°C to +125°C; VIN = -0.5 dBFS @ 50/60 Hz on all channels. Characteristic Operating Current, Digital Sym. Min. Typ. Max. Units Conditions IDD,D — 0.28 0.6 mA MCLK = 4 MHz, proportional to MCLK (Note 2) — 1.1 — mA MCLK = 16 MHz, proportional to MCLK (Note 2) Shutdown Current, Analog IDDS,A — 0.01 2 µA AVDD pin only (Notes 3 and 8) Shutdown Current, Digital IDDS,D — 0.01 4 µA DVDD pin only (Notes 3 and 8) Pull-down Current on OSC2 Pin (External Clock mode only) IOSC2 — 35 — µA CLKEXT = 1 Dynamic performance specified at -0.5 dB below the maximum differential input value, VIN = 1.2 VPP = 424 mVRMS @ 50/60 Hz, VREF = 1.2V. See Section 4.0 “Terminology and Formulas” for definition. This parameter is established by characterization and not 100% tested. For these operating currents, the following Configuration bit settings apply: SHUTDOWN[3:0] = 0000, RESET[3:0] = 0000, VREFEXT = 0, CLKEXT = 0. For these operating currents, the following Configuration bit settings apply: SHUTDOWN[3:0] = 1111, VREFEXT = 1, CLKEXT = 1. Measured on one channel versus all others channels. The average of crosstalk performance over all channels (see Figure 2-32 for individual channel performance). Applies to all gains. Offset and gain errors depend on the PGA gain setting; see typical performance curves for typical performance. Outside of this range, ADC accuracy is not specified. An extended input range of ±2V can be applied continuously to the part with no damage. For proper operation and for optimizing ADC accuracy, AMCLK should be limited to the maximum frequency defined in Table 5-2, as a function of the BOOST and PGA settings chosen. MCLK can take larger values as long as the prescaler settings (PRE[1:0]) limit AMCLK = MCLK/PRESCALE in the defined range in Table 5-2. This parameter is established by characterization and not 100% tested. Note 1: 2: 3: 4: 5: 6: 7: 8: 1.2 Serial Interface Characteristics TABLE 1-2: SERIAL DC CHARACTERISTICS Electrical Specifications: Unless otherwise indicated, all parameters apply at DVDD = 2.7 to 3.6 V; TA = -40°C to +125°C; CLOAD = 30 pF; applies to all digital I/Os. Characteristic Sym. Min. Max. Units VIH 0.7 DVDD Low-Level Input Voltage VIL — — — V Schmitt triggered — 0.3 DVDD V Schmitt triggered Input Leakage Current ILI — — ±1 µA CS = DVDD, VIN = DGND to DVDD Output Leakage Current ILO — — ±1 µA CS = DVDD, VOUT = DGND or DVDD Hysteresis of Schmitt Trigger Inputs VHYS — 500 — mV DVDD = 3.3V only (Note 2) Low-Level Output Voltage VOL — — 0.2 DVDD V High-Level Output Voltage VOH 0.75 DVDD — — V IOH = -1.7 mA Internal Capacitance (All Inputs and Outputs) CINT — — 7 pF TA = +25°C, SCK = 1.0 MHz, DVDD =3.3V (Note 1) High-Level Input Voltage Note 1: 2: Typ. Conditions IOL = +1.7 mA This parameter is periodically sampled and not 100% tested. This parameter is established by characterization and not production tested. DS20005348C-page 6  2014-2020 Microchip Technology Inc. MCP3912 TABLE 1-3: SERIAL AC CHARACTERISTICS Electrical Specifications: Unless otherwise indicated, all parameters apply at DVDD = 2.7 to 3.6V; TA = -40°C to +125°C; GAIN = 1; CLOAD = 30 pF. Characteristic Sym. Min. Typ. Max. Units fSCK — — 20 MHz Serial Clock Frequency CS Setup Time tCSS 25 — — ns CS Hold Time tCSH 50 — — ns CS Disable Time tCSD 50 — — ns Conditions Data Setup Time tSU 5 — — ns Data Hold Time tHD 10 — — ns Serial Clock High Time tHI 20 — — ns Serial Clock Low Time tLO 20 — — ns Serial Clock Delay Time tCLD 50 — — ns Serial Clock Enable Time tCLE 50 — — ns Output Valid from SCK Low tDO — — 25 ns Output Hold Time tHO 0 — — ns Note 1 Note 1 tDIS — — 25 ns Reset Pulse Width (RESET) Output Disable Time tMCLR 100 — — ns Data Transfer Time to DR (Data Ready) tDODR — — 25 ns tDRP — 1/(2 x DMCLK) — µs Data Ready Pulse Low Time Note 1: 2: Note 2 This parameter is periodically sampled and not 100% tested. This parameter is established by characterization and not production tested. TABLE 1-4: TEMPERATURE SPECIFICATIONS Electrical Specifications: Unless otherwise indicated, all parameters apply at AVDD = 2.7 to 3.6V; DVDD = 2.7 to 3.6V. Parameters Sym. Min. Typ. Max. Units. Operating Temperature Range TA -40 — +125 °C Storage Temperature Range TA -65 — +150 °C Thermal Resistance, 28-Lead SSOP JA — 80 — °C/W Thermal Resistance, 28-Lead QFN JA — 41 — °C/W Conditions Temperature Ranges Note 1 Thermal Package Resistances Note 1: The internal junction temperature (TJ) must not exceed the absolute maximum specification of +150°C.  2014-2020 Microchip Technology Inc. DS20005348C-page 7 MCP3912 CS fSCK tHI tCSH tLO Mode 1,1 SCK Mode 0,0 tDO tDIS tHO MSB Out SDO LSB Out DON’T CARE SDI FIGURE 1-1: Serial Output Timing Diagram. tCSD CS tHI Mode 1,1 SCK tCLE fSCK tCSS tCLD tCSH tLO Mode 0,0 tSU tHD MSB In SDI LSB In HIGH-Z SDO FIGURE 1-2: Serial Input Timing Diagram. 1/fD tDRP DR tDODR SCK SDO FIGURE 1-3: Data Ready Pulse/Sampling Timing Diagram. H Timing Waveform for tDO Waveform for tDIS VIH SCK CS tDO SDO 90% SDO tDIS HIGH-Z 10% FIGURE 1-4: DS20005348C-page 8 Timing Waveforms.  2014-2020 Microchip Technology Inc. MCP3912 2.0 TYPICAL PERFORMANCE CURVES Note: The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore outside the warranted range. Note: Unless otherwise indicated, AVDD = 3V; DVDD = 3V; TA = +25°C; MCLK = 4 MHz; PRESCALE = 1; OSR = 256; GAIN = 1; Dithering = Maximum; VIN = -0.5 dBFS @ 60 Hz on all channels; VREFEXT = 0; CLKEXT = 1; BOOST[1:0] = 10. 0 Amplitude (dB) -40 -60 Am mplitud de (dB)) Vin = -0.5 dBFS @ 60 Hz fD = 3.9 ksps OSR = 256 Dithering = Off 16 ksamples FFT -20 -80 -100 -120 -140 140 -160 -180 0 500 1000 1500 2000 0 -20 -40 -60 -80 -100 -120 -140 -160 -180 0 Frequency (Hz) FIGURE 2-1: 500 FIGURE 2-4: Spectral Response. 1000 Frequency (Hz) 1500 2000 Spectral Response. 1.0% 0 -40 -60 Measurement Error (%) Vin = -60 dBFS @ 60 Hz fD = 3.9 ksps OSR = 256 Dithering = Off 16 ksamples FFT 20 -20 Amplitude (dB B) Vin = -60 dBFS @ 60 Hz fD = 3.9 ksps OSR = 256 Dithering = Maximum 16 ksamples FFT -80 -100 -120 -140 -160 -180 0 500 FIGURE 2-2: 1000 1500 Frequency (Hz) 2000 0.5% % Error Channel 0, 1 0.0% -0.5% -1.0% 0.01 0.1 1 10 100 1000 Current Channel Input Amplitude (mVPeak) FIGURE 2-5: Measurement Error with 1-Point Calibration. Spectral Response. Vin = -0.5 dBFS @ 60 Hz fD = 3.9 ksps OSR = 256 Dithering = Maximum 16 ksamples FFT Amplitude (dB) -20 -40 -60 -80 -100 -120 -140 140 Measurement Error (%) 1.0% 0 0.5% % Error Channel 0, 1 0.0% -0.5% -160 -180 0 FIGURE 2-3: 500 1000 Frequency (Hz) 1500 Spectral Response.  2014-2020 Microchip Technology Inc. 2000 -1.0% 0.01 0.1 1 10 100 1000 Current Channel Input Amplitude (mVPeak) FIGURE 2-6: Measurement Error with 2-Point Calibration. DS20005348C-page 9 MCP3912 Unless otherwise indicated, AVDD = 3V; DVDD = 3V; TA = +25°C; MCLK = 4 MHz; PRESCALE = 1; OSR = 256; GAIN = 1; Dithering = Maximum; VIN = -0.5 dBFS @ 60 Hz on all channels; VREFEXT = 0; CLKEXT = 1; BOOST[1:0] = 10. Standar deviation = 78 LSB Noise = 7.4ȝVrms 16 ksamples -108.2 -107.8 -107.4 -107.0 -106.6 Total Harmonic Distortion (-dBc) ( dBc) Output Noise (LSB) FIGURE 2-10: THD Repeatability Freq quency of Occurrence Total Harmonic Distortion (dBc) FIGURE 2-7: Histogram. -106.2 448 481 514 548 581 614 647 680 714 747 780 813 846 880 913 946 979 1,012 1,046 1,079 1,112 F Freque ency off Occurrence e Frequ uency of Occurrence Note: Output Noise Histogram. -90 Dithering=Maximum Dithering=Medium Dithering=Minimum Dithering=Off -95 -100 -105 -110 -115 -120 -125 -130 111.7 112.3 112.9 113.5 114.1 114.7 115.3 Spurious Free Dynamic Range (dBFS) 115.9 FIGURE 2-8: Spurious Free Dynamic Range Repeatability Histogram. 32 64 128 256 512 1024 2048 4096 Oversampling Ratio (OSR) FIGURE 2-11: THD vs.OSR. Signal-to-N Noise and Disto ortion R Ratio (d dB) Frequency o of Occu urrence e 110 105 100 95 90 85 80 75 70 65 60 93.3 93.4 93.5 93.6 93.7 Signal to Noise and Distortion (dB) FIGURE 2-9: Histogram. DS20005348C-page 10 SINAD Repeatability 93.8 Dithering Maximu Dithering=Maximu m Dithering=Medium 32 FIGURE 2-12: 64 128 256 512 1024 2048 4096 Oversampling Ratio (OSR) SINAD vs. OSR.  2014-2020 Microchip Technology Inc. MCP3912 Unless otherwise indicated, AVDD = 3V; DVDD = 3V; TA = +25°C; MCLK = 4 MHz; PRESCALE = 1; OSR = 256; GAIN = 1; Dithering = Maximum; VIN = -0.5 dBFS @ 60 Hz on all channels; VREFEXT = 0; CLKEXT = 1; BOOST[1:0] = 10. Note: 110 105 100 95 90 85 80 75 70 65 60 100 32 64 Spurio ous Fre ee Dyn namic Range ((dBFS)) R 90 85 80 75 70 SNR vs.OSR. 60 2 100 115 95 110 105 100 95 g Dithering=Maximum Dithering=Medium Dithering=Minimum Dithering=Off Dithering Off 85 4 6 8 10 12 14 MCLK Frequency (MHz) FIGURE 2-16: 120 90 Boost = 00 Boost = 01 Boost = 10 65 128 256 512 1024 2048 4096 Oversampling O li Ratio R ti (OSR) FIGURE 2-13: 80 64 SFDR vs. OSR. 18 90 85 80 75 70 Boost = 00 Boost = 01 Boost = 10 Boost = 11 65 128 256 512 1024 2048 4096 O Oversampling li Ratio R ti (OSR) FIGURE 2-14: 16 SINAD vs. MCLK. 60 32 2 4 6 FIGURE 2-17: 8 10 12 14 16 MCLK Frequency (MHz) 18 SNR vs. MCLK. 120 -60 -65 -70 -75 -80 -85 -90 -95 100 -100 -105 -110 Boost = 00 Boost = 01 Boost = 10 Boost = 11 2 4 FIGURE 2-15: 6 8 10 12 14 16 MCLK Frequency (MHz) THD vs. MCLK.  2014-2020 Microchip Technology Inc. 18 Spurio ous Fre ee Dynamic Range (dBF FS) Tota al Harmonic Distortion (dB) 95 Sig gnal-to o-Noise e and Disttortion (dB) Dithering Maximum Dithering=Maximum Dithering=Medium Dithering=Minimum Dithering=Off Signal-to-Noise Rattio (dB)) Signal-to--Noise Ratio ((dB) L 20 110 100 90 80 Boost = 00 Boost = 01 Boost = 10 Boost = 11 70 60 2 FIGURE 2-18: 4 6 8 10 12 14 16 MCLK Frequency (MHz) 18 20 SFDR vs. MCLK. DS20005348C-page 11 MCP3912 Note: Unless otherwise indicated, AVDD = 3V; DVDD = 3V; TA = +25°C; MCLK = 4 MHz; PRESCALE = 1; OSR = 256; GAIN = 1; Dithering = Maximum; VIN = -0.5 dBFS @ 60 Hz on all channels; VREFEXT = 0; CLKEXT = 1; BOOST[1:0] = 10. 140 OSR = 32 OSR = 64 OSR = 128 OSR = 256 OSR = 512 OSR = 1024 OSR = 2048 OSR = 4096 -20 -40 -60 -80 -100 -120 SpuriousFree Dynamic Range (dBFS) Total Harmonic DistorWion (dB) 0 120 100 -140 2 FIGURE 2-19: 4 8 Gain (V/V) 16 40 20 32 THD vs. GAIN. 1 2 FIGURE 2-22: 120 Total Harmonic Distortion (dB) -20 100 80 60 OSR = 32 OSR = 64 OSR = 128 OSR = 256 OSR = 512 OSR = 1024 OSR = 2048 OSR = 4096 40 20 0 1 2 FIGURE 2-20: 4 8 Gain (V/V) 16 32 120 100 80 60 OSR = 32 OSR = 64 OSR = 128 OSR = 256 OSR = 512 OSR = 1024 OSR = 2048 OSR = 4096 40 20 0 1 2 FIGURE 2-21: DS20005348C-page 12 4 8 Gain (V/V) SNR vs. GAIN. 16 -60 32 16 32 SFDR vs. GAIN. -80 -100 -120 0.001 0.01 0.1 1 10 100 Input Signal Amplitude (mVPK) FIGURE 2-23: Amplitude. SINAD vs. GAIN. 4 8 Gain (V/V) GAIN = 1x GAIN = 2x GAIN = 4x GAIN = 8x GAIN = 16x GAIN = 32x -40 Signal-to-Noise and Distortion Ratio (dB) Signal-to-Noise and Distortion Ratio (dB) OSR = 32 OSR = 64 OSR = 128 OSR = 256 OSR = 512 OSR = 1024 OSR = 2048 OSR = 4096 60 0 1 Signal-to-Noise Ratio (dB) 80 1000 THD vs. Input Signal 100 80 60 40 GAIN = 1x GAIN = 2x GAIN = 4x GAIN = 8x GAIN = 16x GAIN = 32x 20 0 -20 0.001 0.01 0.1 1 10 100 Input Signal Amplitude (mVPK) FIGURE 2-24: Amplitude. 1000 SINAD vs. Input Signal  2014-2020 Microchip Technology Inc. MCP3912 Unless otherwise indicated, AVDD = 3V; DVDD = 3V; TA = +25°C; MCLK = 4 MHz; PRESCALE = 1; OSR = 256; GAIN = 1; Dithering = Maximum; VIN = -0.5 dBFS @ 60 Hz on all channels; VREFEXT = 0; CLKEXT = 1; BOOST[1:0] = 10. Note: 80 60 40 GAIN = 1x GAIN = 2x GAIN = 4x GAIN = 8x GAIN = 16x GAIN = 32x 20 0 -20 0.001 0.01 0.1 1 10 100 Input Signal Amplitude (mVPK) FIGURE 2-25: Amplitude. 1000 Total Harmonic Distortion (dB) Signal-to-Noise Ratio (dB) 100 -40 -60 -80 -120 -50 -25 0 FIGURE 2-28: SNR vs. Input Signal 25 50 75 Temperature (°C) 100 125 THD vs. Temperature. 120 100 80 GAIN = 1x GAIN = 2x GAIN = 4x GAIN = 8x GAIN = 16x GAIN = 32x 60 40 20 0 0.001 0.01 0.1 1 10 100 Input Signal Amplitude (mVPK) FIGURE 2-26: Amplitude. OSR = 32 OSR = 64 OSR = 128 OSR = 256 OSR = 512 OSR = 1024 OSR = 2048 OSR = 4096 100 80 60 90 80 70 60 50 40 20 0 GAIN = 1x GAIN = 2x GAIN = 4x GAIN = 8x GAIN = 16x GAIN = 32x 40 30 20 10 0 1000 SFDR vs. Input Signal 120 Signal-to-Noise and Distortion Ratio (dB) 100 -50 -25 0 FIGURE 2-29: 25 50 75 Temperature (°C) 100 125 SINAD vs. Temperature. 100 90 Signal-to-Noise Ratio (dB) SpuriousFree Dyanmic Range (dBFS) GAIN = 1x GAIN = 2x GAIN = 4x GAIN = 8x GAIN = 16x GAIN = 32x -20 -100 140 Signal-to-Noise and Distortion Ratio (dB) 0 80 70 60 50 GAIN = 1x GAIN = 2x GAIN = 4x GAIN = 8x GAIN = 16x GAIN = 32x 40 30 20 10 0 10 FIGURE 2-27: 100 1000 10000 Signal Frequency (Hz) 100000 SINAD vs. Input Frequency.  2014-2020 Microchip Technology Inc. -50 -25 FIGURE 2-30: 0 25 50 75 Temperature (°C) 100 125 SNR vs. Temperature. DS20005348C-page 13 MCP3912 Unless otherwise indicated, AVDD = 3V; DVDD = 3V; TA = +25°C; MCLK = 4 MHz; PRESCALE = 1; OSR = 256; GAIN = 1; Dithering = Maximum; VIN = -0.5 dBFS @ 60 Hz on all channels; VREFEXT = 0; CLKEXT = 1; BOOST[1:0] = 10. Note: 1000 SpuriousFree Dyanmic Range (dBFS) 120 Channel Offset (µV) 100 80 60 GAIN = 1x GAIN = 2x GAIN = 4x GAIN = 8x GAIN = 16x GAIN = 32x 40 20 0 800 Channel 0 600 Channel 1 400 Channel 2 200 Channel 3 0 -200 -400 -600 -800 -1000 -50 -25 0 FIGURE 2-31: 25 50 75 Temperature (°C) 100 125 SFDR vs. Temperature. -40 -20 0 FIGURE 2-34: vs. Temperature. 20 40 60 80 Temperature (°C) 100 120 Channel Offset Matching 0 28LD SSOP 7 -40 -60 -80 -100 -120 5 3 1 -1 -3 -5 -140 1 2 Measured Channel* 3 -40 * All other channels at maximum amplitude VIN = 600 mVPK @ 60 Hz FIGURE 2-32: Channel. Crosstalk vs. Measured 1000 GAIN = 1x GAIN = 2x GAIN = 4x GAIN = 8x GAIN = 16x GAIN = 32x 800 600 400 200 0 -200 -400 -600 -800 -20 0 20 40 60 80 Temperature (°C) FIGURE 2-35: vs. Gain. Internal Voltage Reference (V) 0 Offset (µV) GAIN = 1x GAIN = 2x GAIN = 4x GAIN = 8x GAIN = 16x GAIN = 32x 9 28LD QFN Gain Error (%) Crosstalk (dB) -20 100 120 Gain Error vs. Temperature 1.2 1.199 1.198 1.197 -1000 -40 -20 0 FIGURE 2-33: Gain. DS20005348C-page 14 20 40 60 80 Temperature (°C) 100 120 Offset vs. Temperature vs. -40 -20 0 FIGURE 2-36: vs. Temperature. 20 40 60 80 Temperature (°C) 100 120 140 Internal Voltage Reference  2014-2020 Microchip Technology Inc. MCP3912 Unless otherwise indicated, AVDD = 3V; DVDD = 3V; TA = +25°C; MCLK = 4 MHz; PRESCALE = 1; OSR = 256; GAIN = 1; Dithering = Maximum; VIN = -0.5 dBFS @ 60 Hz on all channels; VREFEXT = 0; CLKEXT = 1; BOOST[1:0] = 10. 1.1969 14 1.1968 12 1.1967 AIDD Boost =0.5x AIDD Boost =0.66x AIDD Boost =1x AIDD Boost =2x DIDD 10 1.1966 IDD (mA) Internal Voltage Reference (V) Note: 1.1965 1.1964 8 6 1.1963 4 1.1962 2 1.1961 2.5 2.6 2.7 2.8 2.9 3 3.1 3.2 3.3 3.4 3.5 3.6 AVDD (V) FIGURE 2-37: Internal Voltage Reference vs. Supply Voltage. 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 MCLK (MHz) FIGURE 2-40: Operating Current vs. MCLK Frequency vs. BOOST, VDD = 3V. Integral NonLinearity Error (ppm) 10 8 6 4 2 0 -2 -4 -6 -8 -10 -0.6 -0.4 -0.2 0.0 0.2 Input Voltage (V) 0.4 0.6 FIGURE 2-38: Integral Nonlinearity (Dithering Maximum). Integral NonLinearity Error (ppm) 10 8 6 4 2 0 -2 -4 -6 -8 -10 -0.6 -0.4 FIGURE 2-39: (Dithering Off). -0.2 0.0 0.2 Input Voltage (V) 0.4 0.6 Integral Nonlinearity  2014-2020 Microchip Technology Inc. DS20005348C-page 15 MCP3912 NOTES: DS20005348C-page 16  2014-2020 Microchip Technology Inc. MCP3912 3.0 PIN DESCRIPTION Descriptions of the pins are listed in Table 3-1. TABLE 3-1: FOUR-CHANNEL MCP3912 PIN FUNCTION TABLE MCP3912 SSOP MCP3912 QFN Symbol 1 25, 11 AVDD Analog Power Supply Pin 2 27 CH0+ Noninverting Analog Input Pin for Channel 0 3 28 CH0- Inverting Analog Input Pin for Channel 0 4 29 CH1- Inverting Analog Input Pin for Channel 1 5 2 CH1+ Noninverting Analog Input Pin for Channel 1 6 3 CH2+ Noninverting Analog Input Pin for Channel 2 7 4 CH2- Inverting Analog Input Pin for Channel 2 8 5 CH3- Inverting Analog Input Pin for Channel 3 9 6 CH3+ Noninverting Analog Input Pin for Channel 3 10, 11, 12, 13, 19 7 NC 14 8 REFIN+/OUT 15 9 REFIN- Function No Connect (for better EMI results, connect to AGND) Noninverting Voltage Reference Input and Internal Reference Output Pin Inverting Voltage Reference Input Pin 16 10, 26 AGND Analog Ground Pin, Return Path for Internal Analog Circuitry 17, 20 13, 15, 23 DGND Digital Ground Pin, Return Path for Internal Digital Circuitry 18 14 DR 21 16 OSC1/CLKI 22 17 OSC2 23 18 CS 24 19 SCK 25 20 SDO Serial Interface Data Output Pin 26 21 SDI Serial Interface Data Input Pin 27 22 RESET Master Reset Logic Input Pin 28 12, 14 DVDD — 29 EP  2014-2020 Microchip Technology Inc. Data Ready Signal Output Pin Oscillator Crystal Connection Pin or External Clock Input Pin Oscillator Crystal Connection Pin Serial Interface Chip Select Input Pin Serial Interface Clock Input Pin for SPI Digital Power Supply Pin Exposed Thermal Pad, Must be connected to AGND or floating DS20005348C-page 17 MCP3912 3.1 Analog Power Supply (AVDD) AVDD is the power supply voltage for the analog circuitry within the MCP3912. It is distributed on several pins (pins 11 and 25 in the 28-lead QFN package, one pin only in the 28-lead SSOP package). For optimal performance, connect these pins together using a star connection and connect the appropriate bypass capacitors (typically a 10 µF in parallel with a 0.1 µF ceramic). AVDD should be maintained between 2.7V and 3.6V for specified operation. To ensure proper functionality of the device, at least one of these pins must be properly connected. To ensure optimal performance of the device, all the pins must be properly connected. If any of these pins are left floating, the accuracy and noise specifications are not ensured. 3.2 ADC Differential Analog Inputs (CHn+/CHn-) The CHn+/- pins (n comprised between 0 and 3) are the four fully-differential analog voltage inputs for the Delta-Sigma ADCs. The linear and specified region of the channels is dependent on the PGA gain. This region corresponds to a differential voltage range of ±600 mV/GAIN with VREF = 1.2V. The maximum absolute voltage, with respect to AGND, for each CHn+/- input pin is ±1V with no distortion, and ±2V with no breaking after continuous voltage. This maximum absolute voltage is not proportional to the VREF voltage. 3.3 Noninverting Reference Input, Internal Reference Output (REFIN+/OUT) This pin is the noninverting side of the differential voltage reference input for all ADCs or the internal voltage reference output. When VREFEXT = 1, an external voltage reference source can be used and the internal voltage reference is disabled. When using an external differential voltage reference, it should be connected to its VREF+ pin. When using an external single-ended reference, it should be connected to this pin. When VREFEXT = 0, the internal voltage reference is enabled and connected to this pin through a switch. This voltage reference has minimal drive capability and thus needs proper buffering and bypass capacitances (a 0.1 µF ceramic capacitor is sufficient in most cases) if used as a voltage source. DS20005348C-page 18 If the voltage reference is only used as an internal VREF, adding bypass capacitance on REFIN+/OUT is not necessary for keeping ADC accuracy. To avoid EMI/EMC susceptibility issues due to the antenna, created by the REFIN+/OUT pin, if left floating, a minimal 0.1 µF ceramic capacitance can be connected. 3.4 Inverting Reference Input (REFIN-) This pin is the inverting side of the differential voltage reference input for all ADCs. When using an external differential voltage reference, it should be connected to its VREF- pin. When using an external single-ended voltage reference, or when VREFEXT = 0 (default) and using the internal voltage reference, the pin should be directly connected to AGND. 3.5 Analog Ground (AGND) AGND is the ground reference voltage for the analog circuitry within the MCP3912. It is distributed on several pins (pins 10 and 26 in the 28-lead QFN package, one pin only in the 28-lead SSOP package). For optimal performance, it is recommended to connect these pins together using a star connection, and to connect them to the same ground node voltage as DGND with a star connection. At least one of these pins needs to be properly connected to ensure proper functionality of the device. All of these pins need to be properly connected to ensure optimal performance of the device. If any of these pins are left floating, the accuracy and noise specifications are not ensured. If an analog ground plane is available, it is recommended that these pins be tied to this plane of the PCB. This plane should also reference all other analog circuitry in the system. 3.6 Digital Ground (DGND) DGND is the ground reference voltage for the digital circuitry within the MCP3912. It is distributed on several pins (pins 13, 15 and 23 in the 28-lead QFN package, two pins only in the 28-lead SSOP package). For optimal performance, connect these pins together using a star connection and connect them to the same ground node voltage as AGND with a star connection. At least one of these pins needs to be properly connected to ensure proper functionality of the device. All of these pins need to be properly connected to ensure optimal performance of the device. If any of these pins are left floating, the accuracy and noise specifications are not ensured. If a digital ground plane is available, it is recommended that these pins be tied to this plane of the Printed Circuit Board (PCB). This plane should also reference all other digital circuitry in the system.  2014-2020 Microchip Technology Inc. MCP3912 3.7 Data Ready Output (DR) The Data Ready pin indicates if a new conversion result is ready to be read. The default state of this pin is logic high when DR_HIZ = 1 and is high-impedance when DR_HIZ = 0 (default). After each conversion is finished, a logic low pulse will take place on the Data Ready pin to indicate the conversion result is ready as an interrupt. This pulse is synchronous with the master clock and has a defined and constant width. The Data Ready pin is independent of the SPI interface and acts like an interrupt output. The Data Ready pin state is not latched, and the pulse width (and period) are both determined by the MCLK frequency, oversampling rate and internal clock prescale settings. The data ready pulse width is equal to half a DMCLK period and the frequency of the pulses is equal to DRCLK (see Figure 1-3). Note: 3.8 This pin should not be left floating when the DR_HIZ bit is low; a 100 k pull-up resistor connected to DVDD is recommended. Oscillator and Master Clock Input Pin (OSC1/CLKI) OSC1/CLKI and OSC2 provide the master clock for the device. When CLKEXT = 0, a resonant crystal or clock source with a similar sinusoidal waveform must be placed across the OSC1 and OSC2 pins to ensure proper operation. The typical clock frequency specified is 4 MHz. For proper operation and for optimizing ADC accuracy, AMCLK should be limited to the maximum frequency defined in Table 5-2 for the function of the BOOST and PGA setting chosen. MCLK can take larger values as long as the prescaler settings (PRE[1:0]) limit AMCLK = MCLK/PRESCALE in the defined range in Table 5-2. Appropriate load capacitance should be connected to these pins for proper operation. Note: 3.9 When CLKEXT = 1, the crystal oscillator is disabled. OSC1 becomes the master clock input, CLKI, a direct path for an external clock source. One example would be a clock source generated by an MCU. Crystal Oscillator (OSC2) When CLKEXT = 0, a resonant crystal or clock source with a similar sinusoidal waveform must be placed across the OSC1 and OSC2 pins to ensure proper operation. Appropriate load capacitance should be connected to these pins for proper operation. 3.10 Chip Select (CS) This pin is the Serial Peripheral Interface (SPI) Chip Select that enables serial communication. When this pin is logic high, no communication can take place. A chip select falling edge initiates serial communication and a chip select rising edge terminates the communication. No communication can take place, even when CS is logic low if RESET is also logic low. This input is Schmitt triggered. 3.11 Serial Data Clock (SCK) This is the Serial Data Clock pin for SPI communication. Data are clocked into the device on the rising edge of SCK. Data are clocked out of the device on the falling edge of SCK. The MCP3912 SPI interface is compatible with SPI 0,0 and 1,1 modes. SPI modes can be changed during a CS high time. The maximum clock speed specified is 20 MHz. SCK and MCLK are two different and asynchronous clocks; SCK is only required when a communication happens, while MCLK is continuously required when the part is converting analog inputs. This input is Schmitt triggered. 3.12 Serial Data Output (SDO) This is the SPI Data Output pin. Data are clocked out of the device on the falling edge of SCK. This pin remains in a high-impedance state during the command byte. It also stays high-impedance during the entire communication for WRITE commands when the CS pin is logic high or when the RESET pin is logic low. This pin is active only when a READ command is processed. The interface is half-duplex (inputs and outputs do not happen at the same time). 3.13 Serial Data Input (SDI) This is the SPI Data Input pin. Data are clocked into the device on the rising edge of SCK. When CS is logic low, this pin is used to communicate with a series of 8-bit commands. The interface is half-duplex (inputs and outputs do not happen at the same time). Each communication starts with a chip select falling edge followed by an 8-bit command word entered through the SDI pin. Each command is either a read or a write command. Toggling SDI after a read command or when CS is logic high has no effect. This input is Schmitt-triggered. When CLKEXT = 1, this pin should be connected to DGND at all times (an internal pull-down operates this function if the pin is left floating).  2014-2020 Microchip Technology Inc. DS20005348C-page 19 MCP3912 3.14 Master Reset (RESET) This pin is active-low and places the entire chip in a Reset state when active. When RESET is logic low, all registers are reset to their default value, no communication can take place and no clock is distributed inside the part, except in the input structure if MCLK is applied (if MCLK is Idle, then no clock is distributed). This state is equivalent to a Power-on Reset (POR) state. Since the default state of the ADCs is on, the analog power consumption when RESET is logic low is equivalent to when RESET is logic high. Only the digital power consumption is largely reduced, because this current consumption is essentially dynamic and is reduced drastically when there is no clock running. All the analog biases are enabled during a Reset, so that the part is fully operational just after a RESET rising edge if MCLK is applied when RESET is logic low. If MCLK is not applied, there is a time after a Hard Reset when the conversion may not accurately correspond to the start-up of the input structure. 3.15 Digital Power Supply (DVDD) DVDD is the power supply voltage for the digital circuitry within the MCP3912. It is distributed on several pins (pins 12 and 24 in the 28-lead QFN package, one pin only in the 28-lead SSOP package). For optimal performance, it is recommended to connect these pins together using a star connection and to connect appropriate bypass capacitors (typically a 10 µF in parallel with a 0.1 µF ceramic). DVDD should be maintained between 2.7V and 3.6V for specified operation. At least one of these pins needs to be properly connected to ensure proper functionality of the device. All of these pins need to be properly connected to ensure optimal performance of the device. If any of these pins are left floating, the accuracy and noise specifications are not ensured. 3.16 Exposed Thermal Pad This pin must be connected to AGND or left floating for proper operation. Connecting it to AGND is preferable for lowest noise performance and best thermal behavior. This input is Schmitt triggered. DS20005348C-page 20  2014-2020 Microchip Technology Inc. MCP3912 4.0 TERMINOLOGY AND FORMULAS 4.1 This section defines the terms and formulas used throughout this data sheet. The following terms are defined: • • • • • • • • • • • • • • • • • • • • • • • MCLK – Master Clock AMCLK – Analog Master Clock DMCLK – Digital Master Clock DRCLK – Data Rate Clock OSR – Oversampling Ratio Offset Error Gain Error Integral Nonlinearity Error Signal-to-Noise Ratio (SNR) Signal-to-Noise Ratio and Distortion (SINAD) Total Harmonic Distortion (THD) Spurious-Free Dynamic Range (SFDR) MCP3912 Delta-Sigma Architecture Idle Tones Dithering Crosstalk PSRR CMRR ADC Reset Mode Hard Reset Mode (RESET = 0) ADC Shutdown Mode Full Shutdown Mode Measurement Error OUT OSC1 OSC2 This is the fastest clock present on the device. This is the frequency of the crystal placed at the OSC1/OSC2 inputs when CLKEXT = 0 or the frequency of the clock input at the OSC1/CLKI when CLKEXT = 1. See Figure 4-1. 4.2 AMCLK – Analog Master Clock AMCLK is the clock frequency that is present on the analog portion of the device after prescaling has occurred via the CONFIG0 PRE[1:0] register bits (see Equation 4-1). The analog portion includes the PGAs and the Delta-Sigma modulators. EQUATION 4-1: MCLK AMCLK = ------------------------------PRESCALE TABLE 4-1: MCP3912 OVERSAMPLING RATIO SETTINGS CONFIG0 Analog Master Clock Prescale PRE[1:0] CLKEXT 1 MCLK – Master Clock 0 0 AMCLK = MCLK/1 (default) 0 1 AMCLK = MCLK/2 1 0 AMCLK = MCLK/4 1 1 AMCLK = MCLK/8 PRE[1:0] MCLK 1/PRESCALE OSR[2:0] AMCLK 1/4 DMCLK 1/OSR DRCLK 0 Xtal Oscillator FIGURE 4-1: Multiplexer Clock Divider Clock Divider Clock Divider Clock Sub-Circuitry.  2014-2020 Microchip Technology Inc. DS20005348C-page 21 MCP3912 4.3 DMCLK – Digital Master Clock This is the clock frequency that is present on the digital portion of the device after prescaling and division by four (Equation 4-2). This is also the sampling frequency, which is the rate at which the modulator outputs are refreshed. Each period of this clock corresponds to one sample and one modulator output. See Figure 4-1. EQUATION 4-2: AMCLK MCLK DMCLK = --------------------- = ---------------------------------------4 4  PRESCALE 4.4 DRCLK – Data Rate Clock This is the output data rate (i.e., the rate at which the ADCs output new data). New data are signaled by a data ready pulse on the DR pin. This data rate is dependent on the OSR and the prescaler with the formula in Equation 4-3. EQUATION 4-3: DMCLK AMCLK MCLK DRCLK = ---------------------- = --------------------- = ----------------------------------------------------------OSR 4  OSR 4  OSR  PRESCALE Since this is the output data rate, and because the decimation filter is a SINC (or notch) filter, there is a notch in the filter transfer function at each integer multiple of this rate. Table 4-2 describes the various combinations of OSR and PRESCALE, and their associated AMCLK, DMCLK and DRCLK rates. DS20005348C-page 22  2014-2020 Microchip Technology Inc. MCP3912 TABLE 4-2: DEVICE DATA RATES IN FUNCTION OF MCLK, OSR AND PRESCALE, MCLK = 4 MHz PRE[1:0] OSR[2:0] OSR AMCLK DMCLK DRCLK DRCLK (ksps) SINAD (dB)(1) ENOB from SINAD (bits)(1) 1 1 1 1 1 4096 MCLK/8 MCLK/32 MCLK/131072 .035 102.5 16.7 1 1 1 1 1 2048 MCLK/8 MCLK/32 MCLK/65536 .061 100 16.3 1 1 1 1 1 1024 MCLK/8 MCLK/32 MCLK/32768 .122 97 15.8 1 1 1 1 1 512 MCLK/8 MCLK/32 MCLK/16384 .244 96 15.6 1 1 0 1 1 256 MCLK/8 MCLK/32 MCLK/8192 0.488 94 15.3 1 1 0 1 0 128 MCLK/8 MCLK/32 MCLK/4096 0.976 90 14.7 1 1 0 0 1 64 MCLK/8 MCLK/32 MCLK/2048 1.95 83 13.5 1 1 0 0 0 32 MCLK/8 MCLK/32 MCLK/1024 3.9 70 11.3 1 0 1 1 1 4096 MCLK/4 MCLK/16 MCLK/65536 .061 102.5 16.7 1 0 1 1 1 2048 MCLK/4 MCLK/16 MCLK/32768 .122 100 16.3 1 0 1 1 1 1024 MCLK/4 MCLK/16 MCLK/16384 .244 97 15.8 1 0 1 1 1 512 MCLK/4 MCLK/16 MCLK/8192 .488 96 15.6 1 0 0 1 1 256 MCLK/4 MCLK/16 MCLK/4096 0.976 94 15.3 1 0 0 1 0 128 MCLK/4 MCLK/16 MCLK/2048 1.95 90 14.7 1 0 0 0 1 64 MCLK/4 MCLK/16 MCLK/1024 3.9 83 13.5 1 0 0 0 0 32 MCLK/4 MCLK/16 MCLK/512 7.8125 70 11.3 0 1 1 1 1 4096 MCLK/2 MCLK/8 MCLK/32768 .122 102.5 16.7 0 1 1 1 1 2048 MCLK/2 MCLK/8 MCLK/16384 .244 100 16.3 0 1 1 1 1 1024 MCLK/2 MCLK/8 MCLK/8192 .488 97 15.8 0 1 1 1 1 512 MCLK/2 MCLK/8 MCLK/4096 .976 96 15.6 0 1 0 1 1 256 MCLK/2 MCLK/8 MCLK/2048 1.95 94 15.3 0 1 0 1 0 128 MCLK/2 MCLK/8 MCLK/1024 3.9 90 14.7 0 1 0 0 1 64 MCLK/2 MCLK/8 MCLK/512 7.8125 83 13.5 0 1 0 0 0 32 MCLK/2 MCLK/8 MCLK/256 15.625 70 11.3 0 0 1 1 1 4096 MCLK MCLK/4 MCLK/16384 .244 102.5 16.7 0 0 1 1 0 2048 MCLK MCLK/4 MCLK/8192 .488 100 16.3 0 0 1 0 1 1024 MCLK MCLK/4 MCLK/4096 .976 97 15.8 0 0 1 0 0 512 MCLK MCLK/4 MCLK/2048 1.95 96 15.6 0 0 0 1 1 256 MCLK MCLK/4 MCLK/1024 3.9 94 15.3 0 0 0 1 0 128 MCLK MCLK/4 MCLK/512 7.8125 90 14.7 0 0 0 0 1 64 MCLK MCLK/4 MCLK/256 15.625 83 13.5 0 0 0 0 0 32 MCLK MCLK/4 MCLK/128 31.25 70 11.3 Note 1: For OSR = 32 and 64, DITHER = None. For OSR = 128 and higher, DITHER = Maximum. The SINAD values are given from GAIN = 1.  2014-2020 Microchip Technology Inc. DS20005348C-page 23 MCP3912 4.5 OSR – Oversampling Ratio 4.8 Integral Nonlinearity Error This is the ratio of the sampling frequency to the output data rate; OSR = DMCLK/DRCLK. The default OSR[2:0] is 256, or with MCLK = 4 MHz, PRESCALE = 1, AMCLK = 4 MHz, fS = 1 MHz and fD = 3.90625 ksps. The OSR[2:0] bits in Table 4-3 in the CONFIG0 register are used to change the Oversampling Ratio (OSR). Integral nonlinearity error is the maximum deviation of an ADC transition point from the corresponding point of an ideal transfer function, with the offset and gain errors removed or with the end points equal to zero. TABLE 4-3: 4.9 MCP3912 OVERSAMPLING RATIO SETTINGS Oversampling Ratio OSR OSR[2:0] 4.6 0 0 0 32 0 0 1 64 0 1 0 128 0 1 1 256 (Default) 1 0 0 512 1 0 1 1024 1 1 0 2048 1 1 1 4096 Offset Error This is the error induced by the ADC when the inputs are shorted together (VIN = 0V). The specification incorporates both PGA and ADC offset contributions. This error varies with PGA and OSR settings. The offset is different on each channel and varies from chipto-chip. The offset is specified in µV. The offset error can be digitally compensated independently on each channel through the OFFCAL_CHn registers with a 24-bit Calibration Word. The offset on the MCP3912 has a low-temperature coefficient. It is the maximum remaining error after calibration of offset and gain errors for a DC input signal. Signal-to-Noise Ratio (SNR) For the MCP3912 ADCs, the Signal-to-Noise ratio is a ratio of the output fundamental signal power to the noise power (not including the harmonics of the signal) when the input is a sine wave at a predetermined frequency (see Equation 4-4). It is measured in dB. Usually, only the maximum Signal-to-Noise ratio is specified. The SNR figure depends mainly on the OSR and DITHER settings of the device. EQUATION 4-4: SignalPower SNR  dB  = 10 log  ---------------------------------- NoisePower 4.10 Signal-to-Noise Ratio and Distortion (SINAD) The most important Figure of Merit for analog performance of the ADCs present on the MCP3912 is the Signal-to-Noise and Distortion (SINAD) specification. The Signal-to-Noise and Distortion ratio is similar to Signal-to-Noise ratio, with the exception that you must include the harmonic’s power in the noise power calculation (see Equation 4-5). The SINAD specification depends mainly on the OSR and DITHER settings. EQUATION 4-5: 4.7 Gain Error This is the error induced by the ADC on the slope of the transfer function. It is the deviation expressed in a percentage, compared to the ideal transfer function defined in Equation 5-3. The specification incorporates both PGA and ADC gain error contributions, but not the VREF contribution (it is measured with an external VREF). This error varies with PGA and OSR settings. The gain error can be digitally compensated independently on each channel through the GAINCAL_CHn registers with a 24-bit Calibration Word. SIGNAL-TO-NOISE RATIO SINAD EQUATION SignalPower SINAD  dB  = 10 log  --------------------------------------------------------------------- Noise + HarmonicsPower The calculated combination of SNR and THD per the following formula also yields SINAD (see Equation 4-6). EQUATION 4-6: SINAD, THD AND SNR RELATIONSHIP SINAD  dB  = 10 log 10  SNR -  ---------10  + 10 THD –  --------------10  The gain error on the MCP3912 has a low-temperature coefficient. DS20005348C-page 24  2014-2020 Microchip Technology Inc. MCP3912 4.11 Total Harmonic Distortion (THD) The Total Harmonic Distortion is the ratio of the output harmonics power to the fundamental signal power for a sine wave input and is defined in Equation 4-7. EQUATION 4-7: HarmonicsPower THD  dB  = 10 log  -----------------------------------------------------  FundamentalPower The THD calculation includes the first 35 harmonics for the MCP3912 specifications. The THD is usually measured only with respect to the ten first harmonics, which leads artificially to better figures. THD is sometimes expressed in a percentage. Equation 4-8 converts the THD in percentages. EQUATION 4-8: THD  %  = 100  10 THD  dB  -----------------------20 This specification depends mainly on the DITHER setting. 4.12 Spurious-Free Dynamic Range (SFDR) Spurious-Free Dynamic Range, or SFDR, is the ratio between the output power of the fundamental and the highest spur in the frequency spectrum (see Equation 4-9). The spur frequency is not necessarily a harmonic of the fundamental, even though it is usually the case. This figure represents the dynamic range of the ADC when a full-scale signal is used at the input. This specification depends mainly on the DITHER setting. EQUATION 4-9: FundamentalPower SFDR  dB  = 10 log  -----------------------------------------------------  HighestSpurPower  4.13 MCP3912 Delta-Sigma Architecture The MCP3912 incorporates four Delta-Sigma ADCs with a multibit architecture. A Delta-Sigma ADC is an oversampling converter that incorporates a built-in modulator, which digitizes the quantity of charges integrated by the modulator loop (see Figure 5-1). The quantizer is the block that is performing the Analog-to-Digital conversion. The quantizer is typically 1 bit, or a simple comparator, which helps maintain the linearity performance of the ADC (the DAC structure is, in this case, inherently linear).  2014-2020 Microchip Technology Inc. Multibit quantizers help to lower the quantization error (the error fed back in the loop can be very large with 1-bit quantizers) without changing the order of the modulator or the OSR, which leads to better SNR figures. However, typically the linearity of such architectures is more difficult to achieve since the DAC linearity is as difficult to attain and its linearity limits the THD of such ADCs. The quantizer present in each ADC channel in the MCP3912 is a Flash ADC, composed of four comparators, arranged with equally spaced thresholds and a thermometer coding. The MCP3912 also includes proprietary five-level DAC architecture that is inherently linear for improved THD figures. 4.14 Idle Tones A Delta-Sigma converter is an integrating converter. It also has a finite quantization step (LSB) that can be detected by its quantizer. A DC input voltage that is below the quantization step should only provide an all zeros result, since the input is not large enough to be detected. As an integrating device, any Delta-Sigma ADC will show Idle tones. This means that the output will have spurs in the frequency content that depend on the ratio between quantization step voltage and the input voltage. These spurs are the result of the integrated subquantization step inputs that will eventually cross the quantization steps after a long enough integration. This will induce an AC frequency at the output of the ADC and can be shown in the ADC output spectrum. These Idle tones are residues that are inherent to the quantization process and the fact that the converter is integrating at all times without being reset. They are residues of the finite resolution of the conversion process. They are very difficult to attenuate and they are heavily signal-dependent. They can degrade the SFDR and THD of the converter, even for DC inputs. They can be localized in the baseband of the converter and are thus difficult to filter from the actual input signal. For power metering applications, Idle tones can be very disturbing because energy can be detected, even at the 50 or 60 Hz frequency, depending on the DC offset of the ADCs, while no power is really present at the inputs. The only practical way to suppress or attenuate the Idle tones phenomenon is to apply dithering to the ADC. The amplitudes of the Idle tones are a function of the order of the modulator, the OSR and the number of levels in the quantizer of the modulator. A higher order, a higher OSR or a higher number of levels for the quantizer will attenuate the amplitudes of the Idle tones. DS20005348C-page 25 MCP3912 4.15 Dithering In order to suppress or attenuate the Idle tones present in any Delta-Sigma ADCs, dithering can be applied to the ADC. Dithering is the process of adding an error to the ADC feedback loop in order to “decorrelate” the outputs and “break” the Idle tone’s behavior. Usually, a random, or pseudorandom generator, adds an analog or digital error to the feedback loop of the Delta-Sigma ADC in order to ensure that no tonal behavior can happen at its outputs. This error is filtered by the feedback loop and typically has a zero average value, so that the converter static transfer function is not disturbed by the dithering process. However, the dithering process slightly increases the noise floor (it adds noise to the part) while reducing its tonal behavior and thus improving SFDR and THD. The dithering process scrambles the Idle tones into baseband white noise and ensures that dynamic specs (SNR, SINAD, THD, SFDR) are less signal-dependent. The MCP3912 incorporates a proprietary dithering algorithm on all ADCs in order to remove Idle tones and improve THD, which is crucial for power metering applications. 4.16 Crosstalk Crosstalk is defined as the perturbation caused on one ADC channel by all the other ADC channels present in the chip. It is a measurement of the isolation between each channel present in the chip. The crosstalk for Channel 0 is then calculated with the formula in Equation 4-10. EQUATION 4-10:  CH0Power CTalk  dB  = 10 log  ---------------------------------  CHnPower The crosstalk depends slightly on the position of the channels in the MCP3912 device. This dependency is shown in the Figure 2-32, where the inner channels show more crosstalk than the outer channels since they are located closer to the perturbation sources. The outer channels have the preferred locations to minimize crosstalk. 4.17 This is the ratio between a change in the power supply voltage and the ADC output codes. It measures the influence of the power supply voltage on the ADC outputs. The PSRR specification can be DC (the power supply is taking multiple DC values) or AC (the power supply is a sine wave at a certain frequency with a certain Common-mode). In AC, the amplitude of the sine wave represents the change in the power supply; it is defined in Equation 4-11. EQUATION 4-11: This measurement is a two-step procedure: 1. 2. Measure one ADC input with no perturbation on the other ADC (ADC inputs shorted). Measure the same ADC input with a perturbation sine wave signal on all the other ADCs at a certain predefined frequency. Crosstalk is the ratio between the output power of the ADC when the perturbation is and is not present, divided by the power of the perturbation signal. A lower crosstalk value implies more independence and isolation between the channels. The measurement of this signal is performed under the default conditions of MCLK = 4 MHz: • • • • GAIN = 1 PRESCALE = 1 OSR = 256 MCLK = 4 MHz Step 1 for CH0 Crosstalk Measurement: • CH0+ = CH0- = AGND • CHn+ = CHn- = AGND n comprised between 1 and 3 Step 2 for CH0 Crosstalk Measurement: • CH0+ = CH0- = AGND • CHn+ – CHn- = 1.2VP-P @ 50/60 Hz (full-scale sine wave), n comprised between 1 and 3 DS20005348C-page 26 PSRR  VOUT PSRR  dB  = 20 log  -------------------  AV DD Where: VOUT is the equivalent input voltage that the output code translates to with the ADC transfer function. In the MCP3912 specification for DC PSRR, AVDD varies from 2.7V to 3.6V; for AC PSRR, a 50/60 Hz sine wave is chosen centered around 3.0V with a maximum 300 mV amplitude. The PSRR specification is measured with AVDD = DVDD. 4.18 CMRR CMRR is the ratio between a change in the Common-mode input voltage and the ADC output codes. It measures the influence of the Common-mode input voltage on the ADC outputs. The CMRR specification can be DC (the Common-mode input voltage is taking multiple DC values) or AC (the Common-mode input voltage is a sine wave at a certain frequency with a certain Common-mode). In AC, the amplitude of the sine wave represents the change in the power supply; it is defined in Equation 4-12.  2014-2020 Microchip Technology Inc. MCP3912 EQUATION 4-12:  V OUT CMRR  dB  = 20 log  -----------------   VCM  Where: VCM = (CHn+ + CHn-)/2 is the Common-mode input voltage and VOUT is the equivalent input voltage that the output code translates to with the ADC transfer function. In the MCP3912 specification, VCM varies from -1V to +1V. 4.19 ADC Reset Mode ADC Reset mode (also called Soft Reset mode) can only be entered through setting the RESET[3:0] bits high in the Configuration register. This mode is defined as the condition where the converters are active, but their output is forced to zero. The Flash ADC output of the corresponding channel will be reset to its default value (‘0011’) in the MOD register. The ADCs can immediately output meaningful codes after leaving Reset mode (and after the SINC filter settling time). This mode is both entered and exited through bit settings in the Configuration register. Each converter can be placed in Soft Reset mode independently. The Configuration registers are not modified by the Soft Reset mode. A data ready pulse will not be generated by an ADC channel in Reset mode. When an ADC exits ADC Reset mode, any phase delay present before Reset was entered will still be present. If one ADC was not in Reset, the ADC leaving Reset mode will automatically resynchronize the phase delay relative to the other ADC channel per the phase delay register block, and give data ready pulses accordingly. If an ADC is placed in Reset mode while others are converting, it does not shut down the internal clock. When coming out of Reset, it will be automatically resynchronized with the clock, which did not stop during Reset. If all ADCs are in Soft Reset mode, the clock is no longer distributed to the digital core for low-power operation. Once any of the ADCs is back to normal operation, the clock is automatically distributed again. However, when the four channels are in Soft Reset mode, the input structure is still clocking, if MCLK is applied, in order to properly bias the inputs so that no leakage current is observed. If MCLK is not applied, large analog input leakage currents can be observed for highly negative input voltages (typically below -0.6V, referred to AGND).  2014-2020 Microchip Technology Inc. 4.20 Hard Reset Mode (RESET = 0) This mode is only available during a POR or when the RESET pin is pulled logic low. The RESET pin logic low state places the device in Hard Reset mode. In this mode, all internal registers are reset to their default state. The DC biases for the analog blocks are still active (i.e., the MCP3912 is ready to convert). However, this pin clears all conversion data in the ADCs. The comparators’ outputs of all ADCs are forced to their Reset state (‘0011’). The SINC filters are all reset, as well as their double-output buffers. The Hard Reset mode requires a minimum pulse low time (see Section 1.0 “Electrical Characteristics”). During a Hard Reset, no communication with the part is possible. The digital interface is maintained in a Reset state. During this state, the clock, MCLK, can be applied to the part in order to properly bias the input structures of all channels. If not applied, large analog input leakage currents can be observed for highly negative input signals, and after removing the Hard Reset state, a certain start-up time is necessary to bias the input structure properly. During this delay, the ADC conversions can be inaccurate. 4.21 ADC Shutdown Mode ADC Shutdown mode is defined as a state where the converters and their biases are off, consuming only leakage current. When one of the SHUTDOWN[3:0] bits is reset to ‘0’, the analog biases of the corresponding channel will be enabled, as well as the clock and the digital circuitry. The ADC of the corresponding channel will give a data ready after the SINC filter settling time has occurred. However, since the analog biases are not completely settled at the beginning of the conversion, the sampling may not be accurate during about 1 ms (corresponding to the settling time of the biasing in worst-case conditions). In order to ensure accuracy, the data ready pulse within the delay of 1 ms + settling time of the SINC filter should be discarded. Each converter can be placed in Shutdown mode independently. The Configuration registers are not modified by the Shutdown mode. This mode is only available through programming the SHUTDOWN[3:0] bits of the CONFIG1 register. The output data are flushed to all zeros while in ADC Shutdown mode. No data ready pulses are generated by any ADC while in ADC Shutdown mode. DS20005348C-page 27 MCP3912 When an ADC exits ADC Shutdown mode, any phase delay present before shutdown was entered will still be present. If one ADC was not in Shutdown, the ADC leaving Shutdown mode will automatically resynchronize the phase delay, relative to the other ADC channel, per the Phase Delay register block and give data ready pulses accordingly. If an ADC is placed in Shutdown mode while others are converting, it does not shut down the internal clock. When coming back out of Shutdown mode, it will automatically be resynchronized with the clock that did not stop during Reset. If all ADCs are in ADC Shutdown mode, the clock is not distributed to the input structure, or to the digital core, for low-power operation. This can potentially cause high analog input leakage currents at the analog inputs if the input voltage is highly negative (typically below -0.6V, referred to AGND). Once either of the ADCs is back to normal operation, the clock is automatically distributed again. 4.22 Full Shutdown Mode The lowest power consumption can be achieved when SHUTDOWN[3:0] = 1111, VREFEXT = CLKEXT = 1. This mode is called Full Shutdown mode, and no analog circuitry is enabled. In this mode, both AVDD and DVDD POR monitoring are also disabled and no clock is propagated throughout the chip. All ADCs are in Shutdown mode and the internal voltage reference is disabled. This mode does not reset the writable part of the register map to its default values. The clock is no longer distributed to the input structure as well. This can potentially cause high analog input leakage currents at the analog inputs if the input voltage is highly negative (typically below -0.6V, referred to AGND). The only circuit that remains active is the SPI interface, but this circuit does not induce any static power consumption. If SCK is Idle, the only current consumption comes from the leakage currents induced by the transistors. This mode can be used to power down the chip completely and avoid power consumption when there is no data to convert at the analog inputs. Any SCK or MCLK edge occurring while in this mode will induce dynamic power consumption. Once any of the SHUTDOWN[3:0], CLKEXT and VREFEXT bits return to ‘0’, the two POR monitoring blocks are operational, and AVDD and DVDD monitoring can take place. 4.23 Measurement Error The measurement error specification is typically used in power meter applications. This specification is a measurement of the linearity of the active energy of a given power meter across its dynamic range. For this measurement, the goal is to measure the active energy of one phase when the voltage Root Mean Square (RMS) value is fixed and the current RMS value is sweeping across the dynamic range specified by the meter. The measurement error is the nonlinearity error of the energy power across the current dynamic range. It is expressed as a percentage. Equation 4-13 shows the formula that calculates the measurement error: EQUATION 4-13: Measured Active Energy – Active Energy present at inputs Measurement Error  I RMS = --------------------------------------------------------------------------------------------------------------------------------------------  100% Active Energy present at inputs In the present device, the calculation of the active energy is done externally as a post-processing step that typically happens in the microcontroller, considering, for example, the even channels as current channels and the odd channels as voltage channels. The odd channels (voltages) are fed with a full-scale sine wave at 600 mV peak, and are configured with GAIN = 1 and DITHER = Maximum. To obtain the active energy measurement error graphs, the even channels are fed with sine waves with amplitudes that vary from 600 mV peak to 60 µV peak, representing a 10000:1 dynamic range. The offset is removed on both current and voltage channels, and the channels are multiplied together to give instantaneous power. The active energy is calculated by multiplying the current and voltage channel, and averaging the results of this power during 20 seconds to extract the active energy. The sampling frequency is chosen as a multiple integer of line frequency (coherent sampling). Therefore, the calculation does not take into account any residue coming from bad synchronization. The measurement error is a function of IRMS and varies with the OSR, averaging time and MCLK frequency, and is tightly coupled with the noise and linearity specifications. The measurement error is a function of the linearity and THD of the ADCs, while the standard deviation of the measurement error is a function of the noise specification of the ADCs. Overall, the low THD specification enables low measurement error on a very large dynamic range (e.g. 10,000:1). A low noise and high SNR specification enables the decreasing of the measurement time, and therefore, the calibration time, to obtain a reliable measurement error specification. Figure 2-5 shows the typical measurement error curves obtained with the samples acquired by the MCP3912, using the default settings with a 1-point and 2-point calibration. These calibrations are detailed in Section 7.0 “Basic Application Recommendations”. DS20005348C-page 28  2014-2020 Microchip Technology Inc. MCP3912 5.0 DEVICE OVERVIEW 5.1 Analog Inputs (CHn+/-) The MCP3912 analog inputs can be connected directly to current and voltage transducers (such as shunts, current transformers, or Rogowski coils). Each input pin is protected by specialized ESD structures that allow bipolar ±2V continuous voltage, with respect to AGND, to be present at their inputs without the risk of permanent damage. All channels have fully differential voltage inputs for better noise performance. The absolute voltage at each pin, relative to AGND, should be maintained in the ±1V range during operation in order to ensure the specified ADC accuracy. The Common-mode signals should be adapted to respect both the previous conditions and the differential input voltage range. For best performance, the Common-mode signals should be maintained to AGND. Note: 5.2 If the analog inputs are held to a potential of -0.6 to -1V for extended periods of time, MCLK must be present inside the device in order to avoid large leakage currents at the analog inputs. This is true even during Hard Reset mode or the Soft Reset of all ADCs. However, during the Shutdown mode of all the ADCs or POR state, the clock is not distributed inside the circuit. During these states, it is recommended to keep the analog input voltages above -0.6V, referred to AGND, to avoid high analog input leakage currents. TABLE 5-1: PGA CONFIGURATION SETTING Gain PGA_CHn[2:0] The PGA block can be used to amplify very low signals, but the differential input range of the Delta-Sigma modulator must not be exceeded. The PGA on each channel is independent and is controlled by the PGA_CHn[2:0] bits in the GAIN register. Table 5-1 displays the gain settings for the PGA.  2014-2020 Microchip Technology Inc. Gain (dB) VIN = (CHn+) – (CHn-) Differential Input Range (V) 0 0 0 1 0 ±0.6 0 0 1 2 6 ±0.3 0 1 0 4 12 ±0.15 0 1 1 8 18 ±0.075 1 0 0 16 24 ±0.0375 1 0 1 32 30 ±0.01875 Note: 5.3 5.3.1 The two undefined settings are G = 1. This table is defined with VREF = 1.2V. Delta-Sigma Modulator ARCHITECTURE All ADCs are identical in the MCP3912 and they include a proprietary second-order modulator with a multibit 5-level DAC architecture (see Figure 5-1). The quantizer is a Flash ADC composed of four comparators with equally spaced thresholds and a thermometer output coding. The proprietary 5-level architecture ensures minimum quantization noise at the outputs of the modulators without disturbing linearity or inducing additional distortion. The sampling frequency is DMCLK (typically 1 MHz with MCLK = 4 MHz), so the modulators are refreshed at a DMCLK rate. Figure 5-1 represents a simplified block diagram of the Delta-Sigma ADC present on MCP3912. Programmable Gain Amplifiers (PGAs) The four Programmable Gain Amplifiers (PGAs) reside at the front end of each Delta-Sigma ADC. They have two functions: translate the Common-mode voltage of the input from AGND to an internal level between AGND and AVDD, and amplify the input differential signal. The translation of the Common-mode voltage does not change the differential signal, but recenters the Common-mode so that the input signal can be properly amplified. Gain (V/V) Quantizer Loop Filter Differential Voltage Input SecondOrder Integrator Output Bitstream 5-Level Flash ADC DAC MCP3912 Delta-Sigma Modulator FIGURE 5-1: Block Diagram. Simplified Delta-Sigma ADC DS20005348C-page 29 MCP3912 5.3.2 MODULATOR INPUT RANGE AND SATURATION POINT 5.3.3 For a specified voltage reference value of 1.2V, the specified differential input range is ±600 mV. The input range is proportional to VREF and scales according to the VREF voltage. This range ensures the stability of the modulator over amplitude and frequency. Outside of this range, the modulator is still functional; however, its stability is no longer ensured, and therefore, it is not recommended to exceed this limit. The saturation point for the modulator is VREF/1.5, since the transfer function of the ADC includes a gain of 1.5 by default (independent from the PGA setting). See Section 5.5 “ADC Output Coding”). TABLE 5-2: The Delta-Sigma modulators include a programmable biasing circuit in order to further adjust the power consumption to the sampling speed applied through the MCLK. This can be programmed through the BOOST[1:0] bits, which are applied to all channels simultaneously. The maximum achievable analog master clock speed (AMCLK), the maximum sampling frequency (DMCLK) and the maximum achievable data rate (DRCLK) highly depend on BOOST[1:0] and PGA_CHn[2:0] settings. Table 5-2 specifies the maximum AMCLK possible to keep optimal accuracy in the function of BOOST[1:0] and PGA_CHn[2:0] settings. MAXIMUM AMCLK LIMITS AS A FUNCTION OF BOOST AND PGA GAIN VDD = 3.0V to 3.6V, TA from -40°C to +125°C Conditions Boost Gain BOOST SETTINGS VDD = 2.7V to 3.6V, TA from -40°C to +125°C Maximum AMCLK (MHz) Maximum AMCLK (MHz) Maximum AMCLK (MHz) Maximum AMCLK (MHz) (SINAD within -3 dB (SINAD within -5 dB (SINAD within -3 dB (SINAD within -5 dB from its maximum) from its maximum) from its maximum) from its maximum) 0.5x 1 4 4 4 4 0.66x 1 6.4 7.3 6.4 7.3 1x 1 11.4 11.4 10.6 10.6 2x 1 16 16 16 16 0.5x 2 4 4 4 4 0.66x 2 6.4 7.3 6.4 7.3 1x 2 11.4 11.4 10.6 10.6 2x 2 16 16 13.3 14.5 0.5x 4 2.9 2.9 2.9 2.9 0.66x 4 6.4 6.4 6.4 6.4 1x 4 10.7 10.7 9.4 10.7 2x 4 16 16 16 16 0.5x 8 2.9 4 2.9 4 0.66x 8 7.3 8 6.4 7.3 1x 8 11.4 12.3 8 8.9 2x 8 16 16 10 11.4 0.5x 16 2.9 2.9 2.9 2.9 0.66x 16 6.4 7.3 6.4 7.3 1x 16 11.4 11.4 9.4 10.6 2x 16 13.3 16 8.9 11.4 0.5x 32 2.9 2.9 2.9 2.9 0.66x 32 7.3 7.3 7.3 7.3 1x 32 10.6 12.3 9.4 10,6 2x 32 13.3 16 10 11.4 DS20005348C-page 30  2014-2020 Microchip Technology Inc. MCP3912 5.3.4 DITHER SETTINGS 5.4 All modulators include a dithering algorithm that can be enabled through the DITHER[1:0] bits in the Configuration register. This dithering process improves THD and SFDR (for high OSR settings), while slightly increasing the noise floor of the ADCs. For power metering applications and applications that are distortion-sensitive, it is recommended to keep the dither at maximum settings for best THD and SFDR performance. In the case of power metering applications, THD and SFDR are critical specifications. Optimizing SNR (noise floor) is not problematic due to the large averaging factor at the output of the ADCs. Therefore, even for low OSR settings, the dithering algorithm will show a positive impact on the performance of the application. SINC3 + SINC1 Filter The decimation filter present in all channels of the MCP3912 is a cascade of two SINC filters (SINC3 + SINC1): a third-order SINC filter with a decimation ratio of OSR3, followed by a first-order SINC filter with a decimation ratio of OSR1 (moving average of OSR1 values). Figure 5-2 represents the decimation filter architecture. OSR1 = 1 Modulator Output SINC3 SINC1 4 OSR3 OSR1 Decimation Filter Output 16 (WIDTH = 0) 24 (WIDTH = 1) Decimation Filter FIGURE 5-2: MCP3912 Decimation Filter Block Diagram. Equation 5-1 calculates the filter z-domain transfer function. EQUATION 5-1: SINC FILTER TRANSFER FUNCTION - OSR 3 3 - OSR 1  OSR 3 1 – z  1 – z      H  z  = ----------------------------------------------  --------------------------------------------------------3 – 1 OSR  OSR  1 – z   3 3 OSR   1 – z 1   Where z = EXP   2   j  f in    DMCLK   Equation 5-2 calculates the settling time of the ADC as a function of DMCLK periods.  2014-2020 Microchip Technology Inc. EQUATION 5-2: SettlingTime  DMCLKperiods = 3  OSR +  OSR – 1   OSR 3 1 3 The SINC1 filter, following the SINC3 filter, is only enabled for the high OSR settings (OSR > 512). This SINC1 filter provides additional rejection at a low cost with little modification to the -3 dB bandwidth. The resolution (number of possible output codes expressed in powers of two or in bits) of the digital filter is 24-bit maximum for any OSR and data format choice. The resolution depends only on the OSR[2:0] bits settings in the CONFIG0 register per Table 5-3. Once the OSR is chosen, the resolution is fixed and the output code respects the data format defined by the WIDTH_DATA[1:0] bits setting in the STATUSCOM register (see Section 5.5 “ADC Output Coding”). DS20005348C-page 31 MCP3912 The gain of the transfer function of this filter is one at each multiple of DMCLK (typically 1 MHz), so a proper anti-aliasing filter must be placed at the inputs. This will attenuate the frequency content around DMCLK and keep the desired accuracy over the baseband of the converter. This anti-aliasing filter can be a simple, firstorder RC network with a sufficiently low time constant to generate high rejection at the DMCLK frequency. Any unsettled data are automatically discarded to avoid data corruption. Each data ready pulse corresponds to fully settled data at the output of the decimation filter. The first data available at the output of the decimation TABLE 5-3: filter is present after the complete settling time of the filter (see Table 5-3). After the first data have been processed, the delay between two data ready pulses coming from the same ADC channel is one DRCLK period. The data stream from input to output is delayed by an amount equal to the settling time of the filter (which is the group delay of the filter). The achievable resolution, the -3 dB bandwidth and the settling time at the output of the decimation filter (the output of the ADC) are dependent on the OSR of each SINC filter and are summarized in Table 5-3. OVERSAMPLING RATIO AND SINC FILTER SETTLING TIME OSR[2:0] OSR3 OSR1 Total OSR Resolution in Bits (No Missing Code) Settling Time -3 dB Bandwidth 32 1 32 17 96/DMCLK 0.26 * DRCLK 0 0 0 0 0 1 64 1 64 20 192/DMCLK 0.26 * DRCLK 0 1 0 128 1 128 23 384/DMCLK 0.26 * DRCLK 0 1 1 256 1 256 24 768/DMCLK 0.26 * DRCLK 1 0 0 512 1 512 24 1536/DMCLK 0.26 * DRCLK 1 0 1 512 2 1024 24 2048/DMCLK 0.37 * DRCLK 1 1 0 512 4 2048 24 3072/DMCLK 0.42 * DRCLK 1 1 1 512 8 4096 24 5120/DMCLK 0.43 * DRCLK 0 0 -20 Magnitude (dB) Ma agnitude (dB) -20 -40 -60 -80 -100 -40 -60 -80 -100 -120 -140 -120 1 10 100 1000 10000 100000 Input Frequency (Hz) FIGURE 5-3: SINC Filter Frequency Response, OSR = 256, MCLK = 4 MHz, PRE[1:0] = 00. DS20005348C-page 32 -160 1 100 10000 Input Frequency (Hz) 1000000 FIGURE 5-4: SINC Filter Frequency Response, OSR = 4096 (in pink), OSR = 512 (in blue), MCLK = 4 MHz, PRE[1:0] = 00.  2014-2020 Microchip Technology Inc. MCP3912 5.5 Equation 5-3 is only true for DC inputs. For AC inputs, this transfer function needs to be multiplied by the transfer function of the SINC3 + SINC1 filter (see Equation 5-1 and Equation 5-3). ADC Output Coding The second-order modulator, SINC3 + SINC1 filter, PGA, VREF and the analog input structure all work together to produce the device transfer function for the Analog-to-Digital conversion (see Equation 5-3). EQUATION 5-3: Channel data are calculated on 24-bit (23-bit plus sign) and coded in two’s complement format, MSB first. The output format can then be modified by the WIDTH_DATA[1:0] bits setting in the STATUSCOM register to allow 16-/24-/32-bit format compatibility (see Section 8.5 “STATUSCOM Register – Status and Communication Register” for more information).   CH n+ – CH n-   DATA_CHn =  -----------------------------------------  8,388,608  G  1.5  V REF+ – V REF- For 24-Bit Mode, WIDTH_Data[1:0] = 01 (Default) For other than the default 24-bit data formats, Equation 5-3 should be multiplied by a scaling factor depending on the data format used (defined by WIDTH_DATA[1:0]). The data format and associated scaling factors are given in Figure 5-5. In case of positive saturation (CHn+ – CHn- > VREF/1.5), the output is locked to 7FFFFF for 24-bit mode. In case of negative saturation (CHn+ – CHn- < -VREF/1.5), the output code is locked to 800000 for 24-bit mode. 23 0 DATA DATA [23:16] [15:8] 15 WIDTH_DATA[1:0] = 00 16-bit DATA DATA [23:16] [15:8] Scaling Factor DATA [7:0] 0 DATA Unformatted ADC Data x1/256 Rounded WIDTH_DATA[1:0] = 01 24-bit 23 WIDTH_DATA[1:0] = 10 32-bit with Zeros Padded 31 WIDTH_DATA[1:0] = 11 32-bit with Sign Extension FIGURE 5-5: DATA DATA [23:16] [15:8] 0 DATA [7:0] x1 0 DATA DATA [23:16] [15:8] DATA [7:0] DATA DATA DATA [23] [23:16] [15:8] DATA [7:0] 31 0x00 x256 0 x1 Output Data Formats.  2014-2020 Microchip Technology Inc. DS20005348C-page 33 MCP3912 The ADC resolution is a function of the OSR (Section 5.4 “SINC3 + SINC1 Filter”). The resolution is the same for all channels. No matter what the resolution is, the ADC output data are always TABLE 5-4: calculated in 24-bit words, with added zeros at the end if the OSR is not large enough to produce 24-bit resolution (left justification). OSR = 256 (AND HIGHER) OUTPUT CODE EXAMPLES ADC Output Code (MSB First) Hexadecimal Decimal, 24-Bit Resolution 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0x7FFFFF + 8,388,607 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0x7FFFFE + 8,388,606 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x000000 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0xFFFFFF –1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0x800001 - 8,388,607 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x800000 - 8,388,608 TABLE 5-5: OSR = 128 OUTPUT CODE EXAMPLES ADC Output Code (MSB First) Hexadecimal Decimal, 23-Bit Resolution 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0x7FFFFE + 4,194,303 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 0 0 0x7FFFFC + 4,194,302 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x000000 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0xFFFFFE –1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0x800002 – 4,194,303 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x800000 – 4,194,304 Hexadecimal Decimal, 20-Bit resolution TABLE 5-6: OSR = 64 OUTPUT CODE EXAMPLES ADC Output Code (MSB First) 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0x7FFFF0 + 524, 287 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0x7FFFE0 + 524, 286 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x000000 0 0xFFFFF0 –1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0x800010 – 524,287 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x800000 – 524, 288 Hexadecimal Decimal, 17-Bit resolution TABLE 5-7: OSR = 32 OUTPUT CODE EXAMPLES ADC Output Code (MSB First) 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0x7FFF80 + 65, 535 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0x7FFF00 + 65, 534 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x000000 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0xFFFF80 –1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0x800080 – 65,535 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x800000 – 65, 536 DS20005348C-page 34  2014-2020 Microchip Technology Inc. MCP3912 5.6 5.6.1 Voltage Reference INTERNAL VOLTAGE REFERENCE by this noise component, even at maximum OSR. This auto-zeroing algorithm is performed synchronously with the MCLK coming to the device. The MCP3912 contains an internal voltage reference source specially designed to minimize drift over temperature. In order to enable the internal voltage reference, the VREFEXT bit in the Configuration register must be set to ‘0’ (default mode). This internal VREF supplies reference voltage to all channels. The typical value of this voltage reference is 1.2V, ±2%. The internal reference has a very low typical temperature coefficient of ±9 ppm/°C, allowing the output to have minimal variation with respect to temperature, since they are proportional to (1/VREF). 5.6.3 The noise of the internal voltage reference is low enough not to significantly degrade the SNR of the ADC if compared to a precision external low noise voltage reference. The output pin for the internal voltage reference is REFIN+/OUT. This temperature coefficient can be adjusted on each part through the VREFCAL[7:0] bits present in the CONFIG0 register (bits 7 to 0). These register settings are only for advanced users. VREFCAL[7:0] should not be modified unless the user wants to calibrate the temperature coefficient of the whole system or application. The default value of this register is set to 0x50. The default value (0x50) was chosen to optimize the standard deviation of the tempco across process variation. The value can be slightly improved to around 7 ppm/°C if the VREFCAL[7:0] bits are written at 0x42, but this setting degrades the standard deviation of the VREF tempco. The typical variation of the temperature coefficient of the internal voltage reference, with respect to the VREFCAL register code, is shown in Figure 5-6. Modifying the value stored in the VREFCAL[7:0] bits may also vary the voltage reference, in addition to the temperature coefficient. If the voltage reference is only used as an internal VREF, adding bypass capacitance on REFIN+/OUT is not necessary for keeping ADC accuracy, but a minimal 0.1 µF ceramic capacitance can be connected to avoid EMI/EMC susceptibility issues due to the antenna created by the REFIN+/OUT pin, if left floating. The bypass capacitors also help applications where the voltage reference output is connected to other circuits. In this case, additional buffering may be needed since the output drive capability of this output is low. Adding too much capacitance on the REFIN+/OUT pin may slightly degrade the THD performance of the ADCs. The internal voltage reference consists of a proprietary circuit and algorithm to compensate first-order and second-order temperature coefficients (tempco). The compensation enables very low-temperature coefficients (typically 9 ppm/°C) on the entire range of temperatures, from -40°C to +125°C. This temperature coefficient varies from part to part. DIFFERENTIAL EXTERNAL VOLTAGE INPUTS When the VREFEXT bit is set to ‘1’, the two reference pins (REFIN+/OUT, REFIN-) become a differential voltage reference input. The voltage at the REFIN+/OUT is noted VREF+ and the voltage at the REFIN- pin is noted VREF-. The differential voltage input value is shown in Equation 5-4. 60 50 VREF Drift (ppm) 5.6.2 TEMPERATURE COMPENSATION (VREFCAL[7:0]) 40 30 20 10 EQUATION 5-4: 0 VREF = VREF+ – VREFThe specified VREF range is from 1.1V to 1.3V. The REFIN- pin voltage (VREF-) should be limited to ±0.1V, with respect to AGND. Typically, for single-ended reference applications, the REFIN- pin should be directly connected to AGND, with its own separate track to avoid any spike due to switching noise. These buffers are injecting a certain quantity of 1/f noise into the system. This noise can be modulated with the incoming input signals and can limit the SNR at very high OSR (OSR > 256). To overcome this limitation, these buffers include an auto-zeroing algorithm that greatly diminishes their 1/f noise, as well as their offset, so that the SNR of the system is not limited  2014-2020 Microchip Technology Inc. 0 64 128 192 VREFCAL Register Trim Code (decimal) FIGURE 5-6: Trim Code Chart. 5.6.4 256 VREF Tempco vs. VREFCAL VOLTAGE REFERENCE BUFFERS Each channel includes a voltage reference buffer tied to the REFIN+/OUT pin, which allows the internal capacitors to properly charge with the voltage reference signals, even in the case of an external voltage reference connection with weak load regulation specifications. This ensures the correct amount of current is sourced to each channel to ensure their accuracy specifications and diminishes the constraints on the voltage reference load regulation. DS20005348C-page 35 MCP3912 5.7 Power-on Reset The MCP3912 contains an internal POR circuit that monitors both analog and digital supply voltages during operation. The typical threshold for a power-up event detection is 2.0V, ±10% and a typical start-up time (tPOR) of 50 µs. The POR circuit has a built-in hysteresis for improved transient spike immunity that has a typical value of 200 mV. Proper decoupling capacitors (0.1 µF in parallel with 10 µF) should be mounted as close as possible to the AVDD and DVDD pins, providing additional transient immunity. Both AVDD and DVDD are monitored, so either power supply can sequence first. Note: Figure 5-7 illustrates the different conditions at a power-up and a power-down event in typical conditions. All internal DC biases are not settled until at least 1 ms, in worst-case conditions, after a system POR. Any data ready pulse occurring within 1 ms, plus the SINC filter settling time after system Reset, should be ignored to ensure proper accuracy. After POR, data ready pulses are present at the pin with all the default conditions in the Configuration registers. In order to ensure a proper power-up sequence, the ramp rate of DVDD should not exceed 3V/µs when coming out of the POR state. Additionally, the user should try to lower the DVDD residual voltage as close to 0V as possible when the device is kept in a POR state (below DVDD POR threshold) for a long time to ensure a proper powerup sequence. The user can verify if the power-up sequence has been correctly performed by reading the default state of all the registers in the register map right after powering up the device. If one or more of the registers do not show the proper default settings when being read, a new power-up cycle should be launched to recover from this condition. Voltage (AVDD, DVDD) Any data ready pulse occurring during this time can yield inaccurate output data. It is recommended to discard them. POR Threshold Up (2.0V typical) (1.8V typical) tPOR POR State Analog Biases Settling Time Power-up Biases are unsettled. Conversions started here may not be accurate FIGURE 5-7: DS20005348C-page 36 SINC Filter Settling Time Normal Operation POR State Time Biases are settled. Conversions started here are accurate. Power-on Reset Operation.  2014-2020 Microchip Technology Inc. MCP3912 5.8 Hard Reset Effect on Delta-Sigma Modulator/SINC Filter When the RESET pin is logic low, all ADCs will be in Reset and output code 0x000000h. The RESET pin performs a Hard Reset (DC biases are still on, the part is ready to convert) and clears all charges contained in the Delta-Sigma modulators. The comparator’s output is ‘0011’ for each ADC. The SINC filters are all reset, as well as their doubleoutput buffers. This pin is independent of the serial interface. It brings all the registers to the default state. When RESET is logic low, any write with the SPI interface will be disabled and will have no effect. All output pins (SDO, DR) are high-impedance. If an external clock (MCLK) is applied, the input structure is enabled and is properly biasing the substrate of the input transistors. In this case, the leakage current on the analog inputs is low if the analog input voltages are kept between -1V and +1V. If MCLK is not applied when in Reset mode, the leakage can be high if the analog inputs are below -0.6V, as referred to AGND. 5.9 Phase Delay Block The MCP3912 incorporates a phase delay generator which ensures that each pair of ADCs (CH0/1, CH2/3) is converting the inputs with a fixed delay between them. The four ADCs are synchronously sampling, but the averaging of modulator outputs is delayed so that the SINC filter outputs (thus the ADC outputs) show a fixed phase delay as determined by the PHASE register setting. The odd channels (CH1,3) are the reference channels for the phase delays of each pair and set the time reference. Typically, these channels can be the voltage channels for a polyphase energy metering application. These odd channels are synchronous at all times, so they become ready and output a data ready pulse at the same time. The even channels (CH0/2) are delayed compared to the time reference (CH1/3) by a fixed amount of time defined for each pair channel in the PHASE register. The PHASE register is split into two 12-bit banks that represent the delay between each pair of channels. The equivalence is defined in Table 5-8. Each phase value (PHASEA/B) represents the delay of the even channel, with respect to the associated odd channel, with an 11-bit plus sign, MSB first, two’s complement code. This code indicates how many DMCLK periods there are between each channel in the pair (see Equation 5-5). Since the odd channels are the time reference, when PHASEx[11:0] are positive, the even channel of the pair is lagging and the odd channel is leading. When PHASEx[11:0] are negative, the even channel of the pair is leading and the odd channel is lagging.  2014-2020 Microchip Technology Inc. TABLE 5-8: PHASE DELAYS EQUIVALENCE Pair of Channels Phase Bank Register Map Position CH1/CH0 PHASEA[11:0] PHASE[11:0] CH3/CH2 PHASEB[11:0] PHASE[23:12] EQUATION 5-5: Total Delay = PHASEx[11:0] Decimal Code DMCLK Where: x = A/B The timing resolution of the phase delay is 1/DMCLK or 1 µs in the default configuration, with MCLK = 4 MHz. Given the definition of DMCLK, the phase delay is affected by a change in the prescaler settings (PRE[1:0]) and the MCLK frequency. The data ready signals are affected by the phase delay settings. Typically, the time difference between the data ready pulses of odd and even channels is equal to the associated phase delay setting. Each ADC conversion start, and therefore, each data ready pulse is delayed by a timing of OSR/2 x DMCLK periods (equal to half a DRCLK period). This timing allows for the odd channel’s data ready signals to be located at a fixed time reference (OSR/2 x DMCLK periods from the Reset), while the even channel can be leading or lagging around this time reference with the corresponding PHASEx[11:0] delay value. Note: 5.9.1 For a detailed explanation of the Data Ready pin (DR) with phase delay, see Section 5.11 “Data Ready Status Bits”. PHASE DELAY LIMITS The limits of the phase delays are determined by the OSR settings; the phase delays can only go from -OSR/2 to +OSR/2-1 DMCLK periods. If larger delays between the two channels are needed, they can be implemented externally to the chip with an MCU. A FIFO in the MCU can save incoming data from the leading channel for a number N of DRCLK clocks. In this case, DRCLK would represent the coarse timing resolution and DMCLK the fine timing resolution. The total delay will then be equal to: EQUATION 5-6: Total Delay = N/DRCLK + PHASE/DMCLK Note: Rewriting the PHASE registers with the same value automatically resets and restarts all ADCs. DS20005348C-page 37 MCP3912 The Phase Delay registers can be programmed once with the OSR = 4096 setting and will adjust the OSR automatically afterwards without the need to change the value of the PHASE registers. • OSR = 4096: The delay can go from -2048 to +2047. PHASEx[11] is the sign bit. PHASEx[10] is the MSB and PHASEx[0] the LSB. • OSR = 2048: The delay can go from -1024 to +1023. PHASEx[10] is the sign bit. PHASEx[9] is the MSB and PHASEx[0] the LSB. • OSR = 1024: The delay can go from -512 to +511. PHASEx[9] is the sign bit. PHASEx[8] is the MSB and PHASEx[0] the LSB. • OSR = 512: The delay can go from -256 to +255 PHASEx[8] is the sign bit. PHASEx[7] is the MSB and PHASEx[0] the LSB. • OSR = 256: The delay can go from -128 to +127. PHASEx[7] is the sign bit. PHASEx[6] is the MSB and PHASEx[0] the LSB. • OSR = 128: The delay can go from -64 to +63. PHASEx[6] is the sign bit. PHASEx[5] is the MSB and PHASEx[0] the LSB. • OSR = 64: The delay can go from -32 to +31. PHASEx[5] is the sign bit. PHASEx[4] is the MSB and PHASEx[0] the LSB. • OSR = 32: The delay can go from -16 to +15. PHASEx[4] is the sign bit. PHASEx[3] is the MSB and PHASEx[0] the LSB. TABLE 5-9: PHASE VALUES WITH MCLK = 4 MHz, OSR = 4096, PRE[1:0] = 00 PHASEx[11:0] for the Channel Pair CH[n/n+1] Hex Delay (CH[n] relative to CH[n+1]) 0 1 1 1 1 1 1 1 1 1 1 1 0x7FF + 2047 µs 0 1 1 1 1 1 1 1 1 1 1 0 0x7FE + 2046 µs 0 0 0 0 0 0 0 0 0 0 0 1 0x001 + 1 µs 0 0 0 0 0 0 0 0 0 0 0 0 0x000 0 µs 1 1 1 1 1 1 1 1 1 1 1 1 0xFFF – 1 µs 1 0 0 0 0 0 0 0 0 0 0 1 0x801 – 2047 µs 1 0 0 0 0 0 0 0 0 0 0 0 0x800 – 2048 µs 5.10 Data Ready Link There are two modes defined with the DR_LINK bit in the STATUSCOM register that control the data ready pulses. The position of the data ready pulses varies with respect to this mode, to the OSR[2:0] and to the PHASE register settings. Section 5.11 “Data Ready Status Bits” represents the behavior of the Data Ready pin with the two DR_LINK configurations. • DR_LINK = 0: Data ready pulses from all enabled channels are output on the DR pin. • DR_LINK = 1 (Recommended and Default mode): Only the data ready pulses from the most lagging ADC between all the active ADCs are present on the DR pin. The lagging ADC data ready position depends on the PHASE register, the PRE[1:0] and the OSR[2:0] settings. In this mode, the active ADCs are linked together, so their data are latched together when the lagging ADC output is ready. For power metering applications, DR_LINK = 1 is recommended (Default mode); it allows the host MCU to gather all channels synchronously within a unique interrupt pulse and it ensures that all channels have been latched at the same time so that no data corruption is happening. 5.11 Data Ready Status Bits In addition to the Data Ready pin indicator, the MCP3912 device includes a separate data ready status bit for each channel. Each ADC channel CHn is associated to the corresponding DRSTATUS[n] that can be read at all times in the STATUSCOM register. These status bits can be used to synchronize the data retrieval in case the DR pin is not connected (see Section 6.8 “ADC Channels Latching and Synchronization”). The DRSTATUS[3:0] bits are not writable; writing on them has no effect. They have a default value of ‘1’, which indicates that the data of the corresponding ADC are not ready. This means that the ADC Output register has not been updated since the last reading (or since the last Reset). The DRSTATUS bits take the ‘0’ state once the ADC Channel register is updated (which happens at a DRCLK rate). A simple read of the STATUSCOM register clears all the DRSTATUS bits to their default value (‘1’). In the case of DR_LINK = 1, the DRSTATUS[3:0] bits are all updated synchronously, with the most lagging channel, at the same time the DR pulse is generated. In the case of DR_LINK = 0, each DRSTATUS bit is updated independently and synchronously with its corresponding channel. DS20005348C-page 38  2014-2020 Microchip Technology Inc. MCP3912 5.12 EQUATION 5-7: Crystal Oscillator The MCP3912 includes a Pierce-type crystal oscillator with very high stability, and ensures very low tempco and jitter for the clock generation. This oscillator can handle crystal frequencies up to 20 MHz, provided proper load capacitances and quartz quality factors are used. The crystal oscillator is enabled when CLKEXT = 0 in the CONFIG1 register. For a proper start-up, the load capacitors of the crystal should be connected between OSC1 and DGND, and between OSC2 and DGND. They should also respect Equation 5-7. PHASE < 0 2 6 1 R M < 1.6  10   ------------------------  f  CLOAD Where: f = Crystal frequency in MHz CLOAD = Load capacitance in pF including parasitics from the PCB RM = Motional resistance in ohms of the quartz When CLKEXT = 1, the crystal oscillator is bypassed by a digital buffer to allow direct clock input for an external clock (see Figure 4-1). In this case, the OSC2 pin is pulled down internally to DGND and should be connected to DGND externally for better EMI/EMC immunity. PHASE > 0 DR DR_LINK = 0 All Channels Data Ready are Present Data Ready Pulse from Odd Channels (reference) PHASE = 0 Data Ready Pulse from Most Lagging ADC Channel Data Ready Pulse from Odd Channels (reference) PHASE = 0 Data Ready Pulse from Most Lagging ADC Channel DR DR_LINK = 1 Only the MostLagging Data Ready is Present, All Channels are Latched Together at DR Falling Edge FIGURE 5-8: One DRCLK Period (OSR times DMCLK periods) DR_LINK Configurations. The external clock should not be higher than 20 MHz before prescaling (MCLK < 20 MHz) for proper operation.  2014-2020 Microchip Technology Inc. Note: In addition to the conditions defining the maximum MCLK input frequency range, the AMCLK frequency should be maintained inferior to the maximum limits defined in Table 5-2 to ensure the accuracy of the ADCs. If these limits are exceeded, it is recommended to choose either a larger OSR or a larger prescaler value so that AMCLK can respect these limits. DS20005348C-page 39 MCP3912 5.13 Digital System Offset and Gain Calibration Registers The MCP3912 incorporates two sets of additional registers per channel to perform system digital offset and gain error calibration. Each channel has its own set of associated registers that will modify the output result of the channel if calibration is enabled. The gain and offset calibrations can be enabled or disabled through two CONFIG0 bits (EN_OFFCAL and EN_GAINCAL). These two bits enable or disable system calibration on all channels at the same time. When both calibrations are enabled, the output of the ADC is modified per Section 5.13.1 “Digital Offset Error Calibration”. 5.13.1 DIGITAL OFFSET ERROR CALIBRATION The OFFCAL_CHn registers are 23-bit plus two’s complement registers, and whose LSB value is the same as the channel ADC data. These registers are added, bit by bit, to the ADC output codes if the EN_OFFCAL bit is enabled. Enabling the EN_OFFCAL bit does not create a pipeline delay; the offset addition is instantaneous. For low OSR values, only the significant digits are added to the output (up to the resolution of the ADC; for example, at OSR = 32, only the 17 first bits are added). The offset is not added when the corresponding channel is in Reset or Shutdown mode. The corresponding input voltage offset value added by each LSB in these 24-bit registers is: EQUATION 5-8: OFFSET(1LSB) = VREF/(PGA_CHn x 1.5 x 8388608) EQUATION 5-10: These registers are a “Don’t Care” if EN_OFFCAL = 0 (offset calibration disabled), but their value is not cleared by the EN_OFFCAL bit. 5.13.2 DIGITAL GAIN ERROR CALIBRATION These registers are signed 24-bit MSB first registers coded with a range of -1x to +(1 – 2-23)x (from 0x800000 to 0x7FFFFF). The gain calibration adds 1x to this register and multiplies it to the output code of the channel, bit by bit, after offset calibration. The range of the gain calibration is thus from 0x to 1.9999999x (from 0x800000 to 0x7FFFFF). The LSB corresponds to a 2-23 increment in the multiplier. Enabling EN_GAINCAL creates a pipeline delay of 24 DMCLK periods on all channels. All data ready pulses are delayed by 24 DMCLK periods, starting from the data ready following the command enabling the EN_GAINCAL bit. The gain calibration is effective on the next data ready following the command enabling the EN_GAINCAL bit. The digital gain calibration does not function when the corresponding channel is in Reset or Shutdown mode. The gain multiplier value for an LSB in these 24-bit registers is: EQUATION 5-9: GAIN (1 LSB) = 1/8388608 This register is a “Don’t Care” if EN_GAINCAL = 0 (offset calibration disabled), but its value is not cleared by the EN_GAINCAL bit. The output data on each channel are kept to either 7FFF or 8000 (16-bit mode), or 7FFFFF or 800000 (24-bit mode) if the output results are out of bounds after all calibrations are performed. DIGITAL OFFSET AND GAIN ERROR CALIBRATION REGISTERS CALCULATIONS DATA_CHn  post – cal  =  DATA_CHn  pre – cal  + OFFCAL_CHn    1 + GAINCAL_CHn  DS20005348C-page 40  2014-2020 Microchip Technology Inc. MCP3912 6.0 SPI SERIAL INTERFACE DESCRIPTION 6.1 Overview The MCP3912 device includes a four-wire (CS, SCK, SDI, SDO) digital serial interface that is compatible with SPI Modes 0,0 and 1,1. Data are clocked out of the MCP3912 on the falling edge of SCK and data are clocked into the MCP3912 on the rising edge of SCK. In these modes, the SCK clock can Idle either high (1,1) or low (0,0). The digital interface is asynchronous with the MCLK clock that controls the ADC sampling and digital filtering. All the digital input pins are Schmitt triggered to avoid system noise perturbations on the communications. Each SPI communication starts with a CS falling edge and stops with the CS rising edge. Each SPI communication is independent. When CS is logic high, SDO is in high-impedance, and transitions on SCK and SDI have no effect. Changing from an SPI Mode 1,1 to an SPI Mode 0,0 and vice versa is possible, and can be done while the CS pin is logic high. Any CS rising edge clears the communication and resets the SPI digital interface. Additional control pins (RESET, DR) are also provided on separate pins for advanced communication features. The Data Ready (DR) pin outputs pulses when new ADC channel data are available for reading, which can be used as an interrupt for an MCU. The Master Reset pin (RESET) acts like a Hard Reset and can reset the part to its default power-up configuration (equivalent to a POR state). The MCP3912 interface has a simple command structure. Every command is either a READ command from a register or a WRITE command to a register. The MCP3912 device includes 32 registers, defined in the register map (Table 8-1). The first byte (8-bit wide) transmitted is always the control byte that defines the address of the register and the type of command (READ or WRITE). It is followed by the register itself, which can be in a 16, 24 or 32-bit format, depending on the multiple format settings defined in the STATUSCOM register. The MCP3912 is compatible with multiple formats that help reduce overhead in the data handling for most MCUs and processors available on the market (8, 16 or 32-bit MCUs), and improve MCU code compaction and efficiency. The MCP3912 digital interface is capable of handling various continuous Read and Write modes, which allows it to perform ADC data streaming or full register map writing within only one communication (and therefore, with only one unique control byte). The internal registers can be grouped together with various configurations through the READ[1:0] and WRITE bits. The internal address counter of the serial interface can be automatically incremented, with no additional control byte needed, in order to loop through the various groups of registers within the register map. The groups are defined in Table 8-2.  2014-2020 Microchip Technology Inc. The MCP3912 device also includes advanced security features. These features secure each communication in order to avoid unwanted WRITE commands being processed to change the desired configuration and to alert the user in case of a change in the desired configuration. Each SPI read communication can be secured through a selectable CRC-16 checksum provided on the SDO pin at the end of every communication sequence. This CRC-16 computation is compatible with the DMA CRC hardware of the PIC24 and PIC32 MCUs, resulting in no additional overhead for the added security. For securing the entire configuration of the device, the MCP3912 includes an 8-bit lock code (LOCK[7:0]), which blocks all WRITE commands to the full register map if the value of the LOCK[7:0] bits are not equal to a defined password (0xA5). The user can protect its configuration by changing the LOCK[7:0] value to 0x00 after the full programming, so that any unwanted WRITE command will not result in a change to the configuration (because the LOCK[7:0] bits are different than the password 0xA5). An additional CRC-16 calculation is also running continuously in the background to ensure the integrity of the full register map. All writable registers of the register map (except the MOD register) are processed through a CRC-16 calculation engine and give a CRC-16 checksum that depends on the configuration. This checksum is readable on the LOCK/CRC register and updated at all times. If a change in this checksum happens, a selectable interrupt can give a flag on the DR pin (DR pin becomes logic low) to warn the user that the configuration is corrupted. 6.2 Control Byte The control byte of the MCP3912 contains two device Address bits (A[6:5]), five register Address bits (A[4:0]) and a Read/Write bit (R/W). The first byte transmitted to the MCP3912 in any communication is always the control byte. During the control byte transfer, the SDO pin is always in a high-impedance state. The MCP3912 interface is device-addressable (through A[6:5]) so that multiple chips can be present on the same SPI bus with no data bus contention. Even if they use the same CS pin, they use a provided half-duplex SPI interface with a different address identifier. This functionality enables, for example, a serial EEPROM, such as 24AAXXX/24LCXXX or 24FCXXX and the MCP3912, to share all the SPI pins and consume less I/O pins in the application processor, since all these serial EEPROM circuits use A[6:5] = 00. . A[6] A[5] Device Address FIGURE 6-1: A[4] A[3] A[2] A[1] Register Address A[0] R/W Read/ Write Control Byte. DS20005348C-page 41 MCP3912 The default device address bits are A[6:5] = 01 (contact the Microchip factory for other available device address bits). For more information, see the Product Identification System section. The register map is defined in Table 8-1. 6.3 Four different Read mode configurations can be defined through the READ[1:0] bits in the STATUSCOM register for the address increment (see Section 6.5, Continuous Communications, Looping on Register Sets and Table 8-2). The data on SDO are clocked out of the MCP3912 on the falling edge of SCK. The reading format for each register is defined in Section 6.5 “Continuous Communications, Looping on Register Sets”. Reading from the Device The first register read on the SDO pin is the one defined by the address (A[4:0]) given in the control byte. After this first register is fully transmitted, if the CS pin is maintained logic low, the communication continues without an additional control byte and the SDO pin transmits another register with the address automatically incremented or not, depending on the READ[1:0] bits settings. CS Device latches SDI on rising edge Device latches SDO on falling edge DATA[ 1] DATA[ 2] DATA[ 3] DATA[ 4] DATA[ 5] DATA[ 6] DATA[ 7] DATA[ 8] DATA[ 9] DATA[ 11] DATA[ 12] DATA[ 13] DATA[ 14] DATA[ 15] DATA[ 16] DATA[ 17] DATA[ 18] DATA[ 19] DATA[ 20] DATA[ 21] DATA[ 22] DATA[ 23] High-Z SDO Don’t care R/W DATA[ 10] A[ 0] A[ 1] A[ 2] A[ 4] A[ 3] Don’t care A[ 5] SDI A[ 6] SCK DATA[ 0] High-Z Read Communication (SPI Mode 1,1) FIGURE 6-2: SPI Mode 1,1). Read on a Single Register with 24-Bit Format (WIDTH_DATA[1:0] = 01, CS Device latches SDI on rising edge Device latches SDO on falling edge DATA [ 0] DATA[ 1] DATA[ 2] DATA[ 3] DATA[ 4] DATA[ 5] DATA[ 6] DATA[ 7] DATA[ 8] DATA[ 9] DATA[ 10] DATA[ 11] DATA[ 12] DATA[ 13] DATA[ 14] DATA[ 15] DATA[ 16] DATA[ 17] DATA[ 18] DATA[ 19] DATA[ 20] A[ 0] A[ 1] A[ 2] A[ 3] R/W DATA[ 23] DATA[ 21] High-Z Don‘t care DATA[ 22] SDO A[ 4] Don’t care A[ 5] SDI A[ 6] SCK Don’t care High-Z Read Communication (SPI Mode 0,0) FIGURE 6-3: SPI Mode 0,0). DS20005348C-page 42 Read on a Single Register with 24-Bit Format (WIDTH_DATA[1:0] = 01,  2014-2020 Microchip Technology Inc. MCP3912 6.4 Two different Write mode configurations for the address increment can be defined through the WRITE bit in the STATUSCOM register (see Section 6.5, Continuous Communications, Looping on Register Sets and Table 8-2). The SDO pin stays in a high-impedance state during a write communication. The data on SDI are clocked into the MCP3912 on the rising edge of SCK. The writing format for each register is defined in Section 6.5 “Continuous Communications, Looping on Register Sets”. A write on an undefined or nonwritable address, such as the ADC channel’s register addresses, will have no effect and also will not increment the address counter. Writing to the Device The first register written from the SDI pin to the device is the one defined by the address (A[4:0]) given in the control byte. After this first register is fully transmitted, if the CS pin is maintained logic low, the communication continues without an additional control byte and the SDI pin transmits another register with the address automatically incremented or not, depending on the WRITE bit setting. CS Device latches SDI on rising edge DATA[ 1] DATA[ 2] DATA[ 3] DATA[ 4] DATA[ 5] DATA[ 6] DATA[ 7] DATA[ 8] DATA[ 9] DATA[ 10] DATA[ 11] DATA[ 12] DATA[ 13] DATA[ 14] DATA[ 15] DATA[ 16] DATA[ 17] DATA[ 18] DATA[ 19] DATA[ 20] DATA[ 21] DATA[ 22] R/W DATA[ 23] A[ 0] A[ 1] A[ 2] A[ 3] A[ 4] Don’t care A[ 5] SDI A[ 6] SCK DATA[ 0] Don’t care High-Z SDO Write WriteCommunication Communication(SPI (SPIMode mode1,1) 1,1) FIGURE 6-4: Write to a Single Register with 24-Bit Format (SPI Mode 1,1). CS Device latches SDI on rising edge DATA[ 0] DATA[ 1] DATA[ 2] DATA[ 3] DATA[ 4] DATA[ 5] DATA[ 6] DATA[ 7] DATA[ 8] DATA[ 9] DATA[ 11] DATA[ 10] DATA[ 12] DATA[ 13] DATA[ 14] DATA[ 15] DATA[ 16] DATA[ 17] DATA[ 18] DATA[ 19] DATA[ 20] DATA[ 21] DATA[ 23] DATA[ 22] R/W A[ 0] A[ 1] A[ 2] A[ 3] A[ 4] Don’t care A[ 5] SDI A[ 6] SCK Don’t care High-Z SDO Write (SPI mode Mode 0,0) 0,0) Write Communication Communication (SPI FIGURE 6-5: Write to a Single Register with 24-Bit Format (SPI Mode 0,0).  2014-2020 Microchip Technology Inc. DS20005348C-page 43 MCP3912 6.5 high. The SPI internal Register Address Pointer starts by transmitting/receiving the address defined in the control byte. After this first transmission/reception, the SPI internal Register Address Pointer automatically increments to the next available address in the register set for each transmission/reception. When it reaches the last address of the set, the communication sequence is finished. The Address Pointer automatically loops back to the first address of the defined set and restarts a new sequence with auto-increment (see Table 6-6). This internal Address Pointer automatic selection allows the following functionality: Continuous Communications, Looping on Register Sets The MCP3912 digital interface can process communications in Continuous mode without having to enter an SPI command between each read or write to a register. This feature allows the user to reduce communication overhead to the strict minimum, which diminishes EMI emissions and reduces switching noise in the system. The registers can be grouped into multiple sets for continuous communications. The grouping of the registers in the different sets is defined by the READ[1:0] and WRITE bits that control the internal SPI Communication Address Pointer. For a graphical representation of the register map sets in the function of the READ[1:0] and WRITE bits, please see Table 8-2. • Read one ADC channel data, pairs of ADC channels or all ADC channels continuously • Continuously read the entire register map • Continuously read or write each separate register • Continuously read or write all Configuration registers In the case of a continuous communication, there is only one control byte on SDI to start the communication after a CS pin falling edge. The part stays within the same communication loop until the CS pin returns logic CS ADDRESS SET SCK 8x SDI CONTROL BYTE 24x 24x ... 24x 24x 24x ... 24x ADDR ADDR + 1 Don’t care Don’t care ... Starts Read Sequence at Address ADDR High-Z SDO Complete READ Sequence ADDR + n Rollover ADDR ADDR + 1 ... ADDR + n ADDR ADDR + 1 Complete READ Sequence ... ADDR + n Complete READ Sequence Continuous Read Communication (24-bit format) CS ADDRESS SET SCK 8x 24x 24x ... 24x 24x 24x ... 24x ADDR ADDR + 1 SDI Don’t care CONTROL BYTE Starts Write Sequence at Address ADDR SDO ADDR ADDR + 1 ... ADDR + n ADDR ADDR + 1 Complete WRITE Sequence ... Complete WRITE Sequence ADDR + n ... Complete WRITE Sequence ADDR + n Rollover High-Z Continuous Write Communication (24-bit format) FIGURE 6-6: DS20005348C-page 44 Continuous Communication Sequences.  2014-2020 Microchip Technology Inc. MCP3912 6.5.1 CONTINUOUS READ with the default settings (DR_LINK = 1, READ[1:0] = 10, WIDTH_DATA[1:0] = 01) in the case of SPI Mode 0,0 (Figure 6-7) and SPI Mode 1,1 (Figure 6-8). The STATUSCOM register contains the read communication loop settings for the internal Register Address Pointer (READ[1:0] bits). For continuous Read modes, the address selection can take the following four values: TABLE 6-1: Note: ADDRESS SELECTION IN CONTINUOUS READ Register Address Set Grouping for Continuous Read Communications READ[1:0] 00 Static (no incrementation) 01 Groups 10 Types (default) 11 Full Register Map Any SDI data coming after the control byte are not considered during a continuous read communication. The following figures represent a typical continuous read communication on all four ADC channels in TYPES mode For continuous reading of ADC data in SPI Mode 0,0 (see Figure 6-7), once the data have been completely read after a data ready, the SDO pin will take the MSB value of the previous data at the end of the reading (falling edge of the last SCK clock). If SCK stays Idle at logic low (by definition of Mode 0,0), the SDO pin will be updated at the falling edge of the next data ready pulse (synchronously with the DR pin falling edge with an output timing of tDODR) with the new MSB of the data corresponding to the data ready pulse. This mechanism allows the MCP3912 to continuously read ADC data outputs seamlessly, even in SPI Mode (0,0). In SPI Mode (1,1), the SDO pin stays in the last state (LSB of previous data) after a complete reading, which also allows seamless continuous Read mode (see Figure 6-8). CS SCK SDI 8x Don’t Care 24x 24x ... 24x 24x 24x ... DATA_CH0 DATA_CH1 ... 24x Don’t Care 0x01 Starts Read Sequence at Address 00000 High-Z SDO DATA_CH0 DATA_CH1 ... DATA_CH3 DATA_CH0[23] DATA_CH0[23] Old Data New Data DATA_CH3 Complete READ Sequence on New ADC Outputs Channels 0 to3 Complete READ Sequence on ADC Outputs Channels 0 to3 DR FIGURE 6-7: Typical Continuous Read Communication (WIDTH_DATA[1:0] = 01, SPI Mode 0,0). CS SCK SDI 8x Don’t Care 24x 24x ... 24x 24x 24x ... 24x DATA_CH0 DATA_CH1 ... DATA_CH3 Don’t Care 0x01 Starts Read Sequence at Address 00000 SDO High-Z DATA_CH0 DATA_CH1 ... DATA_CH3 Complete READ Sequence on ADC Outputs Channels 0 to 3 Stays at DATA_CH3[0] Complete READ Sequence on New ADC Outputs, Channels 0 to 3 DR FIGURE 6-8: Typical Continuous Read Communication (WIDTH_DATA[1:0] = 01, SPI Mode 1,1).  2014-2020 Microchip Technology Inc. DS20005348C-page 45 MCP3912 6.5.2 CONTINUOUS WRITE The STATUSCOM register contains the write loop settings for the internal Register Address Pointer (WRITE). For a continuous write, the address selection can take the following two values: TABLE 6-2: WRITE ADDRESS SELECTION IN CONTINUOUS WRITE Register Address Set Grouping for Continuous Read Communications 0 Static (no incrementation) 1 Types (default) SDO is always in a high-impedance state during a continuous write communication. Writing to a nonwritable address (such as addresses 0x00 to 0x07) has no effect and does not increment the Address Pointer. In this case, the user needs to stop the communication and restart a communication with a control byte pointing to a writable address (0x08 to 0x1F). Note: 6.6 When the LOCK[7:0] bits are different than 0xA5, all the addresses, except 0x1F, become nonwritable (see Section 4.13 “MCP3912 Delta-Sigma Architecture”). Situations that Reset and Restart Active ADCs Immediately after the following actions, the active ADCs (the ones not in Soft Reset or Shutdown modes) are reset and automatically restarted in order to provide proper operation: 1. 2. 3. 4. 5. 6. Change in PHASE register. Overwrite of the same PHASE register value. Change in the OSR[2:0] bits setting. Change in the PRE[1:0] bits setting. Change in the CLKEXT bit setting. Change in the VREFEXT bit setting. 6.7 Data Ready Pin (DR) To communicate when channel data are ready for transmission, the data ready signal is available on the Data Ready (DR) pin at the end of a channel conversion. The Data Ready pin outputs an active-low pulse with a pulse width equal to half a DMCLK clock period. After a data ready pulse falling edge has occurred, the ADC output data are updated within the tDODR timing and can then be read through SPI communication. The first data ready pulse after a Hard or a Soft Reset is located after the settling time of the SINC filter (see Table 5-3) plus the phase delay of the corresponding channel (see Section 5.9 “Phase Delay Block”). Each subsequent pulse is then periodic and the period is equal to a DRCLK clock period (see Equation 4-3 and Figure 1-3). The data ready pulse is always synchronous with the internal DRCLK clock. The DR pin can be used as an interrupt pin when connected to an MCU or DSP, which will synchronize the readings of the ADC data outputs. When not activelow, this pin can either be in high-impedance (when DR_HIZ = 0) or in a defined logic high state (when DR_HIZ = 1). This is controlled through the STATUSCOM register. This allows multiple devices to share the same Data Ready pin (with a pull-up resistor connected between DR and DVDD). If only the MCP3912 device is connected on the interrupt bus, the DR pin does not require a pull-up resistor, and therefore, it is recommended to use DR_HIZ = 1 configuration for such applications. The CS pin has no effect over the DR pin, which means even if the CS pin is logic high, the data ready pulses coming from the active ADC channels will still be provided; the DR pin behavior is independent from the SPI interface. While the RESET pin is logic low, the DR pin is not active. The DR pin is latched in the logic low state when the interrupt flag on CRCREG is present to signal that the desired register’s configuration has been corrupted (see Section 6.11 “Detecting Configuration Change Through CRC-16 Checksum on Register Map and its Associated Interrupt Flag”). After these temporary Resets, the ADCs go back to normal operation with no need for an additional command. Each ADC Data Output register is cleared during this process. The PHASE register can be used to serially soft reset the ADCs, without using the RESET[3:0] bits in the Configuration register, if the same value is written in the PHASE register. DS20005348C-page 46  2014-2020 Microchip Technology Inc. MCP3912 6.8 ADC Channels Latching and Synchronization The ADC Channel Data Output registers (addresses 0x00 to 0x03) have a double-buffer output structure. The two sets of latches in series are triggered by the data ready signal and an internal signal indicating the beginning of a read communication sequence (read start). The first set of latches holds each ADC Channel Data Output register when the data are ready and latches all active outputs together when DR_LINK = 1. This behavior is synchronous with the DMCLK clock. The second set of latches ensures that when reading starts on an ADC output, the corresponding data are latched so that no data corruption can occur within a read. This behavior is synchronous with the SCK clock. If an ADC read has started, in order to read the following ADC output, the current reading needs to be fully completed (all bits must be read on the SDO pin from the ADC Output Data registers). Since the double-output buffer structure is triggered with two events that depend on two asynchronous clocks (data ready with DMCLK and read start with SCK), one of the three following methods on the MCU or processor should be implemented in order to synchronize the reading of the channels: 1. 2. 3. The first method is the preferred one, as it can be used without adding additional MCU code space, but requires connecting the DR pin to an I/O pin of the MCU. The last two methods require more MCU code space and execution time, but they allow synchronized reading of the channels without connecting the DR pin, which saves one I/O pin on the MCU. 6.9 Securing Read Communications Through CRC-16 Checksum Since power/energy metering systems can generate or receive large EMI/EMC interferences and large transient spikes, it is helpful to secure SPI communications as much as possible to maintain data integrity and desired configurations during the lifetime of the application. The communication data on the SDO pin can be secured through the insertion of a Cyclic Redundancy Check (CRC) checksum at the end of each continuous reading sequence. The CRC checksum on communications can be enabled or disabled through the EN_CRCCOM bit in the STATUSCOM register. The CRC message ensures the integrity of the read sequence bits transmitted on the SDO pin and the CRC checksum is inserted in between each read sequence (see Figure 6-9). Use the Data Ready pin pulses as an interrupt: Once a falling edge occurs on the DR pin, the data are available for reading on the ADC Output registers after the tDODR timing. If this timing is not respected, data corruption can occur. Use a timer clocked with MCLK as a synchronization event: Since the Data Ready pin is synchronous with DMCLK, the user can calculate the position of the Data Ready pin depending on the PHASE register, the OSR[2:0] and the PRE[1:0] bits setting for each channel. Again, the tDODR timing needs to be added to this calculation, to avoid data corruption. Poll the DRSTATUS[3:0] bits in the STATUSCOM register: This method consists of continuously reading the STATUSCOM register and waiting for the DRSTATUS bits to be equal to ‘0’. When this event happens, the user can start a new communication to read the desired ADC data. In this case, no additional timing is required.  2014-2020 Microchip Technology Inc. DS20005348C-page 47 MCP3912 CS ADDRESS SET SCK 8x 16x/24x/32x Depending on Data Format 16x/24x/32x Depending on Data Format ... 16x/24x/32x Depending on Data Format 16x/24x/32x Depending on Data Format 16x/24x/32x Depending on Data Format 16x/24x/32x Depending on Data Format ... ADDR ADDR + 1 SDI CONTROL BYTE Don’t care Don’t care ... Starts Read Sequence at Address ADDR ADDR + n* Rollover High-Z SDO Complete READ Sequence ADDR ADDR + 1 ... ADDR + n ADDR Complete READ Sequence ADDR + 1 ... ADDR + n Complete READ Sequence Continuous READ Communication without CRC Checksum (EN_CRCCOM = 0) CS ADDRESS SET SCK 8x 16x/24x/32x Depending on Data Format 16x/24x/32x Depending on Data Format ... 16x/24x/32x Depending on Data Format 16x or 32x Depending on CRC Format 16x/24x/32x Depending on Data Format 16x/24x/32x Depending on Data Format ... 16x/24x/32x Depending on Data Format 16x or 32x Depending on CRC Format ADDR ADDR + 1 SDI CONTROL BYTE Don’t care Don’t care ... Starts Read Sequence at Address ADDR SDO Complete READ Sequence ADDR + n* High-Z ADDR ADDR + 1 ... ADDR + n CRC Checksum ADDR ADDR + 1 ... ADDR + n CRC Checksum CRC Checksum (not part of register map) Rollover Complete READ Sequence = Message for CRC Calculation Checksum New Message New Checksum Continuous READ Communication with CRC Checksum (EN_CRCCOM = 1) *n Depends on the READ[1:0] bits. FIGURE 6-9: Continuous Read Sequences with and without CRC Checksum Enabled. The CRC checksum in the MCP3912 device uses the 16-bit CRC-16 ANSI polynomial, as defined in the IEEE 802.3 standard: x16 + x15 + x2 + 1. This polynomial can also be noted as 0x8005. CRC-16 detects all single and double-bit errors, all errors with an odd number of bits, all burst errors of length 16 or less and most errors for longer bursts. This allows an excellent coverage of the SPI communication errors that can happen in the system and heavily reduces the risk of a miscommunication, even under noisy environments. The CRC-16 format displayed on the SDO pin depends on the WIDTH_CRC bit in the STATUSCOM register (see Figure 6-10). It can be either 16-bit or 32-bit format, to be compatible with both 16-bit and 32-bit MCUs. The CRCCOM[15:0] bits, calculated by the MCP3912 device, are not dependent on the format (the device always calculates only a 16-bit CRC checksum). If a 32-bit MCU is used in the application, it is recommended to use 32-bit formats (WIDTH_CRC = 1) only. WIDTH_DATA[1] = 0 16-Bit Format 15 WIDTH_DATA[1] = 1 32-Bit Format 31 FIGURE 6-10: DS20005348C-page 48 The CRC calculation computed by the MCP3912 device is fully compatible with CRC hardware contained in the Direct Memory Access (DMA) of the PIC24 and PIC32 MCU product lines. The CRC message that should be considered in the PIC® device DMA is the concatenation of the read sequence and its associated checksum. When the DMA CRC hardware computes this extended message, the resulted checksum should be 0x0000. Any other result indicates that a miscommunication has happened and that the current communication sequence should be stopped and restarted. Note: The CRC will be generated only at the end of the selected address set, before the rollover of the Address Pointer occurs (see Figure 6-9). 0 CRCCOM CRCCOM [15:8] [7:0] CRCCOM CRCCOM [15:8] [7:0] 0 0x00 0x00 CRC Checksum Format.  2014-2020 Microchip Technology Inc. MCP3912 6.10 Locking/Unlocking Register Map Write Access The MCP3912 digital interface includes an advanced security feature that permits locking or unlocking the register map write access. This feature prevents the miscommunications that can corrupt the desired configuration of the device, especially an SPI read becoming an SPI write because of the noisy environment. The last register address of the register map (0x1F: LOCK/CRC) contains the LOCK[7:0] bits. If these bits are equal to the password value (which is equal to the default value of 0xA5), the register map write access is not locked. Any write can take place and the communications are not protected. When the LOCK[7:0] bits are different than 0xA5, the register map write access is locked. The register map, and therefore, the full device configuration, is writeprotected. Any write to an address other than 0x1F will yield no result. All the register addresses, except the address 0x1F, become read-only. In this case, if the user wants to change the configuration, the LOCK[7:0] bits have to be reprogrammed back to 0xA5 before sending the desired WRITE command. The LOCK[7:0] bits are located in the last register so the user can program the whole register map, starting from 0x09 to 0x1E, within one continuous write sequence, and then lock the configuration at the end of the sequence by writing all zeros in the address 0x1F, for example. 6.11 Detecting Configuration Change Through CRC-16 Checksum on Register Map and its Associated Interrupt Flag In order to prevent internal corruption of the register and to provide additional security on the register map configuration, the MCP3912 device includes an automatic and continuous CRC checksum calculation on the full register map Configuration bits. This calculation is not the same as the communication CRC checksum described in Section 6.9 “Securing Read Communications Through CRC-16 Checksum”. This calculation takes the full register map as the CRC message and outputs a checksum on the CRCREG[15:0] bits located in the LOCK/CRC register (address 0x1F).  2014-2020 Microchip Technology Inc. Since this feature is intended for protecting the configuration of the device, this calculation is run continuously only when the register map is locked (LOCK[7:0] bits are different than 0xA5, see Section 6.10, Locking/Unlocking Register Map Write Access). If the register map is unlocked, the CRCREG[15:0] bits are cleared and no CRC is calculated. The calculation is fully completed in 16 DMCLK periods and refreshed every 16 DMCLK periods continuously. The CRCREG[15:0] bits are reset when a POR or a Hard Reset occurs. All the bits contained in the registers, from addresses 0x09-0x1F, are processed by the CRC engine to give the CRCREG[15:0] bits. The DRSTATUS[3:0] bits are set to ‘1’ (default) and the CRCREG[15:0] bits are set to ‘0’ (default) for this calculation engine, as they could vary during the calculation. An interrupt flag can be enabled through the EN_INT bit in the STATUSCOM register and provided on the DR pin when the configuration has changed without a WRITE command being processed. This interrupt is a logic low state. This interrupt is cleared when the register map is unlocked (since the CRC calculation is not processed). At power-up, the interrupt is not present and the register map is unlocked. As soon as the user finishes writing its configuration, the user needs to lock the register map (writing 0x00, for example, in the LOCK bits) to be able to use the interrupt flag. The CRCREG[15:0] bits will be calculated for the first time in 16 DMCLK periods. This first value will then be the reference checksum value and will be latched internally until a Hard Reset, a POR or an unlocking of the register map happens. The CRCREG[15:0] bits will then be calculated continuously and checked against the reference checksum. If the CRCREG[15:0] bits are different than the reference, the interrupt sends a flag by setting the DR pin to a logic low state until it is cleared. DS20005348C-page 49 MCP3912 NOTES: DS20005348C-page 50  2014-2020 Microchip Technology Inc. MCP3912 7.0 BASIC APPLICATION RECOMMENDATIONS 7.1 Typical Application Examples Since all channels are identical in the MCP3912, any channel can be chosen as the voltage channel (preferably CH0 or CH3 since they are on the edges and can lead to a cleaner layout). The application schematic referenced in Figure 7-1 can be used as a starting point for MCP3912 applications.The most common solution is to use one channel for voltage measurement and the rest of the channels for current measurement. Since all current lines are at the same potential, shunts can be used as current sensors, even if they do not provide any galvanic isolation. GNDA 1x3 R65 0603 1k 1% GNDA GNDA 1k 1% J7 1k 5 3 1 6 4 2 1 2 3 CH0+ GND CH0- 0603 2x3 GNDA R67 1k R68 GNDA 1x3 R71 0603 1k 1% GNDA GNDA 1k 1% J21 1k 5 3 1 6 4 2 CH1GND CH1+ 0603 1 2 3 R69 J22 2x3 R73 R74 GNDA 1x3 R77 0603 1k 1% GNDA GNDA 1k 1% J23 1k 5 3 1 6 4 2 CH2+ GND CH2- 1 2 3 R75 0603 2x3 R79 GNDA 1x3 R83 0603 1k 1% GNDA GNDA 1k 1% J25 1k 5 3 1 6 4 2 1 2 3 R81 0603 2x3 0603 1% 0603 1% 0603 1% GNDA C47 R66 C50 1k 1% 0603 1k 1% 0603 0603 1% 0.1uF 0603 GNDA 0.1uF 0603 3.3A 3.3D ADC R9 10R 0603 C4 0.1uF R70 C51 R72 C52 1k 1% 0603 1k 1% 0603 R76 1k 1% 0603 1k 1% 0603 R82 1k 1% 0603 1k 1% 0603 0.1uF 0603 GNDA C54 0.1uF 0603 C55 0.1uF 0603 GNDA C56 0.1uF 0603 R7 10R 0603 C3 0.1uF 0603 GND U5 1 0.1uF 0603 C53 0603 GNDA 0.1uF 0603 GNDA 16 GNDA R84 R85 1k FIGURE 7-1: 0603 1% R64 R78 R80 J26 0603 1% GNDA 1k CH3GND CH3+ 0603 1% GNDA 1k J24 0603 1% MCP3912 DVDD AGND 20 DGND 17 DGND CH0+ CH0- 2 CH0+ 3 CH0- CH1CH1+ 4 CH15 CH1+ CH2+ CH2- 6 CH2+ 7 CH28 CH39 CH3+ CH3CH3+ 28 AVDD 14 REFIN+ 15 REFINGNDA RESET SDI SDO SCK CS DR 27 26 25 24 23 18 22 OSC2 21 OSC1/CLKI NC NC NC NC NC 19 13 12 11 10 GND R5 0603 R8 0603 100R 10R R12 10R 0603 R6 0603 R10 0603 10R 10R R14 10R 0603 J3 R17 ECCP3 XTAL X 10R 0603 RD3/3912_CLKIN XTAL X 2x3 C6 18pF C5 0.1uF 0603 GNDA RA5/3912_RESET RG8/3912_SDI RG7/3912_SDO RG6/3912_SCK RG9/3912_CS RA14/3912_DR ADC CLOCK SELECT 1 3 5 2 4 6 R16 R18 J20 0603 GND X1 R20 1M 1% 0603 10MHz C7 18pF 0603 GND MCP3912 Application Example Schematic.  2014-2020 Microchip Technology Inc. DS20005348C-page 51 MCP3912 7.2 Power Supply Design and Bypassing The MCP3912 device was designed to measure positive and negative voltages that might be generated by a current-sensing device. This current-sensing device, with a Common-mode voltage close to 0V, is referred to as AGND, which is a shunt or Current Transformer (CT) with burden resistors attached to ground. The high performance and good flexibility that characterize this ADC enables it to be used in other applications, as long as the absolute voltage on each pin, referred to AGND, stays in the -1V to +1V interval. In any system, the analog ICs (such as references or operational amplifiers) are always connected to the analog ground plane. The MCP3912 should also be considered as a sensitive analog component and connected to the analog ground plane. The ADC features two pairs of pins: AGND and AVDD, DGND and DVDD. For best performance, it is recommended to keep the two pairs connected to two different networks (Figure 7-2). This way, the design will feature two ground traces and two power supplies (Figure 7-3). This means the analog circuitry (including MCP3912) and the digital circuitry (MCU) should have separate power supplies and return paths to the external ground reference, as described in Figure 7-2. An example of a typical power supply circuit, with different lines for analog and digital power, is shown in Figure 7-3. A possible split example is shown in Figure 7-4, where the ground star connection can be done at the bottom of the device with the exposed pad. The split here between analog and digital can be done under the device, and AVDD and DVDD can be connected together with lines coming under the ground plane. Another possibility, sometimes easier to implement in terms of PCB layout, is to consider the MCP3912 as an analog component, and therefore, connect both AVDD and DVDD together, and AGND and DGND together with a star connection. In this scheme, the decoupling capacitors may be larger due to the ripple on the digital power supply (caused by the digital filters and the SPI interface of the MCP3912) now causing glitches on the analog power supply. ID IA 0.1 μF 0.1 μF MCU C VA AVDD DVDD MCP39XX AGND DGND VD IA ID “Star” Point D- = A- = FIGURE 7-2: All Analog and Digital Return Paths Need to Stay Separate with Proper Bypass Capacitors. FIGURE 7-3: Power Supply with Separate Lines for Analog and Digital Sections. Note the “Net Tie” Object NT2 that Represents the Start Ground Connection. DS20005348C-page 52  2014-2020 Microchip Technology Inc. DGND DVDD AVDD CH0+ AGND CH0- ANALOG RESET MCP3912 DIGITAL 28 27 26 25 24 23 22 CH1- 1 21 SDI CH1+ 2 20 SDO CH2+ 3 19 SCK EP 29 CH2- 4 18 CS CH3- 5 17 OSC2 CH3+ 6 16 OSC1/CLKI 15 DGND NC 7 DR DGND AVDD DVDD 9 10 11 12 13 14 REFIN+/ OUT REFINAGND 8 FIGURE 7-4: Separation of Analog and Digital Circuits on Layout. Figure 7-5 shows a more detailed example with a direct connection to a high-voltage line (e.g., a two-wire 120V or 220V system). A current-sensing shunt is used for current measurement on the high side/line side that also supplies the ground for the system. This is necessary as the shunt is directly connected to the channel input pins of the MCP3912. To reduce sensitivity to external influences, such as EMI, these two wires should form a twisted pair, as noted in Figure 7-5. The power supply and MCU are separated on the right side of the PCB, surrounded by the digital ground plane. The MCP3912 is kept on the left side, surrounded by the analog ground plane. There are two separate power supplies going to the digital section of the system and the analog section, including the MCP3912. With this placement, there are two separate current supply paths and current return paths, IA and ID. Analog Ground Plane IA IA 7.3 SPI Interface Digital Crosstalk The MCP3912 incorporates a high-speed 20 MHz SPI digital interface. This interface can induce a crosstalk, especially with the outer channels (CH0, for example), if it is running at its full speed without any precautions. The crosstalk is caused by the switching noise created by the digital SPI signals (also called ground bouncing). This crosstalk would negatively impact the SNR in this case. The noise is attenuated if a proper separation between the analog and digital power supplies is put in place (see Section 7.2 “Power Supply Design and Bypassing”). In order to further remove the influence of the SPI communication on measurement accuracy, it is recommended to add series resistors on the SPI lines to reduce the current spikes caused by the digital switching noise (see Figure 7-5 where these resistors have been implemented). The resistors also help to keep the level of electromagnetic emissions low. The measurement graphs provided in this MCP3912 data sheet have been performed with 100 series resistors connected on each SPI I/O pin. Measurement accuracy disturbances have not been observed, even at the full speed of 20 MHz interfacing. The crosstalk performance is dependent on the package choice due to the difference in the pin arrangement (dual in-line or quad) and is improved in the 28-lead QFN package. Digital Ground Plane MCU MCP3912 The ferrite bead between the digital and analog ground planes helps keep high-frequency noise from entering the device. This ferrite bead is recommended to be low resistance; most often it is a THT component. Ferrite beads are typically placed on the shunt inputs and into the power supply circuit for additional protection. ID ID VD VA Power Supply Circuitry Twisted Pair LINE “Star” Point SHUNT NEUTRAL FIGURE 7-5: Connection Diagram.  2014-2020 Microchip Technology Inc. DS20005348C-page 53 MCP3912 7.4 Sampling Speed and Bandwidth If ADC power consumption is not a concern in the design, the BOOST settings can be increased for best performance so that the OSR is always kept at the maximum settings to improve the SINAD performance (see Table 7-1). If the MCU cannot generate a clock fast enough, it is possible to tap the OSC1/OSC2 pins of the MCP3912 crystal oscillator directly to the crystal of the microcontroller. When the sampling frequency is enlarged, the phase resolution is improved, and with the OSR increased, the phase compensation range can be kept in the same range as the default settings. TABLE 7-1: SAMPLING SPEED vs. MCLK AND OSR, ADC PRESCALE 1:1 MCLK (MHz) BOOST[1:0] OSR Sampling Speed (ksps) 16 11 1024 3.91 7.5 14 11 1024 3.42 12 11 1024 2.93 10 10 1024 2.44 8 10 512 3.91 6 01 512 2.93 4 01 256 3.91 Differential Inputs Anti-Aliasing Filter Due to the nature of the ADCs used in the MCP3912 (oversampling converters), each differential input of the ADC channels requires an anti-aliasing filter so that the oversampling frequency (DMCLK) is largely attenuated and does not generate any disturbances on the ADC accuracy. This anti-aliasing filter also needs to have a gain close to one in the signal bandwidth of interest. Typically for 50/60 Hz measurement and default settings (DMCLK = 1 MHz), a simple RC filter with 1 k and 100 nF can be used. The anti-aliasing filter used for the measurement graphs is a first-order RC filter with 1 k and 15 nF. The typical schematic for connecting a current transformer to the ADC is shown in Figure 7-6. If wires are involved, twisting them is also recommended. DS20005348C-page 54 FIGURE 7-6: First-Order Anti-Aliasing Filter for CT-Based Designs. The di/dt current sensors, such as Rogowski coils, can be an alternative to current transformers. Since these sensing elements are highly sensitive to highfrequency electromagnetic fields, using a second-order anti-aliasing filter is recommended to increase the attenuation of potential perturbing RF signals. FIGURE 7-7: Second-Order Anti-Aliasing Filter for Rogowski Coil-Based Designs. The MCP3912 is highly recommended in applications using di/dt as current sensors because of the extremely low noise floor at low frequencies. In such applications, a Low-Pass Filter (LPF) with a cutoff frequency much lower than the signal frequency (50-60 Hz for metering) is used to compensate for the 90-degree shift and for the 20 db/decade attenuation induced by the di/dt sensor. Because of this filter, the SNR will be decreased, since the signal will attenuate by a few orders of magnitude, while the low-frequency noise will not be attenuated. Usually, a high-order High-Pass Filter (HPF) is used to attenuate the low-frequency noise in order to prevent a dramatic degradation of the SNR, which can be very important in other parts. A high-order filter will also consume a significant portion of the computation power of the MCU. When using the MCP3912, such a high-order HPF is not required since this part has a low noise floor at low frequencies. A first-order HPF is enough to achieve very good accuracy.  2014-2020 Microchip Technology Inc. MCP3912 7.6 Energy Measurement Error Considerations The measurement error is a typical representation of the nonlinearity of a pair of ADCs (see Section 4.0 “Terminology and Formulas” for the definition of measurement error). The measurement error is dependent on the THD and on the noise floor of the ADCs. Improving the measurement error specification on the MCP3912 can be realized by increasing the OSR (to get a better SINAD and THD performance), and to some extent, the BOOST settings (if the bandwidth of the measurements is too limited by the bandwidth of the amplifiers in the Sigma-Delta ADCs). In most of the energy metering AC applications, High-Pass Filters are used to cancel the offset on each ADC channel (current and voltage channels), and therefore, a single point calibration is necessary to calibrate the system for active energy measurement. This calibration is a system gain calibration, and the user can utilize the EN_GAINCAL bit and the GAINCAL_CHn registers to perform this digital calibration. After such calibration, typical measurement error curves, such as in Figure 2-7, can be generated by sweeping the current channel amplitude and measuring the energy at the outputs (the energy calculations here are being realized off-chip). The error is measured using a gain of 1x, as it is commonly used in most CT-based applications.  2014-2020 Microchip Technology Inc. At low signal amplitude values (typically 1000:1 dynamic range and higher), the crosstalk between channels, mainly caused by the PCB, becomes a significant part of the perturbation as the measurement error increases. The 1-point measurement error curves in Figure 2-5 have been performed with a full-scale sine wave on all the inputs that are not measured, which means that these channels induce a maximum amount of crosstalk on the measurement error curve. In order to avoid such behavior, a 2-point calibration can be put in place in the calculation section. This 2-point calibration can be a simple linear interpolation between two calibration points (one at high amplitudes, one at low amplitudes at each end of the dynamic range) and helps to significantly lower the effect of crosstalk between channels. A 2-point calibration is very effective in maintaining the measurement error close to zero on the whole dynamic range, since the nonlinearity and distortion of the MCP3912 are very low. Figure 2-6 shows the measurement error curves obtained with the same ADC data taken for Figure 2-5, but where a 2-point calibration has been applied. The difference is significant only at the low end of the dynamic range, where all the perturbing factors are a bigger part of the ADC output signals. These curves show extremely tight measurement error across the full dynamic range (here, typically 10,000:1), which is required in high-accuracy class meters. DS20005348C-page 55 MCP3912 NOTES: DS20005348C-page 56  2014-2020 Microchip Technology Inc. MCP3912 8.0 MCP3912 INTERNAL REGISTERS The addresses associated with the internal registers are listed in Table 8-1. This section also describes the registers in detail. All registers are 24-bit long registers, which can be addressed and read separately. TABLE 8-1: The format of the data registers (0x00 to 0x03) can be changed with the WIDTH_DATA[1:0] bits in the STATUSCOM register. The READ[1:0] and WRITE bits define the groups and types of registers for continuous read/write communication or looping on address sets, as shown in Table 8-2. MCP3912 REGISTER MAP Address Name Bits R/W Description 0x00 CHANNEL0 24 R Channel 0 ADC Data[23:0], MSB First 0x01 CHANNEL1 24 R Channel 1 ADC Data[23:0], MSB First 0x02 CHANNEL2 24 R Channel 2 ADC Data[23:0], MSB First 0x03 CHANNEL3 24 R Channel 3 ADC Data[23:0], MSB First 0x04 Unused 24 U Unused 0x05 Unused 24 U Unused 0x06 Unused 24 U Unused 0x07 Unused 24 U Unused 0x08 MOD 24 R/W Delta-Sigma Modulators Output Value 0x09 Unused 24 R/W Unused 0x0A PHASE 24 R/W Phase Delay Configuration Register – Channel Pairs 0/1 and 2/3 0x0B GAIN 24 R/W Gain Configuration Register 0x0C STATUSCOM 24 R/W Status and Communication Register 0x0D CONFIG0 24 R/W Configuration Register 0x0E CONFIG1 24 R/W Configuration Register 0x0F OFFCAL_CH0 24 R/W Offset Correction Register – Channel 0 0x10 GAINCAL_CH0 24 R/W Gain Correction Register – Channel 0 0x11 OFFCAL_CH1 24 R/W Offset Correction Register – Channel 1 0x12 GAINCAL_CH1 24 R/W Gain Correction Register – Channel 1 0x13 OFFCAL_CH2 24 R/W Offset Correction Register – Channel 2 0x14 GAINCAL_CH2 24 R/W Gain Correction Register – Channel 2 0x15 OFFCAL_CH3 24 R/W Offset Correction Register – Channel 3 0x16 GAINCAL_CH3 24 R/W Gain Correction Register – Channel 3 0x17 Unused 24 U Unused 0x18 Unused 24 U Unused 0x19 Unused 24 U Unused 0x1A Unused 24 U Unused 0x1B Unused 24 U Unused 0x1C Unused 24 U Unused 0x1D Unused 24 U Unused 0x1E Unused 24 U Unused 0x1F LOCK/CRC 24 R/W  2014-2020 Microchip Technology Inc. Security Register (Password and CRC-16 on Register Map) DS20005348C-page 57 MCP3912 TABLE 8-2: REGISTER MAP GROUPING FOR ALL CONTINUOUS READ/WRITE MODES READ[1:0] 0x02 CHANNEL 3 0x03 MOD 0x08 PHASE 0x0A GAIN 0x0B STATUSCOM 0x0C CONFIG0 0x0D CONFIG1 0x0E OFFCAL_CH0 0x0F GAINCAL_CH0 0x10 OFFCAL_CH1 0x11 GAINCAL_CH1 0x12 OFFCAL_CH2 0x13 GAINCAL_CH2 0x14 OFFCAL_CH3 0x15 GAINCAL_CH3 0x16 LOCK/CRC 0x1F = 00 =1 =0 GROUP Static Not Writable (Address undefined for Write access) CHANNEL 2 = 01 Not Writable (Address undefined for Write access) 0x01 Static TYPE 0x00 LOOP ENTIRE REGISTER MAP CHANNEL 0 CHANNEL 1 = 10 GROUP Static Static GROUP Static Static Static Static Static GROUP Static Static Static GROUP Static Static GROUP Static Static GROUP Static Static GROUP Static Static GROUP Static LOOP ONLY ON WRITABLE REGISTERS = 11 DS20005348C-page 58 WRITE Address TYPE Function Static Static Static Static Static Static Static Static Static Static Static Static Static  2014-2020 Microchip Technology Inc. MCP3912 8.1 The ADC Channel Data Output registers always contain the most recent A/D conversion data for each channel. These registers are read-only. They can be accessed independently or linked together (with the READ[1:0] bits). These registers are latched when an ADC read communication occurs. When a data ready event occurs during a read communication, the most current ADC data are also latched to avoid data corruption issues. These registers are updated and latched together if DR_LINK = 1, synchronously with the data ready pulse (toggling on the most lagging ADC channel data ready event). CHANNEL Registers – ADC Channel Data Output Registers Name Bits Address Cof. CHANNEL0 24 0x00 R CHANNEL1 24 0x01 R CHANNEL2 24 0x02 R CHANNEL3 24 0x03 R REGISTER 8-1: R-0 (MSB) MCP3912 CHANNEL REGISTERS R-0 R-0 R-0 R-0 R-0 R-0 R-0 DATA_CHn[23:16] bit 23 bit 16 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 DATA_CHn[15:8] bit 15 bit 8 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 DATA_CHn[7:0] bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 23-0 x = Bit is unknown DATA_CHn[23:0]: ADC Channel n Output Code bits These data are post-calibration if the EN_OFFCAL or EN_GAINCAL bits are enabled. These data can be formatted in 16-/24-/32-bit modes depending on the WIDTH_DATA[1:0] bits setting (see Section 5.5 “ADC Output Coding”).  2014-2020 Microchip Technology Inc. DS20005348C-page 59 MCP3912 8.2 MOD Register – Modulators Output Register Name Bits Address Cof. MOD 24 0x08 R/W REGISTER 8-2: The MOD register contains the most recent modulator data output and is updated at a DMCLK rate. The default value corresponds to an equivalent input of 0V on all ADCs. Each bit in this register corresponds to one comparator output on one of the channels. Do not write to this register to ensure the accuracy of each ADC. MOD REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 23 bit 16 R/W-0 R/W-0 R/W-1 R/W-1 R/W-0 R/W-0 R/W-1 R/W-1 COMP3_CH3 COMP2_CH3 COMP1_CH3 COMP0_CH3 COMP3_CH2 COMP2_CH2 COMP1_CH2 COMP0_CH2 bit 15 bit 8 R/W-0 R/W-0 R/W-1 R/W-1 R/W-0 R/W-0 R/W-1 R/W-1 COMP3_CH1 COMP2_CH1 COMP1_CH1 COMP0_CH1 COMP3_CH0 COMP2_CH0 COMP1_CH0 COMP0_CH0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 23-16 Unimplemented: Read as ‘0’ bit 15-12 COMPn_CH3: Comparator Outputs from ADC Channel 3 bits bit 11-8 COMPn_CH2: Comparator Outputs from ADC Channel 2 bits bit 7-4 COMPn_CH1: Comparator Outputs from ADC Channel 1 bits bit 3-0 COMPn_CH0: Comparator Outputs from ADC Channel 0 bits DS20005348C-page 60 x = Bit is unknown  2014-2020 Microchip Technology Inc. MCP3912 8.3 PHASE Register – Phase Configuration Register for Channel Pairs 2/3 and 0/1 Name Bits Address Cof. PHASE 24 0x0A R/W Any write to this register automatically resets and restarts all active ADCs. REGISTER 8-3: R/W-0 PHASE REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PHASEB[11] PHASEB PHASEB PHASEB PHASEB PHASEB PHASEB PHASEB bit 23 bit 16 R/W-0 R/W-0 R/W-0 PHASEB[3] PHASEB