MCP39F511A-E/MQ

MCP39F511A AC/DC Dual-Mode Power-Monitoring IC with Calculation and Energy Accumulation Features Applications • Real-Time Measurement of Input Power for AC or DC Supplies • AC/DC Dual-Mode Power Monitoring Accuracy Capable of 0.1% Error Across 4000:1 Dynamic Range • Automatic Sensing and Switching Between AC and DC Modes • Built-In Calculations on Fast 16-Bit Processing Core - Active and Reactive Energy Accumulation - Active, Reactive, Apparent Power - True RMS Current, RMS Voltage - Line Frequency, Power Factor • 64-bit Wide Import and Export Active Energy Accumulation Registers • 64-bit Four Quadrant Reactive Energy Accumulation Registers • Automatic Saving the Energy Accumulation Registers into EEPROM at Power Off • Automatic Loading the Energy Accumulation Registers from EEPROM at Power On • Signed Active and Reactive Power Outputs • Dedicated Zero Crossing Detection (ZCD) Pin Output with Less than 200 µs Latency • Dedicated PWM Output Pin with Programmable Frequency and Duty Cycle • Automatic Event Pin Control through Fast Voltage Sag/Surge Detection • Two Wire Serial Protocol with Selectable Baud Rate Up to 115.2 kbps using Universal Asynchronous Receiver/Transmitter (UART) • Four Independent Registers for Minimum and Maximum Output Quantity Tracking • Fast Calibration Routines and Simplified Command Protocol • 512 Bytes User-Accessible EEPROM through Page Read/Write Commands • Low-Drift Internal Voltage Reference, 7 ppm/°C Typical • 28-lead 5x5 QFN Package • Extended Temperature Range -40°C to +125°C • Power Monitoring and Management for Smart Home/City • Industrial Lighting Power Monitoring • Power Measurement for Renewable Energy System • Intelligent Power Distribution Units • Server Power Monitor Description The MCP39F511A device is a highly-integrated, complete single-phase power-monitoring IC designed for real-time measurement of input power for AC or DC power supplies, making it suitable for a wide range of consumer and industrial applications. It is capable of detecting the input voltage in order to work as DC or AC mode. It includes dual-channel Delta-Sigma ADCs, a 16-bit calculation engine, EEPROM and a flexible 2-wire interface. Separate AC and DC calibration registers are provided, to ensure high-accuracy measurements in both modes. An integrated low-drift voltage reference with 7 ppm/°C in addition to 94.5 dB of SINAD performance on each measurement channel allows for better than 0.1% accurate designs across a 4000:1 dynamic range. Package Types ZCD REFIN+/OUT MCLR DVDD DGND DGND DR MCP39F511A 5x5 QFN* 28 27 26 25 24 23 22 21 AGND EVENT1 1 NC 2 20 AN_IN NC 3 19 V1+ EP 29 UART_RX 4 COMMONA 5 18 V117 I116 I1+ OSCI 6 15 EVENT2 OSCO 7 PWM COMMONB UART_TX AVDD NC 9 10 11 12 13 14 RESET NC 8 *Includes Exposed Thermal Pad (EP); see Table 3-1.  2018 Microchip Technology Inc. DS20006044A-page 1 MCP39F511A Functional Block Diagram I1+ I1- V1+ V1- + PGA - + PGA - AN_IN DS20006044A-page 2 AVDD AGND DVDD DGND Internal Oscillator 24-bit Delta-Sigma Multi-level Modulator ADC 24-bit Delta-Sigma Multi-level Modulator ADC 10-bit SAR ADC SINC3 Digital Filter OSCO Timing Generation SINC3 Digital Filter OSCI UART Serial Interface 16-BIT CORE FLASH UART_TX UART_RX PWM EVENT1 Calculation Engine (CE) EVENT2 Digital Outputs ZCD  2018 Microchip Technology Inc. MCP39F511A MCP39F511A Typical Application – Single Phase, Two-Wire Application Schematic 10  1 µF LOAD 0.1 µF 0.1 µF AVDD DVDD RESET 1 k REFIN/OUT+ I1+ + +3.3V 0.1 µF +3.3V 33 nF 2 m - 1 k to MCU UART I133 nF UART_TX 1 k V1- UART_RX 33 nF to MCU UART MCP39F511A 499 k 499 k V1+ (OPTIONAL) 1 k 33 nF N.C. Leave Floating Connect on PCB +3.3V MCP9700A NC NC NC NC DR COMMONA,B EVENT2 ZCD AN_IN PWM OSCO 4 MHz OSCI 22 pF EVENT1 DGND AGND 22 pF (OPTIONAL) +3.3V 0.47 µ F 470 MCP1754 0.01 µF L N DGND 470 µF AGND Note 1: The MCP39F511A demonstration board uses a switching power supply, however a low-cost capacitive-based supply, as shown here, is sufficient for many applications. 2: The external sensing components shown here, a 2 m shunt, two 499 k and 1 k resistors for the 1000:1 voltage divider, are specifically chosen to match the default values for the calibration registers defined in Section 6.0 “Register Descriptions”. By choosing low-tolerance components of these values (for instance 1% tolerance), measurement accuracy in the 2-3% range can be achieved with zero calibration (AC only, offset calibration may be needed in DC mode). See Section 9.0 “MCP39F511A Calibration” for more information.  2018 Microchip Technology Inc. DS20006044A-page 3 MCP39F511A 1.0 † Notice: Stresses above those listed under “Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings † DVDD .................................................................. -0.3 to +4.5V AVDD .................................................................. -0.3 to +4.0V Digital inputs and outputs w.r.t. AGND ............... -0.3V to +4.0V Analog Inputs (I+,I-,V+,V-) w.r.t. AGND ............... ....-2V to +2V VREF input w.r.t. AGND ........................ ....-0.6V to AVDD +0.6V Maximum Current out of DGND pin..............................300 mA Maximum Current into DVDD pin.................................250 mA Maximum Output Current Sunk by Digital IO ................25 mA Maximum Current Sourced by Digital IO.......................25 mA Storage temperature .....................................-65°C to +150°C Ambient temperature with power applied......-40°C to +125°C Soldering temperature of leads (10 seconds) ............. +300°C ESD on the analog inputs (HBM,MM) .................4.0 kV, 200V ESD on all other pins (HBM,MM) ........................4.0 kV, 200V 1.1 Specifications TABLE 1-1: ELECTRICAL CHARACTERISTICS Electrical Specifications: Unless otherwise indicated, all parameters apply at AVDD, DVDD = +2.7 to +3.6V, TA = -40°C to +125°C, MCLK = 4 MHz, PGA GAIN = 1. Characteristic Sym. Min. Typ. Max. Units Test Conditions Active Power (Note 1) P — ±0.1 — % 4000:1 Dynamic range on current channel (Note 2) Reactive Power (Note 1) Q — ±0.1 — % 4000:1 Dynamic range on current channel (Note 2) Apparent Power (Note 1) S — ±0.1 — % 4000:1 Dynamic range on current channel (Note 2) Current RMS (Note 1) IRMS — ±0.1 — % 4000:1 Dynamic range on current channel (Note 2) Voltage RMS (Note 1) VRMS — ±0.1 — % 4000:1 (DC mode), 20:1 (AC mode) Dynamic range on voltage channel (Note 2, 8) Power Factor (Note 1)  — ±0.1 — % Line Frequency (Note 1) LF — ±0.1 — % 2N x (1/fLINE) — ms Power Measurement Calibration, Calculation and Event Detection Times Auto-Calibration Time Note 1: 2: 3: 4: 5: 6: 7: 8: tCAL — Note 3 Calculated from reading the register values with no averaging, single computation cycle with accumulation interval of 4 line cycles. Specification by design and characterization; not production tested. N = Value in the Accumulation Interval Parameter register. The default value of this register is 2 or TCAL = 80 ms for 50 Hz line. Applies to Voltage Sag and Voltage Surge events only. Applies to all gains. Offset and gain errors depend on the PGA gain setting. See Section 2.0 “Typical Performance Curves” for typical performance. VIN = 1.2 VPP = 424 mVRMS @ 50/60 Hz. This parameter is established by characterization and is not 100% tested. Variation applies to internal clock and UART only. All calculated output quantities can be temperature compensated to the performance listed in the respective specification. The internal ADC clock frequency is affected by the amplitude of the AC signal applied on the voltage channel, decreasing the overall accuracy if the amplitude is low. In DC mode, the internal ADC clock frequency is constant. DS20006044A-page 4  2018 Microchip Technology Inc. MCP39F511A TABLE 1-1: ELECTRICAL CHARACTERISTICS (CONTINUED) Electrical Specifications: Unless otherwise indicated, all parameters apply at AVDD, DVDD = +2.7 to +3.6V, TA = -40°C to +125°C, MCLK = 4 MHz, PGA GAIN = 1. Characteristic Minimum Time for Voltage Surge/Sag Detection Sym. Min. Typ. Max. Units tAC_SASU — 5, see Section 7.2 — ms Test Conditions Note 4 24-Bit Delta-Sigma ADC Performance Analog Input Absolute Voltage VIN -1 — +1 V Analog Input Leakage Current AIN — 1 — nA Differential Input Voltage Range (I1+ – I1-), (V1+ – V1-) -600/GAIN — +600/GAIN mV VOS -1 — +1 mV Offset Error — 0.5 — V/°C GE -4 — +4 % — 1 — ppm/°C ZIN 232 — — k G=1 142 — — k G=2 72 — — k G=4 38 — — k G=8 36 — — k G = 16 Offset Error Drift Gain Error Gain Error Drift Differential Input Impedance Signal-to-Noise and Distortion Ratio VREF = 1.2V, proportional to VREF SINAD Note 5 33 — — k G = 32 92 94.5 — dB Note 6 Total Harmonic Distortion THD — -106.5 -103 dBc Note 6 Signal-to-Noise Ratio SNR 92 95 — dB Note 6 Spurious Free Dynamic Range SFDR — 111 — dB Note 6 Crosstalk CTALK — -122 — dB AC Power Supply Rejection Ratio AC PSRR — -73 — dB AVDD and DVDD = 3.3V + 0.6VPP, 100 Hz, 120 Hz, 1 kHz DC Power Supply Rejection Ratio DC PSRR — -73 — dB AVDD and DVDD = 3.0 to 3.6V DC Common Mode Rejection Ratio DC CMRR — -105 — dB VCM varies from -1V to +1V — bits 10-Bit SAR ADC Performance for Temperature Measurement Resolution Note 1: 2: 3: 4: 5: 6: 7: 8: NR — 10 Calculated from reading the register values with no averaging, single computation cycle with accumulation interval of 4 line cycles. Specification by design and characterization; not production tested. N = Value in the Accumulation Interval Parameter register. The default value of this register is 2 or TCAL = 80 ms for 50 Hz line. Applies to Voltage Sag and Voltage Surge events only. Applies to all gains. Offset and gain errors depend on the PGA gain setting. See Section 2.0 “Typical Performance Curves” for typical performance. VIN = 1.2 VPP = 424 mVRMS @ 50/60 Hz. This parameter is established by characterization and is not 100% tested. Variation applies to internal clock and UART only. All calculated output quantities can be temperature compensated to the performance listed in the respective specification. The internal ADC clock frequency is affected by the amplitude of the AC signal applied on the voltage channel, decreasing the overall accuracy if the amplitude is low. In DC mode, the internal ADC clock frequency is constant.  2018 Microchip Technology Inc. DS20006044A-page 5 MCP39F511A TABLE 1-1: ELECTRICAL CHARACTERISTICS (CONTINUED) Electrical Specifications: Unless otherwise indicated, all parameters apply at AVDD, DVDD = +2.7 to +3.6V, TA = -40°C to +125°C, MCLK = 4 MHz, PGA GAIN = 1. Characteristic Sym. Min. Typ. Max. Absolute Input Voltage VIN DGND - 0.3 — DVDD + 0.3 V Recommended Impedance of Analog Voltage Source RIN — — 2.5 k Integral Nonlinearity INL — ±1 ±2 LSb Differential Nonlinearity DNL — ±1 ±1.5 LSb Gain Error GERR — ±1 ±3 LSb Offset Error EOFF — ±1 ±2 LSb — sps Note 7 See Section 3.2 for protocol details Temperature Measurement Rate — fLINE/2 N Units Test Conditions Clock and Timings UART Baud Rate UDB 1.2 9.6 115.2 kbps Master Clock and Crystal Frequency fMCLK -2% 4 +2% MHz Capacitive Loading on OSCO pin COSC2 — — 15 pF When an external clock is used to drive the device Internal Oscillator Tolerance fINT_OSC — 2 — % -40 to +85°C only (Note 7) VREF -2% 1.2 +2% V VREFEXT = 0, TA = +25°C only TCVREF — 7 — ZOUTVREF — 2 — k VREFEXT = 0 AIDDVREF — 25 — A VREFEXT = 0 SHUTDOWN = 11 Internal Voltage Reference Internal Voltage Reference Tolerance Temperature Coefficient Output Impedance Current, VREF Note 1: 2: 3: 4: 5: 6: 7: 8: ppm/°C TA = -40°C to +125°C, VREFEXT = 0 Calculated from reading the register values with no averaging, single computation cycle with accumulation interval of 4 line cycles. Specification by design and characterization; not production tested. N = Value in the Accumulation Interval Parameter register. The default value of this register is 2 or TCAL = 80 ms for 50 Hz line. Applies to Voltage Sag and Voltage Surge events only. Applies to all gains. Offset and gain errors depend on the PGA gain setting. See Section 2.0 “Typical Performance Curves” for typical performance. VIN = 1.2 VPP = 424 mVRMS @ 50/60 Hz. This parameter is established by characterization and is not 100% tested. Variation applies to internal clock and UART only. All calculated output quantities can be temperature compensated to the performance listed in the respective specification. The internal ADC clock frequency is affected by the amplitude of the AC signal applied on the voltage channel, decreasing the overall accuracy if the amplitude is low. In DC mode, the internal ADC clock frequency is constant. DS20006044A-page 6  2018 Microchip Technology Inc. MCP39F511A TABLE 1-1: ELECTRICAL CHARACTERISTICS (CONTINUED) Electrical Specifications: Unless otherwise indicated, all parameters apply at AVDD, DVDD = +2.7 to +3.6V, TA = -40°C to +125°C, MCLK = 4 MHz, PGA GAIN = 1. Characteristic Sym. Min. Typ. Max. Units — — 10 pF AGND + 1.1V — AGND + 1.3V V Test Conditions Voltage Reference Input Input Capacitance Absolute Voltage on VREF+ Pin VREF+ Power Specifications Operating Voltage AVDD, DVDD 2.7 — 3.6 V DVDD Start Voltage to Ensure Internal Power-On Reset Signal VPOR DGND — 0.7 V DVDD Rise Rate to Ensure Internal Power-On Reset Signal SDVDD 0.05 — — V/ms AVDD Start Voltage to Ensure Internal Power-On Reset Signal VPOR AGND — 2.1 V AVDD Rise Rate to Ensure Internal PowerOn Reset Signal SAVDD 0.042 — — V/ms IDD — 13 — mA Cell Endurance EPS 100,000 — — E/W Self-Timed Write Cycle Time TIWD — 4 — ms Number of Total Write/Erase Cycles Before Refresh RREF — 10,000,000 — E/W TRETDD 40 — — years IDDPD — 7 — mA Operating Current 0–3.3V in 0.1s, 0–2.5V in 60 ms 0 – 2.4V in 50 ms Data EEPROM Memory Characteristic Retention Supply Current During Programming Note 1: 2: 3: 4: 5: 6: 7: 8: Provided no other specifications are violated Calculated from reading the register values with no averaging, single computation cycle with accumulation interval of 4 line cycles. Specification by design and characterization; not production tested. N = Value in the Accumulation Interval Parameter register. The default value of this register is 2 or TCAL = 80 ms for 50 Hz line. Applies to Voltage Sag and Voltage Surge events only. Applies to all gains. Offset and gain errors depend on the PGA gain setting. See Section 2.0 “Typical Performance Curves” for typical performance. VIN = 1.2 VPP = 424 mVRMS @ 50/60 Hz. This parameter is established by characterization and is not 100% tested. Variation applies to internal clock and UART only. All calculated output quantities can be temperature compensated to the performance listed in the respective specification. The internal ADC clock frequency is affected by the amplitude of the AC signal applied on the voltage channel, decreasing the overall accuracy if the amplitude is low. In DC mode, the internal ADC clock frequency is constant.  2018 Microchip Technology Inc. DS20006044A-page 7 MCP39F511A TABLE 1-2: SERIAL DC CHARACTERISTICS Electrical Specifications: Unless otherwise indicated, all parameters apply at AVDD, DVDD = +2.7 to+ 3.6V, TA = -40°C to +125°C, MCLK = 4 MHz Characteristic Sym. Min. Typ. Max. Units VIH 0.8 DVDD — DVDD V Low-Level Input Voltage VIL 0 — 0.2 DVDD V High-Level Output Voltage VOH 3 — — V IOH = -3.0 mA, VDD = 3.6V Low-Level Output Voltage VOL — — 0.4 V IOL = 4.0 mA, VDD = 3.6V ILI — — 1 A 0.050 0.100 High-Level Input Voltage Input Leakage Current TABLE 1-3: Test Conditions Digital Output pins only (ZCD, PWM, EVENT1, EVENT2) TEMPERATURE SPECIFICATIONS Electrical Specifications: Unless otherwise indicated, all parameters apply at AVDD, DVDD = +2.7 to +3.6V. Parameters Sym. Min. Typ. Max. Units Operating Temperature Range TA -40 — +125 °C Storage Temperature Range TA -65 — +150 °C JA — 36.9 — °C/W Conditions Temperature Ranges Thermal Package Resistances Thermal Resistance, 28LD 5x5 QFN DS20006044A-page 8  2018 Microchip Technology Inc. MCP39F511A 2.0 TYPICAL PERFORMANCE CURVES The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore outside the warranted range. Note: 0.50% 0.40% 0.30% 0.20% 0.10% 0.00% -0.10% -0.20% -0.30% -0.40% -0.50% 0.01 0.1 1 10 100 1000 Current Channel Input Amplitude (mVPEAK) FIGURE 2-1: Active Power, Gain = 1. 0 fIN = -60 dBFS @ 60 Hz fD = 3.9 ksps 16384 pt FFT OSR = 256 -20 -40 Amplitude (dB) Measurement Error (%) Note: Unless otherwise indicated, AVDD = +3.3V, DVDD = +3.3V, TA = +25°C, GAIN = 1, VIN = -0.5 dBFS at 60 Hz. -60 -80 -100 -120 -140 -160 -180 -200 0 200 400 600 800 1000 1200 1400 1600 1800 2000 Frequency (Hz) FIGURE 2-4: Spectral Response. RMS Current, Gain = 1. 1 0.8 0.6 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 -1 1 10 100 1000 10000 -105.8 -105.9 -106.1 -106.2 Total Harmonic Distortion (-dBc) FIGURE 2-5: Total HDrmonic Distortion(dBc) Energy Accumulation Error (%) FIGURE 2-2: 1000 -106.4 1 10 100 Input Voltage RMS (mVPP) -106.5 0.1 -106.7 -0.100% -106.8 -0.050% -107.0 0.000% -107.1 0.050% -107.3 Frequency of Occurrence RMS Current Error (%) 0.100% 100000 THD Histogram. 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 G=1 G=8 -50 -25 0 G=2 G = 16 25 50 75 Temperature (°C) G=4 G = 32 100 125 150 Energy Accumulation (Watt-Hours) FIGURE 2-3: Energy, Gain = 8.  2018 Microchip Technology Inc. FIGURE 2-6: THD vs. Temperature. DS20006044A-page 9 MCP39F511A Note: Unless otherwise indicated, AVDD = 3.3V, DVDD = 3.3V, TA = +25°C, GAIN = 1, VIN = -0.5 dBFS at 60 Hz. 5 4 Gain Error (%) Frequency of Occurrence 3 2 1 0 -1 -2 -3 G=1 G=8 -4 -5 94.2 94.3 94.5 94.6 94.8 94.9 95.1 95.2 95.4 95.5 Signal-to-Noise and Distortion Ratio (dB) SNR Histogram. -25 0 25 50 75 G=4 G = 32 100 125 150 Temperature (°C) FIGURE 2-9: Gain Error vs. Temperature. 1.2008 100 90 80 70 60 50 40 30 20 10 0 G=1 G=8 -50 -25 0 FIGURE 2-8: DS20006044A-page 10 G=2 G = 16 G=4 G = 32 25 50 75 100 125 150 Temperature (°C) SINAD vs. Temperature. Internal Voltage Reference (V) Signal-to-Noise and Distortion Ratio (dB) FIGURE 2-7: -50 G=2 G = 16 1.2007 1.2006 1.2005 1.2004 1.2003 1.2002 1.2001 1.2000 1.1999 -50 FIGURE 2-10: vs. Temperature. 0 50 100 Temperature (C) 150 Internal Voltage Reference  2018 Microchip Technology Inc. MCP39F511A 3.0 PIN DESCRIPTION The description of the pins are listed in Table 3-1. TABLE 3-1: PIN FUNCTION TABLE MCP39F511A 5x5 QFN Symbol 1 EVENT1 2, 3, 8, 9 NC Function Event 1 Output pin No Connect (must be left floating) 4 UART_RX UART Communication RX pin 5 COMMONA Common pin A, to be connected to pin 13 (COMMONB) 6 OSCI Oscillator Crystal Connection pin or External Clock Input pin 7 OSCO Oscillator Crystal Connection pin 10 RESET Reset pin for Delta-Sigma ADCs 11 AVDD 12 UART_TX Analog Power Supply pin UART Communication TX pin 13 COMMONB 14 PWM 15 EVENT2 16 I1+ Noninverting Current Channel Input for 24-bit  ADC 17 I1- Inverting Current Channel Input for 24-bit  ADC 18 V1- Inverting Voltage Channel Input for 24-bit  ADC 19 V1+ Noninverting Voltage Channel Input for 24-bit  ADC 20 AN_IN Analog Input for SAR ADC 21 AGND Analog Ground Pin, return path for internal analog circuitry 22 ZCD Zero Crossing Detection Output 23 REFIN+/OUT Common pin B, to be connected to pin 5 (COMMONA) Pulse-Width Modulation (PWM) Output pin Event 2 Output pin Noninverting Voltage Reference Input and Internal Reference Output pin 24, 27 DGND Digital Ground pin, return path for internal digital circuitry 25 DVDD Digital Power Supply pin 26 MCLR Master Clear for device 28 DR Data Ready (must be left floating) 29 EP Exposed Thermal Pad (to be connected to pins 24 and 27 (DGND))  2018 Microchip Technology Inc. DS20006044A-page 11 MCP39F511A 3.1 Event Output Pins (EVENTn) These digital output pins can be configured to act as output flags based on various internal raise conditions. Control is modified through the Event Configuration register. 3.2 UART Communication Pins (UART_RX, UART_TX) 3.8 24-Bit Delta-Sigma ADC Differential Current Channel Input Pins (I1+/I1-) I1- and I1+ are the two fully-differential current-channel inputs for the Delta-Sigma ADCs. The linear and specified region of the channels are dependent on the PGA gain. This region corresponds to a differential voltage range of ±600 mVPEAK/GAIN with VREF = 1.2V. The MCP39F511A device contains an asynchronous full-duplex UART. The UART communication is eight bits with Start and Stop bit. See Section 4.3 “UART Settings” for more information. The maximum absolute voltage, with respect to AGND, for each In+/- input pin is ±1V with no distortion and ±6V with no breaking after continuous voltage. 3.3 3.9 Common Pins (COMMONA and B) COMMONA and COMMONB pins are internal connections for the MCP39F511A. These two pins should be connected together in the application. 3.4 Oscillator Pins (OSCI/OSCO) 24-Bit Delta-Sigma ADC Differential Voltage Channel Inputs (V1-/V1+) V1- and V1+ are the two fully-differential voltage-channel inputs for the Delta-Sigma ADCs. The linear and specified region of the channels are dependent on the PGA gain. This region corresponds to a differential voltage range of ±600 mVPEAK/GAIN with VREF = 1.2V. OSCI and OSCO provide the master clock for the device. Appropriate load capacitance should be connected to these pins for proper operation. An optional 4 MHz crystal can be connected to these pins. If a crystal of external clock source is not detected, the device will clock from the internal 4 MHz oscillator. The maximum absolute voltage, with respect to AGND, for each VN+/- input pin is ±1V with no distortion and ±2V with no breaking after continuous voltage. 3.5 3.10 Reset Pin (RESET) This pin is active-low and places the Delta-Sigma ADCs, PGA, internal VREF and other blocks associated with the Analog Front End (AFE) in a Reset state when pulled low. This input is Schmitt-triggered. 3.6 Analog Power Supply Pin (AVDD) AVDD is the power supply pin for the analog circuitry within the MCP39F511A. This pin requires appropriate bypass capacitors and should be maintained to +2.7V and +3.6V for specified operation. It is recommended to use 0.1 µF ceramic capacitors. 3.7 Pulse-Width Modulator (PWM) This digital output is a dedicated PWM output that can be controlled through the PWM Frequency and PWM Duty Cycle registers. See Section 8.0 “Pulse Width Modulation (PWM)” for more information. DS20006044A-page 12 Analog Input (AN_IN) This is the input to the analog-to-digital converter that can be used for temperature measurement and compensation. If temperature compensation is required in the application, it is advised to connect the low-power active thermistor IC MCP9700A to this pin. If temperature compensation is not required, this can be used as a general purpose analog-to-digital converter input. 3.11 Analog Ground Pin (AGND) AGND is the ground connection to internal analog circuitry (ADCs, PGA, voltage reference, POR). If an analog ground plane is available on the PCB, it is recommended that this pin be tied to that plane. 3.12 Zero Crossing Detection (ZCD) This digital output pin is the output of the zero crossing detection circuit of the IC. The output here will be a logic output with edges that transition at each zero crossing of the voltage channel input. For more information see Section 5.13 “Zero Crossing Detection (ZCD)”.  2018 Microchip Technology Inc. MCP39F511A 3.13 Noninverting Reference Input/Internal Reference Output Pin (REFIN+/OUT) This pin is the noninverting side of the differential voltage reference input for the Delta-Sigma ADCs or the internal voltage reference output. For optimal performance, bypass capacitances should be connected between this pin and AGND at all times, even when the internal voltage reference is used. However, these capacitors are not mandatory to ensure proper operation. 3.14 Digital Ground Connection Pins (DGND) DGND is the ground connection to internal digital circuitry (SINC filters, oscillator, serial interface). If a digital ground plane is available, it is recommended to tie this pin to the digital plane of the PCB. This plane should also reference all other digital circuitry in the system. 3.15 Digital Power Supply Pin (DVDD) DVDD is the power supply pin for the digital circuitry within the MCP39F511A. This pin requires appropriate bypass capacitors and should be maintained between +2.7V and +3.6V for specified operation. It is recommended to use 0.1 µF ceramic capacitors. 3.16 Data-Ready Pin (DR) The data-ready pin indicates if a new Delta-Sigma A/D conversion result is ready to be processed. This pin is for indication only and should be left floating. After each conversion is finished, a low pulse will take place on the data-ready pin to indicate the conversion result is ready and an interrupt is generated in the calculation engine (CE). This pulse is synchronous with the line frequency to ensure an integer number of samples for each line cycle. Note: 3.17 This pin is internally connected to the IRQ of the calculation engine and should be left floating. Exposed Thermal Pad (EP) This pin is the exposed thermal pad. It must be connected to pin 24 (DGND).  2018 Microchip Technology Inc. DS20006044A-page 13 MCP39F511A NOTES: DS20006044A-page 14  2018 Microchip Technology Inc. MCP39F511A 4.0 COMMUNICATION PROTOCOL 4.1 After the reception of a communication frame, the MCP39F511A device has three possible responses, which will be returned with or without data depending on the frame received. These responses are: The communication protocol for the MCP39F511A device is based on the Simple Sensor Interface (SSI) protocol. This protocol is used for point-to-point communication from a single-host microcontroller (MCU) to a single-slave MCP39F511A device. • Acknowledge (ACK, 0x06): Frame received with success, commands understood and commands executed with success. • Negative Acknowledge (NAK, 0x15): Frame received with success, however commands not executed with success, commands not understood or some other error in the command bytes. • Checksum Fail (CSFAIL, 0x51): Frame received with success, however the checksum of the frame did not match the bytes in the frame. All communication to the device occurs in frames. Each frame consists of a header byte, the number of bytes in the frame, command packet (or command packets) and a checksum. It is important to note that the maximum number of bytes in either a receive or transmit frame is 35. Note: Device Responses If a custom communication protocol is desired, please contact a Microchip sales office. This approach allows for single, secure transmission from the host processor to the MCP39F511A device with either a single command or multiple commands. No command in a frame is processed until the entire frame is complete and the checksum and number of bytes are validated. Note: The number of bytes in an individual command packet depend on the specific command. For example, to set the instruction pointer, three bytes are needed in the packet: the command byte and two bytes for the address you want to set to the pointer. The first byte in a command packet is always the command byte. There is one unique device ID response that is used to determine which MCP39FXXX device is present: [NAK(0x15) + ID_BYTE]. If the command received is a single byte (0x5A) instead of a command frame, the response is NAK followed by the ID_BYTE. For the MCP39F511A device, the ID_BYTE is 0x04. This protocol can also be used to set up transmission from the MCP39F511A device on specific registers. A predetermined single-wire transmission frame is defined for one-wire interfaces. The Auto-Transmit mode can be initiated by setting the SINGLE_WIRE bit in the System Configuration register, allowing for single-wire communication within the application. See Section 4.8 “Single-Wire Transmission Mode” for more information on this communication. Frame Header Byte (0xA5) Number of Bytes Command Packet1 Command Packet2 ...Command Packet n Checksum Command BYTE1 BYTE2 BYTE N BYTE0 BYTE N FIGURE 4-1: Communication Frame MCP39F511A.  2018 Microchip Technology Inc. DS20006044A-page 15 MCP39F511A 4.2 Checksum The checksum is generated using simple byte addition and taking the modules to find the remainder after dividing the sum of the entire frame by 256. This operation is done to obtain an 8-bit checksum. All the bytes of the frame are included in the checksum, including the header byte and the number of bytes. If a frame includes multiple command packets, none of the commands will be issued if the frame checksum fails. In this instance, the MCP39F511A device will respond with a CSFAIL response of 0x51. On commands that are requesting data back from the MCP39F511A device, the frame and checksum are created in the same way, with the header byte becoming an Acknowledge (0x06). Communication examples are given in Section 4.5 “Example Communication Frames and MCP39F511A Responses”. 4.3 UART Settings The default baud rate is 9.6 kbps and can be changed using the UART bits in the System Configuration Register. Note that the baud rate is changed at system power-up, so when changing the baud rate, a Save To Flash command followed by a power-on cycle is required. The UART operates in 8-bit mode, plus one Start bit and one Stop bit, for a total of 10 bits per byte, as shown in Figure 4-2. IDLE START D0 D1 D2 FIGURE 4-2: DS20006044A-page 16 D3 D4 D5 D6 D7 STOP IDLE UART Transmission, N-8-1.  2018 Microchip Technology Inc. MCP39F511A 4.4 Command List The following table is a list of all accepted command bytes for the MCP39F511A device. There are 10 possible accepted commands for the MCP39F511A device. TABLE 4-1: MCP39F511A INSTRUCTION SET Command # Command Command ID Instruction Parameter Number of Bytes Successful Response UART_TX 1 Register Read, N bytes 0x4E NoB(3) 2 2 Register Write, N bytes 0x4D NoB(3) 1+N ACK 3 Set Address Pointer 0x41 ADDRESS 3 ACK 4 Save Registers To Flash 0x53 None 1 ACK 5 Page Read EEPROM 0x42 PAGE 2 ACK, NoB, data, checksum 6 Page Write EEPROM 0x50 PAGE 18 ACK 7 Bulk Erase EEPROM 0x4F None 1 8 Auto-Calibrate Gain 0x5A None Note 1 9 Auto-Calibrate Reactive Gain 0x7A None Note 1, 2 10 Auto-Calibrate Frequency 0x76 None 11 Save Energy Counters to EEPROM 0x45 None Note 1: 2: 3: 4.5 ACK, NoB, data, checksum ACK Note 1, 2 1 ACK See Section 9.0 “MCP39F511A Calibration” for more information. AC mode only NoB represents total number of bytes in frame Example Communication Frames and MCP39F511A Responses Tables 4-2 to 4-11 show exact hexadecimal communication frames as recommended to be sent to the MCP39F511A device from the system MCU. The values here can be used as direct examples for writing the code to communicate to the MCP39F511A device. TABLE 4-2: REGISTER READ, N BYTES COMMAND (Note 1) Byte # Value Description 1 0xA5 2 0x08 Number of Bytes in Frame 3 0x41 Command (Set Address Pointer) 4 0x00 Address High Response from MCP39F511A Header Byte 5 0x02 Address Low 6 0x4E Command (Register Read, N Bytes) 7 0x20 Number of Bytes to Read (32) 8 0x5E Checksum ACK + NoB (35) + data (32) + checksum Note 1: This example Register Read, N bytes frame, as it is written here, can be used to poll a subset of the output data, starting at the top, address 0x02, and reading 32 data bytes back or 35 bytes total in the frame.  2018 Microchip Technology Inc. DS20006044A-page 17 MCP39F511A TABLE 4-3: REGISTER WRITE, N BYTES COMMAND (Note 1) Byte # Value Description 1 0xA5 Header Byte 2 0x0C Number of Bytes in Frame 3 0x41 Command (Set Address Pointer) 4 0x00 Address High 5 0x94 Address Low 6 0x4D Command (Register Write, N Bytes) 7 0x04 Number of Bytes to Write (4) 8–11 *Data* 12 Checksum Response from MCP39F511A Data Bytes (4 total data bytes) Checksum ACK Note 1: This Register Write, N Bytes frame, as it is written here, can be used to write the System Configuration register, which controls the device configuration, including the ADC. See Register 6-2 for more information. TABLE 4-4: SET ADDRESS POINTER COMMAND (Note 1) Byte # Value Description Response from MCP39F511A 1 0xA5 2 0x06 Number of Bytes in Frame 3 0x41 Command (Set Address Pointer) 4 0x00 Address High 5 0x02 Address Low 6 0xF8 Checksum Header Byte ACK Note 1: The Set Address Pointer command is typically included inside of a frame that includes a read or write command, as shown in Tables 4-2 and 4-3. There is typically no reason for this command to have its own frame, but is shown here as an example. TABLE 4-5: SAVE TO FLASH COMMAND Byte # Value Description 1 0xA5 Header Byte 2 0x04 Number of Bytes in Frame 3 0x53 Command (Save To Flash) 4 0xFC Checksum TABLE 4-6: Response from MCP39F511A ACK PAGE READ EEPROM COMMAND Byte # Value 1 0xA5 2 0x05 Number of Bytes in Frame 3 0x42 Command (Page Read EEPROM) 4 0x01 Page Number (example: 1) 5 0xF8 Checksum DS20006044A-page 18 Description Response from MCP39F511A Header Byte ACK + NoB (19) + EEPROM Page Data (16) + Checksum  2018 Microchip Technology Inc. MCP39F511A TABLE 4-7: PAGE WRITE EEPROM COMMAND Byte # Value Description 1 0xA5 Header Byte 2 0x15 Number of Bytes in Frame 3 0x50 Command (Page Write EEPROM) 4 0x01 5-20 *Data* 21 Checksum TABLE 4-8: Page Number (e.g. 1) EEPROM Data (16 bytes/page) Checksum ACK BULK ERASE EEPROM COMMAND Byte # Value 1 0xA5 Header Byte 2 0x04 Number of Bytes in Frame 3 0x4F Command (Bulk Erase EEPROM) 4 0xF8 Checksum TABLE 4-9: Response from MCP39F511A Description Response from MCP39F511A ACK AUTO-CALIBRATE GAIN COMMAND Byte # Value 1 0xA5 Description Response from MCP39F511A Header Byte 2 0x04 Number of Bytes in Frame 3 0x5A Command (Auto-Calibrate Gain) 4 0x03 Checksum ACK (or NAK if unable to calibrate)1 Note 1: See Section 9.0 “MCP39F511A Calibration” for more information. TABLE 4-10: AUTO-CALIBRATE REACTIVE GAIN COMMAND Byte # Value Description 1 0xA5 Header Byte 2 0x04 Number of Bytes in Frame 3 0x7A Command (Auto-Calibrate Reactive Gain) 4 0x23 Checksum Response from MCP39F511A ACK (or NAK if unable to calibrate)1 Note 1: See Section 9.0 “MCP39F511A Calibration” for more information. TABLE 4-11: AUTO-CALIBRATE FREQUENCY COMMAND Byte # Value Description 1 0xA5 Header Byte 2 0x04 Number of Bytes in Frame 3 0x76 Command (Auto-Calibrate Frequency) 4 0x1F Checksum Response from MCP39F511A ACK (or NAK if unable to calibrate)1 Note 1: See Section 9.0 “MCP39F511A Calibration” for more information.  2018 Microchip Technology Inc. DS20006044A-page 19 MCP39F511A 4.6 4.6.1 Command Descriptions REGISTER READ, N BYTES (0x4E) 4.6.6 PAGE WRITE EEPROM (0x50) The Page Write EEPROM command is expecting 17 additional bytes in the command parameters, which are EEPROM page plus 16 bytes of data. A more complete description of the memory organization of the EEPROM can be found in Section 10.0 “EEPROM” The response to this command is an Acknowledge. The Register Read, N bytes command returns the N bytes that follow whatever the current address pointer is set to. It should typically follow a Set Address Pointer command and can be used in conjunction with other read commands. An Acknowledge NoB, Data and Checksum is the response for this command. The maximum number of bytes that can be read with this command is 32. If there are other read commands within a frame, the maximum number of bytes that can be read is 32 minus the number of bytes being read in the frame. With this command, the data is returned LSb first. The Bulk Erase EEPROM command will erase the entire EEPROM array and return it to a state of 0xFFFF for each memory location of EEPROM. A more complete description of the memory organization of the EEPROM can be found in Section 10.0 “EEPROM”. The response to this command is an Acknowledge. 4.6.2 4.6.8 REGISTER WRITE, N BYTES (0x4D) The Register Write, N bytes command is followed by N bytes that will be written to whatever the current address pointer is set to. It should typically follow a Set Address Pointer command and can be used in conjunction with other write commands. An Acknowledge is the response for this command. The maximum number of bytes that can be written with this command is 32. If there are other write commands within a frame, the maximum number of bytes that can be written is 32 minus the number of bytes being written in the frame. With this command, the data is written to the LSb first. 4.6.3 SET ADDRESS POINTER (0x41) This command is used to set the address pointer for all read and write commands. This command is expecting the address pointer as the command parameter in the following two bytes, Address High byte followed by Address Low byte. The address pointer is two bytes in length. If the address pointer is within the acceptable addresses of the device, an Acknowledge will be returned. 4.6.4 SAVE REGISTERS TO FLASH (0x53) The Save Registers To Flash command makes a copy of all the calibration and configuration registers to Flash. This includes all R/W registers in the register set. The response to this command is an Acknowledge. 4.6.5 PAGE READ EEPROM (0x42) The Page Read EEPROM command returns 16 bytes of data that are stored in an individual page on the MCP39F511A. A more complete description of the memory organization of the EEPROM can be found in Section 10.0 “EEPROM”. This command is expecting the EEPROM page as the command parameter or the following byte. The response to this command is an Acknowledge NoB, 16-bytes of data and CRC Checksum. DS20006044A-page 20 4.6.7 BULK ERASE EEPROM (0x4F) AUTO-CALIBRATE GAIN (0x5A) The Auto-Calibrate Gain command initiates the single-point calibration that is all that is typically required for the system. This command calibrates the RMS current, RMS voltage and active power based on the target values written in the corresponding registers. See Section 9.0 “MCP39F511A Calibration” for more information on device calibration. The response to this command is an Acknowledge. 4.6.9 AUTO-CALIBRATE REACTIVE POWER GAIN (0X7A) The Auto-Calibrate Reactive Gain command initiates a single-point calibration to match the measured reactive power to the target reactive power. This is typically done at PF = 0.5. See Section 9.0 “MCP39F511A Calibration” for more information on device calibration. 4.6.10 AUTO-CALIBRATE FREQUENCY (0x76) For applications not using an external crystal and running the MCP39F511A device off the internal oscillator, a gain calibration to the line frequency indication is required. The Gain Line Frequency register is set such that the frequency indication matches what is set in the Line Frequency Reference register. See Section 9.0 “MCP39F511A Calibration” for more information on device calibration. 4.6.11 SAVE ENERGY COUNTERS TO EEPROM (0x45) The Save Energy Counters to EEPROM command makes a copy of the energy counters to EEPROM. Import active and reactive energy counters are saved in PAGE 0. Export active and reactive energy counters are saved in PAGE 1. The bytes are written at incremental addresses, starting with the LSb. The response to this command is an Acknowledge.  2018 Microchip Technology Inc. MCP39F511A 4.7 Notation for Register Types The following notation has been adopted for describing the various registers used in the MCP39F511A: TABLE 4-12: Notation SHORT-HAND NOTATION FOR REGISTER TYPES Description u64 Unsigned, 64-bit register u32 Unsigned, 32-bit register s32 Signed, 32-bit register u16 Unsigned, 16-bit register s16 Signed, 16-bit register b32 32-bit register containing discrete Boolean bit settings 4.8 Single-Wire Transmission Mode In Single-Wire Transmission mode, at the end of each computation cycle, the device automatically transmits a frame of power data. This allows for single-wire communication after the device has been configured. The single-wire transmission frame consists of 20 bytes: three Header bytes, one checksum and 16 bytes of power data (including RMS current, RMS voltage, active power, reactive power and line frequency). TABLE 4-13: # Byte 1 HEADERBYTE (0xAB) 2 HEADERBYTE2 (0xCD) 3 HEADERBYTE3 (0xEF) 4 CURRENT RMS – Byte 0 5 CURRENT RMS – Byte 1 6 CURRENT RMS – Byte 2 7 CURRENT RMS – Byte 3 8 VOLTAGE RMS – Byte 0 9 VOLTAGE RMS – Byte 1 10 ACTIVE POWER – Byte 0 11 ACTIVE POWER – Byte 1 12 ACTIVE POWER – Byte 2 13 ACTIVE POWER – Byte 3 14 REACTIVE POWER – Byte 0 15 REACTIVE POWER – Byte 1 16 REACTIVE POWER – Byte 2 17 REACTIVE POWER – Byte 3 18 LINE FREQUENCY – Byte 0 19 LINE FREQUENCY – Byte 1 20 CHECKSUM Note 1:  2018 Microchip Technology Inc. SINGLE-WIRE TRANSMISSION FRAME (Note 1) For custom single-wire transmission packets, contact a Microchip sales office. DS20006044A-page 21 MCP39F511A NOTES: DS20006044A-page 22  2018 Microchip Technology Inc. MCP39F511A 5.0 CALCULATION ENGINE (CE) DESCRIPTION 5.1 Computation Cycle Overview The MCP39F511A device uses a coherent sampling algorithm to phase lock the sampling rate to the line frequency with an integer number of samples per line cycle (56), and reports all power output quantities at a 2N number of line cycles. This is defined as a computation cycle and is dependent on the line frequency, so any change in the line frequency will change the update rate of the power outputs. Assuming that the input frequency is 50 Hz, the sampling speed is 56 * 50 = 2800 samples/second. For the default accumulation interval parameter of 2, the computational cycle is 56 * 4 divided by the sampling speed (the result is 80 ms). In DC mode, the sampling speed is fixed at approximately 1953 samples/second. For the default value of the accumulation interval parameter (2), the computational cycle is 56 * 4 divided by the sampling speed (the result is approximately 114.7 ms). 5.1.1 LINE FREQUENCY The coherent sampling algorithm is also used to calculate the Line Frequency Output register, which is updated every computation cycle. The correction factor for line frequency measurement is the Gain Line Frequency register, which is used during the line frequency calibration, see Section 9.6.1 “Using the Auto-Calibrate Frequency Command”. Note that the resolution of the Line Frequency Output register is fixed, and the resolution is 1 milliHz. 5.1.2 as above, based on the number of zero crossings detected on the voltage channel), the device will switch to DC mode, turning off the high pass filters and setting the frequency output to zero. 5.2 Accumulation Interval Parameter The accumulation interval is defined as an 2N number of line cycles, where N is the value in the Accumulation Interval Parameter register. N can be as low as 0 (for the fastest update rate), but no bigger than 8. 5.3 Raw Voltage and Currents Signal Conditioning The first set of signal conditioning that occurs inside the MCP39F511A is shown in Figure 5-1. All conditions set in this diagram effect all of the output registers (RMS current, RMS voltage, Active power, Reactive power, Apparent power, etc.). The gain of the PGA, the Shutdown and Reset status of the 24-bit ADCs are all controlled through the System Configuration Register. For DC applications, offset can be removed by using the OFFCAL_CH0 and OFFCAL_CH1 registers for current offset and voltage offset, respectively. The OFFCAL_MSB register holds the most significant byte (MSB) for both the OFFCAL_CH0 (current) and OFFCAL_CH1 (voltage) calibration values and together add to the full 24-bit value written directly into the internal offset registers of the ADC. The Phase Compensation register is used to compensate for any external phase error between the voltage and current channels. See Section 9.0 “MCP39F511A Calibration” for more information on device calibration. POWER ON RESET (POR) WITH AC DETECTION BEHAVIOR At Power-on Reset, the calculation engine must initialize the AFE and also initialize all the peripherals, prior to being able to start the first computation cycle. In addition, the device must detect whether or not an AC signal is present and if so, determine the correct coherent sampling clock values. This process is given sufficient time for correct initialization and the start-up time is 500 ms for a 50 Hz line, and 417 ms for a 60 Hz line. The high pass filters are turned off to let pass both DC and AC signals. If the number of zero crossings detected during this time on the voltage channel is less than 10 (to filter out false detections), the device will automatically switch to DC mode. 5.1.3 DC DETECTION AND DC MODE The device uses an internal counter based on the sampling rate of the AFE to determine if an AC signal is not present and if the device should switch to DC mode. If an AC signal is not present for this time period (same  2018 Microchip Technology Inc. DS20006044A-page 23 MCP39F511A 5.4 RMS Current and RMS Voltage The MCP39F511A device provides true RMS measurements. The MCP39F511A device has two simultaneous sampling 24-bit A/D converters for the current and voltage measurements. The root mean square calculations are performed on 2N current and voltage samples, where N is defined by the register Accumulation Interval Parameter. EQUATION 5-1: RMS CURRENT AND VOLTAGE N 2 –1  in  n=0 ----------------------------N 2 I RMS = I1+  2 n=0 -----------------------------N 2 V RMS = 24-bit  ADC Multi-Level Modulator + PGA - I1-  vn  SINC3 Digital Filter  N 2 –1 2 + CHANNEL I1  i HPF 1 + Ch0_Offset:s24(2) SystemConfiguration:b32 Ch1_Offset:s24(2) PhaseCompensation:s16 SINC3 Digital Filter + PGA - V1+ V1- + 24-bit  ADC Multi-Level Modulator +   v HPF 1 CHANNEL V1 Note 1: High-Pass Filters (HPFs) are automatically disabled in the absence of an AC signal on the voltage channel. 2: Ch0_Offset and Ch1_Offset are 24-bit values. The 24-bit two's complement MSB first coding values are calculated internally using the corresponding byte from the OFFCAL_MSB register and OFFCAL_CHn 16-bit values. The result is added to the output code of the corresponding channel bit-by-bit. FIGURE 5-1: Channel I1 and V1 Signal Flow. Range:b32 i X 2N-1 0 ÷ 2 ACCU  N + X ÷2RANGE CurrentRMS:u32 + GainCurrentRMS:u16 OffsetCurrentRMS:s16 ApparentPower:u32 GainVoltageRMS:u16 v X 2N-1 0 ÷ 2 ACCU N X ÷2RANGE X VoltageRMS:u16 Range:b32 FIGURE 5-2: DS20006044A-page 24 RMS Current and Voltage Calculation Signal Flow.  2018 Microchip Technology Inc. MCP39F511A 5.5 Power and Energy The MCP39F511A offers signed power numbers for active and reactive power, import and export registers for active energy, and four-quadrant reactive power measurement. For this device, import power or energy is considered positive (power or energy being consumed by the load), and export power or energy is considered negative (power or energy being delivered by the load). The following figure represents the measurements obtained by the MCP39F511A. Import Reactive Power Consume, Inductive Generate, Capacitive -P, +Q Quadrant II Quadrant I +P, +Q S Q  P Import Active Power Export Active Power Quadrant III Generate, Inductive Quadrant IV Consume, Capacitive +P, -Q -P, -Q Export Reactive Power FIGURE 5-3: The Power Circle and Triangle (S = Apparent, P = Active, Q = Reactive).  2018 Microchip Technology Inc. DS20006044A-page 25 MCP39F511A 5.6 Energy Accumulation Energy accumulation for all four energy registers (Import/Export, Active/Reactive) occurs at the end of each computation cycle, if the energy accumulation has been turned on. See Section 6.3 “System Status Register” on the Energy Control register. A no-load threshold test is done to make sure the measured energy is not below the no-load threshold, if it is above, the accumulation occurs with a default energy resolution of 1 mWh for all of the energy registers. 5.6.1 For scaling of the apparent power indication, the calculation engine uses the register Apparent Power Divisor Digits. This is described in the following register operations, per Equation 5-3. EQUATION 5-3: CurrentRMS  VoltageRMS S = -----------------------------------------------------------------AparentPowerDivisorDigits 10 5.8 NO-LOAD THRESHOLD APPARENT POWER (S) Active Power (P) The no-load threshold is set by modifying the value in the No-Load Threshold register. The unit for this register is power with a default resolution of 0.01W. The default value is 100 or 1.00W. Any power that is below 1W will not be accumulated into any of the energy registers. The MCP39F511A has two simultaneous sampling A/D converters. For the active power calculation, the instantaneous current and instantaneous voltages are multiplied together to create instantaneous power. This instantaneous power is then converted to active power by averaging or calculating the DC component. 5.7 Equation 5-4 controls the number of samples used in this accumulation prior to updating the Active Power output register. Apparent Power (S) This 32-bit register is the output register for the final apparent power indication. It is the product of RMS current and RMS voltage as shown in Equation 5-2. EQUATION 5-2: APPARENT POWER (S) S = I RMS  V RMS Please note that although this register is unsigned, the direction of the active power (import or export) can be determined by the Active Power Sign bit located in the System Status Register. EQUATION 5-4: ACTIVE POWER 1 P = ------N 2 N k = 2 –1  Vk  Ik k=0 GainActivePower:u16 i Range:b32 X v FIGURE 5-4: DS20006044A-page 26 2N-1 0 ÷ 2 ACCU N +  X ÷2RANGE ActivePower:u32 + OffsetActivePower:s16 Active Power Calculation Signal Flow.  2018 Microchip Technology Inc. MCP39F511A 5.9 corresponds to a power factor of 1. The minimum register value of 0x8000 corresponds to a power factor of -1. Power Factor (PF) Power factor is calculated by the ratio of P to S or active power divided by apparent power. EQUATION 5-5: 5.10 POWER FACTOR Reactive Power (Q) In the MCP39F511A device, reactive power is calculated using a 90 degree phase shift in the voltage channel. The same accumulation principles apply as with active power where ACCU acts as the accumulator. Any light load or residual power can be removed by using the Offset Reactive Power register. Gain is corrected by the Gain Reactive Power register. The final output is an unsigned 32-bit value located in the Reactive Power register. P PF = --S The power factor reading is stored in a signed 16-bit register (Power Factor). This register is a signed, 2's complement register with the MSb representing the polarity of the power factor. A positive power factor means Active power is being imported, a negative power factor represents export active power. The sign of the reactive power component is used to tell if the current is lagging the voltage, with a positive sign meaning an inductive load and a negative sign meaning capacitive. Each LSb is then equivalent to a weight of 2-15. A maximum register value of 0x7FFF Please note that although this register is unsigned, the direction of the power can be determined by the Reactive Power Sign bit in the system Status register. GainReactivePower:u16 i HPF Range1,2:b32 X v FIGURE 5-5: 2N-1 0 ÷ 2 N ACCU1 +  + X ÷2RANGE ReactivePower:u32 OffsetReactivePower:s16 HPF (+90deg.) Reactive Power Calculation Signal Flow.  2018 Microchip Technology Inc. DS20006044A-page 27 MCP39F511A 5.11 10-Bit Analog Input The least 10 significant bits of the 16-bit Analog Input register contain the output of the 10-bit ADC. The conversion rate of the analog input occurs once every computation cycle. The thermistor voltage can be used for temperature compensation of the calculation engine. See Section 9.7 “Temperature Compensation” for more information. MCP9700 10-bit ADC AnalogInput:u16 5.13 Zero Crossing Detection (ZCD) The zero crossing detection block generates a logic pulse output on the ZCD pin that is coherent with the zero crossing of the input AC signal present on voltage input pins (V1+, V1-). The ZCD pin can be enabled and disabled by the corresponding bit in the System Configuration Register register. When enabled, this produces a square wave with a frequency that is equivalent to that of the AC signal present on the voltage input. Figure 5-7 represents the signal on the ZCD pin superimposed with the AC signal present on the voltage input in this mode. TCAL 0x0086 TempNegCompCurrent 9.7 R/W u16 Temperature compensation for current for T < TCAL 0x0088 TempPosCompPower 9.7 R/W u16 Temperature compensation for power for T > TCAL 0x008A TempNegCompPower 9.7 R/W u16 Temperature compensation for power for T < TCAL 0x008C Reserved — R u16 Reserved 0x008E Reserved — R u16 Reserved 0x0090 Reserved — R u16 Reserved 0x0092 Reserved — R u16 Reserved Design Configuration Registers 0x94 System Configuration 6.5 R/W b32 Control for device configuration, including ADC configuration 0x98 Event Configuration 7.0 R/W b32 Settings for the event pins including relay control 0x9C Range 6.6 R/W b32 Scaling factor for outputs 0xA0 Calibration Current 9.3.1 R/W u32 Target current to be used during single-point calibration 0xA4 Calibration Voltage 9.3.1 R/W u16 Target voltage to be used during single-point calibration 0xA6 Calibration Power Active 9.3.1 R/W u32 Target active power to be used during single-point calibration 0xAA Calibration Power Reactive 9.3.1 R/W u32 Target active power to be used during single-point calibration 0x00AE Reserved — R u32 Reserved 0x00B2 Reserved — R u32 Reserved 0x00B6 Reserved — R u32 Reserved 0x00BA Reserved — R u16 Reserved Reserved — R u16 Reserved 0x00BC Note 1: 2: The registers are unsigned, however their sign is kept as a separate bit in the System Status register. These registers are reserved for EMI filter compensation when necessary for power supply monitoring. They may require specific adjustment depending on PSU parameters, please contact the local Microchip office for further support.  2018 Microchip Technology Inc. DS20006044A-page 31 MCP39F511A TABLE 6-1: MCP39F511A REGISTER MAP (CONTINUED) Section Read/ Number Write Data Type Address Register Name Description 0x00BE App Power Divisor Digits 5.7 R/W u16 AppPowerDivisorDigits sets the RMS (IRMS and VRMS) indications precision and the desired precision for apparent power. 0x00C0 Accumulation Interval Parameter 5.2 R/W u16 N for 2N number of line cycles to be used during a single computation cycle 0xC2 PWM Period 8.2 R/W u16 Input register controlling PWM period 0xC4 PWM Duty Cycle 8.3 R/W u16 Input register controlling PWM duty cycle 0x00C6 MinMaxPointer1 5.12 R/W u16 Address pointer for Min/Max 1 outputs 0x00C8 MinMaxPointer2 5.12 R/W u16 Address pointer for Min/Max 2 outputs 0x00CA Line Frequency Reference 9.6.1 R/W u16 Reference value for the nominal line frequency 0x00CC Thermistor Voltage Calibration 9.7 R/W u16 Thermistor calibration value for temperature compensation of the calculation engine 0x00CE Voltage Sag Limit 7.2 R/W u16 RMS voltage threshold at which an event flag is recorded 0x00D0 Voltage Surge Limit 7.2 R/W u16 RMS voltage threshold at which an event flag is recorded 0x00D2 Over Current Limit 7.2 R/W u32 RMS current threshold at which an event flag is recorded 0x00D6 Over Power Limit 7.2 R/W u32 Active power limit at which an event flag is recorded 0x00DA Overtemperature Limit 7.2.1 R/W u16 Limit at which an overtemperature event flag is recorded 0x00DC Voltage Low Threshold 7.3 R/W u16 Input voltage save to EE Low threshold 0x00DE Voltage High Threshold 7.3 R/W u16 Input voltage Save to EE High threshold 5.6.1 R/W u16 No load threshold for energy counting 0x00E0 Note 1: 2: No Load Threshold The registers are unsigned, however their sign is kept as a separate bit in the System Status register. These registers are reserved for EMI filter compensation when necessary for power supply monitoring. They may require specific adjustment depending on PSU parameters, please contact the local Microchip office for further support. DS20006044A-page 32  2018 Microchip Technology Inc. MCP39F511A 6.2 Address Pointer Register This unsigned 16-bit register contains the address to which all read and write instructions occur. This register is only written through the Set Address Pointer command and is otherwise outside the writable range of register addresses. 6.3 System Status Register The System Status register is a read-only register and can be used to detect the various states of pin levels as defined in Register 6-1. REGISTER 6-1: R-x DCMODE SYSTEM STATUS REGISTER R-x R-x SIGN_DCCURR SIGN_DCVOLT U-0 R-x R-x U-0 U-0 — EVENT2 EVENT1 — — bit 15 bit 8 R-x R-x R-x R-x R-x R-x R-x R-x XTALOSC OVERTEMP SIGN_PR SIGN_PA OVERPOW OVERCUR VSURGE VSAG bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 DCMODE: Mode of the meter, detected automatically. 1 = DC mode 0 = AC mode bit 14 SIGN_DCCURR: Sign of DC Current RMS. 1 = DC Current RMS is positive 0 = DC Current RMS is negative bit 13 SIGN_DCVOLT: Sign of DC Voltage RMS. 1 = DC Voltage RMS is positive 0 = DC Voltage RMS is negative bit 12 Unimplemented: Read as ‘0’ bit 11 EVENT2: State of Event2 detection algorithm. This bit is latched and must be cleared. 1 = Event 2 has occurred 0 = Event 2 has not occurred bit 10 EVENT1: State of Event1 detection algorithm. This bit is latched and must be cleared. 1 = Event 1 has occurred 0 = Event 1 has not occurred bit 9-8 Unimplemented: Read as ‘0’ bit 7 XTALOSC: State of the Oscillator. 1 = XTAL oscillator is enabled 0 = XTAL oscillator is off, internal oscillator enabled bit 6 OVERTEMP: State of the Overtemperature detection algorithm. 1 = Overtemperature threshold has been broken 0 = Overtemperature threshold has not been broken bit 5 SIGN_PR: Sign of Reactive Power. 1 = Reactive Power is positive, inductive and is in quadrants 1,2 0 = Reactive Power is negative, is capacitive and is in quadrants 3,4  2018 Microchip Technology Inc. DS20006044A-page 33 MCP39F511A REGISTER 6-1: SYSTEM STATUS REGISTER (CONTINUED) bit 4 SIGN_PA: Sign of Active Power (import/export sign of active power). 1 = Active Power is positive (import) and is in quadrants 1,4 0 = Active Power is negative (export) and is in quadrants 2,3 bit 3 OVERPOW: State of Overpower detection algorithm. An over power event has occurred in the system. 1 = Overpower threshold has been broken 0 = Overpower threshold has not been broken bit 2 OVERCUR: State of the Overcurrent detection algorithm. An over current event has occurred in the system. 1 = Overcurrent threshold has been broken 0 = Overcurrent threshold has not been broken bit 1 VSURGE: State of Voltage Surge detection algorithm. This bit is latched and must be cleared. 1 = Surge threshold has been broken 0 = Surge threshold has not been broken bit 0 VSAG: State of Voltage Sag detection algorithm. This bit is latched and must be cleared. 1 = Sag threshold has been broken 0 = Sag threshold has not been broken 6.4 System Version Register The System Version register is hard-coded by Microchip Technology Incorporated and contains calculation engine date code information. The System Version register is a date code in the YYWW format, with year and week number in decimal (for instance, 0x1810 = 2018, 10th week). 6.5 System Configuration Register The System Configuration register contains bits for the following control: • • • • • • • • • PGA settings ADC Reset State ADC Shutdown State UART baud rate Single Wire Auto-Transmission ZCD pin behavior Temperature compensation PWM Energy counting These options are described in the following sections. 6.5.1 PROGRAMMABLE GAIN AMPLIFIERS (PGA) The two Programmable Gain Amplifiers (PGAs) reside at the front-end of each 24-bit Delta-Sigma ADC. They have two functions: • Translate the common mode of the input from AGND to an internal level between AGND and AVDD • Amplify the input differential signal The translation of the common mode does not change the differential signal but enters the common mode so that the input signal can be properly amplified. DS20006044A-page 34 The PGA block can be used to amplify very low signals, but the differential input range of the Delta-Sigma modulator must not be exceeded. The PGA is controlled by the PGA_CHn bits in Register 6-2 the System Configuration register. Table 6-2 represents the gain settings for the PGAs. TABLE 6-2: PGA CONFIGURATION SETTING (Note 1) Gain PGA_CHn Gain (V/V) Gain (dB) VIN Range (V) 0 0 0 1 0 ±0.6 0 0 1 2 6 ±0.3 0 1 0 4 12 ±0.15 0 1 1 8 18 ±0.075 1 0 0 16 24 ±0.0375 1 0 1 32 30 ±0.01875 Note 1: 6.5.2 This table is defined with VREF = 1.2V. The two undefined settings, 110 and 111 are G=1. 24-BIT ADC RESET MODE (SOFT RESET MODE) 24-bit ADC Reset mode (also called Soft Reset) can only be entered through setting high the RESET bits in the System Configuration Register register. This mode is defined as the condition where the converters are active but their output is forced to ‘0’. 6.5.3 ADC SHUTDOWN MODE ADC Shutdown mode is defined as a state where the converters and their biases are OFF, consuming only leakage current. When the Shutdown bit is reset to ‘0’, the analog biases will be enabled, as well as the clock and the digital circuitry.  2018 Microchip Technology Inc. MCP39F511A Each converter can be placed in Shutdown mode independently. This mode is only available through programming of the SHUTDOWN bits in the System Configuration Register register. REGISTER 6-2: Note: The PHASE register can be used to serially Soft Reset the ADCs, without using the RESET bits in the Configuration register, if the same value is written in the PHASE register. SYSTEM CONFIGURATION REGISTER U-0 U-0 — — R/W-0 R/W-0 R/W-0 R/W-0 PGA_CH1 R/W-1 R/W-1 PGA_CH0 bit 31 bit 24 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 23 R/W-1 bit 16 R/W-0 R/W-0 UART1 R/W-0 R/W-0 R/W-0 U-0 R/W-0 ZCD_INV ZCD_PULS ZCD_OUTPUT_DIS — SINGLE_WIRE bit 15 R/W-0 bit 8 R/W-0 TEMPCOMP R/W-0 RESET R/W-0 R/W-0 SHUTDOWN R/W-0 R/W-0 R/W-0 VREFEXT PWM_CNTRL ENRG_CNTRL bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 31-30 Unimplemented: Read as ‘0’ bit 29-27 PGA_CH1 : PGA Setting for the voltage channel. 111 = Reserved (Gain = 1) 110 = Reserved (Gain = 1) 101 = Gain is 32 100 = Gain is 16 011 = Gain is 8 010 = Gain is 4 001 = Gain is 2 000 = Gain is 1 (Default) bit 26-24 PGA_CH0 : PGA Setting for the current channel. 111 = Reserved (Gain = 1) 110 = Reserved (Gain = 1) 101 = Gain is 32 100 = Gain is 16 011 = Gain is 8 (Default) 010 = Gain is 4 001 = Gain is 2 000 = Gain is 1 bit 23-16 Unimplemented: Read as ‘0’  2018 Microchip Technology Inc. x = Bit is unknown DS20006044A-page 35 MCP39F511A REGISTER 6-2: SYSTEM CONFIGURATION REGISTER (CONTINUED) bit 15-13 UART: UART Baud Rate bits (Note 1) 111 = 1200 110 = 2400 101 = 4800 100 = 9600 (Default) 011 = 19200 010 = 38400 001 = 57600 000 = 115200 bit 12 ZCD_INV: Zero Crossing Detection Output Inverse 1 = ZCD is inverted 0 = ZCD is not inverted (Default) bit 11 ZCD_PULS: Zero Crossing Detection Pulse mode 1 = ZCD output is 100 µs pulses on zero crossings 0 = ZCD Output changes logic state on zero crossings (Default) bit 10 ZCD_OUTPUT_DIS: Disable the Zero Crossing output pin 1 = ZCD output is disabled 0 = ZCD output is enabled (Default) bit 9 Unimplemented: Read as ‘0’ bit 8 SINGLE_WIRE: Single-Wire Enable bit 1 = Single-wire transmission is enabled 0 = Single-wire transmission is disabled (Default) bit 7 TEMPCOMP: Temperature-Compensation Enable bit 1 = Temperature compensation is enabled 0 = Temperature compensation is disabled (Default) bit 6-5 RESET : Reset mode setting for ADCs 11 = Both I1 and V1 are in Reset mode 10 = V1 ADC is in Reset mode 01 = I1 ADC is in Reset mode 00 = Neither ADC is in Reset mode (Default) bit 4-3 SHUTDOWN : Shutdown mode setting for ADCs 11 = Both I1 and V1 are in Shutdown 10 = V1 ADC is in Shutdown 01 = I1 ADC is in Shutdown 00 = Neither ADC is in Shutdown (Default) bit 2 VREFEXT: Internal Voltage Reference Shutdown Control 1 = Internal Voltage Reference Disabled 0 = Internal Voltage Reference Enabled (Default) bit 1 PWM_CNTRL: PWM Control 1 = PWM is turned on 0 = PWM is turned off (Default) bit 0 ENRG_CNTRL: Energy Accumulation Control bit 1 = Energy is ON and all registers are accumulating 0 = Energy accumulation is turned off and all energy accumulation registers are reset to 0 (Default) Note 1: The baud rate is only changed at system power-up, so a Save To Flash command is required after changing the baud rate. DS20006044A-page 36  2018 Microchip Technology Inc. MCP39F511A 6.6 Range Register The Range register is a 32-bit register that contains the number of right-bit shifts for the following outputs, divided into separate bytes defined below: • RMS Current • RMS Voltage • Power (Active, Reactive, Apparent) Note that the power range byte operates across both the active and reactive output registers and sets the same scale. The purpose of this register is two fold: the number of right-bit shifting (division by 2RANGE) must be: • High enough to prevent overflow in the output register, • Low enough to allow for the desired output resolution. It is the user’s responsibility to set this register correctly to ensure proper output operation for a given meter design. For further information and example usage, see Section 9.3 “Single-Point Gain Calibrations at Unity Power Factor”. . REGISTER 6-3: RANGE REGISTER R-0 R-0 R-0 R-1 R-1 R-0 R-1 R-1 Energy bit 31 bit 24 R/W-0 R/W-0 R/W-0 R/W-1 R/W-0 R/W-1 R/W-0 R/W-1 POWER bit 23 bit 16 R/W-0 R/W-0 R/W-0 R/W-0 R/W-1 R/W-1 R/W-1 R/W-0 CURRENT bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-1 R/W-0 R/W-0 R/W-1 R/W-0 VOLTAGE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 31-24 ENERGY: Sets the number of right-bit shifts for the Energy output registers. Note that the value is read-only and is calculated automatically as 29 – Accumulation Interval. bit 23-16 POWER: Sets the number of right-bit shifts for the Active and Reactive Power output registers bit 15-8 CURRENT: Sets the number of right-bit shifts for the Current RMS output register bit 7-0 VOLTAGE: Sets the number of right-bit shifts for the Voltage RMS output register  2018 Microchip Technology Inc. DS20006044A-page 37 MCP39F511A NOTES: DS20006044A-page 38  2018 Microchip Technology Inc. MCP39F511A 7.0 EVENT OUTPUT PINS/EVENT CONFIGURATION REGISTER 7.1 Event Pins The calculation engine keeps track of a trailing mean square of the input voltage, as defined by the following equation: EQUATION 7-1: The MCP39F511A device has two event pins that can be configured in three possible configurations. These configurations are: 1. 2. No event is mapped to the pin Voltage Surge, Voltage Sag, Overcurrent, Overtemperature or Overpower event is mapped to the pin. More than one event can be mapped to the same pin. Manual control of two pins, independently 3. These three configurations allow for the control of external interrupts or hardware that is dependent on the measured power, current or voltage. The Event Configuration register below describes how these events and pins can be configured. Note: 7.2 If an event is mapped to a pin, manual control of the respective pin is not possible. To enable manual control, no event has to be mapped to the pin. Limits There are five limit registers associated with these events: • • • • • Overtemperature limit Voltage Sag limit Voltage Surge limit Overcurrent limit Overpower limit Each of these limits are compared to the respective output registers of voltage, current and power. It is recommended that they have the same unit for comparison, e.g. 0.1V, or 0.01W. 7.2.1 OVERTEMPERATURE LIMIT The Overtemperature Limit register is compared to the 10-bit SAR output (Thermistor Voltage Register) and is a number between 0 and 1023. When the threshold is passed, the corresponding event flags and event pins (if mapped) are set. 7.2.2 VOLTAGE SAG AND VOLTAGE SURGE DETECTION The event alarms for Voltage Sag and Voltage Surge work differently compared to the Overcurrent and Overpower events, which are tested against every computation cycle. These two event alarms are designed to provide a much faster interrupt if the condition occurs. Note that neither of these two events have a respective Hold register associated with them, since the detection time is less than one line cycle.  2018 Microchip Technology Inc. 2 2  f LINE V SA = --------------------------  f SAMPLE 0  Vn f SAMPLE n = – -------------------------- – 1 2  f LINE Therefore, at each data-ready occurrence, the value of VSA is compared to the programmable threshold set in the Voltage Sag Limit register and Voltage Surge Limit register to determine if a flag should be set. If either of these events are mapped to either the Event1 or Event2 pin, a logic-high interrupt will be given on these pins. The Sag or Surge events can be used to quickly determine if a power failure has occurred in the system. 7.2.3 OVERCURRENT LIMIT The Over Current Limit register is compared to the Current RMS register. When the threshold is passed, the corresponding event flags and event pins (if mapped) are set. 7.2.4 OVERPOWER LIMIT The Over Power Limit register is compared to the Active Power register. When the threshold is passed, the corresponding event flags and event pins (if mapped) are set. 7.3 Voltage Low and Voltage High Threshold The MCP39F511A device offers two additional registers for monitoring the input voltage, the Voltage Low Threshold and Voltage High Threshold registers. When the input voltage crosses (high to low) the value held in the VoltageLowThreshold register, a write to the device EEPROM will be triggered (saving the Energy counters). To avoid multiple writes to EEPROM, a hysteresis is implemented using VoltageHighThreshold register. At power-up, when the input voltage crosses (low to high) the value held in the VoltageHighThreshold register, a read from the device EEPROM is triggered automatically (loading the energy counters). There are no event bits defined for this feature. DS20006044A-page 39 MCP39F511A REGISTER 7-1: EVENT CONFIGURATION REGISTER U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — OVERTEMP_PIN2 OVERTEMP_PIN1 OVERTEMP_CL2 OVERTEMP_LA OVERTEMP_TST bit 31 bit 24 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 OVERPOW_PIN2 OVERCUR_PIN2 VSURGE_PIN 2 VSAG_PIN2 OVERPOW_PIN1 OVERCUR_PIN1 VSURGE_PIN1 VSAG_PIN1 R/W-0 R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 EVENT2_MC EVENT1_MC1 — — OVERCUR_CL2 OVERPOW_CL2 VSUR_CL2 VSAG_CL2 bit 23 bit 16 1 bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 VSUR_LA VSAG_LA OVERPOW_LA OVERCUR_LA VSUR_TST VSAG_TST OVERPOW_TST OVERCUR_TST bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bits 31-29 Unimplemented: Read as ‘0’ bit 28 OVERTEMP_PIN2: Event pin 2 operation for the Overtemperature event 1 = Event mapped to Event2 pin only 0 = Event not mapped to a pin (Default) bit 27 OVERTEMP_PIN1: Event pin 1 operation for the Overtemperature event 1 = Event mapped to Event1 pin only 0 = Event not mapped to a pin (Default) bit 26 OVERTEMP_CL: Reset or clear bit for the Overtemperature event (Note 2) 1 = Event is cleared 0 = Event is not cleared (Default) bit 25 OVERTEMP_LA: Latching control of the Overtemperature event 1 = Event is latched and needs to be cleared to be reset 0 = Event does not latch (Default) bit 24 OVERTEMP_TST: Test control of the Overtemperature event 1 = Simulated event is turned on 0 = Simulated event is turned off (Default) bit 23 OVERPOW_PIN2: Event pin 2 operation for the Overpower event 1 = Event mapped to Event2 pin only 0 = Event not mapped to a pin (Default) bit 22 OVERCUR_PIN2: Event pin 2 operation for the Overcurrent event 1 = Event mapped to Event2 pin only 0 = Event not mapped to a pin (Default) bit 21 VSURGE_PIN2: Event pin 2 operation for the Voltage Surge event 1 = Event mapped to Event2 pin only 0 = Event not mapped to a pin (Default) bit 20 VSAG_PIN2: Event pin 2 operation for the Voltage Sag event 1 = Event mapped to Event2 pin only 0 = Event not mapped to a pin (Default) DS20006044A-page 40  2018 Microchip Technology Inc. MCP39F511A REGISTER 7-1: EVENT CONFIGURATION REGISTER (CONTINUED) bit 19 OVERPOW_PIN1: Event pin 1 operation for the Overpower event 1 = Event mapped to Event1 pin only 0 = Event not mapped to a pin (Default) bit 18 OVERCUR_PIN1: Event pin 1 operation for the Overcurrent event 1 = Event mapped to Event1 pin only 0 = Event not mapped to a pin (Default) bit 17 VSURGE_PIN1: Event pin 1 operation for the Voltage Surge event 1 = Event mapped to Event1 pin only 0 = Event not mapped to a pin (Default) bit 16 VSAG_PIN1: Event pin 1 operation for the Voltage Sag event 1 = Event mapped to Event1 pin only 0 = Event not mapped to a pin (Default) bit 15 EVENT2_MC: Manual control over EVENT pin 2 (Note 1) 1 = EVENT pin 2 set 0 = EVENT pin 2 clear bit 14 EVENT1_MC: Manual control over EVENT pin 1 (Note 1) 1 = EVENT pin 1 set 0 = EVENT pin 1 clear bits 13-12 Unimplemented: Read as ‘0’ bit 11 OVERCUR_CL: Reset or clear bit for the Overcurrent event (Note 2) 1 = Event is cleared 0 = Event is not cleared (Default) bit 10 OVERPOW_CL: Reset or clear bit for the Overpower event (Note 2) 1 = Event is cleared 0 = Event is not cleared (Default) bit 9 VSUR_CL: Reset or clear bit for the Voltage Surge event (Note 2) 1 = Event is cleared 0 = Event is not cleared (Default) bit 8 VSAG_CL: Reset or clear bit for the Voltage Sag event (Note 2) 1 = Event is cleared 0 = Event is not cleared (Default) bit 7 VSUR_LA: Latching control of the Voltage Surge event 1 = Event is latched and needs to be cleared 0 = Event does not latch (Default) bit 6 VSAG_LA: Latching control of the Voltage Sag event 1 = Event is latched and needs to be cleared 0 = Event does not latch (Default) bit 5 OVERPOW_LA: Latching control of the Overpower event 1 = Event is latched and needs to be cleared 0 = Event does not latch (Default) bit 4 OVERCUR_LA: Latching control of the Overcurrent event 1 = Event is latched and needs to be cleared 0 = Event does not latch (Default) bit 3 VSUR_TST: Test control of the Voltage Surge event 1 = Simulated event is turned on 0 = Simulated event is turned off (Default) bit 2 VSAG_TST: Test control of the Voltage Sag event 1 = Simulated event is turned on 0 = Simulated event is turned off (Default) bit 1 OVERPOW_TST: Test control of the Overpower event 1 = Simulated event is turned on 0 = Simulated event is turned off (Default)  2018 Microchip Technology Inc. DS20006044A-page 41 MCP39F511A REGISTER 7-1: bit 0 Note 1: 2: EVENT CONFIGURATION REGISTER (CONTINUED) OVERCUR_TST: Test control of the Overcurrent event 1 = Simulated event is turned on 0 = Simulated event is turned off (Default) Manual control is possible only when no event is mapped to the pin. Writing a 1 to the Clear bit clears the event, either real or simulated through test bits, and then returns to a state of 0. DS20006044A-page 42  2018 Microchip Technology Inc. MCP39F511A 8.0 PULSE WIDTH MODULATION (PWM) in the register, and the prescaler value is represented by the least two significant bits. These two values together create the PWM Period; see Figure 8-1. 8.1 Overview The 10-bit PWM duty cycle is controlled by a 16-bit register where the most eight significant bits are the 8 MSb and the 2 LSb, corresponding to the 2 LSbs of the 10-bit value. The PWM output pin gives up to a 10-bit resolution of a pulse-width modulated signal. The PWM output is controlled by an internal timer inside the MCP39F511A device, FTIMER described in this section, with a base frequency of 16 MHz. The base period is defined as PTIMER and is 1/[16 MHz]. This 16 MHz time base is fixed due to the 4 MHz internal oscillator or 4 MHz external crystal. The output of the PWM is active only when PWM_CNTRL bit in System Configuration register is set. The PWM output is turned off when the PWM_CNTRL bit is cleared. An example of the register’s values are shown here with 255 for PWM frequency (8-bit value) and 1023 for the Duty cycle (10-bit value), prescaler set to divide by 16 (1:0). Period PWM PERIOD (8-bit) The PWM output (Figure 8-2) has a time base (period) and a time that the output stays high (duty cycle). The frequency of the PWM is the inverse of the period (1/period). 1023 There are two registers that control the PWM output, PWM period and PWM duty cycle. PWM DUTY (10-bit) The 8-bit PWM Period is controlled by a 16-bit register that contains the period bits and also the prescaler bits. The PWM Period bits are the most significant eight bits Prescaler 255 1111111100000010 PWM Period Register MSb LSb 1 1 1 1 11 1 1 0 0 0 0 00 1 1 PWM Duty Cycle Register FIGURE 8-1: PWM Period and Duty-Cycle Registers. Period Duty Cycle FIGURE 8-2: PWM Output.  2018 Microchip Technology Inc. DS20006044A-page 43 MCP39F511A 8.2 PWM Period The PWM period is specified by writing the PWM Period bits of the PWM Period register. The PWM period can be calculated using Equation 8-1. EQUATION 8-1: PWM Period = [(PWM_Frequency) + 1] × 2 × PTIMER × (Prescale Value) The PWM Period is defined as 1/[PWM Frequency]. When PTIMER is equal to PWM Period, the following two events occur on the next increment cycle: • The PWM timer is cleared • The PWM pin is set. Exception: If the PWM Duty Cycle equals 0%, the PWM pin will not be set. 8.3 PWM Duty Cycle The PWM duty cycle is specified by writing to the PWM Duty Cycle register. Up to 10-bit resolution is available. The PWM Duty Cycle register contains the eight MSbs and the two LSbs. The following equations are used to calculate the PWM duty cycle as a percentage or as time: EQUATION 8-2: PWM Duty Cycle (%) = (PWM_DUTY CYCLE>)/(4 × PWM_FREQUENCY) PWM Duty Cycle (time in s) = (PWM_DUTY_CYCLE) × PWM_TIMER_PERIOD/2 × (Prescale Value) PWM duty cycle can be written to at any time, but the duty cycle value is not latched until after a period is complete. The PWM registers and a two-bit internal latch are used to double-buffer the PWM duty cycle. This double-buffering is essential for glitch-less PWM operation. The maximum PWM resolution (bits) for a given PWM frequency is shown in Equation 8-3. EQUATION 8-3: MAXIMUM PWM RESOLUTION BASED ON A FUNCTION OF PWM FREQUENCY 2  F TIMER log  -------------------------- F PWM PWM Resolution (max)= ---------------------------------------bits log  2  Note: If the PWM duty cycle value is longer than the PWM period, the PWM pin will not be cleared. DS20006044A-page 44  2018 Microchip Technology Inc. MCP39F511A TABLE 8-1: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS WITH PWM_TIMER_FREQ = 16 MHz (DEFAULT) PWM Frequency Timer Prescaler PWM Frequency Value Maximum Resolution (bits) REGISTER 8-1: R/W-0 1.95 kHz 31.25 kHz 62.5 kHz 125 kHz 2.67 MHz 4 MHz 16 1 1 1 1 1 FFh FFh 7Fh 3Fh 02h 01h 10 10 9 4 3 2 R/W-1 R/W-1 PWM PERIOD REGISTER R/W-0 R/W-1 R/W-1 R/W-1 R/W-1 PWM_P bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — R/W-0 R/W-0 PRE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-8 PWM_P: 8-bit PWM period value bit 7-2 Unimplemented: Read as ‘0‘ bit 1-0 PRE: PWM Prescaler 11 = Unused 10 = 1:16 01 = 1:4 00 = 1:1 (Default) REGISTER 8-2: R/W-0 x = Bit is unknown PWM DUTY-CYCLE REGISTER R/W-0 R/W-1 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 DUTY bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — R/W-0 R/W-0 DUTY bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-8 DUTY: Upper 8 bits of 10-bit duty cycle value bit 7-2 Unimplemented: Read as ‘0‘ bit 1-0 DUTY: Lower 2 bits of 10-bit duty cycle value  2018 Microchip Technology Inc. x = Bit is unknown DS20006044A-page 45 MCP39F511A 9.0 MCP39F511A CALIBRATION 9.1 Overview Calibration compensates for the ADC gain error, component tolerances and overall noise in the system. The device provides an on-chip calibration algorithm that allows simple system calibration to be performed quickly. The excellent analog performance of the A/D converters on the MCP39F511A allows for a single-point calibration and a single calibration command to achieve accurate measurements in AC mode. In DC mode, offset calibration is usually required. Calibration can be done by either using the predefined Auto-Calibration commands, or by writing directly to the calibration registers. If additional calibration points are required (AC offset, phase compensation, DC offset), the corresponding calibration registers are available to the user and will be described separately in this section. 9.2 Calibration Order The proper steps for calibration need to be maintained. Here is a summary on the order of calibration steps: In AC mode 1. 2. 3. 4. Line Frequency Calibration Gain Calibration at PF=1 Phase Calibration at PF=0.5 (optional) Reactive Gain Calibration at PF=0.5 In DC mode 1. 2. Offset Calibration Gain Calibration 9.3 Single-Point Gain Calibrations at Unity Power Factor When using the device in AC mode with the high-pass filters turned on, most offset errors are removed and only a single-point gain calibration is required. Setting the gain registers to properly produce the desired outputs can be done manually by writing to the appropriate register. The alternative method is to use the auto-calibration commands described in this section. 9.3.1 After a successful calibration (response = ACK), a Save Registers to Flash command can then be issued to save the calibration constants calculated by the device. The following registers are set when the Auto-Calibration Gain command is issued: AC mode • Gain Current RMS • Gain Voltage RMS • Gain Active Power DC Mode • DC Gain Current RMS • DC Gain Voltage RMS • DC Gain Active Power When this command is issued, the MCP39F511A attempts to match the expected values to the measured values for all three output quantities by changing the gain register based on the following formula: EQUATION 9-1: Expected GAIN NEW = GAIN OLD  -------------------------Measured The same formula applies for voltage RMS, current RMS and active power. Since the gain registers for all three quantities are 16-bit numbers, the ratio of the expected value to the measured value (which can be modified by changing the Range register) and the previous gain must be such that the equation yields a valid number. Here the limits are set to be from 25,000 to 65,535. A new gain within this range for all three limits will return an ACK for a successful calibration, otherwise the command returns a NAK for a failed calibration attempt. It is the user’s responsibility to ensure that the proper range settings, PGA settings and hardware design settings are correct to allow for successful calibration using this command. The value of the Thermistor Voltage register is automatically transfered to the Ambient Temperature Reference Voltage register after executing the command. This value is used internally by the temperature compensation algorithm, if enabled. USING THE AUTO-CALIBRATION GAIN COMMAND By applying stable reference voltages and currents that are equivalent to the values that reside in the target Calibration Current, Calibration Voltage and Calibration Active Power registers, the Auto-Calibration Gain command can then be issued to the device. DS20006044A-page 46  2018 Microchip Technology Inc. MCP39F511A 9.3.2 EXAMPLE OF RANGE SELECTION FOR VALID CALIBRATION In this example, the user applies a calibration current of 1A to an uncalibrated system. The indicated value in the Current RMS register is 2300 with the system's specific shunt value, PGA gain, etc. The user expects to see a value of 1000 in the Current RMS register when 1A current is applied, meaning 1.000A with 1 mA resolution. Other given values are: • The existing value for gain current RMS is 33480 • The existing value for Range is 12 By using Equation 9-1, the calculation for GainNEW yields: EQUATION 9-2: Expected 1000 GAIN NEW = GAIN OLD  --------------------------- = 33480  ------------ = 14556 Measured 2300 14556  25 000 When using the Auto-Calibration Gain command, the result would be a failed calibration or a NAK returned form the MCP39F511A, because the resulting GainNEW is less than 25,000. The solution is to use the Range register to bring the measured value closer to the expected value, such that a new gain value can be calculated within the limits specified above. The Range register specifies the number of right-bit shifts (equivalent to divisions by 2) after the multiplication with the Gain Current RMS register. Refer to Section 5.0 “Calculation Engine (CE) Description” for information on the Range register. Incrementing the Range register by 1 unit, an additional right-bit shift or ÷2 is included in the calculation. Increasing the current range from 12 to 13 yields the new measured Current RMS register value of 2300/2 = 1150. The expected (1000) and measured (1150) are much closer now, so the expected new gain should be within the limits: issue. The best approach is to choose a range value that places the new gain in the middle of the bounds of the gain registers described above. In a second example, when applying 1A, the user expects an output of 1.0000A with 0.1 mA resolution. The example is starting with the same initial values: EQUATION 9-4: 10000 Expected GAIN NEW = GAIN OLD  --------------------------- = 33480  --------------- = 145565 2300 Measured 145565  65535 The GainNEW is much larger than the 16-bit limit of 65535, so fewer right-bit shifts must be introduced to get the measured value closer to the expected value. The user needs to compute the number of bit shifts that will give a value lower than 65535. To estimate this number: EQUATION 9-5: 145565 ------------------ = 2.2 65535 2.2 rounds to the closest integer value of 2. The range value changes to 12 – 2 = 10; there are 2 less right-bit shifts. The new measured value will be 2300 x 22 = 9200. EQUATION 9-6: Expected 10000 GAIN NEW = GAIN OLD  --------------------------- = 33480  --------------- = 36391 Measured 9200 25 000  36391  65535 The resulting new gain is within the limits and the device successfully calibrates current RMS and returns an ACK. EQUATION 9-3: 1000 Expected GAIN NEW = GAIN OLD  --------------------------- = 33480  ------------ = 29113 1150 Measured 25 000  29113  65535 The resulting new gain is within the limits and the device successfully calibrates current RMS and returns an ACK. Notice that the range can be set to 14 and the resulting new gain will still be within limits (GainNEW = 58226). However, since this gain value is close to the limit of the 16-bit Gain register, variations from system to system (component tolerances, etc.) might create a scenario where the calibration is not successful on some units and there would be a yield  2018 Microchip Technology Inc. DS20006044A-page 47 MCP39F511A 9.4 Calibrating the Phase Compensation Register Phase compensation is provided to adjust for any phase delay between the current and voltage path. This procedure requires sinusoidal current and voltage waveforms, with a significant phase shift between them, and significant amplitudes. The recommended displacement power factor for calibration is 0.5. The procedure for calculating the phase compensation register is as follows: 1. Determine what the difference is between the angle corresponding to the measured power factor (PFMEAS) and the angle corresponding to the expected power factor (PFEXP), in degrees. EQUATION 9-7: Value in PowerFactor Register PF MEAS = --------------------------------------------------------------------------32768 180 ANGLE MEAS    = acos  PF MEAS   ---------  180 ANGLE EXP    = acos  PF EXP   ---------  2. Convert this from degrees to the resolution provided in Equation 9-8. There are 56 samples per line cycle. One line cycle is 360 degrees, so for each sample the angle is 360 degrees/56 samples = 6.42857 degrees/sample. Since the phase compensation has a bit of sign, the maximum angle error that can be compensated is only half, that is ±3.21 degrees. Converting the angle to 8-bit resolution gives 256/6.42857 degrees = 39.82 with 40 as an approximation. 9.5 Offset/No-Load Calibrations During offset calibrations, it is recommended that no line voltage or current be applied to the system. The system should be in a no-load condition. 9.5.1 AC OFFSET CALIBRATION There are three registers associated with the AC Offset Calibration: • Offset Current RMS • Offset Active Power • Offset Reactive Power When computing the AC offset values, the respective gain and range registers should be taken into consideration according to the block diagrams in Figures 5-2 and 5-4. After a successful offset calibration, a Save Registers to Flash command can then be issued to save the calibration constants calculated by the device. 9.5.2 DC OFFSET CALIBRATION In DC applications, the high-pass filters on the current and voltage channels are turned off. There are two registers associated with the DC Offset Calibration: • DC Offset Current RMS • DC Offset Active Power In addition to that, full access to the ADC's internal 24-bit Offset registers is provided. EQUATION 9-8:  =  ANGLE MEAS – ANGLE EXP   40 3. Combine this additional phase compensation to whatever value is currently in the phase compensation, and update the register. Equation 9-9 should be computed in terms of an 8-bit 2's complement-signed value. The 8-bit result is placed in the least significant byte of the 16-bit Phase Compensation register. EQUATION 9-9: PhaseCompensation NEW = PhaseCompensation OLD +  Based on Equation 9-9, the maximum angle in degrees that can be compensated is approximately ±3.2 degrees. If a larger phase shift is required, contact your local Microchip sales office. DS20006044A-page 48  2018 Microchip Technology Inc. MCP39F511A REGISTER 9-1: R/W-1 R/W-1 OFFCAL_MSB R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 OFFCAL_CH1_MSB bit 15 R/W-1 bit 8 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 OFFCAL_CH0_MSB bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-8 OFFCAL_CH1_MSB: MSB of the 24-bit offset for CH1 (voltage channel) bit 7-0 OFFCAL_CH0_MSB: MSB of the 24-bit offset for CH0 (current channel) REGISTER 9-2: R/W-0 R/W-1 OFFCAL_CH0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-0 R/W-1 OFFCAL_CH0 bit 15 R/W-1 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 OFFCAL_CH0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-0 x = Bit is unknown OFFCAL_CH0: Lower 16-bit of the 24-bit offset for CH0 (current channel)  2018 Microchip Technology Inc. DS20006044A-page 49 MCP39F511A REGISTER 9-3: R/W-1 R/W-1 OFFCAL_CH1 R/W-1 R/W-0 R/W-1 R/W-1 R/W-0 R/W-0 OFFCAL_CH1 bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 OFFCAL_CH1 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-0 OFFCAL_CH1: Lower 16-bit of the 24-bit offset for CH1 (voltage channel) Note 1: 9.6 x = Bit is unknown The 24-bit two's complement MSb first coding values are calculated internally using the corresponding byte from the OFFCAL_MSB register and OFFCAL_CHn 16-bit values. The result is added to the output code of the corresponding channel bit-by-bit. Calibrating the Line Frequency Register 9.6.1 USING THE AUTO-CALIBRATE FREQUENCY COMMAND The Line Frequency register contains a 16-bit number with a value equivalent to the input-line frequency as it is measured on the voltage channel. When in DC mode, this calculation is turned off and the register will be equal to zero. By applying a stable reference voltage with a constant line frequency that is equivalent to the value that resides in the Line Frequency Ref, the Auto-Calibrate Frequency command can then be issued to the device. The measurement of the line frequency is only valid from 45 to 65 Hz. After a successful calibration (response = ACK), a Save Registers to Flash command can then be issued to save the calibration constants calculated by the device. Issuing the command in DC mode generates a NAK response. The following register is set when the Auto-Calibrate Frequency command is issued: • Gain Line Frequency Note that the command is only required when running off the internal oscillator. The formula used to calculate the new gain is shown in Equation 9-1. DS20006044A-page 50  2018 Microchip Technology Inc. MCP39F511A 9.7 Temperature Compensation 9.8 EMI Input Filter Compensation MCP39F511A measures the indication of the temperature sensor and uses the value to compensate the temperature variation of the shunt resistance and the frequency of the internal RC oscillator. The typical EMI input filter location in a power supply is between the AC inlet and the meter, and as a result the components of the filter (capacitors and inductors) affect the accuracy of the meter. The same formula applies for line frequency, current RMS, active power and reactive power. The temperature compensation coefficient depends on the 16-bit unsigned integer value of the corresponding compensation register. The current RMS measurement is affected by the input capacitor and the exact value depends on the frequency and the input voltage. EQUATION 9-10: y = x   1 + c   T – T CAL   The current flowing through the input capacitor can be compensated using the InCapCurrentComp register (enabled in AC mode only). EQUATION 9-11: TemperatureCompensation Register c = ----------------------------------------------------------------------------------------------M 2 cfV y = x + ------------------M 2 Where: x = Uncompensated output (corresponding to line frequency, current RMS, active power and reactive power) y = Compensated output c = Temperature compensation coefficient (depending on the shunt's temperature coefficient of resistance or on the internal RC oscillator temperature frequency drift). There are six registers two for line frequency compensation, two for current compensation and two for power compensation (active and reactive). TempPosComp registers are used when T is greater than TCAL. TempNegComp registers are used when T is less than TCAL. T = Thermistor voltage (in 10-bit ADC units) TCAL = Ambient temperature reference voltage. It should be set at the beginning of the calibration procedure, by reading the thermistor voltage and writing its value to the ambient temperature reference voltage register. The auto-calibration gain command does this automatically. Where: x = Uncompensated current RMS y = Compensated current RMS c = Compensation value found in InCapCurrentComp register f = Measured frequency V = Measured voltage RMS M = INCAPCURRENT value found RANGEVDROPINCAPCOMP register in EXAMPLE 9-1: A 1 F input capacitor at 220V [rms], 50 Hz corresponds to an offset current of . 0.0691A [rms]. M y – x  2 c = ----------------------------f  V Where y - x = offset current M = 32 (default value) At the calibration temperature, the effect of the compensation coefficients is null. The coefficients need to be tuned when the difference between the calibration temperature and the device temperature is significant. It is recommended to use the default values as starting points.  2018 Microchip Technology Inc. c = 691 * 4294967296 / (50000 * 2200) c = 26980, this is the value that should be written to the InCapCurrentComp register DS20006044A-page 51 MCP39F511A The PCB traces and the inductors resistance cause a voltage drop when high currents are flowing through them. The higher the current is, the higher the error of the voltage RMS measurement. This voltage drop can be compensated using the VoltageDropComp register (enabled in DC and AC mode). EQUATION 9-12: cI y = x + ---------M 2 Where: x = Uncompensated voltage RMS y = Compensated voltage RMS c = Compensation value found in VoltageDropComp register I = Measured current RMS M = VOLTAGEDROP value found RANGEVDROPINCAPCOMP register in EXAMPLE 9-2: A 0.1  resistor at 10A [rms] corresponds to an offset voltage of 1V [rms]. M y – x  2 c = ----------------------------I Where: y -x = offset value M = 28 (default value) c = 10 * 268435456 / 100000 c = 26843, this is the value that should be written to the VoltageDropComp register DS20006044A-page 52  2018 Microchip Technology Inc. MCP39F511A REGISTER 9-4: R/W-0 R/W-0 VOLTAGEDROPCOMP R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 VOLTAGEDROPCOMP bit 15 R/W-0 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 VOLTAGEDROPCOMP bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-0 VOLTAGEDROPCOMP: Voltage Drop Compensation register REGISTER 9-5: R/W-0 x = Bit is unknown R/W-0 INCAPCURRENTCOMP R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 INCAPCURRENTCOMP bit 15 R/W-0 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 INCAPCURRENTCOMP bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-0 INCAPCURRENTCOMP: Input Capacitor Current Compensation register REGISTER 9-6: R/W-0 x = Bit is unknown R/W-0 RANGEVDROPINCAPCOMP R/W-0 R/W-1 R/W-1 R/W-1 R/W-0 R/W-0 VOLTAGEDROP bit 15 R/W-0 bit 8 R/W-0 R/W-1 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 INCAPCURRENT bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-8 VOLTAGEDROP: Sets the number of right-bit shifts for the VoltageDropComp register bit 7-0 INCAPCURRENT: Sets the number of right-bit shifts for the InCapCurrentComp register  2018 Microchip Technology Inc. DS20006044A-page 53 MCP39F511A 9.9 Retrieving Factory Default Calibration Values After user calibration and a Save to Flash command has been issued, it is possible to retrieve the factory default calibration values. This can be done by writing 0xA5A5 to the calibration delimiter register, issuing a Save to Flash, and then resetting the part. This procedure will retrieve all factory default calibration values and will remain in this state until calibration has been performed again, and a Save to Flash command has been issued. DS20006044A-page 54  2018 Microchip Technology Inc. MCP39F511A 10.0 There are three commands that support access to the EEPROM array. EEPROM The data EEPROM is organized as 16-bit wide memory. Each word is directly addressable, and is readable and writable across the entire VDD range. The MCP39F511A device has 256 16-bit words of EEPROM that is organized in 32 pages for a total of 512 bytes. TABLE 10-1: • EEPROM Page Read (0x42) • EEPROM Page Write (0x50) • EEPROM Bulk Erase (0x4F) EXAMPLE EEPROM COMMANDS AND DEVICE RESPONSE Command Command ID BYTE 0 BYTE 1-N 0x42 PAGE 2 Page Write EEPROM 0x50 PAGE + DATA (16) 18 ACK Bulk Erase EEPROM 0x4F None 1 ACK Page Read EEPROM TABLE 10-2: Page # Bytes Successful Response ACK, NoB, data, checksum MCP39F511A EEPROM ORGANIZATION 00 02 04 06 08 0A 0C 0E 0 0000 0000 0000 0000 0000 0000 0000 0000 0000 1 0010 0000 0000 0000 0000 0000 0000 0000 0000 2 0020 FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF 3 0030 FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF 4 0040 FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF 5 0050 FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF 6 0060 FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF 7 0070 FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF 8 0080 FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF 9 0090 FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF 10 00A0 FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF 11 00B0 FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF 12 00C0 FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF 13 00D0 FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF 14 00E0 FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF 15 00F0 FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF 16 0100 FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF 17 0110 FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF 18 0120 FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF 19 0130 FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF 20 0140 FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF 21 0150 FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF 22 0160 FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF 23 0170 FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF 24 0180 FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF 25 0190 FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF 26 01A0 FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF 27 01B0 FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF 28 01C0 FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF 29 01D0 FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF 01E0 FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF 30 Note 1: Pages 0 and 1 are reserved for saving the energy counters at power-down. The locations are accessible, but writing to them may interfere with the energy counters functionality.  2018 Microchip Technology Inc. DS20006044A-page 55 MCP39F511A TABLE 10-2: MCP39F511A EEPROM ORGANIZATION Page 31 Note 1: 01F0 00 02 04 06 08 0A 0C 0E FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF Pages 0 and 1 are reserved for saving the energy counters at power-down. The locations are accessible, but writing to them may interfere with the energy counters functionality. DS20006044A-page 56  2018 Microchip Technology Inc. MCP39F511A NOTES:  2018 Microchip Technology Inc. DS20006044A-page 57 MCP39F511A 11.0 PACKAGING INFORMATION 11.1 Package Marking Information 28-Lead QFN (5x5x0.9 mm) Example 39F511A e33 -E/MQ e ^^ 1802156 Legend: XX...X Y YY WW NNN e3 * Note: DS20006044A-page 58 Customer-specific information Year code (last digit of calendar year) Year code (last 2 digits of calendar year) Week code (week of January 1 is week ‘01’) Alphanumeric traceability code Pb-free JEDEC designator for Matte Tin (Sn) This package is Pb-free. The Pb-free JEDEC designator ( e3 ) can be found on the outer packaging for this package. In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information.  2018 Microchip Technology Inc. MCP39F511A 28-Lead Plastic Quad Flat, No Lead Package (MQ) – 5x5x0.9 mm Body [QFN or VQFN] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging D A B N NOTE 1 1 2 E (DATUM B) (DATUM A) 2X 0.10 C 2X TOP VIEW 0.10 C 0.10 C C SEATING PLANE A1 A 28X A3 SIDE VIEW 0.08 C 0.10 C A B D2 0.10 C A B E2 28X K 2 1 NOTE 1 N 28X L e BOTTOM VIEW 28X b 0.10 0.05 C A B C Microchip Technology Drawing C04-140C Sheet 1 of 2  2018 Microchip Technology Inc. DS20006044A-page 59 MCP39F511A 28-Lead Plastic Quad Flat, No Lead Package (MQ) – 5x5x0.9 mm Body [QFN or VQFN] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging Units Dimension Limits Number of Pins N e Pitch Overall Height A Standoff A1 A3 Contact Thickness Overall Width E Exposed Pad Width E2 Overall Length D Exposed Pad Length D2 b Contact Width Contact Length L Contact-to-Exposed Pad K MIN 0.80 0.00 3.15 3.15 0.18 0.35 0.20 MILLIMETERS NOM 28 0.50 BSC 0.90 0.02 0.20 REF 5.00 BSC 3.25 5.00 BSC 3.25 0.25 0.40 - MAX 1.00 0.05 3.35 3.35 0.30 0.45 - Notes: 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. Package is saw singulated. 3. Dimensioning and tolerancing per ASME Y14.5M. BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only. Microchip Technology Drawing C04-140C Sheet 2 of 2 DS20006044A-page 60  2018 Microchip Technology Inc. MCP39F511A 28-Lead Plastic Quad Flat, No Lead Package (MQ) – 5x5 mm Body [QFN] Land Pattern With 0.55 mm Contact Length Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging Microchip Technology Drawing C04-2140A  2018 Microchip Technology Inc. DS20006044A-page 61 MCP39F511A DS20006044A-page 62  2018 Microchip Technology Inc. MCP39F511A APPENDIX A: REVISION HISTORY Revision A (June 2018) • Original release of this document.  2018 Microchip Technology Inc. DS20006044A-page 63 MCP39F511A NOTES: DS20006044A-page 64  2018 Microchip Technology Inc. MCP39F511A PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. Device [X](1) X Tape and Temperature Reel Range Device: /XX Package MCP39F511A:Power-Monitoring IC with Calculation and Energy Accumulation Examples: a) MCP39F511A-E/MQ: Extended temperature, 28LD 5x5 QFN package b) MCP39F511AT-E/MQ: Tape and Reel, Extended temperature, 28LD 5x5 QFN package Tape and Reel Option: Blank = Standard packaging (tube or tray) T = Tape and Reel (1) Temperature Range: E = -40°C to +125°C Package: MQ = Plastic Quad Flat, No Lead Package – 5x5x0.9 mm body (QFN), 28-lead  2018 Microchip Technology Inc. Note 1: Tape and Reel identifier only appears in the catalog part number description. This identifier is used for ordering purposes and is not printed on the device package. Check with your Microchip sales office for package availability for the Tape and Reel option. DS20006044A-page 65 MCP39F511A NOTES: DS20006044A-page 66  2018 Microchip Technology Inc. Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. • Microchip is willing to work with the customer who is concerned about the integrity of their code. • Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer’s risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights unless otherwise stated. Trademarks Microchip received ISO/TS-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company’s quality system processes and procedures are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. QUALITY MANAGEMENT SYSTEM CERTIFIED BY DNV The Microchip name and logo, the Microchip logo, AnyRate, AVR, AVR logo, AVR Freaks, BitCloud, chipKIT, chipKIT logo, CryptoMemory, CryptoRF, dsPIC, FlashFlex, flexPWR, Heldo, JukeBlox, KeeLoq, Kleer, LANCheck, LINK MD, maXStylus, maXTouch, MediaLB, megaAVR, MOST, MOST logo, MPLAB, OptoLyzer, PIC, picoPower, PICSTART, PIC32 logo, Prochip Designer, QTouch, SAM-BA, SpyNIC, SST, SST Logo, SuperFlash, tinyAVR, UNI/O, and XMEGA are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. ClockWorks, The Embedded Control Solutions Company, EtherSynch, Hyper Speed Control, HyperLight Load, IntelliMOS, mTouch, Precision Edge, and Quiet-Wire are registered trademarks of Microchip Technology Incorporated in the U.S.A. Adjacent Key Suppression, AKS, Analog-for-the-Digital Age, Any Capacitor, AnyIn, AnyOut, BodyCom, CodeGuard, CryptoAuthentication, CryptoAutomotive, CryptoCompanion, CryptoController, dsPICDEM, dsPICDEM.net, Dynamic Average Matching, DAM, ECAN, EtherGREEN, In-Circuit Serial Programming, ICSP, INICnet, Inter-Chip Connectivity, JitterBlocker, KleerNet, KleerNet logo, memBrain, Mindi, MiWi, motorBench, MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach, Omniscient Code Generation, PICDEM, PICDEM.net, PICkit, PICtail, PowerSmart, PureSilicon, QMatrix, REAL ICE, Ripple Blocker, SAM-ICE, Serial Quad I/O, SMART-I.S., SQI, SuperSwitcher, SuperSwitcher II, Total Endurance, TSHARC, USBCheck, VariSense, ViewSpan, WiperLock, Wireless DNA, and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. Silicon Storage Technology is a registered trademark of Microchip Technology Inc. in other countries. GestIC is a registered trademark of Microchip Technology Germany II GmbH & Co. KG, a subsidiary of Microchip Technology Inc., in other countries. All other trademarks mentioned herein are property of their respective companies. © 2018, Microchip Technology Incorporated, All Rights Reserved. ISBN: 978-1-5224-3244-9 == ISO/TS 16949 ==  2018 Microchip Technology Inc. DS20006044A-page 1 Worldwide Sales and Service AMERICAS ASIA/PACIFIC ASIA/PACIFIC EUROPE Corporate Office 2355 West Chandler Blvd. Chandler, AZ 85224-6199 Tel: 480-792-7200 Fax: 480-792-7277 Technical Support: http://www.microchip.com/ support Web Address: www.microchip.com Australia - Sydney Tel: 61-2-9868-6733 India - Bangalore Tel: 91-80-3090-4444 China - Beijing Tel: 86-10-8569-7000 India - New Delhi Tel: 91-11-4160-8631 Austria - Wels Tel: 43-7242-2244-39 Fax: 43-7242-2244-393 China - Chengdu Tel: 86-28-8665-5511 India - Pune Tel: 91-20-4121-0141 Denmark - Copenhagen Tel: 45-4450-2828 Fax: 45-4485-2829 China - Chongqing Tel: 86-23-8980-9588 Japan - Osaka Tel: 81-6-6152-7160 Finland - Espoo Tel: 358-9-4520-820 China - Dongguan Tel: 86-769-8702-9880 Japan - Tokyo Tel: 81-3-6880- 3770 China - Guangzhou Tel: 86-20-8755-8029 Korea - Daegu Tel: 82-53-744-4301 France - Paris Tel: 33-1-69-53-63-20 Fax: 33-1-69-30-90-79 China - Hangzhou Tel: 86-571-8792-8115 Korea - Seoul Tel: 82-2-554-7200 China - Hong Kong SAR Tel: 852-2943-5100 Malaysia - Kuala Lumpur Tel: 60-3-7651-7906 China - Nanjing Tel: 86-25-8473-2460 Malaysia - Penang Tel: 60-4-227-8870 China - Qingdao Tel: 86-532-8502-7355 Philippines - Manila Tel: 63-2-634-9065 China - Shanghai Tel: 86-21-3326-8000 Singapore Tel: 65-6334-8870 China - Shenyang Tel: 86-24-2334-2829 Taiwan - Hsin Chu Tel: 886-3-577-8366 China - Shenzhen Tel: 86-755-8864-2200 Taiwan - Kaohsiung Tel: 886-7-213-7830 Israel - Ra’anana Tel: 972-9-744-7705 China - Suzhou Tel: 86-186-6233-1526 Taiwan - Taipei Tel: 886-2-2508-8600 China - Wuhan Tel: 86-27-5980-5300 Thailand - Bangkok Tel: 66-2-694-1351 Italy - Milan Tel: 39-0331-742611 Fax: 39-0331-466781 China - Xian Tel: 86-29-8833-7252 Vietnam - Ho Chi Minh Tel: 84-28-5448-2100 Atlanta Duluth, GA Tel: 678-957-9614 Fax: 678-957-1455 Austin, TX Tel: 512-257-3370 Boston Westborough, MA Tel: 774-760-0087 Fax: 774-760-0088 Chicago Itasca, IL Tel: 630-285-0071 Fax: 630-285-0075 Dallas Addison, TX Tel: 972-818-7423 Fax: 972-818-2924 Detroit Novi, MI Tel: 248-848-4000 Houston, TX Tel: 281-894-5983 Indianapolis Noblesville, IN Tel: 317-773-8323 Fax: 317-773-5453 Tel: 317-536-2380 Los Angeles Mission Viejo, CA Tel: 949-462-9523 Fax: 949-462-9608 Tel: 951-273-7800 Raleigh, NC Tel: 919-844-7510 New York, NY Tel: 631-435-6000 San Jose, CA Tel: 408-735-9110 Tel: 408-436-4270 Canada - Toronto Tel: 905-695-1980 Fax: 905-695-2078 DS20006044A-page 28 China - Xiamen Tel: 86-592-2388138 China - Zhuhai Tel: 86-756-3210040 Germany - Garching Tel: 49-8931-9700 Germany - Haan Tel: 49-2129-3766400 Germany - Heilbronn Tel: 49-7131-67-3636 Germany - Karlsruhe Tel: 49-721-625370 Germany - Munich Tel: 49-89-627-144-0 Fax: 49-89-627-144-44 Germany - Rosenheim Tel: 49-8031-354-560 Italy - Padova Tel: 39-049-7625286 Netherlands - Drunen Tel: 31-416-690399 Fax: 31-416-690340 Norway - Trondheim Tel: 47-7289-7561 Poland - Warsaw Tel: 48-22-3325737 Romania - Bucharest Tel: 40-21-407-87-50 Spain - Madrid Tel: 34-91-708-08-90 Fax: 34-91-708-08-91 Sweden - Gothenberg Tel: 46-31-704-60-40 Sweden - Stockholm Tel: 46-8-5090-4654 UK - Wokingham Tel: 44-118-921-5800 Fax: 44-118-921-5820  2017 Microchip Technology Inc. 10/25/17