MCP39F511N-E/MQ

MCP39F511N Dual-Channel, Single-Phase Power-Monitoring IC with Calculation Features Description • Power Monitoring of Two Loads with accuracy of 0.5% across 4000:1 Dynamic Range • Built-in Calculations on Fast 16-bit Processing Core: - Active, Reactive, Apparent Power - True RMS Current, RMS Voltage - Line Frequency, Power Factor • 64-bit Wide Import and Export Active Energy Accumulation Registers Per Channel • 64-bit Four Quadrant Reactive Energy Accumulation Registers Per Channel • Signed Active and Reactive Power Outputs • Dedicated Zero Crossing Detection (ZCD) Pin Output with Less than 200 µs Latency • Dedicated PWM Output Pin with Programmable Frequency and Duty Cycle • Automatic Event Pin Control through Fast Voltage Surge Detection - Less than 5 ms Delay • Two-Wire Serial Protocol with Selectable Baud Rate up to 115.2 kbps using Universal Asynchronous Receiver/Transmitter (UART) • Fast Calibration Routines and Simplified Command Protocol • 512 Bytes User-Accessible EEPROM through Page Read/Write Commands • Low-Drift Internal Voltage Reference, 10 ppm/°C Typical • 28-lead 5x5 QFN Package • Extended Temperature Range: -40°C to +125°C The MCP39F511N is a highly integrated, complete dual-channel single-phase power-monitoring IC designed for real-time measurement of input power for dual-socket wall outlets, power strips, and consumer and industrial applications. It includes dual-channel 24-bit Delta-Sigma ADCs for dual-current measurements, a 10-bit SAR ADC for voltage measurement, a 16-bit calculation engine, EEPROM and a flexible two-wire interface. An integrated low-drift voltage reference with 10 ppm/°C in addition to 94.5 dB of SINAD performance on each measurement channel allow for better than 0.5% accurate designs across a 4000:1 dynamic range.  2015-2018 Microchip Technology Inc. ZCD REFIN+/OUT MCLR DVDD DGND DGND DR 21 AGND NC 2 20 V+ NC 3 19 I2+ EP 29 UART_RX 4 COMMONA 5 18 I217 I116 I1+ OSCI 6 15 EVENT2 OSCO 7 PWM AVDD 9 10 11 12 13 14 RESET NC 8 COMMONB Wall Socket (Dual Plug) Power Monitoring Power Monitoring for Home Automation Industrial Lighting Power Monitoring Real-Time Measurement of Input Power for AC-DC Supplies • Intelligent Power Distribution Units 28 27 26 25 24 23 22 EVENT1 1 UART_TX • • • • MCP39F511N 5x5 QFN* NC Applications Package Types *Includes Exposed Thermal Pad (EP); see Table 3-1. DS20005473B-page 1 MCP39F511N Functional Block Diagram I1+ I1- I2+ I2- V+ + PGA - + PGA - AVDD AGND DVDD DGND Internal Oscillator 24-bit Delta-Sigma Multi-level Modulator ADC 24-bit Delta-Sigma Multi-level Modulator ADC 10-bit SAR ADC  2015-2018 Microchip Technology Inc. SINC3 Digital Filter OSCO Timing Generation SINC3 Digital Filter OSCI UART Serial Interface 16-BIT CORE FLASH UART_TX UART_RX PWM EVENT1 Calculation Engine (CE) EVENT2 Digital Outputs ZCD DS20005473B-page 2 MCP39F511N Typical Application L N 10  1 µF + I1- AVDD DVDD RESET REFIN/OUT+ 33 nF LOAD – 0.1 µF 0.1 µF 1 k 2 m +3.3V 0.1 µF 1 k I1+ to MCU UART 1 k LOAD + 2 m – UART_TX 33 nF I2- UART_RX 33 nF to MCU UART 1 k (OPTIONAL) I2+ MCP39F511N 33 nF NC NC NC NC DR +3.3V 499 k 51 k 47 µ F 499 k 5.1 k 1 k V+ 51 k 33 nF COMMONA,B 33 nF N.C. Leave Floating Connect on PCB EVENT1 L N EVENT2 ZCD OSCO PWM 8 MHz OSCI 22 pF DGND AGND 22 pF (OPTIONAL) +3.3V 0.47 µ F 470 MCP1754 0.01 µF DGND Note: 470 µF AGND The external sensing components shown here, the 2 mΩ shunts, two 499 kΩ and 5.1 kΩ resistor for the 200:1 voltage divider, are specifically chosen to match the default values for the calibration registers defined in Section 6.0 “Register Descriptions”. By choosing low-tolerance components of these values (e.g. 1% tolerance), measurement accuracy in the 2-3% range can be achieved with zero calibration. See Section 9.0 “MCP39F511N Calibration” for more information.  2015-2018 Microchip Technology Inc. DS20005473B-page 3 MCP39F511N 1.0 ELECTRICAL CHARACTERISTICS † Notice: Stresses above those listed under “Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. Absolute Maximum Ratings † DVDD .................................................................. -0.3 to +4.5V AVDD ................................................................... -0.3 to +4.0V Digital inputs and outputs w.r.t. AGND ...............-0.3V to +4.0V Analog Inputs (I+,I-,V+,V-) w.r.t. AGND ....................-2V to +2V VREF input w.r.t. AGND ......................... ....-0.6V to AVDD +0.6V Maximum Current out of DGND pin ............................. 300 mA Maximum Current into DVDD pin ................................ 250 mA Maximum Output Current Sunk by Digital IO ............... 25 mA Maximum Current Sourced by Digital IO ...................... 25 mA Storage temperature..................................... -65°C to +150°C Ambient temperature with power applied ..... -40°C to +125°C Soldering temperature of leads (10 seconds)............. +300°C ESD on the analog inputs (HBM,MM) ................ 4.0 kV, 200V ESD on all other pins (HBM,MM) ....................... 4.0 kV, 200V 1.1 Specifications TABLE 1-1: ELECTRICAL CHARACTERISTICS Electrical Specifications: Unless otherwise indicated, all parameters apply across both channels at AVDD, DVDD = 2.7 to 3.6V, TA = -40°C to +125°C, MCLK = 4 MHz, PGA GAIN = 1. Characteristic Sym. Min. Typ. Max. Units Test Conditions Active Power (Note 1) P — ±0.5 — % 4000:1 Dynamic Range on Current Channel (Note 2) Reactive Power (Note 1) Q — ±0.5 — % 4000:1 Dynamic Range on Current Channel (Note 2) Apparent Power (Note 1) S — ±1 — % 4000:1 Dynamic Range on Current Channel (Note 2) Current RMS (Note 1) IRMS — ±1 — % 4000:1 Dynamic Range on Current Channel (Note 2) Voltage RMS (Note 1) VRMS — ±1 — % 4000:1 Dynamic Range on Voltage Channel (Note 2) Power Factor (Note 1)  — ±1 — % Line Frequency (Note 1) LF — ±1 — % Power Measurement Note 1: 2: 3: 4: 5: 6: 7: Calculated from reading the register values with no averaging, single computation cycle with accumulation interval of 16 line cycles, channel 1 or channel 2. Specification by design and characterization; not production tested. N = Value in the Accumulation Interval Parameter register. The default value of this register is 4 or TCAL = 320 ms for 50 Hz line. Applies to Voltage Sag and Voltage Surge events only. Applies to all gains. Offset and gain errors depend on the PGA gain setting. See Section 2.0 “Typical Performance Curves” for typical performance. VIN = 1 VPP = 353 mVRMS @ 50/60 Hz. Variation applies to internal clock and UART only.  2015-2018 Microchip Technology Inc. DS20005473B-page 4 MCP39F511N TABLE 1-1: ELECTRICAL CHARACTERISTICS (CONTINUED) Electrical Specifications: Unless otherwise indicated, all parameters apply across both channels at AVDD, DVDD = 2.7 to 3.6V, TA = -40°C to +125°C, MCLK = 4 MHz, PGA GAIN = 1. Characteristic Sym. Min. Typ. Max. Units Test Conditions 2N x (1/fLINE) — ms Note 3 see — ms Note 4 Calibration, Calculation and Event Detection Times Auto-Calibration Time tCAL — Minimum Time for Voltage Surge/Sag Detection tAC_SASU — Section 7.0 24-Bit Delta-Sigma ADC Performance Analog Input Absolute Voltage VIN -1 — +1 V Analog Input Leakage Current AIN — 1 — nA Differential Input Voltage Range (I1+ – I1-), (I2+ – I2-) -600/GAIN — +600/GAIN mV VOS -1 — +1 mV Offset Error Offset Error Drift Gain Error — 0.5 — µV/°C GE -4 — +4 % — 1 — ppm/°C ZIN 232 — — k 142 — — k G=2 72 — — k G=4 Gain Error Drift Differential Input Impedance Signal-to-Noise and Distortion Ratio VREF = 1.2V, proportional to VREF SINAD Note 5 G=1 38 — — k G=8 36 — — k G = 16 33 — — k G = 32 92 94.5 — dB Note 6 Total Harmonic Distortion THD — -106.5 -103 dBc Note 6 Signal-to-Noise Ratio SNR 92 95 — dB Note 6 SFDR — 111 — dB Note 6 Spurious Free Dynamic Range Crosstalk CTALK — -122 — dB AC Power Supply Rejection Ratio AC PSRR — -73 — dB AVDD and DVDD = 3.3V + 0.6VPP, 100 Hz, 120 Hz, 1 kHz DC Power Supply Rejection Ratio DC PSRR — -73 — dB AVDD and DVDD = 3.0 to 3.6V DC Common Mode Rejection Ratio DC CMRR — -105 — dB VCM varies from -1V to +1V Note 1: 2: 3: 4: 5: 6: 7: Calculated from reading the register values with no averaging, single computation cycle with accumulation interval of 16 line cycles, channel 1 or channel 2. Specification by design and characterization; not production tested. N = Value in the Accumulation Interval Parameter register. The default value of this register is 4 or TCAL = 320 ms for 50 Hz line. Applies to Voltage Sag and Voltage Surge events only. Applies to all gains. Offset and gain errors depend on the PGA gain setting. See Section 2.0 “Typical Performance Curves” for typical performance. VIN = 1 VPP = 353 mVRMS @ 50/60 Hz. Variation applies to internal clock and UART only.  2015-2018 Microchip Technology Inc. DS20005473B-page 5 MCP39F511N TABLE 1-1: ELECTRICAL CHARACTERISTICS (CONTINUED) Electrical Specifications: Unless otherwise indicated, all parameters apply across both channels at AVDD, DVDD = 2.7 to 3.6V, TA = -40°C to +125°C, MCLK = 4 MHz, PGA GAIN = 1. Characteristic Sym. Min. Typ. Max. Units Test Conditions 10-Bit SAR ADC Performance for Voltage Measurement Resolution NR — 10 — bits Absolute Input Voltage VIN DGND - 0.3 — DVDD + 0.3 V Recommended Impedance of Analog Voltage Source RIN — — 2.5 k Integral Nonlinearity INL — ±1 ±2 LSb Differential Nonlinearity DNL — ±1 ±1.5 LSb Gain Error GERR — ±1 ±3 LSb Offset Error EOFF — ±1 ±2 LSb UART Baud Rate UDB 1.2 — 115.2 kbps Master Clock and Crystal Frequency fMCLK -2% 8 +2% MHz Capacitive Loading on OSCO pin COSC2 — — 15 pF When an external clock is used to drive the device Internal Oscillator Tolerance fINT_OSC — 2 — % -40°C to +85°C only (Note 7) VREF -2% 1.2 +2% V TCVREF — 10 — Output Impedance ZOUTVREF — 2 — k Current, VREF AIDDVREF — 40 — µA — — 10 pF VREF+ AGND + 1.1V — AGND + 1.3V V AVDD, DVDD 2.7 — 3.6 V VPOR DGND — 0.7 V Clock and Timings See Section 3.2 for protocol details Internal Voltage Reference Internal Voltage Reference Tolerance Temperature Coefficient ppm/°C TA = -40°C to +85°C, VREFEXT = 0 Voltage Reference Input Input Capacitance Absolute Voltage on VREF+ Pin Power Specifications Operating Voltage DVDD Start Voltage to Ensure Internal Power-On Reset Signal Note 1: 2: 3: 4: 5: 6: 7: Calculated from reading the register values with no averaging, single computation cycle with accumulation interval of 16 line cycles, channel 1 or channel 2. Specification by design and characterization; not production tested. N = Value in the Accumulation Interval Parameter register. The default value of this register is 4 or TCAL = 320 ms for 50 Hz line. Applies to Voltage Sag and Voltage Surge events only. Applies to all gains. Offset and gain errors depend on the PGA gain setting. See Section 2.0 “Typical Performance Curves” for typical performance. VIN = 1 VPP = 353 mVRMS @ 50/60 Hz. Variation applies to internal clock and UART only.  2015-2018 Microchip Technology Inc. DS20005473B-page 6 MCP39F511N TABLE 1-1: ELECTRICAL CHARACTERISTICS (CONTINUED) Electrical Specifications: Unless otherwise indicated, all parameters apply across both channels at AVDD, DVDD = 2.7 to 3.6V, TA = -40°C to +125°C, MCLK = 4 MHz, PGA GAIN = 1. Characteristic Sym. Min. Typ. Max. Units Test Conditions DVDD Rise Rate to Ensure Internal Power-on Reset Signal SDVDD 0.05 — — V/ms 0 – 3.3V in 0.1s, 0 – 2.5V in 60 ms AVDD Start Voltage to Ensure Internal Power-on Reset Signal VPOR AGND — 2.1 V SAVDD 0.042 — — V/ms IDD — 15 — mA Cell Endurance EPS 100,000 — — E/W Self-Timed Write Cycle Time TIWD — 4 — ms Number of Total Write/Erase Cycles Before Refresh RREF — 10,000,000 — E/W TRETDD 40 — — Years IDDPD — 7 — mA AVDD Rise Rate to Ensure Internal Power-on Reset Signal Operating Current 0 – 2.4V in 50 ms Data EEPROM Memory Characteristic Retention Supply Current during Programming Note 1: 2: 3: 4: 5: 6: 7: Provided no other specifications are violated Calculated from reading the register values with no averaging, single computation cycle with accumulation interval of 16 line cycles, channel 1 or channel 2. Specification by design and characterization; not production tested. N = Value in the Accumulation Interval Parameter register. The default value of this register is 4 or TCAL = 320 ms for 50 Hz line. Applies to Voltage Sag and Voltage Surge events only. Applies to all gains. Offset and gain errors depend on the PGA gain setting. See Section 2.0 “Typical Performance Curves” for typical performance. VIN = 1 VPP = 353 mVRMS @ 50/60 Hz. Variation applies to internal clock and UART only.  2015-2018 Microchip Technology Inc. DS20005473B-page 7 MCP39F511N TABLE 1-2: SERIAL DC CHARACTERISTICS Electrical Specifications: Unless otherwise indicated, all parameters apply at AVDD, DVDD = 2.7 to 3.6 V, TA = -40°C to +125°C, MCLK = 4 MHz Characteristic Sym. Min. VIH 0.8 DVDD Low-Level Input Voltage VIL 0 High-Level Output Voltage VOH 3 Low-Level Output Voltage VOL ILI High-Level Input Voltage Input Leakage Current TABLE 1-3: Typ. Max. Units Test Conditions — DVDD V — 0.2 DVDD V — — V IOH = -3.0 mA, VDD = 3.6V — — 0.4 V IOL = 4.0 mA, VDD = 3.6V — — 1 µA — 0.050 0.100 µA Digital Output pins only (ZCD, PWM, EVENT1, EVENT2) TEMPERATURE SPECIFICATIONS Electrical Specifications: Unless otherwise indicated, all parameters apply at AVDD, DVDD = 2.7 to 3.6V. Parameters Sym. Min. Typ. Max. Units Operating Temperature Range TA -40 — +125 °C Storage Temperature Range TA -65 — +150 °C JA — 36.9 — °C/W Conditions Temperature Ranges Thermal Package Resistance Thermal Resistance, 28LD 5x5 QFN  2015-2018 Microchip Technology Inc. DS20005473B-page 8 MCP39F511N 2.0 TYPICAL PERFORMANCE CURVES Note: The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range), and therefore outside the warranted range. 0.50% 0.40% 0.30% 0.20% 0.10% 0.00% -0.10% -0.20% -0.30% -0.40% -0.50% 0.01 0.1 1 10 100 Current Channel Input Amplitude (mVPEAK) FIGURE 2-1: 0 fIN = -60 dBFS @ 60 Hz fD = 3.9 ksps 16384 pt FFT OSR = 256 -20 -40 Amplitude (dB) Measurement Error (%) Note: Unless otherwise indicated, AVDD = 3.3V, DVDD = 3.3V, TA = +25°C, GAIN = 1, VIN = -0.5 dBFS at 60 Hz, channel 1 or channel 2. -60 -80 -100 -120 -140 -160 -180 -200 1000 0 200 400 600 800 1000 1200 1400 1600 1800 2000 Frequency (Hz) Active Power, Gain = 1. FIGURE 2-4: Spectral Response. RMS Current, Gain = 1. 10 100 1000 -105.8 -105.9 -106.1 Total Harmonic Distortion (-dBc) 1 0.8 0.6 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 -1 1 -106.2 1000 FIGURE 2-5: Total HDrmonic Distortion(dBc) Energy Accumulation Error (%) FIGURE 2-2: 100 -106.4 1 10 Input Voltage RMS (mVPP) -106.5 0.1 -106.7 -0.100% -106.8 -0.050% -107.0 0.000% -107.1 0.050% -107.3 Frequency of Occurrence RMS Current Error (%) 0.100% 10000 100000 THD Histogram. 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 G=1 G=8 -50 -25 0 G=2 G = 16 25 50 75 Temperature (°C) G=4 G = 32 100 125 150 Energy Accumulation (Watt-Hours) FIGURE 2-3: Energy, Gain = 8.  2015-2018 Microchip Technology Inc. FIGURE 2-6: THD vs. Temperature. DS20005473B-page 9 MCP39F511N Note: Unless otherwise indicated, AVDD = 3.3V, DVDD = 3.3V, TA = +25°C, GAIN = 1, VIN = -0.5 dBFS at 60 Hz, channel 1 or channel 2. 94.2 94.3 94.5 94.6 94.8 94.9 95.1 95.2 95.4 95.5 Signal-to-Noise and Distortion Ratio (dB) Signal-to-Noise and Distortion Ratio (dB) FIGURE 2-7: SNR Histogram. 100 90 80 70 60 50 40 30 20 10 0 G=1 G=8 -50 -25 0 FIGURE 2-8: G=2 G = 16 Internal Voltage Reference (V) Frequency of Occurrence 1.2008 1.2007 1.2006 1.2005 1.2004 1.2003 1.2002 1.2001 1.2000 1.1999 -50 FIGURE 2-10: vs. Temperature. 0 50 Temperature (°C) 100 150 Internal Voltage Reference G=4 G = 32 25 50 75 100 125 150 Temperature (°C) SINAD vs. Temperature. 5 4 Gain Error (%) 3 2 1 0 -1 -2 -3 G=1 G=8 -4 -5 -50 -25 0 25 G=2 G = 16 50 75 G=4 G = 32 100 125 150 Temperature (°C) FIGURE 2-9: Gain Error vs. Temperature.  2015-2018 Microchip Technology Inc. DS20005473B-page 10 MCP39F511N 3.0 PIN DESCRIPTION The pin descriptions are listed in Table 3-1. TABLE 3-1: PIN FUNCTION TABLE MCP39F511N 5x5 QFN Symbol 1 EVENT1 2, 3, 8, 9 NC Function Event 1 Output pin No Connect (must be left floating) 4 UART_RX UART Communication RX pin 5 COMMONA Common pin A, to be connected to pin 13 (COMMONB) 6 OSCI Oscillator Crystal Connection pin or External Clock Input pin 7 OSCO Oscillator Crystal Connection pin 10 RESET Reset pin for Delta-Sigma ADCs 11 AVDD 12 UART_TX Analog Power Supply pin UART Communication TX pin Common pin B, to be connected to pin 5 (COMMONA) 13 COMMONB 14 PWM 15 EVENT2 16 I1+ Non-Inverting Current Channel 1 Input for 24-bit  ADC 17 I1- Inverting Current Channel 1 Input for 24-bit  ADC 18 I2- Inverting Voltage Channel 2 Input for 24-bit  ADC 19 I2+ Non-Inverting Current Channel 2 Input for 24-bit  ADC 20 V+ Non-Inverting Voltage Channel Input for 10-bit SAR ADC 21 AGND Analog Ground pin, return path for internal analog circuitry 22 ZCD Zero Crossing Detection Output 23 REFIN+/OUT Pulse-Width Modulation (PWM) Output pin Event 2 Output pin Non-Inverting Voltage Reference Input and Internal Reference Output pin 24, 27 DGND Digital Ground pin, return path for internal digital circuitry 25 DVDD Digital Power Supply pin 26 MCLR Master Clear for device 28 DR Data Ready (must be left floating) 29 EP Exposed Thermal Pad (to be connected to pins 24 and 27 (DGND))  2015-2018 Microchip Technology Inc. DS20005473B-page 11 MCP39F511N 3.1 Event Output Pins (EVENTn) These digital output pins can be configured to act as output flags based on various internal raise conditions. Control is modified through the Event Configuration register. 3.2 UART Communication Pins (UART_RX, UART_TX) The MCP39F511N device contains an asynchronous full-duplex UART. The UART communication is eight bits with the Start and Stop bits. See Section 4.3 “UART Settings” for more information. 3.3 Common Pins (COMMON A and B) The COMMONA and COMMONB pins are internal connections for the MCP39F511N. These two pins should be connected together in the application. 3.4 Oscillator Pins (OSCI/OSCO) OSCI and OSCO provide the master clock for the device. Appropriate load capacitance should be connected to these pins for proper operation. An optional 8 MHz crystal can be connected to these pins. If a crystal or external clock source is not detected, the device will clock from the internal 8 MHz oscillator. 3.5 Reset Pin (RESET) This pin is active-low and places the Delta-Sigma ADCs, PGA, internal VREF and other blocks associated with the analog front-end in a Reset state when pulled low. This input is Schmitt-triggered. 3.6 Master Clear Pin (MCLR) This pin places the SAR, ADC, Calculation Engine, UART serial interface and digital outputs in a Reset state when pulled low. This input is Schmitt-triggered. 3.7 Analog Power Supply Pin (AVDD) AVDD is the power supply pin for the analog circuitry within the MCP39F511N. This pin requires appropriate bypass capacitors and should be maintained to 2.7V and 3.6V for specified operation. It is recommended to use 0.1 µF ceramic capacitors. 3.8 Pulse-Width Modulator (PWM) 3.9 24-Bit Delta-Sigma ADC Differential Current Channel Input Pins (I1+/I1-/I2+/I2-) (I1-, I1+), (I2-, I2+) are the two fully-differential current-channel pair inputs for the Delta-Sigma ADCs. The linear and specified region of the channels are dependent on the PGA gain. This region corresponds to a differential voltage range of ±600 mVPEAK/GAIN with VREF = 1.2V. The maximum absolute voltage, with respect to AGND, for each In+/- input pin is ±1V with no distortion and ±2V with no breaking after continuous voltage. 3.10 Voltage Analog Input (V+) This is the non-inverting input to the SAR ADC for voltage measurement input. This input is used as the voltage measurement for both channel 1 and channel 2. A DC offset of DVDD/2 and no more than 1 VRMS AC input signal should be applied on the pin as shown in the typical application schematic. 3.11 Analog Ground Pin (AGND) AGND is the ground connection to internal analog circuitry (ADCs, PGA, voltage reference, POR). If an analog ground pin is available on the PCB, it is recommended that this pin be tied to that plane. 3.12 Zero Crossing Detection (ZCD) This digital output pin is the output of the zero crossing detection circuit of the IC. The output here will be a logic output with edges that transition at each zero crossing of the voltage channel input. For more information see Section 5.10 “Zero Crossing Detection (ZCD)”. 3.13 Non-Inverting Reference Input/Internal Reference Output Pin (REFIN+/OUT) This pin is the non-inverting side of the differential voltage reference input for the Delta-Sigma ADCs or the internal voltage reference output. For optimal performance, bypass capacitances should be connected between this pin and AGND at all times, even when the internal voltage reference is used. However, these capacitors are not mandatory to ensure proper operation. This digital output is a dedicated PWM output that can be controlled through the PWM Frequency and PWM Duty-Cycle Registers. See Section 8.0 “Pulse-Width modulation (PWM)” for more information.  2015-2018 Microchip Technology Inc. DS20005473B-page 12 MCP39F511N 3.14 Digital Ground Connection Pins (DGND) DGND is the ground connection to internal digital circuitry (SINC filters, oscillator, serial interface). If a digital ground plane is available, it is recommended to tie this pin to the digital plane of the PCB. This plane should also reference all other digital circuitry components in the system. 3.15 Digital Power Supply Pin (DVDD) DVDD is the power supply pin for the digital circuitry within the MCP39F511N. This pin requires appropriate bypass capacitors and should be maintained between 2.7V and 3.6V for specified operations. It is recommended to use 0.1 µF ceramic capacitors. 3.16 Data Ready Pin (DR) The Data Ready pin indicates if a new Delta-Sigma A/D conversion result is ready to be processed. This pin is for indication only and should be left floating. After each conversion is finished, a low pulse will take place on the Data Ready pin to indicate the conversion result is ready and an interrupt is generated in the calculation engine (CE). This pulse is synchronous with the line frequency to ensure an integer number of samples for each line cycle. Note: 3.17 This pin is internally connected to the IRQ of the calculation engine and should be left floating. Exposed Thermal Pad (EP) This pin is the exposed thermal pad. It must be connected to DGND.  2015-2018 Microchip Technology Inc. DS20005473B-page 13 MCP39F511N NOTES:  2015-2018 Microchip Technology Inc. DS20005473B-page 14 MCP39F511N 4.0 COMMUNICATION PROTOCOL Note: If a custom communication protocol is desired, please contact a Microchip sales office. All communication to the device occurs in frames. Each frame consists of a header byte, the number of bytes in the frame, a command packet (or command packets) and a checksum. It is important to note that the maximum number of bytes in either a Receive or Transmit frame is 35. Frame Header Byte (0xA5) Number of Bytes Command Packet1 Command Packet2 ...Command Packet n Checksum Command BYTE1 BYTE2 BYTE N BYTE0 BYTE N FIGURE 4-1: MCP39F511N Communication Frame. This approach allows for single, secure transmission from the host processor to the MCP39F511N with either a single command or multiple commands. No command in a frame is processed until the entire frame is complete and the checksum and number of bytes are validated. The number of bytes in an individual command packet depends on the specific command. For example, to set the instruction pointer, three bytes are needed in the packet: the command byte and two bytes for the address you want to set to the pointer. The first byte in a command packet is always the command byte. 4.1 Device Responses After the reception of a communication frame, the MCP39F511N has three possible responses, which are returned with or without data, depending on the frame received. These responses are either: • Acknowledge (ACK, 0x06): Frame received with success; commands understood and commands executed with success. • Negative Acknowledge (NAK, 0x15): Frame received with success; however, commands not executed with success, commands not understood or some other error in the command bytes. • Checksum Fail (CSFAIL, 0x51): Frame received with success; however, the checksum of the frame did not match the bytes in the frame. Note: There is one unique device ID response used to determine which MCP39FXXX device is present: [NAK(0x15) + ID_BYTE]. If the device is interrogated with 0x5A, i.e. it receives 0x5A as the first byte instead of the standard 0xA5 first header byte, a special NAK is returned followed by an ID_BYTE. For the MCP39F511N the ID_BYTE is 0x03.  2015-2018 Microchip Technology Inc. 4.2 Checksum The checksum is generated using simple byte addition and taking the modulus to find the remainder after dividing the sum of the entire frame by 256. This operation is done to obtain an 8-bit checksum. All the bytes of the frame are included in the checksum, including the header byte and the number of bytes. If a frame includes multiple command packets, none of the commands will be issued if the frame checksum fails. In this instance, the MCP39F511N will respond with a CSFAIL response of 0x51. On commands that are requesting data back from the MCP39F511N, the frame and checksum are created in the same way, with the header byte becoming an Acknowledge (0x06). Communication examples are given in Section 4.5 “Example Communication Frames and MCP39F511N Responses”. 4.3 UART Settings The default baud rate is 115.2 kbps and can be changed using the UART bits in the System Configuration Register. Note that the baud rate is changed only at system power-up, so when changing the baud rate, a Save To Flash command followed by a power-on cycle is required. The UART operates in 8-bit mode, plus one start bit and one stop bit, for a total of 10 bits per byte, as shown in Figure 4-1. IDLE START D0 D1 FIGURE 4-1: D2 D3 D4 D5 D6 D7 STOP IDLE UART Transmission, N-8-1. DS20005473B-page 15 MCP39F511N 4.4 Command List The following table is a list of all accepted command bytes for the MCP39F511N. There are 10 possible accepted commands for the MCP39F511N. TABLE 4-1: MCP39F511N INSTRUCTION SET Command # Command Command ID Instruction Parameter Number of bytes Successful Response UART_TX 1 Register Read, N bytes 0x4E Number of bytes 2 ACK, Data, Checksum 2 Register Write, N bytes 0x4D Number of bytes 1+N ACK 3 Set Address Pointer 0x41 ADDRESS 3 ACK 4 Save Registers To Flash 0x53 None 1 ACK 5 Page Read EEPROM 0x42 PAGE 2 ACK, Data, Checksum 6 Page Write EEPROM 0x50 PAGE 18 ACK 7 Bulk Erase EEPROM 0x4F None 1 ACK 8 Auto-Calibrate Gain 0x5A Channel Selection (1) Note 2 9 Auto-Calibrate Reactive Gain 0x7A Channel Selection (1) Note 2 Auto-Calibrate Frequency 0x76 None Note 2 10 Note 1: 2: 4.5 Each bit in the instruction parameter byte refers to the corresponding channel that is being calibrated with the command. For example, if bits 0 and 1 are high, both channels 1 and 2 will be calibrated. A NAK or ACK will be returned. If a NAK is returned, refer to the Calibration Status bits in the Event Configuration Register for more information. See Section 9.0 “MCP39F511N Calibration” for more information on calibration. Example Communication Frames and MCP39F511N Responses Tables 4-2 to 4-11 show exact hexadecimal communication frames as they are recommended to be sent to the MCP39F511N from the system MCU. The values here can be used as direct examples for writing the code to communicate to the MCP39F511N. TABLE 4-2: REGISTER READ, N BYTES COMMAND (Note 1) Byte # Value Description 1 0xA5 Header Byte 2 0x08 Number of Bytes in Frame 3 0x41 Command (Set Address Pointer) 4 0x00 Address High 5 0x02 Address Low 6 0x4E Command (Register Read, N Bytes) 7 0x20 Number of Bytes to Read (32) 8 0x5E Checksum Response from MCP39F511N ACK + Number of Bytes (35) + 32 bytes + Checksum Note 1: This example Register Read, N bytes frame, as it is written here, can be used to poll a subset of the output data, starting at the top, address 0x02, and reading 32 data bytes back or 35 bytes total in the frame.  2015-2018 Microchip Technology Inc. DS20005473B-page 16 MCP39F511N TABLE 4-3: REGISTER WRITE, N- BYTES COMMAND (Note 1) Byte # Value 1 0xA5 Header Byte 2 0x17 Number of Bytes in Frame (23) 3 0x41 Command (Set Address Pointer) 4 0x00 Address High 5 0xB1 Address Low 6 0x4D Command (Register Write, N Bytes) 7 0x0F Number of Bytes to Write (15) 8-22 *Data* 23 Checksum Description Response from MCP39F511N Data Bytes (15 total data bytes) Checksum ACK Note 1: This Register Write, N Bytes frame, as shown here, is writing channel 1 range and calibration target values, starting at address 0xB1 (the second byte in the Channel 1 Range register) and then writing 15 bytes of data to consecutive addresses to complete the setup of channel 1 registers prior to calibration. Note these are not the calibration registers, but the calibration targets which need to be written prior to issuing the auto-calibration target commands. See Section 9.0 “MCP39F511N Calibration” for more information. TABLE 4-4: SET ADDRESS POINTER COMMAND (Note 1) Byte # Value Description Response from MCP39F511N 1 0xA5 Header Byte 2 0x06 Number of Bytes in Frame 3 0x41 Command (Set Address Pointer) 4 0x00 Address High 5 0x02 Address Low 6 0xEE Checksum ACK Note 1: The Set Address Pointer command is typically included inside of a frame that includes a read or write command, as shown in Tables 4-2 and 4-3. There is typically no reason for this command to have its own frame, but is shown here as an example. TABLE 4-5: SAVE TO FLASH COMMAND Byte # Value 1 0xA5 Header Byte 2 0x04 Number of Bytes in Frame 3 0x53 Command (Save To Flash) 4 0xFC Checksum TABLE 4-6: Description Response from MCP39F511N ACK PAGE READ EEPROM COMMAND Byte # Value 1 0xA5 Header Byte 2 0x05 Number of Bytes in Frame 3 0x42 Command (Page Read EEPROM) 4 0x01 Page Number (e.g. 1) 5 0xED Checksum  2015-2018 Microchip Technology Inc. Description Response from MCP39F511N ACK + EEPROM Page Data + Checksum DS20005473B-page 17 MCP39F511N TABLE 4-7: PAGE WRITE EEPROM COMMAND Byte # Value 1 0xA5 Header Byte 2 0x15 Number of Bytes in Frame 3 0x50 Command (Page Write EEPROM) Page Number (e.g. 1) 4 0x01 5-20 *Data* 21 Checksum TABLE 4-8: Description EEPROM Data (16 bytes/Page) Checksum ACK BULK ERASE EEPROM COMMAND Byte # Value 1 0xA5 Header Byte 2 0x04 Number of Bytes in Frame 3 0x4F Command (Bulk Erase EEPROM) 4 0xF8 Checksum TABLE 4-9: Response from MCP39F511N Description Response from MCP39F511N ACK AUTO-CALIBRATE GAIN COMMAND Byte # Value Description 1 0xA5 Header Byte 2 0x05 Number of Bytes in Frame 3 0x5A Command (Auto-Calibrate Gain) 4 0x03 Instruction Parameter (Channel Instruction, calibrate both channels 1 and 2) 5 0x07 Checksum Response from MCP39F511N ACK (or NAK if unable to calibrate)(1) Note 1: See Section 9.0 “MCP39F511N Calibration” for more information. TABLE 4-10: AUTO-CALIBRATE REACTIVE GAIN COMMAND Byte # Value Description 1 0xA5 Header Byte 2 0x05 Number of Bytes in Frame 3 0x7A Command (Auto-Calibrate Reactive Gain) 4 0x01 Instruction Parameter (Channel Instruction, calibrate channel 1 only) 5 0x25 Checksum Response from MCP39F511N ACK (or NAK if unable to calibrate)(1) Note 1: See Section 9.0 “MCP39F511N Calibration” for more information.  2015-2018 Microchip Technology Inc. DS20005473B-page 18 MCP39F511N TABLE 4-11: AUTO-CALIBRATE FREQUENCY COMMAND Byte # Value Description Response from 1 0xA5 Header Byte 2 0x04 Number of Bytes in Frame 3 0x76 Command (Auto-Calibrate Frequency) 4 0x1F Checksum ACK (or NAK if unable to calibrate)(1) Note 1: See Section 9.0 “MCP39F511N Calibration” for more information. 4.6 4.6.1 Command Descriptions REGISTER READ, N BYTES (0x4E) The Register Read, N Bytes command returns the N bytes that follow whatever the current address pointer is set to. It should typically follow a Set Address Pointer command and can be used in conjunction with other read commands. An Acknowledge, Data and Checksum is the response for this command. The maximum number of bytes that can be read with this command is 32. If there are other read commands within a frame, the maximum number of bytes that can be read is 32 minus the number of bytes being read in the frame. With this command, the data is returned LSB first. 4.6.2 REGISTER WRITE, N BYTES (0x4D) The Register Write, N Bytes command is followed by N bytes that will be written to whatever the current address pointer is set to. It should typically follow a Set Address Pointer command and can be used in conjunction with other write commands. An Acknowledge is the response for this command. The maximum number of bytes that can be written with this command is 32. If there are other write commands within a frame, the maximum number of bytes that can be written is 32 minus the number of bytes being written in the frame. With this command, the data is written LSB first. 4.6.3 SET ADDRESS POINTER (0x41) This command is used to set the address pointer for all read and write commands. This command is expecting the address pointer as the command parameter in the following two bytes: Address High Byte followed by Address Low Byte. The address pointer is two bytes in length. If the address pointer is within the acceptable addresses of the device, an Acknowledge will be returned. 4.6.4 4.6.5 PAGE READ EEPROM (0x42) The Page Read EEPROM command returns 16 bytes of data that are stored in an individual page on the MCP39F511N. A more complete description of the memory organization of the EEPROM can be found in Section 10.0 “EEPROM”. This command is expecting the EEPROM page as the command parameter or the following byte. The response to this command is an Acknowledge, 16-bytes of data and CRC Checksum. 4.6.6 PAGE WRITE EEPROM (0x50) The Page Write EEPROM command is expecting 17 additional bytes in the command parameters, which are the EEPROM page plus 16 bytes of data. A more complete description of the memory organization of the EEPROM can be found in Section 10.0 “EEPROM”. The response to this command is an Acknowledge. 4.6.7 BULK ERASE EEPROM (0x4F) The Bulk Erase EEPROM command will erase the entire EEPROM array and return it to a state of 0xFFFF for each memory location of EEPROM. A more complete description of the memory organization of the EEPROM can be found in Section 10.0 “EEPROM”. The response to this command is Acknowledge. 4.6.8 AUTO-CALIBRATE GAIN (0x5A) The Auto-Calibrate Gain command initiates the single-point calibration that is all that is typically required for the system. This command calibrates the RMS current, RMS voltage and Active power based on the target values written in the corresponding registers. The instruction parameter for this command selects if you are calibrating channel 1, 2 or both. Bit 0 corresponds to channel 1 and bit 1 corresponds to channel 2. See Section 9.0 “MCP39F511N Calibration” for more information on device calibration. The response to this command is Acknowledge. SAVE REGISTERS TO FLASH (0x53) The Save Registers To Flash command makes a copy of all the calibration and configuration registers to flash. This includes all R/W registers in the register set. The response to this command is an Acknowledge.  2015-2018 Microchip Technology Inc. DS20005473B-page 19 MCP39F511N 4.6.9 AUTO-CALIBRATE REACTIVE POWER GAIN (0x7A) The Auto-Calibrate Reactive Gain command initiates a single-point calibration to match the measured Reactive power to the target Reactive power. The instruction parameter for this command selects if you are calibrating channel 1, 2, or both. Bit 0 corresponds to channel 1 and bit 1 corresponds to channel 2. This is typically done at PF = 0.5. See section Section 9.0 “MCP39F511N Calibration” for more information on device calibration. 4.6.10 AUTO-CALIBRATE FREQUENCY (0x76) For applications not using an external crystal and running the MCP39F511N off the internal oscillator, a gain calibration to the line frequency indication is required. The Gain Line Frequency register is set such that the frequency indication matches what is set in the Line Frequency Reference register. See Section 9.0 “MCP39F511N Calibration” for more information on device calibration. 4.7 Notation for Register Types The following notation has been adopted for describing the various registers used in the MCP39F511N: TABLE 4-12: Notation SHORT-HAND NOTATION FOR REGISTER TYPES Description u64 Unsigned, 64-bit register u32 Unsigned, 32-bit register s32 Signed, 32-bit register u16 Unsigned, 16-bit register s16 Signed, 16-bit register b32 32-bit register containing discrete Boolean bit settings  2015-2018 Microchip Technology Inc. DS20005473B-page 20 MCP39F511N 5.0 CALCULATION ENGINE (CE) DESCRIPTION 5.1 Computation Cycle Overview The MCP39F511N uses a coherent sampling algorithm to phase lock the sampling rate to the line frequency on the voltage channel input with an integer number of samples per line cycle, and reports all power output quantities at a 2N number of line cycles. This is defined as a computation cycle and is dependent on the line frequency, so any change in the line frequency will change the update rate of the power outputs. There are two separate computation paths, using two currents from two separate channels (channel 1 and channel 2) referenced below as IN and V. Therefore each current, power, and energy output is duplicated, one for each calculation channel. In addition, there are duplicate calibration registers (offset, gain, phase, etc.) for each calculation channel. 5.1.1 LINE FREQUENCY IN+ + PGA - IN- 24-bit  ADC Multi-Level Modulator CHANNEL IN SINC3 Digital Filter The coherent sampling algorithm is also used to calculate the Line Frequency Output register, which is updated every computation cycle. The correction factor for line frequency measurement is the Gain Line Frequency register, which is used during the line frequency calibration (see section Section 9.6.1 “Using the Auto-Calibrate Frequency Command”. Note that the resolution of the Line Frequency Output register is fixed, and the resolution is 1 mHz. 5.2 Accumulation Interval Parameter The accumulation interval is defined as a 2N number of line cycles, where N is the value in the Accumulation Interval Parameter register. This is identical for both calculation channels. 5.3 Raw Voltage and Currents Signal Conditioning The first set of signal conditioning that occurs inside the MCP39F511N is shown in Figure 5-1. All conditions set in this diagram affect all of the output registers (RMS current, RMS voltage, Active power, Reactive power, apparent power, etc.). The gain of the PGA, the Shutdown and Reset status of the 24-bit ADCs are all controlled through the System Configuration Register. To compensate for any external phase error between the current and voltage channels, the Phase Compensation register can be used. See Section 9.0 “MCP39F511N Calibration” for more information on device calibration. +  HPF (1) iN + SystemConfiguration:b32 PhaseCompensation1:s16 V+ 10-bit SAR ADC  HPF (1) v CHANNEL V Note 1: FIGURE 5-1: High-Pass Filters (HPFs) are automatically disabled in the absence of an AC signal on the voltage channel. Channels 1 or 2 (IN and V) Input-Signal Flow.  2015-2018 Microchip Technology Inc. DS20005473B-page 21 MCP39F511N 5.4 RMS Current, RMS Voltage and Apparent Power (S) The MCP39F511N device provides true RMS measurements. The MCP39F511N device has two simultaneous sampling 24-bit A/D converters for the current measurements. The root mean square calculations are performed on 2N current and voltage samples, where N is defined by the register Accumulation Interval Parameter. EQUATION 5-1: RMS CURRENT AND VOLTAGE N 2 –1  I RMS = N 2 –1  in  2 n=0 ----------------------------N 2   vn  2 n=0 -----------------------------N 2 V RMS = Range:b32 2N-1 0 ÷ 2 X iN  N + ACCU X ÷2RANGE CurrentRMS1,2:u32 + GainCurrentRMS1,2:u16 OffsetCurrentRMS1,2:s32 ApparentPower1,2:u32 GainVoltageRMS:u16 X v 2N-1 0 ÷ 2 N ACCU X ÷2RANGE X VoltageRMS:u16 Range:b32 FIGURE 5-2: RMS Current (Channel 1 or 2), Apparent Power (Channel 1 and 2) and Voltage Calculation Signal Flow. 5.4.1 APPARENT POWER (S) This 32-bit register is the output register for the final apparent power indication. It is the product of RMS current and RMS voltage as shown in Equation 5-2. EQUATION 5-2: APPARENT POWER (S) S = I RMS  V RMS 5.4.2 APPARENT POWER DIVISOR DIGITS Because AppPowerDivisorDigits registers can be higher than 4, it may result in a 32-bit divisor. To improve the speed of this part of the calculation engine, a method that uses only multiplications and right-bit shifts was implemented. Therefore the following equation applies: EQUATION 5-3: APPARENT POWER (S) I RMS  V RMS ApparentPower = --------------------------------------------------------------------10AppPowerDivisorDigits The registers AppPowerDivisorDigits1 and AppPowerDivisorDigits2 are configurable by the user depending on the precision of the RMS indications and the desired precision for ApparentPower1 or ApparentPower2.  2015-2018 Microchip Technology Inc. DS20005473B-page 22 MCP39F511N 5.5 Power and Energy The MCP39F511N offers signed power numbers for active and reactive power, import and export registers for active energy, and four-quadrant reactive power measurement. For this device, import power or energy is considered positive (power or energy being consumed by the load), and export power or energy is considered negative (power or energy being delivered by the load). The following figure represents the measurements obtained by the MCP39F511N. Import Reactive Power Generate, Inductive -P, +Q Quadrant II Consume, Inductive +P, +Q Quadrant I S Q  P Import Active Power Export Active Power Quadrant III Generate, Capacitive -P, -Q Quadrant IV Consume, Capacitive +P, -Q Export Reactive Power FIGURE 5-3: The Power Circle and Triangle (S = Apparent, P = Active, Q = Reactive).  2015-2018 Microchip Technology Inc. DS20005473B-page 23 MCP39F511N 5.6 Energy Accumulation 5.7 Energy accumulation for all four energy registers (import/export, active/reactive) occurs at the end of each computation cycle if the energy accumulation has been turned on. See Section 6.5 “System Configuration Register” for the energy-control bits. The accumulation of energy occurs in one of eight 64-bit energy counters, four for each channel (import and export counters for both active and reactive power). 5.6.1 Active Power (P) The MCP39F511N has three simultaneous sampling A/D converters monitoring two individual currents and two individual active powers. For the Active Power calculations, the instantaneous currents and voltage are multiplied together to create instantaneous power. This instantaneous power is then converted to Active Power by averaging or calculating the DC component. Equation 5-5 controls the number of samples used in this accumulation prior to updating the Active Power output register. NO-LOAD THRESHOLD Please note that although this register is unsigned, the direction of the Active power (import or export) can be determined by the Active Power Sign bit located in the System Status Register. The no-load threshold is set by modifying the value in the No-Load Threshold register. The unit for this register is power with a default resolution of 0.01W. The default value is 100 or 1.00W. Any power that is below 1W will not be accumulated into any of the energy registers. EQUATION 5-5: For scaling of the apparent power indication, the calculation engine uses the Apparent Power Divisor register. This is described in the following register operations, per Equation 5-4. EQUATION 5-4: ACTIVE POWER 1 P = ------N 2 N k=2 –1  Vk  Ik k=0 APPARENT POWER (S) CurrentRMS  VoltageRMS S = --------------------------------------------------------------------ApparentPowerDivisor 10 GainActivePower1,2:u16 iN Range1,2:b32 X 2N-1 0 ÷ 2 ACCU +  X ÷2RANGE ActivePower1,2:u32 + OffsetActivePower1,2:s32 v FIGURE 5-4: N Channel 1 or Channel 2 Active Power Calculation Signal Flow.  2015-2018 Microchip Technology Inc. DS20005473B-page 24 MCP39F511N 5.8 Power Factor (PF) Power factor is calculated by the ratio of P to S, or Active power divided by Apparent power. EQUATION 5-6: POWER FACTOR P PF = --S The Power Factor Reading is stored in two signed 16-bit registers (Power Factor), one for each channel. This register is a signed, two's complement register with the MSB representing the polarity of the power factor. Positive power factor means import power, negative power factor means export power. The sign of the Reactive power component can be used to determine if the load is inductive (positive) or capacitive (negative). Each LSB is then equivalent to a weight of 2-15. A maximum register value of 0x7FFF corresponds to a power factor of 1. The minimum register value of 0x8000 corresponds to a power factor of -1. 5.9 Reactive Power (Q) In the MCP39F511N, Reactive Power is calculated using a 90 degree phase shift in the voltage channel. The same accumulation principles apply as with Active power where ACCU acts as the accumulator. Any light load or residual power can be removed by using the Offset Reactive Power register. Gain is corrected by the Gain Reactive Power register. The final output is an unsigned 32-bit value located in the Reactive Power register. Please note that although this register is unsigned, the direction of the power can be determined by the Reactive Power Sign bit in the System Status Register. GainReactivePower1,2:u16 iN Range1,2:b32 X v FIGURE 5-5: 2N-1 0 ÷ 2 N ACCU1 + -  X ÷2RANGE ReactivePower1,2:u32 OffsetReactivePower1,2:s32 HPF (+90deg.) Channel 1 or Channel 2 Reactive Power Calculation Signal Flow.  2015-2018 Microchip Technology Inc. DS20005473B-page 25 MCP39F511N 5.10 Zero Crossing Detection (ZCD) The zero crossing detection block generates a logic pulse output on the ZCD pin that is coherent with the zero crossing of the input AC signal present on voltage input pin (V+). The ZCD pin can be enabled and disabled by the corresponding bit in the System Configuration Register. When enabled, this produces a square wave with a frequency that is the same as the AC signal present on the voltage input. Figure 5-6 represents the signal on the ZCD pin superimposed with the AC signal present on the voltage input in this mode.