MCP39F521T-E/MQ

MCP39F521 I2C Power Monitor with Calculation and Energy Accumulation Features Description • Power Monitoring Accuracy Capable of 0.1% Error Across 4000:1 Dynamic Range • Built-In Calculations on Fast 16-bit Processing Core - Active, Reactive, Apparent Power - True Root Mean Square (RMS) Current, RMS Voltage - Line Frequency, Power Factor • 64-bit Wide Import and Export Active Energy Accumulation Registers • 64-bit Four Quadrant Reactive Energy Accumulation Registers • Signed Active and Reactive Power Outputs • Dedicated Zero Crossing Detection (ZCD) Pin Output with Less than 100 µs Latency • Automatic Event Pin Control through Fast Voltage Surge Detection, Less than 5 ms Delay • I2C Interface, up to 400 kHz Clock Rate • Two Independent Registers for Minimum and Maximum Output Quantity Tracking • Fast Calibration Routines and Simplified Command Protocol • 512 Bytes User-Accessible EEPROM through Page Read/Write Commands • Low-Drift Internal Voltage Reference, 10 ppm/°C Typical • 28-lead 5 x 5 mm QFN Package • Extended Temperature Range -40°C to +125°C The MCP39F521 is a highly integrated, complete single-phase power-monitoring device, designed for real-time measurement of input power for AC/DC power supplies, power distribution units, consumer and industrial applications. It includes dual-channel delta-sigma ADCs, a 16-bit calculation engine, EEPROM and a flexible two-wire I2C interface. An integrated low-drift voltage reference with 10 ppm/°C in addition to 94.5 dB of signal-to-noise and distortion ratio (SINAD) performance on each measurement channel allows for better than 0.1% accurate designs across a 4000:1 dynamic range.  2015 Microchip Technology Inc. ZCD REFIN+/OUT DVDD DGND MCLR DGND DR 28 27 26 25 24 23 22 EVENT 1 NC 2 21 AGND 20 AN_IN NC 3 19 V1+ EP 29 COMMONB 4 COMMONA 5 18 V117 I116 I1+ OSCI 6 15 A1 OSCO 7 SDA SCL A0 AVDD 8 9 10 11 12 13 14 RESET • Power Monitoring for Home Automation • Industrial Lighting Power Monitoring • Real-Time Measurement of Input Power for AC/DC Supplies • Intelligent Power Distribution Units MCP39F521 5x5 QFN* NC NC Applications Package Types *Includes Exposed Thermal Pad (EP); see Table 3-1. DS20005442A-page 1 MCP39F521 Functional Block Diagram Timing Generation OSCI OSCO V1+ V1- DVDD DGND A1 Internal Oscillator + PGA - 24-bit Delta-Sigma Multi-Level Modulator ADC SINC3 Digital Filter I1- AGND + PGA - 24-bit Delta-Sigma Multi-Level Modulator ADC SINC3 Digital Filter I1+ AVDD AN_IN DS20005442A-page 2 I2C Serial Interface A0 SCL SDA 16-BIT CORE FLASH Calculation Engine (CE) EVENT Digital Outputs ZCD 10-bit SAR ADC  2015 Microchip Technology Inc. MCP39F521 MCP39F521 Typical Application – Single-Phase, Two-Wire Application Schematic 10 1 µF LOAD 0.1 µF 0.1 µF AVDD DVDD RESET 1 k REFIN/OUT+ I1+ + +3.3V 0.1 µF 33 nF 2 m - 1 k I133 nF A1 To DVDD or GND, do not float A0 To DVDD or GND, do not float MCP39F521 1 k 3.3 DVDD V133 nF SCL 499 k 499 k 3.3 DVDD V1+ 2 k 33 nF N.C. Leave Floating Connect on PCB to MCU SCL SDA NC NC NC NC DR COMMONA,B Isolation 1 k Isolation 2 k to MCU SDA (OPTIONAL) +3.3V MCP9700A EVENT AN_IN ZCD OSCO 4 MHz OSCI 22 pF DGND AGND 22 pF (OPTIONAL) +3.3V 0.47 µ F 470 MCP1754 0.01 µF N Note: L DGND 470 µF AGND The external sensing components shown here, a 2 mΩ shunt, two 499 kΩ and 1 kΩ resistors for the 1000:1 voltage divider, are specifically chosen to match the default values for the calibration registers defined in Section 6.0, Register Descriptions. By choosing low-tolerance components of these values (e.g. 1% tolerance), measurement accuracy in the 2-3% range can be achieved with zero calibration. See Section 8.0, MCP39F521 Calibration for more information.  2015 Microchip Technology Inc. DS20005442A-page 3 MCP39F521 1.0 † Notice: Stresses above those listed under “Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings † DVDD .................................................................. -0.3 to +4.5V AVDD .................................................................. -0.3 to +4.0V Digital inputs and outputs w.r.t. AGND ............... -0.3V to +4.0V Analog Inputs (I+,I-,V+,V-) w.r.t. AGND ............... ....-2V to +2V VREF input w.r.t. AGND ........................ ....-0.6V to AVDD +0.6V Maximum Current out of DGND pin..............................300 mA Maximum Current into DVDD pin .................................250 mA Maximum Output Current Sunk by Digital IO ................25 mA Maximum Current Sourced by Digital IO.......................25 mA Storage temperature .....................................-65°C to +150°C Ambient temperature with power applied......-40°C to +125°C Soldering temperature of leads (10 seconds) ............. +300°C ESD on the analog inputs (HBM,MM) .................4.0 kV, 200V ESD on all other pins (HBM,MM) ........................4.0 kV, 200V 1.1 Specifications TABLE 1-1: ELECTRICAL CHARACTERISTICS Electrical Specifications: Unless otherwise indicated, all parameters apply at AVDD, DVDD = 2.7 to 3.6V, TA = -40°C to +125°C, MCLK = 4 MHz, PGA GAIN = 1. Characteristic Sym. Min. Typ. Max. Units Test Conditions Active Power (Note 1) P — ±0.1 — % 4000:1 Dynamic Range on Current Channel (Note 2) Reactive Power (Note 1) Q — ±0.1 — % 4000:1 Dynamic Range on Current Channel (Note 2) Apparent Power (Note 1) S — ±0.1 — % 4000:1 Dynamic Range on Current Channel (Note 2) Current RMS (Note 1) IRMS — ±0.1 — % 4000:1 Dynamic Range on Current Channel (Note 2) Voltage RMS (Note 1) VRMS — ±0.1 — % 4000:1 Dynamic Range on Voltage Channel (Note 2) Power Measurement Power Factor (Note 1)  — ±0.1 — % Line Frequency (Note 1) LF — ±0.1 — % Note 1: 2: 3: 4: 5: 6: 7: Calculated from reading the register values with no averaging, single computation cycle with accumulation interval of 4 line cycles. Specification by design and characterization; not production tested. N = Value in the Accumulation Interval Parameter register. The default value of this register is 2 or TCAL = 80 ms for 50 Hz line. Applies to Voltage Sag and Voltage Surge events only. Applies to all gains. Offset and gain errors depend on the PGA gain setting. See Section 2.0, Typical Performance Curves for typical performance. VIN = 1VPP = 353 mVRMS @ 50/60 Hz. Variation applies to internal clock and I2C only. All calculated output quantities are temperature compensated to the performance listed in the respective specification. DS20005442A-page 4  2015 Microchip Technology Inc. MCP39F521 TABLE 1-1: ELECTRICAL CHARACTERISTICS (CONTINUED) Electrical Specifications: Unless otherwise indicated, all parameters apply at AVDD, DVDD = 2.7 to 3.6V, TA = -40°C to +125°C, MCLK = 4 MHz, PGA GAIN = 1. Characteristic Sym. Min. Typ. Max. Units Test Conditions — 2N x (1/fLINE) — ms Note 3 — see — ms Note 4 Calibration, Calculation and Event Detection Times Auto-Calibration Time Minimum Time for Voltage Surge/Sag Detection tCAL tAC_SASU Section 7.0 24-Bit Delta-Sigma ADC Performance Analog Input Absolute Voltage VIN -1 — +1 V Analog Input Leakage Current AIN — 1 — nA — +600/GAIN mV Differential Input Voltage Range (I1+ – I1-), -600/GAIN (V1+ – V1-) Offset Error VOS Offset Error Drift Gain Error GE — +1 mV 0.5 — µV/°C -4 — +4 % — 1 — ppm/°C 232 — — k G=1 142 — — k G=2 72 — — k G=4 38 — — k G=8 36 — — k G = 16 33 — — k G = 32 SINAD 92 94.5 — dB Note 6 THD — -106.5 -103 dBc Note 6 Gain Error Drift Differential Input Impedance Signal-to-Noise and Distortion Ratio -1 — VREF = 1.2V, proportional to VREF ZIN Total Harmonic Distortion Signal-to-Noise Ratio Note 5 SNR 92 95 — dB Note 6 Spurious Free Dynamic Range SFDR — 111 — dB Note 6 Crosstalk CTALK — -122 — dB AC Power Supply Rejection Ratio AC PSRR — -73 — dB AVDD and DVDD = 3.3V + 0.6VPP, 100 Hz, 120 Hz, 1 kHz DC Power Supply Rejection Ratio DC PSRR — -73 — dB AVDD and DVDD = 3 to 3.6V DC Common Mode Rejection Ratio DC CMRR — -105 — dB VCM varies from -1V to +1V Note 1: 2: 3: 4: 5: 6: 7: Calculated from reading the register values with no averaging, single computation cycle with accumulation interval of 4 line cycles. Specification by design and characterization; not production tested. N = Value in the Accumulation Interval Parameter register. The default value of this register is 2 or TCAL = 80 ms for 50 Hz line. Applies to Voltage Sag and Voltage Surge events only. Applies to all gains. Offset and gain errors depend on the PGA gain setting. See Section 2.0, Typical Performance Curves for typical performance. VIN = 1VPP = 353 mVRMS @ 50/60 Hz. Variation applies to internal clock and I2C only. All calculated output quantities are temperature compensated to the performance listed in the respective specification.  2015 Microchip Technology Inc. DS20005442A-page 5 MCP39F521 TABLE 1-1: ELECTRICAL CHARACTERISTICS (CONTINUED) Electrical Specifications: Unless otherwise indicated, all parameters apply at AVDD, DVDD = 2.7 to 3.6V, TA = -40°C to +125°C, MCLK = 4 MHz, PGA GAIN = 1. Characteristic Sym. Min. Typ. Max. Units bits Test Conditions 10-Bit SAR ADC Performance for Temperature Measurement Resolution NR — 10 — Absolute Input Voltage VIN DGND - 0.3 — DVDD + 0.3 V Recommended Impedance of Analog Voltage Source RIN — — 2.5 k Integral Nonlinearity INL — ±1 ±2 LSb Differential Nonlinearity DNL — ±1 ±1.5 LSb GERR — ±1 ±3 LSb EOFF — ±1 ±2 LSb — fLINE/2N — sps Note 3 fSCL — — 400 kHz 100 kHz and 400 kHz I2C modes supported fMCLK -2% 4 +2% MHz Capacitive Loading on OSCO pin COSC2 — — 15 pF When an external clock is used to drive the device Internal Oscillator Tolerance fINT_OSC — 2 — % -40 to +85°C only (Note 7) VREF -2% 1.2 +2% V TCVREF — 10 — ZOUTVREF — 2 — k AIDDVREF — 40 — µA — — 10 pF AGND + 1.1V — AGND + 1.3V V Gain Error Offset Error Temperature Measurement Rate Clock and Timings I2C Clock Frequency Master Clock and Crystal Frequency Internal Voltage Reference Internal Voltage Reference Tolerance Temperature Coefficient Output Impedance Current, VREF ppm/°C TA = -40°C to +85°C, VREFEXT = 0 Voltage Reference Input Input Capacitance Absolute Voltage on VREF+ Pin Note 1: 2: 3: 4: 5: 6: 7: VREF+ Calculated from reading the register values with no averaging, single computation cycle with accumulation interval of 4 line cycles. Specification by design and characterization; not production tested. N = Value in the Accumulation Interval Parameter register. The default value of this register is 2 or TCAL = 80 ms for 50 Hz line. Applies to Voltage Sag and Voltage Surge events only. Applies to all gains. Offset and gain errors depend on the PGA gain setting. See Section 2.0, Typical Performance Curves for typical performance. VIN = 1VPP = 353 mVRMS @ 50/60 Hz. Variation applies to internal clock and I2C only. All calculated output quantities are temperature compensated to the performance listed in the respective specification. DS20005442A-page 6  2015 Microchip Technology Inc. MCP39F521 TABLE 1-1: ELECTRICAL CHARACTERISTICS (CONTINUED) Electrical Specifications: Unless otherwise indicated, all parameters apply at AVDD, DVDD = 2.7 to 3.6V, TA = -40°C to +125°C, MCLK = 4 MHz, PGA GAIN = 1. Characteristic Sym. Min. Typ. Max. Units Operating Voltage AVDD, DVDD 2.7 — 3.6 V DVDD Start Voltage to Ensure Internal Power-On Reset Signal VPOR DGND — 0.7 V DVDD Rise Rate to Ensure Internal Power-On Reset Signal SDVDD 0.05 — — V/ms AVDD Start Voltage to Ensure Internal Power-On Reset Signal VPOR AGND — 2.1 V AVDD Rise Rate to Ensure Internal Power On Reset Signal SAVDD 0.042 — — V/ms IDD — 13 — mA Cell Endurance EPS 100,000 — — E/W Self-Timed Write Cycle Time TIWD — 4 — ms Number of Total Write/Erase Cycles Before Refresh RREF — 10,000,000 — E/W TRETDD 40 — — Years IDDPD — 7 — mA Test Conditions Power Specifications Operating Current 0 – 3.3V in 0.1s, 0 – 2.5V in 60 ms 0 – 2.4V in 50 ms Data EEPROM Memory Characteristic Retention Supply Current during Programming Note 1: 2: 3: 4: 5: 6: 7: Provided no other specifications are violated Calculated from reading the register values with no averaging, single computation cycle with accumulation interval of 4 line cycles. Specification by design and characterization; not production tested. N = Value in the Accumulation Interval Parameter register. The default value of this register is 2 or TCAL = 80 ms for 50 Hz line. Applies to Voltage Sag and Voltage Surge events only. Applies to all gains. Offset and gain errors depend on the PGA gain setting. See Section 2.0, Typical Performance Curves for typical performance. VIN = 1VPP = 353 mVRMS @ 50/60 Hz. Variation applies to internal clock and I2C only. All calculated output quantities are temperature compensated to the performance listed in the respective specification.  2015 Microchip Technology Inc. DS20005442A-page 7 MCP39F521 TABLE 1-2: SERIAL DC CHARACTERISTICS Electrical Specifications: Unless otherwise indicated, all parameters apply at AVDD, DVDD = 2.7 to 3.6V, TA = -40°C to +125°C, MCLK = 4 MHz Characteristic Sym. Min. High-Level Input Voltage VIH 0.8 DVDD Low-Level Input Voltage VIL 0 High-Level Output Voltage VOH 3 Low-Level Output Voltage VOL — ILI Input Leakage Current TABLE 1-3: Typ. Max. Units Test Conditions — DVDD V — 0.2 DVDD V — — V IOH = -3.0 mA, VDD = 3.6V — 0.4 V IOL = 4.0 mA, VDD = 3.6V — — 1 µA — 0.050 0.100 µA Digital Output pins only (ZCD, EVENT) TEMPERATURE SPECIFICATIONS Electrical Specifications: Unless otherwise indicated, all parameters apply at AVDD, DVDD = 2.7 to 3.6V. Parameters Sym. Min. Typ. Max. Units Operating Temperature Range TA -40 — +125 °C Storage Temperature Range TA -65 — +150 °C JA — 36.9 — °C/W Conditions Temperature Ranges Thermal Package Resistances Thermal Resistance, 28LD 5x5 QFN DS20005442A-page 8  2015 Microchip Technology Inc. MCP39F521 2.0 TYPICAL PERFORMANCE CURVES The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore outside the warranted range. Note: 0.50% 0.40% 0.30% 0.20% 0.10% 0.00% -0.10% -0.20% -0.30% -0.40% -0.50% 0.01 0.1 1 10 100 1000 Current Channel Input Amplitude (mVPEAK) FIGURE 2-1: Active Power, Gain = 1. 0 fIN = -60 dBFS @ 60 Hz fD = 3.9 ksps 16384 pt FFT OSR = 256 -20 -40 Amplitude (dB) Measurement Error (%) Note: Unless otherwise indicated, AVDD = 3.3V, DVDD = 3.3V, TA = +25°C, GAIN = 1, VIN = -0.5 dBFS at 60 Hz. -60 -80 -100 -120 -140 -160 -180 -200 0 200 400 600 800 1000 1200 1400 1600 1800 2000 Frequency (Hz) FIGURE 2-4: Spectral Response. RMS Current, Gain = 1. 1 0.8 0.6 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 -1 1 10 100 1000 10000 -105.8 -105.9 -106.1 -106.2 Total Harmonic Distortion (-dBc) FIGURE 2-5: Total HDrmonic Distortion(dBc) Energy Accumulation Error (%) FIGURE 2-2: 1000 -106.4 1 10 100 Input Voltage RMS (mVPP) -106.5 0.1 -106.7 -0.100% -106.8 -0.050% -107.0 0.000% -107.1 0.050% -107.3 Frequency of Occurrence RMS Current Error (%) 0.100% 100000 THD Histogram. 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 G=1 G=8 -50 -25 0 G=2 G = 16 25 50 75 Temperature (°C) G=4 G = 32 100 125 150 Energy Accumulation (Watt-Hours) FIGURE 2-3: Energy, Gain = 8.  2015 Microchip Technology Inc. FIGURE 2-6: THD vs. Temperature. DS20005442A-page 9 MCP39F521 Note: Unless otherwise indicated, AVDD = 3.3V, DVDD = 3.3V, TA = +25°C, GAIN = 1, VIN = -0.5 dBFS at 60 Hz. Frequency of Occurrence Internal Voltage Reference (V) 1.2008 94.2 94.3 94.5 94.6 94.8 94.9 95.1 95.2 95.4 95.5 Signal-to-Noise and Distortion Ratio (dB) Signal-to-Noise and Distortion Ratio (dB) FIGURE 2-7: SNR Histogram. 100 90 80 70 60 50 40 30 20 10 0 G=1 G=8 -50 -25 0 FIGURE 2-8: G=2 G = 16 1.2007 1.2006 1.2005 1.2004 1.2003 1.2002 1.2001 1.2000 1.1999 -50 FIGURE 2-10: vs. Temperature. 0 50 100 Temperature (C) 150 Internal Voltage Reference G=4 G = 32 25 50 75 100 125 150 Temperature (°C) SINAD vs. Temperature. 5 4 Gain Error (%) 3 2 1 0 -1 -2 -3 G=1 G=8 -4 -5 -50 -25 0 25 G=2 G = 16 50 75 G=4 G = 32 100 125 150 Temperature (°C) FIGURE 2-9: DS20005442A-page 10 Gain Error vs. Temperature.  2015 Microchip Technology Inc. MCP39F521 3.0 PIN DESCRIPTION The description of the pins are listed in Table 3-1. TABLE 3-1: PIN FUNCTION TABLE MCP39F521 5x5 QFN Symbol Function 1 EVENT 2, 3, 8, 9 NC 4 COMMONB Common pin B, to be connected to COMMONA 5 COMMONA Common pin A, to be connected to COMMONB 3.1 Event Output Pin No Connect (must be left floating) 6 OSCI Oscillator Crystal Connection Pin or External Clock Input Pin 7 OSCO Oscillator Crystal Connection Pin 10 RESET Reset Pin for Delta Sigma ADCs 11 AVDD Analog Power Supply Pin 12 A0 I2C Address Select Pin A0 13 SCL I2C Serial Clock 14 SDA I2C Serial Data 15 A1 I2C Address Select Pin A1 16 I1+ Noninverting Current Channel Input for 24-bit  ADC 17 I1- Inverting Current Channel Input for 24-bit  ADC 18 V1- Inverting Voltage Channel Input for 24-bit  ADC Noninverting Voltage Channel Input for 24-bit  ADC 19 V1+ 20 AN_IN Analog Input for SAR ADC 21 AGND Analog Ground Pin, Return Path for internal analog circuitry 22 ZCD Zero Crossing Detection Output 23 REFIN+/OUT Noninverting Voltage Reference Input and Internal Reference Output Pin 24, 27 DGND Digital Ground Pin, Return Path for internal digital circuitry 25 DVDD Digital Power Supply Pin 26 MCLR Master Clear for Device 28 DR Data Ready (must be left floating) 29 EP Exposed Thermal Pad (to be connected to DGND) Event Output Pin (EVENT) This digital output pin can be configured to act as an output flag based on various internal raise conditions. Control is modified through the Event Configuration register. 3.2 Common Pins (COMMONA and COMMONB) The COMMONA and COMMONB pins are internal connections for the MCP39F521. These two pins should be connected together in the application.  2015 Microchip Technology Inc. 3.3 Oscillator Pins (OSCI/OSCO) OSCI and OSCO provide the master clock for the device. Appropriate load capacitance should be connected to these pins for proper operation. An optional 4 MHz crystal can be connected to these pins. If a crystal of external clock source is not detected, the device will clock from the internal 4 MHz oscillator. 3.4 Reset Pin (RESET) This pin is active-low and places the delta-sigma ADCs, PGA, internal VREF and other blocks associated with the analog front-end in a Reset state when pulled low. This input is Schmitt-triggered. DS20005442A-page 11 MCP39F521 3.5 Analog Power Supply Pin (AVDD) AVDD is the power supply pin for the analog circuitry within the MCP39F521. This pin requires appropriate bypass capacitors and should be maintained to 2.7V and 3.6V for specified operation. It is recommended to use 0.1 µF ceramic capacitors. 3.6 Chip Address Inputs (A0, A1) 3.10 24-Bit Delta Sigma ADC Differential Voltage Channel Inputs (V1-/V1+) V1- and V1+ are the two fully-differential voltage channel inputs for the Delta-Sigma ADCs. The linear and specified region of the channels are dependent on the PGA gain. This region corresponds to a differential voltage range of ±600 mVPEAK/GAIN with VREF = 1.2V. The A0 and A1 inputs are used by the MCP39F521 for multiple device operations. The levels on these inputs are compared with the corresponding bits in the slave address. The chip is selected if the compare is true. The maximum absolute voltage, with respect to AGND, for each VN+/- input pin is ±1V with no distortion and ±2V, with no breaking after continuous voltage. Up to four devices may be connected to the same bus by using different combinations. These inputs must be connected to VDD or GND and cannot be left floating. 3.11 In most applications, the chip address inputs are hardwired to logic 0 or logic 1. For applications in which these pins are controlled by a microcontroller or other programmable device, the chip address pins must be driven to logic 0 or logic 1 before normal device operation can proceed. 3.7 I2C Serial Clock (SCL) This input is used to synchronize the data transfer to and from the device. 3.8 I2C Serial Data (SDA) This is a bidirectional pin used to transfer addresses and data into and out of the device. It is an open drain terminal. Therefore, the SDA bus requires a pull-up resistor to DVDD (typical 10k for 100kHz, 2k for 400kHz). Analog Input (AN_IN) This is the input to the analog-to-digital converter that can be used for temperature measurement and compensation. If temperature compensation is required in the application, it is advised to connect the low-power active thermistor IC MCP9700A to this pin. If temperature compensation is not required, this can be used as a general purpose analog-to-digital converter input. 3.12 Analog Ground Pin (AGND) AGND is the ground connection to internal analog circuitry (ADCs, PGA, voltage reference, POR). If an analog ground pin is available on the PCB, it is recommended that this pin be tied to that plane. 3.13 Zero Crossing Detection (ZCD) For normal data transfer, SDA is allowed to change only during SCL low. Change during SCL high is reserved for indicating the Start and Stop conditions. This digital output pin is the output of the Zero Crossing Detection circuit of the IC. The output here will be a logic output with edges that transition at each zero crossing of the voltage channel input. For more information see Section 5.13, Zero Crossing Detection (ZCD). 3.9 3.14 24-Bit Delta Sigma ADC Differential Current Channel Input Pins (I1+/I1-) I1- and I1+ are the two fully-differential current channel inputs for the Delta-Sigma ADCs. The linear and specified region of the channels are dependent on the PGA gain. This region corresponds to a differential voltage range of ±600 mVPEAK/GAIN with VREF = 1.2V. The maximum absolute voltage, with respect to AGND, for each In+/- input pin is ±1V with no distortion and ±6V with no breaking after continuous voltage. DS20005442A-page 12 Noninverting Reference Input/Internal Reference Output Pin (REFIN+/OUT) This pin is the noninverting side of the differential voltage reference input for the delta sigma ADCs or the internal voltage reference output. For optimal performance, bypass capacitances should be connected between this pin and AGND at all times, even when the internal voltage reference is used. However, these capacitors are not mandatory to ensure proper operation.  2015 Microchip Technology Inc. MCP39F521 3.15 Digital Ground Connection Pins (DGND) DGND is the ground connection to internal digital circuitry (SINC filters, oscillator, serial interface). If a digital ground plane is available, it is recommended to tie this pin to the digital plane of the PCB. This plane should also reference all other digital circuitry in the system. 3.16 Digital Power Supply Pin (DVDD) DVDD is the power supply pin for the digital circuitry within the MCP39F521. This pin requires appropriate bypass capacitors and should be maintained between 2.7V and 3.6V for specified operation. It is recommended to use 0.1 µF ceramic capacitors. 3.17 Data Ready Pin (DR) The data ready pin indicates if a new delta-sigma A/D conversion result is ready to be processed. This pin is for indication only and should be left floating. After each conversion is finished, a low pulse will take place on the Data Ready pin to indicate that the conversion result is ready and an interrupt is generated in the calculation engine (CE). This pulse is synchronous with the line frequency to ensure an integer number of samples for each line cycle. Note: 3.18 This pin is internally connected to the IRQ of the calculation engine and should be left floating. Exposed Thermal Pad (EP) This pin is the exposed thermal pad. It must be connected to DGND.  2015 Microchip Technology Inc. DS20005442A-page 13 MCP39F521 NOTES: DS20005442A-page 14  2015 Microchip Technology Inc. MCP39F521 4.0 COMMUNICATION PROTOCOL The I2C communication protocol is a frame-based protocol, with a complete communication frame occurring between the I2C start and stop bits. A command frame is a write transmission from the I2C master to the MCP39F521 device. Each command frame consists of a header byte, the number of bytes in the frame, command packet (or command packets) and a checksum. Each response frame consists of either a ACK, NAK, CSFAIL, or ACK+Data with checksum. If a custom communication protocol is desired, please contact a Microchip sales office. Note: A read response frame is read transmission from the I2C master to the MCP39F521. 4.1 COMMUNICATION FRAMES The following two figures represent the command frames and read request frames. Frame Byte 1 Frame Byte 2 Header Byte (0xA5) Number of Bytes Command Frame Frame Byte 3 ... Command Packet1 Command Packet2 Frame Byte N ...Command Packet n Checksum Command BYTE1 BYTE2 BYTE N BYTE0 BYTE N FIGURE 4-1: MCP39F521 Command Write Frame. Frame Byte 1 Frame Byte 2 ACK (0x06) Number of Bytes FIGURE 4-2: Read Response Frame Frame Byte 3 Frame Byte 4 Data Byte 1 Data Byte 2 ... Frame Byte N-1 ...Data Byte N Frame Byte N Checksum MCP39F521 Read Response Frame (ACK with Data). The following two figures represent I2C command frame writes and read frame responses. S Bus Activity T Command A Control Byte Master Frame Byte 1 R T SDA Line A S1 1101A 1000 A Bus Activity C K FIGURE 4-3: 0 A C K 0 A C K Command Frame Byte N 0 A C K S T O P 0P A C K I2C Command Write Frame. S Response Bus Activity T A Control Byte Master Frame Byte 1 R T SDA Line AA S1 11011010 A Bus Activity C K FIGURE 4-4: Command Frame Byte 3 Command Frame Byte 2 Response Frame Byte 2 0 A C K Frame Byte N Frame Byte 3 0 A C K 0 A C K S T O P 1P N O A C K I2C Read Response Frame.  2015 Microchip Technology Inc. DS20005442A-page 15 MCP39F521 This approach allows for single, secure transmission from the host processor to the MCP39F521 with either a single command, or multiple commands. No command in a frame is processed until the frame is complete and the checksum and number of bytes are validated after the stop bit. The number of bytes in an individual command packet depends on the specific command. For example, to set the instruction pointer, three bytes are needed in the packet: the command byte and two bytes for the address you want to set to the pointer. The first byte in a command packet is always the command byte. 4.2 I2C CONTROL BYTE A Control byte is the first byte received following the Start condition from the master device. The Control byte consists of a 4-bit control code. For the MCP39F521 the control code is ‘1110’ for all read and write operations. The following three bits are chip-select address bits, A2, A1, and A0. For the MCP39F521, A2 is always set to binary ‘1’. A1 and A0 are controlled by the logic pins A1 and A0, which allows up to 4 different devices on the I2C bus. The last bit of the Control byte defines the operation to be performed. When set to ‘1’, a read operation is selected. When set to ‘0’, a write operation is selected. Following a Start condition, the MCP39F521 monitors the SDA bus checking for the 4-bit control code (‘1110’) and proper address bits. Upon receiving the correct control code and address bits, the slave (MCP39F521) outputs an acknowledge signal on the SDA line, and depending on the state of the R/W bit, will either respond with data or wait to receive additional bytes prior to the Stop condition. The Control byte is defined in the following figure. 4.3 I2C Time Out and Clock Stretching Time out is when an I2C slave resets its interface if the I2C clock is low for longer than a specified time. The MCP39F521 offers a set 2 ms I2C time out that can be disabled through the Time-out Disable bit in the System Configuration Register (Register 6-2). In addition, the device includes a clock stretching feature which allows the master to know when a frame has been processed. Clock stretching is when a slave device can not cooperate with the clock speed or needs to slow down the bus. In the case of the MCP39F521, after a frame is received, the device will hold the clock low until the frame has been processed. The maximum clock stretching duration is less than 10 milliseconds. 4.4 Checksum The checksum is generated using simple byte addition and taking the modulus to find the remainder after dividing the sum of the entire frame by 256. This operation is done to obtain an 8-bit checksum. All the bytes of the frame are included in the checksum, including the header byte and number of bytes. If a frame includes multiple command packets, none of the commands will be issued if the frame checksum fails. In this instance, the MCP39F521 will respond with a CSFAIL response of 0x51. On commands that are requesting data back from the MCP39F521, the frame and checksum are created in the same way, with the header byte becoming an acknowledge (0x06). Communication examples are given in Section 4.6, Example Communication Frames and MCP39F521 Responses. Read/Write Bit Chip Select Bits Control Code S 1 Start Bit FIGURE 4-5: 1 1 0 1 A1 A0 R/W ACK Slave Address Acknowledge Bit MCP39F521 Control Byte Format. DS20005442A-page 16  2015 Microchip Technology Inc. MCP39F521 4.5 Command List The following table is a list of all accepted command bytes for the MCP39F521. There are 10 possible accepted commands for the MCP39F521. TABLE 4-1: MCP39F521 INSTRUCTION SET Command # Command Command ID Instruction Parameter Number of Bytes Successful Response 1 Register Read, N bytes 0x4E Number of Bytes 2 ACK, Data, Checksum 2 Register Write, N bytes 0x4D Number of Bytes 1+N ACK 3 Set Address Pointer 0x41 ADDRESS 3 ACK 4 Save Registers To Flash 0x53 None 2 ACK 5 Page Read EEPROM 0x42 PAGE 2 ACK, Data, Checksum 6 Page Write EEPROM 0x50 PAGE 18 ACK 7 Bulk Erase EEPROM 0x4F None 2 8 Auto-Calibrate Gain 0x5A None 9 Auto-Calibrate Reactive Gain 0x7A None Note 1 10 Auto-Calibrate Frequency 0x76 None Note 1 Note 1: 4.6 ACK Note 1 See Section 8.0, MCP39F521 Calibration for more information on calibration. Example Communication Frames and MCP39F521 Responses Tables 4-2 to 4-11 show exact hexadecimal communication frames as they should be sent to the MCP39F521 from the system MCU. The values here can be used as direct examples for writing your code to communicate to the MCP39F521. TABLE 4-2: REGISTER READ, N BYTES COMMAND (Note 1) Byte # Value Byte Description 1 0xA5 Header Byte 2 0x08 Number of Bytes in Frame 3 0x41 Command (Set Address Pointer) 4 0x00 Address High 5 0x02 Address Low 6 0x4E Command (Register Read, N bytes) 7 0x20 Number of Bytes to Read (32) 8 0x5E Checksum Note 1: Response from MCP39F521 ACK + Number of Bytes (35) + 32 bytes, + Checksum This example Register Read, N bytes frame, as written here, can be used to poll a subset of the output data, starting at the top, address 0x02, and reading 32 data bytes back or 35 bytes total in the frame.  2015 Microchip Technology Inc. DS20005442A-page 17 MCP39F521 TABLE 4-3: REGISTER WRITE, N- BYTES COMMAND (Note 1) Byte # Value Byte Description 1 0xA5 2 0x25 Number of Bytes in Frame 3 0x41 Command (Set Address Pointer) 4 0x00 Address High 5 0x48 Address Low Response from MCP39F521 Header Byte 6 0x4D Command (Register Write, N Bytes) 7 0x1C Number of Bytes to Write (28) 8-36 *Data* Data Bytes (28 total data bytes) 37 Checksum Note 1: Checksum ACK This Register Write, N Bytes frame, as written here, can be used to write the entire set of calibration target data, starting at the top, address 0x7A, and continuing to write until the end of this set of registers, 28 bytes later, register 0x94. Note these are not the calibration registers, but the calibration targets which need to be written prior to issuing the auto-calibration target commands. See Section 8.0, MCP39F521 Calibration for more information. TABLE 4-4: SET ADDRESS POINTER COMMAND (Note 1) Byte # Value Byte Description 1 0xA5 Header Byte 2 0x06 Number of Bytes in Frame 3 0x41 Command (Set Address Pointer) 4 0x00 Address High 5 0x02 Address Low 6 0xEE Checksum Note 1: Response from MCP39F521 ACK The Set Address Pointer command is typically included inside of a frame that includes a read or write command, as shown in Table 4-2 and Table 4-3. There is typically no reason for this command to have its own frame, but is shown here as an example. TABLE 4-5: SAVE TO FLASH COMMAND Byte # Value 1 0xA5 Header Byte 2 0x04 Number of Bytes in Frame 3 0x53 Command (Save To Flash) 4 0xFC Checksum TABLE 4-6: Byte Description Response from MCP39F521 ACK PAGE READ EEPROM COMMAND Byte # Value 1 0xA5 Header Byte 2 0x05 Number of Bytes in Frame 3 0x42 Command (Page Read EEPROM) 4 0x01 Page Number (e.g. 1) 5 0xED Checksum DS20005442A-page 18 Byte Description Response from MCP39F521 ACK + EEPROM Page Data + Checksum  2015 Microchip Technology Inc. MCP39F521 TABLE 4-7: PAGE WRITE EEPROM COMMAND Byte # Value 1 0xA5 Header Byte 2 0x15 Number of Bytes in Frame 3 0x50 Command (Page Write EEPROM) Page Number (e.g. 1) 4 0x01 5-20 *Data* 21 Checksum TABLE 4-8: Byte Description Response from MCP39F521 EEPROM Data (16 bytes/Page) Checksum ACK BULK ERASE EEPROM COMMAND Byte # Value 1 0xA5 Header Byte 2 0x04 Number of Bytes in Frame 3 0x4F Command (Bulk Erase EEPROM) 4 0xF8 Checksum TABLE 4-9: Byte Description ACK AUTO-CALIBRATE GAIN COMMAND Byte # Value 1 0xA5 Header Byte 2 0x04 Number of Bytes in Frame 3 0x5A Command (Auto-Calibrate Gain) 4 0x03 Checksum TABLE 4-10: Byte Description Response from MCP39F521 ACK (or NAK if unable to calibrate), see Section 8.0, MCP39F521 Calibration for more information. AUTO-CALIBRATE REACTIVE GAIN COMMAND Byte # Value Byte Description Response from MCP39F521 1 0xA5 Header Byte 2 0x04 Number of Bytes in Frame 3 0x7A Command (Auto-Calibrate Reactive Gain) 4 0x23 Checksum TABLE 4-11: Response from MCP39F521 ACK (or NAK if unable to calibrate), see Section 8.0, MCP39F521 Calibration for more information. AUTO-CALIBRATE FREQUENCY COMMAND Byte # Value Byte Description 1 0xA5 Header Byte 2 0x04 Number of Bytes in Frame 3 0x76 Command (Auto-Calibrate Frequency) 4 0x1F Checksum  2015 Microchip Technology Inc. Response from MCP39F521 ACK (or NAK if unable to calibrate), see Section 8.0, MCP39F521 Calibration for more information. DS20005442A-page 19 MCP39F521 4.7 4.7.1 Command Descriptions REGISTER READ, N BYTES (0x4E) 4.7.6 PAGE WRITE EEPROM (0x50) The Page Write EEPROM command is expecting 17 additional bytes in the command parameters, which are the EEPROM page plus 16 bytes of data. A more complete description of the memory organization of the EEPROM can be found in Section 9.0, EEPROM The response to this command is an acknowledge. The Register Read, N bytes command returns the N bytes that follow whatever the current address pointer is set to. It should typically follow a Set Address Pointer command and can be used in conjunction with other read commands. An acknowledge, data and checksum is the response for this command. The maximum number of bytes that can be read with this command is 32. If there are other read commands within a frame, the maximum number of bytes that can be read is 32 minus the number of bytes being read in the frame. With this command, the data is returned LSB first. The Bulk Erase EEPROM command will erase the entire EEPROM array and return it to a state of 0xFFFF for each memory location of EEPROM. A more complete description of the memory organization of the EEPROM can be found in Section 9.0, EEPROM. The response to this command is acknowledge. 4.7.2 4.7.8 REGISTER WRITE, N BYTES (0x4D) The Register Write, N bytes command is followed by N bytes that will be written to whatever the current address pointer is set to. It should typically follow a Set Address Pointer command and can be used in conjunction with other write commands. An acknowledge is the response for this command. The maximum number of bytes that can be written with this command is 32. If there are other write commands within a frame, the maximum number of bytes that can be written is 32 minus the number of bytes being written in the frame. With this command, the data is written LSB first. 4.7.3 SET ADDRESS POINTER (0x41) This command is used to set the address pointer for all read and write commands. This command is expecting the address pointer as the command parameter in the following two bytes, address high byte followed by address low byte. The address pointer is two bytes in length. If the address pointer is within the acceptable addresses of the device, an acknowledge will be returned. 4.7.4 SAVE REGISTERS TO FLASH (0x53) The Save Registers To Flash command makes a copy of all the calibration and configuration registers to flash. This includes all R/W registers in the register set. The response to this command is an acknowledge. 4.7.5 4.7.7 BULK ERASE EEPROM (0x4F) AUTO-CALIBRATE GAIN (0x5A) The Auto-Calibrate Gain command initiates the single-point calibration that is all that is typically required for the system. This command calibrates the RMS current, RMS voltage and active power based on the target values written in the corresponding registers. See Section 8.0, MCP39F521 Calibration for more information on device calibration. The response to this command is acknowledge. 4.7.9 AUTO-CALIBRATE REACTIVE GAIN (0X7A) The Auto-Calibrate Reactive Gain command initiates a single-point calibration to match the measured reactive power to the target reactive power. This is typically done at PF = 0.5. See section Section 8.0, MCP39F521 Calibration for more information on device calibration. 4.7.10 AUTO-CALIBRATE FREQUENCY (0x76) For applications not using an external crystal and running the MCP39F521 off the internal oscillator, a gain calibration to the line frequency indication is required. The Gain Line Frequency (0x00AE) register is set such that the frequency indication matches what is set in the Line Frequency Reference (0x0094) register. See Section 8.0, MCP39F521 Calibration for more information on device calibration. PAGE READ EEPROM (0x42) The Read Page EEPROM command returns 16 bytes of data that are stored in an individual page on the MCP39F521. A more complete description of the memory organization of the EEPROM can be found in Section 9.0, EEPROM. This command is expecting the EEPROM page as the command parameter or the following byte. The response to this command is an acknowledge, 16-bytes of data and CRC checksum. DS20005442A-page 20  2015 Microchip Technology Inc. MCP39F521 4.8 Notation for Register Types The following notation has been adopted for describing the various registers used in the MCP39F521: TABLE 4-12: Notation SHORT-HAND NOTATION FOR REGISTER TYPES Description u64 Unsigned, 64-bit register u32 Unsigned, 32-bit register s32 Signed, 32-bit register u16 Unsigned, 16-bit register s16 Signed, 16-bit register b32 32-bit register containing discrete Boolean bit settings  2015 Microchip Technology Inc. DS20005442A-page 21 MCP39F521 5.0 CALCULATION ENGINE (CE) DESCRIPTION 5.1 Computation Cycle Overview The MCP39F521 uses a coherent sampling algorithm to phase lock the sampling rate to the line frequency with an integer number of samples per line cycle, and reports all power output quantities at a 2N number of line cycles. This is defined as a computation cycle and is dependent on the line frequency, so any change in the line frequency will change the update rate of the output power quantities. 5.2 Accumulation Interval Parameter 24-bit  ADC Multi-Level Modulator + PGA - I1+ I1- SINC3 Digital Filter The accumulation interval is defined as an 2N number of line cycles, where N is the value in the Accumulation Interval Parameter register. CHANNEL I1 5.3 Raw Voltage and Currents Signal Conditioning The first set of signal conditioning that occurs inside the MCP39F521 is shown in Figure 5-1. All conditions set in this diagram effect all of the output registers (RMS current, RMS voltage, active power, reactive power, apparent power, etc.). The gain of the PGA, the Shutdown and Reset status of the 24-bit ADCs are all controlled through the System Configuration register (Register 6-2). For DC applications, offset can be removed by using the DC Offset Current register. To compensate for any external phase error between the current and voltage channels, the Phase Compensation register can be used. See Section 8.0, MCP39F521 Calibration for more information on device calibration. +  + HPF 1 i DC Offset Current:s16 SystemConfiguration:b32 V1- 24-bit  ADC Multi-Level Modulator SINC3 + PGA - V1+ Digital Filter PhaseCompensation:s16 CHANNEL V1 Note 1: HPF 1 v High-Pass Filters (HPFs) are automatically disabled in the absence of an AC signal on the voltage channel. FIGURE 5-1: 5.4  Channel I1 and V1 Signal Flow. RMS Current and RMS Voltage The MCP39F521 device provides true RMS measurements. The MCP39F521 device has two simultaneous sampling 24-bit A/D converters for the current and voltage measurements. The root mean square calculations are performed on 2N current and voltage samples, where N is defined by the register Accumulation Interval Parameter. EQUATION 5-1: RMS CURRENT AND VOLTAGE N 2 –1  I RMS = N 2 –1  in  2 n=0 ----------------------------N 2 DS20005442A-page 22  V RMS =  vn  2 n=0 -----------------------------N 2  2015 Microchip Technology Inc. MCP39F521 Range:b32 X i 2N-1 0 ÷ 2 N ACCU +  X ÷2RANGE CurrentRMS:u32 + GainCurrentRMS:u16 OffsetCurrentRMS:s32 X ApparentPower:u32 GainVoltageRMS:u16 X v FIGURE 5-2: 5.5 2N-1 0 ÷ 2 X N ACCU ÷2RANGE VoltageRMS:u16 RMS Current and Voltage Calculation Signal Flow. Power and Energy The MCP39F521 offers signed power numbers for active and reactive power, import and export registers for active energy, and four-quadrant reactive power measurement. For this device, import power or energy is considered positive (power or energy being consumed by the load), and export power or energy is considered negative (power or energy being delivered by the load). The following figure represents the measurements obtained by the MCP39F521. Import Reactive Power Consume, Inductive Generate, Inductive -P, +Q Quadrant II Quadrant I +P, +Q S Q  P Import Active Power Export Active Power Quadrant III Generate, Capacitive Quadrant IV Consume, Capacitive +P, -Q -P, -Q Export Reactive Power FIGURE 5-3: The Power Circle and Triangle (S = Apparent, P = Active, Q = Reactive).  2015 Microchip Technology Inc. DS20005442A-page 23 MCP39F521 5.6 Energy Accumulation 5.8 Energy accumulation for all four energy registers (import/export, active/reactive) occurs at the end of each computation cycle, if the energy accumulation has been turned on. See Section 6.3, System Status Register on the Energy Control register. A no-load threshold test is done to make sure the measured energy is not below the no-load threshold; if it is above the no-load threshold, the accumulation occurs with a default energy resolution of 1mWh for all of the energy registers. 5.6.1 The MCP39F521 has two simultaneous sampling A/D converters. For the active power calculation, the instantaneous current and instantaneous voltages are multiplied together to create instantaneous power. This instantaneous power is then converted to active power by averaging or calculating the DC component. Equation 5-4 controls the number of samples used in this accumulation prior to updating the Active Power output register. Please note that although this register is unsigned, the direction of the active power (import or export) can be determined by the Active Power Sign bit (SIGN_PA) located in the System Status register (Register 6-1). NO-LOAD THRESHOLD The no-load threshold is set by modifying the value in the No-Load Threshold register. The unit for this register is power with a default resolution of 0.01W. The default value is 100 or 1.00W. Any power that is below 1W will not be accumulated into any of the energy registers. 5.7 Active Power (P) EQUATION 5-4: ACTIVE POWER 1 P = ------N 2 Apparent Power (S) N k=2 –1  Vk  Ik k=0 This 32-bit register is the output register for the final apparent power indication. It is the product of RMS current and RMS voltage as shown in Equation 5-2. EQUATION 5-2: APPARENT POWER (S) S = I RMS  V RMS For scaling of the apparent power indication, the calculation engine uses the register Apparent Power Divisor. This is described in the following register operations, per Equation 5-3. EQUATION 5-3: APPARENT POWER (S) CurrentRMS  VoltageRMS S = --------------------------------------------------------------------ApparentPowerDivisor 10 GainActivePower:u16 i Range:b32 X v FIGURE 5-4: DS20005442A-page 24 2N-1 0 ÷ 2 ACCU N +  X ÷2RANGE ActivePower:u32 + OffsetActivePower:s32 Active Power Calculation Signal Flow.  2015 Microchip Technology Inc. MCP39F521 5.9 Power Factor (PF) Power factor is calculated by the ratio of P to S or active power divided by apparent power. EQUATION 5-5: POWER FACTOR P PF = --S The Power Factor Reading is stored in a signed 16-bit register (Power Factor). This register is a signed, two's complement register with the MSB representing the polarity of the power factor. Positive means inductive load, negative means capacitive load. Each LSB is then equivalent to a weight of 2-15. A maximum register value of 0x7FFF corresponds to a power factor of 1. The minimum register value of 0x8000 corresponds to a power factor of -1. 5.10 Reactive Power (Q) In the MCP39F521, Reactive Power is calculated using a 90 degree phase shift in the voltage channel. The same accumulation principles apply as with active power where ACCU acts as an accumulator. Any light load or residual power can be removed by using the Offset Reactive Power register. Gain is corrected by the Gain Reactive Power register. The final output is an unsigned 32-bit value located in the Reactive Power register. Please note that although this register is unsigned, the direction of the power can be determined by the Reactive Power Sign bit (SIGN_PR) in the System Status register (Register 6-1). GainReactivePower:u16 i HPF Range:b32 X v FIGURE 5-5: 2N-1 0 ÷ 2 N ACCU1 +  - X ÷2RANGE ReactivePower:u32 OffsetReactivePower:s32 HPF (+90deg.) Reactive Power Calculation Signal Flow.  2015 Microchip Technology Inc. DS20005442A-page 25 MCP39F521 5.11 10-Bit Analog Input The least 10 significant bits of the 16-bit Analog Input register contain the output of the 10-bit ADC. The conversion rate of the analog input occurs once every computation cycle. The Thermistor Voltage can be used for temperature compensation of the calculation engine. See Section 8.7, Temperature Compensation for more information. MCP9700 10-bit ADC AnalogInput:u16 5.13 Zero Crossing Detection (ZCD) The Zero Crossing Detection block generates a logic pulse output on the ZCD pin that is coherent with the zero crossing of the input AC signal present on voltage input pins (V1+, V1-). The ZCD pin can be enabled and disabled by the corresponding bit (ZCD_OUTPUT_DIS) in the System Configuration register (Register 6-2). When enabled, this produces a square wave with a frequency that is twice that of the AC signal present on the voltage input. Figure 5-7 represents the signal on the ZCD pin superimposed with the AC signal present on the voltage input in this mode.