MCP4728A0T-E/UNVAO

MCP4728 12-Bit, Quad Digital-to-Analog Converter with EEPROM Memory Features Description • 12-Bit Voltage Output DAC with Four Buffered Outputs • On-Board Nonvolatile Memory (EEPROM) for DAC Codes and I2C™ Address Bits • Internal or External Voltage Reference Selection • Output Voltage Range: - Using Internal VREF (2.048V): The MCP4728 device is a quad, 12-bit voltage output Digital-to-Analog Convertor (DAC) with nonvolatile memory (EEPROM). Its on-board precision output amplifier allows it to achieve rail-to-rail analog output swing. 0.000V to 2.048V with Gain Setting = 1 0.000V to 4.096V with Gain Setting = 2 - Using External VREF (VDD): 0.000V to VDD • ±0.2 Least Significant Bit (LSB) Differential Nonlinearity (DNL) (typical) • Fast Settling Time: 6 µs (typical) • Normal or Power-Down Mode • Low Power Consumption • Single-Supply Operation: 2.7V to 5.5V • I2C Interface: - Address bits: User Programmable to EEPROM - Standard (100 kbps), Fast (400 kbps) and High Speed (HS) Mode (3.4 Mbps) • 10-Lead MSOP Package • Extended Temperature Range: -40°C to +125°C Applications • • • • • • • • • Set Point or Offset Adjustment Sensor Calibration Closed-Loop Servo Control Low Power Portable Instrumentation PC Peripherals Programmable Voltage and Current Source Industrial Process Control Instrumentation Bias Voltage Adjustment for Power Amplifiers © 2010 Microchip Technology Inc. The DAC input codes, device configuration bits, and I2C address bits are programmable to the nonvolatile memory (EEPROM) by using I2C serial interface commands. The nonvolatile memory feature enables the DAC device to hold the DAC input codes during power-off time, allowing the DAC outputs to be available immediately after power-up with the saved settings. This feature is very useful when the DAC device is used as a supporting device for other devices in the application’s network. The MCP4728 device has a high precision internal voltage reference (VREF = 2.048V). The user can select the internal reference or external reference (VDD) for each channel individually. Each channel can be operated in Normal mode or Power-Down mode individually by setting the configuration register bits. In Power-Down mode, most of the internal circuits in the powered down channel are turned off for power savings, and the output amplifier can be configured to present a known low, medium, or high resistance output load. The MCP4728 device includes a Power-on Reset (POR) circuit to ensure reliable power-up and an on-board charge pump for the EEPROM programming voltage. The MCP4728 has a two-wire I2C compatible serial interface for standard (100 kHz), fast (400 kHz), or high speed (3.4 MHz) mode. The MCP4728 DAC is an ideal device for applications requiring design simplicity with high precision, and for applications requiring the DAC device settings to be saved during power-off time. The MCP4728 device is available in a 10-lead MSOP package and operates from a single 2.7V to 5.5V supply voltage. DS22187E-page 1 MCP4728 Package Type MCP4728 MSOP VDD 1 10 VSS SCL 2 9 VOUT D SDA 3 8 VOUT C LDAC 4 7 VOUT B RDY/BSY 5 6 VOUT A Functional Block Diagram LDAC EEPROM A VDD INPUT REGISTER A VSS SDA SCL I2C Interface Logic EEPROM B INPUT REGISTER B EEPROM C INPUT REGISTER C EEPROM D RDY/BSY INPUT REGISTER D Internal VREF (2.048V) OUTPUT REGISTER A UDAC OUTPUT REGISTER B UDAC OUTPUT REGISTER C UDAC OUTPUT REGISTER D VREF Selector VDD DS22187E-page 2 UDAC VREF A STRING DAC A VREF B OP AMP B VOUT B Power Down Control Output Logic OP AMP C VOUT C Power Down Control Gain Control STRING DAC D VOUT A Power Down Control Output Logic Gain Control STRING DAC C VREF D OP AMP A Gain Control STRING DAC B VREF C Output Logic Gain Control OP AMP D VREF Output Logic VOUT D Power Down Control (VREF A, VREF B, VREF C, VREF D) © 2010 Microchip Technology Inc. MCP4728 1.0 ELECTRICAL CHARACTERISTICS † Notice: Stresses above those listed under “Maximum Absolute Maximum Ratings† VDD...................................................................................6.5V All inputs and outputs w.r.t VSS ................. -0.3V to VDD+0.3V Current at Input Pins ....................................................±2 mA ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. Current at Supply Pins ............................................. ±110 mA Current at Output Pins ...............................................±25 mA Storage Temperature ...................................-65°C to +150°C Ambient Temp. with Power Applied .............-55°C to +125°C ESD protection on all pins ................ ≥ 4 kV HBM, ≥ 400V MM Maximum Junction Temperature (TJ) ......................... +150°C ELECTRICAL CHARACTERISTICS Electrical Specifications: Unless otherwise indicated, all parameters apply at VDD = +2.7V to 5.5V, VSS = 0V, RL = 5 kΩ, CL = 100 pF, GX = 1, TA = -40°C to +125°C. Typical values are at +25°C, VIH = VDD, VIL = VSS. Parameter Symbol Min VDD 2.7 IDD_EXT — Typical Max Units Conditions 5.5 V 800 1400 µA VREF = VDD, VDD = 5.5V All 4 channels are in Normal mode. — 600 — µA 3 channels are in Normal mode, 1 channel is powered down. — 400 — µA 2 channels are in Normal mode, 2 channel are powered down. — 200 — µA 1 channel is in Normal mode, 3 channels are powered down. Power Requirements Operating Voltage Supply Current with External Reference (VREF = VDD) (Note 1) Power-Down Current with External Reference IPD_EXT — 40 — nA All 4 channels are powered down. (VREF = VDD) Supply Current with Internal Reference (VREF = Internal) (Note 1) IDD_INT — 800 1400 µA VREF = Internal Reference VDD = 5.5V All 4 channels are in normal mode. — 600 — µA 3 channels are in Normal mode, 1 channel is powered down. — 400 — µA 2 channels are in Normal mode, 2 channels are powered down. — 200 — µA 1 channel is in Normal mode, 3 channels are powered down. — 45 60 µA All 4 channels are powered down. VREF = Internal Reference Power-Down Current with Internal Reference Note 1: 2: 3: 4: 5: 6: 7: 8: 9: IPD_INT All digital input pins (SDA, SCL, LDAC) are tied to “High”, Output pins are unloaded, code = 0 x 000. The power-up ramp rate measures the rise of VDD over time. This parameter is ensured by design and not 100% tested. This parameter is ensured by characterization and not 100% tested. Test code range: 100 - 4000 codes, VREF = VDD, VDD = 5.5V. Time delay to settle to a new reference when switching from external to internal reference or vice versa. This parameter is indirectly tested by Offset and Gain error testing. Within 1/2 LSB of the final value when code changes from 1/4 of to 3/4 of full scale. This time delay is measured from the falling edge of ACK pulse in I2C command to the beginning of VOUT. This time delay is not included in the output settling time specification. © 2010 Microchip Technology Inc. DS22187E-page 3 MCP4728 ELECTRICAL CHARACTERISTICS (CONTINUED) Electrical Specifications: Unless otherwise indicated, all parameters apply at VDD = +2.7V to 5.5V, VSS = 0V, RL = 5 kΩ, CL = 100 pF, GX = 1, TA = -40°C to +125°C. Typical values are at +25°C, VIH = VDD, VIL = VSS. Parameter Symbol Min Typical Max Units Conditions Power-on Reset Threshold Voltage VPOR — 2.2 — V All circuits, including EEPROM, are ready to operate. Power-Up Ramp Rate VRAMP 1 — — V/s Note 2, Note 4 n 12 — — Bits Code Change: 000h to FFFh Integral Nonlinearity (INL) Error INL — ±2 ±13 LSB Note 5 DNL Error DNL -0.75 ±0.2 ±0.75 LSB Note 5 VOS — 5 20 mV Code = 000h See Figure 2-24 DC Accuracy Resolution Offset Error Offset Error Drift Gain Error Gain Error Drift ΔVOS/°C — ±0.16 — ppm/°C -45°C to +25°C — ±0.44 — ppm/°C +25°C to +125°C GE -1.25 0.4 +1.25 % of FSR ΔGE/°C — -3 — ppm/°C 2.048 2.089 Code = FFFh, Offset error is not included. Typical value is at room temperature See Figure 2-25 Internal Voltage Reference (VREF), (Note 3) Internal Voltage Reference Temperature Coefficient VREF ΔVREF/°C 2.007 V — 125 — ppm/°C -40 to 0°C — 0.25 — LSB/°C — 45 — ppm/°C 0 to +125°C — 0.09 — LSB/°C Reference Output Noise ENREF — 290 — µVp-p Code = FFFh, 0.1 – 10 Hz, Gx = 1 Output Noise Density eNREF — 1.2 — μV HZ Code = FFFh, 1 kHz, Gx = 1 1/f Corner Frequency fCORNER Note 1: 2: 3: 4: 5: 6: 7: 8: 9: — 1.0 — — 400 — Code = FFFh, 10 kHz, Gx = 1 Hz All digital input pins (SDA, SCL, LDAC) are tied to “High”, Output pins are unloaded, code = 0 x 000. The power-up ramp rate measures the rise of VDD over time. This parameter is ensured by design and not 100% tested. This parameter is ensured by characterization and not 100% tested. Test code range: 100 - 4000 codes, VREF = VDD, VDD = 5.5V. Time delay to settle to a new reference when switching from external to internal reference or vice versa. This parameter is indirectly tested by Offset and Gain error testing. Within 1/2 LSB of the final value when code changes from 1/4 of to 3/4 of full scale. This time delay is measured from the falling edge of ACK pulse in I2C command to the beginning of VOUT. This time delay is not included in the output settling time specification. DS22187E-page 4 © 2010 Microchip Technology Inc. MCP4728 ELECTRICAL CHARACTERISTICS (CONTINUED) Electrical Specifications: Unless otherwise indicated, all parameters apply at VDD = +2.7V to 5.5V, VSS = 0V, RL = 5 kΩ, CL = 100 pF, GX = 1, TA = -40°C to +125°C. Typical values are at +25°C, VIH = VDD, VIL = VSS. Parameter Symbol Min Typical Max Units Conditions Analog Output (Output Amplifier) Output Voltage Swing VOUT — FSR — V Note 7 Full Scale Range (Note 7) FSR — VDD — V VREF = VDD FSR = from 0.0V to VDD — VREF — V VREF = Internal, Gx = 1, FSR = from 0.0 V to VREF — 2 * VREF — V VREF = Internal, Gx = 2, FSR = from 0.0V to 2 * VREF TSETTLING — 6 — µs Note 8 Analog Output Time Delay from Power-Down Mode TdExPD — 4.5 — µs VDD = 5V, Note 4, Note 9 Time delay to settle to new reference (Note 4, Note 6) TdREF — 26 — µs From External to Internal Reference — 44 — µs From Internal to External Reference Power Supply Rejection PSRR — -57 — dB Capacitive Load Stability CL — — 1000 Slew Rate SR — 0.55 — Phase Margin pM — 66 — Short Circuit Current ISC — 15 24 mA Short Circuit Current Duration TSC_DUR — Infinite — hours Output Voltage Settling Time DC Output Impedance (Note 4) Note 1: 2: 3: 4: 5: 6: 7: 8: 9: ROUT pF VDD = 5V ±10%, VREF = Internal RL = 5 kΩ No oscillation, Note 4 V/µs Degree CL = 400 pF, RL = ∞ (°) VDD = 5V, All VOUT Pins = Grounded. Tested at room temperature. Note 4 — 1 — Ω Normal mode — 1 — kΩ Power-Down mode 1 (PD1:PD0 = 0:1), VOUT to VSS — 100 — kΩ Power-Down mode 2 (PD1:PD0 = 1:0), VOUT to VSS — 500 — kΩ Power-Down mode 3 (PD1:PD0 = 1:1), VOUT to VSS All digital input pins (SDA, SCL, LDAC) are tied to “High”, Output pins are unloaded, code = 0 x 000. The power-up ramp rate measures the rise of VDD over time. This parameter is ensured by design and not 100% tested. This parameter is ensured by characterization and not 100% tested. Test code range: 100 - 4000 codes, VREF = VDD, VDD = 5.5V. Time delay to settle to a new reference when switching from external to internal reference or vice versa. This parameter is indirectly tested by Offset and Gain error testing. Within 1/2 LSB of the final value when code changes from 1/4 of to 3/4 of full scale. This time delay is measured from the falling edge of ACK pulse in I2C command to the beginning of VOUT. This time delay is not included in the output settling time specification. © 2010 Microchip Technology Inc. DS22187E-page 5 MCP4728 ELECTRICAL CHARACTERISTICS (CONTINUED) Electrical Specifications: Unless otherwise indicated, all parameters apply at VDD = +2.7V to 5.5V, VSS = 0V, RL = 5 kΩ, CL = 100 pF, GX = 1, TA = -40°C to +125°C. Typical values are at +25°C, VIH = VDD, VIL = VSS. Parameter Symbol Min Typical Max Units — 45 — nV-s Conditions Dynamic Performance (Note 4) Major Code Transition Glitch Digital Feedthrough —