MCP47CXDX1/2
8/10/12-Bit Digital-to-Analog Converters, 1 LSb INL,
Single/Dual Voltage Outputs with I2C Interface
MCP47CXDX1 (Single)
MSOP-10, DFN-10 (3x3)
VDD 1
A0 2
10 SDA
VREF 3
8 A1
VOUT 4
7 VSS
9 SCL
NC 5
6 LAT/HVC
A0 1
VREF 2
13 SDA
14 NC
15 NC
16 VDD
QFN-16 (3x3)
12 SCL
11 A1
17 EP(1)
VOUT 3
10 VSS
NC 4
NC 8
NC 6
NC 7
NC 5
9 LAT/HVC
MCP47CXDX2 (Dual)
MSOP-10, DFN-10 (3x3)
VDD 1
A0 2
10 SDA
VREF 3
8 A1
VOUT0 4
7 VSS
VOUT1 5
6 LAT/HVC(2)
9 SCL
13 SDA
14 NC
15 NC
QFN-16 (3x3)
16 VDD
A0 1
VREF0 2
VOUT0 3
12 SCL
11 A1
17 EP(1)
10 VSS
VREF1 4
LAT1 8
NC 6
9 LAT0/HVC
NC 7
• Memory Options:
- Volatile Memory: MCP47CVDXX
- Nonvolatile Memory: MCP47CMDXX
• Operating Voltage Range:
- 2.7V to 5.5V – full specifications
- 1.8V to 2.7V – reduced device specifications
• Output Voltage Resolutions:
- 8-bit: MCP47CXD0X (256 steps)
- 10-bit: MCP47CXD1X (1024 steps)
- 12-bit: MCP47CXD2X (4096 steps)
• Nonvolatile Memory (MTP) Size: 32 Locations
• 1 LSb Integral Nonlinearity (INL) Specification
• DAC Voltage Reference Source Options:
- Device VDD
- External VREF pin (buffered or unbuffered)
- Internal band gap (1.214V typical)
• Output Gain Options:
- 1x (unity)
- 2x (available when not using internal VDD as
voltage source)
• Power-on/Brown-out Reset (POR/BOR)
Protection
• Power-Down Modes:
- Disconnects output buffer (high-impedance)
- Selection of VOUT pull-down resistors
(100 k or 1 k)
• I2C Interface:
- Client address options: register-defined
address with two physical address select pins
(package dependent)
- Standard (100 kbps), Fast (400 kbps) and
High-Speed (up to 3.4 Mbps) modes
• Package Types:
- Dual: 16-lead 3 x 3 QFN, 10-lead MSOP,
10-lead 3 x 3 DFN
- Single: 16-lead 3 x 3 QFN, 10-lead MSOP,
10-lead 3 x 3 DFN
• Extended Temperature Range: -40°C to +125°C
Package Types
VOUT1 5
Features
Note 1: Exposed pad (substrate paddle).
2: This pin’s signal can be connected to DAC0
and/or DAC1.
2022 Microchip Technology Inc. and its subsidiaries
DS20006666B-page 1
MCP47CXDX1/2
General Description
The MCP47CXDX1/2 devices are single and dual
channel 8-bit, 10-bit and 12-bit buffered voltage output
Digital-to-Analog Converters (DAC) with volatile or
MTP memory and an I2C serial interface.
The MTP memory can be written by the user up to
32 times for each specific register. It requires a highvoltage level on the HVC pin, typically 7.5V, in order to
successfully program the desired memory location.
The nonvolatile memory includes power-up output
values, device configuration registers and general
purpose memory.
The VREF pin, the device VDD or the internal band gap
voltage can be selected as the DAC’s reference
voltage. When VDD is selected, VDD is internally
connected to the DAC reference circuit.
When the VREF pin is used with an external voltage
reference, the user can select between a gain of 1 or 2
and can have the reference buffer enabled or disabled.
When the gain is 2, the VREF pin voltage must be
limited to a maximum of VDD/2.
These devices have a two-wire I2C compatible serial
interface for Standard (100 kHz), Fast (400 kHz) or
High-Speed (1.7 MHz and 3.4 MHz) modes.
Applications
•
•
•
•
•
Set Point or Offset Trimming
Sensor Calibration
Low-Power Portable Instrumentation
PC Peripherals
Data Acquisition Systems
MCP47CMDX1 Block Diagram (Single Channel Output)
VDD
VSS
SDA
SCL
A0
A1
Memory
Power-up/Brown-out Control
VOLATILE (4 x 16)
DAC0
VREF
POWER-DOWN
GAIN
STATUS
I2C Serial Interface Module
and Control Logic
(WiperLock™ Technology)
ADDR6:ADDR0
NONVOLATILE (13 x 16)
VIHH
LAT/HVC
LAT0
VDD
DAC0
VREF
POWER-DOWN
GAIN/I2C ADDRESS
WiperLock™
PD1:PD0 and
VREF1:VREF0
Band Gap
1.214V
VBG
GAIN
VREF1:VREF0
VOUT0
OP AMP
PD1:PD0
100 k
Resistor
Ladder
VDD
1 k
VREF0
VREF1:VREF0
DS20006666B-page 2
2022 Microchip Technology Inc. and its subsidiaries
MCP47CXDX1/2
MCP47CMDX2 Block Diagram (Dual Channel Output)
VDD
VSS
SDA
SCL
A0
A1
Memory
Power-up/Brown-out Control
VOLATILE (5 x 16)
DAC0 and DAC1
VREF
POWER-DOWN
GAIN
STATUS
I2C Serial Interface Module
and Control Logic
(WiperLock™ Technology)
ADDR6:ADDR0
NONVOLATILE (14 x 16)
VIHH
LAT0/HVC
LAT0
VDD
DAC0 and DAC1
VREF
POWER-DOWN
GAIN/I2C ADDRESS
WiperLock™
PD1:PD0 and
VREF1:VREF0
Band Gap
1.214V
VBG
GAIN
VREF1:VREF0
VOUT0
PD1:PD0
1 k
Resistor
Ladder
VDD
100 k
OP AMP
VREF0(2)
VREF1:VREF0
LAT1(1)
LAT0(1)
VDD
PD1:PD0 and
VREF1:VREF0
GAIN
VBG
VREF1:VREF0
VOUT1
PD1:PD0
1 k
Resistor
Ladder
VDD
100 k
OP AMP
VREF1(2)
VREF1:VREF0
Note 1:
2:
On dual output devices, except those in a QFN16 package, the LAT0 pin is internally connected to
the LAT1 input of DAC1.
On dual output devices, except those in a QFN16 package, the VREF0 pin is internally connected to
the VREF1 input of DAC1.
2022 Microchip Technology Inc. and its subsidiaries
DS20006666B-page 3
MCP47CXDX1/2
# of LAT Inputs(3)
# of Address Pins
Memory(2)
GP MTP Locations
MSOP, QFN, DFN
1
8
7Fh
1
1
2
RAM
—
MCP47CVD11
MSOP, QFN, DFN
1
10
1FFh
1
1
2
RAM
—
MCP47CVD21
MSOP, QFN, DFN
1
12
7FFh
1
1
2
RAM
—
QFN
2
8
7Fh
2
2
2
RAM
—
MSOP, DFN
2
8
7Fh
1
1
2
RAM
—
QFN
2
10
1FFh
2
2
2
RAM
—
MSOP, DFN
2
10
1FFh
1
1
2
RAM
—
QFN
2
12
7FFh
2
2
2
RAM
—
MCP47CVD02
MCP47CVD12
MCP47CVD22
Package Type
Resolution (bits)
MCP47CVD01
Device
# of Channels
# of VREF Inputs
Family Device Features
DAC Output
POR/BOR
Setting(1)
MSOP, DFN
2
12
7FFh
1
1
2
RAM
—
MCP47CMD01
MSOP, QFN, DFN
1
8
7Fh
1
1
2
MTP
8
MCP47CMD11
MSOP, QFN, DFN
1
10
1FFh
1
1
2
MTP
8
MCP47CMD21
MSOP, QFN, DFN
1
12
7FFh
1
1
2
MTP
8
QFN
2
8
7Fh
2
2
2
MTP
8
MSOP, DFN
2
8
7Fh
1
1
2
MTP
8
QFN
2
10
1FFh
2
2
2
MTP
8
MSOP, DFN
2
10
1FFh
1
1
2
MTP
8
QFN
2
12
7FFh
2
2
2
MTP
8
MSOP, DFN
2
12
7FFh
1
1
2
MTP
8
MCP47CMD02
MCP47CMD12
MCP47CMD22
Note 1:
2:
3:
The factory default value.
Each nonvolatile memory location can be written 32 times. For subsequent writes to the MTP, the device
will ignore the commands and the memory will not be modified.
If the product is a dual device and the package has only one LAT pin, it is associated with both DAC0 and
DAC1.
DS20006666B-page 4
2022 Microchip Technology Inc. and its subsidiaries
MCP47CXDX1/2
1.0
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings(†)
Voltage on VDD with Respect to VSS ........................................................................................................ -0.6V to +6.5V
Voltage on all Pins with Respect to VSS ........................................................................................... -0.6V to VDD + 0.3V
Input Clamp Current, IIK (VI < 0, VI > VDD, VI > VPP on HV pins) ........................................................................ ±20 mA
Output Clamp Current, IOK (VO < 0 or VO > VDD) ................................................................................................. ±20 mA
(Single) ..........................................................................................................50 mA
Maximum Current out of VSS Pin
(Dual)...........................................................................................................100 mA
(Single) ..........................................................................................................50 mA
Maximum Current into VDD Pin
(Dual)...........................................................................................................100 mA
Maximum Current Sourced by the VOUT Pin...........................................................................................................20 mA
Maximum Current Sunk by the VOUT Pin................................................................................................................20 mA
Maximum Current Sourced/Sunk by the VREF(0) Pin (in Band Gap mode) .............................................................20 mA
Maximum Current Sunk by the VREFx Pin (when VREF is in Unbuffered mode) ....................................................175 µA
Maximum Current Sourced by the VREFx Pin...........................................................................................................20 µA
Maximum Current Sunk by the VREF Pin ...............................................................................................................125 µA
Maximum Input Current Sourced/Sunk by the SDA, SCL Pins ................................................................................2 mA
Maximum Output Current Sunk by the SDA Output Pin .........................................................................................25 mA
Total Power Dissipation(1) ....................................................................................................................................400 mW
ESD Protection on all Pins±6 kV (HBM)
±400V (MM)
±2 kV (CDM)
Latch-up (per JEDEC® JESD78A) at +125°C .................................................................................................... ±100 mA
Storage Temperature .............................................................................................................................. -65°C to +150°C
Ambient Temperature with Power Applied ............................................................................................. -55°C to +125°C
Soldering Temperature of Leads (10 seconds) ..................................................................................................... +300°C
Maximum Junction Temperature (TJ) .................................................................................................................... +150°C
† Notice: Stresses above those listed under “Maximum Ratings” may cause permanent damage to the device. This
is a stress rating only and functional operation of the device at those or any other conditions above those indicated
in the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended
periods may affect device reliability.
Note 1: Power dissipation is calculated as follows:
PDIS = VDD x {IDD – IOH} + {(VDD – VOH) x IOH} + (VOL x IOL)
2022 Microchip Technology Inc. and its subsidiaries
DS20006666B-page 5
MCP47CXDX1/2
DC CHARACTERISTICS
Standard Operating Conditions (unless otherwise specified):
Operating Temperature: -40°C TA +125°C (Extended)
All parameters apply across the specified operating ranges unless noted.
VDD = +2.7V to 5.5V, VREF = +1.000V to VDD, VSS = 0V, RL = 2 k from VOUT to GND, CL = 100 pF.
Typical specifications represent values for VDD = 5.5V, TA = +25°C.
Parameters
Supply Voltage
Sym.
VDD
Min.
Typ.
Max.
Units
Conditions
2.7
—
5.5
V
—
1.8
—
2.7
V
DAC operation (reduced analog
specifications) and serial interface
VDD Voltage
(rising) to Ensure Device
Power-on Reset
VPOR
—
—
1.75
V
RAM retention voltage: (VRAM) < VPOR,
VDD voltages greater than the VPOR limit
ensure that the device is out of Reset
VDD Voltage
(falling) to Ensure Device
Brown-out Reset
VBOR
VRAM
—
1.61
V
RAM retention voltage: (VRAM) < VBOR
VDD Rise Rate to Ensure
Power-on Reset
VDDRR
Power-on Reset to
Output-Driven Delay(1)
TPOR2OD
Note 3
V/ms —
—
—
130
µs
VDD rising, VDD > VPOR, single output
—
—
145
µs
VDD rising, VDD > VPOR, dual output
Note 1
This parameter is ensured by design.
Note 3
POR/BOR voltage trip point is not slope-dependent. Hysteresis implemented with time delay.
DS20006666B-page 6
2022 Microchip Technology Inc. and its subsidiaries
MCP47CXDX1/2
DC CHARACTERISTICS (CONTINUED)
Standard Operating Conditions (unless otherwise specified):
Operating Temperature: -40°C TA +125°C (Extended)
All parameters apply across the specified operating ranges unless noted.
VDD = +2.7V to 5.5V, VREF = +1.000V to VDD, VSS = 0V, RL = 2 k from VOUT to GND, CL = 100 pF.
Typical specifications represent values for VDD = 5.5V, TA = +25°C.
Parameters
Supply Current
LAT/HVC Pin
Write Current(1)
Power-Down
Current
Sym.
IDD
Min.
Typ.
Max. Units
µA
Conditions
Single 100 kHz
(2)
—
—
180
—
—
350
Serial interface active,
VRxB:VRxA = 10(4),
VOUT is unloaded,
1.7 MHz(2)
VREF = VDD = 5.5V,
3.4 MHz(2) Volatile DAC register = Mid-Scale
100 kHz(2)
—
—
360
—
—
550
—
—
260
—
—
410
400 kHz
—
—
420
1.7 MHz(2)
—
—
610
3.4 MHz(2)
400 kHz
Dual
—
—
140
—
—
240
Single Serial interface inactive, VRxB:VRxA = 10,
VOUT is unloaded, VREF = VDD = 5.5V,
Volatile DAC register = Mid-Scale
IDD(MTP_WR)
—
—
6.40
mA
—
Serial interface inactive (MTP write active),
VRxB:VRxA = 10 (valid for all modes),
VDD = 5.5V, LAT/HVC = VIHH,
write all ‘1’s to nonvolatile DAC0,
VOUT pins are unloaded
IDDP
—
0.5
2.4
µA
—
PDxB:PDxA = 01(5), VRxB:VRxA = 10,
VOUT not connected
Dual
Note 1
This parameter is ensured by design.
Note 2
This parameter is ensured by characterization.
Note 4
Supply current is independent of current through the resistor ladder in mode VRxB:VRxA = 10.
Note 5
The PDxB:PDxA = 01, 10 and 11 configurations must have the same current.
2022 Microchip Technology Inc. and its subsidiaries
DS20006666B-page 7
MCP47CXDX1/2
DC CHARACTERISTICS (CONTINUED)
Standard Operating Conditions (unless otherwise specified):
Operating Temperature: -40°C TA +125°C (Extended)
All parameters apply across the specified operating ranges unless noted.
VDD = +2.7V to 5.5V, VREF = +1.000V to VDD, VSS = 0V, RL = 2 k from VOUT to GND, CL = 100 pF.
Typical specifications represent values for VDD = 5.5V, TA = +25°C.
Parameters
Sym.
Min.
Typ.
Max.
Units
Resistor Ladder
Resistance(6)
RL
62.475
73.5
84.525
k
Resolution (# of resistors
and # of taps),
(see C.1 “Resolution”)
N
(10)
Nominal VOUT Match
VOUT Tempco(2)
(see C.19 “VOUT
Temperature Coefficient”)
VREF Pin Input Voltage
Range(1)
Conditions
VRxB:VRxA = 10,
VREF = VDD
256
Taps
8-bit No missing codes
1024
Taps
10-bit No missing codes
4096
Taps
12-bit No missing codes
|VOUT – VOUTMEAN|/
VOUTMEAN
—
0.026
0.300
VOUT/T
—
3
—
VREF
VSS
—
VDD
%
1.8V VDD 5.5V(2)
ppm/°C Code = Mid-Scale,
VRxB:VRxA = 00, 10 and 11
V
1.8V VDD 5.5V
Note 1
This parameter is ensured by design.
Note 2
This parameter is ensured by characterization.
Note 6
Resistance is defined as the resistance between the VREF pin (mode VRxB:VRxA = 10) and the VSS
pin. For dual channel devices (MCP47CXDX2), this is the effective resistance of each resistor ladder.
The resistance measurement is one of the two resistor ladders measured in parallel.
Note 10
Variation of one output voltage to mean output voltage for dual devices only.
DS20006666B-page 8
2022 Microchip Technology Inc. and its subsidiaries
MCP47CXDX1/2
DC CHARACTERISTICS (CONTINUED)
Standard Operating Conditions (unless otherwise specified):
Operating Temperature: -40°C TA +125°C (Extended)
All parameters apply across the specified operating ranges unless noted.
VDD = +2.7V to 5.5V, VREF = +1.000V to VDD, VSS = 0V, RL = 2 k from VOUT to GND, CL = 100 pF.
Typical specifications represent values for VDD = 5.5V, TA = +25°C.
Parameters
Zero-Scale Error
(Code = 000h)
Sym.
Min.
Typ.
Max.
Units
EZS
—
—
0.5
LSb
8-bit VRxB:VRxA = 10, G = 0,
VREF = VDD, no load
—
—
2
LSb
10-bit VRxB:VRxA = 10, G = 0,
VREF = VDD, no load
—
—
8
LSb
12-bit VRxB:VRxA = 10, G = 0,
VREF = VDD, no load
-9
±1.1
+9
mV
VRxB:VRxA = 10, Gx = 0, no load,
8-bit: Code = 4; 10-bit: Code = 16;
12-bit: Code = 64
—
±9
—
—
—
0.625
LSb
8-bit VRxB:VRxA = 10, G = 0,
VREF = VDD, no load
—
—
2.5
LSb
10-bit VRxB:VRxA = 10, G = 0,
VREF = VDD, no load
—
—
10
LSb
12-bit VRxB:VRxA = 10, G = 0,
VREF = VDD, no load
-0.6
±0.1
+0.6
% of
FSR
VRxB:VRxA = 10, G = 0,
8-bit Code = 252, VREF = VDD, no
load
-0.6
±0.1
+0.6
% of
FSR
VRxB:VRxA = 10, G = 0,
10-bit Code = 1008, VREF = VDD, no
load
-0.6
±0.1
+0.6
% of
FSR
VRxB:VRxA = 10, G = 0,
12-bit Code = 4032, VREF = VDD, no
load
—
-10
—
(see C.5 “Zero-Scale
Error (EZS)”)
Offset Error
(see C.7 “Offset Error
(EOS)”)
EOS
Offset Voltage Temperature VOSTC
Coefficient(2, 9)
Full-Scale Error
EFS
(see C.4 “Full-Scale
Error (EFS)”)
Gain Error(7)
EG
(see C.9 “Gain Error
(EG)”)
Gain Error Drift(2, 9)
(see C.10 “Gain Error
Drift (EGD)”)
G/°C
Conditions
µV/°C —
ppm/°C —
Note 2
This parameter is ensured by characterization.
Note 7
This gain error does not include the offset error.
Note 9
Code range dependent on resolution: 8-bit, codes 4 to 252; 10-bit, codes 16 to 1008; 12-bit, codes 64 to
4032.
2022 Microchip Technology Inc. and its subsidiaries
DS20006666B-page 9
MCP47CXDX1/2
DC CHARACTERISTICS (CONTINUED)
Standard Operating Conditions (unless otherwise specified):
Operating Temperature: -40°C TA +125°C (Extended)
All parameters apply across the specified operating ranges unless noted.
VDD = +2.7V to 5.5V, VREF = +1.000V to VDD, VSS = 0V,
RL = 2 k from VOUT to GND, CL = 100 pF.
Typical specifications represent values for VDD = 5.5V, TA = +25°C.
Parameters
Sym.
Min.
Typ.
Max.
Units
Total Unadjusted Error
ET
-1.375
—
0.625
LSb
8-bit
VRxB:VRxA = 10, G = 0,
VREF = VDD, no load
-5.5
—
2.5
LSb
10-bit
VRxB:VRxA = 10, G = 0,
VREF = VDD, no load
-22
—
10
LSb
12-bit
VRxB:VRxA = 10, G = 0,
VREF = VDD, no load
(2, 9)
(see C.6 “Total
Unadjusted Error
(ET)”)
See Section 2.0
“Typical
Performance
Curves”
Integral
Nonlinearity(9)
(see C.11 “Integral
Nonlinearity (INL)”)
INL
LSb
Conditions
VRxB:VRxA = 00
no load
VDD = 1.8-5.5V
VREF = VDD, G = 0
VRxB:VRxA = 01
no load
VDD = 1.8-5.5V, G = 0,
VREF = VBG = 1.2V (typ.)
VDD = 2.7-5.5 V, G = 1,
VREF = VBG = 1.2V (typ.)
12-bit
VRxB:VRxA = 10
VRxB:VRxA = 11
no load
VDD = 1.8-5.5 V
VREF = VDD, G = 0
VDD = 2.7-5.5 V
VREF = 0.5 X VDD, G = 1
-0.10
—
+0.10
LSb
8-bit
VRxB:VRxA = 10, G = 0,
VREF = VDD, no load
-0.25
—
+0.25
LSb
10-bit
VRxB:VRxA = 10, G = 0,
VREF = VDD, no load
-1
—
+1
LSb
12-bit
VRxB:VRxA = 10, G = 0,
VREF = VDD, no load
See Section 2.0
“Typical
Performance
Curves”
LSb
VRxB:VRxA = 00
no load
VDD = 1.8-5.5V
VREF = VDD, G = 0
VRxB:VRxA = 01
no load
VDD = 1.8-5.5V, G = 0,
VREF = VBG = 1.2V (typ.)
VDD = 2.7-5.5 V, G = 1,
VREF = VBG = 1.2V (typ.)
12-bit
VRxB:VRxA = 10
VRxB:VRxA = 11
no load
VDD = 1.8-5.5 V
VREF = VDD, G = 0
VDD = 2.7-5.5 V
VREF = 0.5 X VDD, G = 1
Note 2 This parameter is ensured by characterization.
Note 9 Code range dependent on resolution: 8-bit, codes 4 to 252; 10-bit, codes 16 to 1008; 12-bit, codes 64 to 4032.
DS20006666B-page 10
2022 Microchip Technology Inc. and its subsidiaries
MCP47CXDX1/2
DC CHARACTERISTICS (CONTINUED)
Standard Operating Conditions (unless otherwise specified):
Operating Temperature: -40°C TA +125°C (Extended)
All parameters apply across the specified operating ranges unless noted.
VDD = +2.7V to 5.5V, VREF = +1.000V to VDD, VSS = 0V,
RL = 2 k from VOUT to GND, CL = 100 pF.
Typical specifications represent values for VDD = 5.5V, TA = +25°C.
Parameters
Differential
Nonlinearity(9)
(see C.12
“Differential
Nonlinearity
(DNL)”)
Sym.
Min.
Typ.
Max.
Units
DNL
-0.1
—
+0.1
LSb
8-bit
VRxB:VRxA = 10, G = 0,
VREF = VDD, no load
-0.25
—
+0.25
LSb
10-bit
VRxB:VRxA = 10, G = 0,
VREF = VDD, no load
-1.0
—
+1.0
LSb
12-bit
VRxB:VRxA = 10, G = 0,
VREF = VDD, no load
See Section 2.0
“Typical
Performance
Curves”
LSb
Conditions
VRxB:VRxA = 00
no load
VDD = 1.8-5.5V
VREF = VDD, G = 0
VRxB:VRxA = 01
no load
VDD = 1.8-5.5V, G = 0,
VREF = VBG = 1.2V (typ.)
VDD = 2.7-5.5 V, G = 1,
VREF = VBG = 1.2V (typ.)
12-bit
VRxB:VRxA = 10
VRxB:VRxA = 11
no load
VDD = 1.8-5.5 V
VREF = VDD, G = 0
VDD = 2.7-5.5 V
VREF = 0.5 X VDD, G = 1
Note 9 Code range dependent on resolution: 8-bit, codes 4 to 252; 10-bit, codes 16 to 1008; 12-bit, codes 64 to 4032.
2022 Microchip Technology Inc. and its subsidiaries
DS20006666B-page 11
MCP47CXDX1/2
DC CHARACTERISTICS (CONTINUED)
Standard Operating Conditions (unless otherwise specified):
Operating Temperature: -40°C TA +125°C (Extended)
All parameters apply across the specified operating ranges unless noted.
VDD = +2.7V to 5.5V, VREF = +1.000V to VDD, VSS = 0V, RL = 2 k from VOUT to GND, CL = 100 pF.
Typical specifications represent values for VDD = 5.5V, TA = +25°C.
Parameters
-3 dB Bandwidth
(see C.16 “-3 dB
Bandwidth”)
Sym.
Min.
Typ.
Max.
Units
Conditions
BW
—
270
—
kHz
VREF = 3.00V ± 2V, VRxB:VRxA = 10, Gx = 0
—
170
—
—
76
—
VREF = 3.50V ± 1.5V, VRxB:VRxA = 10,
Gx = 1
Output Amplifier (Op Amp)
Phase Margin(1)
PM
Slew Rate
SR
—
0.7
—
Load Regulation
—
—
147
—
—
300
—
Short-Circuit Current
Settling Time(8)
ISC_OA
°C
V/µs
RL = ∞
RL = 2 k
µV/mA 1 mA I mA
VDD = 5.5V,
µV/mA -6 mA I-1 mA DAC code = Mid-Scale
6
10
14
mA
Short to VSS
DAC code = Full Scale
6
10
14
mA
Short to VDD
DAC code = Zero Scale
tSETTLING
—
4
—
µs
RL = 2 k
1.8V VDD 5.5V
Internal Band Gap
Band Gap Voltage
VBG
1.180
1.214
1.260
V
Short-Circuit Current
ISC_BG
6
10
14
mA
Short to VSS
6
10
14
mA
Short to VDD
Band Gap Voltage
Temperature
Coefficient
VBGTC
—
18
—
ppm/°C 1.8V VDD 5.5V
Band Gap mode,
VREF Pin Load
Regulation
IBG
—
52
—
µV/mA 1 mA I6 mA
—
374
—
µV/mA -6 mA I-1 mA
VDD = 5.5V
Note 1
This parameter is ensured by design.
Note 8
Within 1/2 LSb of the final value, when code changes from 1/4 to 3/4 of FSR. (Example: 400h to C00h in 12bit device.)
DS20006666B-page 12
2022 Microchip Technology Inc. and its subsidiaries
MCP47CXDX1/2
DC CHARACTERISTICS (CONTINUED)
Standard Operating Conditions (unless otherwise specified):
Operating Temperature: -40°C TA +125°C (Extended)
All parameters apply across the specified operating ranges unless noted.
VDD = +2.7V to 5.5V, VREF = +1.000V to VDD, VSS = 0V, RL = 2 k from VOUT to GND, CL = 100 pF.
Typical specifications represent values for VDD = 5.5V, TA = +25°C.
Parameters
Sym.
Min.
Typ.
Max.
Units
Conditions
Input Range(1)
VREF
VSS
—
VDD
V
VRxB:VRxA = 10
(Unbuffered mode)
Input Capacitance
CREF
—
29
—
pF
VRxB:VRxA = 10
(Unbuffered mode)
k
2.7V VDD 5.5V,
VRxB:VRxA = 10, VREF VDD
External Reference (VREF)
Input Impedance
RL
See
Resistor Ladder Resistance(6)
Current through VREF(1)
IVREF
—
—
176.07
µA
Mathematically from RVREF(min)
spec (at 5.5V)
Total Harmonic
Distortion(1)
THD
—
-76
—
dB
VREF = 2.048V ± 0.1V,
VRxB:VRxA = 10, Gx = 0,
Frequency = 1 kHz
Major Code Transition Glitch
(see C.14 “Major Code
Transition Glitch”)
—
—
60
—
nV-s
1 LSb change around major carry
(7FFh to 800h)
Digital Feedthrough (see C.15
“Digital Feedthrough”)
—
—
VPOR,
VOUT driven to VOUT disabled
Power-Down
Output Disable Time Delay
TPDD
—
0.4
—
µs
PDxB:PDxA = 00 11, 10 or 01 started from
the rising edge of the ACK bit;
VOUT = VOUT – 10 mV,
VOUT not connected
Power-Down
Output Enable Time Delay
TPDE
—
7
—
µs
PDxB:PDxA = 11, 10, or 01 00 started from
the rising edge of the ACK bit;
Volatile DAC register = FFFh, VOUT = 10 mV,
VOUT not connected
Note 10
Not tested. This parameter is ensured by design.
DS20006666B-page 18
2022 Microchip Technology Inc. and its subsidiaries
MCP47CXDX1/2
HVC
VIH
VIHH
94
VIH
VIH
SCL
91
90
92
93
111
SDA
VIL
Start
Condition
Note 1:
Stop
Condition
The HVC pin must be at VIHH until the MTP write cycle is complete.
FIGURE 1-5:
I2C Bus Start/Stop Bits and HVC Timing Waveforms.
2022 Microchip Technology Inc. and its subsidiaries
DS20006666B-page 19
MCP47CXDX1/2
TABLE 1-4:
I2C BUS START/STOP BITS AND LAT REQUIREMENTS
Standard Operating Conditions (unless otherwise specified):
Operating Temperature: -40C TA +125C (Extended).
The operating voltage range is described in DC Characteristics.
I2C AC Characteristics
Param.
No.
Sym.
—
FSCL
90
91
92
93
94
Note 1
TSU:STA
THD:STA
TSU:STO
THD:STO
THVCSU
Characteristic
SCL Pin Frequency
Min.
Max.
Units
Conditions
Standard mode
0
100
kHz
Cb = 400 pF, 1.8V-5.5V(1)
Fast mode
0
400
kHz
Cb = 400 pF, 2.7V-5.5V
High Speed 1.7
0
1.7
MHz
Cb = 400 pF, 4.5V-5.5V(1)
High Speed 3.4
0
3.4
MHz
Cb = 100 pF, 4.5V-5.5V(1)
Start Condition
Setup Time
(only relevant for
Repeated Start condition)
100 kHz mode
4700
—
ns
Note 1
400 kHz mode
600
—
ns
—
1.7 MHz mode
160
—
ns
Note 1
3.4 MHz mode
160
—
ns
Start Condition
Hold Time
(after this period, the first
clock pulse is generated)
100 kHz mode
4000
—
ns
Note 1
400 kHz mode
600
—
ns
—
1.7 MHz mode
160
—
ns
Note 1
3.4 MHz mode
160
—
ns
Stop Condition
Setup Time
100 kHz mode
4000
—
ns
Note 1
Stop Condition
Hold Time
400 kHz mode
600
—
ns
—
1.7 MHz mode
160
—
ns
Note 1
3.4 MHz mode
160
—
ns
100 kHz mode
4000
—
ns
Note 1
400 kHz mode
600
—
ns
—
1.7 MHz mode
160
—
ns
Note 1
3.4 MHz mode
160
—
ns
0
—
µs
HVC High to Start Condition
(setup time)
Not tested, specification
ensured by Host
Not tested. This parameter is ensured by characterization.
DS20006666B-page 20
2022 Microchip Technology Inc. and its subsidiaries
MCP47CXDX1/2
103
102
100
101
SCL
90
106
91
92
107
SDA In
110
109
109
SDA Out
I2C Bus Data Timing Waveforms.
FIGURE 1-6:
TABLE 1-5:
I2C BUS REQUIREMENTS (CLIENT MODE)
Standard Operating Conditions (unless otherwise specified):
Operating Temperature: -40C TA +125C (Extended).
The operating voltage range is described in DC Characteristics.
I2C AC Characteristics
Param.
No.
Sym.
100
THIGH
101
102A(10)
102B(10)
103A(10)
TLOW
TRSCL
TRSDA
TFSCL
Characteristic
Clock High Time
Clock Low Time
SCL Rise Time
SDA Rise Time
SCL Fall Time
Min.
Max.
Units
100 kHz mode
4000
—
ns
1.8V-5.5V(1)
400 kHz mode
600
—
ns
2.7V-5.5V
1.7 MHz mode
120
—
ns
4.5V-5.5V(1)
3.4 MHz mode
60
—
ns
4.5V-5.5V(1)
100 kHz mode
4700
—
ns
1.8V-5.5V(1)
400 kHz mode
1300
—
ns
2.7V-5.5V
1.7 MHz mode
320
—
ns
4.5V-5.5V(1)
3.4 MHz mode
160
—
ns
4.5V-5.5V(1)
100 kHz mode
—
1000
ns
400 kHz mode
20 + 0.1Cb(4)
300
ns
1.7 MHz mode
20
80
ns
Cb is specified to be from
10 to 400 pF (100 pF
maximum for 3.4 MHz mode)
1.7 MHz mode
20
160
ns
3.4 MHz mode
10
40
ns
3.4 MHz mode
10
80
ns
After a Repeated Start
condition or an
Acknowledge bit
100 kHz mode
—
1000
ns
400 kHz mode
20 + 0.1Cb
300
ns
1.7 MHz mode
20
160
ns
Cb is specified to be from
10 to 400 pF (100 pF
maximum for 3.4 MHz mode)
3.4 MHz mode
10
80
ns
100 kHz mode
—
300
ns
400 kHz mode
20 + 0.1Cb
300
ns
1.7 MHz mode
20
80
ns
3.4 MHz mode
10
40
ns
Note 1
Not tested. This parameter is ensured by characterization.
Note 4
Use Cb in pF for the calculations.
Note 10
Not tested. This parameter is ensured by design.
2022 Microchip Technology Inc. and its subsidiaries
Conditions
After a Repeated Start
condition or an
Acknowledge bit
Cb is specified to be from
10 to 400 pF (100 pF
maximum for 3.4 MHz
mode)(4)
DS20006666B-page 21
MCP47CXDX1/2
TABLE 1-5:
I2C BUS REQUIREMENTS (CLIENT MODE) (CONTINUED)
Standard Operating Conditions (unless otherwise specified):
Operating Temperature: -40C TA +125C (Extended).
The operating voltage range is described in DC Characteristics.
I2C AC Characteristics
Param.
No.
Sym.
103B(10)
TFSDA
106
107
109
110
111
Characteristic
SDA Fall Time
THD:DAT Data Input Hold
Time
TSU:DAT Data Input Setup
Time
TAA
TBUF
TSP
Output Valid from
Clock
Bus Free Time
Input Filter Spike
Suppression (SDA
and SCL)
Min.
Max.
Units
Conditions
100 kHz mode
—
300
ns
400 kHz mode
20 + 0.1Cb
300
ns
1.7 MHz mode
20
160
ns
3.4 MHz mode
10
80
ns
100 kHz mode
0
—
ns
1.8V-5.5V(1, 5)
400 kHz mode
0
—
ns
2.7V-5.5V(5)
1.7 MHz mode
0
—
ns
4.5V-5.5V(1, 5)
3.4 MHz mode
0
—
ns
4.5V-5.5V(1, 5)
Cb is specified to be from
10 to 400 pF (100 pF
maximum for 3.4 MHz
mode)(4)
100 kHz mode
250
—
ns
Notes 1, 6
400 kHz mode
100
—
ns
Note 6
1.7 MHz mode
10
—
ns
Notes 1, 6
3.4 MHz mode
10
—
ns
Notes 1, 6
100 kHz mode
—
3450
ns
Notes 1, 5, 7, 9
400 kHz mode
—
900
ns
Notes 5, 7, 9
1.7 MHz mode
—
310
ns
Cb = 400 pF(1, 9)
3.4 MHz mode
—
150
ns
Cb = 100 pF(1, 9)
Time the bus must be free
before a new transmission
can start(1)
100 kHz mode
4700
—
ns
400 kHz mode
1300
—
ns
1.7 MHz mode
N.A.
—
ns
3.4 MHz mode
N.A.
—
ns
100 kHz mode
—
50
ns
NXP Spec states N.A.(1)
400 kHz mode
—
50
ns
NXP Spec states N.A.
1.7 MHz mode
—
10
ns
NXP Spec states N.A.(1)
3.4 MHz mode
—
10
ns
NXP Spec states N.A.(1)
Note 1
Not tested. This parameter is ensured by characterization.
Note 4
Use Cb in pF for the calculations.
Note 5
A Host transmitter must provide a delay to ensure that the difference between SDA and SCL fall times does
not unintentionally create a Start or Stop condition.
Note 6
A Fast mode (400 kHz) I2C bus device can be used in a Standard mode (100 kHz) I2C bus system, but the
requirement, tSU:DAT 250 ns, must then be met. This will automatically be the case if the device does not
stretch the Low period of the SCL signal. If such a device does stretch the Low period of the SCL signal, it
must output the next data bit to the SDA line, TR max.+ tSU:DAT = 1000 + 250 = 1250 ns (according to the
Standard mode I2C bus specification) before the SCL line is released.
Note 7
As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region
(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions.
Note 8
Ensured by the TAA 3.4 MHz specification test.
Note 9
The specification is not part of the I2C specification. TAA = THD:DAT + TFSDA (or TRSDA).
Note 10 Not tested. This parameter is ensured by design.
DS20006666B-page 22
2022 Microchip Technology Inc. and its subsidiaries
MCP47CXDX1/2
Timing Notes:
1.
2.
3.
Not tested. This parameter is ensured by characterization.
Within 1/2 LSb of final value when code changes from 1/4 to 3/4 of FSR.
The transition of the LAT signal, between 10 ns before the rising edge (Spec 94) and 250 ns after the rising edge
(Spec 95) of the SCL signal, is indeterminate whether the change in VOUT is delayed or not.
4. Use Cb in pF for the calculations.
5. A Host transmitter must provide a delay to ensure that the difference between SDA and SCL fall times does not
unintentionally create a Start or Stop condition.
6. A Fast mode (400 kHz) I2C bus device can be used in a Standard mode (100 kHz) I2C bus system, but the
requirement, tSU:DAT 250 ns, must then be met. This will automatically be the case if the device does not stretch
the Low period of the SCL signal. If such a device does stretch the Low period of the SCL signal, it must output
the next data bit to the SDA line, TR max.+ tSU:DAT = 1000 + 250 = 1250 ns (according to the Standard mode I2C
bus specification) before the SCL line is released.
7. As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region
(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions.
8. Ensured by the TAA 3.4 MHz specification test.
9. The specification is not part of the I2C specification. TAA = THD:DAT + TFSDA (or TRSDA).
10. Not tested. This parameter is ensured by design.
2022 Microchip Technology Inc. and its subsidiaries
DS20006666B-page 23
MCP47CXDX1/2
TEMPERATURE SPECIFICATIONS
Electrical Specifications: Unless otherwise indicated, VDD = +2.7V to +5.5V, VSS = GND.
Parameters
Sym.
Min.
Typ.
Max.
Units
Specified Temperature Range
TA
-40
—
+125
°C
Operating Temperature Range
TA
-40
—
+125
°C
Storage Temperature Range
TA
-65
—
+150
°C
Thermal Resistance, 10L-MSOP
JA
—
206
—
°C/W
Thermal Resistance, 10L-DFN (3 x 3)
JA
—
91
—
°C/W
Thermal Resistance, 16L-QFN (3 x 3)
JA
—
58
—
°C/W
Conditions
Temperature Ranges
Thermal Package Resistances
DS20006666B-page 24
2022 Microchip Technology Inc. and its subsidiaries
MCP47CXDX1/2
2.0
Note:
2.1
Note:
TYPICAL PERFORMANCE CURVES
The graphs and tables provided following this note are a statistical summary based on a limited number of
samples and are provided for informational purposes only. The performance characteristics listed herein
are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified
operating range (e.g., outside specified power supply range), and therefore, outside the warranted range.
Electrical Data
Unless otherwise indicated, TA = +25°C, VDD = 5.5V.
FIGURE 2-1:
Average Device Supply
Current vs. FSCL, Voltage and Temperature –
Active Interface, VRxB:VRxA = 00 (VDD Mode).
FIGURE 2-4:
Average Device Supply
Current vs. Voltage and Temperature – Inactive
Interface, VRxB:VRxA = 00 (VDD Mode).
FIGURE 2-2:
Average Device Supply
Current vs. FSCL, Voltage and Temperature –
Active Interface, VRxB:VRxA = 01 (Band Gap
Mode).
FIGURE 2-5:
Average Device Supply
Current vs. Voltage and Temperature – Inactive
Interface, VRxB:VRxA = 01 (Band Gap Mode).
FIGURE 2-3:
Average Device Supply
Current vs. FSCL, Voltage and Temperature –
Active Interface, VRxB:VRxA = 10 (VREF
Unbuffered Mode).
FIGURE 2-6:
Average Device Supply
Current vs. Voltage and Temperature – Inactive
Interface, VRxB:VRxA = 10 (VREF Unbuffered
Mode).
2022 Microchip Technology Inc. and its subsidiaries
DS20006666B-page 25
MCP47CXDX1/2
Note:
Unless otherwise indicated, TA = +25°C, VDD = 5.5V.
FIGURE 2-7:
Average Device Supply
Current vs. FSCL Frequency, Voltage and
Temperature – Active Interface,
VRxB:VRxA = 11 (VREF Buffered Mode).
FIGURE 2-9:
Average Device Supply
Current vs. Voltage and Temperature – Inactive
Interface, VRxB:VRxA = 11 (VREF Buffered
Mode).
FIGURE 2-8:
Average Device Supply
Active Current (IDDA) (at 5.5V and
FSCL = 3.4 MHz) vs. Temperature and DAC
Reference Voltage Mode.
DS20006666B-page 26
2022 Microchip Technology Inc. and its subsidiaries
MCP47CXDX1/2
2.2
2.2.1
Note:
Linearity Data
TOTAL UNADJUSTED ERROR (TUE) – VDD MODE (VRXB:VRXA = 00)
MCP47CXD22 (12-BIT), CODE 64-4032
Unless otherwise indicated: TA = +25°C, VDD = 5.5V.
FIGURE 2-10:
TUE (VOUT) vs. DAC Code
and Temperature, VREF = VDD = 5.5V, G = 1x.
FIGURE 2-12:
TUE (VOUT) vs. DAC Code
and Temperature, VREF = VDD = 1.8V, G = 1x.
FIGURE 2-11:
TUE (VOUT) vs. DAC Code
and Temperature, VREF = VDD = 2.7V, G = 1x.
FIGURE 2-13:
TUE (VOUT) vs. DAC Code,
Temperature = +25°C.
2022 Microchip Technology Inc. and its subsidiaries
DS20006666B-page 27
MCP47CXDX1/2
2.2.2
Note:
TOTAL UNADJUSTED ERROR (TUE) – INTERNAL BAND GAP MODE (VRXB:VRXA = 01),
MCP47CXD22 (12-BIT), CODE 64-4032
Unless otherwise indicated: TA = +25°C, VDD = 5.5V.
FIGURE 2-14:
TUE (VOUT) vs. DAC Code
and Temperature, VDD = 5.5V, VREF = 1.2V,
G = 1x.
FIGURE 2-17:
TUE (VOUT) vs. DAC Code
and Temperature, VDD = 5.5V, VREF = 1.2V,
G = 2x.
FIGURE 2-15:
TUE (VOUT) vs. DAC Code
and Temperature, VDD = 2.7V, VREF = 1.2V,
G = 1x.
FIGURE 2-18:
TUE (VOUT) vs. DAC Code
and Temperature, VDD = 2.7V, VREF = 1.2V,
G = 2x.
FIGURE 2-16:
TUE (VOUT) vs. DAC Code
and Temperature, VDD = 1.8V, VREF = 1.2V,
G = 1x.
FIGURE 2-19:
TUE (VOUT) vs. DAC Code,
Temperature = +25°C.
DS20006666B-page 28
2022 Microchip Technology Inc. and its subsidiaries
MCP47CXDX1/2
2.2.3
Note:
TOTAL UNADJUSTED ERROR (TUE) – EXTERNAL UNBUFFERED VREF MODE
(VRXB:VRXA = 10), MCP47CXD22 (12-BIT), CODE 64-4032
Unless otherwise indicated: TA = +25°C, VDD = 5.5V.
FIGURE 2-20:
TUE (VOUT) vs. DAC Code
and Temperature, VREF =VDD = 5.5V, G = 1x.
FIGURE 2-23:
TUE (VOUT) vs. DAC Code
and Temperature, VDD = 5.5V, VREF = 2.75V,
G = 2x.
FIGURE 2-21:
TUE (VOUT) vs. DAC Code
and Temperature, VREF = VDD = 2.7V, G = 1x.
FIGURE 2-24:
TUE (VOUT) vs. DAC Code
and Temperature, VDD = 2.7V, VREF = 1.35V,
G = 2x.
FIGURE 2-22:
TUE (VOUT) vs. DAC Code
and Temperature, VREF = VDD = 1.8V, G = 1x.
FIGURE 2-25:
TUE (VOUT) vs. DAC Code,
Temperature = +25°C.
2022 Microchip Technology Inc. and its subsidiaries
DS20006666B-page 29
MCP47CXDX1/2
2.2.4
Note:
TOTAL UNADJUSTED ERROR (TUE) – EXTERNAL BUFFERED VREF MODE (VRXB:VRXA =
11), MCP47CXD22 (12-BIT), CODE 64-4032
Unless otherwise indicated: TA = +25°C, VDD = 5.5V.
FIGURE 2-26:
TUE (VOUT) vs. DAC Code
and Temperature, VREF = VDD = 5.5V, G = 1x.
FIGURE 2-29:
TUE (VOUT) vs. DAC Code
and Temperature, VREF = 2.75V, VDD = 5.5V,
G = 2x.
FIGURE 2-27:
TUE (VOUT) vs. DAC Code
and Temperature, VREF = VDD = 2.7V, G = 1x.
FIGURE 2-30:
TUE (VOUT) vs. DAC Code
and Temperature, VREF = 1.35V, VDD = 2.7V,
G = 2x.
FIGURE 2-28:
TUE (VOUT) vs. DAC Code
and Temperature, VREF = VDD = 2.7V, G = 1x.
FIGURE 2-31:
TUE (VOUT) vs. DAC Code,
Temperature = +25°C.
DS20006666B-page 30
2022 Microchip Technology Inc. and its subsidiaries
MCP47CXDX1/2
2.2.5
Note:
INTEGRAL NONLINEARITY (INL) – VDD MODE (VRXB:VRXA = 00)
MCP47CXD22 (12-BIT), CODE 64-4032
Unless otherwise indicated: TA = +25°C, VDD = 5.5V.
FIGURE 2-32:
INL Error vs. DAC Code
and Temperature, VREF = VDD = 5.5V, G = 1x.
FIGURE 2-34:
INL Error vs. DAC Code
and Temperature, VREF = VDD = 1.8V, G = 1x.
FIGURE 2-33:
INL Error vs. DAC Code
and Temperature, VREF = VDD = 2.7V, G = 1x.
FIGURE 2-35:
INL Error vs. DAC Code,
Temperature = +25°C.
2022 Microchip Technology Inc. and its subsidiaries
DS20006666B-page 31
MCP47CXDX1/2
2.2.6
Note:
INTEGRAL NONLINEARITY (INL) – INTERNAL BAND GAP MODE (VRXB:VRXA = 01),
MCP47CXD22 (12-BIT), CODE 64-4032
Unless otherwise indicated: TA = +25°C, VDD = 5.5V.
FIGURE 2-36:
INL Error vs. DAC Code
and Temperature, VDD = 5.5V, VREF = 1.2V,
G = 1x.
FIGURE 2-39:
INL Error vs. DAC Code
and Temperature, VDD = 5.5V, VREF = 1.2V,
G = 2x.
FIGURE 2-37:
INL Error vs. DAC Code
and Temperature, VDD = 2.7V, VREF = 1.2V,
G = 1x.
FIGURE 2-40:
INL Error vs. DAC Code
and Temperature, VDD = 2.7V, VREF = 1.2V,
G = 2x.
FIGURE 2-38:
INL Error vs. DAC Code
and Temperature, VDD = 1.8V, VREF = 1.2V,
G = 1x.
FIGURE 2-41:
INL Error vs. DAC Code,
Temperature = +25°C.
DS20006666B-page 32
2022 Microchip Technology Inc. and its subsidiaries
MCP47CXDX1/2
2.2.7
Note:
INTEGRAL NONLINEARITY (INL) – EXTERNAL UNBUFFERED VREF MODE
(VRXB:VRXA = 10), MCP47CXD22 (12-BIT), CODE 64-4032
Unless otherwise indicated: TA = +25°C, VDD = 5.5V.
FIGURE 2-42:
INL Error vs. DAC Code
and Temperature, VDD = VREF = 5.5V, G = 1x.
FIGURE 2-45:
INL Error vs. DAC Code and
Temperature, VDD = 5.5V, VREF = 2.75V, G = 2x.
FIGURE 2-43:
INL Error vs. DAC Code and
Temperature, VDD = VREF = 2.7V, G = 1x.
FIGURE 2-46:
INL Error vs. DAC Code and
Temperature, VDD = 2.7V, VREF = 1.35V, G = 2x.
FIGURE 2-44:
INL Error vs. DAC Code
and Temperature, VDD = VREF = 1.8V, G = 1x.
FIGURE 2-47:
INL Error vs. DAC Code,
Temperature = +25°C.
2022 Microchip Technology Inc. and its subsidiaries
DS20006666B-page 33
MCP47CXDX1/2
2.2.8
Note:
INTEGRAL NONLINEARITY (INL) – EXTERNAL BUFFERED VREF MODE
(VRXB:VRXA = 11), MCP47CXD22 (12-BIT), CODE 64-4032
Unless otherwise indicated: TA = +25°C, VDD = 5.5V.
FIGURE 2-48:
INL Error vs. DAC Code
and Temperature, VDD = VREF = 5.5V, G = 1x.
FIGURE 2-51:
INL Error vs. DAC Code
and Temperature, VDD = 5.5V, VREF = 2.75V,
G = 2x.
FIGURE 2-49:
INL Error vs. DAC Code and
Temperature, VDD = VREF = 2.7V, G = 1x.
FIGURE 2-52:
INL Error vs. DAC Code and
Temperature, VDD = 2.7V, VREF = 1.35V, G = 2x.
FIGURE 2-50:
INL Error vs. DAC Code and
Temperature, VDD = VREF = 1.8V, G = 1x.
FIGURE 2-53:
INL Error vs. DAC Code,
Temperature = +25°C.
DS20006666B-page 34
2022 Microchip Technology Inc. and its subsidiaries
MCP47CXDX1/2
2.2.9
Note:
DIFFERENTIAL NONLINEARITY (DNL) – VDD MODE (VRXB:VRXA = 00)
MCP47CXD22 (12-BIT), CODE 64-4032
Unless otherwise indicated: TA = +25°C, VDD = 5.5V.
FIGURE 2-54:
DNL Error vs. DAC Code
and Temperature, VREF = VDD = 5.5V, G = 1x.
FIGURE 2-56:
DNL Error vs. DAC Code
and Temperature, VREF = VDD = 1.8V, G = 1x.
FIGURE 2-55:
DNL Error vs. DAC Code
and Temperature, VREF = VDD = 2.7V, G = 1x.
FIGURE 2-57:
DNL Error vs. DAC Code,
Temperature = +25°C.
2022 Microchip Technology Inc. and its subsidiaries
DS20006666B-page 35
MCP47CXDX1/2
2.2.10
Note:
DIFFERENTIAL NONLINEARITY (DNL) – INTERNAL BAND GAP MODE (VRXB:VRXA = 01),
MCP47CXD22 (12-BIT), CODE 64-4032
Unless otherwise indicated: TA = +25°C, VDD = 5.5V.
FIGURE 2-58:
DNL Error vs. DAC Code
and Temperature, VDD = 5.5V, VREF = 1.2V,
G = 1x.
FIGURE 2-61:
DNL Error vs. DAC Code
and Temperature, VDD = 5.5V, VREF = 1.2V,
G = 2x.
FIGURE 2-59:
DNL Error vs. DAC Code
and Temperature, VDD = 2.7V, VREF = 1.2V,
G = 1x.
FIGURE 2-62:
DNL Error vs. DAC Code
and Temperature, VDD = 2.7V, VREF = 1.2V,
G = 2x.
FIGURE 2-60:
DNL Error vs. DAC Code
and Temperature, VDD = 1.8V, VREF = 1.2V,
G = 1x.
FIGURE 2-63:
DNL Error vs. DAC Code,
Temperature = +25°C.
DS20006666B-page 36
2022 Microchip Technology Inc. and its subsidiaries
MCP47CXDX1/2
2.2.11
Note:
DIFFERENTIAL NONLINEARITY (DNL) – EXTERNAL UNBUFFERED VREF MODE
(VRXB:VRXA = 10), MCP47CXD22 (12-BIT), CODE 64-4032
Unless otherwise indicated: TA = +25°C, VDD = 5.5V.
FIGURE 2-64:
DNL Error vs. DAC Code
and Temperature, VDD = VREF = 5.5V, G = 1x.
FIGURE 2-67:
DNL Error vs. DAC Code
and Temperature, VDD = 5.5V, VREF = 2.75V,
G = 2x.
FIGURE 2-65:
DNL Error vs. DAC Code
and Temperature, VDD = VREF = 2.7V, G = 1x.
FIGURE 2-68:
DNL Error vs. DAC Code
and Temperature, VDD = 2.7V, VREF = 1.35V,
G = 2x.
FIGURE 2-66:
DNL Error vs. DAC Code
and Temperature, VDD = VREF = 2.7V, G = 1x.
FIGURE 2-69:
DNL Error vs. DAC Code,
Temperature = +25°C.
2022 Microchip Technology Inc. and its subsidiaries
DS20006666B-page 37
MCP47CXDX1/2
2.2.12
Note:
DIFFERENTIAL NONLINEARITY (DNL) – EXTERNAL BUFFERED VREF MODE
(VRXB:VRXA = 11), MCP47CXD22 (12-BIT), CODE 64-4032
Unless otherwise indicated: TA = +25°C, VDD = 5.5V.
FIGURE 2-70:
DNL Error vs. DAC Code
and Temperature, VDD = VREF = 5.5V, G = 1x.
FIGURE 2-73:
DNL Error vs. DAC Code
and Temperature, VDD = 5.5V, VREF = 2.75V,
G = 1x.
FIGURE 2-71:
DNL Error vs. DAC Code
and Temperature, VDD = VREF = 2.7V, G = 1x.
FIGURE 2-74:
DNL Error vs. DAC Code
and Temperature, VDD = 2.7V, VREF = 1.35V,
G = 2x.
FIGURE 2-72:
DNL Error vs. DAC Code
and Temperature, VREF = VDD = 1.8V, G = 1x.
FIGURE 2-75:
DNL Error vs. DAC Code,
Temperature = +25°C.
DS20006666B-page 38
2022 Microchip Technology Inc. and its subsidiaries
MCP47CXDX1/2
3.0
PIN DESCRIPTIONS
Overviews of the pin functions are provided in
Section 3.1 “Positive Power Supply Input (VDD)”
through Section 3.5 “No Connect (NC)”.
TABLE 3-1:
The descriptions of the pins for the single DAC output
device are listed in Table 3-1 and descriptions for the
dual DAC output device are listed in Table 3-2.
MCP47CXDX1 (SINGLE DAC) PIN FUNCTION TABLE
Pin
MSOP
10L
DFN
10L
QFN
16L
Symbol
I/O
Buffer
Type
1
1
16
VDD
—
P
2
2
1
A0
I
ST
3
3
2
VREF
A
Analog
4
4
3
VOUT
A
Analog
5
5
4, 5, 6, 7,
8,14,15
NC
—
—
Not Internally Connected
6
6
9
LAT/HVC
I
ST
DAC Wiper Register Latch/High-Voltage Command Pin.
The Latch pin allows the value in the Volatile DAC registers
(Wiper and Configuration bits) to be transferred to the DAC
output (VOUT).
High-voltage commands allow the user MTP Configuration
bits to be written.
7
7
10
VSS
—
P
8
8
11
A1
I
ST
I2C Client Address Bit 1 Pin
9
9
12
SCL
I
ST
I2C Serial Clock Pin
10
10
13
SDA
I/O
ST
I2C Serial Data Pin
—
—
17
EP
—
P
Note 1:
Description
Supply Voltage Pin
I2C Client Address Bit 0 Pin
Voltage Reference Input/Output Pin
Buffered Analog Voltage Output Pin
Ground Reference Pin for all circuitries on the device
Exposed Thermal Pad Pin, must be connected to VSS
A = Analog, I = Input, ST = Schmitt Trigger, O = Output, I/O = Input/Output, P = Power
2022 Microchip Technology Inc. and its subsidiaries
DS20006666B-page 39
MCP47CXDX1/2
TABLE 3-2:
MCP47CXDX2 (DUAL DAC) PIN FUNCTION TABLE
Pin
Buffer
Type
DFN
10L
QFN
16L
Symbol
I/O
1
1
16
VDD
—
P
2
2
1
A0
I
ST
MSOP
10L
Description
Supply Voltage Pin
I2C Client Address Bit 0 Pin
3
3
—
VREF
A
Analog
Voltage Reference Input/Output Pin
—
—
2
VREF0
A
Analog
Voltage Reference Input/Output Pin for DAC0
—
—
4
VREF1
A
Analog
Voltage Reference Input/Output Pin for DAC1
4
4
3
VOUT0
A
Analog
Buffered Analog Voltage Output 0 Pin
Buffered Analog Voltage Output 1 Pin
5
5
5
VOUT1
A
Analog
—
—
6, 7,
14, 15
NC
—
—
Not Internally Connected
6
6
—
LAT/HVC
I
ST
DAC Wiper Register Latch/High-Voltage Command Pin.
The Latch pin allows the value in the Volatile DAC registers
(Wiper and Configuration bits) to be transferred to the DAC
output (VOUT).
High-voltage commands allow the user MTP Configuration
bits to be written.
—
—
9
LAT0/HVC
I
ST
DAC0 Wiper Register Latch/High-Voltage Command Pin.
The Latch pin allows the value in the Volatile DAC0 registers
(Wiper and Configuration bits) to be transferred to the DAC0
output (VOUT0).
High-voltage commands allow the user MTP Configuration
bits to be written.
—
—
8
LAT1
I
ST
DAC1 Wiper Register Latch Pin.
The Latch pin allows the value in the Volatile DAC1 registers
(Wiper and Configuration bits) to be transferred to the DAC1
output (VOUT1).
7
7
10
VSS
—
P
8
8
11
A1
I
ST
I2C Client Address Bit 1 Pin
9
9
12
SCL
I
ST
I2C Serial Clock Pin
10
10
13
SDA
I/O
ST
I2C Serial Data Pin
Note 1:
Ground Reference Pin for all circuitries on the device
A = Analog, I = Input, ST = Schmitt Trigger, O = Output, I/O = Input/Output, P = Power
DS20006666B-page 40
2022 Microchip Technology Inc. and its subsidiaries
MCP47CXDX1/2
3.1
Positive Power Supply Input (VDD)
VDD is the positive supply voltage input pin. The input
supply voltage is relative to VSS.
The power supply at the VDD pin must be as clean as
possible for good DAC performance. It is recommended to use an appropriate bypass capacitor of
about 0.1 µF (ceramic) to ground as close as possible
to the pin. An additional 10 µF capacitor (tantalum) in
parallel is also recommended to further attenuate noise
present in application boards.
3.2
Ground (VSS)
The VSS pin is the device ground reference.
The user must connect the VSS pin to a ground plane
through a low-impedance connection. If an analog
ground path is available in the application PCB (Printed
Circuit Board), it is highly recommended that the VSS
pin be tied to the analog ground path or isolated within
an analog ground plane of the circuit board.
3.3
Voltage Reference Pin (VREF)
The VREF pin is either an input or an output. When the
DAC’s voltage reference is configured as the VREF pin,
the pin is an input. When the DAC’s voltage reference is
configured as the internal band gap, the pin is an output.
When the DAC’s voltage reference is configured as the
VREF pin, there are two options for this voltage input:
buffered or unbuffered. The buffered option is offered in
cases where the external reference voltage does not
have sufficient current capability to not drop its voltage
when connected to the internal resistor ladder circuit.
When the DAC’s voltage reference is configured as the
device VDD, the VREF pin is disconnected from the
internal circuit.
When the DAC’s voltage reference is configured as the
internal band gap, the VREF pin’s drive capability is
minimal, so the output signal must be buffered.
See Section 5.2 “Voltage Reference Selection” and
Register 4-2 for more details on the Configuration bits.
3.4
I2C Client Address Pins (A0, A1)
The state of these pins will determine the device’s I2C
Client Address bits 1:0 values (overriding the ADD0 bit
and the ADD1 bit in Register 4-5).
3.5
No Connect (NC)
The NC pin is not internally connected to the device.
2022 Microchip Technology Inc. and its subsidiaries
3.6
Analog Output Voltage Pins
(VOUT0, VOUT1)
VOUT0 and VOUT1 are the DAC analog voltage output
pins. Each DAC output has an output amplifier. The DAC
output range depends on the selection of the voltage reference source (and potential output gain selection).
These are:
• Device VDD – The Full-Scale Range (FSR) of the
DAC output is from VSS to approximately VDD.
• VREF pin – The FSR of the DAC output is from
VSS to G x VRL, where G is the gain selection
option (1x or 2x).
• Internal Band Gap – The FSR of the DAC output
is from VSS to G X VBG, where G is the gain selection option (1x or 2x).
In Normal mode, the DC impedance of the output pin is
about 1. In Power-Down mode, the output pin is
internally connected to a known pull-down resistor of
1 k, 100 k or open. The power-down selection bits
settings are shown in Register 4-3 (Table 5-5).
3.7
Latch/High-Voltage Command Pin
(LAT/HVC)
The DAC output value update event can be controlled
and synchronized using the LAT pin, for one or both
channels, on single or different devices.
The LAT pin controls the effect of the Volatile Wiper
registers, VRxB:VRxA and PDxB:PDxA, and the Gx bits
on the DAC output. If the LAT pin is held at VIH, the
values sent to the Volatile Wiper registers and Configuration bits have no effect on the DAC outputs. After the
Volatile Wiper registers and Configuration bits are
loaded with the desired data, once the voltage on the pin
transitions to VIL, the values in the Volatile Wiper registers and Configuration bits are transferred to the DAC
outputs. Pulsing LAT low during writes to the registers
could lead to unpredictable DAC output voltage values
until the next pulse is issued and must be avoided. The
pin is level-sensitive, so writing to the Volatile Wiper registers and Configuration bits while it is being held at VIL
will trigger an immediate change in the outputs.
For dual output devices in MSOP and DFN packages,
the LAT pin controls both channels at the same time.
The HVC pin allows the device’s MTP memory to be
programmed for the MCP47CMDXX devices. The
programming voltage supply should provide 7.5V and
at least 6.4 mA.
Note:
The HVC pin must have voltages greater
than 5.5V present only during the MTP
programming operation. Using voltages
greater than 5.5V for an extended time on
the pin may cause device reliability
issues.
DS20006666B-page 41
MCP47CXDX1/2
3.8
I2C – Serial Clock Pin (SCL)
The SCL pin is the serial clock pin of the I2C interface.
The MCP47CXDX1/2 I2C interface only acts as a Client
and the SCL pin accepts only external serial clocks.
The input data from the device are shifted into the SDA
pin on the rising edges of the SCL clock, and output
from the device occurs at the falling edges of the SCL
clock. The SCL pin is an open-drain N-channel driver.
Therefore, it needs an external pull-up resistor from the
VDD line to the SCL pin. Refer to Section 6.0 “I2C
Serial Interface Module” for more details on the I2C
serial interface communication.
DS20006666B-page 42
3.9
I2C – Serial Data Pin (SDA)
The SDA pin is the serial data pin of the I2C interface.
The SDA pin is used to write or read the DAC registers
and Configuration bits. The SDA pin is an open-drain
N-channel driver. Therefore, it needs an external
pull-up resistor from the VDD line to the SDA pin. Except
for Start and Stop conditions, the data on the SDA pin
must be stable during the high period of the clock. The
high or low state of the SDA pin can only change when
the clock signal on the SCL pin is low. See Section 6.0
“I2C Serial Interface Module”.
2022 Microchip Technology Inc. and its subsidiaries
MCP47CXDX1/2
4.0
GENERAL DESCRIPTION
The MCP47CXDX1 (MCP47CXD01, MCP47CXD11
and MCP47CXD21) devices are single channel voltage
output devices.
4.1
Power-on Reset/Brown-out Reset
(POR/BOR)
MCP47CXDX2 (MCP47CXD02, MCP47CXD12 and
MCP47CXD22) are dual channel voltage output devices.
The internal Power-on Reset (POR)/Brown-out Reset
(BOR) circuit monitors the power supply voltage (VDD)
during operation. This circuit ensures correct device
start-up at system power-up and power-down events.
These devices are offered with 8-bit (MCP47CXD0X),
10-bit (MCP47CXD1X) and 12-bit (MCP47CXD2X)
resolutions.
The device’s RAM Retention Voltage (VRAM) is lower
than the POR/BOR Voltage Trip Point (VPOR/VBOR).
The maximum VPOR/VBOR voltage is less than 1.8V.
The family offers two memory options:
The POR and BOR trip points are at the same voltage,
and the condition is determined by whether the VDD
voltage is rising or falling (see Figure 4-1). What occurs
is different depending on whether the Reset is a POR
or BOR Reset.
• The MCP47CVDXX devices have volatile
memory.
• The MCP47CMDXX have 32-times
programmable nonvolatile memory (MTP).
All devices include an I2C serial interface and a write
latch (LAT) pin to control the update of the analog output voltage value from the value written in the Volatile
DAC Output register.
The devices use a resistor ladder architecture. The
resistor ladder DAC is driven from a softwareselectable voltage reference source. The source can
be either the device’s internal VDD, an external VREF
pin voltage (buffered or unbuffered) or an internal
band gap voltage source.
POR occurs as the voltage rises (typically from 0V),
while BOR occurs as the voltage falls (typically from
VDD(MIN) or higher).
When VPOR/VBOR < VDD < 2.7V, the electrical performance may not meet the data sheet specifications. In
this region, the device is capable of reading and writing
to its volatile memory if the proper serial command is
executed.
4.1.1
POWER-ON RESET
The DAC output is buffered with a low-power and
precision output amplifier. This output amplifier provides a rail-to-rail output with low offset voltage and
low noise. The gain (1x or 2x) of the output buffer is
software configurable.
The Power-on Reset is the case where the device’s
VDD has power applied to it from the VSS voltage level.
As the device powers up, the VOUT pin floats to an
unknown value. When the device’s VDD is above the
transistor threshold voltage of the device, the output
starts to be pulled low.
The devices operate from a single supply voltage. This
voltage is specified from 2.7V to 5.5V for full specified
operation, and from 1.8V to 5.5V for digital operation.
The device operates between 1.8V and 2.7V, but
some device parameters are not specified.
After the VDD is above the POR/BOR trip point
(VBOR/VPOR), the resistor network’s wiper is loaded
with the POR value. The POR value is either mid-scale
(MCP47CVDXX) or the user’s MTP programmed value
(MCP47CMDXX).
The MCP47CMDXX devices also have userprogrammable nonvolatile configuration memory
(MTP). This allows the device’s desired POR values to
be saved or the I2C address to be changed. The
device also has general purpose MTP memory
locations for storing system-specific information
(calibration data, serial numbers, system ID information). A high-voltage requirement for programming on
the HVC pin ensures that these device settings are not
accidentally modified during normal system operation.
Therefore, it is recommended that the MTP memory
be programmed at the user’s factory.
Note:
In order to have the MCP47CMDXX
devices load the values from nonvolatile
memory locations at POR, they have to be
programmed at least once by the user;
otherwise, the loaded values will be the
default ones. After MTP programming, a
POR event is required to load the written
values from the nonvolatile memory.
The main functional blocks are:
•
•
•
•
•
Power-on Reset/Brown-out Reset (POR/BOR)
Device Memory
Resistor Ladder
Output Buffer/VOUT Operation
I2C Serial Interface Module
2022 Microchip Technology Inc. and its subsidiaries
DS20006666B-page 43
MCP47CXDX1/2
Volatile memory determines the Analog Output (VOUT)
pin voltage. After the device is powered up, the user
can update the device memory.
The Analog Output (VOUT) state is determined by the
state of the Volatile Configuration bits and the DAC
register. This is called a Power-on Reset (event).
When the rising VDD voltage crosses the VPOR trip
point, the following occur:
Figure 4-1 illustrates the conditions for power-up and
power-down events under typical conditions.
• The default DAC POR value is latched into the
Volatile DAC register.
• The default DAC POR Configuration bit values
are latched into the Volatile Configuration bits.
• POR status bit is set (‘1’).
• The Reset Delay Timer (tPORD) starts; when the
Reset Delay Timer (tPORD) times out, the I2C
serial interface is operational. During this delay
time, the I2C interface will not accept commands.
• The Device Memory Address Pointer is forced to 00h.
POR starts Reset Delay Timer.
When timer times out, the I2C interface
can operate (if VDD VDD(MIN)).
Volatile Memory
Retains Data Value
POR Reset
Force Active
Default device configuration
latched into Volatile Configuration
bits and DAC register.
POR status bit is set (‘1’).
TPOR2OD
Case 1: VDD Ramp
BOR Reset,
Volatile DAC Register = 000h
Volatile VRxB:VRxA = 00
Volatile Gx = 0
Volatile PDxB:PDxA = 11
VDD(MIN)
VBOR
VPOR
Volatile Memory
becomes Corrupted
VRAM
Device in Unknown
State
Volatile Memory
Retains Data Value
Device Normal Operation
in POR
State
Below Min. Device in Device in
Unknown
Operating PowerDown State State
Voltage
Device in
Known State
POR Event
Case 2: VDD Step
VDD(MIN)
VBOR
VPOR
Volatile Memory
becomes Corrupted
TPORD2OD
VRAM
Device in Unknown
State
FIGURE 4-1:
DS20006666B-page 44
Normal Operation
Below Min. Device in Device in
Operating PowerUnknown
Voltage
Down State State
Power-on Reset Operation.
2022 Microchip Technology Inc. and its subsidiaries
MCP47CXDX1/2
4.1.2
BROWN-OUT RESET
A Brown-out Reset occurs when a device had power
applied to it and that power (voltage) drops below the
specified range.
When the falling VDD voltage crosses the VPOR trip
point (BOR event), the following occurs:
• Serial interface is disabled.
• MTP writes are disabled.
• Device is forced into a power-down state
(PDxB:PDxA = 11). Analog circuitry is turned off.
• Volatile DAC register is forced to 000h.
Volatile Configuration bits, VRxB:VRxA and Gx, are
forced to ‘0’.
If the VDD voltage decreases below the VRAM voltage,
all volatile memory may become corrupted.
As the voltage recovers above the VPOR/VBOR voltage,
see Section 4.1.1 “Power-on Reset” for further details.
Serial commands not completed due to a brown-out
condition may cause the memory location to become
corrupted.
Figure 4-1 illustrates the conditions for power-up and
power-down events under typical conditions.
4.2
Device Memory
Each memory location is up to 16 bits wide. The
memory-mapped register space is shown in Table 4-1.
The I2C interface depends on how this memory is read
and written. Refer to Section 6.0 “I2C Serial Interface
Module” and Section 7.0 “Device Commands” for
more details on reading and writing the device’s
memory.
4.2.1
VOLATILE REGISTER MEMORY
(RAM)
The MCP47CXDX1/2 devices have volatile memory to
directly control the operation of the DACs. There are
up to five volatile memory locations:
•
•
•
•
DAC0 and DAC1 Output Value registers
VREF Select register
Power-Down Configuration register
Gain and Status register
The volatile memory starts functioning when the
device VDD is at (or above) the RAM retention voltage
(VRAM). The volatile memory will be loaded with the
default device values when the VDD rises across the
VPOR/VBOR voltage trip point.
After the device is powered-up, the user can update the
device memory. Table 4-2 shows the volatile memory
locations and their interaction due to a POR event.
User memory includes the following types:
• Volatile Register Memory (RAM)
• Nonvolatile Register Memory (MTP)
MTP memory is only present for the MCP47CMDXX
devices and has three groupings:
• NV DAC Output Values (loaded on POR event)
• Device Configuration Memory
• General Purpose NV Memory
2022 Microchip Technology Inc. and its subsidiaries
DS20006666B-page 45
MCP47CXDX1/2
Dual
Address
Single(1)
Dual(1)
MCP47CXDX1/2 MEMORY MAP (16-BIT)
Y
10h Nonvolatile DAC Wiper Register 0
Y
Y
11h Nonvolatile DAC Wiper Register 1
—
Y
12h Reserved
— —
Single
Address
TABLE 4-1:
00h Volatile DAC Wiper Register 0
Y
01h Volatile DAC Wiper Register 1
—
Y
02h Reserved
— —
03h Reserved
— —
13h Reserved
— —
04h Reserved
— —
14h Reserved
— —
05h Reserved
— —
15h Reserved
— —
06h Reserved
— —
16h Reserved
— —
07h Reserved
— —
17h Reserved
— —
08h Volatile VREF Register
Y
Y
18h Nonvolatile VREF Register
Y
Y
09h Volatile Power-Down Register
Y
Y
19h Nonvolatile Power-Down Register
Y
Y
0Ah Volatile Gain and Status Register
Y
Y
1Ah NV Gain and I2C 7-Bit Client Address
Y
Y
Y
Function
Function
0Bh Reserved
— —
1Bh NV WiperLock™ Technology Register
Y
0Ch General Purpose MTP
Note 1
1Ch General Purpose MTP
Note 1
0Dh General Purpose MTP
Note 1
1Dh General Purpose MTP
Note 1
0Eh General Purpose MTP
Note 1
1Eh General Purpose MTP
Note 1
0Fh General Purpose MTP
Note 1
1Fh General Purpose MTP
Note 1
Legend:
Volatile Memory Addresses
MTP Memory Addresses
Memory Locations Not Implemented on this Device Family
Note 1:
On nonvolatile memory devices only (MCP47CMDXX).
DS20006666B-page 46
2022 Microchip Technology Inc. and its subsidiaries
MCP47CXDX1/2
4.2.2
NONVOLATILE REGISTER
MEMORY (MTP)
This memory option is available only for the
MCP47CMDXX devices.
MTP memory starts functioning below the device’s
VPOR/VBOR trip point, and once the VPOR event
occurs, the Volatile Memory registers are loaded with
the corresponding MTP register memory values.
Memory addresses, 0Ch through 1Fh, are nonvolatile
memory locations. These registers contain the DAC
POR/BOR wiper values, the DAC POR/BOR Configuration bits, the I2C Client address and eight general
purpose memory addresses for storing user-defined
data as calibration constants or identification numbers.
The Nonvolatile DAC Wiper registers and Configuration
bits contain the user’s DAC Output and configuration
values for the POR event.
The Nonvolatile DAC Wiper registers contain the user’s
DAC output and configuration values for the POR
event. These nonvolatile values will overwrite the
factory default values. If these MTP addresses are
unprogrammed, the factory default values define the
output state.
The Nonvolatile DAC registers enable the stand-alone
operation of the device (without microcontroller control)
after being programmed to the desired values.
4.2.3
POR/BOR OPERATION WITH
WIPERLOCK TECHNOLOGY
ENABLED
Regardless of the WiperLock technology state, a POR
event will load the Volatile DACx Wiper register value
with the Nonvolatile DACx Wiper register value. Refer
to Section 4.1 “Power-on Reset/Brown-out Reset
(POR/BOR)” for further information.
4.2.4
4.2.4.1
UNIMPLEMENTED LOCATIONS
Unimplemented Register Bits
When issuing read commands to a valid memory location with unimplemented bits, the unimplemented bits
will be read as ‘0’.
4.2.4.2
Unimplemented (RESERVED)
Locations
There are a number of unimplemented memory
locations that are reserved for future use. Normal
(voltage) commands (read or write) to any unimplemented memory address will result in a command
error condition (I2C NACK).
High-voltage commands to any unimplemented
Configuration bit(s) will also result in a command error
condition.
To program nonvolatile memory locations, a highvoltage source on the LAT/HVC pin is required. Each
register/MTP location can be programmed 32 times.
After 32 writes, a new write operation will not be
possible and the last successful value written will
remain associated with the memory location.
The device starts writing the MTP memory cells at the
completion of the serial interface command at the rising
edge of the last data bit. The high voltage must remain
present on the LAT/HVC pin until the write cycle is complete; otherwise, the write is unsuccessful and the location is compromised (cannot be used again and the
number of available writes decreases by one).
To recover from an aborted MTP write operation, the
following procedure must be used:
• Write again any valid value to the same address
• Force a POR condition
• Write again the desired value to the MTP location
It is recommended to keep high voltage on only during
the MTP write command and programming cycle;
otherwise, the reliability of the device could be affected.
2022 Microchip Technology Inc. and its subsidiaries
DS20006666B-page 47
MCP47CXDX1/2
POR/BOR Value
POR/BOR Value
12-Bit
8-Bit
10-Bit
12-Bit
Function
10-Bit
Function
Address
FACTORY DEFAULT POR/BOR VALUES (MTP MEMORY UNPROGRAMMED)
8-Bit
Address
TABLE 4-2:
00h Volatile DAC0 Register
7Fh
1FFh
7FFh
10h Nonvolatile DAC0 Wiper
Register(1)
7Fh
1FFh
7FFh
01h Volatile DAC1 Register
7Fh
1FFh
7FFh
11h Nonvolatile DAC1 Wiper
Register(1)
7Fh
1FFh
7FFh
02h Reserved(3)
—
—
—
12h Reserved(3)
—
—
—
03h
Reserved(3)
—
—
—
13h Reserved(3)
—
—
—
04h
Reserved(3)
—
—
—
14h
Reserved(3)
—
—
—
05h Reserved(3)
—
—
—
15h Reserved(3)
—
—
—
06h Reserved(3)
—
—
—
16h Reserved(3)
—
—
—
—
Reserved(3)
—
07h
Reserved(3)
—
—
08h Volatile VREF Register
0000h 0000h 0000h
—
18h Nonvolatile VREF Register(1) 0000h
0000h
0000h
09h Volatile Power-Down
Register
0000h 0000h 0000h
19h Nonvolatile Power-Down
Register(1)
0000h
0000h
0000h
0Ah Volatile Gain and Status
Register(4)
0080h 0080h 0080h
1Ah NV Gain and I2C 7-Bit Client 0060h
Address(1, 2)
0060h
0060h
0Bh Reserved(3)
0000h 0000h 0000h
1Bh NV WiperLock™
Technology Register(1)
0000h
0000h
0000h
0Ch General Purpose MTP(1)
—
17h
0000h 0000h 0000h
1Ch General Purpose MTP(1)
0000h
0000h
0000h
MTP(1)
0000h 0000h 0000h
1Dh General Purpose
MTP(1)
0000h
0000h
0000h
0Eh General Purpose MTP(1)
0000h 0000h 0000h
1Eh General Purpose MTP(1)
0000h
0000h
0000h
0000h 0000h 0000h
MTP(1)
0000h
0000h
0000h
0Dh General Purpose
0Fh General Purpose
MTP(1)
1Fh General Purpose
Legend:
Volatile Memory Address Range
Nonvolatile Memory Address Range
Not Implemented
Note 1: On nonvolatile devices only (MCP47CMDXX).
2: Default I2C 7-bit Client address is ‘110 0000’ (‘110 00xx’ when A1:A0 bits are determined from the A1 and A0 pins).
3: Reading a reserved memory location will result in the I2C command to Not ACK the command byte. The device data
bits will output all ‘1’s. A Start condition will reset the I2C interface.
4: The ‘1’ bit is the POR status bit, which is set after the POR event and cleared after address 0Ah is read.
DS20006666B-page 48
2022 Microchip Technology Inc. and its subsidiaries
MCP47CXDX1/2
4.2.5
DEVICE REGISTERS
Register 4-1 shows the format of the DAC Output Value
registers for the volatile memory locations. These
registers will be either 8 bits, 10 bits or 12 bits wide. The
values are right justified.
REGISTER 4-1:
DAC0 (00h/10h) AND DAC1 (01h/11h) OUTPUT VALUE REGISTERS
(VOLATILE/NONVOLATILE)
U-0
U-0
U-0
U-0
12-bit
—
—
—
—
R/W-n R/W-n R/W-n R/W-n R/W-n R/W-n R/W-n R/W-n R/W-n R/W-n R/W-n R/W-n
D11
D10
D09
D08
D07
D06
D05
D04
D03
D02
D01
D00
10-bit
—
—
—
—
—
—
D09
D08
D07
D06
D05
D04
D03
D02
D01
D00
8-bit
—
—
—
—
—
—
—
—
D07
D06
D05
D04
D03
D02
D01
D00
bit 15
bit 0
Legend:
R = Readable bit
-n = Value at POR
= 12-bit device
12-bit
10-bit
W = Writable bit
‘1’ = Bit is set
= 10-bit device
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
= 8-bit device
x = Bit is unknown
8-bit
bit 15-12 bit 15-10 bit 15-8
Unimplemented: Read as ‘0’
bit 11-0
—
—
D11:D00: DAC Output Value bits – 12-bit devices
FFFh = Full-scale output value
7FFh = Mid-scale output value
000h = Zero-scale output value
—
bit 9-0
—
D09:D00: DAC Output Value bits – 10-bit devices
3FFh = Full-scale output value
1FFh = Mid-scale output value
000h = Zero-scale output value
—
—
bit 7-0
D07:D00: DAC Output Value bits – 8-bit devices
FFh = Full-scale output value
7Fh = Mid-scale output value
00h = Zero-scale output value
2022 Microchip Technology Inc. and its subsidiaries
DS20006666B-page 49
MCP47CXDX1/2
Register 4-2 shows the format of the Voltage Reference Control register. Each DAC has two bits to control
the source of the voltage reference of the DAC. This
register is for the volatile memory locations. The width
of this register is two times the number of DACs for the
device.
REGISTER 4-2:
VOLTAGE REFERENCE (VREF) CONTROL REGISTERS (08h/18h)
(VOLATILE/NONVOLATILE)
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
Single
—
—
—
—
—
—
—
—
—
—
—
—
Dual
—
—
—
—
—
—
—
—
—
—
—
—
R/W-n R/W-n R/W-n R/W-n
—(1)
—(1)
VR0B VR0A
VR1B VR1A VR0B VR0A
bit 15
bit 0
Legend:
R = Readable bit
-n = Value at POR
= Single channel device
W = Writable bit
U = Unimplemented bit, read as ‘0’
‘1’ = Bit is set
‘0’ = Bit is cleared
= Dual channel device
x = Bit is unknown
Single
Dual
bit 15-2
bit 15-4
Unimplemented: Read as ‘0’
bit 1-0
bit 3-0
VRxB:VRxA: DAC Voltage Reference Control bits
11 = VREF pin (buffered); VREF buffer enabled
10 = VREF pin (unbuffered); VREF buffer disabled
01 = Internal band gap (1.214V typical); VREF buffer enabled, VREF voltage driven when
powered down(2)
00 = VDD (unbuffered); VREF buffer disabled, use this state with power-down bits for lowest current
Note 1:
2:
Unimplemented bit, read as ‘0’.
When the internal band gap is selected, the band gap voltage source will continue to output the voltage on
the VREF pin in any of the Power-Down modes. To reduce the power consumption to its lowest level
(band gap disabled), after selecting the desired Power-Down mode, the voltage reference must be
changed to VDD or the VREF pin unbuffered (‘00’ or ‘10’), which turns off the internal band gap circuitry.
After wake-up, the user needs to reselect the internal band gap (‘01’) for the voltage reference source.
DS20006666B-page 50
2022 Microchip Technology Inc. and its subsidiaries
MCP47CXDX1/2
Register 4-3 shows the format of the Power-Down
Control register. Each DAC has two bits to control the
power-down state of the DAC. This register is for the
volatile memory locations and the nonvolatile memory
locations. The width of this register is two times the
number of DACs for the device.
REGISTER 4-3:
POWER-DOWN CONTROL REGISTERS (09h/19h)
(VOLATILE/NONVOLATILE)
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
Single
—
—
—
—
—
—
—
—
—
—
—
—
Dual
—
—
—
—
—
—
—
—
—
—
—
—
R/W-n R/W-n R/W-n R/W-n
—(1)
—(1)
PD0B PD0A
PD1B PD1A PD0B PD0A
bit 15
bit 0
Legend:
R = Readable bit
-n = Value at POR
= Single channel device
W = Writable bit
U = Unimplemented bit, read as ‘0’
‘1’ = Bit is set
‘0’ = Bit is cleared
= Dual channel device
Single
Dual
bit 15-2
bit 15-4
Unimplemented: Read as ‘0’
bit 1-0
bit 3-0
PDxB:PDxA: DAC Power-Down Control bits(2)
11 = Powered down – VOUT is open circuit
10 = Powered down – VOUT is loaded with a 100 k resistor to ground
01 = Powered down – VOUT is loaded with a 1 k resistor to ground
00 = Normal operation (not powered down)
Note 1:
2:
Unimplemented bit, read as ‘0’.
See Table 5-5 for more details.
2022 Microchip Technology Inc. and its subsidiaries
x = Bit is unknown
DS20006666B-page 51
MCP47CXDX1/2
Register 4-4 shows the format of the Gain Control and
System Status register. Each DAC has one bit to
control the gain of the DAC and two Status bits.
REGISTER 4-4:
GAIN CONTROL AND SYSTEM STATUS REGISTER (0Ah)
(VOLATILE)
U-0
U-0
U-0
U-0
U-0
U-0
R
U-0
U-0
U-0
U-0
U-0
U-0
Single
—
—
—
—
—
—
R/W-n R/W-n R/C-1
—(1)
G0
POR
MTPMA
—
—
—
—
—
—
Dual
—
—
—
—
—
—
G1
G0
POR
MTPMA
—
—
—
—
—
—
bit 15
bit 0
Legend:
R = Readable bit
-n = Value at POR
= Single channel device
W = Writable bit
C = Clearable bit
‘1’ = Bit is set
‘0’ = Bit is cleared
= Dual channel device
U = Unimplemented bit, read as ‘0’
x = Bit is unknown
Single
Dual
bit 15-9
bit 15-10 Unimplemented: Read as ‘0’
—
bit 9
G1: DAC1 Output Driver Gain Control bit
1 = 2x gain; not applicable when VDD is used as VRL(2)
0 = 1x gain
bit 8
bit 8
G0: DAC0 Output Driver Gain Control bit
1 = 2x gain; not applicable when VDD is used as VRL(2)
0 = 1x gain
bit 7
bit 7
POR: Power-on Reset (Brown-out Reset) Status bit
This bit indicates if a POR or BOR event has occurred since the last read command of this
register. Reading this register clears the state of the POR Status bit.
1 = A POR (BOR) event occurred since the last read of this register; reading this register clears
this bit
0 = A POR (BOR) event has not occurred since the last read of this register
bit 6
bit 6
MTPMA: MTP Memory Access Status bit(3)
This bit indicates if the MTP memory access is occurring.
1 = An MTP memory access is currently occurring (during the POR MTP read cycle or an MTP
write cycle is occurring); only serial commands addressing the volatile memory are allowed
0 = An MTP memory access is NOT currently occurring
bit 5-0
bit 5-0
Unimplemented: Read as ‘0’
Note 1:
2:
Unimplemented bit, read as ‘0’.
The DAC’s Gain bit is ignored and the gain is forced to 1x (Gx = 0) when the DAC voltage reference is
selected as VDD (VRxB:VRxA = 00).
For volatile memory devices, this bit is read as ‘0’.
3:
DS20006666B-page 52
2022 Microchip Technology Inc. and its subsidiaries
MCP47CXDX1/2
Register 4-5 shows the format of the Nonvolatile Gain
Control and Client Address register. Each DAC has
one bit to control the gain of the DAC. I2C devices also
have seven bits that are the I2C Client address.
REGISTER 4-5:
GAIN CONTROL AND CLIENT ADDRESS REGISTER (1Ah)
(NONVOLATILE)
R/W-n
U-0
R/W-n
R/W-n
R/W-n
R/W-n R/W-n
Single
U-0 U-0 U-0 U-0 U-0 U-0 R/W-n
—
—
—
—
—
—
—(1)
G0
—
ADD6
ADD5
ADD4
ADD3
ADD2 ADD1(3) ADD0(3)
Dual
—
—
—
—
—
—
G1
G0
—
ADD6
ADD5
ADD4
ADD3
ADD2 ADD1(3) ADD0(3)
bit 15
R/W-n
R/W-n
bit 0
Legend:
R = Readable bit
-n = Value at POR
= Single channel device
W = Writable bit
C = Clearable bit
‘1’ = Bit is set
‘0’ = Bit is cleared
= Dual channel device
Single
Dual
bit 15-10
bit 15-10
Unimplemented: Read as ‘0’
bit 9-8
bit 9-8
Gx: DAC Output Driver Gain Control bits(2)
1 = 2x gain
0 = 1x gain
bit 7
bit 7
Unimplemented: Read as ‘0’
bit 6-0
bit 6-0
ADD6:ADD0: I2C 7-Bit Client Address bits(3)
Note 1:
2:
3:
U = Unimplemented bit, read as ‘0’
x = Bit is unknown
Unimplemented bit, read as ‘0’.
When the DAC voltage reference is selected as VDD (VRxB:VRxA = 00), the DAC’s Gain bit is ignored and
the gain is forced to 1x (Gx = 0).
For I2C devices that have the A1 and A0 pins, the 7-bit Client address is ADD6:ADD2 + A1:A0. These bits
(ADD1 and ADD0) can be read and written, but the value of A1 and A0 pins will take precedence, so their
value will be disregarded by the I2C communication module. For devices that do not have the A1 and A0
pins, the 7-bit Client address is determined only by the ADD6:ADD0 bits.
2022 Microchip Technology Inc. and its subsidiaries
DS20006666B-page 53
MCP47CXDX1/2
Register 4-6 shows the format of the DAC WiperLock
Technology Status register. The width of this register is
two times the number of DACs for the device.
REGISTER 4-6:
WiperLock technology bits only control access to
volatile memory. Nonvolatile memory write access is
controlled by the requirement of high voltage on the
HVC pin, which is recommended to not be available
during normal device operation.
WiperLock™ TECHNOLOGY CONTROL REGISTER (1Bh) (NONVOLATILE)
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
Single
—
—
—
—
—
—
—
—
—
—
—
—
Dual
—
—
—
—
—
—
—
—
—
—
—
—
bit 15
R/W-n R/W-n R/W-n R/W-n
—(1)
—(1)
WL0B WL0A
WL1B WL1A WL0B WL0A
bit 0
Legend:
R = Readable bit
-n = Value at POR
= Single channel device
W = Writable bit
C = Clearable bit
‘1’ = Bit is set
‘0’ = Bit is cleared
= Dual channel device
U = Unimplemented bit, read as ‘0’
x = Bit is unknown
Single
Dual
bit 15-2
bit 15-4
Unimplemented: Read as ‘0’
bit 1-0
bit 3-1
WLxB:WLxA: WiperLock™ Technology Status bits(2)
11 = Volatile DAC Wiper register and Volatile DAC Configuration bits are locked
10 = Volatile DAC Wiper register is locked and Volatile DAC Configuration bits are unlocked
01 = Volatile DAC Wiper register is unlocked and Volatile DAC Configuration bits are locked
00 = Volatile DAC Wiper register and Volatile DAC Configuration bits are unlocked
Note 1:
2:
Unimplemented bit, read as ‘0’.
The Volatile PDxB:PDxA bits are NOT locked due to the requirement of being able to exit Power-Down mode.
DS20006666B-page 54
2022 Microchip Technology Inc. and its subsidiaries
MCP47CXDX1/2
5.0
DAC CIRCUITRY
The functional blocks of the DAC include:
•
•
•
•
•
The Digital-to-Analog Converter circuitry converts a
digital value into its analog representation. This
description shows the functional operation of the
device.
The DAC circuit uses a resistor ladder implementation.
Devices have up to two DACs. Figure 5-1 shows the
functional block diagram for the MCP47CXDX1/2 DAC
circuitry.
Power-Down
Operation
Resistor Ladder
Voltage Reference Selection
Output Buffer/VOUT Operation
Latch Pin (LAT)
Power-Down Operation
VDD
PD1:PD0 and
VREF1:VREF0
Internal Band Gap
VDD
Voltage
Reference
Selection
VREF
VREF1:VREF0
and PD1:PD0
Band Gap
(1.214V typical)
VDD
VREF1:VREF0
A (RL)
RS(2n)
DAC
Output
Selection
Power-Down
Operation
VDD
PD1:PD0
RS(2n – 1)
VW
RS(2n – 3)
VOUT
Gain
(1x or 2x)
RRL
(~71 k)
Output Buffer/VOUT
Operation
RS(2)
PD1:PD0
100 kΩ
RS(2n – 2)
1 kΩ
VRL
Power-Down
Operation
DAC Register Value
V W = ---------------------------------------------------------------------- V RL
# Resistor in Resistor Ladder
RS(1)
Where:
B
Resistor
Ladder
# Resistors in Resistor Ladder = 256 (MCP47CXD0X)
1024 (MCP47CXD1X)
4096 (MCP47CXD2X)
FIGURE 5-1:
MCP47CXDX1/2 DAC Module Block Diagram.
2022 Microchip Technology Inc. and its subsidiaries
DS20006666B-page 55
MCP47CXDX1/2
5.1
Resistor Ladder
DAC
Register
The resistor ladder is a digital potentiometer with the
A Terminal connected to the selected reference voltage
and the B Terminal internally grounded (see Figure 5-2).
The Volatile DAC register controls the wiper position.
The Wiper Voltage (VW) is proportional to the DAC
register value divided by the number of Resistor
Elements (RS) in the ladder (256, 1024 or 4096) related
to the VRL voltage.
VRL
RS(2n)
The output of the resistor network will drive the input of
an output buffer.
RW(1)
2n – 1
RS(2n – 1)
RW(1)
2n – 2
RS(2n – 2)
RW(1)
2n – 3
The resistor network is made up of three parts:
• Resistor Ladder (string of RS elements)
• Wiper Switches
• DAC Register Decode
RS(2n – 3)
The resistor ladder has a typical impedance (RRL) of
approximately 71 k. This Resistor Ladder Resistance
(RRL) may vary from device to device, up to ±10%.
Since this is a voltage divider configuration, the actual
RRL resistance does not affect the output, given a fixed
voltage at VRL.
VW
RRL
RS(2)
RS(1)
Equation 5-1 shows the calculation for the step
resistance.
Note:
2
RW(1)
1
RW(1)
0
Analog MUX
2n
The maximum wiper position is
– 1,
while the number of resistors in the
resistor ladder is 2n. This means that
when the DAC register is at full scale,
there is one Resistor Element (RS)
between the wiper and the VRL voltage.
If the unbuffered VREF pin is used as the VRL voltage
source, the external voltage source must have a low
output impedance.
When the DAC is powered down, the resistor ladder is
disconnected from the selected reference voltage.
DS20006666B-page 56
RW(1)
Note 1:
The analog Switch Resistance (RW)
does not affect performance due to
the voltage divider configuration.
FIGURE 5-2:
Block Diagram.
Resistor Ladder Model
EQUATION 5-1:
RS CALCULATION
R RL
R S = ------------- 256
8-Bit Device
R RL
R S = ----------------- 1024
10-Bit Device
R RL
R S = ----------------- 4096
12-Bit Device
2022 Microchip Technology Inc. and its subsidiaries
MCP47CXDX1/2
5.2
Voltage Reference Selection
The resistor ladder has up to four sources for the reference voltage. The selection of the voltage reference
source is specified with the Volatile VREF1:VREF0
Configuration bits (see Register 4-2). The selected
voltage source is connected to the VRL node (see
Figure 5-3 and Figure 5-4).
The four voltage source options for the resistor ladder
are:
1.
2.
3.
4.
VDD pin voltage.
Internal band gap voltage reference (VBG).
VREF pin voltage – unbuffered.
VREF pin voltage – internally buffered.
VDD
PD1:PD0 and
VREF1:VREF0
PD1:PD0 and
VREF1:VREF0
Band Gap(1)
(1.214V typical)
VREF
On a POR/BOR event, the default configuration state or
the value written in the Nonvolatile register is latched into
the Volatile VREF1:VREF0 Configuration bits.
PD1:PD0 and
VREF1:VREF0
Note 1:
VREF1:VREF0
Reference
Selection
VDD
Band Gap
VRL
Buffer
FIGURE 5-3:
Resistor Ladder Reference
Voltage Selection Block Diagram.
VRL
VDD
If the VREF pin is used with an external voltage source,
then the user must select between Buffered or
Unbuffered mode.
VREF
VDD
The band gap voltage (VBG) is 1.214V
typical. The band gap output goes
through the buffer with a 2x gain to
create the VRL voltage. See Table 5-1
for additional information on the
band gap circuit.
FIGURE 5-4:
Reference Voltage Selection
Implementation Block Diagram.
5.2.1
USING VDD AS VREF
When the user selects the VDD as reference, the VREF
pin voltage is not connected to the resistor ladder. The
VDD voltage is internally connected to the resistor
ladder.
5.2.2
USING AN EXTERNAL VREF
SOURCE IN UNBUFFERED MODE
In this case, the VREF pin voltage may vary from VSS to
VDD. The voltage source must have a low output
impedance. If the voltage source has a high output
impedance, then the voltage on the VREF pin could be
lower than expected. The resistor ladder has a typical
impedance of 71 k and a typical capacitance of 29 pF.
If a single VREF pin is supplying multiple DACs, the
VREF pin source must have adequate current capability
to support the number of DACs. It must be assumed
that the Resistor Ladder Resistance (RRL) of each DAC
is at the minimum specified resistance and these
resistances are in parallel.
If the VREF pin is tied to the VDD voltage, selecting
the VDD Reference mode (VREF1:VREF0 = 00) is
recommended.
2022 Microchip Technology Inc. and its subsidiaries
DS20006666B-page 57
MCP47CXDX1/2
5.3
The VREF pin voltage may be from 0V to VDD. The input
buffer (amplifier) provides low offset voltage, low noise,
and a very high input impedance, with only minor
limitations on the input range and frequency response.
Any variation or noises on the reference source can
directly affect the DAC output. The reference voltage
needs to be as clean as possible for accurate DAC
performance.
5.2.4
USING THE INTERNAL BAND GAP
AS VOLTAGE REFERENCE
Output Buffer/VOUT Operation
The output driver buffers the Wiper Voltage (VW) of the
resistor ladder.
The DAC output is buffered with a low-power, precision
output amplifier with selectable gain. This amplifier provides a rail-to-rail output with low offset voltage and low
noise. The amplifier’s output can drive the resistive and
high-capacitive loads without oscillation. The amplifier
provides a maximum load current, which is enough for
most programmable voltage reference applications.
Refer to Section 1.0 “Electrical Characteristics” for
the specifications of the output amplifier.
Note:
The internal band gap is designed to drive the resistor
ladder buffer.
If the internal band gap is selected, then the band gap
voltage source will drive the external VREF pins. The
VREF0 pin can source up to 1 mA of current without
affecting the DAC output specifications. The VREF1 pin
must be left unloaded in this mode. The voltage reference source can be independently selected on devices
with two DAC channels, but these restrictions apply:
Figure 5-5 shows a block diagram of the output driver
circuit.
VDD
PD1:PD0
• The VDD mode can be used without issues on any
channel.
• When the internal band gap is selected as the voltage
source, all the VREF pins are connected to its output.
The use of the Unbuffered mode is only possible on
VREF0, because it’s the only one that can be loaded.
• When using the Internal Band Gap mode on
Channel 0, Channel 1 must be put in Buffered
External VREF mode or VDD Reference mode and
the VREF1 pin must be left unloaded.
The resistance of the RRL is targeted to be 71 k
(10%), which means a minimum resistance of
63.9 k.
The band gap selection can be used across the VDD
voltages while maximizing the VOUT voltage ranges.
For VDD voltages below the Gain VBG voltage, the
output for the upper codes will be clipped to the VDD
voltage. Table 5-1 shows the maximum DAC register
code given device VDD and Gain bit setting.
5.5
2.7
1.8
DAC Gain
VDD
TABLE 5-1:
VOUT USING BAND GAP
Comment
FFh VOUT(max) = 1.214V
FFFh
3FFh
2
FFFh
3FFh
Gain
(1x or 2x)
FIGURE 5-5:
1
FFFh
3FFh
FFh VOUT(max) = 1.214V(3)
2
FFFh
3FFh
FFh VOUT(max) = 2.428V
1
FFFh
3FFh
FFh VOUT(max) = 1.214V
BBCh
2EFh
BBh 1.8V
Note 1: Without the VOUT pin voltage being clipped.
2: Recommended to use the Gain = 1 setting.
3: When VBG = 1.214V typical.
PD1:PD0
Output Driver Block Diagram.
Power-down logic also controls the output buffer
operation (see Section 5.5 “Power-Down Operation”
for additional information on power-down). In any of the
three Power-Down modes, the output amplifier is
powered down and its output becomes a high-impedance
to the VOUT pin.
5.3.1
a)
FFh VOUT(max) = 2.428V(3)
2(2)
VOUT
PROGRAMMABLE GAIN
The Gain options are:
(3)
1
DS20006666B-page 58
VW
The amplifier’s gain is controlled by the Gain (G)
Configuration bit (see Register 4-4) and the VRL
reference selection (see Register 4-2).
Max DAC Code(1)
12-Bit 10-Bit 8-Bit
The load resistance must be kept higher
than 2 k to maintain stability of the
analog output and have it meet electrical
specifications.
100 kΩ
USING AN EXTERNAL VREF
SOURCE IN BUFFERED MODE
1 kΩ
5.2.3
b)
Gain of 1, with either the VDD or VREF pin used
as the reference voltage.
Gain of 2, only when the VREF pin or the internal
band gap is used as the reference voltage. The
VREF pin voltage must be limited to VDD/2. When
the Reference Voltage Selection (VRL) is the
device’s VDD voltage, the Gx bit is ignored and a
gain of 1 is used.
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MCP47CXDX1/2
Table 5-2 shows the gain bit operation.
TABLE 5-2:
When Gain = 2 (VRL = VREF), if VREF > VDD/2, the VOUT
voltage is limited to VDD. So if VREF = VDD, the VOUT
voltage does not change for Volatile DAC register
values mid-scale and greater, since the output amplifier
is at full-scale output.
OUTPUT DRIVER GAIN
Gain Bit
Gain
0
1
1
2
Comment
The following events update the DAC register value,
and therefore, the analog Voltage Output (VOUT):
• Power-on Reset
• Brown-out Reset
• I2C write command (to Volatile registers) on the
rising edge of the last write command bit
• I2C General Call Reset command; the output is
updated with default POR data or MTP values
• I2C general call wake-up command; the output is
updated with default POR data or MTP values
Limits VREF pin voltages
relative to device VDD voltage.
The volatile G bit value can be modified by:
• POR Event
• BOR Event
• I2C Write Commands
• I2C General Call Reset Command
5.3.2
OUTPUT VOLTAGE
Next, the VOUT voltage starts driving to the new value
after the event has occurred.
The Volatile DAC register values, along with the
device’s Configuration bits, control the analog VOUT
voltage. The Volatile DAC register’s value is unsigned
binary. The formula for the output voltage is provided in
Equation 5-2. Examples of Volatile DAC register values
and the corresponding theoretical VOUT voltage for the
MCP47CXDX1/2 devices are shown in Table 5-6.
EQUATION 5-2:
5.3.3
STEP VOLTAGE (VS)
The step voltage depends on the device resolution and
the calculated output voltage range. One LSb is
defined as the ideal voltage difference between two
successive codes. The step voltage can easily be calculated by using Equation 5-3 (the DAC register value
is equal to ‘1’). Theoretical step voltages are shown in
Table 5-3 for several VREF voltages.
CALCULATING OUTPUT
VOLTAGE (VOUT)
V RL DAC Register Value
V OUT = ---------------------------------------------------------------------- Gain
# Resistor in Resistor Ladder
EQUATION 5-3:
Where:
VS CALCULATION
V RL
V S = ---------------------------------------------------------------------- Gain
# Resistor in Resistor Ladder
# Resistors in R-Ladder = 4096 (MCP47CXD2X)
1024 (MCP47CXD1X)
Where:
256 (MCP47CXD0X)
# Resistors in R-Ladder = 4096 (12-bit)
1024 (10-bit)
256 (8-bit)
TABLE 5-3:
Step
Voltage
VS
Note 1:
THEORETICAL STEP VOLTAGE (VS)(1)
VREF
5.0
2.7
1.8
1.5
1.0
1.22 mV
659 uV
439 uV
366 uV
244 uV
12-bit
4.88 mV
2.64 mV
1.76 mV
1.46 mV
977 uV
10-bit
19.5 mV
10.5 mV
7.03 mV
5.86 mV
3.91 mV
8-bit
When Gain = 1x, VFS = VRL and VZS = 0V.
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MCP47CXDX1/2
5.3.4
OUTPUT SLEW RATE
Figure 5-6 shows an example of the slew rate of the VOUT
pin. The slew rate can be affected by the characteristics
of the circuit connected to the VOUT pin.
VOUT
VOUT(B)
VOUT(A)
DACx = A
DACx = B
Time
V OUT B – V OUT A
Slew Rate = -------------------------------------------------T
FIGURE 5-6:
5.3.4.1
VOUT Pin Slew Rate.
Large Capacitive Load
With a larger capacitive load, the slew rate is
determined by two factors:
• The output buffer’s Short-Circuit Current (ISC)
• The VOUT pin’s external load
IOUT cannot exceed the output buffer’s Short-Circuit
Current (ISC), which fixes the output Buffer Slew Rate
(SRBUF). The voltage on the Capacitive Load (CL), VCL,
changes at a rate proportional to IOUT, which fixes a
Capacitive Load Slew Rate (SRCL).
The VCL voltage slew rate is limited to the slower of the
output buffer’s internally Set Slew Rate (SRBUF) and
the Capacitive Load Slew Rate (SRCL).
5.3.5
Therefore, when driving large capacitive loads with the
output buffer, a small Series Resistor (RISO) at the
output (see Figure 5-7) improves the output buffer’s
stability (feedback loop’s phase margin) by making the
output load resistive at higher frequencies. The
bandwidth will be generally lower than the bandwidth
with no capacitive load.
Small Capacitive Load
With a small capacitive load, the output buffer’s current
is not affected by the Capacitive Load (CL). However,
the VOUT pin’s voltage is not a step transition from one
output value (DAC register value) to the next output
value. The change of the VOUT voltage is limited by the
output buffer’s characteristics, so the VOUT pin voltage
will have a slope from the old voltage to the new voltage. This slope is fixed for the output buffer and is
referred to as the Buffer Slew Rate (SRBUF).
5.3.4.2
Driving large capacitive loads can cause stability
problems for voltage feedback output amplifiers. As the
load capacitance increases, the feedback loop’s phase
margin decreases and the closed-loop bandwidth is
reduced. This produces gain peaking in the frequency
response with overshoot and ringing in the step
response. That is, since the VOUT pin’s voltage does
not quickly follow the buffer’s input voltage (due to the
large capacitive load), the output buffer will overshoot
the desired target voltage. Once the driver detects this
overshoot, it compensates by forcing it to a voltage
below the target. This causes voltage ringing on the
VOUT pin.
VOUT
VW
RISO
RL
VCL
CL
Gain
FIGURE 5-7:
Circuit to Stabilize Output
Buffer for Large Capacitive Loads (CL).
The RISO resistor value for your circuit needs to be
selected. The resulting frequency response peaking
and step response overshoot for this RISO resistor
value must be verified on the bench. Modify the RISO’s
resistance value until the output characteristics meet
application requirements.
A method to evaluate the system’s performance is to
inject a step voltage on the VREF pin and observe the
VOUT pin’s characteristics.
Note:
Additional insight into circuit design for
driving capacitive loads can be found in
AN884, “Driving Capacitive Loads With
Op Amps” (DS00884).
DRIVING RESISTIVE AND
CAPACITIVE LOADS
The VOUT pin can drive up to 100 pF of capacitive load
in parallel with a 5 k resistive load (to meet electrical
specifications). VOUT drops slowly as the load resistance decreases after about 3.5 k. It is recommended
to use a load with RL greater than 2 k.
Refer to Section 2.0 “Typical Performance Curves” for
a detailed VOUT vs. resistive load characterization
graph.
DS20006666B-page 60
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MCP47CXDX1/2
5.4
Latch Pin (LAT)
The Latch pin controls when the Volatile DAC register
value is transferred to the DAC wiper. This is useful for
applications that need to synchronize the wiper(s)
updates to an external event, such as zero-crossing or
updates to the other wipers on the device. The LAT pin
is asynchronous to the serial interface operation.
Serial Shift Reg.
Register Address
Write Command
16 Clocks
Vol. DAC Register x
Transfer
LAT
Data
SYNC
(internal signal)
DAC Wiper x
When the LAT pin is high, transfers from the Volatile
DAC register to the DAC wiper are inhibited. The Volatile
DAC register value(s) can continue to be updated.
When the LAT pin is low, the Volatile DAC register
value is transferred to the DAC wiper.
Note:
This allows both the Volatile DAC0 and
DAC1 registers to be updated while the
LAT pin is high, and to have outputs
synchronously updated as the LAT pin is
driven low.
Figure 5-8 shows the interaction of the LAT pin and the
loading of the DAC Wiper x (from the Volatile DAC
Register x). The transfers are level-driven. If the LAT
pin is held low, the corresponding DAC wiper is
updated as soon as the Volatile DAC register value is
updated.
LAT SYNC
Transfer
Data
Comment
1
1
0
No Transfer
1
0
0
No Transfer
0
1
1
Vol. DAC Register x DAC Wiper x
0
0
0
No Transfer
FIGURE 5-8:
LAT and DAC Interaction.
The LAT pin allows the DAC wiper to be updated to an
external event and to have multiple DAC
channels/devices update at a common event.
Since the DAC Wiper x is updated from the Volatile
DAC Register x, all DACs that are associated with a
given LAT pin can be updated synchronously.
If the application does not require synchronization, this
signal must be tied low.
Figure 5-9 shows two cases of using the LAT pin to
control when the Wiper register is updated relative to
the value of a sine wave signal.
Case 1: Zero-Crossing of Sine Wave to Update the Volatile DAC0 Register (using LAT pin)
Case 2: Fixed-Point Crossing of Sine Wave to Update the Volatile DAC0 Register (using LAT pin)
Indicates where LAT pin pulses are active (Volatile DAC0 register updated)
FIGURE 5-9:
Example Use of LAT Pin Operation.
2022 Microchip Technology Inc. and its subsidiaries
DS20006666B-page 61
MCP47CXDX1/2
5.5
Power-Down Operation
To allow the application to conserve power when DAC
operation is not required, three Power-Down modes
are available. On devices with multiple DACs, each
DAC’s Power-Down mode is individually controllable.
All Power-Down modes do the following:
• Turn off most of the DAC module’s internal circuits
• Op amp output becomes high-impedance to the
VOUT pin
• Retain the value of the Volatile DAC register and
Configuration bits
• VOUT pin is switched to one of the two resistive
pull-downs:
- 100 k (typical)
- 1 k (typical)
• Op amp is powered down and the VOUT pin
becomes high-impedance
PD0
0
0
1
1
0
1
0
1
POWER-DOWN BITS AND
OUTPUT RESISTIVE LOAD
Function
Normal operation
1 k resistor to ground
100 k resistor to ground
Open circuit
Table 5-5 shows the current sources for the DAC based
on the selected source of the DAC’s reference voltage
and if the device is in normal operating mode or one of
the Power-Down modes.
DAC CURRENT SOURCES
PDxB:xA = 00,
VREFxB:xA =
PDxB:xA 00,
VREFxB:xA =
00 01
10
11
00
01
10
Output Op Amp
Y
Y
Y
Y
N
N
N
N
Resistor Ladder
Y
Y
N(1)
Y
N
N
N(1)
N
VREF Selection Buffer N
Y
N
Y
N
N
N
N
Band Gap
Y
N
N
N
11
N(2) Y(2) N(2) N(2)
Note 1: The current is sourced from the VREF pin, not the
device VDD.
2: If DAC0 and DAC1 are in one of the Power-Down
modes, MTP write operations are not recommended.
DS20006666B-page 62
EXITING POWER-DOWN
The following events change the PD1:PD0 bits to ‘00’,
and therefore, exit the Power-Down mode. These are:
When the device exits Power-Down mode, the
following occurs:
In any of the Power-Down modes, where the VOUT pin
is not externally connected (sinking or sourcing current), as the number of DACs increases, the device’s
power-down current will also increase.
Device VDD Current
Source
5.5.1
• Any I2C Write Command, where the PD1:PD0 bits
are ‘00’
• I2C General Call Wake-up Command
• I2C General Call Reset Command
There is a delay (TPDD) between the PD1:PD0 bits
changing from ‘00’ to either ‘01’, ‘10’ or ‘11’ and the
op amp no longer driving the VOUT output, and the
pull-down resistors’ sinking current.
TABLE 5-5:
Note 1: The I2C serial interface circuit is not
affected by the Power-Down mode. This
circuit remains active in order to receive
any command that might come from the
I2C Host device.
2: A General Call Reset will do the POR
event sequence, except that the MTP
shadow memory values will be transfered
to the Volatile Memory registers.
The Power-Down Configuration bits (PD1:PD0) control
the power-down operation (Table 5-4).
PD1
Section 7.0 “Device Commands” describes the I2C
commands for writing the power-down bits. The
commands that can update the volatile PD1:PD0 bits are:
• Write
• General Call Reset
• General Call Wake-up
Depending on the selected Power-Down mode, the
following will occur:
TABLE 5-4:
The power-down bits are modified by using a write
command to the Volatile Power-Down register, or a POR
event, which transfers the Nonvolatile Power-Down
register to the Volatile Power-Down register.
• Disabled internal circuits are turned on
• Resistor ladder is connected to the selected
Reference Voltage (VRL)
• Selected pull-down resistor is disconnected
• The VOUT output is driven to the voltage
represented by the Volatile DAC register’s value
and Configuration bits
The DAC Wiper register and DAC wiper value may be
different due to the DAC Wiper register being modified
while the LAT pin was driven to (and remaining at) VIH.
The VOUT output signal requires time as these circuits
are powered up and the output voltage is driven to the
specified value, as determined by the Volatile DAC
register and Configuration bits.
Note:
Since the op amp and resistor ladder were
powered off (0V), the op amp’s Input
Voltage (VW) can be considered as 0V.
There is a delay (TPDE) between the
PD1:PD0 bits updating to ‘00’ and the
op amp driving the VOUT output. The
op amp’s settling time (from 0V) needs to
be taken into account to ensure the VOUT
voltage reflects the selected value.
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TABLE 5-6:
Device
DAC INPUT CODE VS. CALCULATED ANALOG OUTPUT (VOUT) (VDD = 5.0V)
Volatile DAC
Register Value
1111 1111 1111
LSb
Equation
µV
5.0V
5.0V/4096
1,220.7
1x
VRL (4095/4096) 1
4.998779
2.5V
2.5V/4096
610.4
1x
VRL (4095/4096) 1
2.499390
VRL
MCP47CVD2X (12-bit)
0011 1111 1111
0000 0000 0000
MCP47CVD1X (10-bit)
11 1111 1111
01 1111 1111
00 1111 1111
00 0000 0000
MCP47CVD0X (8-bit)
1111 1111
0111 1111
0011 1111
0000 0000
Note 1:
2:
3:
5.0V
5.0V/4096
1,220.7
2.5V
2.5V/4096
610.4
5.0V
5.0V/4096
1,220.7
2.5V
2.5V/4096
610.4
5.0V
5.0V/4096
1,220.7
2.5V
2.5V/4096
610.4
5.0V
5.0V/1024
4,882.8
2.5V
2.5V/1024
2,441.4
5.0V
5.0V/1024
4,882.8
2.5V
2.5V/1024
2,441.4
5.0V
5.0V/1024
4,882.8
2.5V
2.5V/1024
2,441.4
5.0V
5.0V/1024
4,882.8
2.5V
2.5V/1024
2,441.4
5.0V
5.0V/256
19,531.3
2.5V
2.5V/256
9,765.6
5.0V
5.0V/256
19,531.3
2.5V
2.5V/256
9,765.6
5.0V
5.0V/256
19,531.3
2.5V
2.5V/256
9,765.6
5.0V
5.0V/256
19,531.3
2.5V
2.5V/256
9,765.6
(2)
Equation
V
VRL (4095/4096) 2)
4.998779
1x
VRL (2047/4096) 1)
2.498779
1x
VRL (2047/4096) 1)
1.249390
2x
0111 1111 1111
VOUT(3)
Gain
Selection(2)
(1)
2x(2)
VRL (2047/4096) 2)
2.498779
1x
VRL (1023/4096) 1)
1.248779
1x
VRL (1023/4096) 1)
0.624390
2x(2)
VRL (1023/4096) 2)
1.248779
1x
VRL (0/4096) * 1)
0
1x
VRL (0/4096) * 1)
0
2x(2)
VRL (0/4096) * 2)
0
1x
VRL (1023/1024) 1
4.995117
1x
VRL (1023/1024) 1
2.497559
2x(2)
VRL (1023/1024) 2
4.995117
1x
VRL (511/1024) 1
2.495117
1.247559
1x
VRL (511/1024) 1
2x(2)
VRL (511/1024) 2
2.495117
1x
VRL (255/1024) 1
1.245117
1x
VRL (255/1024) 1
0.622559
2x(2)
VRL (255/1024) 2
1.245117
1x
VRL (0/1024) 1
0
1x
VRL (0/1024) 1
0
2x(2)
VRL (0/1024) 1
0
1x
VRL (255/256) 1
4.980469
2.490234
1x
VRL (255/256) 1
2x(2)
VRL (255/256) 2
4.980469
1x
VRL (127/256) 1
2.480469
1.240234
1x
VRL (127/256) 1
2x(2)
VRL (127/256) 2
2.480469
1x
VRL (63/256) 1
1.230469
1x
VRL (63/256) 1
0.615234
2x(2)
VRL (63/256) 2
1.230469
1x
VRL (0/256) 1
0
1x
VRL (0/256) 1
0
2x(2)
VRL (0/256) 2
0
VRL is the resistor ladder’s reference voltage. It is independent of the VREF1:VREF0 selection.
Gain selection of 2x (Gx = 1) requires the voltage reference source to come from the VREF pin
(VREF1:VREF0 = 10 or 11) and requires VREF pin voltage (or VRL) ≤ VDD/2 or from the internal band gap
(VREF1:VREF0 = 01).
These theoretical calculations do not take into account the offset, gain and nonlinearity errors.
2022 Microchip Technology Inc. and its subsidiaries
DS20006666B-page 63
MCP47CXDX1/2
NOTES:
DS20006666B-page 64
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MCP47CXDX1/2
6.0
I2C SERIAL INTERFACE
MODULE
The MCP47CXDX1/2’s I2C serial interface module
supports the I2C serial protocol specification. This I2C
interface is a two-wire interface (clock and data).
Figure 6-1 shows a typical I2C interface connection.
The I2C specification only defines the field types,
lengths, timings, etc., of a frame. The frame content
defines the behavior of the device. The frame content
(commands) for the MCP47CXDX1/2 is defined in
Section 7.0 “Device Commands”.
An overview of the I2C protocol is available in
Appendix B: “I2C Serial Interface”.
6.2
The I2C interface specifies different communication bit
rates. These are referred to as Standard, Fast or HighSpeed modes. The MCP47CXDX1/2 supports these
three modes. The clock rates (bit rate) of these modes
are:
• Standard mode: Up to 100 kHz (kbit/s)
• Fast mode: Up to 400 kHz (kbit/s)
• High-Speed mode (HS mode): Up to 3.4 MHz
(Mbit/s)
A description on how to enter High-Speed mode is
described in Section 6.8 “Slope Control”.
6.3
Typical I2C Interface Connections
MCP47CVDXX
(Client)
Host
Controller
6.4
SDA
SDA
The memory address is the 5-bit value that specifies
the location in the device’s memory that the specified
command will operate on.
Typical I2C Interface.
Overview
This section discusses some of the specific characteristics of the MCP47CXDX1/2 devices’ I2C serial interface module. This is to assist in the development of
user application.
The following sections discuss some of these
device-specific characteristics.
Interface Pins (SCL and SDA)
Communication Data Rates
POR/BOR
Device Memory Address
General Call Commands
Device I2C Client Addressing
Slope Control
6.1.1
On a POR/BOR event, the I2C serial interface module
state machine is reset, which includes forcing the
device’s Memory Address Pointer to 00h.
SCL
FIGURE 6-1:
•
•
•
•
•
•
•
POR/BOR
SCL
Other Devices
6.1
Communication Data Rates
INTERFACE PINS (SCL AND SDA)
The MCP47CXDX1/2 I2C module SCL pin does not
generate the serial clock since the device operates in
Client mode. Also, the MCP47CXDX1/2 will not stretch
the clock signal (SCL) since memory read access
occurs fast enough.
Device Memory Address
On a POR/BOR event, the device’s Memory Address
Pointer is forced to 00h.
The MCP47CXDX1/2 retains the last received “Device
Memory Address”. That is, the MCP47CXDX1/2 does
not “corrupt” the “device memory address” after
Repeated Start or Stop conditions.
6.5
General Call Commands
The general call commands utilize the I2C specification
reserved general call command address and command
codes. The MCP47CXDX1/2 also implements a
nonstandard general call command.
The general call commands are:
• General Call Reset
• General Call Wake-up (MCP47CXDX1/2 defined)
The General Call Wake-up command will cause all the
MCP47CXDX1/2 devices to exit their power-down
state.
6.6
Multi-Host Systems
The MCP47CXDX1/2 is not a Host device (generates
the interface clock), but it can be used in Multi-Host
applications.
The MCP47CXDX1/2 I2C module implements slope
control on the SDA pin output driver.
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MCP47CXDX1/2
Device I2C Client Addressing
6.7
The address byte is the first byte received following the
Start (or Repeated Start) condition from the Host device
(see Figure 6-2). For nonvolatile devices, the seven bits of
the I2C Client address are user-programmable. The
default address is ‘110 0000’. If the address pins are
present on the specific package, the lower two bits of
the address are determined by the state of the A1 and
A0 pins.
Note:
Address bits, A6:A0, are MTP and can
be programmed during the user’s
manufacturing flow.
For volatile devices (MCP47CVDXX), the I2C Client
address bits, A6:A0, are fixed (‘110 0000’). The user
still has Client address programmability with the A1:A0
address pins (if available on the package).
Acknowledge Bit
Start Bit
Read/Write Bit
Table 6-1 shows the four standard orderable I2C Client
addresses and their respective device order codes.
TABLE 6-1:
Default
7-Bit I2C
Address
‘1100000’
0
A6 A5 A4
Note 1:
0
0
0
A3 A2 A1 A0
Default
Factory
Address
(Note 1)
Address bits (A6:A0) can be
programmed by the user
(MCP47CMDXX devices). Bits A1 and
A0 are determined by either the MTP
bits or the A0 and A1 pin values if
present on the package.
FIGURE 6-2:
I2C Control Byte.
DS20006666B-page 66
MCP47CXDX1/2E/XX
Y
Y
N
MCP47CXDX1/2TE/XX
Y
Y
Y
CUSTOM I2C CLIENT ADDRESS
OPTIONS
Custom I2C Client address options can be requested.
Users can request the custom I2C Client address via
the Nonstandard Customer Authorization Request
(NSCAR) process.
R/W ACK
0
NV
6.7.1
Non-Recurring Engineering (NRE) charges
and minimum ordering requirements for
custom orders. Please contact Microchip
sales for additional information.
A custom device will be assigned custom
device marking.
Client Address (7 bits)
1
Memory
Nonvolatile devices’ I2C Client address can
be reprogrammed by the end user.
Address Byte
1
VOL
Tape
and
Reel
Device Order
Code(1)
Note 1:
Note:
Client Address
I2C ADDRESS/ORDER CODE
6.8
Slope Control
The slope control on the SDA output is different
between the Fast/Standard Speed and the High-Speed
Clock modes of the interface.
6.9
Pulse Gobbler
The pulse gobbler on the SCL pin is automatically
adjusted to suppress spikes
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