MCP48FXBX4/8
8/10/12-Bit Quad/Octal Voltage Output, 6 LSb INL
Digital-to-Analog Converters with SPI Interface
2020 Microchip Technology Inc.
20-Lead VQFN
5x5 mm Quad
17 SDI
16 SCK
18 LAT0/HVC
19 LAT1
20 VDD
MCP48FXBX4
CS 1
15 SDO
VREF0 2
14 VREF1
VOUT0 3
21 EP
13 VOUT1
(1)
VOUT2 4
12 VOUT3
NC 5
LAT1 1
VDD 2
MCP48FXBX4
20-Lead TSSOP
Quad
20
19
18
17
16
15
14
13
12
11
CS 3
VREF0 4
VOUT0 5
VOUT2 6
NC 7
NC 8
VSS 9
20-Lead VQFN
5x5 mm Octal
LAT0/HVC
SDI
SCK
SDO
VREF1
VOUT1
VOUT3
NC
NC
NC
17 SDI
16 SCK
18 LAT0/HVC
19 LAT1
NC 10
MCP48FXBX8
NC 10
NC 9
NC 8
NC 6
VSS 7
11 NC
20 VDD
CS 1
VREF0 2
VOUT0 3
VOUT2 4
15 SDO
14 VREF1
21
EP(1)
13 VOUT1
12 VOUT3
LAT1 1
VDD 2
MCP48FXBX8
20-Lead TSSOP
Octal
CS 3
VREF0 4
VOUT0 5
VOUT2 6
VOUT4 7
VOUT6 8
VSS 9
NC 10
VOUT7 10
11 VOUT5
NC 9
VOUT4 5
NC 8
• Operating Voltage Range:
- 2.7V to 5.5V – Full specifications
- 1.8V to 2.7V – Reduced device specifications
• Output Voltage Resolutions:
- 8-bit: MCP48FXB0X (256 steps)
- 10-bit: MCP48FXB1X (1024 steps)
- 12-bit: MCP48FXB2X (4096 steps)
• Rail-to-Rail Output
• Fast Settling Time of 7.8 µs (Typical)
• DAC Voltage Reference Source Options:
- Device VDD
- External VREF pin (buffered or unbuffered)
- Internal band gap (1.22V typical)
• Output Gain Options:
- 1x (unity)
- 2x (available when not using internal VDD as
voltage source)
• Nonvolatile Memory (EEPROM) Option:
- User-programmable Power-on Reset
(POR)/Brown-out Reset (BOR) output setting
and device Configuration bits recall
- Auto-recall of saved DAC register setting
- Auto-recall of saved device configuration
(voltage reference, gain, power-down)
• Power-on/Brown-out Reset Protection
• Power-Down Modes:
- Disconnects output buffer (high-impedance)
- Selection of VOUT pull-down resistors
(125 k or 1 k)
• Low-Power Consumption:
- Normal operation: VDD, VI > VPP on HV Pins) ........................................................................ ±20 mA
Output Clamp Current, IOK (VO < 0 or VO > VDD) ................................................................................................. ±20 mA
Maximum Current out of the VSS Pin (Quad) .........................................................................................................150 mA
(Octal)..........................................................................................................150 mA
Maximum Current into the VDD Pin (Quad) .........................................................................................................150 mA
(Octal)..........................................................................................................150 mA
Maximum Current Sourced by the VOUT Pin...........................................................................................................20 mA
Maximum Current Sunk by the VOUT Pin................................................................................................................20 mA
Maximum Current Sunk by the VREF Pin ...............................................................................................................125 µA
Maximum Input Current Source/Sunk by the SDI, SCK and CS Pins ......................................................................2 mA
Maximum Output Current Sunk by the SDO Output Pin ........................................................................................25 mA
Total Power Dissipation(1) ....................................................................................................................................400 mW
Package Power Dissipation (TA = +50°C, TJ = +150°C)
20-Lead TSSOP ......................................................................................................................................1300 mW
20-Lead VQFN (5 x 5 mm, ML)...............................................................................................................2800 mW
ESD Protection on all Pins±6 kV (HBM)
±400V (MM)
±2 kV (CDM)
Latch-up (per JEDEC® JESD78A) at +125°C .................................................................................................... ±100 mA
Storage Temperature ..............................................................................................................................-65°C to +150°C
Ambient Temperature with Power Applied .............................................................................................-55°C to +125°C
Soldering Temperature of Leads (10 seconds) ..................................................................................................... +300°C
Maximum Junction Temperature (TJ) .................................................................................................................... +150°C
† Notice: Stresses above those listed under “Maximum Ratings” may cause permanent damage to the device. This
is a stress rating only and functional operation of the device at those or any other conditions above those indicated
in the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended
periods may affect device reliability.
Note 1: Power dissipation is calculated as follows:
PDIS = VDD × {IDD – IOH} + {(VDD – VOH) × IOH} + (VOL × IOL)
2020 Microchip Technology Inc.
DS20006362A-page 5
MCP48FXBX4/8
DC CHARACTERISTICS
Standard Operating Conditions (unless otherwise specified):
Operating Temperature: -40°C TA +125°C (Extended).
All parameters apply across the specified operating ranges unless noted.
VDD = +2.7V to 5.5V, VREF = +2.048V to VDD, VSS = 0V, Gx = 0, RL = 5 k from VOUT to GND, CL = 100 pF.
Typical specifications represent values for VDD = 5.5V, TA = +25°C.
Parameters
Supply Voltage
Sym.
Min.
VDD
2.7
—
5.5
V
1.8
—
2.7
V
Serial interface operational,
DAC operation with reduced analog
specifications
—
—
1.7
V
RAM retention voltage: (VRAM) < VPOR,
VDD voltages greater than the VPOR/BOR
limit ensure that the device is out of
Reset
VDD Voltage
VPOR/BOR
(Rising) to Ensure Device
Power-on Reset
Typ.
Max.
Conditions
VDD Rise Rate to Ensure
Power-on Reset
VDDRR
High-Voltage Commands
Voltage Range (HVC Pin)
VHV
VSS
—
12.5
V
The HVC pin will be at one of the three
input levels (VIL, VIH or VIHH)(1)
High-Voltage
Input Entry Voltage
VIHHEN
9.0
—
—
V
Threshold for entry into WiperLock™
technology
High-Voltage
Input Exit Voltage
VIHHEX
—
—
VDD + 0.8V
V
Note 1
Note 1:
3:
Note 3
Units
V/ms
This parameter is ensured by design.
POR/BOR voltage trip point is not slope dependent. Hysteresis implemented with time delay.
DS20006362A-page 6
2020 Microchip Technology Inc.
MCP48FXBX4/8
DC CHARACTERISTICS (CONTINUED)
Standard Operating Conditions (unless otherwise specified):
Operating Temperature: -40°C TA +125°C (Extended).
All parameters apply across the specified operating ranges unless noted.
VDD = +2.7V to 5.5V, VREF = +2.048V to VDD, VSS = 0V, Gx = 0, RL = 5 k from VOUT to GND, CL = 100 pF.
Typical specifications represent values for VDD = 5.5V, TA = +25°C.
Parameters
Sym.
Min.
Typ.
Max.
Units
Supply Current
IDD
—
—
1.0
mA
—
—
1.7
mA
—
—
2.6
mA
—
—
1.6
mA
Power-Down
Current
Note 1:
4:
5:
IDDP
Conditions
Quad
1 MHz(1)
—
—
2.3
mA
Serial interface active (not
10 MHz(1) High-Voltage Command),(4)
VRnB:VRnA = All Modes ,
20 MHz
VOUT is unloaded, VDD = 5.5V,
1 MHz(1) Volatile DAC Register = Midscale
10 MHz(1)
—
—
3.2
mA
20 MHz
—
—
0.85
mA
Quad
—
—
1.6
mA
Octal
—
—
2.2
mA
Quad
—
—
2.7
mA
Octal
—
560
700
µA
Quad
—
1100
1300
µA
Octal
—
0.68
3.8
µA
PDnB:PDnA = 01(5), VOUT not connected
Octal
Serial interface inactive(1) (not
High-Voltage Command),
VRnB:VRnA = All Modes, SCK = SDI = VSS,
VOUT is unloaded,
Volatile DAC Register = Midscale
EE write current, VREF = VDD = 5.5V
(after write, serial interface is inactive),
write 0x7FF to nonvolatile DAC0 (address
10h), VOUT pins are unloaded
HVC = 12.5V (High-Voltage Command),
serial interface inactive, VREF = VDD = 5.5V,
LAT/HVC = VIHH, DAC Registers = Midscale,
VOUT pins are unloaded
This parameter is ensured by characterization.
Supply current is independent of current through the resistor ladder in mode VRnB:VRnA = 10.
The PDnB:PDnA = 00, 10 and 11 configurations should have the same current.
2020 Microchip Technology Inc.
DS20006362A-page 7
MCP48FXBX4/8
DC CHARACTERISTICS (CONTINUED)
Standard Operating Conditions (unless otherwise specified):
Operating Temperature: -40°C TA +125°C (Extended).
All parameters apply across the specified operating ranges unless noted.
VDD = +2.7V to 5.5V, VREF = +2.048V to VDD, VSS = 0V, Gx = 0, RL = 5 k from VOUT to GND, CL = 100 pF.
Typical specifications represent values for VDD = 5.5V, TA = +25°C.
Parameters
Sym.
Min.
Typ.
Max.
Units
Resistor Ladder
Resistance
RL
100
140
180
k
Resolution; # of
Resistors and # of Taps
(see B.1 “Resolution”)
N
Nominal VOUT Match(11)
|VOUT – VOUTMEAN|
/VOUTMEAN
—
0.5
1.0
%
2.7V VDD 5.5V(2)
—
—
1.2
%
1.8V(2)
VOUT/T
—
15
—
VREF
VSS
—
VDD
VOUT Temperature
Coefficient (see B.19
“VOUT Temperature
Coefficient”)
VREF Pin Input Voltage
Range
Conditions
VRnB:VRnA = 10,
VREF = VDD(6)
256
Taps
8-bit No missing codes
1024
Taps
10-bit No missing codes
4096
Taps
12-bit No missing codes
ppm/°C Code = Midscale
(7Fh, 1FFh or 7FFh)
V
1.8V VDD 5.5V(1)
Note 1:
2:
6:
This parameter is ensured by design.
This parameter is ensured by characterization.
Resistance is defined as the resistance between the VREF pin (mode VRnB:VRnA = 10) to VSS pin. For
octal-channel devices (MCP48FXBX8), this is the effective resistance of each resistor ladder. The
resistance measurement is one of the two resistor ladders measured in parallel.
11: Variation of one output voltage to mean output voltage.
DS20006362A-page 8
2020 Microchip Technology Inc.
MCP48FXBX4/8
DC CHARACTERISTICS (CONTINUED)
Standard Operating Conditions (unless otherwise specified):
Operating Temperature: -40°C TA +125°C (Extended).
All parameters apply across the specified operating ranges unless noted.
VDD = +2.7V to 5.5V, VREF = +2.048V to VDD, VSS = 0V, Gx = 0, RL = 5 k from VOUT to GND, CL = 100 pF.
Typical specifications represent values for VDD = 5.5V, TA = +25°C.
Parameters
Sym.
Min.
Typ.
Max.
Units
Zero-Scale Error;
Code = 000h
(see B.5 “Zero-Scale
Error (EZS)”)
EZS
—
—
0.75
LSb
8-bit
VRnB:VRnA = 10, Gx = 0,
VREF = VDD, no load
—
—
3
LSb
10-bit
VRnB:VRnA = 10, Gx = 0,
VREF = VDD, no load
—
—
12
LSb
12-bit
VRnB:VRnA = 10, Gx = 0,
VREF = VDD, no load
Full-Scale Error (see
B.4 “Full-Scale Error
(EFS)”)
Offset Error
(see B.7 “Offset
Error (EOS)”)
Offset Voltage
Temperature
Coefficient
Note 1:
EFS
Conditions
See Section 2.0 “Typical
Performance Curves”(1)
LSb
VRnB:VRnA = 11, Gx = 0, Gx = 1,
VREF = 0.5 × VDD = 2.7, no load
See Section 2.0 “Typical
Performance Curves”(1)
LSb
VRnB:VRnA = 10, Gx = 0, Gx = 1,
VREF = VDD/2, VREF = VDD,
VDD = 2.7-5.5V, no load
See Section 2.0 “Typical
Performance Curves”(1)
LSb
VRnB:VRnA = 10, Gx = 0, Gx= 1,
VREF = VDD/2, VREF = VDD,
VDD = 2.7-5.5V, no load
See Section 2.0 “Typical
Performance Curves”(1)
LSb
VRnB:VRnA = 00, Gx = 0,
VREF = VDD = 2.7-5.5V, no load
—
—
4.5
LSb
8-bit
VRnB:VRnA = 10, Gx = 0,
VREF = VDD, no load
—
—
18
LSb
10-bit
VRnB:VRnA = 10, Gx = 0,
VREF = VDD, no load
—
—
70
LSb
12-bit
VRnB:VRnA = 10, Gx = 0,
VREF = VDD, no load
See Section 2.0 “Typical
Performance Curves”(1)
LSb
VRnB:VRnA = 11, Gx = 0, Gx = 1,
VREF = 0.5 × VDD = 2.7, no load
See Section 2.0 “Typical
Performance Curves”(1)
LSb
VRnB:VRnA = 10, Gx = 0, Gx = 1,
VREF = VDD/2, VREF = VDD,
VDD = 2.7-5.5V, no load
See Section 2.0 “Typical
Performance Curves”(1)
LSb
VRnB:VRnA = 10, Gx = 0, Gx = 1,
VREF = VDD/2, VREF = VDD,
VDD = 2.7-5.5V, no load
See Section 2.0 “Typical
Performance Curves”(1)
LSb
VRnB:VRnA = 00, Gx = 0,
VREF = VDD = 2.7-5.5V, no load
EOS
-15
±1.5
+15
mV
VOSTC
—
±10
—
µV/°C
VRnB:VRnA = 00, Gx = 0, no load
This parameter is ensured by characterization.
2020 Microchip Technology Inc.
DS20006362A-page 9
MCP48FXBX4/8
DC CHARACTERISTICS (CONTINUED)
Standard Operating Conditions (unless otherwise specified):
Operating Temperature: -40°C TA +125°C (Extended).
All parameters apply across the specified operating ranges unless noted.
VDD = +2.7V to 5.5V, VREF = +2.048V to VDD, VSS = 0V, Gx = 0, RL = 5 k from VOUT to GND, CL = 100 pF.
Typical specifications represent values for VDD = 5.5V, TA = +25°C.
Parameters
Gain Error
(see B.9 “Gain Error
(EG)”)(8)
Sym.
Min.
Typ.
Max.
Units
Conditions
EG
-1.0
±0.1
+1.0
% of
FSR
8-bit
Code = 250, no load,
VRnB:VRnA = 00, Gx = 0
-1.0
±0.1
+1.0
% of
FSR
10-bit
Code = 1000, no load,
VRnB:VRnA = 00, Gx = 0
-1.0
±0.1
+1.0
% of
FSR
12-bit
Code = 4000, no load,
VRnB:VRnA = 00, Gx = 0
Gain Error Drift (see
B.10 “Gain Error Drift
(EGD)”)
G/°C
—
-3
—
ppm/°C
Total Unadjusted Error
(see B.6 “Total
Unadjusted Error
(ET)”)(2)
ET
-2.5
—
+0.5
LSb
8-bit
VRnB:VRnA = 10, Gx = 0,
VREF = VDD, no load
-10.0
—
+2.0
LSb
10-bit
VRnB:VRnA = 10, Gx = 0,
VREF = VDD, no load
-40.0
—
+8.0
LSb
12-bit
VRnB:VRnA = 10, Gx = 0,
VREF = VDD, no load
Note 1:
See Section 2.0 “Typical
Performance Curves”(1)
VRnB:VRnA = 11, Gx = 0, Gx = 1,
VREF = 0.5 × VDD = 2.7, no load
See Section 2.0 “Typical
Performance Curves”(1)
VRnB:VRnA = 10, Gx = 0, Gx = 1,
VREF = VDD/2, VREF = VDD,
VDD = 2.7-5.5V, no load
See Section 2.0 “Typical
Performance Curves”(1)
VRnB:VRnA = 10, Gx = 0, Gx = 1,
VREF = VDD/2, VREF = VDD,
VDD = 2.7-5.5V, no load
See Section 2.0 “Typical
Performance Curves”(1)
VRnB:VRnA = 00, Gx = 0,
VREF = VDD = 2.7-5.5V, no load
This parameter is ensured by characterization.
DS20006362A-page 10
2020 Microchip Technology Inc.
MCP48FXBX4/8
DC CHARACTERISTICS (CONTINUED)
Standard Operating Conditions (unless otherwise specified):
Operating Temperature: -40°C TA +125°C (Extended).
All parameters apply across the specified operating ranges unless noted.
VDD = +2.7V to 5.5V, VREF = +2.048V to VDD, VSS = 0V, Gx = 0, RL = 5 k from VOUT to GND, CL = 100 pF.
Typical specifications represent values for VDD = 5.5V, TA = +25°C.
Parameters
Sym.
Min.
Typ.
Max.
Units
Conditions
Integral Nonlinearity
(see B.11 “Integral
Nonlinearity
(INL)”)(7,10)
INL
-0.5
±0.1
+0.5
LSb
8-bit
-1.5
±0.4
+1.5
LSb
10-bit VRnB:VRnA = 10, Gx = 0,
VREF = VDD, no load
-6
±1.5
+6
LSb
12-bit VRnB:VRnA = 10, Gx = 0,
VREF = VDD, no load
VRnB:VRnA = 10, Gx = 0,
VREF = VDD, no load
See Section 2.0 “Typical
Performance Curves”(1)
LSb
VRnB:VRnA = 11, Gx = 0, Gx = 1,
VREF = 0.5 × VDD = 2.7, no load
See Section 2.0 “Typical
Performance Curves”(1)
LSb
VRnB:VRnA = 10, Gx = 0, Gx = 1,
VREF = VDD/2, VREF = VDD,
VDD = 2.7-5.5V, no load
See Section 2.0 “Typical
Performance Curves”(1)
LSb
VRnB:VRnA = 10, Gx = 0, Gx = 1,
VREF = VDD/2, VREF = VDD,
VDD = 2.7-5.5V, no load
See Section 2.0 “Typical
Performance Curves”(1)
LSb
VRnB:VRnA = 00, Gx = 0,
VREF = VDD = 2.7-5.5V, no load
Note 1: This parameter is ensured by characterization.
7: INL and DNL are measured at VOUT with VRL = VDD (VRnB:VRnA = 00).
10: Code range is dependent on resolution: 8-bit, codes 6 to 250; 10-bit, codes 25 to 1000; 12-bit,
100 to 4000.
2020 Microchip Technology Inc.
DS20006362A-page 11
MCP48FXBX4/8
DC CHARACTERISTICS (CONTINUED)
Standard Operating Conditions (unless otherwise specified):
Operating Temperature: -40°C TA +125°C (Extended).
All parameters apply across the specified operating ranges unless noted.
VDD = +2.7V to 5.5V, VREF = +2.048V to VDD, VSS = 0V, Gx = 0, RL = 5 k from VOUT to GND, CL = 100 pF.
Typical specifications represent values for VDD = 5.5V, TA = +25°C.
Parameters
Sym.
Min.
Typ.
Max.
Units
Conditions
Differential Nonlinearity
(see B.12
“Differential
Nonlinearity
(DNL)”)(7,10)
DNL
-0.25
±0.0125
+0.25
LSb
8-bit
-0.5
±0.05
+0.5
LSb
10-bit VRnB:VRnA = 10, Gx = 0,
VREF = VDD, no load
-1.0
±0.2
+1.0
LSb
12-bit VRnB:VRnA = 10, Gx = 0,
VREF = VDD, no load
See Section 2.0 “Typical
Performance Curves”(1)
LSb
VRnB:VRnA = 11, Gx = 0, Gx = 1,
VREF = 0.5 × VDD = 2.7, no load
See Section 2.0 “Typical
Performance Curves”(1)
LSb
VRnB:VRnA = 10, Gx = 0, Gx = 1,
VREF = VDD/2, VREF = VDD,
VDD = 2.7-5.5V, no load
See Section 2.0 “Typical
Performance Curves”(1)
LSb
VRnB:VRnA = 10, Gx = 0, Gx = 1,
VREF = VDD/2, VREF = VDD,
VDD = 2.7-5.5V, no load
See Section 2.0 “Typical
Performance Curves”(1)
LSb
VRnB:VRnA = 00, Gx = 0,
VREF = VDD = 2.7-5.5V, no load
VRnB:VRnA = 10, Gx = 0,
VREF = VDD, no load
Note 1: This parameter is ensured by characterization.
7: INL and DNL are measured at VOUT with VRL = VDD (VRnB:VRnA = 00).
10: Code range is dependent on resolution: 8-bit, codes 6 to 250; 10-bit, codes 25 to 1000; 12-bit,
100 to 4000.
DS20006362A-page 12
2020 Microchip Technology Inc.
MCP48FXBX4/8
DC CHARACTERISTICS (CONTINUED)
Standard Operating Conditions (unless otherwise specified):
Operating Temperature: -40°C TA +125°C (Extended).
All parameters apply across the specified operating ranges unless noted.
VDD = +2.7V to 5.5V, VREF = +2.048V to VDD, VSS = 0V, Gx = 0, RL = 5 k from VOUT to GND, CL = 100 pF.
Typical specifications represent values for VDD = 5.5V, TA = +25°C.
Parameters
Sym.
Min.
Typ.
Max.
Units
Conditions
-3 dB Bandwidth
(see B.16 “-3 dB
Bandwidth”)
BW
—
86.5
—
kHz
VREF = 2.048V ±0.1V,
VRnB:VRnA = 10, Gx = 0
—
67.7
—
kHz
VREF = 2.048V ±0.1V,
VRnB:VRnA = 10, Gx = 1
Output Amplifier
Minimum Output
Voltage
VOUT(MIN)
—
0.01
—
V
1.8V VDD 5.5V,
output amplifier’s minimum drive
Maximum Output
Voltage
VOUT(MAX)
—
VDD – 0.016
—
V
1.8V VDD 5.5V,
output amplifier’s maximum drive
PM
—
58
—
°C
CL = 400 pF, RL =
SR
—
0.44
—
V/µs
RL = 5 k
ISC
3
9
22
mA
Short to VSS DAC Code = Full Scale
3
9
22
mA
Short to VDD DAC Code = 000h
Phase Margin
Slew
Rate(9)
Short-Circuit Current
Internal Band Gap
Band Gap Voltage
VBG
1.18
1.22
1.26
V
Band Gap Voltage
Temperature
Coefficient
VBGTC
—
15
—
ppm/°C
Operating Range
VDD
2.0
—
5.5
V
VREF pin voltage stable
2.2
—
5.5
V
VOUT output linear
External Reference (VREF)
Input Range(1)
VREF
VSS
—
VDD – 0.04
V
VRnB:VRnA = 11 (Buffered mode)
VSS
—
VDD
V
VRnB:VRnA = 10 (Unbuffered
mode)
Input Capacitance
CREF
—
1
—
pF
VRnB:VRnA = 10 (Unbuffered
mode)
Total Harmonic
Distortion(1)
THD
—
-64
—
dB
VREF = 2.048V ±0.1V,
VRnB:VRnA = 10, Gx = 0,
Frequency = 1 kHz
Major Code
Transition Glitch (see
B.14 “Major Code
Transition Glitch”)
—
—
45
—
nV-s
Digital Feedthrough
(see B.15 “Digital
Feedthrough”)
—
—
VPOR
Brown-out Reset Delay tBORD
—
45
—
µs
VDD transitions from VDD(MIN) > VPOR,
VOUT driven to VOUT disabled
Power-Down DAC
Output Disable Time
Delay
TPDE
—
10.5
—
µs
PDnB:PDnA = 00 11, 10 or 01 started from the falling
edge of the SCK at the end of the 24th clock cycle,
VOUT = VOUT – 10 mV, VOUT not connected
Power-Down DAC
Output Enable Time
Delay
TPDD
—
1
—
µs
PDnB:PDnA = 11, 10 or 01 00 started from the falling
edge of the SCK at the end of the 24th clock cycle,
Volatile DAC Register = FFh, VOUT = 10 mV,
VOUT not connected
DS20006362A-page 18
2020 Microchip Technology Inc.
MCP48FXBX4/8
1.2
SPI Mode Timing Waveforms and Requirements
VIHH
HVC
97
VIH
98
CS
VIH
VIL
96
‘1’
LAT
84
‘0’
‘1’
‘0’
70
94
72
96
SCK
83
71
80
SDO
MSb
73
FIGURE 1-5:
VIH
77
Bit 6 - - - -1
LSb In
SPI Timing Waveforms – Mode 1,1.
VIHH
97
VIH
98
VIH
82
VIH
VIL
CS
84
‘1’
LAT
LSb
74
MSb In
SDI
HVC
Bit 6 - - - - - -1
96
‘1’
‘0’
‘0’
70
71
94
72
83
96
SCK
80
73
MSb
SDO
Bit 6 - -1
77
LSb
74
SDI
FIGURE 1-6:
MSb In
Bit 6 - - - -1
LSb In
SPI Timing (Mode 0,0) Waveforms.
2020 Microchip Technology Inc.
DS20006362A-page 19
MCP48FXBX4/8
TABLE 1-4:
SPI REQUIREMENTS (MODE 1,1)
#
Characteristic
SCK Input Frequency
70
CS Active (VIL) to Command’s 1st SCK Input
71
SCK Input High Time
72
SCK Input Low Time
Symbol
Min.
FSCK
—
10
MHz VDD = 2.7V to 5.5V
(READ command)
—
20
MHz VDD = 2.7V to 5.5V
(all other commands)
60
—
TCSA2SCH
TSCH
TSCL
Max. Units
Conditions
ns
20
—
ns
VDD = 2.7V to 5.5V
400
—
ns
VDD = 1.8V to 2.7V
20
—
ns
VDD = 2.7V to 5.5V
400
—
ns
VDD = 1.8V to 2.7V
73
Setup Time of SDI Input to SCK Edge
TDIV2SCH
10
—
ns
74
Hold Time of SDI Input from SCK Edge
TSCH2DIL
20
—
ns
77
CS Inactive (VIH) to SDO Output
High-Impedance
TCSH2DOZ
—
50
ns
Note 1
80
SDO Data Output Valid after SCK Edge
TSCL2DOV
—
45
ns
VDD = 2.7V to 5.5V
—
170
ns
VDD = 1.8V to 2.7V
100
—
ns
VDD = 2.7V to 5.5V
µs
VDD = 1.8V to 2.7V
83
CS Inactive (VIH) after SCK Edge
TSCH2CSL
1
84
CS High Time (VIH)
94
LAT to SCK ↑ (write data 24th bit) Setup
Time
96
LAT High or Low Time
97
98
Note 1:
3:
TCSH
50
—
ns
TLATSU
20
—
ns
TLAT
20
—
ns
HVC to SCK (1st data bit)
(HVC setup time)
THVCSU
0
—
ns
High-Voltage Commands(1)
SCK ↑ (last bit of command, 8th or 24th bit) to
HVC (HVC hold time)
THVCHD
25
—
ns
High-Voltage Commands(1)
Write data transferred(3)
This parameter is ensured by design.
Within 1/2 LSb of the final value when the code changes from 1/4 to 3/4 of FSR. (Example: 400h to C00h in
12-bit device.) The transition of the LAT signal must occur 10 ns before the rising edge of the 24th SCK
signal (Spec 94) or the current register data value may not be transferred to the output latch (VOUT) before
the register is overwritten with the new value.
DS20006362A-page 20
2020 Microchip Technology Inc.
MCP48FXBX4/8
TABLE 1-5:
#
SPI REQUIREMENTS (MODE 0,0)
Characteristic
SCK Input Frequency
Sym.
FSCK
Min. Max. Units
Conditions
—
10
MHz VDD = 2.7V to 5.5V
(READ command)
—
20
MHz VDD = 2.7V to 5.5V
(all other commands)
70
CS Active (VIL) to SCK Input
TCSA2SCH
60
—
ns
71
SCK Input High Time
TSCH
20
—
ns
VDD = 2.7V to 5.5V
400
—
ns
VDD = 1.8V to 2.7V
72
SCK Input Low Time
TSCL
20
—
ns
VDD = 2.7V to 5.5V
VDD = 1.8V to 2.7V
73
Setup Time of SDI Input to SCK Edge
74
400
—
ns
TDIV2SCH
10
—
ns
Hold Time of SDI Input from SCK Edge
TSCH2DIL
20
—
ns
77
CS Inactive (VIH) to SDO Output
High-Impedance
TCSH2DOZ
—
50
ns
80
SDO Data Output Valid after SCK Edge
TSCL2DOV
Note 1
—
45
ns
VDD = 2.7V to 5.5V
—
170
ns
VDD = 1.8V to 2.7V
82
SDO Data Output Valid after CS Active (VIL)
TSSL2DOV
—
70
ns
83
CS Inactive (VIH) after SCK Edge
TSCH2CSL
100
—
ns
VDD = 2.7V to 5.5V
µs
VDD = 1.8V to 2.7V
1
84
CS High Time (VIH)
94
LAT to SCK ↑ (write data 24th bit) Setup
Time
96
LAT High or Low Time
97
98
Note 1:
3:
TCSH
50
—
ns
TLATSU
10
—
ns
TLAT
50
—
ns
HVC to SCK (1st data bit)
(HVC setup time)
THVCSU
0
—
ns
High-Voltage Commands(1)
SCK (last bit of command, 8th or 24th bit) to
HVC (HVC hold time)
THVCHD
25
—
ns
High-Voltage Commands(1)
Write data transferred(3)
This parameter is ensured by design.
Within 1/2 LSb of the final value when the code changes from 1/4 to 3/4 of FSR. (Example: 400h to C00h in
12-bit device.) The transition of the LAT signal must occur 10 ns before the rising edge of the 24th SCK
signal (Spec 94) or the current register data value may not be transferred to the output latch (VOUT) before
the register is overwritten with the new value.
2020 Microchip Technology Inc.
DS20006362A-page 21
MCP48FXBX4/8
Timing Table Notes:
1.
2.
3.
This parameter is ensured by design.
This parameter is ensured by characterization.
Within 1/2 LSb of the final value when the code changes from 1/4 to 3/4 of FSR. (Example: 400h to C00h in 12-bit
device).The transition of the LAT signal must occur 10 ns before the rising edge of the 24th SCK signal (Spec 94)
or the current register data value may not be transferred to the output latch (VOUT) before the register is
overwritten with the new value.
DS20006362A-page 22
2020 Microchip Technology Inc.
MCP48FXBX4/8
TEMPERATURE SPECIFICATIONS
Electrical Specifications: Unless otherwise indicated, VDD = +2.7V to +5.5V, VSS = GND.
Parameters
Sym.
Min.
Typ.
Max.
Units
TA
-40
—
+125
°C
Operating Temperature Range
TA
-40
—
+125
°C
Storage Temperature Range
TA
-65
—
+150
°C
Thermal Resistance, 20-Lead TSSOP
JA
—
90
—
°C/W
Thermal Resistance, 20-Lead VQFN
(5x5 mm, P8X)
JA
—
36.1
—
°C/W
Conditions
Temperature Ranges
Specified Temperature Range
Note 1
Thermal Package Resistances
Note 1:
Operation in this range must not cause TJ to exceed the Maximum Junction Temperature of +150°C.
2020 Microchip Technology Inc.
DS20006362A-page 23
MCP48FXBX4/8
NOTES:
DS20006362A-page 24
2020 Microchip Technology Inc.
MCP48FXBX4/8
2.0
Note:
2.1
Note:
TYPICAL PERFORMANCE CURVES
The graphs and tables provided following this note are a statistical summary based on a limited number of
samples and are provided for informational purposes only. The performance characteristics listed herein
are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified
operating range (e.g., outside specified power supply range) and therefore outside the warranted range.
Electrical Data
Unless otherwise indicated, TA = +25°C, VDD = 5.5V.
FIGURE 2-1:
Average Device Supply
Current vs. FSCK Frequency, Voltage and
Temperature – Active Interface,
VRnB:VRnA = 00, (VDD Mode).
FIGURE 2-4:
Average Device Supply
Current – Inactive Interface (SCK = VIH or VIL)
vs. Voltage and Temperature, VRnB:VRnA = 00
(VDD Mode).
FIGURE 2-2:
Average Device Supply
Current vs. FSCK Frequency, Voltage and
Temperature – Active Interface,
VRnB:VRnA = 01 (Band Gap Mode).
FIGURE 2-5:
Average Device Supply
Current – Inactive Interface (SCK = VIH or VIL)
vs. Voltage and Temperature, VRnB:VRnA = 01
(Band Gap Mode).
FIGURE 2-3:
Average Device Supply
Current vs. FSCK Frequency, Voltage and
Temperature – Active Interface,
VRnB:VRnA = 11 (VREF Buffered Mode).
FIGURE 2-6:
Average Device Supply
Current – Inactive Interface (SCK = VIH or VIL)
vs. Voltage and Temperature, VRnB:VRnA = 11
(VREF Buffered Mode).
2020 Microchip Technology Inc.
DS20006362A-page 25
MCP48FXBX4/8
Note:
Unless otherwise indicated, TA = +25°C, VDD = 5.5V.
FIGURE 2-7:
Average Device Supply
Current vs. FSCK Frequency, Voltage and
Temperature – Active Interface,
VRnB:VRnA = 10 (VREF Unbuffered Mode).
FIGURE 2-9:
Average Device Supply
Current – Inactive Interface (SCK = VIH or VIL)
vs. Voltage and Temperature, VRnB:VRnA = 10
(VREF Unbuffered Mode).
FIGURE 2-8:
Average Device Supply
Active Current (IDDA) (at 5.5V and
FSCK = 20 MHz) vs. Temperature and DAC
Reference Voltage Mode.
FIGURE 2-10:
DS20006362A-page 26
Power-Down Currents.
2020 Microchip Technology Inc.
MCP48FXBX4/8
2.2
2.2.1
Note:
Linearity Data
TOTAL UNADJUSTED ERROR (TUE) – MCP48FXB28 (12-BIT), VREF = VDD
(VRnB:VRnA = 00), GAIN = 1x, CODE 100-4000
Unless otherwise indicated: TA = +25°C, VDD = 5.5V
FIGURE 2-11:
Total Unadjusted Error
(VOUT) vs. DAC Code, T = -40°C, VDD = 5.5V.
FIGURE 2-14:
Total Unadjusted Error
(VOUT) vs. DAC Code, T = -40°C, VDD = 2.7V.
FIGURE 2-12:
Total Unadjusted Error
(VOUT) vs. DAC Code, T = +25°C, VDD = 5.5V.
FIGURE 2-15:
Total Unadjusted Error
(VOUT) vs. DAC Code, T = +25°C, VDD = 2.7V.
FIGURE 2-13:
Total Unadjusted Error
(VOUT) vs. DAC Code, T = +125°C, VDD = 5.5V.
FIGURE 2-16:
Total Unadjusted Error
(VOUT) vs. DAC Code, T = +125°C, VDD = 2.7V.
2020 Microchip Technology Inc.
DS20006362A-page 27
MCP48FXBX4/8
2.2.2
Note:
INTEGRAL NONLINEARITY (INL) – MCP48FXB28 (12-BIT), VREF = VDD (VRnB:VRnA = 00),
GAIN = 1x, CODE 64-4032
Unless otherwise indicated, TA = +25°C, VDD = 5.5V.
FIGURE 2-17:
INL Error vs. DAC Code,
T = 40°C, VDD = 5.5V.
FIGURE 2-20:
INL Error vs. DAC Code,
T = -40°C, VDD = 2.7V.
FIGURE 2-18:
INL Error vs. DAC Code,
T = +25°C, VDD = 5.5V.
FIGURE 2-21:
INL Error vs. DAC Code,
T = +25°C, VDD = 2.7V.
FIGURE 2-19:
INL Error vs. DAC Code,
T = +125°C, VDD = 5.5V.
FIGURE 2-22:
INL Error vs. DAC Code,
T = +125°C, VDD = 2.7V.
DS20006362A-page 28
2020 Microchip Technology Inc.
MCP48FXBX4/8
2.2.3
Note:
DIFFERENTIAL NONLINEARITY (DNL) – MCP48FXB28 (12-BIT), VREF = VDD
(VRnB:VRnA = 00), GAIN = 1x, CODE 64-4032
Unless otherwise indicated, TA = +25°C, VDD = 5.5V.
FIGURE 2-23:
DNL Error vs. DAC Code,
T = -40°C, VDD = 5.5V.
FIGURE 2-26:
DNL Error vs. DAC Code,
T = -40°C, VDD = 2.7V.
FIGURE 2-24:
DNL Error vs. DAC Code,
T = +25°C, VDD = 5.5V.
FIGURE 2-27:
DNL Error vs. DAC Code,
T = +25°C, VDD = 2.7V.
FIGURE 2-25:
DNL Error vs. DAC Code,
T = +125°C, VDD = 5.5V.
FIGURE 2-28:
DNL Error vs. DAC Code,
T = +125°C, VDD = 2.7V.
2020 Microchip Technology Inc.
DS20006362A-page 29
MCP48FXBX4/8
2.2.4
Note:
TOTAL UNADJUSTED ERROR (TUE) – MCP48FXB28 (12-BIT), BAND GAP MODE
(VRnB:VRnA = 01), GAIN = 2x, CODE 100-4000
Unless otherwise indicated, TA = +25°C, VDD = 5.5V.
FIGURE 2-29:
Total Unadjusted Error
(VOUT) vs. DAC Code, T = -40°C, VDD = 5.5V.
FIGURE 2-32:
Total Unadjusted Error
(VOUT) vs. DAC Code, T = -40°C, VDD = 2.7V.
FIGURE 2-30:
Total Unadjusted Error
(VOUT) vs. DAC Code, T = +25°C, VDD = 5.5V.
FIGURE 2-33:
Total Unadjusted Error
(VOUT) vs. DAC Code, T = +25°C, VDD = 2.7V.
FIGURE 2-31:
Total Unadjusted Error
(VOUT) vs. DAC Code, T = +125°C, VDD = 5.5V.
FIGURE 2-34:
Total Unadjusted Error
(VOUT) vs. DAC Code, T = +125°C, VDD = 2.7V.
DS20006362A-page 30
2020 Microchip Technology Inc.
MCP48FXBX4/8
2.2.5
Note:
TOTAL UNADJUSTED ERROR (TUE) – MCP48FXB28 (12-BIT), BAND GAP MODE
(VRnB:VRnA = 01), GAIN = 4x, CODE 100-4000
Unless otherwise indicated, TA = +25°C, VDD = 5.5V.
FIGURE 2-35:
Total Unadjusted Error
(VOUT) vs. DAC Code, T = -40°C, VDD = 5.5V.
FIGURE 2-37:
Total Unadjusted Error
(VOUT) vs. DAC Code, T = +125°C, VDD = 5.5V.
FIGURE 2-36:
Total Unadjusted Error
(VOUT) vs. DAC Code, T = +25°C, VDD = 5.5V.
2020 Microchip Technology Inc.
DS20006362A-page 31
MCP48FXBX4/8
2.2.6
Note:
INTEGRAL NONLINEARITY (INL) – MCP48FXB28 (12-BIT), BAND GAP MODE
(VRnB:VRnA = 01), GAIN = 2x, CODE 100-4000
Unless otherwise indicated, TA = +25°C, VDD = 5.5V.
FIGURE 2-38:
INL Error vs. DAC Code,
T = -40°C, VDD = 5.5V.
FIGURE 2-41:
INL Error vs. DAC Code,
T = -40°C, VDD = 2.7V.
FIGURE 2-39:
INL Error vs. DAC Code,
T = +25°C, VDD = 5.5V.
FIGURE 2-42:
INL Error vs. DAC Code,
T = +25°C, VDD = 2.7V.
FIGURE 2-40:
INL Error vs. DAC Code,
T = +125°C, VDD = 5.5V.
FIGURE 2-43:
INL Error vs. DAC Code,
T = +125°C, VDD = 2.7V.
DS20006362A-page 32
2020 Microchip Technology Inc.
MCP48FXBX4/8
2.2.7
Note:
INTEGRAL NONLINEARITY (INL) – MCP48FXB28 (12-BIT), BAND GAP MODE
(VRnB:VRnA = 01), GAIN = 4x, CODE 100-4000
Unless otherwise indicated, TA = +25°C, VDD = 5.5V.
FIGURE 2-44:
INL Error vs. DAC Code,
T = -40°C, VDD = 5.5V.
FIGURE 2-46:
INL Error vs. DAC Code,
T = +125°C, VDD = 5.5V.
FIGURE 2-45:
INL Error vs. DAC Code,
T = +25°C, VDD = 5.5V.
2020 Microchip Technology Inc.
DS20006362A-page 33
MCP48FXBX4/8
2.2.8
Note:
DIFFERENTIAL NONLINEARITY ERROR (DNL) – MCP48FXB28 (12-BIT), BAND GAP MODE
(VRnB:VRnA = 01), GAIN = 2x, CODE 100-4000
Unless otherwise indicated, TA = +25°C, VDD = 5.5V.
FIGURE 2-47:
DNL Error vs. DAC Code,
T = -40°C, VDD = 5.5V.
FIGURE 2-50:
DNL Error vs. DAC Code,
T = -40°C, VDD = 2.7V.
FIGURE 2-48:
DNL Error vs. DAC Code,
T = +25°C, VDD = 5.5V.
FIGURE 2-51:
DNL Error vs. DAC Code,
T = +25°C, VDD = 2.7V.
FIGURE 2-49:
DNL Error vs. DAC Code,
T = +125°C, VDD = 5.5V.
FIGURE 2-52:
DNL Error vs. DAC Code,
T = +125°C, VDD = 2.7V.
DS20006362A-page 34
2020 Microchip Technology Inc.
MCP48FXBX4/8
2.2.9
Note:
DIFFERENTIAL NONLINEARITY ERROR (DNL) – MCP48FXB28 (12-BIT), BAND GAP MODE
(VRnB:VRnA = 01), GAIN = 4x, CODE 100-4000
Unless otherwise indicated, TA = +25°C, VDD = 5.5V.
FIGURE 2-53:
DNL Error vs. DAC Code,
T = -40°C, VDD = 5.5V.
FIGURE 2-55:
DNL Error vs. DAC Code,
T = +125°C, VDD = 5.5V.
FIGURE 2-54:
DNL Error vs. DAC Code,
T = +25°C, VDD = 5.5V.
2020 Microchip Technology Inc.
DS20006362A-page 35
MCP48FXBX4/8
2.2.10
Note:
TOTAL UNADJUSTED ERROR (TUE) – MCP48FXB28 (12-BIT), EXTERNAL VREF
UNBUFFERED MODE (VRnB:VRnA = 10), VREF = VDD, GAIN = 1x, CODE 100-4000
Unless otherwise indicated, TA = +25°C, VDD = 5.5V.
FIGURE 2-56:
Total Unadjusted Error
(VOUT) vs. DAC Code, T = -40°C, VDD = 5.5V.
FIGURE 2-59:
Total Unadjusted Error
(VOUT) vs. DAC Code, T = -40°C, VDD = 2.7V.
FIGURE 2-57:
Total Unadjusted Error
(VOUT) vs. DAC Code, T = +25°C,VDD = 5.5V.
FIGURE 2-60:
Total Unadjusted Error
(VOUT) vs. DAC Code, T = +25°C, VDD = 2.7V.
FIGURE 2-58:
Total Unadjusted Error
(VOUT) vs. DAC Code, T = +125°C, VDD = 5.5V.
FIGURE 2-61:
Total Unadjusted Error
(VOUT) vs. DAC Code, T = +125°C, VDD = 2.7V.
DS20006362A-page 36
2020 Microchip Technology Inc.
MCP48FXBX4/8
2.2.11
Note:
TOTAL UNADJUSTED ERROR (TUE) – MCP48FXB28 (12-BIT), EXTERNAL VREF
UNBUFFERED MODE (VRnB:VRnA = 10), VREF = VDD/2, GAIN = 2x, CODE 100-4000
Unless otherwise indicated, TA = +25°C, VDD = 5.5V.
FIGURE 2-62:
Total Unadjusted Error
(VOUT) vs. DAC Code, T = -40°C, VDD = 5.5V.
FIGURE 2-65:
Total Unadjusted Error
(VOUT) vs. DAC Code, T = -40°C, VDD = 2.7V.
FIGURE 2-63:
Total Unadjusted Error
(VOUT) vs. DAC Code, T = +25°C,VDD = 5.5V.
FIGURE 2-66:
Total Unadjusted Error
(VOUT) vs. DAC Code, T = +25°C, VDD = 2.7V.
FIGURE 2-64:
Total Unadjusted Error
(VOUT) vs. DAC Code, T = +125°C, VDD = 5.5V.
FIGURE 2-67:
Total Unadjusted Error
(VOUT) vs. DAC Code, T = +125°C, VDD = 2.7V.
2020 Microchip Technology Inc.
DS20006362A-page 37
MCP48FXBX4/8
2.2.12
Note:
INTEGRAL NONLINEARITY ERROR (INL) – MCP48FXB28 (12-BIT), EXTERNAL VREF
MODE, UNBUFFERED (VRnB:VRnA = 10), VREF = VDD, GAIN = 1x, CODE 100-4000
Unless otherwise indicated, TA = +25°C, VDD = 5.5V.
FIGURE 2-68:
INL Error vs. DAC Code,
T = -40°C, VDD = 5.5V.
FIGURE 2-71:
INL Error vs. DAC Code,
T = -40°C, VDD = 2.7V.
FIGURE 2-69:
INL Error vs. DAC Code,
T = +25°C, VDD = 5.5V.
FIGURE 2-72:
INL Error vs. DAC Code,
T = +25°C, VDD = 2.7V.
FIGURE 2-70:
INL Error vs. DAC Code,
T = +125°C, VDD = 5.5V.
FIGURE 2-73:
INL Error vs. DAC Code,
T = +125°C, VDD = 2.7V.
DS20006362A-page 38
2020 Microchip Technology Inc.
MCP48FXBX4/8
2.2.13
Note:
INTEGRAL NONLINEARITY ERROR (INL) – MCP48FXB28 (12-BIT), EXTERNAL VREF
MODE, UNBUFFERED (VRnB:VRnA = 10), VREF = VDD/2, GAIN = 2x, CODE 100-4000
Unless otherwise indicated, TA = +25°C, VDD = 5.5V.
FIGURE 2-74:
INL Error vs. DAC Code,
T = -40°C, VDD = 5.5V.
FIGURE 2-77:
INL Error vs. DAC Code,
T = -40°C, VDD = 2.7V.
FIGURE 2-75:
INL Error vs. DAC Code,
T = +25°C, VDD = 5.5V.
FIGURE 2-78:
INL Error vs. DAC Code,
T = +25°C, VDD = 2.7V.
FIGURE 2-76:
INL Error vs. DAC Code,
T = +125°C, VDD = 5.5V.
FIGURE 2-79:
INL Error vs. DAC Code,
T = +125°C, VDD = 2.7V.
2020 Microchip Technology Inc.
DS20006362A-page 39
MCP48FXBX4/8
2.2.14
Note:
DIFFERENTIAL NONLINEARITY ERROR (DNL) – MCP48FXB28 (12-BIT), EXTERNAL VREF
MODE, UNBUFFERED (VRnB:VRnA = 10), VREF = VDD, GAIN = 1x, CODE 100-4000
Unless otherwise indicated, TA = +25°C, VDD = 5.5V.
.
FIGURE 2-80:
DNL Error vs. DAC Code,
T = -40°C, VDD = 5.5V.
FIGURE 2-83:
DNL Error vs. DAC Code,
T = -40°C, VDD = 2.7V.
FIGURE 2-81:
DNL Error vs. DAC Code,
T = +25°C, VDD = 5.5V.
FIGURE 2-84:
DNL Error vs. DAC Code,
T = +25°C, VDD = 2.7V.
FIGURE 2-82:
DNL Error vs. DAC Code,
T = +125°C, VDD = 5.5V.
FIGURE 2-85:
DNL Error vs. DAC Code,
T = +125°C, VDD = 2.7V.
DS20006362A-page 40
2020 Microchip Technology Inc.
MCP48FXBX4/8
2.2.15
Note:
DIFFERENTIAL NONLINEARITY ERROR (DNL) – MCP48FXB28 (12-BIT), EXTERNAL VREF
MODE, UNBUFFERED (VRnB:VRnA = 10), VREF = VDD/2, GAIN = 2x, CODE 100-4000
Unless otherwise indicated, TA = +25°C, VDD = 5.5V.
.
FIGURE 2-86:
DNL Error vs. DAC Code,
T = -40°C, VDD = 5.5V.
FIGURE 2-89:
DNL Error vs. DAC Code,
T = -40°C, VDD = 2.7V.
FIGURE 2-87:
DNL Error vs. DAC Code,
T = +25°C, VDD = 5.5V.
FIGURE 2-90:
DNL Error vs. DAC Code,
T = +25°C, VDD = 2.7V.
FIGURE 2-88:
DNL Error vs. DAC Code,
T = +125°C, VDD = 5.5V.
FIGURE 2-91:
DNL Error vs. DAC Code,
T = +125°C, VDD = 2.7V.
2020 Microchip Technology Inc.
DS20006362A-page 41
MCP48FXBX4/8
2.2.16
Note:
TOTAL UNADJUSTED ERROR (TUE) – MCP48FXB28 (12-BIT), EXTERNAL VREF
BUFFERED MODE (VRnB:VRnA = 10), VREF = VDD, GAIN = 1x, CODE 100-4000
Unless otherwise indicated, TA = +25°C, VDD = 5.5V.
FIGURE 2-92:
Total Unadjusted Error
(VOUT) vs. DAC Code, T = -40°C, VDD = 5.5V.
FIGURE 2-95:
Total Unadjusted Error
(VOUT) vs. DAC Code, T = -40°C, VDD = 2.7V.
FIGURE 2-93:
Total Unadjusted Error
(VOUT) vs. DAC Code, T = +25°C,VDD = 5.5V.
FIGURE 2-96:
Total Unadjusted Error
(VOUT) vs. DAC Code, T = +25°C, VDD = 2.7V.
FIGURE 2-94:
Total Unadjusted Error
(VOUT) vs. DAC Code, T = +125°C, VDD = 5.5V.
FIGURE 2-97:
Total Unadjusted Error
(VOUT) vs. DAC Code, T = +125°C, VDD = 2.7V.
DS20006362A-page 42
2020 Microchip Technology Inc.
MCP48FXBX4/8
2.2.17
Note:
TOTAL UNADJUSTED ERROR (TUE) – MCP48FXB28 (12-BIT), EXTERNAL VREF
BUFFERED MODE (VRnB:VRnA = 10), VREF = VDD/2, GAIN = 2x, CODE 100-4000
Unless otherwise indicated, TA = +25°C, VDD = 5.5V.
FIGURE 2-98:
Total Unadjusted Error
(VOUT) vs. DAC Code, T = -40°C, VDD = 5.5V.
FIGURE 2-101:
Total Unadjusted Error
(VOUT) vs. DAC Code, T = -40°C, VDD = 2.7V.
FIGURE 2-99:
Total Unadjusted Error
(VOUT) vs. DAC Code, T = +25°C,VDD = 5.5V.
FIGURE 2-102:
Total Unadjusted Error
(VOUT) vs. DAC Code, T = +25°C, VDD = 2.7V.
FIGURE 2-100:
Total Unadjusted Error
(VOUT) vs. DAC Code, T = +125°C, VDD = 5.5V.
FIGURE 2-103:
Total Unadjusted Error
(VOUT) vs. DAC Code, T = +125°C, VDD = 2.7V.
2020 Microchip Technology Inc.
DS20006362A-page 43
MCP48FXBX4/8
2.2.18
Note:
INTEGRAL NONLINEARITY ERROR (INL) – MCP48FXB28 (12-BIT), EXTERNAL VREF
MODE, BUFFERED (VRnB:VRnA = 11), VREF = VDD, GAIN = 1x, CODE 100-4000
Unless otherwise indicated, TA = +25°C, VDD = 5.5V.
FIGURE 2-104:
INL Error vs. DAC Code,
T = -40°C, VDD = 5.5V.
FIGURE 2-107:
INL Error vs. DAC Code,
T = -40°C, VDD = 2.7V.
FIGURE 2-105:
INL Error vs. DAC Code,
T = +25°C, VDD = 5.5V.
FIGURE 2-108:
INL Error vs. DAC Code,
T = +25°C, VDD = 2.7V.
FIGURE 2-106:
INL Error vs. DAC Code,
T = +125°C, VDD = 5.5V.
FIGURE 2-109:
INL Error vs. DAC Code,
T = +125°C, VDD = 2.7V.
DS20006362A-page 44
2020 Microchip Technology Inc.
MCP48FXBX4/8
2.2.19
Note:
INTEGRAL NONLINEARITY ERROR (INL) – MCP48FXB28 (12-BIT), EXTERNAL VREF
MODE, BUFFERED (VRnB:VRnA = 11), VREF = VDD/2, GAIN = 2x, CODE 100-4000
Unless otherwise indicated, TA = +25°C, VDD = 5.5V.
FIGURE 2-110:
INL Error vs. DAC Code,
T = -40°C, VDD = 5.5V.
FIGURE 2-113:
INL Error vs. DAC Code,
T = -40°C, VDD = 2.7V.
FIGURE 2-111:
INL Error vs. DAC Code,
T = +25°C, VDD = 5.5V.
FIGURE 2-114:
INL Error vs. DAC Code,
T = +25°C, VDD = 2.7V.
FIGURE 2-112:
INL Error vs. DAC Code,
T = +125°C, VDD = 5.5V.
FIGURE 2-115:
INL Error vs. DAC Code,
T = +125°C, VDD = 2.7V.
2020 Microchip Technology Inc.
DS20006362A-page 45
MCP48FXBX4/8
2.2.20
Note:
DIFFERENTIAL NONLINEARITY ERROR (DNL) – MCP48FXB28 (12-BIT), EXTERNAL VREF
MODE, BUFFERED (VRnB:VRnA = 11), VREF = VDD, GAIN = 1x, CODE 100-4000
Unless otherwise indicated, TA = +25°C, VDD = 5.5V.
.
FIGURE 2-116:
DNL Error vs. DAC Code,
T = -40°C, VDD = 5.5V.
FIGURE 2-119:
DNL Error vs. DAC Code,
T = -40°C, VDD = 2.7V.
FIGURE 2-117:
DNL Error vs. DAC Code,
T = +25°C, VDD = 5.5V.
FIGURE 2-120:
DNL Error vs. DAC Code,
T = +25°C, VDD = 2.7V.
FIGURE 2-118:
DNL Error vs. DAC Code,
T = +125°C, VDD = 5.5V.
FIGURE 2-121:
DNL Error vs. DAC Code,
T = +125°C, VDD = 2.7V.
DS20006362A-page 46
2020 Microchip Technology Inc.
MCP48FXBX4/8
2.2.21
Note:
DIFFERENTIAL NONLINEARITY ERROR (DNL) – MCP48FXB28 (12-BIT), EXTERNAL VREF
MODE, BUFFERED (VRnB:VRnA = 11), VREF = VDD/2, GAIN = 2x, CODE 100-4000
Unless otherwise indicated, TA = +25°C, VDD = 5.5V.
.
FIGURE 2-122:
DNL Error vs. DAC Code,
T = -40°C, VDD = 5.5V.
FIGURE 2-125:
DNL Error vs. DAC Code,
T = -40°C, VDD = 2.7V.
FIGURE 2-123:
DNL Error vs. DAC Code,
T = +25°C, VDD = 5.5V.
FIGURE 2-126:
DNL Error vs. DAC Code,
T = +25°C, VDD = 2.7V.
FIGURE 2-124:
DNL Error vs. DAC Code,
T = +125°C, VDD = 5.5V.
FIGURE 2-127:
DNL Error vs. DAC Code,
T = +125°C, VDD = 2.7V.
2020 Microchip Technology Inc.
DS20006362A-page 47
MCP48FXBX4/8
NOTES:
DS20006362A-page 48
2020 Microchip Technology Inc.
MCP48FXBX4/8
3.0
PIN DESCRIPTIONS
Overviews of the pin functions are provided in
Section 3.1 “Positive Power Supply Input Pin
(VDD)” through Section 3.10 “No Connect Pin (NC)”.
The descriptions of the pins for the quad DAC output
devices are listed in Table 3-1 and descriptions for the
octal DAC output devices are listed in Table 3-2.
TABLE 3-1:
MCP48FXBX4 (QUAD DAC) PIN FUNCTION TABLE
Pin
20-Lead
TSSOP
20-Lead
VQFN
Symbol
I/O
Buffer
Type
Description
1
19
LAT1
I
ST
DAC Register Latch Pin. The Latch 1 pin allows the value in the
volatile DAC1/DAC3 registers (wiper and Configuration bits) to
be transferred to the DAC1/DAC3 outputs (VOUT1, VOUT3).
2
20
VDD
—
P
Supply Voltage Pin
3
1
CS
I
ST
SPI Chip Select Pin
4
2
VREF0
A
Analog
Voltage Reference Input 0 Pin
5
3
VOUT0
A
Analog
Buffered Analog Voltage Output – Channel 0 Pin
6
4
VOUT2
A
Analog
Buffered Analog Voltage Output – Channel 2 Pin
NC
—
—
7, 8, 10, 5, 6, 8, 9,
11, 12, 13
10,11
Not internally connected
9
7
VSS
—
P
Ground Reference Pin for all circuitries on the device
14
12
VOUT3
—
—
Buffered Analog Voltage Output – Channel 3 Pin
15
13
VOUT1
—
—
16
14
VREF1
A
Analog
17
15
SDO
I
—
SPI Serial Data Output Pin
18
16
SCK
I
ST
SPI Serial Clock Pin
19
17
SDI
I
ST
SPI Serial Data Input Pin
20
18
LAT0/HVC
I
ST
DAC Register Latch/High-Voltage Command Pin. The Latch 0
pin allows the value in the volatile DAC0/DAC2 registers (wiper
and Configuration bits) to be transferred to the DAC0/DAC2
outputs (VOUT0, VOUT2). The High-Voltage Command (HVC)
allows user Configuration bits to be written.
—
21
EP
—
—
Exposed Thermal Pad Pin(1)
Note 1:
Buffered Analog Voltage Output – Channel 1 Pin
Voltage Reference Input 1 Pin
A = Analog, ST = Schmitt Trigger, HV = High Voltage, I = Input, O = Output, I/O = Input/Output,
P = Power.
2020 Microchip Technology Inc.
DS20006362A-page 49
MCP48FXBX4/8
TABLE 3-2:
MCP48FXBX8 (OCTAL DAC) PIN FUNCTION TABLE
Pin
20-Lead 20-Lead
TSSOP VQFN
Symbol
I/O
Buffer
Type
Description
ST
DAC Register Latch Pin. The Latch 1 pin allows the value in the
volatile DAC1/DAC3/DAC5/DAC7 registers (wiper and Configuration bits) to be transferred to the DAC1/DAC3/DAC5/DAC7 outputs
(VOUT1, VOUT3, VOUT5, VOUT7).
1
19
LAT1
I
2
20
VDD
—
P
Supply Voltage Pin
ST
SPI Chip Select Pin
3
1
CS
I
4
2
VREF0
A
Analog
Voltage Reference Input 0 Pin
5
3
VOUT0
A
Analog
Buffered Analog Voltage Output – Channel 0 Pin
6
4
VOUT2
A
Analog
Buffered Analog Voltage Output – Channel 2 Pin
7
5
VOUT4
A
Analog
Buffered Analog Voltage Output – Channel 4 Pin
8
6
VOUT6
A
Analog
Buffered Analog Voltage Output – Channel 6 Pin
P
Ground Reference Pin for all circuitries on the device
Not internally connected
9
7
VSS
—
10, 11
8, 9
NC
—
—
12
10
VOUT7
A
Analog
Buffered Analog Voltage Output – Channel 7 Pin
13
11
VOUT5
A
Analog
Buffered Analog Voltage Output – Channel 5 Pin
14
12
VOUT3
A
Analog
Buffered Analog Voltage Output – Channel 3 Pin
15
13
VOUT1
A
Analog
Buffered Analog Voltage Output – Channel 1 Pin
Analog
Voltage Reference Input 1 Pin
16
14
VREF1
A
17
15
SDO
I
—
SPI Serial Data Output Pin
18
16
SCK
I
ST
SPI Serial Clock Pin
19
17
SDI
I
ST
SPI Serial Data Input Pin
20
18
LAT0/HVC
I
ST
DAC Register Latch/High-Voltage Command Pin. The Latch 0 pin
allows the value in the volatile DAC0/DAC2/DAC4/DAC6 registers
(wiper and Configuration bits) to be transferred to the
DAC0/DAC2/DAC4/DAC6 outputs (VOUT0, VOUT2, VOUT4, VOUT6).
The High-Voltage Command (HVC) allows user Configuration bits
to be written.
—
21
EP
—
—
Exposed Thermal Pad Pin(1)
Note 1:
A = Analog, ST = Schmitt Trigger, HV = High Voltage, I = Input, O = Output, I/O = Input/Output, P = Power.
DS20006362A-page 50
2020 Microchip Technology Inc.
MCP48FXBX4/8
3.1
Positive Power Supply Input Pin
(VDD)
VDD is the positive supply voltage input pin. The input
supply voltage is relative to VSS.
The power supply at the VDD pin should be as clean as
possible for a good DAC performance. It is recommended to use an appropriate bypass capacitor of
about 0.1 µF (ceramic) to ground. An additional 10 µF
capacitor (tantalum) in parallel is also recommended to
further attenuate noise present in application boards.
3.2
Ground Pin (VSS)
The VSS pin is the device ground reference.
The user must connect the VSS pin to a ground plane
through a low-impedance connection. If an analog
ground path is available in the application PCB (Printed
Circuit Board), it is highly recommended that the VSS
pin be tied to the analog ground path or isolated within
an analog ground plane of the circuit board.
3.3
Voltage Reference Pins (VREF)
3.4
Analog Output Voltage Pins
(VOUTn)
VOUT is the DAC analog voltage output pin. The DAC
output has an output amplifier. The DAC output range
depends on the selection of the voltage reference
source (and potential output gain selection). These are:
• Device VDD – The full-scale range of the DAC
output is from VSS to approximately VDD.
• VREF Pin – The full-scale range of the DAC output
is from VSS to G × VRL, where G is the gain
selection option (1x or 2x).
• Internal Band Gap – The full-scale range of the
DAC output is from VSS to G × (2 × VBG), where G
is the gain selection option (1x or 2x).
In Normal mode, the DC impedance of the output pin is
about 1. In Power-Down mode, the output pin is
internally connected to a known pull-down resistor of
1 k, 125 k or open. The power-down selection bits
setting are shown in Register 4-3 and Table 5-4.
3.5
Latch Pin (LAT)/High-Voltage
Command Pin (HVC)
The VREF pin is either an input or an output. When the
DAC’s voltage reference is configured as the VREF pin,
the pin is an input. When the DAC’s voltage reference is
configured as the internal band gap, the pin is an output.
The DAC output value update event can be controlled
and synchronized using the LAT pins, for one or both
channels, on a single or different devices.
When the DAC’s voltage reference is configured as the
VREF pin, there are two options for this voltage input:
The LAT pins control the effect of the Volatile Wiper
registers, and the VRnB:VRnA, PDnB:PDnA and Gx
bits on the DAC output.
• VREF pin voltage buffered
• VREF pin voltage unbuffered
The buffered option is offered in cases where the external reference voltage does not have sufficient current
capability to not drop its voltage when connected to the
internal resistor ladder circuit.
When the DAC’s voltage reference is configured as the
device VDD, the VREF pin is disconnected from the
internal circuit.
When the DAC’s voltage reference is configured as the
internal band gap, the VREF pin’s drive capability is minimal, so the output signal should be buffered.
There are two VREF pins, each corresponding to a
group of output channels. VREF0 is connected to even
channels: 0-6, while VREF1 is connected to odd
channels: 1-7. See Section 5.2 “Voltage Reference
Selection” and Register 4-2 for more details on the
configuration bits.
2020 Microchip Technology Inc.
If the LAT pins are held at VIH, the values sent to the
Volatile Wiper registers and Configuration bits have no
effect on the DAC outputs.
Once voltage on the pin transitions to VIL, the values in
the Volatile Wiper registers and Configuration bits are
transferred to the DAC outputs.
The pin is level-sensitive, so writing to the Volatile
Wiper registers and Configuration bits, while it is being
held at VIL, will trigger an immediate change in the
outputs.
The HVC pin allows the device’s nonvolatile user
Configuration bits to be programmed when the voltage
on the pin is greater than the VIHH entry voltage.
3.6
SPI – Chip Select Pin (CS)
The CS pin enables/disables the serial interface. The
serial interface must be enabled for the SPI commands
to be received by the device. See Section 6.2 “SPI
Serial Interface” for more details on the SPI serial
interface communication.
DS20006362A-page 51
MCP48FXBX4/8
3.7
SPI – Serial Data Input Pin (SDI)
The SDI pin is the serial data input pin of the SPI
interface. The SDI pin is used to read the DAC registers
and Configuration bits.
See Section 6.2 “SPI Serial Interface” for more
details on the SPI serial interface communication.
3.8
SPI – Serial Data Output Pin (SDO)
The SDO pin is the serial data output pin of the SPI
interface. The SDO pin is used to write the DAC
registers and Configuration bits.
3.10
No Connect Pin (NC)
The NC pins are not connected to the device.
3.11
Exposed Pad Pin
This pad is conductively connected to the device’s
substrate. It should be tied to the same potential as the
VSS pin (or left unconnected). This pad could be used
to assist in heat dissipation for the device when connected to a PCB heat sink. The pad is only present on
the VQFN package.
See Section 6.2 “SPI Serial Interface” for more
details on the SPI serial interface communication.
3.9
SPI – Serial Clock Pin (SCK)
The SCK pin is the serial clock pin of the SPI interface.
The MCP48FXBX4/8 SPI interface only accepts
external serial clocks.
See Section 6.2, SPI Serial Interface for more details
on the SPI serial interface communication.
DS20006362A-page 52
2020 Microchip Technology Inc.
MCP48FXBX4/8
4.0
GENERAL DESCRIPTION
The MCP48FXBX4 (MCP48FXB04, MCP48FXB14
and MCP48FXB24) devices are quad-channel voltage
output devices. The MCP48FXBX8 (MCP48FXB08,
MCP48FXB18 and MCP48FXB28) devices are
octal-channel voltage output devices.
These devices are offered with 8-bit (MCP48FXB0X),
10-bit (MCP48FXB1X) and 12-bit (MCP48FXB2X) resolutions and include nonvolatile memory (EEPROM),
an SPI serial interface and two write Latch pins (LAT0,
LAT1) to control the update of the written DAC value to
the DAC output pin.
The devices use a resistor ladder architecture. The
resistor ladder DAC is driven from a softwareselectable voltage reference source. The source can
be either the device’s internal VDD, an external VREF
pin voltage (buffered or unbuffered) or an internal band
gap voltage source.
The DAC output is buffered with a low-power and
precision output amplifier (op amp). This output
amplifier provides a rail-to-rail output with low offset
voltage and low noise. The gain (1x or 2x) of the
output buffer is software configurable.
This device family also has a user-programmable
nonvolatile memory (EEPROM) option, which allows
the user to save the desired POR/BOR value of the
DAC register and device Configuration bits.
High-voltage lock bits can be used to ensure that the
device’s output settings are not accidentally modified.
The device operates from a single-supply voltage. This
voltage is specified from 2.7V to 5.5V for full specified
operation and from 1.8V to 5.5V for digital operation.
The device can operate between 1.8V and 2.7V, but its
analog performance is significantly reduced; therefore,
most device parameters are not specified for this
range.
The main functional blocks are:
•
•
•
•
•
•
Power-on Reset/Brown-out Reset (POR/BOR)
Device Memory
Resistor Ladder
Output Buffer/VOUT Operation
Internal Band Gap
SPI Serial Interface Module
4.1
Power-on Reset/Brown-out Reset
(POR/BOR)
The internal POR/BOR circuit monitors the power
supply voltage (VDD) during operation. This circuit
ensures correct device start-up at system power-up
and power-down events. The device’s RAM Retention
Voltage (VRAM) is lower than the POR/BOR Voltage
(VPOR/VBOR) trip point. The maximum VPOR/VBOR
voltage is less than 1.8V.
POR occurs as the voltage rises (typically from 0V),
while BOR occurs as the voltage falls (typically from
VDD(MIN) or higher).
The POR and BOR trip points are at the same voltage
and the condition is determined by whether the VDD
voltage is rising or falling (see Figure 4-1). What occurs
is different depending on whether the reset is a POR or
BOR.
When VPOR/VBOR < VDD < 2.7V, the electrical performance may not meet the data sheet specifications. In
this region, the device is capable of reading and writing
to its EEPROM and reading and writing to its volatile
memory if the proper serial command is executed.
4.1.1
POWER-ON RESET
The Power-on Reset is the case where the VDD has
power applied to it, ramping up from the VSS voltage
level. As the device powers up, the VOUT pin floats to
an unknown value. When VDD is above the transistor
threshold voltage of the device, the output starts to be
pulled low. After the VDD is above the POR/BOR trip
point (VBOR/VPOR), the resistor network’s wiper is
loaded with the POR value (midscale). The volatile
memory determines the analog output (VOUT) pin voltage. After the device is powered up, the user can
update the device’s memory.
When the rising VDD voltage crosses the VPOR trip
point, the following occurs:
• The nonvolatile DAC register value is latched into
the volatile DAC register.
• The nonvolatile Configuration bit values are
latched into the volatile Configuration bits.
• The POR status bit is set (‘1’).
• The POR Reset Delay Timer (tPORD) starts; when
the POR Reset Delay Timer (tPORD) times out, the
serial interface is operational. During this delay
time, the serial interface will not accept commands.
• The Device Memory Address Pointer is forced to
00h.
The Analog Output (VOUT) state is determined by the
state of the volatile Configuration bits and the DAC
register. This is called a Power-on Reset (event).
Figure 4-1 illustrates the conditions for power-up and
power-down events under typical conditions.
2020 Microchip Technology Inc.
DS20006362A-page 53
MCP48FXBX4/8
4.1.2
BROWN-OUT RESET
The Brown-out Reset occurs when a device has power
applied to it and that power (voltage) drops below the
specified range.
When the falling VDD voltage crosses the VPOR trip
point (BOR event), the following occurs:
• The serial interface is disabled.
• EEPROM writes are disabled.
• The device is forced into a Power-Down state
(PDnB:PDnA = 11). Analog circuitry is turned off.
• The volatile DAC register is forced to 000h.
• Volatile Configuration bits, VRnB:VRnA and Gx,
are forced to ‘0’.
If the VDD voltage decreases below the VRAM voltage,
all volatile memory may become corrupted.
As the voltage recovers above the VPOR/VBOR voltage,
see Section 4.1.1 “Power-on Reset”.
Serial commands not completed due to a brown-out
condition may cause the memory location (volatile and
nonvolatile) to become corrupted.
Figure 4-1 illustrates the conditions for power-up and
power-down events under typical conditions.
POR Starts Reset Delay Timer;
After it Times Out, the Serial Interface
Default Device Configuration
can Operate (if VDD VDD(MIN))
Latched into Volatile Configuration
Bits and DAC Register; POR
Status Bit is Set (‘1’)
Volatile Memory Retains
Data Values
POR Forced
TPORD
Active
BOR,
Volatile DAC Register = 000h,
Volatile VRnB:VRnA = 00,
Volatile Gx = 0,
Volatile PDnB:PDnA = 11
VDD(MIN)
VBOR
VPOR
Volatile Memory
becomes Corrupted
VRAM
Device in Unknown
State
FIGURE 4-1:
DS20006362A-page 54
Device Normal Operation
in POR
State
Device in
Below Min. PowerOperating Down
Voltage
State
Device in
Unknown
State
POR/BOR Operation.
2020 Microchip Technology Inc.
MCP48FXBX4/8
4.2
Device Memory
User memory includes the following types:
• Volatile Register Memory (RAM)
• Nonvolatile Register Memory
• Device Configuration Memory
Each memory address is 16 bits wide. There are up to
17 nonvolatile user control bits that do not reside in
memory-mapped register space (see Section 4.2.3
“Device Configuration Memory”).
4.2.1
VOLATILE REGISTER MEMORY
(RAM)
4.2.3
DEVICE CONFIGURATION
MEMORY
There are up to sixteen nonvolatile user bits that are not
directly mapped into the address space. These nonvolatile device Configuration bits control the WiperLock
technology for DAC registers and configuration (two bits
per DAC).
The Status register shows the states of the device
WiperLock technology Configuration bits. The Status
register is described in Register 4-6.
The operation of WiperLock technology is discussed in
Section 4.2.6 “WiperLock Technology”.
There are up to twelve volatile memory locations:
4.2.4
•
•
•
•
•
READ commands of a valid location will read
unimplemented bits as ‘0’.
DAC0 through DAC7 Output Value registers
VREF Select register
Power-Down Configuration register
Gain and Status register
WiperLock Technology Status register
The volatile memory starts functioning when the
device VDD is at (or above) the RAM Retention Voltage
(VRAM). The volatile memory will be loaded with the
default device values when the VDD rises across the
VPOR/VBOR voltage trip point.
4.2.2
NONVOLATILE REGISTER
MEMORY
This device family uses the nonvolatile memory for the
DAC output value and Configuration registers:
• Nonvolatile DAC0 through DAC7 Output Value
registers
• Nonvolatile VREF Select register
• Nonvolatile Power-Down Configuration register
• Nonvolatile Gain register
The nonvolatile memory starts functioning below the
device’s VPOR/VBOR trip point, and is loaded into the
corresponding volatile registers whenever the device
rises above the POR/BOR voltage trip point.
4.2.5
UNIMPLEMENTED REGISTER BITS
UNIMPLEMENTED (RESERVED)
LOCATIONS
Normal (voltage) commands (READ or WRITE) to any
unimplemented memory address (reserved) will result
in a Command Error (CMDERR) condition. READ
commands of a reserved location will read bits as ‘1’.
High-Voltage Commands (enable or disable) to any
unimplemented Configuration bits will result in a
Command Error (CMDERR) condition.
4.2.5.1
Default Factory POR Memory State
of Nonvolatile Memory (EEPROM)
Table 4-2 shows the default factory POR initialization
of the device memory map for the 8, 10 and 12-bit
devices. In the case of volatile memory devices
(MCP48FVBXX), the factory default values cannot be
modified.
Note:
The volatile memory locations will be
determined by the nonvolatile memory
states (registers and device Configuration
bits).
The device starts writing the nonvolatile (EEPROM)
memory location at the completion of the serial
interface command, after the Acknowledge pulse of the
WRITE single command. Continuous WRITE
commands addressing the nonvolatile memory are not
permitted.
Note:
When the nonvolatile memory is written,
the corresponding volatile memory is not
modified.
Nonvolatile DAC registers enable the stand-alone
operation of the device (without microcontroller control)
after being programmed to the desired value.
2020 Microchip Technology Inc.
DS20006362A-page 55
MCP48FXBX4/8
Config
Bit(1)
Quad
Octal
Y
10h
Nonvolatile DAC0 Register
DL0
Y
Y
Y
11h
Nonvolatile DAC1 Register
DL1
Y
Y
Y
12h
Nonvolatile DAC2 Register
DL2
Y
Y
Y
Y
13h
Nonvolatile DAC3 Register
DL3
Y
Y
CL4
—
Y
14h
Nonvolatile DAC4 Register
DL4
—
Y
CL5
—
Y
15h
Nonvolatile DAC5 Register
DL5
—
Y
Volatile DAC6 Register
CL6
—
Y
16h
Nonvolatile DAC6 Register
DL6
—
Y
07h
Volatile DAC7 Register
CL7
—
Y
17h
Nonvolatile DAC7 Register
DL7
—
Y
08h
VREF Register
—
Y
Y
18h
Nonvolatile VREF Register
—
Y
Y
09h
Power-Down Register
—
Y
Y
19h
Nonvolatile Power-Down
Register
—
Y
Y
0Ah
Gain and Status Register
—
Y
Y
1Ah
Nonvolatile Gain Register
—
Y
Y
0Bh
WiperLock™ Technology
Status Register
—
Y
Y
1Bh
Reserved
—
—
—
Config
Bit(1)
Quad
Address
Address
MCP48FXBX4/8 MEMORY MAP
Octal
TABLE 4-1:
00h
Volatile DAC0 Register
CL0
Y
01h
Volatile DAC1 Register
CL1
Y
02h
Volatile DAC2 Register
CL2
Y
03h
Volatile DAC3 Register
CL3
04h
Volatile DAC4 Register
05h
Volatile DAC5 Register
06h
Function
Volatile Memory Address Range
Nonvolatile Memory Address Range
Device Configuration memory bits require a high-voltage enable or disable command
(LATn = VIHH or CS = VIHH) to modify the bit value.
TABLE 4-2:
FACTORY DEFAULT POR/BOR VALUES
Address
POR/BOR Value
POR/BOR Value
10-Bit
12-Bit
8-Bit
10-Bit
12-Bit
Function
8-Bit
Function
Address
Note 1:
Function
00h Volatile DAC0 Register
7Fh
1FFh
7FFh
10h Nonvolatile DAC0 Register
7Fh
1FFh
7FFh
01h Volatile DAC1 Register
7Fh
1FFh
7FFh
11h Nonvolatile DAC1 Register
7Fh
1FFh
7FFh
02h Volatile DAC2 Register
FFh
3FFh
FFFh
12h Nonvolatile DAC2 Register
FFh
3FFh
FFFh
03h Volatile DAC3 Register
FFh
3FFh
FFFh
13h Nonvolatile DAC3 Register
FFh
3FFh
FFFh
04h Volatile DAC4 Register
FFh
3FFh
FFFh
14h Nonvolatile DAC4 Register
FFh
3FFh
FFFh
05h Volatile DAC5 Register
FFh
3FFh
FFFh
15h Nonvolatile DAC5 Register
FFh
3FFh
FFFh
06h Volatile DAC6 Register
FFh
3FFh
FFFh
16h Nonvolatile DAC6 Register
FFh
3FFh
FFFh
07h Volatile DAC7 Register
FFh
3FFh
FFFh
17h Nonvolatile DAC7 Register
FFh
3FFh
FFFh
08h VREF Register
0000h 0000h 0000h
18h Nonvolatile VREF Register
0000h 0000h 0000h
09h Power-Down Register
0000h 0000h 0000h
19h Nonvolatile Power-Down
Register
0000h 0000h 0000h
0Ah Gain and Status Register
0080h 0080h 0080h
1Ah Nonvolatile Gain Register
0000h 0000h 0000h
0Bh WiperLock™ Technology
Status Register
0000h 0000h 0000h
Volatile Memory address range
Note 1:
1Bh
Reserved(1)
—
—
—
Nonvolatile Memory address range
Reading a reserved memory location results in the SPI command error condition. The SDO pin will output all
‘0’s. Forcing the CS pin to the VIH state will reset the SPI interface.
DS20006362A-page 56
2020 Microchip Technology Inc.
MCP48FXBX4/8
4.2.6
WIPERLOCK TECHNOLOGY
To modify the Configuration bits, the HVC pin must be
forced to the VIHH state and then an enable or disable
command must be received for the desired pair of
DAC register addresses.
The MCP48FXBX4/8 WiperLock technology allows
application-specific device settings (DAC register and
configuration) to be secured without requiring the use
of an additional write-protect pin. There are two Configuration bits (DLn:CLn) for each DAC channel (DAC0
through DAC7).
Example: To modify the CL0 bit, the enable or disable
command specifies address 00h; while to modify the
DL0 bit, the enable or disable command specifies
address 10h.
Dependent on the state of the DLn:CLn Configuration
bits, WiperLock technology prevents the serial commands from the following actions on the DACn
registers and bits:
Note:
• Writing to the specified volatile DACn register
memory location
• Writing to the specified nonvolatile DACn register
memory location
• Writing to the specified volatile DACn
Configuration bits
• Writing to the specified nonvolatile DACn
Configuration bits
4.2.6.1
Each pair of these Configuration bits controls one of
the four modes.
TABLE 4-3:
During device communication, if the
device address/command combination is
invalid or an unimplemented address is
specified, the MCP48FXBX4/8 will command error that command byte. To reset
the serial interface state machine, the CS
pin must be driven to the Inactive state
(VIH) before returning to the Active state
(VIL or VIHH).
POR/BOR Operation with
WiperLock Technology Enabled
The WiperLock Technology state is not affected by a
POR/BOR event. A POR/BOR event will load the volatile
DACn register values with the nonvolatile or default
factory values (in case of volatile memory only devices).
WIPERLOCK™ TECHNOLOGY CONFIGURATION BITS – FUNCTIONAL DESCRIPTION
Register/Bits
DLn:CLn(1)
DACn Wiper
DACn Configuration(1)
Comments
Volatile
Nonvolatile
Volatile
Nonvolatile
11
Locked
Locked
Locked
Locked
All DACn registers are locked.
10
Locked
Locked
Unlocked
Locked
All DACn registers are locked, except for volatile
DACn Configuration registers. This allows
operation of Power-Down modes.
01
Unlocked
Locked
Unlocked
Locked
Volatile DACn registers are unlocked, nonvolatile
DACn registers are locked.
00
Unlocked
Unlocked
Unlocked
Unlocked
Note 1:
All DACn registers are unlocked.
The state of these Configuration bits (DLn:CLn) is reflected in the WLnB:WLnA bits, as shown in
Register 4-6. DAC Configuration bits include Voltage Reference Control bits (VRnB:VRnA), Power-Down
Control bits (PDnB:PDnA) and Output Gain bits (Gx).
2020 Microchip Technology Inc.
DS20006362A-page 57
MCP48FXBX4/8
4.2.7
DEVICE REGISTERS
Register 4-1 shows the format of the DAC Output
Value registers for both volatile and nonvolatile memory locations. These registers will be either 8 bits,
10 bits or 12 bits wide. The values are right justified.
REGISTER 4-1:
12-bit
DAC0 TO DAC7: DAC OUTPUT VALUE REGISTERS
(ADDRESSES 00h THROUGH 07h/10h THROUGH 17h; VOLATILE/NONVOLATILE)
U-0
U-0
U-0
U-0
—
—
—
—
D11
D10
(1)
(1)
—
—(1)
R/W-n R/W-n R/W-n R/W-n R/W-n R/W-n R/W-n R/W-n R/W-n R/W-n R/W-n R/W-n
10-bit
—
—
—
—
—
8-bit
—
—
—
—
—(1)
D09
D08
D07
D06
D05
D04
D03
D02
D01
D00
D09
D08
D07
D06
D05
D04
D03
D02
D01
D00
—(1)
—(1)
D07
D06
D05
D04
D03
D02
D01
D00
bit 15
bit 0
Legend:
R = Readable bit
-n = Value at POR
= 12-bit device
12-Bit
10-Bit
W = Writable bit
‘1’ = Bit is set
= 10-bit device
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
= 8-bit device
8-Bit
bit 15-12 bit 15-10 bit 15-8
Unimplemented: Read as ‘0’
bit 11-0
—
—
D11-D00: DAC Output Value – 12-bit devices
FFFh = Full-scale output value
7FFh = Midscale output value
000h = Zero scale output value
—
bit 9-0
—
D09-D00: DAC Output Value – 10-bit devices
3FFh = Full-scale output value
1FFh = Midscale output value
000h = Zero scale output value
—
—
bit 7-0
Note 1:
x = Bit is unknown
D07-D00: DAC Output Value – 8-bit devices
FFh = Full-scale output value
7Fh = Midscale output value
000h = Zero scale output value
Unimplemented bit, read as ‘0’.
DS20006362A-page 58
2020 Microchip Technology Inc.
MCP48FXBX4/8
Register 4-2 shows the format of the Voltage
Reference Control register. Each DAC has two bits to
control the source of the DAC’s voltage reference. This
register is for both volatile and nonvolatile memory
locations.
REGISTER 4-2:
R/W-n
Octal
Quad
VREF: VOLTAGE REFERENCE CONTROL REGISTER
(ADDRESSES 08h AND 18h; VOLATILE/NONVOLATILE)
R/W-n R/W-n R/W-n R/W-n R/W-n R/W-n R/W-n R/W-n R/W-n R/W-n R/W-n R/W-n R/W-n R/W-n R/W-n
VR7B VR7A VR6B VR6A VR5B VR5A VR4B VR4A VR3B VR3A VR2B VR2A VR1B VR1A VR0B VR0A
—(1)
—(1)
—(1)
—(1)
—(1)
—(1)
—(1)
—(1)
VR3B VR3A VR2B VR2A VR1B VR1A VR0B VR0A
bit 15
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
= Quad-channel device
= Octal-channel device
Octal
—
x = Bit is unknown
Quad
bit 15-8
Unimplemented: Read as ‘0’
bit 15-0
bit 7-0
VRnB:VRnA: DAC Voltage Reference Control
11 = VREF pin (buffered); VREF buffer enabled
10 = VREF pin (unbuffered); VREF buffer disabled
01 = Internal band gap (1.22V typical); VREF buffer enabled, VREF voltage driven when powered
down
00 = VDD (unbuffered); VREF buffer disabled
Use this state with Power-Down bits for lowest current.
Note 1:
Unimplemented bit, read as ‘0’.
2020 Microchip Technology Inc.
DS20006362A-page 59
MCP48FXBX4/8
Register 4-3 shows the format of the Power-Down
Control register. Each DAC has two bits to control the
Power-Down state of the DAC. This register is for both
volatile and nonvolatile memory locations.
REGISTER 4-3:
POWER-DOWN CONTROL REGISTER (ADDRESSES 09h, 19h;
VOLATILE/NONVOLATILE)
R/W-n R/W-n R/W-n R/W-n R/W-n R/W-n R/W-n R/W-n R/W-n R/W-n R/W-n R/W-n R/W-n R/W-n R/W-n R/W-n
Octal
Quad
PD7B PD7A PD6B PD6A PD5B PD5A PD4B PD4A PD3B PD3A PD2B PD2A PD1B PD1A PD0B PD0A
—(1)
—(1)
—(1)
—(1)
—(1)
—(1)
—(1)
—(1)
PD0B PD0A PD0B PD0A PD0B PD0A PD0B PD0A
bit 15
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
= Quad-channel device
= Octal-channel device
Octal
—
x = Bit is unknown
Quad
bit 15-8
Unimplemented: Read as ‘1’
bit 15-0
bit 7-0
PDnB:PDnA: DAC Power-Down Control(2)
11 = Powered down – VOUT is open circuit
10 = Powered down – VOUT is loaded with a 125 k resistor to ground
01 = Powered down – VOUT is loaded with a 1 k resistor to ground
00 = Normal operation (not powered down)
Note 1:
2:
Unimplemented bit, read as ‘0’.
See Table 5-4 for more details.
DS20006362A-page 60
2020 Microchip Technology Inc.
MCP48FXBX4/8
Register 4-4 shows the format of the volatile Gain
Control and System Status register. Each DAC has one
bit to control the gain of the DAC and three status bits.
REGISTER 4-4:
GAIN CONTROL AND SYSTEM STATUS REGISTER (ADDRESS 0Ah; VOLATILE)
U-0
U-0
U-0
U-0
U-0
U-0
POR EEWA
—
—
—
—
—
—
POR EEWA
—
—
—
—
—
R/W-n R/W-n R/W-n R/W-n R/W-n R/W-n R/W-n R/W-n R/C-1
Octal
G7
G6
G5
G4
G3
G2
G1
G0
Quad
—(1)
—(1)
—(1)
—(1)
G3
G2
G1
G0
R-0
bit 15
—
bit 0
Legend:
R = Readable bit
W = Writable bit
C = Clearable bit
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
= Quad-channel device
= Octal-channel device
Octal
—
U = Unimplemented bit, read as ‘0’
x = Bit is unknown
Quad
bit 15-12 Unimplemented: Read as ‘0’
bit 15-8
bit 11-8
Gn: DAC Channel n Output Driver Gain Control
1 = 2x gain
0 = 1x gain
bit 7
bit 7
POR: Power-on Reset (Brown-out Reset) Status bit
This bit indicates if a POR or BOR event has occurred since the last READ command of this
register. Reading this register clears the state of the POR status bit.
1 = A POR (BOR) event has occurred since the last read of this register; reading this register
clears this bit
0 = A POR (BOR) event has not occurred since the last read of this register
bit 6
bit 6
EEWA: EEPROM Write Active Status
This bit indicates if the EEPROM write cycle is occurring.
1 = An EEPROM write cycle is currently occurring; only serial commands to the volatile memory are allowed
0 = An EEPROM write cycle is NOT currently occurring
bit 5-0
bit 5-0
Unimplemented: Read as ‘0’
Note 1:
Unimplemented bit, read as ‘0’.
2020 Microchip Technology Inc.
DS20006362A-page 61
MCP48FXBX4/8
Register 4-5 shows the format of the nonvolatile Gain
Control register. Each DAC has one bit to control the
gain of the DAC.
REGISTER 4-5:
GAIN CONTROL REGISTER (ADDRESS 1Ah; NONVOLATILE)
R/W-n R/W-n R/W-n R/W-n R/W-n R/W-n R/W-n R/W-n
Octal
G7
G6
G5
G4
G3
G2
G1
Quad
—(1)
—(1)
—(1)
—(1)
G3
G2
G1
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
G0
—
—
—
—
—
—
—
—
G0
—
—
—
—
—
—
—
bit 15
—
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
= Quad-channel device
= Octal-channel device
Octal
—
x = Bit is unknown
Quad
bit 15-12 Unimplemented: Read as ‘0’
bit 15-8
bit 11-8
Gn: DACn Output Driver Gain Control bits
1 = 2x gain
0 = 1x gain
bit 7-0
bit 7-0
Unimplemented bits.
Note 1:
Unimplemented bit, read as ‘0’.
DS20006362A-page 62
2020 Microchip Technology Inc.
MCP48FXBX4/8
Register 4-6 shows the format of the DAC WiperLock
Technology Status register.
REGISTER 4-6:
R-0(1)
Octal
Quad
R-0(1)
R-0(1)
DAC WiperLock™ TECHNOLOGY STATUS REGISTER (ADDRESS 0Bh; VOLATILE)
R-0(1)
R-0(1)
R-0(1)
R-0(1)
R-0(1)
R-0(1)
R-0(1)
R-0(1)
R-0(1)
R-0(1)
R-0(1)
R-0(1)
R-0(1)
WL7B WL7A WL6B WL6A WL5B WL5A WL4B WL4A WL3B WL3A WL2B WL2A WL1B WL1A WL0B WL0A
—(2)
—(2)
—(2)
—(2)
—(2)
—(2)
—(2)
—(2)
WL3B WL3A WL2B WL2A WL1B WL1A WL0B WL0A
bit 15
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
= Quad-channel device
= Octal-channel device
x = Bit is unknown
Quad
Octal
—
bit 15-8
Unimplemented: Read as ‘0’
bit 15-0
bit 7-0
WLnB:WLnA: WiperLock™ Technology Status
These bits reflect the state of the DLn:CLn nonvolatile Configuration bits.
11 = DAC Wiper and DAC Configuration (volatile and nonvolatile registers) are locked
(DLn = CLn = Enabled)
10 = DAC Wiper (volatile and nonvolatile) and DAC Configuration (nonvolatile registers) are
locked (DLn = Enabled; CLn = Disabled)
01 = DAC Wiper (nonvolatile) and DAC Configuration (nonvolatile registers) are locked
(DLn = Disabled; CLn = Enabled)
00 = DAC Wiper and DAC Configuration are unlocked (DLn = CLn = Disabled)
Note 1:
POR value depends on the programmed values of the DLn:CLn Configuration bits. The devices are
shipped with a default DLn:CLn Configuration bit state of ‘0’.
Unimplemented bit, read as ‘0’.
2:
2020 Microchip Technology Inc.
DS20006362A-page 63
MCP48FXBX4/8
NOTES:
DS20006362A-page 64
2020 Microchip Technology Inc.
MCP48FXBX4/8
5.0
DAC CIRCUITRY
The functional blocks of the DAC include:
•
•
•
•
•
•
The Digital-to-Analog Converter circuitry converts a
digital value into its analog representation. The
description shows the functional operation of the device.
The DAC circuit uses a resistor ladder implementation.
Devices have up to eight DACs.
Figure 5-1 shows the functional block diagram for the
MCP48FXBX4/8 DAC circuitry.
Power-Down
Operation
Resistor Ladder
Voltage Reference Selection
Output Buffer/VOUT Operation
Internal Band Gap
Latch Pins (LATn)
Power-Down Operation
VDD
PDnB:PDnA and
VRnB:VRnA
Internal Band Gap
VDD
Voltage
Reference
Selection
VREF
VRnB:VRnA and
PDnB:PDnA
Band Gap
(1.22V typical)
VDD
PDnB:PDnA
VRnB:VRnA
A (RL)
RS(2n)
DAC
Output
Selection
Power-Down
Operation
VDD
PDnB:PDnA
RS(2n – 1)
VW
RS(2n – 2)
PDnB:PDnA
Gain
(1x or 2x)
RRL
(~120 k)
Output Buffer/VOUT
Operation
RS(2)
125 kΩ
RS(2n – 3)
VOUT
1 kΩ
VRL
Power-Down
Operation
RS(1)
B
Resistor Ladder
DAC Register Value
VW = ---------------------------------------------------------------------- VRL
# Resistor in Resistor Ladder
Where:
# Resistors in Resistor Ladder =
256 (MCP48FXB0X)
1024 (MCP48FXB1X)
4096 (MCP48FXB2X)
FIGURE 5-1:
MCP48FXBX4/8 DAC Module Block Diagram.
2020 Microchip Technology Inc.
DS20006362A-page 65
MCP48FXBX4/8
Resistor Ladder
The resistor ladder is a digital potentiometer with the B
Terminal internally grounded and the A Terminal
connected to the selected reference voltage (see
Figure 5-2). The volatile DAC register controls the
wiper position. The Wiper Voltage (VW) is proportional
to the DAC register value divided by the number of
Resistor Elements (RS) in the ladder (256, 1024 or
4096) related to the VRL voltage.
Equation 5-1 shows the calculation for the step
resistance:
EQUATION 5-1:
The output of the resistor network will drive the input of
an output buffer.
VRL
DAC
Register
PDnB:PDnA
RS(2n)
RW(1)
2n – 1
RS(2n – 1)
RW(1)
2n – 2
RS(2n – 2)
RW(1)
2n – 3
RW(1)
RS(2)
RW(1)
RS(1)
RW(1)
R RL
R S = ------------ 256
8-Bit Device
RRL
R S = --------------- 1024
10-Bit Device
RRL
R S = --------------- 4096
12-Bit Device
The maximum wiper position is 2n – 1,
while the number of resistors in the
resistor ladder is 2n. This means that
when the DAC register is at full scale,
there is one Resistor Element (RS)
between the wiper and the VRL voltage.
If the unbuffered VREF pin is used as the VRL voltage
source, this voltage source should have a low output
impedance.
VW
RS(2n – 3)
RRL
Note:
RS CALCULATION
2
1
When the DAC is powered down, the resistor ladder is
disconnected from the selected reference voltage.
5.2
Voltage Reference Selection
The resistor ladder has up to four sources for the
reference voltage. Two user control bits (VRnB:VRnA)
are used to control the selection with the selection connected to the VRL node (see Figure 5-3 and Figure 5-4).
0
VREF
Analog Mux
VRnB:VRnA
VDD
Reference
Selection
5.1
Band Gap
Note 1: The analog Switch Resistance (RW) does not
affect performance due to the voltage divider
configuration.
FIGURE 5-2:
Resistor Ladder Model.
The resistor network is made of these three parts:
• Resistor ladder (string of RS elements)
• Wiper switches
• DAC register decode
The Resistor Ladder (RRL) has a typical impedance of
approximately 120 k. This resistance may vary from
device to device by up to ±20%. Since this is a voltage
divider configuration, the actual RRL resistance does
not affect the output given a fixed voltage at VRL.
DS20006362A-page 66
VRL
Buffer
FIGURE 5-3:
Resistor Ladder Reference
Voltage Selection Block Diagram.
The four voltage source options for the resistor ladder
are:
1.
2.
3.
4.
VDD pin voltage.
Internal Voltage Reference (VBG).
VREF pin voltage unbuffered.
VREF pin voltage internally buffered.
2020 Microchip Technology Inc.
MCP48FXBX4/8
The selection of the voltage is specified with the volatile
VRnB:VRnA Configuration bits (see Register 4-2).
There are nonvolatile and volatile VRnB:VRnA Configuration bits. On a POR/BOR event, the state of the
nonvolatile VRnB:VRnA Configuration bits is latched
into the volatile VRnB:VRnA Configuration bits.
When the user selects the VDD as reference, the VREF
pin voltage is not connected to the resistor ladder.
VDD
VDD
5.2.2
UNBUFFERED MODE
The VREF pin voltage may be from VSS to VDD.
Note 1: The voltage source should have a low
output impedance. If the voltage source
has a high output impedance, then the
voltage on the VREF pin is lower than
expected. The resistor ladder has a
typical impedance of 140 k and a typical
capacitance of 29 pF.
2: If the VREF pin is tied to the VDD voltage,
the VDD mode (VRnB:VRnA = 00) is
recommended.
PDnB:PDnA and
VRnB:VRnA
5.2.3
PDnB:PDnA and
VRnB:VRnA
BAND GAP MODE
If the internal band gap is selected, then the external
VREF pin should not be driven and should only use
high-impedance loads.
Band Gap(1)
(1.227V typical)
+
VREF
VRL
–
VDD
The band gap output is buffered, but the internal
switches limit the current that the output should source
to the VREF pin. The resistor ladder buffer is used to
drive the band gap voltage for the cases of multiple
DAC outputs. This ensures that the resistor ladders are
always properly sourced when the band gap is
selected.
5.3
The Band Gap Voltage (VBG) is 1.22V
typical. The band gap output goes
through the buffer with a 2x gain to
create the VRL voltage. See Table 5-1
for additional information on the
band gap circuit.
FIGURE 5-4:
Reference Voltage Selection
Implementation Block Diagram.
If the VREF pin is selected, then a selection has to be
made between the Buffered and Unbuffered mode.
5.2.1
BUFFERED MODE
The VREF pin voltage may be from 0.01V to VDD – 0.04V.
The input buffer (amplifier) provides low offset voltage,
low noise and a very high input impedance, with only
minor limitations on the input range and frequency
response.
Note 1: Any variation or noises on the reference
source can directly affect the DAC output.
The reference voltage needs to be as
clean as possible for accurate DAC
performance.
2: If the VREF pin is tied to the VDD voltage,
the VDD mode (VRnB:VRnA = 00) is
recommended.
2020 Microchip Technology Inc.
The resistance of a Resistor Ladder (RRL) is targeted to
be 140 k (40 k), which means a minimum
resistance of 100 k.
The band gap selection can be used across the VDD
voltages while maximizing the VOUT voltage ranges.
For VDD voltages below the 2 × Gain × VBG voltage, the
output for the upper codes will be clipped to the VDD
voltage. Table 5-1 shows the maximum DAC register
code given device VDD and Gain bit setting.
TABLE 5-1:
5.5
2.7
DAC Gain
Note 1:
The internal band gap is designed to drive the resistor
ladder buffer.
VDD(3)
PDnB:PDnA and
VRnB:VRnA
Internal Band Gap
VOUT USING BAND GAP
Max DAC Code(1)
12-Bit 10-Bit 8-Bit
Comment
1
FFFh
3FFh
FFh VOUT(max) = 2.44V(2)
2
FFFh
3FFh
FFh VOUT(max) = 4.88V(2)
1
FFFh
3FFh
FFh VOUT(max) = 2.44V(2)
2
8CDh 233h
Note 1:
2:
3:
8Ch ~ 0 to 56% range
Without the VOUT pin voltage being
clipped.
When VBG = 1.22V typical.
Band gap performance achieves full
performance starting from a VDD of 2.0V.
DS20006362A-page 67
MCP48FXBX4/8
5.4
Output Buffer/VOUT Operation
The output driver buffers the Wiper Voltage (VW) of the
resistor ladder.
The DAC output is buffered with a low-power and precision output amplifier (op amp). This amplifier provides
a rail-to-rail output with low offset voltage and low
noise. The amplifier’s output can drive the resistive and
high capacitive loads without oscillation. The amplifier
provides a maximum load current, which is enough for
most programmable voltage reference applications.
See Section 1.0 “Electrical Characteristics” for the
specifications of the output amplifier.
Note:
The load resistance must be kept higher
than 5 k for the stable and expected
analog output (to meet electrical
specifications).
5.4.2
OUTPUT VOLTAGE
The volatile DAC register values, along with the
device’s Configuration bits, control the analog VOUT
voltage. The volatile DAC register’s value is unsigned
binary. The formula for the output voltage is given in
Equation 5-2. Table 5-5 shows examples of volatile
DAC register values and the corresponding theoretical
VOUT voltage for the MCP48FXBX4/8 devices.
EQUATION 5-2:
V RL DAC Register Value
VOUT = ---------------------------------------------------------------------- Gain
# Resistor in Resistor Ladder
Where:
# Resistors in R-Ladder = 4096 (MCP48FXB2X)
1024 (MCP48FXB1X)
256 (MCP48FXB0X)
Figure 5-5 shows the block diagram of the output driver
circuit.
The user can select the output gain of the output
amplifier. The gain options are:
a)
b)
Gain of 1, when either the VDD, External VREF or
Band Gap mode are used. In case of the Band
Gap mode, the effective gain is 2; see
Section 5.3 “Internal Band Gap”.
Gain of 2, when the External VREF or Internal
Band Gap modes are used. In case of the Band
Gap mode, the effective gain is 4; see
Section 5.3 “Internal Band Gap”.
VDD
Note:
The following events update the DAC register value,
and therefore, the analog Voltage Output (VOUT):
• POR
• BOR
• WRITE command
5.4.3
+
VOUT
–
FIGURE 5-5:
5.4.1
125 kΩ
PDnB:PDnA
1 kΩ
Gain
(1x or 2x)
Output Driver Block Diagram.
PROGRAMMABLE GAIN
The amplifier’s gain is controlled by the Gain (G)
Configuration bit (see Register 4-5) and the VRL
reference selection.
The volatile Gain bit value can be modified by:
• POR events
• BOR events
• SPI WRITE commands
DS20006362A-page 68
When Gain = 2 (VRL= VREF) and if
VREF > VDD/2, the VOUT voltage will be
limited to VDD. So if VREF = VDD, then the
VOUT voltage will not change for volatile
DAC register values midscale and
greater, since the op amp is at full-scale
output.
The VOUT voltage starts driving to the new value after
the event has occurred.
PDnB:PDnA
VW
CALCULATING OUTPUT
VOLTAGE (VOUT)
STEP VOLTAGE (VS)
The step voltage depends on the device resolution and
the calculated output voltage range. One LSb is
defined as the ideal voltage difference between two
successive codes. The step voltage can be easily calculated by using Equation 5-3 (DAC register value is
equal to 1). Theoretical step voltages are shown in
Table 5-2 for several VREF voltages.
EQUATION 5-3:
VS CALCULATION
VRL
VS = ---------------------------------------------------------------------- Gain
# Resistor in Resistor Ladder
Where:
# Resistors in R-Ladder = 4096 (12-bit)
1024 (10-bit)
256 (8-bit)
2020 Microchip Technology Inc.
MCP48FXBX4/8
TABLE 5-2:
THEORETICAL STEP
VOLTAGE (VS)(1)
VREF
5.0
2.7
1.8
1.5
1.0
1.22 mV 659 µV 439 µV 366 µV 244 µV 12-bit
VS 4.88 mV 2.64 mV 1.76 mV 1.46 mV 977 µV 10-bit
19.5 mV 10.5 mV 7.03 mV 5.86 mV 3.91 mV 8-bit
Note 1:
When Gain = 1x, VFS = VRL and VZS = 0V.
5.4.4
OUTPUT SLEW RATE
Figure 5-6 shows an example of the slew rate for the
VOUT pin. The slew rate can be affected by the characteristics of the circuit connected to the VOUT pin.
VOUT
VOUT(B)
VOUT(A)
DACn = A
DACn = B
Time
VOUT B – VOUT A
Slew Rate = -------------------------------------------------T
FIGURE 5-6:
5.4.4.1
DRIVING RESISTIVE AND
CAPACITIVE LOADS
The VOUT pin can drive up to 100 pF of capacitive load
in parallel with a 5 k resistive load (to meet electrical
specifications).
VOUT drops slowly as the load resistance decreases
after about 3.5 k. It is recommended to use a load with
RL greater than 5 k.
Driving large capacitive loads can cause stability
problems for voltage feedback op amps. As the load
capacitance increases, the feedback loop’s phase margin decreases and the closed-loop bandwidth is
reduced. This produces gain peaking in the frequency
response with overshoot and ringing in the step
response. That is, since the VOUT pin’s voltage does
not quickly follow the buffer’s input voltage (due to the
large capacitive load), the output buffer will overshoot
the desired target voltage. Once the driver detects this
overshoot, it compensates by forcing it to a voltage
below the target. This causes voltage ringing on the
VOUT pin.
When driving large capacitive loads with the output
buffer, a small Series Resistor (RISO) at the output (see
Figure 5-7) improves the output buffer’s stability (feedback loop’s phase margin) by making the output load
resistive at higher frequencies. The bandwidth will be
generally lower than the bandwidth with no capacitive
load.
VOUT Pin Slew Rate.
Small Capacitive Load
With a small Capacitive Load (CL), the output buffer’s
current is not affected, but the VOUT pin’s voltage is not
a step transition from one output value (DAC register
value) to the next output value. The change of the VOUT
voltage is limited by the output buffer’s characteristics,
so the VOUT pin voltage will have a slope from the old
voltage to the new one. This slope is fixed for the output
buffer and is referred to as the Buffer Slew Rate
(SRBUF).
5.4.4.2
5.4.5
Large Capacitive Load
With a larger capacitive load, the slew rate is determined
by two factors:
• The output buffer’s Short-Circuit Current (ISC)
• The VOUT pin’s external load
IOUT cannot exceed the output buffer’s Short-Circuit
Current (ISC), which fixes the output Buffer Slew Rate
(SRBUF). The voltage on the Capacitive Load, VCL,
changes at a rate proportional to IOUT, which fixes a
Capacitive Load Slew Rate (SRCL).
The VCL voltage slew rate is limited to the slower of the
output buffer’s internally set Slew Rate (SRBUF) and
the Capacitive Load Slew Rate (SRCL).
2020 Microchip Technology Inc.
VW
+
–
VOUT
RISO
VCL
RL
CL
Gain
FIGURE 5-7:
Circuit to Stabilize the
Output Buffer for Large Capacitive Loads (CL).
The RISO resistor value for your circuit needs to be
selected. The resulting frequency response peaking
and step response overshoot for this RISO resistor
value should be verified on the bench. Modify the
RISO’s resistance value until the output characteristics
meet your requirements.
A method to evaluate the system’s performance is to
inject a step voltage on the VREF pin and observe the
VOUT pin’s characteristics.
Note:
Additional insight into circuit design for
driving capacitive loads can be found in
AN884, “Driving Capacitive Loads with
Op Amps” (DS00884).
DS20006362A-page 69
MCP48FXBX4/8
5.5
Power-Down Operation
To allow the application to conserve power when the
DAC operation is not required, three Power-Down
modes are available. The Power-Down configuration
bits (PDnB:PDnA) control the power-down operation
(Figure 5-8 and Table 5-3). On devices with multiple
DACs, each DACs Power-Down mode is individually
controllable. All Power-Down modes do the following:
• Turn off most DAC module’s internal circuits
(output op amp, resistor ladder, etc.)
• Op amp output becomes high-impedance to the
VOUT pin
• Disconnect the resistor ladder from the Reference
Voltage (VRL)
• Retain the value of the volatile DAC register and
Configuration bits and the nonvolatile (EEPROM)
DAC register and Configuration bits
Depending on the selected Power-Down mode, the
following will occur:
• VOUT pin is switched to one of the two resistive
pull-downs (see Table 5-4):
- 125 k (typical)
- 1 k (typical)
• Op amp is powered down and the VOUT pin
becomes high-impedance
There is a delay (TPDE) between the PDnB:PDnA bits,
changing from ‘00’ to either ‘01’, ‘10’ or ‘11’, with the op
amp no longer driving the VOUT output and the pull-down
resistors sinking current.
PDnB:PDnA
VW
VOUT
FIGURE 5-8:
Diagram.
125 kΩ
PDnB:PDnA
1 kΩ
TABLE 5-3:
POWER-DOWN BITS AND
OUTPUT RESISTIVE LOAD
PDnB PDnA
Function
0
0
Normal operation
0
1
1 k resistor to ground
1
0
125 k resistor to ground
1
1
Open circuit
Table 5-4 shows the current sources for the DAC based
on the selected source of the DAC’s reference voltage
and if the device is in a normal operating mode or in
one of the Power-Down modes.
TABLE 5-4:
Device VDD
Current
Source
DAC CURRENT SOURCES
PDnB:A = 00,
VRnB:A =
PDnB:A 00,
VRnB:A =
00 01 10 11 00 01 10 11
Output Op Amp Y
Y
Y
N
N
Resistor
Ladder
Y
Y N(1) Y
N
N N(1) N
RL Op Amp
N
Y
N
Y
N
N
N
N
Band Gap
N
Y
N
N
N
Y
N
N
Note 1:
Y
N
N
Current is sourced from the VREF pin, not
the device VDD.
Section 7.0 “SPI Device Commands” describes the
SPI commands for writing the power-down bits. The command that can update the volatile PDnB:PDnA bits is a
WRITE command (normal and high voltage).
VDD
Gain
(1x or 2x)
The Power-Down bits are modified by using a WRITE
command to the volatile Power-Down register or a POR
event which transfers the nonvolatile Power-Down
register to the volatile Power-Down register.
Note:
The SPI serial interface circuit is not
affected by the Power-Down mode. This
circuit remains active in order to receive
any command that might come from the
master device.
VOUT Power-Down Block
In any of the Power-Down modes where the VOUT pin
is not externally connected (sinking or sourcing current), the power-down current will typically be 680 nA
for a quad DAC device. As the number of DACs
increases, the device’s power-down current will also
increase.
DS20006362A-page 70
2020 Microchip Technology Inc.
MCP48FXBX4/8
5.5.1
EXITING POWER-DOWN
When the device exits Power-Down mode, the
following occurs:
• Disabled circuits (op amp, resistor ladder, etc.)
are turned on
• The resistor ladder is connected to the selected
Reference Voltage (VRL)
• The selected pull-down resistor is disconnected
• The VOUT output will be driven to the voltage
represented by the volatile DAC register’s value
and Configuration bits
The VOUT output signal requires time as these circuits
are powered up and the output voltage is driven to the
specified value as determined by the volatile DAC
register and Configuration bits.
Note:
Since the op amp and resistor ladder are
powered off (0V), the op amp’s Input
Voltage (VW) can be considered 0V. There
is a delay (TPDD) between the
PDnB:PDnA bits updating to ‘00’ and the
op amp driving the VOUT output. The
op amp’s settling time (from 0V) needs to
be taken into account to ensure the VOUT
voltage reflects the selected value.
Any WRITE command where the PDnB:PDnA bits are
‘00’ will cause the device to exit the Power-Down mode.
5.6
DAC Registers, Configuration Bits
and Status Bits
The MCP48FXBX4/8 device family has both volatile
and nonvolatile (EEPROM) memory options. Table 4-2
shows the volatile and nonvolatile memory, and their
interaction due to a POR event.
There are five Configuration bits, DAC registers, and two
volatile status bits in both the volatile and nonvolatile
memory. The DAC registers (volatile and nonvolatile) will
be either twelve bits (MCP48FXB2X), ten bits
(MCP48FEB1X) or eight bits (MCP48FXB0X) wide.
When the device is first powered up, it automatically
uploads the EEPROM memory values or factory
default values (in case of MCP48FVBXX devices) to
the volatile memory. The volatile memory determines
the analog Output Voltage (VOUT) pin. After the device
is powered up, the user can update the memory.
This memory is read and written through the SPI interface. See Section 6.0 “SPI Serial Interface Module”
and Section 7.0 “SPI Device Commands” for more
details on reading and writing the device’s memory.
When the nonvolatile memory is written, the device
starts writing the EEPROM cell at the Acknowledge
pulse of the WRITE single memory location command.
Register 4-4 shows the operation of the device status
bits and Table 4-2 shows the factory default value of a
POR/BOR event for the device Configuration bits.
There are two status bits. These are only in volatile
memory and indicate the status of the device. The POR
bit indicates if the device VDD is above or below the
POR trip point. During normal operation, this bit should
be ‘1’. The EEWA bit indicates if an EEPROM write
cycle is in progress. While the EEWA bit is ‘1’ (during
the EEPROM writing), all commands are ignored,
except for the READ command.
2020 Microchip Technology Inc.
DS20006362A-page 71
MCP48FXBX4/8
5.7
Latch Pins (LATn)
The Latch pins control when the volatile DAC register
value is transferred to the DAC wiper. This is useful for
applications that need to synchronize the wiper(s)
updates to an external event, such as zero-crossing or
updates to the other wipers on the device. The LAT pin
functionality is asynchronous to the serial interface
operation.
Serial Shift Reg.
Register Address
WRITE Command
16 Clocks
Vol. DAC Register n
Transfer
LAT
Data
SYNC
(internal signal)
DAC Wiper n
When the LAT pin is high, transfers from the volatile DAC
register to the DAC wiper are inhibited. The volatile DAC
register value(s) can continue to update.
When the LAT pin is low, the volatile DAC register value
is transferred to the DAC wiper.
Note:
This allows the volatile DAC0 through
DAC7 registers to be updated while the
LATn pins are high, and to have outputs
synchronously updated as the LATn pins
are driven low.
Figure 5-9 shows the interaction of the LAT pin and the
loading of the DAC Wiper n (from the volatile DAC
register n). The transfers are level-driven. If the LAT pin
is held low, the corresponding DAC wiper is updated as
soon as the volatile DAC register value is updated.
The LAT pin allows the DAC wiper to be updated to
an external event and have multiple DAC
channels/devices updating at a common event.
LAT SYNC
Transfer
Data
Comment
1
1
0
No Transfer
1
0
0
No Transfer
0
1
1
Vol. DAC Register n DAC Wiper n
0
0
0
No Transfer
FIGURE 5-9:
LAT and DAC Interaction.
Since the DAC wiper n is updated from the volatile DAC
register n, all DACs that are associated with a given
LAT pin can be updated synchronously.
If the application does not require synchronization, then
this signal should be tied low.
Figure 5-10 shows two examples of using the LAT pin
to control when the Wiper register is updated relative to
the value of a sine wave signal.
Case 1: Zero-Crossing of Sine Wave to Update the Volatile DAC0 Register (using LAT pin)
Case 2: Fixed-Point Crossing of Sine Wave to Update the Volatile DAC0 Register (using LAT pin)
Indicates Where LAT Pin Pulses are Active (volatile DAC0 register updated)
FIGURE 5-10:
DS20006362A-page 72
LAT Pin Operation Example.
2020 Microchip Technology Inc.
MCP48FXBX4/8
TABLE 5-5:
Device
DAC INPUT CODE VS. CALCULATED ANALOG OUTPUT (VOUT) (VDD = 5.0V)
Volatile DAC
Register Value
1111 1111 1111
VRL
(1)
5.0V
MCP48FXB2X (12-bit)
2.5V
0111 1111 1111
0011 1111 1111
MCP48FEB1X (10-bit)
11 1111 1111
01 1111 1111
00 1111 1111
MCP48FXB0X (8-bit)
1111 1111
0111 1111
0011 1111
0000 0000
Note 1:
2:
3:
Equation
µV
5.0V/4096
1,220.7
1x
VRL (4095/4096) 1
4.998779
610.4
1x
VRL (4095/4096) 1
2.499390
2x(2)
VRL (4095/4096) 2)
4.998779
2.5V/4096
Equation
V
5.0V/4096
1,220.7
1x
VRL (2047/4096) 1)
2.498779
2.5V
2.5V/4096
610.4
1x
VRL (2047/4096) 1)
1.249390
2x(2)
VRL (2047/4096) 2)
2.498779
1,220.7
1x
VRL (1023/4096) 1)
1.248779
610.4
1x
VRL (1023/4096) 1)
0.624390
2x(2)
VRL (1023/4096) 2)
1.248779
5.0V
5.0V/4096
2.5V/4096
5.0V
5.0V/4096
1,220.7
1x
VRL (0/4096) * 1)
0
2.5V
2.5V/4096
610.4
1x
VRL (0/4096) * 1)
0
2x(2)
VRL (0/4096) * 2)
0
5.0V
5.0V/1024
4,882.8
1x
VRL (1023/1024) 1
4.995117
2.5V
2.5V/1024
2,441.4
1x
VRL (1023/1024) 1
2.497559
2x(2)
VRL (1023/1024) 2
4.995117
5.0V
5.0V/1024
4,882.8
1x
VRL (511/1024) 1
2.495117
2.5V
2.5V/1024
2,441.4
1x
VRL (511/1024) 1
1.247559
2x(2)
VRL (511/1024) 2
2.495117
4,882.8
1x
VRL (255/1024) 1
1.245117
2,441.4
1x
VRL (255/1024) 1
0.622559
2x(2)
VRL (255/1024) 2
1.245117
5.0V
2.5V
00 0000 0000
VOUT(3)
Gain
Selection(2)
5.0V
2.5V
0000 0000 0000
LSb
5.0V/1024
2.5V/1024
5.0V
5.0V/1024
4,882.8
1x
VRL (0/1024) 1
0
2.5V
2.5V/1024
2,441.4
1x
VRL (0/1024) 1
0
2x(2)
VRL (0/1024) 1
0
5.0V
5.0V/256
19,531.3
1x
VRL (255/256) 1
4.980469
2.5V
2.5V/256
9,765.6
1x
VRL (255/256) 1
2.490234
2x(2)
VRL (255/256) 2
4.980469
5.0V
5.0V/256
19,531.3
1x
VRL (127/256) 1
2.480469
2.5V
2.5V/256
9,765.6
1x
VRL (127/256) 1
1.240234
2x(2)
VRL (127/256) 2
2.480469
5.0V
5.0V/256
19,531.3
1x
VRL (63/256) 1
1.230469
2.5V
2.5V/256
9,765.6
1x
VRL (63/256) 1
0.615234
2x(2)
VRL (63/256) 2
1.230469
5.0V
5.0V/256
19,531.3
1x
VRL (0/256) 1
0
2.5V
2.5V/256
9,765.6
1x
VRL (0/256) 1
0
2x(2)
VRL (0/256) 2
0
VRL is the resistor ladder’s reference voltage. It is independent of the VRnB:VRnA selection.
Gain selection of 2x (Gx = 1) requires the voltage reference source to come from the VREF pin
(VRnB:VRnA = 10 or 11) and requires a VREF pin voltage (or VRL) ≤ VDD/2, or from the internal band gap
(VRnB:VRnA = 01).
These theoretical calculations do not take into account the offset, gain and nonlinearity errors.
2020 Microchip Technology Inc.
DS20006362A-page 73
MCP48FXBX4/8
NOTES:
DS20006362A-page 74
2020 Microchip Technology Inc.
MCP48FXBX4/8
6.0
SPI SERIAL INTERFACE
MODULE
The MCP48FXBX4/8 devices’ SPI serial interface
module supports the SPI serial protocol specification.
The command format and waveforms for the
MCP48FXBX4/8 are defined in Section 7.0 “SPI
Device Commands”.
6.1
Overview
This section discusses some of the specific
characteristics of the MCP48FXBX4/8’s serial interface
module.
The following sections discuss some of these
device-specific characteristics:
• SPI Serial Interface
• Interface Pins (CS, SCK, SDI, SDO and
LAT/HVC)
• Communication Data Rates
• POR/BOR
6.2
SPI Serial Interface
The MCP48FXBX4/8 devices support the SPI serial
protocol. This SPI operates in Slave mode (does not
generate the serial clock).
The SPI interface uses up to four pins. These are:
•
•
•
•
Typical SPI Interface Connections
MCP48FXBXX
SDO
SDI
SDI
SDO
SCK
SCK
GPIO
CS
GPIO
LAT/HVC
(Master)
FIGURE 6-1:
Diagram.
The HVC pin is high-voltage tolerant. To enter a HighVoltage Command, the HVC pin must be greater than
the VIHH voltage.
6.2.1
SPI MODES
The SPI module supports two (of the four) standard
SPI modes. These are Mode 0,0 and 1,1. The mode is
determined by the state of the SDI pin on the rising
edge of the first clock bit (of the 8-bit byte).
6.2.1.1
Mode 0,0
In Mode 0,0:
• SCK Idle state = low (VIL)
• Data are clocked in on the SDI pin on the rising
edge of SCK
• Data are clocked out on the SDO pin on the falling
edge of SCK
Mode 1,1
In Mode 1,1:
Typical SPI interfaces are shown in Figure 6-1. In the
SPI interface, the master’s output pin is connected to
the slave’s input pin, and the master’s input pin is
connected to the slave’s output pin.
Other Devices
An additional HVC pin is available for High-Voltage
Command support. High-Voltage Commands allow the
device to enable and disable nonvolatile Configuration
bits. Without a high voltage present, those bits are
inhibited from being modified.
6.2.1.2
CS – Chip Select
SCK – Serial Clock
SDI – Serial Data In (MOSI)
SDO – Serial Data Out (MISO)
Host
Controller
The MCP48FXBX4/8 SPI’s module supports two (of
the four) standard SPI modes. These are Mode 0,0
and 1,1. The SPI mode is determined by the state of
the SCK pin (VIH or VIL) when the CS pin transitions
from inactive (VIH) to active (VIL).
(Slave)
• SCK Idle state = high (VIH)
• Data are clocked in on the SDI pin on the rising
edge of SCK
• Data are clocked out on the SDO pin on the falling
edge of SCK
6.3
Interface Pins (CS, SCK, SDI, SDO
and LAT/HVC)
The operation of the five interface pins and the HighVoltage Command (HVC) pin is discussed in this
section. The pins are:
•
•
•
•
•
SDI (Serial Data In)
SDO (Serial Data Out)
SCK (Serial Clock)
CS (Chip Select)
LAT/HVC (High-Voltage Command)
The serial interface works on either 8-bit or 24-bit
boundaries depending on the selected command. The
Chip Select (CS) pin frames the SPI commands.
Typical SPI Interface Block
2020 Microchip Technology Inc.
DS20006362A-page 75
MCP48FXBX4/8
6.3.1
SERIAL DATA IN (SDI)
6.3.4
The Serial Data In (SDI) signal is the data signal into
the device. The value on this pin is latched on the
rising edge of the SCK signal.
6.3.2
SERIAL DATA OUT (SDO)
The Serial Data Out (SDO) signal is the data signal out
of the device. The value on this pin is driven on the
falling edge of the SCK signal.
Once the CS pin is forced to the active level (VIL or
VIHH), the SDO pin will be driven. The state of the
SDO pin is determined by the serial bit’s position in the
command, the command selected and if there is a
Command Error (CMDERR) state.
6.3.3
SERIAL CLOCK (SCK)
(SPI FREQUENCY OF OPERATION)
The SPI interface is specified to operate up to 20 MHz.
The actual clock rate depends on the configuration of
the system and the serial command used. Table 6-1
shows the SCK frequency for different configurations.
TABLE 6-1:
SCK FREQUENCY
Command
Memory Type Access
Nonvolatile
Memory
Volatile
Memory
Note 1:
2:
SDI, SDO
SDI, SDO
Read
Write,
Enable,
Disable
10 MHz
20 MHz(1,2)
10 MHz
20
MHz(2)
After a WRITE command, the internal
write cycle must be completed before the
next SPI command is received.
This is a design goal. The SDO pin
performance is believed to be the limiting
factor.
CS SIGNAL
The Chip Select (CS) signal is used to select the
device and frame a command sequence. To start a
command, or sequence of commands, the CS signal
must transition from the Inactive state (VIH) to an
Active state (VIL or VIHH).
After the CS signal has gone active, the SDO pin is
driven and the clock bit counter is reset.
Note: There is a required delay after the CS pin
goes active to the first edge of the SCK pin.
If an error condition occurs for an SPI command, then
the command byte’s Command Error (CMDERR) bit
(on the SDO pin) will be driven low (VIL). To exit the
error condition, the user must take the CS pin to the
VIH level.
When the CS pin returns to the Inactive state (VIH), the
SPI module resets (including the Address Pointer).
While the CS pin is in the Inactive state (VIH), the serial
interface is ignored. This allows the host controller to
interface to other SPI devices using the same SDI,
SDO and SCK signals.
6.3.5
HVC SIGNAL
The high-voltage capability of the HVC pin allows HighVoltage Commands. High-Voltage Commands allow the
device’s WiperLock technology and write-protect
features to be enabled and disabled.
6.4
Communication Data Rates
The MCP48FXBX4/8 devices support clock rates (bit
rate) of up to 20 MHz for WRITE commands and
10 MHz for READ commands.
For most applications, the write time will be considered
more important, since that is how the device operation
is controlled.
6.5
POR/BOR
On a POR/BOR event, the SPI serial interface module
state machine is reset, which means that the device’s
Memory Address Pointer is forced to 00h.
DS20006362A-page 76
2020 Microchip Technology Inc.
MCP48FXBX4/8
7.0
SPI DEVICE COMMANDS
Command Byte
The MCP48FXBX4/8 devices’ SPI command format
supports 32 memory address locations and four
commands:
AD AD AD AD AD C
4 3 2 1 0 1
The supported commands are shown in Table 7-1.
These commands allow for both single data or continuous data operation. Table 7-2 also shows the required
number of bit clocks for each command’s different mode
of operation.
7.1
COMMAND BITS OVERVIEW
# of Bits Normal or HV
Read Data
24 Bits Normal
00
Write Data
24 Bits Normal
01
Enable(1)
8 Bits
HV Only
10
Disable(1)
8 Bits
HV Only
Note 1:
7.2
Command Byte
Data Bytes
Data Word (2 bytes)
AD AD AD AD AD C
4 3 2 1 0 1
FIGURE 7-2:
8-Bit SPI Command Format.
Data bytes are only present in the READ and WRITE
commands. These commands concatenate the two
data bytes, after the command byte, for a 24-bit long
command (see Figure 7-2).
The 8-bit commands (see Figure 7-1) are used to modify the device Configuration bits (Section 7.9 “Enable
Configuration Bit (High Voltage)” and Section 7.10
“Disable Configuration Bit (High Voltage)”) while
the 24-bit commands (see Figure 7-2) are used to read
and write to the device registers (Section 7.8 “READ
Command (Normal and High Voltage)” and
Section 7.7 “WRITE Command (Normal and High
Voltage)”). These commands contain a command byte
and two data bytes.
Legend:
X Reserved
As the command byte is being loaded into the device (on
the SDI pin), the device’s SDO pin is driving. The SDO pin
will output high bits for the first seven bits of that command. On the 8th bit, the SDO pin will output the
CMDERR bit state (see Section 7.6 “Error Condition”).
High-voltage enable and disable commands on selected nonvolatile memory
locations.
Command Byte
D
Data Bits
nn
The device memory is accessed when the master
sends a proper command byte to select the desired
operation. The memory location getting accessed is
contained in the command byte’s AD4:AD0 bits. The
action desired is contained in the command byte’s
C1:C0 bits; see Table 7-2. C1:C0 determines if the
desired memory location will be read, written, enabled
or disabled.
Normal serial commands are those where the HVC pin
is driven to either VIH or VIL. With high-voltage serial
commands, the HVC pin is driven to VIHH.
11
C
Command Bits
n
The command byte has three fields: the address, the
command and one reserved bit (see Figure 7-1).
• Normal Serial Commands
• High-Voltage Serial Commands
Command
AD
Memory Address
n
FIGURE 7-1:
Commands may have two modes. These are:
C1:C0 Bit
States
X
Legend:
• WRITE command (C1:C0 = 00)
• READ command (C1:C0 = 11)
• Enable Configuration bit (high voltage,
HVC = VIHH):
- Enable Configuration bit (C1:C0 = 10)
- Disable Configuration bit (C1:C0 = 01)
TABLE 7-1:
C
0
C
0
X
AD
Memory Address
n
X
X
X
X
D D D D
11 10 09 08
C
Command Bits
n
D D D D D D D D
07 06 05 04 03 02 01 00
D
Data Bits
nn
X Reserved
24-Bit SPI Command Format.
2020 Microchip Technology Inc.
DS20006362A-page 77
MCP48FXBX4/8
TABLE 7-2:
SPI COMMANDS – OVERVIEW AND COMMAND RATE
Command
Operation
Code
HV
Mode(1)
C1
C0
0
0
No(3)
Single
0
0
No(3)
Continuous
1
1
No(3)
Single
1
1
No(3)
Continuous
Enable Configuration
Bit (High Voltage)
1
0
Yes
Single
1
0
Yes
Continuous
Disable Configuration
Bit (High Voltage)
0
1
Yes
Single
0
1
Yes
Continuous
WRITE Command
READ Command(4)
Note 1:
2:
3:
4:
5:
7.3
Estimated Peak
Command Rate
(Commands/ms)(5)
Comments
1 MHz 10 MHz 20 MHz
24
24 * n
24
41
416
833
125
1250
2500
24 * n
Read frequency can
be up to 10 MHz
8
8*n
8
8*n
Nonvolatile registers can only use the Single mode.
“n” indicates the number of times the command operation is to be repeated.
If the state of the HVC pin is VIHH, then the command is ignored, but a Command Error condition
(CMDERR) will NOT be generated.
This command is used to determine when an EEPROM programming cycle is complete.
The actual voltage output update rate depends on several factors, such as output settling time, code,
reference voltage or load impedance.
Continuous Commands
The devices support the ability to execute commands
continuously. While the CS pin is in the Active state
(VIL), any sequence of valid commands may be
received.
The following example is a valid sequence of events:
1.
2.
3.
4.
5.
# of Bit
Clocks(2)
CS pin is driven active (VIL).
READ command.
WRITE command (volatile memory).
WRITE command (nonvolatile memory).
CS pin is driven inactive (VIH).
Note 1: It is recommended that while the CS pin is
active, only one type of command should
be issued. When changing commands, it
is advisable to take the CS pin inactive,
then force it back to the Active state.
2: Long command strings should be broken
down into shorter command strings. This
reduces the probability of noise on the
SCK pin, corrupting the desired SPI
command string.
7.4
Commands to Modify the Device
Configuration Bits
The MCP48FXBX4/8 devices support two commands,
which are used to program the device’s Configuration
bits. These commands require a High Voltage (VIHH) on
the HVC pin. The commands are:
• Enable Configuration Bit (High Voltage)
• Disable Configuration Bit (High Voltage)
The Configuration bits are used to inhibit the DAC
values from inadvertent modification. High voltage is
required to change the state of these bits if/when the
DAC values need to be modified.
7.5
High-Voltage Command (HVC)
Signal
The High-Voltage Command (HVC) signal is used to
indicate that the command or sequence of commands
are in the High-Voltage mode. Signals higher than VIHH
(~9.0V) on the LAT/HVC pin puts the device into HighVoltage mode. High-voltage commands allow the
device’s WiperLock technology and write-protect
features to be enabled and disabled.
Note 1: There is a required delay after the HVC
pin is driven to the VIHH level on the first
edge of the SCK pin.
DS20006362A-page 78
2020 Microchip Technology Inc.
MCP48FXBX4/8
7.6
Error Condition
The Command Error (CMDERR) bit indicates if the five
Address bits received (AD4:AD0) and the two Command bits received (C1:C0) are a valid combination (see
Figures 7-1 and 7-2). The CMDERR bit is high if the
combination is valid and low if the combination is invalid.
The Command Error bit will also be low if a write to a
nonvolatile address has been specified and another
SPI command occurs before the CS pin is driven
inactive (VIH).
SPI commands that do not have a multiple of eight
clocks are ignored.
Once an error condition has occurred, any following
commands are ignored. All following SDO bits will be
low until the CMDERR condition is cleared by forcing
the CS pin to the Inactive state (VIH).
7.6.1
ABORTING A TRANSMISSION
All SPI transmissions must have the correct number of
SCK pulses to be executed. The command is not
executed until the complete number of clocks is
received. Some commands also require the CS pin to
be forced inactive (VIH). If the CS pin is forced to the
Inactive state (VIH), the serial interface is reset. Partial
commands are not executed.
SPI is more susceptible to noise than other bus
protocols. The most likely case is that noise corrupts
the value of the data being clocked into the
MCP48FXBX4/8 or the SCK pin is injected with extra
clock pulses. This may cause data to be corrupted in
the device, or a Command Error to occur, since the
address and command bits were not a valid combination. The extra SCK pulse will also cause the SPI data
(SDI) and clock (SCK) to be out of sync. Forcing the
CS pin to the Inactive state (VIH) resets the serial interface. The SPI interface will ignore activity on the SDI
and SCK pins until the CS pin transition to the Active
state is detected (VIH to VIL or VIH to VIHH).
Note 1: When the MCP48FXBX4/8 devices do not
receive data, it is recommended that the
CS pin be forced to the Inactive Level (VIL).
2: It is also recommended that long continuous command strings be broken down
into single commands or shorter continuous command strings. This reduces the
probability of noise on the SCK pin
corrupting the desired SPI commands.
2020 Microchip Technology Inc.
7.7
WRITE Command
(Normal and High Voltage)
WRITE commands are used to transfer data to the
desired memory location (from the host controller). The
WRITE command can be issued to both the volatile and
nonvolatile memory locations.
WRITE commands can be structured as either single or
continuous.
The format of the command is shown in Figure 7-3
(single) and Figure 7-6 (continuous).
A WRITE command to a volatile memory location
changes that location after a properly formatted WRITE
command has been received.
A WRITE command to a nonvolatile memory location
starts an EEPROM write cycle only after a properly formatted WRITE command has been received and the
CS pin transitions to the Inactive state (VIH).
Note 1: Writes to certain memory locations
depend on the state of the WiperLock™
technology status bits.
2: During device communication, if an
unimplemented address is specified, then
the MCP48FXBX4/8 will generate a
Command Error state. To reset the SPI
state machine, the CS pin must transition
to the Inactive state (VIH).
7.7.1
SINGLE WRITE TO VOLATILE
MEMORY
The write operation requires that the CS pin be in the
Active state (VIL). Typically, the CS pin will be in the
Inactive state (VIH) and it is driven to the Active state
(VIL). The 24-bit WRITE command (command byte and
data bytes) is then clocked in on the SCK and SDI pins.
Once all 24 bits have been received, the specified
volatile address is updated. A write will not occur if the
WRITE command is not exactly 24 clock pulses. This
protects against system issues corrupting the
nonvolatile memory locations.
Figures 7-4 and 7-5 show the waveforms for a single
write (depending on the SPI mode).
DS20006362A-page 79
MCP48FXBX4/8
7.7.2
SINGLE WRITE TO NONVOLATILE
MEMORY
7.7.3
The sequence to write to a single nonvolatile memory
location is the same as a single write to volatile memory,
with the exception that after the CS pin is driven inactive
(VIH), the EEPROM Write Cycle (tWC) is started. A write
cycle will not start if the WRITE command is not exactly
24 clock pulses. This protects against system issues
corrupting the nonvolatile memory locations.
A Continuous Write mode of operation is possible when
writing to the device’s volatile memory registers (see
Table 7-3). Figure 7-6 shows the sequence for three
continuous writes. The writes do not need to be to the
same volatile memory address.
TABLE 7-3:
Once a WRITE command to a nonvolatile memory
location has been received, no other SPI commands
should be received before the CS pin transitions to the
Inactive state (VIH) or the current SPI command will
have a Command Error (CMDERR) occur.
After the CS pin is driven inactive (VIH), the serial
interface may immediately be re-enabled by driving
the CS pin to the Active state (VIL).
During an EEPROM write cycle, access to the volatile
memory is allowed when using the appropriate command sequence. Commands that address nonvolatile
memory are ignored until the EEPROM Write Cycle
(tWC) completes. This allows the host controller to
operate on the volatile DAC registers.
Note:
CONTINUOUS WRITES TO
VOLATILE MEMORY
VOLATILE MEMORY
ADDRESSES
Address
Quad-Channel
Octal-Channel
00h-03h
04h-07h
08h
09h
0Ah
Yes
No
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
7.7.4
CONTINUOUS WRITES TO
NONVOLATILE MEMORY
Continuous writes to nonvolatile memory are not
allowed and attempts to do so will result in a
Command Error (CMDERR) condition.
The EEWA status bit indicates if an
EEPROM write cycle is active (see
Register 4-4).
7.7.5
HIGH-VOLTAGE COMMAND (HVC)
SIGNAL
The High-Voltage Command (HVC) signal is used to
indicate that the command or sequence of commands
are in the high-voltage operational state. HVC
commands allow the device’s WiperLock technology
and write-protect features to be enabled and disabled.
Note:
Writes to a volatile DAC register will not
transfer to the output register until the LAT
(HVC) pin is transitioned from the VIHHEN
voltage to a VIL voltage.
CMDERR
12-bit data
SDI
SDO
AD AD AD AD AD C
4 3 2 1 0 1
C
0
X
10-bit data
8-bit data
X
X
X
X
D D D D D D D D D D D D
11 10 09 08 07 06 05 04 03 02 01 00
*
*
*
*
*
0
0
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
X
X
X
X
X
X
X
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1 Valid(2)
X
X
X
X
X
X
X
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0 Invalid(3)
Note 1:
2:
3:
For WRITE commands addressing the DAC Wiper registers, the data bits depend on the resolution of the
device: 12-bit = D11:D00, 10-bit = D09:D00 and 8-bit = D07:D00. Data are right justified for easy host
controller operation (no data manipulation before transmitting the desired value). The unimplemented bits
are ignored.
After a valid memory address and WRITE command byte are received (CMDERR = 1), all the following
SDO bits will be output as ‘1’.
If an error condition occurs (CMDERR = 0), all the following SDO bits will be output as ‘0’ until the
CMDERR condition is cleared (the CS pin is forced to the Inactive state).
FIGURE 7-3:
DS20006362A-page 80
Write Single Memory Location Command – SDI and SDO States.(1)
2020 Microchip Technology Inc.
MCP48FXBX4/8
VIHH
HVC(1)
VIH
CS
Note: HVC must be at VIHH before the start of a WRITE command and only lowered to VIH or VIL after the last bit of the 24-bit command.
VIH
VIL
SCK
00
AD4
SDI
01
AD3
02
AD2
03
AD1
04
AD0
05
C1
06
C0
07
X
08
D15
09
20
D14
21
D03
SDO
22
D02
D01
23
D00
CMDERR
Input
Sample
Note 1:
If the state of the HVC pin is VIHH, then the command is ignored, but a Command Error condition (CMDERR) will NOT be generated.
FIGURE 7-4:
24-Bit WRITE Command (C1:C0 = 00) – SPI Waveform (Mode 1,1).
VIHH
HVC(1)
VIH
CS VIH
Note: HVC must be at VIHH before the start of a WRITE command and only lowered to VIH or VIL after the last bit of the 24-bit command.
VIL
SCK
00
AD4
SDI
01
AD3
SDO
02
AD2
03
AD1
04
AD0
05
C1
06
C0
07
X
08
D15
09
D14
19
20
D03
21
22
D02
D01
23
D00
CMDERR
Input
Sample
Note 1:
If the state of the HVC pin is VIHH, then the command is ignored, but a Command Error condition (CMDERR) will NOT be generated.
FIGURE 7-5:
24-Bit WRITE Command (C1:C0 = 00) – SPI Waveform (Mode 0,0).
2020 Microchip Technology Inc.
DS20006362A-page 81
MCP48FXBX4/8
CMDERR
12-bit data
AD AD AD AD AD C
SDI 4 3 2 1 0 1
* * * * * 0
10-bit data
8-bit data
C
0
X
X
X
X
X
D D D D D D D D D D D D
11 10 09 08 07 06 05 04 03 02 01 00
0
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
(1)
X
X
X
X
X
X
X
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1 Valid(2)
X
X
X
X
X
X
X
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0 Invalid(3)
AD AD AD AD AD C
SDI 4 3 2 1 0 1
* * * * * 0
C
0
X
X
X
X
X
D D D D D D D D D D D D
11 10 09 08 07 06 05 04 03 02 01 00
0
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
SDO
(1)
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1 Valid(2)
0
0
0
0
0
0
(4)
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0 Invalid(3)
AD AD AD AD AD C
SDI 4 3 2 1 0 1
* * * * * 0
C
0
X
X
X
X
X
D D D D D D D D D D D D
11 10 09 08 07 06 05 04 03 02 01 00
0
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
1
SDO (3)
1
SDO (3)
Note 1:
2:
3:
4:
(1)
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1 Valid(2)
0
0
0
0
0
0
(4)
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0 Invalid(3)
For WRITE commands addressing the DAC Wiper registers, the data bits depend on the resolution of the
device: 12-bit = D11:D00, 10-bit = D09:D00, and 8-bit = D07:D00. Data are right justified for easy host
controller operation (no data manipulation before transmitting the desired value). The unimplemented
bits are ignored.
After a valid memory address and WRITE command byte are received (CMDERR = 1), all the following
SDO bits will be output as ‘1’.
If an error condition occurs (CMDERR = 0), all the following SDO bits will be output as ‘0’ until the
CMDERR condition is cleared (the CS pin is forced to the Inactive state).
This CMDERR bit will be forced to ‘0’, regardless if this Address+Command combination is valid. This
command will not be completed and requires the CS pin to return to VIH to clear the CMDERR
condition.
FIGURE 7-6:
DS20006362A-page 82
Continuous WRITE Commands (Volatile Memory Only).
2020 Microchip Technology Inc.
MCP48FXBX4/8
7.8
READ Command
(Normal and High Voltage)
The READ command formats include:
• Single Read
• Continuous Reads
The READ command is a 24-bit command and is used
to transfer data from the specified memory location to
the host controller. The READ command can be issued
to both the volatile and nonvolatile memory locations.
The format of the command, as well as an example of
SDI and SDO data, are shown in Figure 7-7.
7.8.1
LAT PIN INTERACTION
During a READ command of the DACn registers, if the
LAT pin transitions from VIH to VIL, then the read data
may be corrupted. This is due to the fact that the data
being read are the output value and not the DAC
register value. The LAT pin transition causes an update
of the output value. Based on the DAC output value,
the DACn register value and the Command bit where
the LAT pin transitions, the value being read could be
corrupted.
The first seven bits of the READ command determine
the address and the command. The 8th clock will output the CMDERR bit on the SDO pin. By means of the
remaining 16 clocks, the device will transmit the data
bits of the specified address (AD4:AD0).
During an EEPROM write cycle (write to nonvolatile
memory location or enable/disable Configuration bit
command), the READ command can only read the
volatile memory locations. By reading the Status
register (0Ah), the host controller can determine when
the write cycle has been completed (via the state of the
EEWA bit).
If LAT pin transitions occur during a read of the DACn
register, it is recommended that sequential reads be
performed until the two most recent read values match.
Then the most recent read data are good.
7.8.2
SINGLE READ
The READ command operation requires that the
CS pin be in the Active state (VIL). Typically, the CS
pin will be in the Inactive state (VIH) and is driven to
the Active state (VIL). The 24-bit READ command
(command byte and data byte) is then clocked in on
the SCK and SDI pins. The SDO pin starts driving data
on the 8th bit (CMDERR bit) and the addressed data
come out on the 9th through 24th clocks.
Note 1: During device communication, if an unimplemented address is specified, then the
MCP48FXBX4/8 will command error that
byte. To reset the SPI state machine, the
CS pin must be driven to the VIH state.
2: If the LAT pin is high (VIH), reads of the
volatile DAC register read the output
value, not the internal register.
3: The READ commands operate the same
regardless of the state of the High-Voltage
Command (HVC) signal.
CMDERR
12-bit data
AD AD AD AD AD C
SDI 4 3 2 1 0 1
* * * * * 1
SDO
C
0
X
10-bit data
8-bit data
X
X
X
X
D D D D D D D D D D D D
11 10 09 08 07 06 05 04 03 02 01 00
1
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
X
X
X
X
X
X
X
1
0
0
0
0
d
d
d
d
d
d
d
d
d
d
d
d Valid(1)
X
X
X
X
X
X
X
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0 Invalid(2)
Note 1:
2:
The Data bits depend on the resolution of the device: 12-bit = D11:D00, 10-bit = D09:D00, and
8-bit = D07:D00. The unimplemented bits are output as ‘0’ and data are right justified for easy host
controller operation (no data manipulation after reading the register value).
If an error condition occurs (CMDERR = 0), all the following SDO bits will be output as ‘0’ until the
CMDERR condition is cleared (the CS pin is forced to the Inactive state).
FIGURE 7-7:
READ Command – SDI and SDO States.
2020 Microchip Technology Inc.
DS20006362A-page 83
MCP48FXBX4/8
7.8.3
CONTINUOUS READS
Figure 7-8 shows the sequence for three continuous
reads. The reads do not need to be to the same
memory address.
Continuous reads format allows the device’s memory
to be read quickly. Continuous reads are possible to all
memory locations. If a nonvolatile memory write cycle
is occurring, then READ commands may only access
the volatile memory locations.
This is useful in reading the System Status register
(0Ah) to determine if an EEPROM write cycle is
complete (EEWA bit).
CMDERR
12-bit data
AD AD AD AD AD C
SDI 4 3 2 1 0 1
* * * * * 0
C
0
X
10-bit data
8-bit data
X
X
X
D D D D D D D D D D D D
X
11 10 09 08 07 06 05 04 03 02 01 00
0
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
X
X
X
X
X
X
X
1
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1 Valid(1)
X
X
X
X
X
X
X
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0 Invalid(2)
AD AD AD AD AD C
SDI 4 3 2 1 0 1
* * * * * 0
C
0
X
X
X
X
X
D D D D D D D D D D D D
11 10 09 08 07 06 05 04 03 02 01 00
0
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
1
1
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1 Valid(1)
0
0
(3)
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0 Invalid(2)
AD AD AD AD AD C
SDI 4 3 2 1 0 1
* * * * * 0
C
0
X
X
X
X
X
D D D D D D D D D D D D
11 10 09 08 07 06 05 04 03 02 01 00
0
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
1
1
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1 Valid(1)
0
(3)
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0 Invalid(2)
SDO
SDO
SDO
1
0
1
0
Note 1:
2:
3:
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1
0
The data bits depend on the resolution of the device: 12-bit = D11:D00, 10-bit = D09:D00, and
8-bit = D07:D00. The unimplemented bits are output as ‘0’ and data are right justified for easy host
controller operation (no data manipulation after reading the register value).
If an error condition occurs (CMDERR = 0), all the following SDO bits will be output as ‘0’ until the
CMDERR condition is cleared (the CS pin is forced to the Inactive state).
The CMDERR bit will be forced to ‘0’, regardless if this Address+Command combination is valid. This
command will not be completed and requires the CS pin to return to VIH to clear the CMDERR
condition.
FIGURE 7-8:
DS20006362A-page 84
READ Command – Continuous Read Sequence.
2020 Microchip Technology Inc.
MCP48FXBX4/8
VIHH
HVC(1)
VIH
Note: HVC must be at VIHH before the start of a WRITE command and only lowered to VIH or VIL after the last bit of the 24-bit command.
CS VIH
VIL
SCK
00
AD4
SDI
01
AD3
02
AD2
03
AD1
04
AD0
05
C1
06
C0
07
X
08
D15
09
20
D03
D14
SDO
21
22
D02
D01
23
D00
CMDERR
Input
Sample
Note 1:
If the state of the HVC pin is VIHH, then the command is ignored, but a Command Error condition (CMDERR) will NOT be generated.
FIGURE 7-9:
24-Bit READ Command (C1:C0 = 11) – SPI Waveforms (Mode 1,1).
VIHH
HVC(1)
VIH
CS VIH
Note: HVC must be at VIHH before start of a WRITE command and only lowered to VIH or VIL after the last bit of the 24-bit command.
VIL
SCK
00
AD4
SDI
01
AD3
SDO
02
AD2
03
AD1
04
AD0
05
C1
06
C0
07
X
08
D15
09
D14
19
20
D03
21
22
D02
D01
23
D00
CMDERR
Input
Sample
Note 1:
If the state of the HVC pin is VIHH, then the command is ignored, but a Command Error condition (CMDERR) will NOT be generated.
FIGURE 7-10:
24-Bit READ Command (C1:C0 = 11) – SPI Waveforms (Mode 0,0).
2020 Microchip Technology Inc.
DS20006362A-page 85
MCP48FXBX4/8
7.9
Enable Configuration Bit
(High Voltage)
During an EEPROM write cycle, only serial commands
to volatile memory are accepted. All other serial commands are ignored until the EEPROM Write Cycle (tWC)
completes. This allows the host controller to operate on
the volatile DAC, the volatile VREF, Power-Down, Gain
and Status, and WiperLock Technology Status registers.
The EEWA bit in the Status register indicates the status
of the EEPROM write cycle.
CMDERR
Figure 7-11 shows the formats for a single enable
Configuration bit command. The command will only
start the EEPROM Write Cycle (tWC) after a properly
formatted command has been received.
AD AD AD AD AD C
4 3 2 1 0 1
C
0
X
AD AD AD AD AD C
4 3 2 1 0 1
C
0
X
AD AD AD AD AD C
4 3 2 1 0 1
C
0
X
SDI *
*
*
*
*
1
0
*
*
*
*
*
*
1
0
*
*
*
*
*
*
1
0
*
X
X
X
X
X
X
X
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1 Valid(1)
X
X
X
X
X
X
X
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0 Invalid(2)
SDO
Note 1:
2:
If an error condition occurs (CMDERR = 0), all the following SDO bits will be low until the CMDERR
condition is cleared (the CS pin is forced to the Inactive state).
The CMDERR bit will be forced to ‘0’, regardless if this Address+Command combination is valid. This
command will not be completed and requires the CS pin to return to VIH to clear the CMDERR
condition.
FIGURE 7-11:
Enable Command Sequence.
VIHH
HVC
VIH
VIH
CS
SCK
SDI
SDO
VIL
00
AD4
01
AD3
02
AD2
03
AD1
04
AD0
05
C1
06
C0
07
X
CMDERR
Input
Sample
FIGURE 7-12:
DS20006362A-page 86
8-Bit Enable Command (C1:C0 = 10) – SPI Waveforms (Mode 1,1).
2020 Microchip Technology Inc.
MCP48FXBX4/8
VIHH
HVC
VIH
VIH
CS
VIL
SCK
00
01
AD4
SDI
AD3
02
04
03
AD2
AD1
05
AD0
C1
06
07
C0
X
SDO
CMDERR
Input
Sample
FIGURE 7-13:
7.10
8-Bit Enable Command (C1:C0 = 10) – SPI Waveforms (Mode 0,0).
Disable Configuration Bit
(High Voltage)
During an EEPROM write cycle, only serial commands
to volatile memory are accepted. All other serial
commands are ignored until the EEPROM Write Cycle
(tWC) completes. This allows the host controller to operate on the volatile DAC, the volatile VREF, Power-Down,
Gain and Status, and WiperLock Technology Status
registers. The EEWA bit in the Status register indicates
the status of an EEPROM write cycle.
CMDERR
Figure 7-14 shows the formats for a single disable
Configuration bit command. The command will only
start an EEPROM Write Cycle (tWC) after a properly
formatted command has been received.
AD AD AD AD AD C
4 3 2 1 0 1
C
0
X
AD AD AD AD AD C
4 3 2 1 0 1
C
0
X
AD AD AD AD AD C
4 3 2 1 0 1
C
0
X
SDI *
*
*
*
*
0
1
*
*
*
*
*
*
0
1
*
*
*
*
*
*
0
1
*
X
X
X
X
X
X
X
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1 Valid(1)
X
X
X
X
X
X
X
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0 Invalid(2)
SDO
Note 1:
2:
If an error condition occurs (CMDERR = 0), all the following SDO bits will be low until the CMDERR
condition is cleared (the CS pin is forced to the Inactive state).
The CMDERR bit will be forced to ‘0’, regardless if this Address+Command combination is valid. This
command will not be completed and requires the CS pin to return to VIH to clear the CMDERR
condition.
FIGURE 7-14:
Disable Command Sequence.
2020 Microchip Technology Inc.
DS20006362A-page 87
MCP48FXBX4/8
VIHH
HVC
VIH
VIH
CS
VIL
SCK
00
AD4
SDI
01
AD3
02
AD2
03
AD1
04
AD0
05
C1
06
C0
SDO
07
X
CMDERR
Input
Sample
FIGURE 7-15:
8-Bit Disable Command (C1:C0 = 01) – SPI Waveforms (Mode 1,1).
VIHH
HVC
VIH
VIH
CS
SCK
SDI
SDO
VIL
00
AD4
01
AD3
02
AD2
03
AD1
04
AD0
05
C1
06
C0
07
X
CMDERR
Input
Sample
FIGURE 7-16:
DS20006362A-page 88
8-Bit Disable Command (C1:C0 = 01) – SPI Waveforms (Mode 0,0).
2020 Microchip Technology Inc.
MCP48FXBX4/8
APPLICATIONS INFORMATION
Since the devices include a nonvolatile EEPROM
memory, the user can utilize these devices for
applications that require the output to return to the
previous setup value on subsequent power-ups.
8.1
VDD
VDD
C1
Any noise induced on the VDD line can affect the DAC
performance. Typical applications will require a bypass
capacitor in order to filter out high-frequency noise on
the VDD line. The noise can be induced onto the power
supply’s traces or as a result of changes on the DAC output. The bypass capacitor helps to minimize the effect of
these noise sources on signal integrity. Figure 8-1
shows an example of using two bypass capacitors (a
10 µF tantalum capacitor and a 0.1 µF ceramic capacitor) in parallel on the VDD line. These capacitors should
be placed as close to the VDD pin as possible (within
4 mm). If the application circuit has separate digital and
analog power supplies, the VDD and VSS pins of the
device should reside on the analog plane.
When setting the part voltage reference to Band Gap
mode, the use of the VREF pin decoupling capacitors is
not recommended.
SDO
C2
VREF
VOUT0
SCK
To MCU
CS
Analog
Output
LAT/HVC
VOUTN
Power Supply Considerations
The power source should be as clean as possible. The
power supply to the device is also used for the DAC
voltage reference internally if the internal VDD is
selected as the resistor ladder’s reference voltage
(VRnB:VRnA = 00).
SDI
....
The MCP48FXBX4/8 devices are general purpose,
quad/octal-channel voltage output DACs for various
applications, where a precision operation with
low-power and nonvolatile EEPROM memory is
needed.
C3
VSS
CN
Optional
(a) Circuit when VDD is selected as reference.
Note: VDD is connected to the reference circuit internally.
VDD
Analog
C1
C2
SDI
VDD
VREF
SDO
VREF
SCK
To MCU
CS
VOUT0
LAT/HVC
Analog
Output
VSS
....
8.0
VOUTN
C3
CN
Optional
(b) Circuit when external reference is used.
C1 :
0.1 µF capacitor = Ceramic
C2 :
10 µF capacitor
= Tantalum
C3 :
~0.1 µF
= Optional to reduce noise
C4 :
0.1 µF capacitor = Ceramic
in VOUT pin
10 µF capacitor
C6 :
0.1 µF capacitor = Ceramic
FIGURE 8-1:
2020 Microchip Technology Inc.
= Tantalum
C5 :
Example Circuit.
DS20006362A-page 89
MCP48FXBX4/8
Layout Considerations
Several layout considerations may be applicable to
your application. These may include:
• Noise
• PCB Area Requirements
8.2.0.1
8.2.0.2
Multilayer boards utilizing a low-inductance ground
plane, isolated inputs, isolated outputs and proper
decoupling are critical to achieving the performance
that the silicon is capable of providing.
PACKAGE FOOTPRINT(1)
TABLE 8-1:
Package
Noise
Particularly harsh environments may require shielding
of critical signals. Inductively coupled AC transients
and digital switching noise can degrade the input and
output signal integrity, potentially masking the
MCP48FXBX4/8 devices’ performance. Careful board
layout minimizes these effects and increases the
Signal-to-Noise Ratio (SNR).
PCB Area Requirements
In some applications, PCB area is a criteria for device
selection. Table 8-1 shows the typical package
dimensions and area for the different package options.
Pins
8.2
Type
Package Footprint
Code
Dimensions
(mm)
Area (mm2)
Length Width
20 TSSOP
ST
3.00
4.90
14.70
20 VQFN
MQ
5
5
25
Note 1:
Does not include recommended land
pattern dimensions. Dimensions are
typical values.
Separate digital and analog ground planes are
recommended. In this case, the VSS pin and the ground
pins of the VDD capacitors should be terminated to the
analog ground plane.
Note:
Breadboards and wire-wrapped boards
are not recommended.
DS20006362A-page 90
2020 Microchip Technology Inc.
MCP48FXBX4/8
9.0
DEVELOPMENT SUPPORT
Figure 9-1 shows how the TSSOP20EV bond-out PCB
can be populated to easily evaluate the
MCP48FXBX4/8 devices. The PICkit™ Serial Analyzer
can be used to control the DAC Output registers and
state of the Configuration, Control and Status register.
Development support can be classified into two groups.
These are:
• Development Tools
• Technical Documentation
9.1
The TSSOP20EV boards may be purchased directly
from the Microchip website at www.microchip.com.
Development Tools
9.2
Several development tools are available to assist in
your design and evaluation of the MCP48FXBX4/8
devices. The currently available tools are shown in
Table 9-1.
TABLE 9-1:
Technical Documentation
Several additional technical documents are available to
assist you in your design and development. These
technical documents include Application Notes,
Technical Briefs and Design Guides. Table 9-2 lists
some of these documents.
DEVELOPMENT TOOLS(1)
Board Name
Part #
Comment
20-Pin TSSOP and SSOP Evaluation Board
TSSOP20EV
Most Flexible Option – Recommended Bond-out PCB
Note 1:
Supports the PICkit™ Serial Analyzer. See the User’s Guide for additional information and requirements.
TABLE 9-2:
TECHNICAL DOCUMENTATION
Application
Note Number
AN1326
Title
Literature #
Using the MCP4828 12-Bit DAC for LDMOS Amplifier Bias Control Applications
DS01326
—
Signal Chain Design Guide
DS21825
—
Analog Solutions for Automotive Applications Design Guide
DS01005
2020 Microchip Technology Inc.
DS20006362A-page 91
MCP48FXBX4/8
MCP48FXBX8-20E/ST
Installed in U3 Footprint
Connected to
Digital Ground
(DGND) Plane
LAT1
VDD
CS
Connected to
Digital Power (VL) Plane
LAT0/HVC
1.0 µF
0
4.7k
10k
4.7k
SDI
SCK
SDO
VOUT0
VREF1
48FEB
VREF0
VOUT2
VOUT7
VOUT4
VOUT5
VOUT6
VOUT3
VSS
0
Two-Wire Jumpers to Connect the
PICkit™ Serial Analyzer (SPI) to Device Pins
FIGURE 9-1:
DS20006362A-page 92
VOUT1
1x6 Male Header with 90° Right Angle
MCP48FXBX4/8 Evaluation Board Circuit Using TSSOP20EV.
2020 Microchip Technology Inc.
MCP48FXBX4/8
10.0
PACKAGING INFORMATION
10.1
Package Marking Information
20-Lead 5 x 5 mm VQFN
Example
MCP48FE
B04
-E/MQ
2010256
Example
20-Lead TSSOP
XXXXXXXX
XXXXXNNN
YYWW
Legend: XX...X
Y
YY
WW
NNN
e3
*
Note:
MCP48FVB
0420E256
2010
Customer-specific information
Year code (last digit of calendar year)
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code
Pb-free JEDEC designator for Matte Tin (Sn)
This package is Pb-free. The Pb-free JEDEC designator ( e3 )
can be found on the outer packaging for this package.
In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
2020 Microchip Technology Inc.
DS20006362A-page 93
MCP48FXBX4/8
20-Lead Plastic Quad Flat, No Lead Package (MQ) – 5x5x1.0 mm Body [VQFN]
With 0.40 mm Contact Length
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
D
A
B
N
NOTE 1
1
2
E
(DATUM B)
(DATUM A)
2X
0.20 C
2X
TOP VIEW
0.20 C
0.10 C
C
SEATING
PLANE
A1
A
20X
(A3)
0.08 C
SIDE VIEW
0.10
C A B
D2
0.10
C A B
E2
2
1
NOTE 1
K
N
L
e
BOTTOM VIEW
20X b
0.10
0.05
C A B
C
Microchip Technology Drawing C04-139C (MQ) Sheet 1 of 2
DS20006362A-page 94
2020 Microchip Technology Inc.
MCP48FXBX4/8
20-Lead Plastic Quad Flat, No Lead Package (MQ) – 5x5x1.0 mm Body [VQFN]
With 0.40 mm Contact Length
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Units
Dimension Limits
N
Number of Terminals
e
Pitch
A
Overall Height
A1
Standoff
(A3)
Contact Thickness
Overall Length
D
Exposed Pad Length
D2
Overall Width
E
Exposed Pad Width
E2
Contact Width
b
Contact Length
L
Contact-to-Exposed Pad
K
MIN
0.80
0.00
3.15
3.15
0.25
0.35
0.20
MILLIMETERS
NOM
20
0.65 BSC
0.90
0.02
0.20 REF
5.00 BSC
3.25
5.00 BSC
3.25
0.30
0.40
-
MAX
1.00
0.05
3.35
3.35
0.35
0.45
-
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. Package is saw singulated
3. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
Microchip Technology Drawing C04-139C (MQ) Sheet 2 of 2
2020 Microchip Technology Inc.
DS20006362A-page 95
MCP48FXBX4/8
20-Lead Plastic Quad Flat, No Lead Package (MQ) – 5x5x1.0 mm Body [VQFN]
With 0.40 mm Contact Length
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
C1
X2
EV
20
1
Y2
C2
ØV
2
G
EV
Y1
E
X1
SILK SCREEN
RECOMMENDED LAND PATTERN
Units
Dimension Limits
Contact Pitch
E
W2
Optional Center Pad Width
Optional Center Pad Length
T2
Contact Pad Spacing
C1
C2
Contact Pad Spacing
Contact Pad Width (X20)
X1
Contact Pad Length (X20)
Y1
Distance Between Pads
G
Thermal Via Diameter
V
Thermal Via Pitch
EV
MIN
MILLIMETERS
NOM
0.65 BSC
MAX
3.35
3.35
4.50
4.50
0.40
0.55
0.20
0.30
1.00
Notes:
1. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
2. For best soldering results, thermal vias, if used, should be filled or tented to avoid solder loss during
reflow process
Microchip Technology Drawing C04-2139B (MQ)
DS20006362A-page 96
2020 Microchip Technology Inc.
MCP48FXBX4/8
2020 Microchip Technology Inc.
DS20006362A-page 97
MCP48FXBX4/8
DS20006362A-page 98
2020 Microchip Technology Inc.
MCP48FXBX4/8
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2020 Microchip Technology Inc.
DS20006362A-page 99
MCP48FXBX4/8
NOTES:
DS20006362A-page 100
2020 Microchip Technology Inc.
MCP48FXBX4/8
APPENDIX A:
REVISION HISTORY
Revision A (May 2020)
• Original release of this document.
2020 Microchip Technology Inc.
DS20006362A-page 101
MCP48FXBX4/8
NOTES:
DS20006362A-page 102
2020 Microchip Technology Inc.
MCP48FXBX4/8
APPENDIX B:
Resolution
The resolution is the number of DAC output states that
divide the full-scale range. For the 12-bit DAC, the
resolution is 212, meaning the DAC code ranges from
0 to 4095.
Note:
B.2
B.3
Least Significant Bit (LSb)
This is the voltage difference between two successive
codes. For a given output voltage range, it is divided by
the resolution of the device (Equation B-1). The range
may be VDD (or VREF) to VSS (ideal); the DAC register
codes across the linear range of the output driver
(Measured 1), or full scale to zero scale (Measured 2).
EQUATION B-1:
LSb VOLTAGE
CALCULATION
Ideal
VDD
V LSb(IDEAL) = -----------N
2
or
VREF
--------------N
2
VS64
40h
N
When there are 2 resistors in the resistor
ladder and 2N tap points, the full-scale
DAC register code is the resistor element
(1 LSb) from the source reference voltage
(VDD or VREF).
Monotonic Operation
Monotonic operation means that the device’s output
voltage (VOUT) increases with every 1 code step (LSb)
increment (from VSS to the DAC’s reference voltage
(VDD or VREF)).
VS63
3Fh
Wiper Code
B.1
TERMINOLOGY
3Eh
VS3
03h
VS1
02h
01h
VS0
00h
VW (@ tap)
n=?
VW = VSn + VZS(@ Tap 0)
n=0
Voltage (VW VOUT)
FIGURE B-1:
VW (VOUT).
Measured 1
VOUT(@4000) – VOUT(@100)
V LSb(Measured) = ---------------------------------------------------------------------------- 4000 – 100
Measured 2
V OUT(@FS) – VOUT(@ZS)
V LSb = --------------------------------------------------------------------N
2 –1
2N = 4096 (MCP48FXB2X)
= 1024 (MCP48FXB1X)
= 256
(MCP48FXB0X)
2020 Microchip Technology Inc.
DS20006362A-page 103
MCP48FXBX4/8
B.4
Full-Scale Error (EFS)
The Full-Scale Error (see Figure B-3) is the error on
the VOUT pin relative to the expected VOUT voltage
(theoretical) for the maximum device DAC register
code (code FFFh for 12-bit, code 3FFh for 10-bit and
code FFh for 8-bit); see Equation B-2. The error
depends on the resistive load on the VOUT pin (and
where that load is tied to, such as VSS or VDD). For
loads (to VSS) greater than specified, the Full-Scale
Error will be greater.
The error in bits is determined by the theoretical voltage step-size to give an error in LSb.
EQUATION B-2:
FULL-SCALE ERROR
VOUT(@FS) – VIDEAL(@FS)
E FS = --------------------------------------------------------------------------V LSb(IDEAL)
Where:
EFS is expressed in LSb.
VOUT(@FS) = The VOUT voltage when the DAC
register code is at full scale.
VIDEAL(@FS) = The ideal output voltage when the
DAC register code is at full scale.
VLSb(IDEAL) = The theoretical voltage step size.
B.5
Zero-Scale Error (EZS)
The Zero-Scale Error (see Figure B-2) is the difference
between the ideal and the measured VOUT voltage with
the DAC register code equal to 000h (Equation B-3).
The error depends on the resistive load on the VOUT pin
(and where that load is tied to, such as VSS or VDD). For
loads (to VDD) greater than specified, the Zero-Scale
Error will be greater.
B.6
Total Unadjusted Error (ET)
The Total Unadjusted Error (ET) is the difference
between the ideal and the measured VOUT voltage.
Typically, calibration of the output voltage is
implemented to improve system performance.
The error in bits is determined by the theoretical
voltage step-size to give an error in LSb.
Equation B-4 shows the Total Unadjusted Error
calculation.
EQUATION B-4:
TOTAL UNADJUSTED
ERROR CALCULATION
VOUT_Actual(@Code) – V OUT_Ideal(@Code)
E T = ------------------------------------------------------------------------------------------------------------------------V LSb(Ideal)
Where:
ET is expressed in LSb.
VOUT_Actual(@Code) = The measured DAC output
voltage at the specified code.
VOUT_Ideal(@Code) = The calculated DAC output
voltage at the specified code.
(code × VLSb(Ideal)).
VLSb(Ideal) = VREF/# Steps
12-bit = VREF/4096
10-bit = VREF/1024
8-bit = VREF/256
The error in bits is determined by the theoretical
voltage step-size to give an error in LSb.
EQUATION B-3:
ZERO-SCALE ERROR
V OUT(@ZS)
EZS = ---------------------------------V LSb(IDEAL)
Where:
EZS is expressed in LSb.
VOUT(@ZS) = The VOUT voltage when the DAC
register code is at zero scale.
VLSb(IDEAL) = The theoretical voltage step-size.
DS20006362A-page 104
2020 Microchip Technology Inc.
MCP48FXBX4/8
B.7
Offset Error (EOS)
The Offset Error is the delta voltage of the VOUT voltage
from the ideal output voltage at the specified code. This
code is specified where the output amplifier is in the
linear operating range; for the MCP48FXBX4/8, we
specify code 100 (decimal). Offset error does not
include Gain Error, see Figure B-2.
Gain Error (EG)
(@ Code = 4000)
VREF
Actual
Transfer
Function
VOUT
This error is expressed in mV. Offset Error can be
negative or positive. The Offset Error can be calibrated
by software in application circuits.
Gain Error indicates how well the slope of the actual
transfer function matches the slope of the ideal transfer
function. Gain Error is usually expressed as a percent
of full-scale range (% of FSR) or in LSb. FSR is the
ideal full-scale voltage of the DAC (see Equation B-5).
VOUT
Actual
Transfer
Function
Zero-Scale
Error (EZS)
Ideal Transfer
Function
0
Offset
Error (EOS)
FIGURE B-2:
Error.
B.8
4000
100
DAC Input Code
Offset Error and Zero-Scale
Offset Error Drift (EOSD)
The Offset Error Drift is the variation in Offset Error due
to a change in ambient temperature. The Offset Error
Drift is typically expressed in ppm/°C or µV/°C.
B.9
Gain Error (EG)
Gain Error is a calculation based on the ideal slope
using the voltage boundaries for the linear range of the
output driver (ex.: code 100 and code 4000); see
Figure B-3. The Gain Error calculation nullifies the
device’s Offset Error.
Full-Scale
Error (EFS)
Ideal Transfer
Function Shifted by
Offset Error
(crosses at start of
defined linear range)
Ideal Transfer
Function
100
0
4000
DAC Input Code
4095
FIGURE B-3:
Error Example.
Gain Error and Full-Scale
EQUATION B-5:
EXAMPLE GAIN ERROR
V OUT(@4000) – V OS – V OUT_Ideal(@4000)
E G = ---------------------------------------------------------------------------------------------------------------------- 100
V Full-Scale Range
Where:
EG is expressed in % of FSR.
VOUT(@4000) = The measured DAC output
voltage at the specified code.
VOUT_Ideal(@4000) = The calculated DAC output
voltage at the specified code
(4000 * VLSb(Ideal)).
VOS = Measured offset voltage.
VFull-Scale Range = Expected full-scale output
value (such as the VREF
voltage).
B.10
Gain Error Drift (EGD)
The Gain Error Drift is the variation in Gain Error due to
a change in ambient temperature. Gain Error Drift is
typically expressed in ppm/°C (of FSR).
2020 Microchip Technology Inc.
DS20006362A-page 105
MCP48FXBX4/8
B.11
Integral Nonlinearity (INL)
The Integral Nonlinearity (INL) error is the maximum
deviation of an actual transfer function from an ideal
transfer function (straight line) passing through the
defined end points of the DAC transfer function (after
offset and gain errors have been removed).
In the MCP48FXBX4/8, INL is calculated using the
defined end points, DAC code 100 and code 4000. INL
can be expressed as a percentage of FSR or in LSb.
INL is also called ‘Relative Accuracy’. Equation B-6
shows how to calculate the INL error in LSb and
Figure B-4 shows an example of INL accuracy.
B.12
Differential Nonlinearity (DNL)
The Differential Nonlinearity (DNL) error (see
Figure B-5) is the measure of step-size between codes
in an actual transfer function. The ideal step-size
between codes is 1 LSb. A DNL error of zero would
imply that every code is exactly 1 LSb wide. If the DNL
error is less than 1 LSb, the DAC ensures monotonic
output and no missing codes. Equation B-7 shows how
to calculate the DNL error between any two adjacent
codes in LSb.
EQUATION B-7:
DNL ERROR
Positive INL means higher VOUT voltage than the ideal
one. Negative INL means lower VOUT voltage than the
ideal one.
V OUT(code = n+1) – V OUT(code = n)
EDNL = ---------------------------------------------------------------------------------------------------- – 1
VLSb(Measured)
EQUATION B-6:
Where:
INL ERROR
VOUT – VCalc_Ideal
EINL = ---------------------------------------------------------V LSb(Measured)
DNL is expressed in LSb.
VOUT(code = n) = The measured DAC output voltage
with a given DAC register code.
VLSb(Measured) = For Measured:
(VOUT(4000) – VOUT(100))/3900.
Where:
INL is expressed in LSb.
VCalc_Ideal = Code × VLSb(Measured) + VOS
VOUT(Code = n) = The measured DAC output
voltage with a given DAC
register code.
VLSb(Measured) = For Measured:
(VOUT(4000) – VOUT(100))/3900.
VOS = Measured offset voltage.
7
DNL = 0.5 LSb
6
5
DNL = 2 LSb
Analog
Output 4
(LSb)
3
7
INL = < -1 LSb
6
INL = -1 LSb
5
Analog 4
Output
(LSb) 3
2
1
0
000 001 010 011 100 101 110 111
DAC Input Code
INL = 0.5 LSb
Ideal Transfer Function
2
Actual Transfer Function
1
FIGURE B-5:
DNL Accuracy.
0
000 001 010 011 100 101 110 111
DAC Input Code
Ideal Transfer Function
Actual Transfer Function
FIGURE B-4:
DS20006362A-page 106
INL Accuracy.
2020 Microchip Technology Inc.
MCP48FXBX4/8
B.13
Settling Time
The settling time is the time delay required for the VOUT
voltage to settle into its new output value. This time is
measured from the start of code transition to when the
VOUT voltage is within the specified accuracy.
For the MCP48FXBX4/8, the settling time is a
measurement of the time delay until the VOUT voltage
reaches within 0.5 LSb of its final value, when the volatile DAC register changes from 1/4 to 3/4 of the FSR
(12-bit device: 400h to C00h).
B.14
Major Code Transition Glitch
Major code transition glitch is the impulse energy
injected into the DAC analog output when the code in
the DAC register changes the state. It is normally
specified as the area of the glitch in nV-Sec and is
measured when the digital code is changed by 1 LSb at
the major carry transition.
Example: 011...111 to 100...000
or 100...000 to 011...111
B.15
Power Supply Sensitivity (PSS)
PSS indicates how the output of the DAC is affected by
changes in the supply voltage. PSS is the ratio of the
change in VOUT to a change in VDD for midscale output
of the DAC. The VOUT is measured while the VDD is
varied from 5.5V to 2.7V as a step (VREF voltage held
constant) and is expressed in %/%, which is the %
change of the DAC output voltage with respect to the %
change of the VDD voltage.
EQUATION B-8:
PSS CALCULATION
V
–V
V
OUT(@5.5V)
OUT(@2.7V) OUT(@5.5V)
PSS = --------------------------------------------------------------------------------------------------------------------------- 5.5V – 2.7V 5.5V
Where:
PSS is expressed in %/%.
VOUT(@5.5V) = The measured DAC output
voltage with VDD = 5.5V.
VOUT(@2.7V) = The measured DAC output
voltage with VDD = 2.7V.
Digital Feedthrough
The digital feed-through is the glitch that appears at the
analog output, caused by coupling from the digital input
pins of the device. The area of the glitch is expressed
in nV-Sec and is measured with a full-scale change on
the digital input pins; example: all ‘0’s to all ‘1’s and vice
versa. The digital feedthrough is measured when the
DAC is not written to the output register.
B.16
B.17
-3 dB Bandwidth
This is the frequency of the signal at the VREF pin that
causes the voltage at the VOUT pin to fall a -3 dB value
from a static value on the VREF pin. The output
decreases due to the RC characteristics of the resistor
ladder and the characteristics of the output buffer.
B.18
Power Supply Rejection Ratio
(PSRR)
PSRR indicates how the output of the DAC is affected
by changes in the supply voltage. PSRR is the ratio of
the change in VOUT to a change in VDD for full-scale
output of the DAC. The VOUT is measured while the
VDD is varied ±10% (VREF voltage held constant) and
expressed in dB or µV/V.
B.19
VOUT Temperature Coefficient
The VOUT temperature coefficient quantifies the error in
the resistor ladder’s resistance ratio (DAC register
code value) and output buffer due to temperature drift.
B.20
Absolute Temperature Coefficient
The absolute temperature coefficient quantifies the
error in the end-to-end output voltage (nominal Output
Voltage, VOUT) due to temperature drift. For a DAC,
this error is typically not an issue due to the ratiometric
aspect of the output.
B.21
Noise Spectral Density
Noise spectral density is a measurement of the
device’s internally generated random noise and is
characterized as a spectral density (voltage per √Hz).
It is measured by loading the DAC to the midscale
value and measuring the noise at the VOUT pin. It is
measured in nV/√Hz.
2020 Microchip Technology Inc.
DS20006362A-page 107
MCP48FXBX4/8
NOTES:
DS20006362A-page 108
2020 Microchip Technology Inc.
MCP48FXBX4/8
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
PART NO.
X
XX
X
/XX
Device
Tape and
Reel
Pin
Count
Temperature
Range
Package
Examples:
a) MCP48FEB04-E/MQ:
Device:
MCP48FXB0X: Quad/Octal-Channel, 8-Bit DAC
with SPI Interface
MCP48FXB1X: Quad/Octal-Channel, 10-Bit DAC
with SPI Interface
MCP48FXB2X: Quad/Octal-Channel, 12-Bit DAC
with SPI Interface
Tape and Reel:
T
= Tape and Reel
Blank = Tube
Pin Count:
20-Lead
Temperature
Range:
E
= -40°C to +125°C (Extended)
Package:
MQ
= Plastic Quad Flat, No Lead Package (VQFN),
5 x 5 mm, 20-Lead
ST
= Plastic Thin Shrink Small Outline
Package (TSSOP), 20-Lead
Quad-Channel, 8-Bit Nonvolatile
DAC, Extended Temperature,
20-Lead VQFN.
b) MCP48FEB08T-E/MQ:
Octal-Channel, 8-Bit Nonvolatile
DAC, Tape and Reel, Extended
Temperature, 20-Lead VQFN.
c) MCP48FEB18-20E/ST:
Octal-Channel, 10-Bit Nonvolatile
DAC, Extended Temperature,
20-Lead TSSOP.
d) MCP48FEB18T-20E/ST: Octal-Channel, 10-Bit Nonvolatile
DAC, Tape and Reel, Extended
Temperature, 20-Lead TSSOP.
e) MCP48FVB28-E/MQ:
Octal-Channel, 12-Bit Volatile
DAC, Extended Temperature,
20-Lead VQFN.
f) MCP48FVB28T-E/MQ:
Octal-Channel, 12-Bit Volatile
DAC, Tape and Reel, Extended
Temperature, 20-Lead VQFN.
Note 1:
2020 Microchip Technology Inc.
Tape and Reel identifier only appears in the
catalog part number description. This identifier is
used for ordering purposes and is not printed on
the device package. Check with your Microchip
Sales Office for package availability with the
Tape and Reel option.
DS20006362A-page 109
MCP48FXBX4/8
NOTES:
DS20006362A-page 110
2020 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
•
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
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OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
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devices in life support and/or safety applications is entirely at
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please visit www.microchip.com/quality.
2020 Microchip Technology Inc.
ISBN: 978-1-5224-6143-2
DS20006362A-page 111
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