MCP4902-E/SL

MCP4902/4912/4922 8/10/12-Bit Dual Voltage Output Digital-to-Analog Converter with SPI Interface Features Description • • • • • • The MCP4902/4912/4922 devices are dual 8-bit, 10-bit, and 12-bit buffered voltage output Digital-to-Analog Converters (DACs), respectively. The devices operate from a single 2.7V to 5.5V supply with SPI compatible Serial Peripheral Interface. The user can configure the full-scale range of the device to be VREF or 2 * VREF by setting the Gain Selection Option bit (gain of 1 of 2). • • • • • • MCP4902: Dual 8-Bit Voltage Output DAC MCP4912: Dual 10-Bit Voltage Output DAC MCP4922: Dual 12-Bit Voltage Output DAC Rail-to-Rail Output SPI Interface with 20 MHz Clock Support Simultaneous Latching of the Dual DACs with LDAC pin Fast Settling Time of 4.5 µs Selectable Unity or 2x Gain Output External Voltage Reference Inputs External Multiplier Mode 2.7V to 5.5V Single-Supply Operation Extended Temperature Range: -40°C to +125°C Applications • • • • • Set Point or Offset Trimming Precision Selectable Voltage Reference Motor Control Feedback Loop Digitally-Controlled Multiplier/Divider Calibration of Optical Communication Devices Related Products(1) P/N DAC No. of Resolution ChannelS Voltage Reference (VREF) The user can shut down both DAC channels by using SHDN pin or shut down the DAC channel individually by setting the Configuration register bits. In Shutdown mode, most of the internal circuits in the shutdown channel are turned off for power savings and the output amplifier is configured to present a known high resistance output load (500 ktypical. The devices include double-buffered registers, allowing synchronous updates of two DAC outputs, using the LDAC pin. These devices also incorporate a Power-on Reset (POR) circuit to ensure reliable powerup. The devices utilize a resistive string architecture, with its inherent advantages of low DNL error and fast settling time. These devices are specified over the extended temperature range (+125°C). The devices provide high accuracy and low noise performance for consumer and industrial applications where calibration or compensation of signals (such as temperature, pressure and humidity) are required. MCP4801 8 1 MCP4811 10 1 MCP4821 12 1 MCP4802 8 2 MCP4812 10 2 MCP4822 12 2 VDD 1 14 VOUTA 13 VREFA Internal (2.048V) The MCP4902/4912/4922 devices are available in the PDIP, SOIC and TSSOP packages. Package Types MCP4901 8 1 NC 2 MCP4911 10 1 CS 3 External SCK 4 MCP4921 12 1 MCP4902 8 2 SDI 5 2 NC 6 2 NC 7 MCP4912 MCP4922 10 12 Note 1: The products listed here have similar AC/ DC performances.  2010 Microchip Technology Inc. MCP49X2 14-Pin PDIP, SOIC, TSSOP 12 VSS 11 VREFB 10 VOUTB 9 SHDN 8 LDAC MCP4902: 8-bit dual DAC MCP4912: 10-bit dual DAC MCP4922: 12-bit dual DAC DS22250A-page 1 MCP4902/4912/4922 Block Diagram LDAC CS SDI SCK Interface Logic Input Register A Input Register B String DACB String DACA Buffer Gain Logic VDD VSS DACB Register DACA Register VREF A Power-on Reset VREF B Buffer Gain Logic Output Op Amps Output Logic VOUTA DS22250A-page 2 SHDN VOUTB  2010 Microchip Technology Inc. MCP4902/4912/4922 1.0 ELECTRICAL CHARACTERISTICS † Notice: Stresses above those listed under “Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. Absolute Maximum Ratings † VDD....................................................................... 6.5V All inputs and outputs w.r.t ..... VSS –0.3V to VDD+0.3V Current at Input Pins ......................................... ±2 mA Current at Supply Pins .................................... ±50 mA Current at Output Pins .................................... ±25 mA Storage temperature .......................... -65°C to +150°C Ambient temp. with power applied ..... -55°C to +125°C ESD protection on all pins 4 kV (HBM), 400V (MM) Maximum Junction Temperature (TJ)................+150°C ELECTRICAL CHARACTERISTICS Electrical Specifications: Unless otherwise indicated, VDD = 5V, VSS = 0V, VREF = 2.048V, Output Buffer Gain (G) = 2x, RL = 5 k to GND, CL = 100 pF TA = -40 to +85°C. Typical values are at +25°C. Parameters Sym Min Typ Max Units Conditions Power Requirements Operating Voltage VDD 2.7 — 5.5 V Operating CurrentInput Current IDD — 350 700 µA — 250 500 µA Hardware Shutdown Current ISHDN — 0.3 2 µA Power-on Reset circuit is turned off Software Shutdown Current ISHDN_SW — 3.3 6 µA Power-on Reset circuit stays on Power-on-Reset Threshold VPOR — 2.0 — V VDD = 5V VDD = 3V VREF input is unbuffered, all digital inputs are grounded, all analog outputs (VOUT) are unloaded. Code = 000h. DC Accuracy MCP4902 Resolution n 8 — — Bits INL Error INL -1 ±0.125 1 LSb DNL DNL -0.5 ±0.1 +0.5 LSb Note 1 MCP4912 Resolution n 10 — — Bits INL Error INL -3.5 ±0.5 3.5 LSb DNL DNL -0.5 ±0.1 +0.5 LSb Note 1 MCP4922 Resolution n 12 — — Bits INL Error INL -12 ±2 12 LSb DNL DNL -0.75 ±0.2 +0.75 LSb Note 1 VOS — ±0.02 1 % of FSR Code = 0x000h Offset Error Note 1: 2: Guaranteed monotonic by design over all codes. This parameter is ensured by design, and not 100% tested.  2010 Microchip Technology Inc. DS22250A-page 3 MCP4902/4912/4922 ELECTRICAL CHARACTERISTICS (CONTINUED) Electrical Specifications: Unless otherwise indicated, VDD = 5V, VSS = 0V, VREF = 2.048V, Output Buffer Gain (G) = 2x, RL = 5 k to GND, CL = 100 pF TA = -40 to +85°C. Typical values are at +25°C. Parameters Sym Min Typ Max Units VOS/°C — 0.16 — ppm/°C -45°C to 25°C — -0.44 — ppm/°C +25°C to 85°C gE — -0.10 1 % of FSR G/°C — -3 — ppm/°C Input Range – Buffered Mode VREF 0.040 — VDD – 0.040 V Input Range – Unbuffered Mode VREF 0 — VDD V Input Impedance RVREF — 165 — k Input Capacitance – Unbuffered Mode CVREF — 7 — pF Multiplier Mode -3 dB Bandwidth fVREF — 450 — kHz VREF = 2.5V ±0.2Vp-p, Unbuffered, G = 1x fVREF — 400 — kHz VREF = 2.5V ±0.2 Vp-p, Unbuffered, G = 2x THDVREF — -73 — dB VREF = 2.5V ±0.2Vp-p, Frequency = 1 kHz Output Swing VOUT — 0.01 to VDD – 0.04 — V Accuracy is better than 1 LSb for VOUT = 10 mV to (VDD – 40 mV) Phase Margin m — 66 — degrees Slew Rate SR — 0.55 — V/µs Short Circuit Current ISC — 15 24 mA tsettling — 4.5 — µs Offset Error Temperature Coefficient Gain Error Gain Error Temperature Coefficient Conditions Code = 0xFFFh, not including offset error Input Amplifier (VREF Input) Multiplier Mode – Total Harmonic Distortion Note 2 Code = 2048 VREF = 0.2V p-p, f = 100 Hz and 1 kHz Unbuffered Mode Output Amplifier Settling Time Within 1/2 LSb of final value from 1/4 to 3/4 full-scale range Dynamic Performance (Note 2) DAC-to-DAC Crosstalk — 10 — nV-s Major Code Transition Glitch — 45 — nV-s Digital Feedthrough — 10 — nV-s Analog Crosstalk — 10 — nV-s Note 1: 2: 1 LSb change around major carry (0111...1111 to 1000...0000) Guaranteed monotonic by design over all codes. This parameter is ensured by design, and not 100% tested. DS22250A-page 4  2010 Microchip Technology Inc. MCP4902/4912/4922 ELECTRICAL CHARACTERISTIC WITH EXTENDED TEMPERATURE Electrical Specifications: Unless otherwise indicated, VDD = 5V, VSS = 0V, VREF = 2.048V, Output Buffer Gain (G) = 2x, RL = 5 k to GND, CL = 100 pF. Typical values are at +125°C by characterization or simulation. Parameters Sym Min Typ Max Units Conditions Operating Voltage VDD 2.7 — 5.5 V Operating Current IDD — 400 — µA VREF input is unbuffered, all digital inputs are grounded, all analog outputs (VOUT) are unloaded. Code=000h ISHDN — 1.5 — µA POR circuit is turned-off — 5 — µA POR circuit stays turned-on — 1.85 — V — — Power Requirements Hardware Shutdown Current Software Shutdown Current ISHDN_SW Power-On Reset threshold VPOR DC Accuracy MCP4902 Resolution n 8 Bits INL Error INL ±0.25 LSb DNL DNL ±0.2 LSb Note 1 MCP4912 Resolution n 10 — — Bits INL Error INL ±1 LSb DNL DNL ±0.2 LSb Note 1 MCP4922 Resolution n 12 — — Bits INL Error INL ±4 LSb DNL DNL ±0.25 LSb Offset Error VOS — ±0.02 — % of FSR VOS/°C — -5 — ppm/°C gE — -0.10 — % of FSR G/°C — -3 — ppm/°C Input Range – Buffered Mode VREF — 0.040 to VDD – 0.040 — V Input Range – Unbuffered Mode VREF 0 — VDD V Input Impedance RVREF — 174 — k Input Capacitance – Unbuffered Mode CVREF — 7 — pF Offset Error Temperature Coefficient Gain Error Gain Error Temperature Coefficient Note 1 Code 0x000h +25°C to +125°C Code = 0xFFFh, not including offset error Input Amplifier (VREF Input) Note 1: 2: Note 1 Code = 2048, VREF = 0.2V p-p, f = 100 Hz and 1 kHz Unbuffered mode Guaranteed monotonic by design over all codes. This parameter is ensured by design, and not 100% tested.  2010 Microchip Technology Inc. DS22250A-page 5 MCP4902/4912/4922 ELECTRICAL CHARACTERISTIC WITH EXTENDED TEMPERATURE (CONTINUED) Electrical Specifications: Unless otherwise indicated, VDD = 5V, VSS = 0V, VREF = 2.048V, Output Buffer Gain (G) = 2x, RL = 5 k to GND, CL = 100 pF. Typical values are at +125°C by characterization or simulation. Parameters Sym Min Typ Max Units fVREF — 450 — kHz VREF = 2.5V ±0.1 Vp-p, Unbuffered, G = 1x fVREF — 400 — kHz VREF = 2.5V ±0.1 Vp-p, Unbuffered, G = 2x THDVREF — — — dB VREF = 2.5V ±0.1Vp-p, Frequency = 1 kHz Output Swing VOUT — 0.01 to VDD – 0.04 — V Accuracy is better than 1 LSb for VOUT = 10 mV to (VDD – 40 mV) Phase Margin m — 66 — degrees Slew Rate SR — 0.55 — V/µs Short Circuit Current ISC — 17 — mA tsettling — 4.5 — µs DAC to DAC Crosstalk — 10 — nV-s Major Code Transition Glitch — 45 — nV-s Digital Feedthrough — 10 — nV-s Analog Crosstalk — 10 — nV-s Multiplying Mode -3 dB Bandwidth Multiplying Mode – Total Harmonic Distortion Conditions Output Amplifier Settling Time Within 1/2 LSb of final value from 1/4 to 3/4 full-scale range Dynamic Performance (Note 2) Note 1: 2: 1 LSb change around major carry (0111...1111 to 1000...0000) Guaranteed monotonic by design over all codes. This parameter is ensured by design, and not 100% tested. DS22250A-page 6  2010 Microchip Technology Inc. MCP4902/4912/4922 AC CHARACTERISTICS (SPI TIMING SPECIFICATIONS) Electrical Specifications: Unless otherwise indicated, VDD= 2.7V – 5.5V, TA= -40 to +125°C. Typical values are at +25°C. Parameters Sym Min Typ Max Units Schmitt Trigger High-Level Input Voltage (All digital input pins) VIH 0.7 VDD — — V Schmitt Trigger Low-Level Input Voltage (All digital input pins) VIL — — 0.2 VDD V VHYS — 0.05 VDD — V Input Leakage Current ILEAKAGE -1 — 1 A SHDN = LDAC = CS = SDI = SCK + VREF = VDD or VSS Digital Pin Capacitance (All inputs/outputs) CIN, COUT — 10 — pF VDD = 5.0V, TA = +25°C, fCLK = 1 MHz (Note 1) Clock Frequency FCLK — — 20 MHz Clock High Time tHI 15 — — ns Note 1 tLO 15 — — ns Note 1 tCSSR 40 — — ns Applies only when CS falls with CLK high. (Note 1) tSU 15 — — ns Note 1 Data Input Hold Time tHD 10 — — ns Note 1 SCK Rise to CS Rise Hold Time tCHS 15 — — ns Note 1 CS High Time tCSH 15 — — ns Note 1 LDAC Pulse Width tLD 100 — — ns Note 1 LDAC Setup Time tLS 40 — — ns Note 1 tIDLE 40 — — ns Note 1 Hysteresis of Schmitt Trigger Inputs Clock Low Time CS Fall to First Rising CLK Edge Data Input Setup Time SCK Idle Time before CS Fall Note 1: Conditions TA = +25°C (Note 1) This parameter is ensured by design and not 100% tested. tCSH CS tIDLE tCSSR Mode 1,1 tHI tLO tCHS SCK Mode 0,0 tSU tHD SI MSb in LSb in LDAC tLS FIGURE 1-1: tLD SPI Input Timing Data.  2010 Microchip Technology Inc. DS22250A-page 7 MCP4902/4912/4922 TEMPERATURE CHARACTERISTICS Electrical Specifications: Unless otherwise indicated, VDD = +2.7V to +5.5V, VSS = GND. Parameters Sym Min Typ Max Units Specified Temperature Range TA -40 — +125 °C Operating Temperature Range TA -40 — +125 °C Storage Temperature Range TA -65 — +150 °C Thermal Resistance, 14L-PDIP JA — 70 — °C/W Thermal Resistance, 14L-SOIC JA — 120 — °C/W Thermal Resistance, 14L-TSSOP JA — 100 — °C/W Conditions Temperature Ranges Note 1 Thermal Package Resistances Note 1: The MCP4902/4912/4922 devices operate over this extended temperature range, but with reduced performance. Operation in this range must not cause TJ to exceed the maximum junction temperature of 150°C. DS22250A-page 8  2010 Microchip Technology Inc. MCP4902/4912/4922 2.0 TYPICAL PERFORMANCE CURVES Note: The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore outside the warranted range. Note: Unless otherwise indicated, TA = +25°C, VDD = 5V, VSS = 0V, VREF = 2.048V, Gain = 2x, RL = 5 k, CL = 100 pF. 0.0766 0.3 Absolute DNL (LSB) DNL (LSB) 0.2 0.1 0 -0.1 -0.2 0.0764 0.0762 0.076 0.0758 0.0756 0.0754 0.0752 0.075 -0.3 0 1024 2048 3072 -40 4096 FIGURE 2-1: DNL vs. Code (MCP4922). 20 40 60 80 100 120 0.35 Absolute DNL (LSB) 0.1 DNL (LSB) 0 FIGURE 2-4: Absolute DNL vs. Temperature (MCP4922). 0.2 0 -0.1 0.3 0.25 0.2 0.15 0.1 0.05 0 -0.2 0 1024 2048 3072 Code (Decimal) 1 4096 125C 85C INL (LSB) 0.2 0.1 0 -0.1 -0.2 -0.3 -0.4 2048 Code (Decimal) 3072 1 2 4096 3 4 5.5 FIGURE 2-3: DNL vs. Code and VREF, Gain = 1 (MCP4922).  2010 Microchip Technology Inc. 4 5 FIGURE 2-5: Absolute DNL vs. Voltage Reference (MCP4922). 0.3 1024 3 Voltage Reference (V) 0.4 0 2 25C FIGURE 2-2: DNL vs. Code and Temperature (MCP4922). DNL (LSB) -20 Ambient Temperature (ºC) Code (Decimal) 5 4 3 2 1 0 -1 -2 -3 -4 -5 Ambient Temperature 125C 0 1024 85 2048 3072 Code (Decimal) 25 4096 FIGURE 2-6: INL vs. Code and Temperature (MCP4922). DS22250A-page 9 MCP4902/4912/4922 Note: Unless otherwise indicated, TA = +25°C, VDD = 5V, VSS = 0V, VREF = 2.048V, Gain = 2x, RL = 5 k, CL = 100 pF. 2 2 0 INL (LSB) Absolute INL (LSB) 2.5 1.5 1 -2 -4 0.5 0 -6 -40 -20 0 20 40 60 80 100 120 0 1024 Ambient Temperature (ºC) 3072 4096 Code (Decimal) FIGURE 2-7: Absolute INL vs. Temperature (MCP4922). FIGURE 2-10: Note: 3 INL vs. Code (MCP4922). Single device graph (Figure 2-10) for illustration of 64 code effect. 0.2 Temp = - 40oC to +125oC 2.5 0.1 2 DNL (LSB) Absolute INL (LSB) 2048 1.5 1 0 -0.1 0.5 0 1 2 3 4 -0.2 5 0 Voltage Reference (V) FIGURE 2-8: (MCP4922). Absolute INL vs. VREF 3 1 2 3 384 512 640 Code 768 896 1024 1.5 4 5.5 0.5 1 0 INL (LSB) INL (LSB) 256 FIGURE 2-11: DNL vs. Code and Temperature (MCP4912). VREF 2 128 -1 -2 o 85 C -0.5 -1.5 o -3 1024 FIGURE 2-9: (MCP4922). DS22250A-page 10 2048 3072 Code (Decimal) 4096 INL vs. Code and VREF - 40 C o 125 C -4 0 25 C o -2.5 -3.5 0 128 256 384 512 640 Code 768 896 1024 FIGURE 2-12: INL vs. Code and Temperature (MCP4912).  2010 Microchip Technology Inc. MCP4902/4912/4922 Note: Unless otherwise indicated, TA = +25°C, VDD = 5V, VSS = 0V, VREF = 2.048V, Gain = 2x, RL = 5 k, CL = 100 pF. 96 128 160 192 224 256 Code FIGURE 2-13: DNL vs. Code and Temperature (MCP4902). IDD (μA) IDD Histogram (VDD = 2.7V). FIGURE 2-16: 0.5 16 o 14 o -40 C to +85 C 12 Occurrence 0.25 INL (LSB) 325 64 315 32 305 0 295 -0.06 285 215 -0.04 275 -0.02 265 0 255 0.02 245 Occurrence DNL (LSB) 0.04 20 18 16 14 12 10 8 6 4 2 0 235 Temp = -40oC to +125oC 225 0.06 0 10 8 6 4 -0.25 2 o 125 C 0 32 64 96 128 160 Code 192 224 400 415 400 385 370 355 340 325 310 295 280 IDD (μA) 256 FIGURE 2-17: 5.0V). FIGURE 2-14: INL vs. Code and Temperature (MCP4902). IDD Histogram (VDD = 5.5V 5.0V 4.0V 3.0V 2.7V 350 IDD (µA) 265 250 0 -0.5 VDD 300 250 200 -40 -20 FIGURE 2-15: VDD. 0 20 40 60 80 100 120 Ambient Temperature (ºC) IDD vs. Temperature and  2010 Microchip Technology Inc. DS22250A-page 11 MCP4902/4912/4922 Note: Unless otherwise indicated, TA = +25°C, VDD = 5V, VSS = 0V, VREF = 2.048V, Gain = 2x, RL = 5 k, CL = 100 pF. 2 -0.08 VDD 5.5V 5.0V 4.0V 1 3.0V 2.7V 0.5 5.5V Gain Error (%) ISHDN (μA) 1.5 VDD -0.1 5.0V -0.12 4.0V 3.0V 2.7V -0.14 -0.16 0 -40 -20 -40 0 20 40 60 80 100 120 Ambient Temperature (ºC) FIGURE 2-18: Hardware Shutdown Current vs. Ambient Temperature and VDD. -20 0 20 40 60 80 100 120 Ambient Temperature (ºC) FIGURE 2-21: Gain Error vs. Ambient Temperature and VDD. 6 VDD 4 5.5V 5.0V 4 4.0V 3 3.0V 2.7V 2 VDD 1 VIN Hi Threshold (V) ISHDN_SW (μA) 5 0 5.0V 3 2.5 4.0V 2 3.0V 2.7V 1.5 1 -40 -20 0 20 40 60 80 100 120 Ambient Temperature (ºC) -40 FIGURE 2-19: Software Shutdown Current vs. Ambient Temperature and VDD. -20 0 20 40 60 80 100 120 Ambient Temperature (ºC) FIGURE 2-22: VIN High Threshold vs Ambient Temperature and VDD. 0.12 0.08 VDD 0.06 0.04 5.5V 0.02 0 5.0V 4.0V 3.0V 2.7V -0.02 -40 -20 0 20 40 60 80 100 120 Ambient Temperature (ºC) FIGURE 2-20: Offset Error vs. Ambient Temperature and VDD. DS22250A-page 12 VIN Low Threshold (V) 1.6 0.1 Offset Error (%) 5.5V 3.5 VDD 1.5 5.5V 1.4 5.0V 1.3 1.2 4.0V 1.1 1 3.0V 2.7V 0.9 0.8 -40 -20 0 20 40 60 80 100 120 Ambient Temperature (ºC) FIGURE 2-23: VIN Low Threshold vs Ambient Temperature and VDD.  2010 Microchip Technology Inc. MCP4902/4912/4922 VDD 5.5V 5.0V 4.0V 3.0V 2.7V -40 -20 0.0045 VOUT_LOW Limit (Y-AVSS)(V) 2.5 2.25 2 1.75 1.5 1.25 1 0.75 0.5 0.25 0 5.5V 0.0035 0.003 5.0V 0.0025 4.0V 3.0V 2.7V 0.002 0.0015 -40 -20 0 20 40 60 80 100 120 Ambient Temperature (ºC) FIGURE 2-24: Input Hysteresis vs. Ambient Temperature and VDD. FIGURE 2-27: VOUT Low Limit vs. Ambient Temperature and VDD. 18 175 VREF_UNBUFFERED Impedance (kOhm) 5.5V 2.7V VDD 170 165 160 VDD 17 5.5V 5.0V 4.0V 3.0V 2.7V 16 15 14 13 12 11 10 155 -40 -20 -40 0 20 40 60 80 100 120 Ambient Temperature (ºC) FIGURE 2-25: VREF Input Impedance vs. Ambient Temperature and VDD. 0.045 5.0 0.035 VREF=4.0 4.0V 0.03 0.025 3.0V 2.7V 0.02 VDD 0.015 0.01 0 20 40 60 80 100 120 Ambient Temperature (ºC) 6.0 5.5V 5.0V 0.04 -20 FIGURE 2-28: IOUT High Short vs. Ambient Temperature and VDD. VOUT (V) VOUT_HI Limit (VDD-Y)(V) VDD 0.004 0 20 40 60 80 100 120 Ambient Temperature (ºC) IOUT_HI_SHORTED (mA) VIN_SPI Hysteresis (V) Note: Unless otherwise indicated, TA = +25°C, VDD = 5V, VSS = 0V, VREF = 2.048V, Gain = 2x, RL = 5 k, CL = 100 pF. 4.0 Output Shorted to VDD 3.0 2.0 1.0 Output Shorted to VSS 0.005 0.0 0 -40 -20 0 20 40 60 80 100 120 Ambient Temperature (ºC) FIGURE 2-26: VOUT High Limit vs. Ambient Temperature and VDD.  2010 Microchip Technology Inc. 0 2 FIGURE 2-29: 4 6 8 10 IOUT (mA) 12 14 16 IOUT vs VOUT. Gain = 1x. DS22250A-page 13 MCP4902/4912/4922 Note: Unless otherwise indicated, TA = +25°C, VDD = 5V, VSS = 0V, VREF = 2.048V, Gain = 2x, RL = 5 k, CL = 100 pF. VOUT VOUT SCK LDAC LDAC Time (1 µs/div) FIGURE 2-30: VOUT Rise Time. Time (1 µs/div) FIGURE 2-33: VOUT Rise Time. VOUT VOUT SCK SCK LDAC LDAC Time (1 µs/div) VOUT Fall Time. FIGURE 2-34: Shutdown. VOUT SCK LDAC Time (1 µs/div) FIGURE 2-32: DS22250A-page 14 VOUT Rise Time Exit Ripple Rejection (dB) FIGURE 2-31: Time (1 µs/div) VOUT Rise Time. Frequency (Hz) FIGURE 2-35: PSRR vs. Frequency.  2010 Microchip Technology Inc. MCP4902/4912/4922 Note: Unless otherwise indicated, TA = +25°C, VDD = 5V, VSS = 0V, VREF = 2.50V, Gain = 2x, RL = 5 k, CL = 100 pF. 0 Attenuation (dB) -2 -4 -6 -8 -10 -12 100 FIGURE 2-36: Frequency (kHz) 160 416 672 928 1184 1440 1696 1952 2208 2464 2720 2976 3232 3488 3744 1,000 Multiplier Mode Bandwidth. -45 qVREF – qVOUT D= D= D= D= D= D= D= D= D= D= D= D= D= D= D= 0 D= D= D= D= D= D= D= D= D= D= D= D= D= D= D= -90 -135 -180 100 FIGURE 2-38: Frequency (kHz) 160 416 672 928 1184 1440 1696 1952 2208 2464 2720 2976 3232 3488 3744 1,000 Phase Shift. Note: Bandwidth (kHz) Dn • G VOUT Attenuation (dB) = 20 log ( - 20 log ( 4096 ) VREF ) 600 580 560 540 520 500 480 460 440 420 400 G=1 G=2 44 37 88 34 32 32 76 29 20 27 64 24 08 22 52 19 96 16 40 14 84 11 8 92 2 67 6 41 0 16 Worst Case Codes (decimal) FIGURE 2-37: Codes. -3 db Bandwidth vs. Worst  2010 Microchip Technology Inc. DS22250A-page 15 MCP4902/4912/4922 NOTES: DS22250A-page 16  2010 Microchip Technology Inc. MCP4902/4912/4922 3.0 PIN DESCRIPTIONS The descriptions of the pins are listed in Table 3-1. TABLE 3-1: 3.1 PIN FUNCTION TABLE Pin No. Symbol Function 1 VDD Supply Voltage Input (2.7V to 5.5V) 2 NC No Connection 3 CS Chip Select Input 4 SCK Serial Clock Input 5 SDI Serial Data Input 6 NC No Connection 7 NC No Connection 8 LDAC Synchronization Input. This pin is used to transfer DAC settings (Input Registers) to the output registers (VOUT) 9 SHDN Hardware Shutdown Input 10 VOUTB DACB Output 11 VREFB DACB Reference Voltage Input (VSS to VDD) 12 VSS 13 VREFA DACA Reference Voltage Input (VSS to VDD) 14 VOUTA DACA Output Ground reference point for all circuitry on the device Supply Voltage Pins (VDD, VSS) VDD is the positive supply voltage input pin. The input supply voltage is relative to VSS and can range from 2.7V to 5.5V. The power supply at the VDD pin should be as clean as possible for a good DAC performance. It is recommended to use an appropriate bypass capacitor of about 0.1 µF (ceramic) to ground. An additional 10 µF capacitor (tantalum) in parallel is also recommended to further attenuate high frequency noise present in application boards. VSS is the analog ground pin and the current return path of the device. The user must connect the VSS pin to a ground plane through a low-impedance connection. If an analog ground path is available in the application Printed Circuit Board (PCB), it is highly recommended that the VSS pin be tied to the analog ground path or isolated within an analog ground plane of the circuit board. 3.2 Chip Select (CS) CS is the Chip Select input, which requires an active low signal to enable serial clock and data functions. 3.3 Serial Clock Input (SCK) SCK is the SPI compatible serial clock input pin. 3.4 Serial Data Input (SDI) 3.5 Latch DAC Input (LDAC) LDAC (latch DAC synchronization input) pin is used to transfer the input latch registers to their corresponding DAC registers (output latches, VOUT). When this pin is low, both VOUTA and VOUTB are updated at the same time with their input register contents. This pin can be tied to low (VSS) if the VOUT update is desired at the rising edge of the CS pin. This pin can be driven by an external control device such as an MCU I/O pin. 3.6 Hardware Shutdown Input (SHDN) SHDN is the hardware shutdown input pin. When this pin is low, both DAC channels are shut down. DAC output is not available during the shutdown. 3.7 Analog Outputs (VOUTA, VOUTB) VOUTA is the DAC A output pin, and VOUTB is the DAC B output pin. Each output has its own output amplifier. The DAC output amplifier of each channel can drive the output pin with a range of VSS to VDD. 3.8 Voltage Reference Inputs (VREFA, VREFB) VREFA is the voltage reference input for DAC channel A, and VREFB is the reference input for DAC channel B. The reference on these pins is utilized to set the reference voltage on the string DAC. The input signal can range from VSS to VDD. These pins can be tied to VDD. SDI is the SPI compatible serial data input pin.  2010 Microchip Technology Inc. DS22250A-page 17 MCP4902/4912/4922 NOTES: DS22250A-page 18  2010 Microchip Technology Inc. MCP4902/4912/4922 4.0 GENERAL OVERVIEW The MCP4902, MCP4912 and MCP4922 are dual voltage-output 8-bit, 10-bit and 12-bit DAC devices, respectively. These devices include input amplifiers, rail-to-rail output amplifiers, reference buffers for external voltage reference, shutdown and reset-management circuitry. The devices use an SPI serial communication interface and operate with a single supply voltage from 2.7V to 5.5V. The DAC input coding of these devices is straight binary. Equation 4-1 shows the DAC analog output voltage calculation. TABLE 4-1: VOUT = ------------------------------ G n 2 Where: VREF Dn G n ANALOG OUTPUT VOLTAGE (VOUT)  VREF  Dn  = = = = = = = = = EXternal voltage reference DAC input code Gain Selection 2 for bit = 0 1 for bit = 1 DAC Resolution 8 for MCP4902 10 for MCP4912 12 for MCP4922 Gain Selection Device 1x VREF/256 2x (2* VREF)/256 MCP4912 1x VREF/1024 (n = 10) 2x (2* VREF)/1024 MCP4922 1x VREF/4096 (n = 12) 2x (2* VREF)/4096 where VREF is the external voltage reference. 4.1.1 DC Accuracy INL ACCURACY Integral Non-Linearity (INL) error is the maximum deviation between an actual code transition point and its corresponding ideal transition point, after offset and gain errors have been removed. The two end points (from 0x000 and 0xFFF) method is used for the calculation. Figure 4-1 shows the details. A positive INL error represents transition(s) later than ideal. A negative INL error represents transition(s) earlier than ideal. INL < 0 111 110 The ideal output range of each device is: (b) 0 V to 255/256 * 2 * VREF when gain setting = 2x. Digital Input Code • MCP4912 (n = 10) 100 011 (a) 0 V to 1023/1024 * VREF when gain setting = 1x. 010 (b) 0 V to 1023/1024 * 2 * VREF when gain setting = 2x. 001 • MCP4922 (n = 12) INL < 0 (b) 0 V to 4095/4096 * 2 * VREF when gain setting = 2x. See the output swing voltage specification in Section 1.0 “Electrical Characteristics”. 1 LSb is the ideal voltage difference between two successive codes. Table 4-1 illustrates the LSb calculation of each device.  2010 Microchip Technology Inc. Ideal Transfer Function 000 (a) 0 V to 4095/4096 * VREF when Gain setting = 1x. Note: Actual Transfer Function 101 • MCP4902 (n = 8) (a) 0 V to 255/256 * VREF when gain setting = 1x. LSb Size MCP4902 (n = 8) 4.1 EQUATION 4-1: LSb OF EACH DEVICE DAC Output FIGURE 4-1: 4.1.2 Example for INL Error. DNL ACCURACY A Differential Non-Linearity (DNL) error is the measure of variations in code widths from the ideal code width. A DNL error of zero indicates that every code is exactly 1 LSb wide. DS22250A-page 19 MCP4902/4912/4922 4.2.2 111 110 Actual transfer function 101 100 Ideal transfer function 011 010 Wide code, > 1 LSb 001 4.2.3 Narrow code, < 1 LSb DAC Output FIGURE 4-2: Example for DNL Accuracy. OFFSET ERROR An offset error is the deviation from zero voltage output when the digital input code is zero. 4.1.4 GAIN ERROR A gain error is the deviation from the ideal output, VREF– 1 LSb, excluding the effects of offset error. 4.2 4.2.1 Circuit Descriptions OUTPUT AMPLIFIERS The DAC’s outputs are buffered with a low-power, precision CMOS amplifier. This amplifier provides low offset voltage and low noise. The output stage enables the device to operate with output voltages close to the power supply rails. Refer to Section 1.0 “Electrical Characteristics” for the analog output voltage range and load conditions. In addition to resistive load driving capability, the amplifier will also drive high capacitive loads without oscillation. The amplifier’s strong outputs allow VOUT to be used as a programmable voltage reference in a system. Selecting a gain of 2 reduces the bandwidth of the amplifier in Multiplying mode. Refer to Section 1.0 “Electrical Characteristics” for the Multiplying mode bandwidth for given load conditions. 4.2.1.1 POWER-ON RESET CIRCUIT The internal Power-on Reset (POR) circuit monitors the power supply voltage (VDD) during the device operation. The circuit also ensures that the DACs power-up with high output impedance ( = 0, typically 500 k. The devices will continue to have a high-impedance output until a valid write command is performed to either of the DAC registers and the LDAC pin meets the input low threshold. If the power supply voltage is less than the POR threshold (VPOR = 2.0V, typical), the DACs will be held in their Reset state. The DACs will remain in that state until VDD > VPOR and a subsequent write command is received. Figure 4-3 shows a typical power supply transient pulse and the duration required to cause a reset to occur, as well as the relationship between the duration and trip voltage. A 0.1 µF decoupling capacitor, mounted as close as possible to the VDD pin, can provide additional transient immunity. 5V Supply Voltages 000 4.1.3 The input buffer amplifiers for the MCP4902/4912/4922 devices provide low offset voltage and low noise. A Configuration bit for each DAC allows the VREF input to bypass the VREF input buffer amplifiers, achieving a Buffered or Unbuffered mode. Buffered mode provides a very high input impedance, with only minor limitations on the input range and frequency response. Unbuffered ( = 0) is the default configuration. Unbuffered mode provides a wide input range (0V to VDD), with a typical input impedance of 165 k with 7 pF. VPOR VDD - VPOR Transient Duration Time 10 Transient Duration (µs) Digital Input Code VOLTAGE REFERENCE AMPLIFIERS Programmable Gain Block The rail-to-rail output amplifier has configurable gain, allowing optimal full-scale outputs for different voltage reference inputs. The output amplifier gain has two selections, a gain of 1x ( = 1) or a gain of 2x ( = 0). = 6 4 Transients above the 2 Transients 0 FIGURE 4-3: TA 8 1 below the 2 3 4 VDD – VPOR (V) 5 Typical Transient Response. The default value is a gain of 2 ( = 0). DS22250A-page 20  2010 Microchip Technology Inc. MCP4902/4912/4922 4.2.4 SHUTDOWN MODE The user can shut down each DAC channel selectively by using a software command or shut down all channels by using the SHDN pin. During Shutdown mode, most of the internal circuits in the channel that was shut down are turned off for power savings. The serial interface remains active, thus allowing a write command to bring the device out of the Shutdown mode. There will be no analog output at the channel that was shut down and the VOUT pin is internally switched to a known resistive load (500 k typical. Figure 4-4 shows the analog output stage during the Shutdown mode. The condition of the Power-on Reset circuit during the shutdown is as follows: a) b) Turned-off, if the shutdown occurred by the SHDN pin; On, if the shutdown occurred by the software. VOUT Op Amp Power-Down Control Circuit Resistive String DAC FIGURE 4-4: Mode. Resistive Load 500 k Output Stage for Shutdown The device will remain in Shutdown mode until the SHDN pin is brought to high or a write command with bit = 1 is latched into the device. When a DAC is changed from Shutdown to Active mode, the output settling time takes less than 10 µs, but more than the standard active mode settling time (4.5 µs).  2010 Microchip Technology Inc. DS22250A-page 21 MCP4902/4912/4922 NOTES: DS22250A-page 22  2010 Microchip Technology Inc. MCP4902/4912/4922 5.0 SERIAL INTERFACE 5.1 Overview The MCP4902/4912/4922 devices are designed to interface directly with the Serial Peripheral Interface (SPI) port, which is available on many microcontrollers and supports Mode 0,0 and Mode 1,1. Commands and data are sent to the device via the SDI pin, with data being clocked-in on the rising edge of SCK. The communications are unidirectional, thus the data cannot be read out of the MCP4902/4912/4922. The CS pin must be held low for the duration of a write command. The write command consists of 16 bits and is used to configure the DAC’s control and data latches. Register 5-1 to Register 5-3 detail the input register that is used to configure and load the DACA and DACB registers for each device. Figure 5-1 to Figure 5-3 show the write command for each device. Refer to Figure 1-1 and SPI Timing Specifications Table for detailed input and output timing specifications for both Mode 0,0 and Mode 1,1 operation.  2010 Microchip Technology Inc. 5.2 Write Command The write command is initiated by driving the CS pin low, followed by clocking the four Configuration bits and the 12 data bits into the SDI pin on the rising edge of SCK. The CS pin is then raised, causing the data to be latched into the selected DAC’s input registers. The MCP4902/4912/4922 utilizes a double-buffered latch structure to allow both DACA’s and DACB’s outputs to be synchronized with the LDAC pin, if desired. Upon the LDAC pin achieving a low state, the values held in the DAC’s input registers are transferred into the DAC’s output registers. The outputs will transition to the value and held in the DACX register. All writes to the MCP4902/4912/4922 are 16-bit words. Any clocks past the 16th clock will be ignored. The Most Significant 4 bits are Configuration bits. The remaining 12 bits are data bits. No data can be transferred into the device with CS high. This transfer will only occur if 16 clocks have been transferred into the device. If the rising edge of CS occurs prior to that, shifting of data into the input registers will be aborted. DS22250A-page 23 MCP4902/4912/4922 REGISTER 5-1: WRITE COMMAND REGISTER FOR MCP4922 (12-BIT DAC) W-x W-x W-x W-0 W-x W-x W-x W-x W-x W-x W-x W-x W-x W-x W-x W-x A/B BUF GA SHDN D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 bit 15 bit 0 REGISTER 5-2: WRITE COMMAND REGISTER FOR MCP4912 (10-BIT DAC) W-x W-x W-x W-0 W-x W-x W-x W-x W-x W-x W-x W-x W-x W-x W-x A/B BUF GA SHDN D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 x bit 15 W-x x bit 0 REGISTER 5-3: WRITE COMMAND REGISTER FOR MCP4902 (8-BIT DAC) W-x W-x W-x W-0 W-x W-x W-x W-x W-x W-x W-x W-x W-x W-x W-x A/B BUF GA SHDN D7 D6 D5 D4 D3 D2 D1 D0 x x x bit 15 W-x x bit 0 Where: bit 15 bit 14 A/B: DACA or DACB Selection bit 1 = Write to DACB 0 = Write to DACA BUF: VREF Input Buffer Control bit Buffered Unbuffered 1= 0= bit 13 GA: Output Gain Selection bit 1 = 1x (VOUT = VREF * D/4096) 0 = 2x (VOUT = 2 * VREF * D/4096) bit 12 SHDN: Output Shutdown Control bit 1 = Active mode operation. VOUT is available.  0 = Shutdown the selected DAC channel. Analog output is not available at the channel that was shut down. VOUT pin is connected to 500 ktypical) bit 11-0 D11:D0: DAC Input Data bits. Bit x is ignored. Legend R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR 1 = bit is set 0 = bit is cleared DS22250A-page 24 x = bit is unknown  2010 Microchip Technology Inc. MCP4902/4912/4922 CS 0 1 2 3 4 5 6 7 8 9 10 11 12 (Mode 1,1) 13 14 15 SCK (Mode 0,0) config bits SDI 12 data bits A/B BUF GA SHDN D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 LDAC VOUT FIGURE 5-1: Write Command for MCP4922 (12-bit DAC). CS 0 1 2 3 4 5 6 7 8 9 10 11 12 (Mode 1,1) 13 14 15 SCK (Mode 0,0) config bits SDI 12 data bits A/B BUF GA SHDN D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X X LDAC VOUT Note: X = “don’t care” bits FIGURE 5-2: Write Command for MCP4912 (10-bit DAC). CS 0 1 2 3 4 5 6 7 8 9 10 11 12 (Mode 1,1) 13 14 15 SCK (Mode 0,0) config bits SDI A/B BUF GA SHDN D7 12 data bits D6 D5 D4 D3 D2 D1 D0 X X X X LDAC VOUT Note: FIGURE 5-3: X = “don’t care” bits Write Command for MCP4902 (8-bit DAC).  2010 Microchip Technology Inc. DS22250A-page 25 MCP4902/4912/4922 NOTES: DS22250A-page 26  2010 Microchip Technology Inc. MCP4902/4912/4922 TYPICAL APPLICATIONS VDD Applications generally suited for the devices are: • • • • • VDD Set Point or Offset Trimming Sensor Calibration Digitally-Controlled Multiplier/Divider Portable Instrumentation (Battery Powered) Motor Control Feedback Loop 6.1 Digital Interface The MCP4902/4912/4922 utilizes a 3-wire synchronous serial protocol to transfer the DAC’s setup and output values from the digital source. The serial protocol can be interfaced to SPI or Microwire peripherals that is common on many microcontroller units (MCUs), including Microchip’s PIC® MCUs and dsPIC® DSCs. In addition to the three serial connections (CS, SCK and SDI), the LDAC signal synchronizes the two DAC outputs. By bringing down the LDAC pin to “low”, all DAC input codes and settings in the two DAC input registers are latched into their DAC output registers at the same time. Therefore, both DACA and DACB outputs are updated at the same time. Figure 6-1 shows an example of the pin connections. Note that the LDAC pin can be tied low (VSS) to reduce the required connections from 4 to 3 I/O pins. In this case, the DAC output can be immediately updated when a valid 16-clock transmission has been received and CS pin has been raised. 6.2 Power Supply Considerations The typical application will require a bypass capacitor in order to filter high-frequency noise. The noise can be induced onto the power supply’s traces from various events such as digital switching or as a result of changes on the DAC’s output. The bypass capacitor helps to minimize the effect of these noise sources. Figure 6-1 illustrates an appropriate bypass strategy. In this example, two bypass capacitors are used in parallel: (a) 0.1 µF (ceramic) and (b) 10 µF (tantalum). These capacitors should be placed as close to the device power pin (VDD) as possible (within 4 mm). C2 C1 VREFB VOUTB CS1 SDI VREFA VOUTA VREFB VOUTB SDI C2 C1 VREFA VOUTA C1 VDD AVSS SDO SCK LDAC PIC® Microcontroller C1 = 10 µF C2 = 0.1 µF MCP49x2 The MCP4902/4912/4922 family of devices are general purpose DACs intended to be used in applications where a precision with low-power and moderate bandwidth is required. MCP49x2 6.0 CS0 VSS AVSS FIGURE 6-1: Diagram. 6.3 Typical Connection Layout Considerations Inductively-coupled AC transients and digital switching noises can degrade the input and output signal integrity, and potentially reduce the device performance. Careful board layout will minimize these effects and increase the Signal-to-Noise Ratio (SNR). Bench testing has shown that a multi-layer board utilizing a low-inductance ground plane, isolated inputs and isolated outputs with proper decoupling, is critical for the best performance. Particularly harsh environments may require shielding of critical signals. Breadboards and wire-wrapped boards are not recommended if low noise is desired. The power source supplying these devices should be as clean as possible. If the application circuit has separate digital and analog power supplies, VDD and VSS should reside on the analog plane.  2010 Microchip Technology Inc. DS22250A-page 27 MCP4902/4912/4922 6.4 Single-Supply Operation 6.4.1.1 If the application is calibrating the bias voltage of a diode or transistor, a bias voltage range of 0.8V may be desired with about 200 µV resolution per step. Two common methods to achieve a 0.8V range is to either reduce VREF to 0.82V or use a voltage divider on the DAC’s output. The MCP4902/4912/4922 family of devices are rail-torail voltage output DAC devices designed to operate with a VDD range of 2.7V to 5.5V. Its output amplifier is robust enough to drive small-signal loads directly. Therefore, it does not require any external output buffer for most applications. 6.4.1 Decreasing Output Step Size Using a VREF is an option if the VREF is available with the desired output voltage range. However, occasionally, when using a low-voltage VREF, the noise floor causes SNR error that is intolerable. Using a voltage divider method is another option and provides some advantages when VREF needs to be very low or when the desired output voltage is not available. In this case, a larger value VREF is used while two resistors scale the output range down to the precise desired level. DC SET POINT OR CALIBRATION A common application for the DAC devices is digitally-controlled set points and/or calibration of variable parameters, such as sensor offset or slope. For example, the MCP4922 provides 4096 output steps. If the external voltage reference (VREF) is 4.096V, the LSb size is 1 mV. If a smaller output step size is desired, a lower external voltage reference is needed. Example 6-1 illustrates this concept. Note that the bypass capacitor on the output of the voltage divider plays a critical function in attenuating the output noise of the DAC and the induced noise from the environment. EXAMPLE 6-1: EXAMPLE CIRCUIT OF SET POINT OR THRESHOLD CALIBRATION (a) Single Output DAC: MCP4901 MCP4911 MCP4921 VDD (b) Dual Output DAC: MCP4902 MCP4912 MCP4922 VREF VDD DAC VCC+ RSENSE VOUT R1 VTRIP R2 0.1 uF Comparator VO VCC– SPI 3-wire Dn V OUT = V REF  G  -----N 2  R2  Vtrip = V OUT  --------------------  R1 + R2 DS22250A-page 28 G = Gain selection (1x or 2x) Dn = Digital value of DAC (0-255) for MCP4901/MCP4902 = Digital value of DAC (0-1023) for MCP4911/MCP4912 = Digital value of DAC (0-4095) for MCP4921/MCP4922 N = DAC Bit Resolution  2010 Microchip Technology Inc. MCP4902/4912/4922 6.4.1.2 Building a “Window” DAC If the threshold is not near VREF or VSS, then creating a “window” around the threshold has several advantages. One simple method to create this “window” is to use a voltage divider network with a pull-up and pull-down resistor. Example 6-2 and Example 6-4 illustrate this concept. When calibrating a set point or threshold of a sensor, typically only a small portion of the DAC output range is utilized. If the LSb size is adequate enough to meet the application’s accuracy needs, the unused range is sacrificed without consequences. If greater accuracy is needed, then the output range will need to be reduced to increase the resolution around the desired threshold. EXAMPLE 6-2: SINGLE-SUPPLY “WINDOW” DAC (a) Single Output DAC: MCP4901 MCP4911 MCP4921 (b) Dual Output DAC: MCP4902 MCP4912 MCP4922 VREF VCC+ VCC+ Rsense VDD DAC VOUT R3 R1 Comparator Vtrip 0.1 µF R2 SPI 3 VCC- VCC- Dn V OUT = VREF  G  -----N 2 G = Gain selection (1x or 2x) Dn = Digital value of DAC (0-255) for MCP4901/MCP4902 = Digital value of DAC (0-1023) for MCP4911/MCP4912 = Digital value of DAC (0-4095) for MCP4921/MCP4922 N = DAC Bit Resolution Thevenin Equivalent R 2 R3 R 23 = -----------------R2 + R 3 V 23 VOUT R1 VO  V CC+ R2  +  VCC- R3  = ----------------------------------------------------R 2 + R3 V OUT R23 + V 23 R1 V trip = -------------------------------------------R 2 + R23  2010 Microchip Technology Inc. R23 V23 DS22250A-page 29 MCP4902/4912/4922 6.5 Bipolar Operation Bipolar operation is achievable using the MCP4902/ 4912/4922 family of devices by using an external operational amplifier (op amp). This configuration is desirable due to the wide variety and availability of op amps. This allows a general purpose DAC, with its cost and availability advantages, to meet almost any desired output voltage range, power and noise performance. EXAMPLE 6-3: Example 6-3 illustrates a simple bipolar voltage source configuration. R1 and R2 allow the gain to be selected, while R3 and R4 shift the DAC’s output to a selected offset. Note that R4 can be tied to VREF instead of VSS, if a higher offset is desired. Also note that a pull-up to VREF could be used instead of R4, if a higher offset is desired. DIGITALLY-CONTROLLED BIPOLAR VOLTAGE SOURCE 2 VREF (a) Single Output DAC: MCP4901 MCP4911 MCP4921 VREF VDD (b) Dual Output DAC: DAC MCP4902 MCP4912 MCP4922 VOUT R3 R4 SPI VCC+ R1 VO VIN+ 0.1 µF VCC– 3 Dn VOUT = V REF  G  -----N 2 VIN+ V OUT R4 = -------------------R3 + R 4 R2 R2 VO = V IN+  1 + ------ – VDD  ------   R 1 R1 6.5.1 G = Gain selection (1x or 2x) Dn = Digital value of DAC (0-255) for MCP4901/MCP4902 = Digital value of DAC (0-1023) for MCP4911/MCP4912 = Digital value of DAC (0-4095) for MCP4921/MCP4922 N = DAC Bit Resolution DESIGN EXAMPLE: DESIGN A BIPOLAR DAC USING EXAMPLE 6-3 WITH 12-BIT MCP4922 OR MCP4921 An output step magnitude of 1 mV with an output range of ±2.05V is desired for a particular application. The following steps show the details: Step 1: Calculate the range: +2.05V – (-2.05V) = 4.1V. Step 2: Calculate the resolution needed: 4.1V/1 mV = 4100 Since 212 = 4096, 12-bit resolution is desired. Step 3:The amplifier gain (R2/R1), multiplied by VREF, must be equal to the desired minimum output to achieve bipolar operation. Since any gain can be realized by choosing resistor values (R1+R2), the VREF source needs to be determined first. If a VREF of 4.1V is used, solve for the gain by setting the DAC to 0, knowing that the output needs to be -2.05V. The equation can be simplified to: DS22250A-page 30 –R2 – 2.05 – 2.05 --------- = ------------- = ------------R1 V REF 4.1 R2 1 ------ = --R1 2 If R1 = 20 k and R2 = 10 k, the gain will be 0.5. Step 4: Next, solve for R3 and R4 by setting the DAC to 4096, knowing that the output needs to be +2.05V. R4 2.05V + 0.5V REF 2 ----------------------- = ----------------------------------------- = --1.5VREF  R3 + R 4  3 If R4 = 20 k, then R3 = 10 k  2010 Microchip Technology Inc. MCP4902/4912/4922 6.6 Selectable Gain and Offset Bipolar Voltage Output Using a Dual DAC This circuit is typically used in Multiplier mode and is ideal for linearizing a sensor whose slope and offset varies. Refer to Section 6.9 “Using Multiplier Mode” for more information on Multiplier mode. In some applications, precision digital control of the output range is desirable. Example 6-4 illustrates how to use the MCP4902/4912/4922 to achieve this in a bipolar or single-supply application. EXAMPLE 6-4: The equation to design a bipolar “window” DAC would be utilized if R3, R4 and R5 are populated. BIPOLAR VOLTAGE SOURCE WITH SELECTABLE GAIN AND OFFSET R2 VREFA VDD VOUTA DACA Dual Output DAC: MCP4902 MCP4912 VREFB MCP4922 VCC+ R1 DACA (Gain Adjust) VDD VOUTB DACB VCC+ R5 R3 DACB (Offset Adjust) SPI VO R4 3 0.1uF VCC– VCC– DA VOUTA =  V REFA G A  -----N 2 DB V OUTB =  VREFB G B  -----N 2 GX = Gain selection (1x or 2x) N = DAC Bit Resolution DA, DB = Digital value of DAC (0-255) for MCP4902 VOUTB R 4 + VCC- R3 V IN+ = -----------------------------------------------R3 + R4 = Digital value of DAC (0-1023) for MCP4912 = Digital value of DAC (0-4095) for MCP4922 R2 R2 V O = V IN+  1 + ------ – V OUTA  ------  R 1  R 1 Offset Adjust Gain Adjust Bipolar “Window” DAC using R4 and R5 Thevenin Equivalent V CC+ R4 + V CC- R 5 V45 = -------------------------------------------R4 + R5 VOUTB R 45 + V45 R 3 V IN+ = ----------------------------------------------R3 + R 45 R4 R5 R 45 = -----------------R4 + R5 R2 R2 V O = VIN+  1 + ------ – V OUTA  ------   R 1 R 1 Offset Adjust Gain Adjust  2010 Microchip Technology Inc. DS22250A-page 31 MCP4902/4912/4922 6.7 Designing a Double-Precision DAC Using a Dual DAC Example 6-5 illustrates how to design a single-supply voltage output capable of up to 24-bit resolution from a dual 12-bit DAC. This design is simply a voltage divider with a buffered output. As an example, if a application similar to the one developed in Section 6.5.1 “Design Example: Design a Bipolar DAC Using Example 6-3 with 12-bit MCP4922 or MCP4921” required a resolution of 1 µV instead of 1 mV and a range of 0V to 4.1V, then 12-bit resolution would not be adequate. EXAMPLE 6-5: Step 1: Calculate the resolution needed: 4.1V/1 µV = 4.1x106. Since 222 = 4.2x106, 22bit resolution is desired. Since DNL = ±0.75 LSb, this design can be attempted with the MCP4922. Step 2: Since DACB’s VOUTB has a resolution of 1 mV, its output only needs to be “pulled” 1/1000 to meet the 1 µV target. Dividing VOUTA by 1000 would allow the application to compensate for DACB’s DNL error. Step 3: If R2 is 100, then R1 needs to be 100 k. Step 4:The resulting transfer function is not perfectly linear, as shown in the equation of Example 6-5. SIMPLE, DOUBLE-PRECISION DAC WITH MCP4922 VDD VREF MCP4922 VDD MCP4922 VCC+ VOUTA DACA (Fine Adjust) VO R1 R1 >> R2 VOUTB R2 0.1 µF VCC– DACB (Course Adjust) SPI 3 DA V OUTA = VREFA GA ------12 2 G = Gain selection (1x or 2x) D = Digital value of DAC (0- 4096) VOUTA R 2 + VOUTB R 1 V O = ----------------------------------------------------R 1 + R2 DB V OUTB = VREFB GB ------12 2 DS22250A-page 32  2010 Microchip Technology Inc. MCP4902/4912/4922 6.8 Building Programmable Current Source When working with very small sensor voltages, plan on eliminating the amplifier’s offset error by storing the DAC’s setting under known sensor conditions. Example 6-6 shows an example for building a programmable current source using a voltage follower. The current sensor (sensor resistor) is used to convert the DAC voltage output into a digitally-selectable current source. Adding the resistor network from Example 6-2 would be advantageous in this application. The smaller Rsense is, the less power dissipated across it. However, this also reduces the resolution that the current can be controlled with. The voltage divider, or “window”, DAC configuration would allow the range to be reduced, thus increasing resolution around the range of interest. EXAMPLE 6-6: DIGITALLY-CONTROLLED CURRENT SOURCE VDD or VREF (a) Single Output DAC: VREF MCP4901 MCP4911 MCP4921 VDD DAC VOUT (b) Dual Output DAC: MCP4902 MCP4912 MCP4922 Load VCC+ IL Ib SPI 3-wire VCC– RSENSE IL Ib = --- VOUT  IL = ---------------  -----------R sense  + 1 where Common-Emitter Current Gain Dn VOUT = V REF  G  -----N 2  2010 Microchip Technology Inc. G = Gain select (1x or 2x) Dn = Digital value of DAC (0-255) for MCP4901/MCP4902 = Digital value of DAC (0-1023) for MCP4911/MCP4912 = Digital value of DAC (0-4095) for MCP4921/MCP4922 N = DAC Bit Resolution DS22250A-page 33 MCP4902/4912/4922 6.9 Using Multiplier Mode If the gain selection bit is configured for 1x mode ( = 1), the resulting input signal will be attenuated by D/2n. With the 12-bit DAC (MCP4921 or MCP4922), if the gain is configured for 2x mode ( = 0), the codes less than 2048 attenuate the signal, while the codes greater than 2048 gain the signal. The MCP4902/4912/4922 family of devices use external reference, and these devices are ideally suited for use as a multiplier/divider in a signal chain. The common applications are: (a) Precision programmable gain/attenuator amplifiers and (b) Motor control feedback loop. The wide input range (0V – VDD) is in Unbuffered mode and near rail-to-rail range in Buffered mode: its bandwidth (> 400 kHz), selectable 1x/2x gain and low power consumption give maximum flexibility to meet the application’s needs. A DAC provides significantly more gain/attenuation resolution when compared to typical Programmable Gain Amplifiers. Adding an op amp to buffer the output, as illustrated in Examples 6-2 to 6-6, extends the output range and power to meet the precise needs of the application. To configure the MCP4902/4912/4922 family of devices for multiple applications, connect the input signal to VREF and serially configure the DAC’s input buffer, gain and output value. The DAC’s output can utilize any of Examples 6-1 to 6-6, depending on the application requirements. Example 6-7 is an illustration of how the DAC can operate in a motor control feedback loop. EXAMPLE 6-7: MULTIPLIER MODE USING VREF INPUT VRPM_SET VRPM (a) Single Output DAC: MCP4901 MCP4911 MCP4921 (b) Dual Output DAC: MCP4902 MCP4912 MCP4922 VDD DAC VREF ZFB VOUT SPI 3 VCC+ + – VCCRsense Dn V OUT = V REF  G  -----N 2 DS22250A-page 34  2010 Microchip Technology Inc. MCP4902/4912/4922 7.0 DEVELOPMENT SUPPORT 7.1 Evaluation and Demonstration Boards The Mixed Signal PICtailTM Demo Board supports the MCP4902/4912/4922 family of devices. Please refer to www.microchip.com for further information on this products capabilities and availability.  2010 Microchip Technology Inc. DS22250A-page 35 MCP4902/4912/4922 NOTES: DS22250A-page 36  2010 Microchip Technology Inc. MCP4902/4912/4922 8.0 PACKAGING INFORMATION 8.1 Package Marking Information 14-Lead PDIP (300 mil) Example: XXXXXXXXXXXXXX XXXXXXXXXXXXXX YYWWNNN 14-Lead SOIC (150 mil) MCP4922 E/P e3 1011256 Example: XXXXXXXXXX XXXXXXXXXX YYWWNNN Example: 14-Lead TSSOP XXXXXX YYWW 4922E/ST 1011 NNN 256 Legend: XX...X Y YY WW NNN e3 * Note: MCP4922 E/SL e3 1011256 Customer-specific information Year code (last digit of calendar year) Year code (last 2 digits of calendar year) Week code (week of January 1 is week ‘01’) Alphanumeric traceability code Pb-free JEDEC designator for Matte Tin (Sn) This package is Pb-free. The Pb-free JEDEC designator ( e3 ) can be found on the outer packaging for this package. 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