MCP6001/1R/1U/2/4
1 MHz, Low-Power Op Amp
Features
Description
•
•
•
•
•
•
•
The Microchip Technology Inc. MCP6001/2/4 family of
operational amplifiers (op amps) is specifically
designed for general-purpose applications. This family
has a 1 MHz Gain Bandwidth Product (GBWP) and 90°
phase margin (typical). It also maintains 45° phase
margin (typical) with a 500 pF capacitive load. This
family operates from a single supply voltage as low as
1.8V, while drawing 100 µA (typical) quiescent current.
Additionally, the MCP6001/2/4 supports rail-to-rail input
and output swing, with a Common-mode input voltage
range of VDD + 300 mV to VSS – 300 mV. This family of
op amps is designed with Microchip’s advanced CMOS
process.
Available in SC-70-5 and SOT-23-5 packages
Gain Bandwidth Product: 1 MHz (typical)
Rail-to-Rail Input/Output
Supply Voltage: 1.8V to 6.0V
Supply Current: IQ = 100 µA (typical)
Phase Margin: 90° (typical)
Temperature Range:
- Industrial: -40°C to +85°C
- Extended: -40°C to +125°C
• Available in Single, Dual and Quad Packages
Applications
•
•
•
•
•
•
The MCP6001/2/4 family is available in the industrial
and extended temperature ranges, with a power supply
range of 1.8V to 6.0V.
Automotive
Portable Equipment
Photodiode Amplifier
Analog Filters
Notebooks and PDAs
Battery-Powered Systems
Package Types
VOUT 1
VSS 2
SPICE Macro Models
FilterLab® Software
Mindi™ Circuit Designer & Simulator
Microchip Advanced Part Selector (MAPS)
Analog Demonstration and Evaluation Boards
Application Notes
VDD 2
VIN+ 3
+
VOUT
+ –
4 VIN–
MCP6002
MCP6001U
SOT-23-5
VOUTA 1
8 VDD
–+
VINA– 2
+
-
5 VDD
VIN+ 1
7 VOUTB
VSS 2
6 VINB–
VIN– 3
+
–
VOUTA 1
VINA+ 3
VSS 4
MCP6004
PDIP, SOIC, TSSOP
8 VDD
EP
9
14 VOUTD
VOUTA 1
V –
7 VOUTB INA 2
– + + – 13 VIND–
V +
6 VINB– INA 3
5 V + VDD 4
12 VIND+
11 VSS
INB
VINB+ 5
R1
R1
Gain = 1 + -----R2
Non-Inverting Amplifier
2019 Microchip Technology Inc.
4 VOUT
5 VINB+
VINA– 2
VSS
5 VSS
PDIP, SOIC, MSOP
MCP6002
2x3 DFN *
MCP6001
–
VREF
4 VIN–
VIN+ 3
VSS 4
VDD
R2
5 VDD
VOUT 1
+ –
VINA+ 3
Typical Application
VIN
SOT-23-5
SC70-5, SOT-23-5
Design Aids
•
•
•
•
•
•
MCP6001R
MCP6001
VINB– 6
VOUTB 7
10 VINC+
– + +–
9 VINC–
8 VOUTC
* Includes Exposed Thermal Pad (EP); see Table 3-1.
DS20001733K-page 1
MCP6001/1R/1U/2/4
NOTES:
DS20001733K-page 2
2019 Microchip Technology Inc.
MCP6001/1R/1U/2/4
1.0
ELECTRICAL
CHARACTERISTICS
VDD – VSS ........................................................................7.0V
† Notice: Stresses above those listed under “Absolute
Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of
the device at those or any other conditions above those
indicated in the operational listings of this specification is not
implied. Exposure to maximum rating conditions for extended
periods may affect device reliability.
Current at Analog Input Pins (VIN+, VIN–).....................±2 mA
†† See Section 4.1.2 “Input Voltage and Current Limits”.
Absolute Maximum Ratings †
Analog Inputs (VIN+, VIN–) †† ........ VSS – 1.0V to VDD + 1.0V
All Other Inputs and Outputs ......... VSS – 0.3V to VDD + 0.3V
Difference Input Voltage ...................................... |VDD – VSS|
Output Short Circuit Current ................................ Continuous
Current at Output and Supply Pins ............................±30 mA
Storage Temperature ................................... –65°C to +150°C
Maximum Junction Temperature (TJ)......................... .+150°C
ESD Protection On All Pins (HBM; MM) 4 kV; 200V
DC ELECTRICAL SPECIFICATIONS
Electrical Characteristics: Unless otherwise indicated, TA = +25°C, VDD = +1.8V to +5.5V, VSS = GND, VCM = VDD/2, VL = VDD/2,
RL = 10 kto VL, and VOUT VDD/2 (refer to Figure 1-1).
Parameters
Sym
Min
Typ
Max
Units
VOS
-4.5
—
+4.5
mV
VOS/TA
—
±2.0
—
µV/°C
PSRR
—
86
—
dB
Conditions
Input Offset
Input Offset Voltage
Input Offset Drift with Temperature
Power Supply Rejection Ratio
VCM = VSS (Note 1)
TA= -40°C to +125°C,
VCM = VSS
VCM = VSS
Input Bias Current and Impedance
IB
—
±1.0
—
pA
Industrial Temperature
IB
—
19
—
pA
TA = +85°C
Extended Temperature
IB
—
1100
—
pA
TA = +125°C
Input Offset Current
IOS
—
±1.0
—
pA
Common-mode Input Impedance
ZCM
—
1013||6
—
||pF
Differential Input Impedance
ZDIFF
—
1013||3
—
||pF
Common-mode Input Range
VCMR
VSS 0.3
—
VDD + 0.3
V
Common-mode Rejection Ratio
CMRR
60
76
—
dB
VCM = -0.3V to 5.3V,
VDD = 5V
AOL
88
112
—
dB
VOUT = 0.3V to VDD – 0.3V,
VCM = VSS
VOL, VOH
VSS + 25
—
VDD – 25
mV
VDD = 5.5V,
0.5V Input Overdrive
Input Bias Current:
Common-mode
Open-Loop Gain
DC Open-Loop Gain (Large Signal)
Output
Maximum Output Voltage Swing
Output Short Circuit Current
—
±6
—
mA
VDD = 1.8V
—
±23
—
mA
VDD = 5.5V
VDD
1.8
—
6.0
V
Note 2
IQ
50
100
170
µA
IO = 0, VDD = 5.5V, VCM = 5V
ISC
Power Supply
Supply Voltage
Quiescent Current per Amplifier
Note 1:
2:
MCP6001/1R/1U/2/4 parts with date codes prior to December 2004 (week code 49) were tested to ±7 mV
minimum/maximum limits.
All parts with date codes November 2007 and later have been screened to ensure operation at
VDD = 6.0V. However, the other minimum and maximum specifications are measured at 1.8V and 5.5V.
2019 Microchip Technology Inc.
DS20001733K-page 3
MCP6001/1R/1U/2/4
AC ELECTRICAL SPECIFICATIONS
Electrical Characteristics: Unless otherwise indicated, TA = +25°C, VDD = +1.8 to 5.5V, VSS = GND, VCM = VDD/2,
VL = VDD/2, VOUT VDD/2, RL = 10 k to VL, and CL = 60 pF (refer to Figure 1-1).
Parameters
Sym
Min
Typ
Max
Units
Conditions
GBWP
—
1.0
—
MHz
Phase Margin
PM
—
90
—
°
Slew Rate
SR
—
0.6
—
V/µs
Input Noise Voltage
Eni
—
6.1
—
µVp-p
Input Noise Voltage Density
eni
—
28
—
nV/Hz
f = 1 kHz
Input Noise Current Density
ini
—
0.6
—
fA/Hz
f = 1 kHz
AC Response
Gain Bandwidth Product
G = +1 V/V
Noise
f = 0.1 Hz to 10 Hz
TEMPERATURE SPECIFICATIONS
Electrical Characteristics: Unless otherwise indicated, VDD = +1.8V to +5.5V and VSS = GND.
Parameters
Sym
Min
Typ
Max
Units
Industrial Temperature Range
TA
-40
—
+85
°C
Extended Temperature Range
TA
-40
—
+125
°C
Operating Temperature Range
TA
-40
—
+125
°C
Storage Temperature Range
TA
-65
—
+150
°C
Thermal Resistance, 5L-SC70
JA
—
331
—
°C/W
Thermal Resistance, 5L-SOT-23
JA
—
256
—
°C/W
Thermal Resistance, 8L-PDIP
JA
—
85
—
°C/W
Thermal Resistance, 8L-SOIC (150 mil)
JA
—
163
—
°C/W
Thermal Resistance, 8L-MSOP
JA
—
206
—
°C/W
Thermal Resistance, 8L-DFN (2x3)
JA
—
68
—
°C/W
Thermal Resistance, 14L-PDIP
JA
—
70
—
°C/W
Thermal Resistance, 14L-SOIC
JA
—
120
—
°C/W
Thermal Resistance, 14L-TSSOP
JA
—
100
—
°C/W
Conditions
Temperature Ranges
Note
Thermal Package Resistances
Note:
The industrial temperature devices operate over this extended temperature range, but with reduced
performance. In any case, the internal Junction Temperature (TJ) must not exceed the Absolute Maximum
specification of +150°C.
DS20001733K-page 4
2019 Microchip Technology Inc.
MCP6001/1R/1U/2/4
1.1
Test Circuits
The circuit used for most DC and AC tests is shown in
Figure 1-1. This circuit can independently set VCM and
VOUT; see Equation 1-1. Note that VCM is not the
circuit’s Common-mode voltage ((VP + VM)/2), and that
VOST includes VOS plus the effects (on the input offset
error, VOST) of temperature, CMRR, PSRR and AOL.
CF
6.8 pF
RG
100 k
VP
G DM = R F R G
MCP600X
V CM = V P + V DD 2 2
CB1
100 nF
+
–
VDD/2
CB2
1 µF
VIN–
V OST = V IN– – V IN+
V OUT = V DD 2 + V P – V M + V OST 1 + G DM
Where:
GDM = Differential Mode Gain
(V/V)
VCM = Op Amp’s Common-mode
Input Voltage
(V)
2019 Microchip Technology Inc.
VDD
VIN+
EQUATION 1-1:
VOST = Op Amp’s Total Input Offset
Voltage
RF
100 k
(mV)
VM
RG
100 k
RL
10 k
RF
100 k
CF
6.8 pF
VOUT
CL
60 pF
VL
FIGURE 1-1:
AC and DC Test Circuit for
Most Specifications.
DS20001733K-page 5
MCP6001/1R/1U/2/4
NOTES:
DS20001733K-page 6
2019 Microchip Technology Inc.
MCP6001/1R/1U/2/4
2.0
TYPICAL PERFORMANCE CURVES
Note:
The graphs and tables provided following this note are a statistical summary based on a limited number of
samples and are provided for informational purposes only. The performance characteristics listed herein
are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified
operating range (e.g., outside specified power supply range) and therefore outside the warranted range.
Input Offset Voltage (µV)
-300
-400
TA = -40°C
TA = +25°C
TA = +85°C
TA = +125°C
-500
-600
0
0.05
0.04
0.03
0.02
0.01
0.00
-0.01
-0.02
2.2
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
-300
-400
TA = -40°C
TA = +25°C
TA = +85°C
TA = +125°C
-500
-600
6.0
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
Common Mode Input Voltage (V)
Input Offset Quadratic Temp. Co.;
TC2 (µV/°C2)
Input Offset Quadratic
2019 Microchip Technology Inc.
-200
-700
10 12
2453 Samples
TA = -40°C to +125°C
VCM = VSS
FIGURE 2-3:
Temp. Co.
VDD = 5.5V
-100
-0.5
8
Input Offset Voltage Drift.
45%
40%
35%
30%
25%
20%
15%
10%
5%
0%
0.4
FIGURE 2-4:
Input Offset Voltage vs.
Common-mode Input Voltage at VDD = 1.8V.
2453 Samples
TA = -40°C to +125°C
VCM = VSS
FIGURE 2-2:
0.2
Common Mode Input Voltage (V)
Input Offset Voltage.
-12 -10 -8 -6 -4 -2 0 2 4 6
Input Offset Voltage Drift;
TC1 (µV/°C)
0.0
5
-0.2
4
-0.4
-2 -1
0
1
2
3
Input Offset Voltage (mV)
Input Offset Voltage (µV)
Percentage of Occurrences
-200
0.0
-3
FIGURE 2-5:
Input Offset Voltage vs.
Common-mode Input Voltage at VDD = 5.5V.
200
Input Offset Voltage (µV)
-4
FIGURE 2-1:
Percentage of Occurrences
VDD = 1.8V
-100
-700
5
18%
16%
14%
12%
10%
8%
6%
4%
2%
0%
0
64,695 Samples
VCM = VSS
0.07
20%
18%
16%
14%
12%
10%
8%
6%
4%
2%
0%
0.06
Percentage of Occurrences
Note: Unless otherwise indicated, TA = +25°C, VDD = +1.8V to +5.5V, VSS = GND, VCM = VDD/2, VOUT VDD/2,
VL = VDD/2, RL = 10 kto VL, and CL = 60 pF.
150
100
50
0
VDD = 5.5V
VDD = 1.8V
-50
-100
-150
VCM = VSS
-200
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Output Voltage (V)
FIGURE 2-6:
Output Voltage.
Input Offset Voltage vs.
DS20001733K-page 7
MCP6001/1R/1U/2/4
Note: Unless otherwise indicated, TA = +25°C, VDD = +1.8V to +5.5V, VSS = GND, VCM = VDD/2, VOUT VDD/2,
VL = VDD/2, RL = 10 kto VL, and CL = 60 pF.
10%
8%
6%
4%
2%
70
PSRR–
60
PSRR+
50
CMRR
40
6
55%
50%
45%
40%
35%
30%
25%
20%
15%
10%
5%
0%
9 12 15 18 21 24
Input Bias Current (pA)
27
Input Bias Current at +85°C.
Input Bias Current (pA)
1k
10k
1.E+03
1.E+04
Frequency (Hz)
100k
1.E+05
PSRR, CMRR vs.
0
100
-30
80
Phase
60
-90
40
Gain
20
0
-60
-120
-150
VCM = VSS
-180
-20
-210
0.1 1.E+
1 1.E+
10 1.E+
100 1.E+
1k 1.E+
10k 100k
1M 10M
1.E1.E+ 1.E+
1.E+
(Hz) 05 06 07
01 00 01 Frequency
02 03 04
Open-Loop Gain, Phase vs.
1,000
Input Noise Voltage Density
(nV/Hz)
95
90
PSRR (VCM = VSS)
85
80
CMRR (VCM = -0.3V to +5.3V)
75
70
-25
100
1.E+02
120
FIGURE 2-11:
Frequency.
Input Bias Current at
VDD = 5.0V
-50
FIGURE 2-10:
Frequency.
Open-Loop Gain (dB)
1500
1350
1200
1050
900
750
600
300
150
0
605 Samples
VDD = 5.5V
VCM = VDD
TA = +125°C
FIGURE 2-8:
+125°C.
20
10
1.E+01
30
Open-Loop Phase (°)
3
FIGURE 2-7:
PSRR, CMRR (dB)
80
30
0%
100
VCM = VSS
90
PSRR, CMRR (dB)
12%
0
Percentage of Occurrences
100
1230 Samples
VDD = 5.5V
VCM = VDD
TA = +85°C
450
Percentage of Occurrences
14%
0
25
50
75
Ambient Temperature (°C)
FIGURE 2-9:
Temperature.
DS20001733K-page 8
100
125
CMRR, PSRR vs. Ambient
100
10
0.1
1
10
100 1.E+0
1k
10k 1.E+0
100k
1.E-01
1.E+0
1.E+0
1.E+0
1.E+0
0
1Frequency
2 (Hz)3
4
5
FIGURE 2-12:
vs. Frequency.
Input Noise Voltage Density
2019 Microchip Technology Inc.
MCP6001/1R/1U/2/4
Note: Unless otherwise indicated, TA = +25°C, VDD = +1.8V to +5.5V, VSS = GND, VCM = VDD/2, VOUT VDD/2,
VL = VDD/2, RL = 10 kto VL, and CL = 60 pF.
0.08
G = +1 V/V
25
Output Voltage (20 mV/div)
Short Circuit Current
Magnitude (mA)
30
TA = -40°C
TA = +25°C
TA = +85°C
TA = +125°C
20
15
10
5
0
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Power Supply Voltage (V)
FIGURE 2-13:
Output Short Circuit Current
vs. Power Supply Voltage.
0.02
0.00
-0.02
-0.04
-0.06
1.E-06
2.E-06
3.E-06
4.E-06
5.E-06
6.E-06
7.E-06
8.E-06
FIGURE 2-16:
Pulse Response.
G = +1 V/V
VDD = 5.0V
VOL – VSS
10
1
10µ
1.E-05
160
10m
1.E-02
120
100
80
40
20
3.5
3.0
2.5
2.0
1.5
1.0
0.0
TA = +125°C
TA = +85°C
TA = +25°C
TA = -40°C
0
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
0.E+00
1.E-05
2019 Microchip Technology Inc.
3.E-05
FIGURE 2-17:
Pulse Response.
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.0
4.E-05
5.E-05
6.E-05
7.E-05
8.E-05
9.E-05
1.E-04
Large-Signal, Non-Inverting
VDD = 5.5V
Falling Edge
VDD = 1.8V
Rising Edge
-50
-25
0
25
50
75
100
125
Ambient Temperature (°C)
Power Supply Voltage (V)
FIGURE 2-15:
Quiescent Current vs.
Power Supply Voltage.
2.E-05
Time (10 µs/div)
VCM = VDD - 0.5V
140
60
4.0
0.5
100µ
1m
1.E-04
1.E-03
Output Current Magnitude (A)
FIGURE 2-14:
Output Voltage Headroom
vs. Output Current Magnitude.
180
Output Voltage (V)
4.5
VDD – VOH
1.E-05
Small-Signal, Non-Inverting
5.0
100
9.E-06
Time (1 µs/div)
Slew Rate (V/µs)
Output Voltage Headroom
(mV)
0.04
-0.08
0.E+00
1,000
Quiescent Current
per amplifier (µA)
0.06
FIGURE 2-18:
Temperature.
Slew Rate vs. Ambient
DS20001733K-page 9
MCP6001/1R/1U/2/4
6
10
Input, Output Voltages (V)
Output Voltage Swing (V
P-P )
Note: Unless otherwise indicated, TA = +25°C, VDD = +1.8V to +5.5V, VSS = GND, VCM = VDD/2, VOUT VDD/2,
VL = VDD/2, RL = 10 kto VL, and CL = 60 pF.
VDD = 5.5V
VDD = 1.8V
1
0.1
1k
1.E+03
10k
100k
1.E+04
1.E+05
Frequency (Hz)
FIGURE 2-19:
Frequency.
Input Current Magnitude (A)
1.E-02
10m
1m
1.E-03
100µ
1.E-04
10µ
1.E-05
1µ
1.E-06
100n
1.E-07
10n
1.E-08
1n
1.E-09
100p
1.E-10
10p
1.E-11
1p
1.E-12
1M
1.E+06
Output Voltage Swing vs.
VIN
5
VDD = 5.0V
G = +2 V/V
VOUT
4
3
2
1
0
-1
0.E+00
1.E-05
2.E-05
3.E-05
4.E-05
5.E-05
6.E-05
7.E-05
8.E-05
9.E-05
1.E-04
Time (10 µs/div)
FIGURE 2-21:
Phase Reversal.
The MCP6001/2/4 Show No
+125°C
+85°C
+25°C
-40°C
-1.0 -0.9 -0.8 -0.7 -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0.0
Input Voltage (V)
FIGURE 2-20:
Measured Input Current vs.
Input Voltage (below VSS).
DS20001733K-page 10
2019 Microchip Technology Inc.
MCP6001/1R/1U/2/4
3.0
PIN DESCRIPTIONS
Descriptions of the pins are listed in Table 3-1.
TABLE 3-1:
PIN FUNCTION TABLE
MCP6001 MCP6001R MCP6001U
SC70-5,
SOT-23-5
3.1
SOT-23-5
SOT-23-5
MCP6002
MSOP,
PDIP,
SOIC
DFN
2x3
Symbol
Description
1
1
4
1
1
1
VOUT, VOUTA Analog Output (op amp A)
4
3
2
2
2
VIN–, VINA– Inverting Input (op amp A)
3
3
1
3
3
3
VIN+, VINA+ Non-inverting Input (op amp A)
5
2
5
8
8
4
VDD
—
—
—
5
5
5
VINB+
—
—
—
6
6
6
VINB–
Inverting Input (op amp B)
—
—
—
7
7
7
VOUTB
Analog Output (op amp B)
—
—
—
—
—
8
VOUTC
Analog Output (op amp C)
—
—
—
—
—
9
VINC–
Inverting Input (op amp C)
—
—
—
—
—
10
VINC+
Non-inverting Input (op amp C)
Positive Power Supply
Non-inverting Input (op amp B)
2
5
2
4
4
11
VSS
—
—
—
—
—
12
VIND+
Non-inverting Input (op amp D)
—
—
—
—
—
13
VIND–
Inverting Input (op amp D)
—
—
—
—
—
14
VOUTD
—
—
—
—
9
—
EP
Analog Outputs
Analog Inputs
The non-inverting and inverting inputs are
high-impedance CMOS inputs with low bias currents.
3.3
PDIP,
SOIC,
TSSOP
4
The output pins are low-impedance voltage sources.
3.2
MCP6004
3.4
Negative Power Supply
Analog Output (op amp D)
Exposed Thermal Pad (EP);
must be connected to VSS.
Exposed Thermal Pad (EP)
There is an internal electrical connection between the
Exposed Thermal Pad (EP) and the VSS pin; they must
be connected to the same potential on the Printed
Circuit Board (PCB).
Power Supply Pins
The positive power supply (VDD) is 1.8V to 6.0V higher
than the negative power supply (VSS). For normal
operation, the other pins are at voltages between VSS
and VDD.
Typically, these parts are used in a single (positive)
supply configuration. In this case, VSS is connected to
ground and VDD is connected to the supply. VDD will
need bypass capacitors.
2019 Microchip Technology Inc.
DS20001733K-page 11
MCP6001/1R/1U/2/4
NOTES:
DS20001733K-page 12
2019 Microchip Technology Inc.
MCP6001/1R/1U/2/4
4.0
APPLICATION INFORMATION
The MCP6001/2/4 family of op amps is manufactured
using Microchip’s state-of-the-art CMOS process and
is specifically designed for low-cost, low-power and
general-purpose applications. The low supply voltage,
low quiescent current and wide bandwidth makes the
MCP6001/2/4 ideal for battery-powered applications.
This device has high phase margin, which makes it
stable for larger capacitive load applications.
4.1
VDD, and dump any currents onto VDD. When
implemented as shown, resistors R1 and R2 also limit
the current through D1 and D2.
VDD
D1
V1
R1
Rail-to-Rail Inputs
4.1.1
R2
PHASE REVERSAL
INPUT VOLTAGE AND CURRENT
LIMITS
The ESD protection on the inputs can be depicted as
shown in Figure 4-1. This structure was chosen to
protect the input transistors, and to minimize input bias
current (IB). The input ESD diodes clamp the inputs
when they try to go more than one diode drop below
VSS. They also clamp any voltages that go too far
above VDD; their breakdown voltage is high enough to
allow normal operation, and low enough to bypass
quick ESD events within the specified limits.
VDD Bond
Pad
R3
VSS – (minimum expected V1)
2 mA
VSS – (minimum expected V2)
R2 >
2 mA
R1 >
FIGURE 4-2:
Inputs.
Input
Stage
Bond V –
IN
Pad
VSS Bond
Pad
FIGURE 4-1:
Structures.
Simplified Analog Input ESD
In order to prevent damage and/or improper operation
of these op amps, the circuit they are in must limit the
currents and voltages at the VIN+ and VIN– pins (see
Absolute Maximum Ratings † at the beginning of
Section 1.0 “Electrical Characteristics”). Figure 4-2
shows the recommended approach to protecting these
inputs. The internal ESD diodes prevent the input pins
(VIN+ and VIN–) from going too far below ground, and
the resistors R1 and R2 limit the possible current drawn
out of the input pins. Diodes D1 and D2 prevent the
input pins (VIN+ and VIN–) from going too far above
2019 Microchip Technology Inc.
Protecting the Analog
It is also possible to connect the diodes to the left of
resistors R1 and R2. In this case, current through the
diodes D1 and D2 needs to be limited by some other
mechanism. The resistors then serve as in-rush current
limiters; the DC current into the input pins (VIN+ and
VIN–) should be very small.
A significant amount of current can flow out of the
inputs when the Common-mode voltage (VCM) is below
ground (VSS); see Figure 2-20. Applications that are
high impedance may need to limit the usable voltage
range.
4.1.3
VIN+ Bond
Pad
+
MCP600X
–
V2
The MCP6001/1R/1U/2/4 op amp is designed to
prevent phase reversal when the input pins exceed the
supply voltages. Figure 2-21 shows the input voltage
exceeding the supply voltage without any phase
reversal.
4.1.2
D2
NORMAL OPERATION
The input stage of the MCP6001/1R/1U/2/4 op amps
use two differential CMOS input stages in parallel. One
operates at low Common-mode input voltage (VCM),
while the other operates at high VCM. WIth this
topology, the device operates with VCM up to 0.3V
above VDD and 0.3V below VSS.
The transition between the two input stages occurs
when VCM = VDD – 1.1V. For the best distortion and
gain linearity, with non-inverting gains, avoid this region
of operation.
4.2
Rail-to-Rail Output
The output voltage range of the MCP6001/2/4 op amps
is VDD – 25 mV (minimum) and VSS + 25 mV
(maximum) when RL = 10 k is connected to VDD/2
and VDD = 5.5V. Refer to Figure 2-14 for more
information.
DS20001733K-page 13
MCP6001/1R/1U/2/4
4.3
Capacitive Loads
4.4
Driving large capacitive loads can cause stability
problems for voltage feedback op amps. As the load
capacitance increases, the feedback loop’s phase
margin decreases and the closed-loop bandwidth is
reduced. This produces gain peaking in the frequency
response, with overshoot and ringing in the step
response. While a unity-gain buffer (G = +1) is the most
sensitive to capacitive loads, all gains show the same
general behavior.
When driving large capacitive loads with these op
amps (e.g., > 100 pF when G = +1), a small series
resistor at the output (RISO in Figure 4-3) improves the
feedback loop’s phase margin (stability) by making the
output load resistive at higher frequencies. The
bandwidth will be generally lower than the bandwidth
with no capacitance load.
–
RISO
VOUT
MCP600X
VIN
+
CL
Supply Bypass
With this family of operational amplifiers, the power
supply pin (VDD for single-supply) should have a local
bypass capacitor (i.e., 0.01 µF to 0.1 µF) within 2 mm
for good high-frequency performance. It also needs a
bulk capacitor (i.e., 1 µF or larger) within 100 mm to
provide large, slow currents. This bulk capacitor can be
shared with nearby analog parts.
4.5
Unused Op Amps
An unused op amp in a quad package (MCP6004)
should be configured as shown in Figure 4-5. These
circuits prevent the output from toggling and causing
crosstalk. Circuits A sets the op amp at its minimum
noise gain. The resistor divider produces any desired
reference voltage within the output voltage range of the
op amp; the op amp buffers that reference voltage.
Circuit B uses the minimum number of components
and operates as a comparator, but it may draw more
current.
¼ MCP6004 (A)
VDD
FIGURE 4-3:
Output resistor, RISO
stabilizes large capacitive loads.
R1
Figure 4-4 gives recommended RISO values for
different capacitive loads and gains. The x-axis is the
normalized load capacitance (CL/GN), where GN is the
circuit's noise gain. For non-inverting gains, GN and the
Signal Gain are equal. For inverting gains, GN is
1+|Signal Gain| (e.g., -1 V/V gives GN = +2 V/V).
R2
VDD
VDD
+
–
Recommended RISO (Ω)
100
VDD = 5.0V
RL = 100 k
GN = 1
GN 2
10
10p
1.E-11
100p
1n
10n
1.E-10
1.E-09
1.E-08
Normalized Load Capacitance; CL/GN (F)
FIGURE 4-4:
Recommended RISO values
for Capacitive Loads.
After selecting RISO for your circuit, double-check the
resulting frequency response peaking and step
response overshoot. Modify RISO’s value until the
response is reasonable. Bench evaluation and
simulations with the MCP6001/1R/1U/2/4 SPICE
macro model are very helpful.
DS20001733K-page 14
+
VREF
–
R2
V REF = V DD -----------------R1 + R2
FIGURE 4-5:
1000
¼ MCP6004 (B)
4.6
Unused Op Amps.
PCB Surface Leakage
In applications where low input bias current is critical,
Printed Circuit Board (PCB) surface leakage effects
need to be considered. Surface leakage is caused by
humidity, dust or other contamination on the board.
Under low humidity conditions, a typical resistance
between nearby traces is 1012. A 5V difference would
cause 5 pA of current to flow; which is greater than the
MCP6001/1R/1U/2/4 family’s bias current at 25°C (typically 1 pA).
The easiest way to reduce surface leakage is to use a
guard ring around sensitive pins (or traces). The guard
ring is biased at the same voltage as the sensitive pin.
An example of this type of layout is shown in
Figure 4-6.
2019 Microchip Technology Inc.
MCP6001/1R/1U/2/4
VIN-
VIN+
VSS
–
VIN1
R1
R2
1/2
MCP6002
+
–
VOUT
MCP6001
+
–
Guard Ring
FIGURE 4-6:
for Inverting Gain.
1.
2.
4.7
4.7.1
VIN2
Example Guard Ring Layout
Non-inverting Gain and Unity-Gain Buffer:
a.Connect the non-inverting pin (VIN+) to the
input with a wire that does not touch the
PCB surface.
b.Connect the guard ring to the inverting input
pin (VIN–). This biases the guard ring to the
Common-mode input voltage.
Inverting Gain and Transimpedance Gain
Amplifiers (convert current to voltage, such as
photo detectors):
a.Connect the guard ring to the non-inverting
input pin (VIN+). This biases the guard ring
to the same reference voltage as the op
amp (e.g., VDD/2 or ground).
b.Connect the inverting pin (VIN–) to the input
with a wire that does not touch the PCB
surface.
Application Circuits
UNITY-GAIN BUFFER
The rail-to-rail input and output capability of the
MCP6001/2/4 op amp is ideal for unity-gain buffer
applications. The low quiescent current and wide
bandwidth makes the device suitable for a buffer
configuration in an instrumentation amplifier circuit, as
shown in Figure 4-7.
R2
1/2
MCP6002
+
R1
R1 = 20 k
R2 = 10 k
VREF
R1
V OUT = V IN2 – V IN1 ------ + V REF
R2
FIGURE 4-7:
Instrumentation Amplifier
with Unity-Gain Buffer Inputs.
4.7.2
ACTIVE LOW-PASS FILTER
The MCP6001/2/4 op amp’s low input bias current
makes it possible for the designer to use larger
resistors and smaller capacitors for active low-pass
filter applications. However, as the resistance
increases, the noise generated also increases.
Parasitic capacitances and the large value resistors
could also modify the frequency response. These
trade-offs need to be considered when selecting circuit
elements.
Usually, the op amp bandwidth is 100x the filter cutoff
frequency (or higher) for good performance. It is
possible to have the op amp bandwidth 10X higher
than the cutoff frequency, thus having a design that is
more sensitive to component tolerances.
Figure 4-8 shows a second-order Butterworth filter with
100 kHz cutoff frequency and a gain of +1 V/V; the op
amp bandwidth is only 10x higher than the cutoff
frequency. The component values were selected using
Microchip’s FilterLab® software.
100 pF
VIN 14.3 k 53.6 k
+
MCP6002
33 pF
FIGURE 4-8:
Low-Pass Filter.
2019 Microchip Technology Inc.
–
VOUT
Active Second-Order
DS20001733K-page 15
MCP6001/1R/1U/2/4
4.7.3
PEAK DETECTOR
EQUATION 4-1:
The MCP6001/2/4 op amp has a high input impedance,
rail-to-rail input/output and low input bias current, which
makes this device suitable for peak detector
applications. Figure 4-9 shows a peak detector circuit
with clear and sample switches. The peak-detection
cycle uses a clock (CLK), as shown in Figure 4-9.
dV C1
I SC = C 1 ------------dt
I SC
dV C1
------------- = -------dt
C1
At the rising edge of CLK, Sample Switch closes to
begin sampling. The peak voltage stored on C1 is
sampled to C2 for a sample time defined by tSAMP. At
the end of the sample time (falling edge of Sample
Signal), Clear Signal goes high and closes the Clear
Switch. When the Clear Switch closes, C1 discharges
through R1 for a time defined by tCLEAR. At the end of
the clear time (falling edge of Clear Signal), op amp A
begins to store the peak value of VIN on C1 for a time
defined by tDETECT.
dV C1
------------- = 250mV s
dt
25mA
= --------------0.1F
This voltage rate of change is less than the MCP6001/2/4
slew rate of 0.6 V/µs. When the input voltage swings
below the voltage across C1, D1 becomes
reverse-biased. This opens the feedback loop and rails
the amplifier. When the input voltage increases, the
amplifier recovers at its slew rate. Based on the rate of
voltage change shown in the above equation, it takes an
extended period of time to charge a 0.1 µF capacitor. The
capacitors need to be selected so that the circuit is not
limited by the amplifier slew rate. Therefore, the
capacitors should be less than 40 µF and a stabilizing
resistor (RISO) needs to be properly selected. (Refer to
Section 4.3 “Capacitive Loads”).
In order to define tSAMP and tCLEAR, it is necessary to
determine the capacitor charging and discharging
period. The capacitor charging time is limited by the
amplifier source current, while the discharging time ()
is defined using R1 ( = R1C1). tDETECT is the time that
the input signal is sampled on C1 and is dependent on
the input voltage change frequency.
The op amp output current limit, and the size of the
storage capacitors (both C1 and C2), could create
slewing limitations as the input voltage (VIN) increases.
Current through a capacitor is dependent on the size of
the capacitor and the rate of voltage change. From this
relationship, the rate of voltage change or the slew rate
can be determined. For example, with an op amp short
circuit current of ISC = 25 mA and a load capacitor of
C1 = 0.1 µF, then:
VIN
+
1/2
MCP6002
–
D1
Op Amp A
RISO VC1
+ 1/2
C1
R1
RISO VC2
MCP6002
–
Op Amp B
+
C2
VOUT
MCP6001
–
Op Amp C
Sample
Switch
Clear
Switch
tSAMP
Sample Signal
tCLEAR
Clear Signal
tDETECT
CLK
FIGURE 4-9:
DS20001733K-page 16
Peak Detector with Clear and Sample CMOS Analog Switches.
2019 Microchip Technology Inc.
MCP6001/1R/1U/2/4
5.0
DESIGN AIDS
Microchip provides the basic design tools needed for
the MCP6001/1R/1U/2/4 family of op amps.
5.1
SPICE Macro Model
The latest SPICE macro model for the
MCP6001/1R/1U/2/4 op amps is available on the
Microchip web site at www.microchip.com. The model
was written and tested in official Orcad (Cadence)
owned PSPICE. For the other simulators, it may
require translation.
The model covers a wide aspect of the op amp's
electrical specifications. Not only does the model cover
voltage, current, and resistance of the op amp, but it
also covers the temperature and noise effects on the
behavior of the op amp. The model has not been
verified outside of the specification range listed in the
op amp data sheet. The model behaviors under these
conditions can not be guaranteed that it will match the
actual op amp performance.
Moreover, the model is intended to be an initial design
tool. Bench testing is a very important part of any
design and cannot be replaced with simulations. Also,
simulation results using this macro model need to be
validated by comparing them to the data sheet
specifications and characteristic curves.
5.2
FilterLab® Software
Microchip’s FilterLab® software is an innovative
software tool that simplifies analog active filter (using
op amps) design. Available at no cost from the
Microchip web site at www.microchip.com/filterlab, the
FilterLab design tool provides full schematic diagrams
of the filter circuit with component values. It also
outputs the filter circuit in SPICE format, which can be
used with the macro model to simulate actual filter
performance.
5.3
5.4
Microchip Advanced Part Selector
(MAPS)
MAPS is a software tool that helps semiconductor
professionals efficiently identify Microchip devices that
fit a particular design requirement. Available at no cost
from the Microchip web site at www.microchip.com/
maps, the MAPS is an overall selection tool for
Microchip’s product portfolio that includes Analog,
Memory, MCUs and DSCs. Using this tool you can
define a filter to sort features for a parametric search of
devices and export side-by-side technical comparison
reports. Helpful links are also provided for Data sheets,
Purchase, and Sampling of Microchip parts.
5.5
Analog Demonstration and
Evaluation Boards
Microchip offers a broad spectrum of Analog
Demonstration and Evaluation Boards that are
designed to help you achieve faster time to market. For
a complete listing of these boards and their
corresponding user’s guides and technical information,
visit the Microchip web site at www.microchip.com/analogtools.
Some boards that are especially useful are:
•
•
•
•
•
•
•
MCP6XXX Amplifier Evaluation Board 1
MCP6XXX Amplifier Evaluation Board 2
MCP6XXX Amplifier Evaluation Board 3
MCP6XXX Amplifier Evaluation Board 4
Active Filter Demo Board Kit
5/6-Pin SOT-23 Evaluation Board, P/N VSUPEV2
8-Pin SOIC/MSOP/TSSOP/DIP Evaluation Board,
P/N SOIC8EV
• 14-Pin SOIC/TSSOP/DIP Evaluation Board,
P/N SOIC14EV
Mindi™ Circuit Designer &
Simulator
Microchip’s Mindi™ Circuit Designer & Simulator aids
in the design of various circuits useful for active filter,
amplifier and power-management applications. It is a
free online circuit designer & simulator available from
the Microchip web site at www.microchip.com/mindi.
This interactive circuit designer & simulator enables
designers to quickly generate circuit diagrams,
simulate circuits. Circuits developed using the Mindi
Circuit Designer & Simulator can be downloaded to a
personal computer or workstation.
2019 Microchip Technology Inc.
DS20001733K-page 17
MCP6001/1R/1U/2/4
5.6
Application Notes
The following Microchip Analog Design Note and
Application Notes are available on the Microchip web
site at www.microchip. com/appnotes and are
recommended as supplemental reference resources.
• ADN003: “Select the Right Operational Amplifier
for your Filtering Circuits,” DS21821
• AN722: “Operational Amplifier Topologies and DC
Specifications,” DS00722
• AN723: “Operational Amplifier AC Specifications
and Applications,” DS00723
• AN884: “Driving Capacitive Loads With Op
Amps,” DS00884
• AN990: “Analog Sensor Conditioning Circuits –
An Overview,” DS00990
• AN1177: “Op Amp Precision Design: DC Errors,”
DS01177
• AN1228: “Op Amp Precision Design: Random
Noise,” DS01228
• AN1297: "Microchip 's Op Amp SPICE Macro
Models"
These application notes and others are listed in the
design guide:
• “Signal Chain Design Guide,” DS21825
DS20001733K-page 18
2019 Microchip Technology Inc.
MCP6001/1R/1U/2/4
6.0
PACKAGING INFORMATION
6.1
Package Marking Information
5-Lead SC-70 (MCP6001)
XXN (Front)
YWW (Back)
Example: (I-Temp)
Device
MCP6001
I-Temp
Code
E-Temp
Code
AAN
CDN
AA7 (Front)
432 (Back)
Note: Applies to 5-Lead SC-70.
OR
OR
XXNN
Device
I-Temp
Code
E-Temp
Code
MCP6001
AANN
CDNN
AA74
Note: Applies to 5-Lead SC-70.
Example: (E-Temp)
5-Lead SOT-23 (MCP6001/1R/1U)
5
4
XXNN
1
2
I-Temp
Code
E-Temp
Code
MCP6001
AANN
CDNN
MCP6001R
ADNN
CENN
MCP6001U
AFNN
CFNN
Device
3
5
4
CD25
1
2
3
Note: Applies to 5-Lead SOT-23.
8-Lead PDIP (300 mil)
XXXXXXXX
XXXXXNNN
YYWW
MCP6002
I/P256
0432
8-Lead DFN (2 x 3)
XXX
YWW
NN
OR
MCP6002
e3
I/P^^256
0746
Example:
ABY
944
25
Legend: XX...X
Y
YY
WW
NNN
e3
*
Note:
Example:
Customer-specific information
Year code (last digit of calendar year)
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code
Pb-free JEDEC designator for Matte Tin (Sn)
This package is Pb-free. The Pb-free JEDEC designator ( e3 )
can be found on the outer packaging for this package.
In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
2019 Microchip Technology Inc.
DS20001733K-page 19
MCP6001/1R/1U/2/4
Package Marking Information (Continued)
8-Lead SOIC (150 mil)
Example:
XXXXXXXX
XXXXYYWW
NNN
MCP6002I
SN0432
256
MCP6002I
e3
SN^^0746
256
OR
Example:
8-Lead MSOP
6002I
432256
14-Lead PDIP (300 mil) (MCP6004)
Example:
XXXXXXXXXXXXXX
XXXXXXXXXXXXXX
YYWWNNN
MCP6004
e3
I/P^^
0432256
OR
MCP6004
e3
E/P^^
0746256
14-Lead SOIC (150 mil) (MCP6004)
XXXXXXXXXX
XXXXXXXXXX
YYWWNNN
14-Lead TSSOP (MCP6004)
Example:
OR
0432256
Example:
XXXXXX
YYWW
6004ST
0432
NNN
256
DS20001733K-page 20
MCP6004
e3
E/SL^^
0746256
MCP6004ISL
OR
6004STE
0432
256
2019 Microchip Technology Inc.
MCP6001/1R/1U/2/4
5-Lead Plastic Small Outline Transistor (LT) [SC70]
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
D
A
e
e
3
B
1
E1
E
2X
0.15 C
4
N
5X TIPS
0.30 C
NOTE 1
2X
0.15 C
5X b
0.10
C A B
TOP VIEW
C
c
A2
A
SEATING
PLANE
A1
L
SIDE VIEW
END VIEW
Microchip Technology Drawing C04-061D Sheet 1 of 2
2019 Microchip Technology Inc.
DS20001733K-page 21
MCP6001/1R/1U/2/4
5-Lead Plastic Small Outline Transistor (LT) [SC70]
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Units
Dimension Limits
Number of Pins
N
e
Pitch
Overall Height
A
Standoff
A1
Molded Package Thickness
A2
Overall Length
D
Exposed Pad Length
D2
Overall Width
E
Exposed Pad Width
E1
b
Terminal Width
Terminal Length
L
c
Lead Thickness
MIN
0.80
0.00
0.80
2.50
0.15
0.10
0.08
MILLIMETERS
NOM
5
0.65 BSC
2.00 BSC
2.60
2.10 BSC
1.25 BSC
0.20
-
MAX
1.10
0.10
1.00
2.70
0.40
0.46
0.26
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or
protrusions shall not exceed 0.15mm per side.
3. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
Microchip Technology Drawing C04-061D Sheet 2 of 2
DS20001733K-page 22
2019 Microchip Technology Inc.
MCP6001/1R/1U/2/4
5-Lead Plastic Small Outline Transistor (LT) [SC70]
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
E
Gx
SILK SCREEN
3
2
1
C
G
4
5
Y
X
RECOMMENDED LAND PATTERN
Units
Dimension Limits
Contact Pitch
E
Contact Pad Spacing
C
Contact Pad Width
X
Contact Pad Length
Y
Distance Between Pads
G
Distance Between Pads
Gx
MIN
MILLIMETERS
NOM
0.65 BSC
2.20
MAX
0.45
0.95
1.25
0.20
Notes:
1. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
Microchip Technology Drawing No. C04-2061B
2019 Microchip Technology Inc.
DS20001733K-page 23
MCP6001/1R/1U/2/4
5-Lead Plastic Small Outline Transistor (OT) [SOT23]
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
0.20 C 2X
D
e1
A
D
N
E/2
E1/2
E1
E
(DATUM D)
(DATUM A-B)
0.15 C D
2X
NOTE 1
1
2
e
B
NX b
0.20
C A-B D
TOP VIEW
A
A A2
0.20 C
SEATING PLANE
A
SEE SHEET 2
A1
C
SIDE VIEW
Microchip Technology Drawing C04-091-OT Rev E Sheet 1 of 2
DS20001733K-page 24
2019 Microchip Technology Inc.
MCP6001/1R/1U/2/4
5-Lead Plastic Small Outline Transistor (OT) [SOT23]
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
c
T
L
L1
VIEW A-A
SHEET 1
Units
Dimension Limits
Number of Pins
N
e
Pitch
e1
Outside lead pitch
Overall Height
A
Molded Package Thickness
A2
Standoff
A1
E
Overall Width
E1
Molded Package Width
D
Overall Length
L
Foot Length
Footprint
L1
I
Foot Angle
c
Lead Thickness
b
Lead Width
MIN
0.90
0.89
-
0.30
0°
0.08
0.20
MILLIMETERS
NOM
5
0.95 BSC
1.90 BSC
2.80 BSC
1.60 BSC
2.90 BSC
0.60 REF
-
MAX
1.45
1.30
0.15
0.60
10°
0.26
0.51
Notes:
1. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or
protrusions shall not exceed 0.25mm per side.
2. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
Microchip Technology Drawing C04-091-OT Rev E Sheet 2 of 2
2019 Microchip Technology Inc.
DS20001733K-page 25
MCP6001/1R/1U/2/4
5-Lead Plastic Small Outline Transistor (OT) [SOT23]
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
X
SILK SCREEN
5
Y
Z
C
G
1
2
E
GX
RECOMMENDED LAND PATTERN
Units
Dimension Limits
E
Contact Pitch
C
Contact Pad Spacing
X
Contact Pad Width (X5)
Contact Pad Length (X5)
Y
Distance Between Pads
G
Distance Between Pads
GX
Overall Width
Z
MIN
MILLIMETERS
NOM
0.95 BSC
2.80
MAX
0.60
1.10
1.70
0.35
3.90
Notes:
1. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
Microchip Technology Drawing No. C04-2091B [OT]
DS20001733K-page 26
2019 Microchip Technology Inc.
MCP6001/1R/1U/2/4
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