MCP6021-I/SN

MCP6021/1R/2/3/4 Rail-to-Rail Input/Output, 10 MHz Op Amps Features Description • • • • The MCP6021, MCP6021R, MCP6022, MCP6023 and MCP6024 from Microchip Technology Inc. are rail-torail input and output operational amplifiers with high performance. Key specifications include: wide bandwidth (10 MHz), low noise (8.7 nV/Hz), low input offset voltage and low distortion (0.00053% THD+N). The MCP6023 also offers a Chip Select pin (CS) that gives power savings when the part is not in use. • • • • • • Rail-to-Rail Input/Output Wide Bandwidth: 10 MHz (typical) Low Noise: 8.7 nV/Hz at 10 kHz (typical) Low Offset Voltage: - Industrial Temperature: ±500 µV (max.) - Extended Temperature: ±250 µV (max.) Mid-Supply VREF: MCP6021 and MCP6023 Low Supply Current: 1 mA (typical) Total Harmonic Distortion: - 0.00053% (typical, G = 1 V/V) Unity Gain Stable Power Supply Range: 2.5V to 5.5V Temperature Range: - Industrial: -40°C to +85°C - Extended: -40°C to +125°C The single MCP6021 and MCP6021R are available in SOT-23-5 packages. The single MCP6021, single MCP6023 and dual MCP6022 are available in 8-lead PDIP, SOIC and TSSOP packages. The Extended Temperature single MCP6021 is available in 8-lead MSOP. The quad MCP6024 is offered in 14-lead PDIP, SOIC and TSSOP packages. The MCP6021/1R/2/3/4 family is available in Industrial and Extended temperature ranges. It has a power supply range of 2.5V to 5.5V. Applications • • • • • • Package Types Automotive Multi-Pole Active Filters Audio Processing DAC Buffer Test Equipment Medical Instrumentation MCP6021 SOT-23-5 VOUT 1 VSS 2 VIN+ 3 Design Aids • • • • • • SPICE Macro Models FilterLab® Software MPLAB® Mindi™ Analog Simulator Microchip Advanced Part Selector (MAPS) Analog Demonstration and Evaluation Boards Application Notes Typical Application Photo Detector 5.6 pF 100 k MCP6021 VDD/2 Transimpedance Amplifier  2001-2017 Microchip Technology Inc. 5 VDD VOUTA 1 VINA- 2 4 VIN- VINA+ 3 8 VDD 7 VOUTB VSS 4 5 VINB+ MCP6021R SOT-23-5 VOUT 1 VDD 2 5 VSS VIN+ 3 4 VIN- MCP6021 PDIP, SOIC, MSOP, TSSOP NC 1 VIN- 2 VIN+ 3 VSS 4 100 pF MCP6022 PDIP, SOIC, TSSOP 6 VINB- MCP6023 PDIP, SOIC, TSSOP NC 1 VIN- 2 VIN+ 3 VSS 4 8 CS 7 VDD 6 VOUT 5 VREF MCP6024 PDIP, SOIC, TSSOP 8 NC 7 VDD VOUTA 1 6 VOUT VINA- 2 VINA+ 3 5 V REF VDD 4 VINB+ 5 VINB- 6 VOUTB 7 14 VOUTD 13 VIND12 VIND+ 11 VSS 10 VINC+ 9 VINC8 VOUTC DS20001685E-page 1 MCP6021/1R/2/3/4 NOTES: DS20001685E-page 2  2001-2017 Microchip Technology Inc. MCP6021/1R/2/3/4 1.0 † Notice: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings† VDD – VSS ........................................................................7.0V Current Analog Input Pins (VIN+, VIN-)..........................±2 mA Analog Inputs (VIN+, VIN-) ††......... VSS – 1.0V to VDD + 1.0V All Other Inputs and Outputs.......... VSS – 0.3V to VDD + 0.3V Difference Input Voltage ...................................... |VDD – VSS| Output Short-Circuit Current ................................ Continuous Current at Output and Supply Pins ............................±30 mA Storage Temperature ....................................-65°C to +150°C Maximum Junction Temperature ................................. +150°C ESD Protection on All Pins (HBM; MM)   2 kV; 200V †† See Section 4.1.2, Input Voltage Limits. DC ELECTRICAL CHARACTERISTICS Electrical Specifications: Unless otherwise indicated, TA = +25°C, VDD = +2.5V to +5.5V, VSS = GND, VCM = VDD/2, VOUT  VDD/2 and RL = 10 kto VDD/2. Parameters Sym. Min. Typ. Max. Units Conditions Input Offset Input Offset Voltage: Industrial Temperature Parts VOS -500 — +500 µV VCM = 0V Extended Temperature Parts VOS -250 — +250 µV VCM = 0V, VDD = 5.0V Extended Temperature Parts VOS -2.5 — +2.5 mV VCM = 0V, VDD = 5.0V, TA = -40°C to +125°C VOS/TA — ±3.5 — PSRR 74 90 — Input Offset Voltage Temperature Drift Power Supply Rejection Ratio µV/°C TA = -40°C to +125°C dB VCM = 0V Input Current and Impedance IB — 1 — pA Industrial Temperature Parts IB — 30 150 pA TA = +85°C Extended Temperature Parts IB — 640 5,000 pA TA = +125°C IOS — ±1 — pA Input Bias Current: Input Offset Current Common-Mode Input Impedance ZCM — 1013||6 — ||pF Differential Input Impedance ZDIFF — 1013||3 — ||pF Common-Mode Input Range VCMR VSS – 0.3 — VDD + 0.3 V Common-Mode Rejection Ratio CMRR 74 90 — dB VDD = 5V, VCM = -0.3V to 5.3V CMRR 70 85 — dB VDD = 5V, VCM = 3.0V to 5.3V CMRR 74 90 — dB VDD = 5V, VCM = -0.3V to 3.0V Common-Mode Voltage Reference (MCP6021 and MCP6023 only) VREF Accuracy (VREF – VDD/2) VREF_ACC -50 — +50 VREF Temperature Drift VREF/TA — ±100 — mV AOL 90 110 — dB VOL, VOH VSS + 15 — VDD – 20 mV 0.5V input overdrive ISC — ±30 — mA VDD = 2.5V ISC — ±22 — mA VDD = 5.5V VDD 2.5 — 5.5 V IQ 0.5 1.0 1.35 mA µV/°C TA = -40°C to +125°C Open-Loop Gain DC Open-Loop Gain (Large Signal) VCM = 0V, VOUT = VSS + 0.3V to VDD – 0.3V Output Maximum Output Voltage Swing Output Short Circuit Current Power Supply Supply Voltage Quiescent Current per Amplifier  2001-2017 Microchip Technology Inc. IO = 0 DS20001685E-page 3 MCP6021/1R/2/3/4 AC ELECTRICAL CHARACTERISTICS Electrical Specifications: Unless otherwise indicated, TA = +25°C, VDD = +2.5V to +5.5V, VSS = GND, VCM = VDD/2, VOUT  VDD/2, RL = 10 kto VDD/2 and CL = 60 pF. Parameters Sym. Min. Typ. Max. Units GBWP — 10 — MHz Conditions AC Response Gain Bandwidth Product Phase Margin Settling Time, 0.2% Slew Rate PM — 65 — ° tSETTLE — 250 — ns SR — 7.0 — V/µs G = +1 V/V G = +1 V/V, VOUT = 100 mVp-p Total Harmonic Distortion Plus Noise f = 1 kHz, G = +1 V/V THD + N — 0.00053 — % VOUT = 0.25V to 3.25V (1.75V ± 1.50VPK), VDD = 5.0V, BW = 22 kHz f = 1 kHz, G = +1 V/V, RL = 600 THD + N — 0.00064 — % VOUT = 0.25V to 3.25V (1.75V ± 1.50VPK), VDD = 5.0V, BW = 22 kHz f = 1 kHz, G = +1 V/V THD + N — 0.0014 — % VOUT = 4VP-P, VDD = 5.0V, BW = 22 kHz f = 1 kHz, G = +10 V/V THD + N — 0.0009 — % VOUT = 4VP-P, VDD = 5.0V, BW = 22 kHz f = 1 kHz, G = +100 V/V THD + N — 0.005 — % VOUT = 4VP-P, VDD = 5.0V, BW = 22 kHz Noise Input Noise Voltage Eni — 2.9 — µVp-p Input Noise Voltage Density eni — 8.7 — nV/Hz f = 10 kHz f = 0.1 Hz to 10 Hz Input Noise Current Density ini — 3 — fA/Hz f = 1 kHz MCP6023 CHIP SELECT (CS) ELECTRICAL CHARACTERISTICS Electrical Specifications: Unless otherwise indicated, TA = +25°C, VDD = +2.5V to +5.5V, VSS = GND, VCM = VDD/2, VOUT  VDD/2, RL = 10 kto VDD/2 and CL = 60 pF. Parameters Sym. Min. Typ. Max. CS Logic Threshold, Low VIL CS Input Current, Low ICSL CS Logic Threshold, High CS Input Current, High Units Conditions VSS — 0.2 VDD V -1.0 0.01 — µA VIH 0.8 VDD — VDD V ICSH — 0.01 2.0 µA CS = VDD ISS -2 -0.05 — µA CS = VDD IO(LEAK) — 0.01 — µA CS = VDD CS Low to Amplifier Output Turn-on Time tON — 2 10 µs G = +1, VIN = VSS, CS = 0.2 VDD to VOUT = 0.45 VDD time CS High to Amplifier Output High-Z Time tOFF — 0.01 — µs G = +1, VIN = VSS, CS = 0.8 VDD to VOUT = 0.05 VDD time VHYST — 0.6 — V VDD = 5.0V, internal switch CS Low Specifications CS = VSS CS High Specifications GND Current Amplifier Output Leakage CS Dynamic Specifications Hysteresis DS20001685E-page 4  2001-2017 Microchip Technology Inc. MCP6021/1R/2/3/4 TEMPERATURE CHARACTERISTICS Electrical Specifications: Unless otherwise indicated, VDD = +2.5V to +5.5V and VSS = GND. Parameters Sym. Min. Typ. Max. Units Conditions Temperature Ranges Industrial Temperature Range TA -40 — +85 °C Extended Temperature Range TA -40 — +125 °C Operating Temperature Range TA -40 — +125 °C Storage Temperature Range TA -65 — +150 °C (Note 1) Thermal Package Resistances Thermal Resistance, 5L-SOT-23 JA — 256 — °C/W Thermal Resistance, 8L-PDIP JA — 85 — °C/W Thermal Resistance, 8L-SOIC JA — 163 — °C/W Thermal Resistance, 8L-MSOP JA — 206 — °C/W Thermal Resistance, 8L-TSSOP JA — 124 — °C/W Thermal Resistance, 14L-PDIP JA — 70 — °C/W Thermal Resistance, 14L-SOIC JA — 120 — °C/W Thermal Resistance, 14L-TSSOP JA — 100 — °C/W Note 1: The industrial temperature devices operate over this Extended temperature range, but with reduced performance. In any case, the internal Junction Temperature (TJ) must not exceed the absolute maximum specification of +150°C. 1.1 CS tON VOUT High-Z ISS -50 nA (typical) ICS tOFF Amplifier On -1 mA (typical) High-Z -50 nA (typical) Test Circuits The test circuits used for the DC and AC tests are shown in Figure 1-2 and Figure 1-3. The bypass capacitors are laid out according to the rules discussed in Section 4.7 “Supply Bypass”. VIN RN 1 k: 10 nA (typical) 10 nA (typical) 10 nA (typical) VDD 0.1 µF 1 µF CB1 CB2 VDD/2 RG FIGURE 1-1: Timing Diagram for the CS Pin on the MCP6023. VOUT MCP6021 RF 2 k: CL 60 pF RL 10 k: VL 2 k: FIGURE 1-2: AC and DC Test Circuit for Most Non-Inverting Gain Conditions. VDD/2 RN 1 k: VIN VDD 0.1 µF 1 µF CB1 CB2 VOUT MCP6021 RG RF 2 k: 2 k: CL 60 pF RL 10 k: VL FIGURE 1-3: AC and DC Test Circuit for Most Inverting Gain Conditions.  2001-2017 Microchip Technology Inc. DS20001685E-page 5 MCP6021/1R/2/3/4 NOTES: DS20001685E-page 6  2001-2017 Microchip Technology Inc. MCP6021/1R/2/3/4 2.0 TYPICAL PERFORMANCE CURVES Note: The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore outside the warranted range. Input Offset Voltage (µV) 20 16 20 16 12 8 4 0 -4 FIGURE 2-5: Input Offset Voltage Drift (Extended Temperature Parts). FIGURE 2-3: Input Offset Voltage vs. Common-Mode Input Voltage with VDD = 2.5V. 6.0 5.5 5.0 4.5 3.5 3.0 2.5 2.0 1.5 1.0 4.0 -40°C +25°C +85°C +125°C VDD = 5.5V 0.0 3.0 500 400 300 200 100 0 -100 -200 -300 -400 -500 -0.5 Input Offset Voltage (µV) Input Offset Voltage (µV) -8 Input Offset Voltage Drift (µV/°C) FIGURE 2-2: Input Offset Voltage (Extended Temperature Parts). 500 400 VDD = 2.5V -40°C 300 +25°C 200 +85°C +125°C 100 0 -100 -200 -300 -400 -500 -0.5 0.0 0.5 1.0 1.5 2.0 2.5 Common Mode Input Voltage (V) 438 Samples VCM = 0V TA = -40°C to +125°C -12 -16 24% 22% E-Temp 20% Parts 18% 16% 14% 12% 10% 8% 6% 4% 2% 0% -20 240 200 160 120 80 40 0 -40 -80 -120 -160 -200 -240 Percentage of Occurances 438 Samples VDD = 5.0V VCM = 0V TA = +25°C Percentage of Occurances FIGURE 2-4: Input Offset Voltage Drift (Industrial Temperature Parts). FIGURE 2-1: Input Offset Voltage (Industrial Temperature Parts).  2001-2017 Microchip Technology Inc. 12 Input Offset Voltage Drift (µV/°C) Input Offset Voltage (µV) 24% 22% E-Temp Parts 20% 18% 16% 14% 12% 10% 8% 6% 4% 2% 0% 8 500 400 300 200 100 0 -100 -200 -300 -400 0% 4 2% 0 4% -4 6% -8 8% -12 10% 1192 Samples VCM = 0V TA = -40°C to +85°C I-Temp Parts 0.5 12% 24% 22% 20% 18% 16% 14% 12% 10% 8% 6% 4% 2% 0% -16 1192 Samples VCM = 0V TA = +25°C I-Temp Parts -20 14% Percentage of Occurances 16% -500 Percentage of Occurances Note: Unless otherwise indicated, TA = +25°C, VDD = +2.5V to +5.5V, VSS = GND, VCM = VDD/2, VOUT  VDD/2, RL = 10 k to VDD/2 and CL = 60 pF. Common Mode Input Voltage (V) FIGURE 2-6: Input Offset Voltage vs. Common-Mode Input Voltage with VDD = 5.5V. DS20001685E-page 7 MCP6021/1R/2/3/4 Note: Unless otherwise indicated, TA = +25°C, VDD = +2.5V to +5.5V, VSS = GND, VCM = VDD/2, VOUT  VDD/2, RL = 10 k to VDD/2 and CL = 60 pF. 200 Input Offset Voltage (µV) 50 0 -50 -100 -150 -200 VDD = 5.0V VCM = 0V -250 -300 100 0 -100 -150 125 FIGURE 2-10: Output Voltage. FIGURE 2-8: vs. Frequency. 1.E+05 100k 1.E+06 1M Input Noise Voltage Density 5.5 1.E+04 10k 5.0 1.E+03 4.5 1.E+02 10 100 1k Frequency (Hz) 4.0 1.E+01 1 3.5 1.E+00 3.0 1.E-01 0.1 f = 10 kHz 2.5 1 f = 1 kHz 2.0 10 VDD = 5.0V -0.5 Input Noise Voltage Density (nV/√Hz) 100 24 22 20 18 16 14 12 10 8 6 4 2 0 Input Offset Voltage vs. 1.5 Input Offset Voltage vs. 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 Output Voltage (V) 1.0 100 1,000 Input Noise Voltage Density (nV/√Hz) VDD = 2.5V -50 0.5 -25 0 25 50 75 Ambient Temperature (°C) FIGURE 2-7: Temperature. Common Mode Input Voltage (V) FIGURE 2-11: Input Noise Voltage Density vs. Common-Mode Input Voltage. 110 100 PSRR+ PSRR- 105 PSRR, CMRR (dB) 90 CMRR, PSRR (dB) VDD = 5.5V 50 -200 -50 80 70 60 CMRR 50 40 CMRR 100 95 90 PSRR (VCM = 0V) 85 80 75 30 20 VCM = VDD/2 150 0.0 Input Offset Voltage (µV) 100 1.E+02 100 1.E+03 1k FIGURE 2-9: Frequency. DS20001685E-page 8 1.E+04 10k Frequency (Hz) 1.E+05 100k CMRR, PSRR vs. 1.E+06 1M 70 -50 -25 FIGURE 2-12: Temperature. 0 25 50 75 Ambient Temperature (°C) 100 125 CMRR, PSRR vs.  2001-2017 Microchip Technology Inc. MCP6021/1R/2/3/4 1,000 IB, TA = +125°C IOS, TA = +125°C IB, TA = +85°C 100 10 IOS, TA = +85°C 1 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 Common Mode Input Voltage (V) Quiescent Current (mA/amplifier) FIGURE 2-13: Input Bias, Offset Currents vs. Common-Mode Input Voltage. 1.2 1.1 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0.0 +125°C +85°C +25°C -40°C 10,000 VCM = VDD VDD = 5.5V 1,000 Quiescent Current vs. 1 25 35 45 55 65 75 85 95 105 115 125 Ambient Temperature (°C) FIGURE 2-16: vs. Temperature. 1.2 1.1 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0.0 20 15 10 5 +125°C +85°C +25°C -40°C 0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 Supply Voltage (V) FIGURE 2-15: Output Short-Circuit Current vs. Supply Voltage.  2001-2017 Microchip Technology Inc. Open-Loop Gain (dB) Output ShortCircuit Current (mA) 25 VDD = 2.5V VCM = VDD - 0.5V -25 FIGURE 2-17: Temperature. 120 110 100 90 80 70 60 50 40 30 20 10 0 -10 -20 1.E+00 1 Input Bias, Offset Currents VDD = 5.5V -50 35 30 IOS 10 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 Power Supply Voltage (V) FIGURE 2-14: Supply Voltage. IB 100 0 25 50 75 100 Ambient Temperature (°C) 125 Quiescent Current vs. 0 -15 -30 -45 -60 -75 Phase -90 -105 -120 -135 Gain -150 -165 -180 -195 -210 10 100 1k 10k 100k 1M 10M 100M Frequency (Hz) 1.E+01 FIGURE 2-18: Frequency. 1.E+02 1.E+03 1.E+04 1.E+05 1.E+06 1.E+07 Open-Loop Phase (°) VDD = 5.5V Input Bias, Offset Currents (pA) 10,000 Quiescent Current (mA/amplifier) Input Bias, Offset Currents (pA) Note: Unless otherwise indicated, TA = +25°C, VDD = +2.5V to +5.5V, VSS = GND, VCM = VDD/2, VOUT  VDD/2, RL = 10 k to VDD/2 and CL = 60 pF. 1.E+08 Open-Loop Gain, Phase vs. DS20001685E-page 9 MCP6021/1R/2/3/4 Note: Unless otherwise indicated, TA = +25°C, VDD = +2.5V to +5.5V, VSS = GND, VCM = VDD/2, VOUT  VDD/2, RL = 10 k to VDD/2 and CL = 60 pF. 120 VDD = 2.5V 100 90 1.E+02 1.E+03 100 1.E+04 FIGURE 2-19: Load Resistance. 100k DC Open-Loop Gain vs. VDD = 2.5V 100 95 -25 0 25 50 75 Ambient Temperature (°C) FIGURE 2-22: Temperature. 100 VDD = 5.5V 100 90 VDD = 2.5V 80 0.05 0.10 0.15 0.20 0.25 Output Voltage Headroom (V); VDD - VOH or VOL - VSS 0.30 FIGURE 2-20: Small Signal DC Open-Loop Gain vs. Output Voltage Headroom. 105 GBWP, VDD = 5.5V GBWP, VDD = 2.5V PM, VDD = 2.5V PM, VDD = 5.5V -50 -25 0 25 50 75 100 Ambient Temperature (°C) 125 FIGURE 2-21: Gain Bandwidth Product, Phase Margin vs. Temperature. DS20001685E-page 10 12 Gain Bandwidth Product 60 8 Phase Margin, G = +1 6 45 30 4 2 90 75 10 15 VDD = 5.0V 0 0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 Common Mode Input Voltage (V) FIGURE 2-23: Gain Bandwidth Product, Phase Margin vs. Common-Mode Input Voltage. 14 Phase Margin, G = +1 (°) 100 90 80 70 60 50 40 30 20 10 0 Gain Bandwidth Product (MHz) 110 125 DC Open-Loop Gain vs. 14 VCM = VDD/2 70 0.00 Gain Bandwidth Product (MHz) 105 -50 120 10 9 8 7 6 5 4 3 2 1 0 110 90 1.E+05 1k 10k Load Resistance (Ω Ω) VDD = 5.5V Phase Margin, G = +1 (°) 110 115 12 105 Gain Bandwidth Product 10 75 8 Phase Margin, G = +1 6 60 45 4 2 90 30 VDD = 5.0V VCM = VDD/2 0 15 Phase Margin, G = +1 (°) 120 80 DC Open-Loop Gain (dB) DC Open-Loop Gain (dB) VDD = 5.5V Gain Bandwidth Product (MHz) DC Open-Loop Gain (dB) 130 0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 Output Voltage (V) FIGURE 2-24: Gain Bandwidth Product, Phase Margin vs. Output Voltage.  2001-2017 Microchip Technology Inc. MCP6021/1R/2/3/4 11 10 9 8 7 6 5 4 3 2 1 0 10 Falling, VDD = 5.5V Rising, VDD = 5.5V Maximum Output Voltage Swing (VP-P) Slew Rate (V/µs) Note: Unless otherwise indicated, TA = +25°C, VDD = +2.5V to +5.5V, VSS = GND, VCM = VDD/2, VOUT  VDD/2, RL = 10 k to VDD/2 and CL = 60 pF. Falling, VDD = 2.5V Rising, VDD = 2.5V -50 -25 0 25 50 75 Ambient Temperature (°C) FIGURE 2-25: 100 1.E+05 1.E+06 100k Frequency (Hz) THD+N (%) G = +100 V/V G = +100 V/V G = +10 V/V 0.0100% G = +10 V/V 0.0010% G = +1 V/V f = 20 kHz BWMeas = 80 kHz VDD = 5.0V G = +1 V/V 0.0001% 0.0001% 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 Output Voltage (VP-P) 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 Output Voltage (VP-P) 6 VDD = 5.0V G = +2 V/V VOUT 5 4 VIN 3 2 1 0 -1 10 20 Time 30 (10 40 µs/div) 50 60 70 80 90 100 FIGURE 2-27: The MCP6021/1R/2/3/4 Family Shows No Phase Reversal Under Overdrive.  2001-2017 Microchip Technology Inc. FIGURE 2-29: Total Harmonic Distortion plus Noise vs. Output Voltage with f = 20 kHz. Channel-to-Channel Separation (dB) FIGURE 2-26: Total Harmonic Distortion plus Noise vs. Output Voltage with f = 1 kHz. Input, Output Voltage (V) 10M 0.1000% 0.0010% 0 1.E+07 1M FIGURE 2-28: Maximum Output Voltage Swing vs. Frequency. f = 1 kHz BWMeas = 22 kHz VDD = 5.0V THD+N (%) 1 1.E+04 0.1000% 0.0100% VDD = 2.5V 0.1 10k 125 Slew Rate vs. Temperature. VDD = 5.5V 135 130 125 120 115 110 G = +1 V/V 105 1.E+03 1k 1.E+04 10k Frequency (Hz) 1.E+05 100k 1.E+06 1M FIGURE 2-30: Channel-to-Channel Separation vs. Frequency (MCP6022 and MCP6024 only). DS20001685E-page 11 MCP6021/1R/2/3/4 Note: Unless otherwise indicated, TA = +25°C, VDD = +2.5V to +5.5V, VSS = GND, VCM = VDD/2, VOUT  VDD/2, RL = 10 k to VDD/2 and CL = 60 pF. Output Voltage Headroom VDD – VOH or VOL – VSS (mV) Output Voltage Headroom; VDD – VOH or VOL – VSS (mV) 1,000 100 10 VOL – VSS VDD – VOH 1 0.01 0.1 1 Output Current Magnitude (mA) 10 9 8 7 6 5 4 3 2 1 0 10 FIGURE 2-31: Output Voltage Headroom vs. Output Current. VOL – VSS VDD – VOH -50 -25 0 25 50 75 Ambient Temperature (°C) FIGURE 2-34: vs. Temperature. 100 125 Output Voltage Headroom 6.E-02 6.E-02 G = +1 V/V G = -1 V/V RF = 1 kΩ 5.E-02 Output Voltage (10 mV/div) Output Voltage (10 mV/div) 5.E-02 4.E-02 3.E-02 2.E-02 1.E-02 0.E+00 -1.E-02 -2.E-02 -3.E-02 -4.E-02 4.E-02 3.E-02 2.E-02 1.E-02 0.E+00 -1.E-02 -2.E-02 -3.E-02 -4.E-02 -5.E-02 -5.E-02 -6.E-02 0.E+00 -6.E-02 0.E+00 2.E-07 4.E-07 6.E-07 8.E-07 1.E-06 1.E-06 1.E-06 2.E-06 2.E-06 2.E-07 4.E-07 6.E-07 8.E-07 1.E-06 1.E-06 1.E-06 2.E-06 2.E-06 2.E-06 Time (200 ns/div) 2.E-06 Time (200 ns/div) FIGURE 2-32: Pulse Response. Small Signal Non-Inverting 5.0 G = -1 V/V RF = 1 kΩ 4.5 4.0 Output Voltage (V) Output Voltage (V) Small Signal Inverting Pulse 5.0 G = +1 V/V 4.5 3.5 3.0 2.5 2.0 1.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 1.0 0.5 0.5 0.0 FIGURE 2-35: Response. 0.0 0.E+00 5.E-07 1.E-06 FIGURE 2-33: Pulse Response. DS20001685E-page 12 2.E-06 2.E-06 3.E-06 3.E-06 4.E-06 4.E-06 5.E-06 0.E+00 5.E-07 5.E-06 Time (500 ns/div) Large Signal Non-Inverting FIGURE 2-36: Response. 1.E-06 2.E-06 2.E-06 3.E-06 3.E-06 4.E-06 4.E-06 5.E-06 5.E-06 Time (500 ns/div) Large Signal Inverting Pulse  2001-2017 Microchip Technology Inc. MCP6021/1R/2/3/4 50 40 30 20 10 0 -10 -20 -30 -40 -50 VREF Accuracy; VREF – VDD/2 (mV) VREF Accuracy; VREF – VDD/2 (mV) Note: Unless otherwise indicated, TA = +25°C, VDD = +2.5V to +5.5V, VSS = GND, VCM = VDD/2, VOUT  VDD/2, RL = 10 k to VDD/2 and CL = 60 pF. 50 40 30 20 10 0 -10 -20 -30 -40 -50 1.4 1.2 Quiescent Current (mA/amplifier) Quiescent Current (mA/amplifier) 1.6 Op Amp shuts off here Op Amp turns on here 1.0 CS swept high to low 0.8 Hysteresis 0.6 0.4 CS swept low to high VDD = 2.5V G = +1 V/V VIN = 1.25V 0.2 0.5 1.0 1.5 Chip Select Voltage (V) 2.0 2.5 VOUT 0.0E+00 5.0E-06 Output High-Z 1.0E-05 1.5E-05 2.0E-05 Output on 2.5E-05 3.0E-05 Time (5 µs/div) FIGURE 2-39: Chip Select (CS) to Amplifier Output Response Time (MCP6023 Only).  2001-2017 Microchip Technology Inc. 125 Op Amp turns on here Op Amp shuts off here Hysteresis 1.0 0.8 CS swept high to low 0.6 0.4 CS swept low to high VDD = 5.5V G = +1 V/V VIN = 2.75V 0.0 FIGURE 2-41: Chip Select (CS) Hysteresis (MCP6023 only) with VDD = 5.5V. 10m 1.E-02 1m 1.E-03 100µ 1.E-04 10µ 1.E-05 1µ 1.E-06 100n 1.E-07 10n 1.E-08 +125°C 1n 1.E-09 +85°C 100p 1.E-10 +25°C -40°C 10p 1.E-11 1p 1.E-12 -1.0 -0.9 -0.8 -0.7 -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0.0 Input Voltage (V) Input Current Magnitude (A) Chip Select Voltage, Output Voltage (V) VDD = 5.0V G = +1 V/V VIN = VSS CS Voltage Output on 100 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 Chip Select Voltage (V) FIGURE 2-38: Chip Select (CS) Hysteresis (MCP6023 only) with VDD = 2.5V. 5.5 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 -0.5 -25 0 25 50 75 Ambient Temperature (°C) 1.2 0.2 0.0 0.0 VDD = 2.5V FIGURE 2-40: VREF Accuracy vs. Temperature (MCP6021 and MCP6023 only). 1.6 1.4 VDD = 5.5V -50 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 Power Supply Voltage (V) FIGURE 2-37: VREF Accuracy vs. Supply Voltage (MCP6021 and MCP6023 only). Representative Part 3.5E-05 FIGURE 2-42: Measured Input Current vs. Input Voltage (Below VSS) DS20001685E-page 13 MCP6021/1R/2/3/4 NOTES: DS20001685E-page 14  2001-2017 Microchip Technology Inc. MCP6021/1R/2/3/4 3.0 PIN DESCRIPTIONS Descriptions of the pins are listed in Table 3-1. TABLE 3-1: PIN FUNCTION TABLE MCP6021 MCP6021 MCP6022 MCP6023 MCP6024 PDIP, SOIC, MSOP, TSSOP(1) SOT-23-5 SOT-23-5(2) 6 1 1 1 6 1 2 4 4 2 2 2 VIN-, VINA- 3 3 3 3 3 3 VIN+, VINA+ Non-Inverting Input (Op Amp A) 7 5 2 8 7 4 VDD — — — 5 — 5 VINB+ Non-Inverting Input (Op Amp B) — — — 6 — 6 VINB– Inverting Input (Op Amp B) Analog Output (Op Amp B) Symbol Description VOUT, VOUTA Analog Output (Op Amp A) Inverting Input (Op Amp A) Positive Power Supply — — — 7 — 7 VOUTB — — — — — 8 VOUTC Analog Output (Op Amp C) — — — — — 9 VINC– Inverting Input (Op Amp C) — — — — — 10 VINC+ Non-Inverting Input (Op Amp C) Negative Power Supply 4 2 5 4 4 11 VSS — — — — — 12 VIND+ Non-Inverting Input (Op Amp D) — — — — — 13 VIND– Inverting Input (Op Amp D) — — — — — 14 VOUTD Analog Output (Op Amp D) 5 — — — 5 — VREF — — — — 8 — CS Chip Select 1, 8 — — — 1 — NC No Internal Connection Note 1: 2: 3.1 PDIP, SOIC, PDIP, SOIC, PDIP, SOIC, TSSOP TSSOP TSSOP Reference Voltage The MCP6021 in the 8-pin TSSOP package is only available for I-temp (Industrial Temperature) parts. The MCP6021R is only available in the 5-pin SOT-23 package and for E-temp (Extended Temperature) parts. Analog Outputs 3.4 Chip Select Digital Input (CS) The operational amplifier output pins are low-impedance voltage sources. This is a CMOS, Schmitt triggered input that places the part into a Low-Power mode of operation. 3.2 3.5 Analog Inputs Power Supply (VSS and VDD) The operational amplifier non-inverting and inverting inputs are high-impedance CMOS inputs with low bias currents. The positive power supply pin (VDD) is 2.5V to 5.5V higher than the negative power supply pin (VSS). For normal operation, the other pins are at voltages between VSS and VDD. 3.3 Typically, these parts are used in a single (positive) supply configuration. In this case, VSS is connected to ground and VDD is connected to the supply. VDD will need a bypass capacitor. Reference Voltage (VREF) MCP6021 and MCP6023 Mid-supply reference voltage is provided by the single operational amplifiers (except in the SOT-23-5 package). This is an unbuffered, resistor voltage divider internal to the part.  2001-2017 Microchip Technology Inc. DS20001685E-page 15 MCP6021/1R/2/3/4 NOTES: DS20001685E-page 16  2001-2017 Microchip Technology Inc. MCP6021/1R/2/3/4 4.0 APPLICATIONS INFORMATION The MCP6021/1R/2/3/4 family of operational amplifiers is fabricated on Microchip’s state-of-the-art CMOS process. The amplifiers are unity-gain stable and suitable for a wide range of general purpose applications. 4.1 D1 U1 D2 V1 MCP602X Rail-to-Rail Input 4.1.1 VDD VOUT V2 PHASE REVERSAL The MCP6021/1R/2/3/4 operational amplifiers are designed to prevent phase reversal when the input pins exceed the supply voltages. Figure 2-42 shows the input voltage exceeding the supply voltage without any phase reversal. 4.1.2 INPUT VOLTAGE LIMITS In order to prevent damage and/or improper operation of these amplifiers, the circuit must limit the voltages at the input pins. See the Absolute Maximum Ratings† section. The ESD protection on the inputs can be depicted as shown in Figure 4-1. This structure was chosen to protect the input transistors and to minimize Input Bias (IB) current. FIGURE 4-2: 4.1.3 INPUT CURRENT LIMITS In order to prevent damage and/or improper operation of these amplifiers, the circuit must limit the voltages at the input pins. See the Absolute Maximum Ratings† section. Figure 4-3 shows one approach to protecting these inputs. The resistors, R1 and R2, limit the possible currents in or out of the input pins (and the ESD diodes, D1 and D2). The diode currents will go through either VDD or VSS. VDD D1 VDD Protecting the Analog Inputs. D2 U1 V1 Bond Pad R1 MCP602X VOUT V2 R2 VIN+ VSS Bond Pad Input Stage Bond Pad VIN Bond Pad FIGURE 4-1: Structures. VSS – min (V1,V2) 2 mA max(V1,V2) – VDD min(R1,R2) > 2 mA min(R1,R2) > FIGURE 4-3: Simplified Analog Input ESD The input ESD diodes clamp the inputs when they try to go more than one diode drop below VSS. They also clamp any voltages that go well above VDD. Their breakdown voltage is high enough to allow normal operation, but not low enough to protect against slow overvoltage (beyond VDD) events. Very fast ESD events (that meet the specifications) are limited so that damage does not occur. In some applications, it may be necessary to prevent excessive voltages from reaching the operational amplifier inputs. Figure 4-2 shows one approach to protecting these inputs. A significant amount of current can flow out of the inputs when the Common-Mode Voltage (VCM) is below ground (VSS). See Figure 2-42.  2001-2017 Microchip Technology Inc. 4.1.4 Protecting the Analog Inputs. NORMAL OPERATION The input stage of the MCP6021/1R/2/3/4 operational amplifiers uses two differential CMOS input stages in parallel. One operates at a low Common-Mode Voltage (VCM) input, while the other operates at high VCM. With this topology, the device operates with VCM up to 0.3V above VDD and 0.3V below VSS. 4.2 Rail-to-Rail Output The maximum output voltage swing is the maximum swing possible under a particular output load. According to the specification table, the output can reach within 20 mV of either supply rail when RL = 10 k. See Figure 2-31 and Figure 2-34 for more information concerning typical performance. DS20001685E-page 17 MCP6021/1R/2/3/4 4.3 Capacitive Loads 4.4 Driving large capacitive loads can cause stability problems for voltage feedback operational amplifiers. As the load capacitance increases, the feedback loop’s phase margin decreases and the closed loop bandwidth is reduced. This produces gain peaking in the frequency response, with overshoot and ringing in the step response. When driving large capacitive loads with these operational amplifiers (e.g., > 60 pF when G = +1), a small series resistor at the output (RISO in Figure 4-4) improves the feedback loop’s phase margin (stability) by making the load resistive at higher frequencies. The bandwidth will be generally lower than the bandwidth with no capacitive load. VIN Figure 2-35 and Figure 2-36 use RF = 1 k to avoid (frequency response) gain peaking and (step response) overshoot. The capacitance to ground at the inverting input (CG) is the op amp’s Common-mode input capacitance plus board parasitic capacitance. CG is in parallel with RG, which causes an increase in gain at high frequencies for non-inverting gains greater than 1 V/V (unity gain). CG also reduces the phase margin of the feedback loop for both non-inverting and inverting gains. VIN VOUT CG RISO MCP602X RF RG VOUT CL FIGURE 4-4: Output Resistor, RISO, Stabilizes Large Capacitive Loads. FIGURE 4-6: Non-Inverting Gain Circuit with Parasitic Capacitance. The largest value of RF in Figure 4-6 that should be used is a function of noise gain (see GN in Section 4.3 “Capacitive Loads”) and CG. Figure 4-7 shows results for various conditions. Other compensation techniques may be used, but they tend to be more complicated to design. 1.E+05 100k GN > +1 V/V Maximum RF (W) Figure 4-5 gives recommended RISO values for different capacitive loads and gains. The x-axis is the normalized load capacitance (CL/GN), where GN is the circuit’s noise gain. For non-inverting gains, GN and the Signal Gain are equal. For inverting gains, GN is 1+|Signal Gain| (e.g., -1 V/V gives GN = +2 V/V). 1,000 Recommended RISO (Ω) Gain Peaking CG = 7 pF CG = 20 pF 1.E+04 10k GN ≥ +1 1.E+03 1k CG = 50 pF CG = 100 pF 100 1.E+02 100 1 10 Noise Gain; GN (V/V) 10 10 100 1,000 Normalized Capacitance; CL/GN (pF) 10,000 FIGURE 4-5: Recommended RISO Values for Capacitive Loads. After selecting RISO for your circuit, double-check the resulting frequency response peaking and step response overshoot. Modify RISO’s value until the response is reasonable. Evaluation on the bench and simulations with the MCP6021/1R/2/3/4 Spice macro model are helpful. DS20001685E-page 18 FIGURE 4-7: Non-Inverting Gain Circuit with Parasitic Capacitance. 4.5 MCP6023 Chip Select (CS) The MCP6023 is a single amplifier with Chip Select (CS). When CS is pulled high, the supply current drops to 10 nA (typical) and flows through the CS pin to VSS. When this happens, the amplifier output is put into a high-impedance state. By pulling CS low, the amplifier is enabled. The CS pin has an internal 5 MΩ (typical) pull-down resistor connected to VSS, so it will go low if the CS pin is left floating. Figure 1-1 and Figure 2-39 show the output voltage and supply current response to a CS pulse.  2001-2017 Microchip Technology Inc. MCP6021/1R/2/3/4 4.6 MCP6021 and MCP6023 Reference Voltage The single operational amplifiers (MCP6021 and MCP6023), not in the SOT-23-5 package, have an internal mid-supply reference voltage connected to the VREF pin (see Figure 4-8). The MCP6021 has CS internally tied to VSS, which always keeps the operational amplifier on and always provides a mid-supply reference. With the MCP6023, taking the CS pin high conserves power by shutting down both the operational amplifier and the VREF circuitry. Taking the CS pin low turns on the operational amplifier and VREF circuitry. VDD RG VREF 50 k CS 5 M VREF CB FIGURE 4-10: Inverting Gain Circuit Using VREF (MCP6021 and MCP6023 only). 4.7 Supply Bypass With this family of operational amplifiers, the power supply pin (VDD for single supply) should have a local bypass capacitor (i.e., 0.01 µF to 0.1 µF) within 2 mm for good, high-frequency performance. It also needs a bulk capacitor (i.e., 1 µF or larger) within 100 mm to provide large, slow currents. This bulk capacitor can be shared with nearby analog parts. 4.8 VSS (CS tied internally to VSS for MCP6021) FIGURE 4-8: Simplified Internal VREF Circuit (MCP6021 and MCP6023 only). See Figure 4-9 for a non-inverting gain circuit using the internal mid-supply reference. The DC Blocking Capacitor (CB) also reduces noise by coupling the operational amplifier input to the source. CB VIN VOUT If you don’t need the mid-supply reference, leave the VREF pin open. 50 k RG RF VIN Unused Operational Amplifiers An unused operational amplifier in a quad package (MCP6024) should be configured as shown in Figure 4-11. These circuits prevent the output from toggling and causing crosstalk. Circuit A sets the operational amplifier at its minimum noise gain. The resistor divider produces any desired reference voltage within the output voltage range of the operational amplifier. The operational amplifier buffers that reference voltage. Circuit B uses the minimum number of components and operates as a comparator, but it may draw more current. ¼ MCP6024 (A) RF VDD VOUT R1 VDD VDD VREF FIGURE 4-9: Non-Inverting Gain Circuit Using VREF (MCP6021 and MCP6023 only). To use the internal mid-supply reference for an inverting gain circuit, connect the VREF pin to the non-inverting input, as shown in Figure 4-10. The capacitor, CB, helps reduce power supply noise on the output.  2001-2017 Microchip Technology Inc. ¼ MCP6024 (B) VREF R2 R2 V REF = V DD + -------------------R1 + R2 FIGURE 4-11: Amplifiers. Unused Operational DS20001685E-page 19 MCP6021/1R/2/3/4 4.9 PCB Surface Leakage In applications where low input bias current is critical, PCB (Printed Circuit Board) surface leakage effects need to be considered. Surface leakage is caused by humidity, dust or other contamination on the board. Under low humidity conditions, a typical resistance between nearby traces is 1012. A 5V difference would cause 5 pA of current to flow, which is greater than the MCP6021/1R/2/3/4 family’s bias current at +25°C (1 pA, typical). The easiest way to reduce surface leakage is to use a guard ring around sensitive pins (or traces). The guard ring is biased at the same voltage as the sensitive pin. Figure 4-12 shows an example of this type of layout. Guard Ring VIN- VIN+ Use a solid ground plane and connect the bypass local capacitor(s) to this plane with minimal length traces. This cuts down inductive and capacitive crosstalk. Separate digital from analog, low speed from high speed and low power from high power. This will reduce interference. Keep sensitive traces short and straight. Separate them from interfering components and traces. This is especially important for high-frequency (low rise time) signals. Sometimes it helps to place guard traces next to victim traces. They should be on both sides of the victim trace and as close as possible. Connect the guard trace to the ground plane at both ends and in the middle for long traces. Use coax cables (or low-inductance wiring) to route signal and power to and from the PCB. 4.11 Typical Applications 4.11.1 FIGURE 4-12: 1. 2. Example Guard Ring Layout. Non-Inverting Gain and Unity Gain Buffer. a) Connect the guard ring to the inverting input pin (VIN-); this biases the guard ring to the Common-mode input voltage. b) Connect the non-inverting pin (VIN+) to the input with a wire that does not touch the PCB surface. Inverting (Figure 4-12) and Transimpedance Gain Amplifiers (convert current to voltage, such as photo detectors). a) Connect the guard ring to the non-inverting input pin (VIN+). This biases the guard ring to the same reference voltage as the operational amplifier’s input (e.g., VDD/2 or ground). b) Connect the inverting pin (VIN-) to the input with a wire that does not touch the PCB surface. 4.10 High-Speed PCB Layout A/D CONVERTER DRIVER AND ANTI-ALIASING FILTER Figure 4-13 shows a third-order Butterworth filter that can be used as an A/D Converter driver. It has a bandwidth of 20 kHz and a reasonable step response. It will work well for conversion rates of 80 ksps and greater (it has 29 dB attenuation at 60 kHz). 1.0 nF 8.45 k 14.7 k 33.2 k 1.2 nF 100 pF MCP602X FIGURE 4-13: A/D Converter Driver and Anti-Aliasing Filter with a 20 kHz Cutoff Frequency. This filter can easily be adjusted to another bandwidth by multiplying all capacitors by the same factor. Alternatively, the resistors can all be scaled by another common factor to adjust the bandwidth. Due to their speed capabilities, a little extra care in the PCB (Printed Circuit Board) layout can make a significant difference in the performance of these operational amplifiers. Good PC board layout techniques will help you achieve the performance shown in Section 1.0 “Electrical Characteristics” and Section 2.0 “Typical Performance Curves”, while also helping you minimize EMC (Electro-Magnetic Compatibility) issues. DS20001685E-page 20  2001-2017 Microchip Technology Inc. MCP6021/1R/2/3/4 4.11.2 OPTICAL DETECTOR AMPLIFIER Figure 4-14 shows the MCP6021 operational amplifier used as a transimpedance amplifier in a photo detector circuit. The photo detector looks like a capacitive current source, so the 100 k resistor gains the input signal to a reasonable level. The 5.6 pF capacitor stabilizes this circuit and produces a flat frequency response with a bandwidth of 370 kHz. Photo Detector 5.6 pF 100 k 100 pF MCP6021 VDD/2 FIGURE 4-14: Transimpedance Amplifier for an Optical Detector.  2001-2017 Microchip Technology Inc. DS20001685E-page 21 MCP6021/1R/2/3/4 NOTES: DS20001685E-page 22  2001-2017 Microchip Technology Inc. MCP6021/1R/2/3/4 5.0 DESIGN AIDS Microchip provides the basic design tools needed for the MCP6021/1R/2/3/4 family of operational amplifiers. 5.1 SPICE Macro Model The latest SPICE macro model available for the MCP6021/1R/2/3/4 operational amplifiers is on Microchip’s web site at www.microchip.com. This model is intended as an initial design tool that works well in the operational amplifier’s linear region of operation at room temperature. There is information on its capabilities within the macro model file. Bench testing is a very important part of any design and cannot be replaced with simulations. Also, simulation results using this macro model need to be validated by comparing them to the data sheet specifications and characteristic curves. 5.2 FilterLab® Software Microchip’s FilterLab® software is an innovative software tool that simplifies analog active filter (using operational amplifiers) design. Available at no cost from the Microchip web site at www.microchip.com/filterlab, the FilterLab design tool provides full schematic diagrams of the filter circuit with component values. It also outputs the filter circuit in SPICE format, which can be used with the macro model to simulate actual filter performance. 5.3 MPLAB® Mindi™ Analog Simulator Microchip’s Mindi™ circuit designer and simulator aids in the design of various circuits useful for active filter, amplifier and power management applications. It is a free online circuit designer and simulator available from the Microchip web site at www.microchip.com/mindi. This interactive circuit designer and simulator enables designers to quickly generate circuit diagrams and simulate circuits. Circuits developed using the MPLAB Mindi analog simulator can be downloaded to a personal computer or workstation. 5.4 Microchip Advanced Part Selector (MAPS) 5.5 Analog Demonstration and Evaluation Boards Microchip offers a broad spectrum of analog demonstration and evaluation boards that are designed to help you achieve faster time to market. For a complete listing of these boards, and their corresponding user’s guides and technical information, visit the Microchip web site at www.microchip.com/analogtools. Some boards that are especially useful are: • • • • • • MCP6XXX Amplifier Evaluation Board 1 MCP6XXX Amplifier Evaluation Board 2 MCP6XXX Amplifier Evaluation Board 3 MCP6XXX Amplifier Evaluation Board 4 Active Filter Demo Board Kit 8-Pin SOIC/MSOP/TSSOP/DIP Evaluation Board, P/N: SOIC8EV • 14-Pin SOIC/TSSOP/DIP Evaluation Board, P/N: SOIC14EV 5.6 Application Notes The following Microchip Application Notes are available on the Microchip web site at www.microchip. com/appnotes and are recommended as supplemental reference resources. • ADN003, “Select the Right Operational Amplifier for your Filtering Circuits” (DS21821) • AN722, “Operational Amplifier Topologies and DC Specifications” (DS00722) • AN723, “Operational Amplifier AC Specifications and Applications” (DS00723) • AN884, “Driving Capacitive Loads With Op Amps” (DS00884) • AN990, “Analog Sensor Conditioning Circuits – An Overview” (DS00990) • AN1177, “Op Amp Precision Design: DC Errors” (DS01177) • AN1228, “Op Amp Precision Design: Random Noise” (DS01228) These application notes and others are listed in the design guide: “Signal Chain Design Guide” (DS21825). MAPS is a software tool that helps semiconductor professionals efficiently identify Microchip devices that fit a particular design requirement. Available at no cost from the Microchip web site at www.microchip.com/maps, the MAPS is an overall selection tool for Microchip’s product portfolio, that includes analog, memory, MCUs and DSCs. Using this tool you can define a filter to sort features for a parametric search of devices and export side-by-side technical comparison reports. Helpful links are also provided for data sheets, purchasing and sampling of Microchip parts.  2001-2017 Microchip Technology Inc. DS20001685E-page 23 MCP6021/1R/2/3/4 NOTES: DS20001685E-page 24  2001-2017 Microchip Technology Inc. MCP6021/1R/2/3/4 6.0 PACKAGING INFORMATION 6.1 Package Marking Information 5-Lead SOT-23 (MCP6021/MCP6021R) Example: Device MCP6021 EYNN MCP6021R EZNN Note: 8-Lead PDIP (300 mil) E-Temp Code Applies to 5-Lead SOT-23. Example: MCP6021 I/P256 1603 8-Lead SOIC (150 mil) e3 * Note: OR MCP6021 E/P e3 256 1603 Example: MCP6021 I/SN1603 256 Legend: XX...X Y YY WW NNN EY25 OR MCP6021E SN e3 1603 256 Customer-specific information Year code (last digit of calendar year) Year code (last 2 digits of calendar year) Week code (week of January 1 is week ‘01’) Alphanumeric traceability code Pb-free JEDEC® designator for Matte Tin (Sn) This package is Pb-free. The Pb-free JEDEC designator ( e3 ) can be found on the outer packaging for this package. In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information.  2001-2017 Microchip Technology Inc. DS20001685E-page 25 MCP6021/1R/2/3/4 Package Marking Information (Continued) 8-Lead MSOP Example: 6021E 903256 8-Lead TSSOP Example: 6021 E903 256 14-Lead PDIP (300 mil) (MCP6024) Example: MCP6024-I/P 0903256 OR MCP6024-E/P e3 0903256 DS20001685E-page 26  2001-2017 Microchip Technology Inc. MCP6021/1R/2/3/4 Package Marking Information (Continued) 14-Lead SOIC (150 mil) (MCP6024) Example: MCP6024-I/SL 1603256 OR MCP6024 E/SL e3 1603256 14-Lead TSSOP (MCP6024) Example: 6024E 1603 256  2001-2017 Microchip Technology Inc. DS20001685E-page 27 MCP6021/1R/2/3/4 5-Lead Plastic Small Outline Transistor (OT) [SOT23] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging 0.20 C 2X D e1 A D N E/2 E1/2 E1 E (DATUM D) (DATUM A-B) 0.15 C D 2X NOTE 1 1 2 e B NX b 0.20 C A-B D TOP VIEW A A A2 0.20 C SEATING PLANE A SEE SHEET 2 C A1 SIDE VIEW Microchip Technology Drawing C04-028D [OT] Sheet 1 of DS20001685E-page 28  2001-2017 Microchip Technology Inc. MCP6021/1R/2/3/4 5-Lead Plastic Small Outline Transistor (OT) [SOT23] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging c T L L1 VIEW A-A SHEET 1 Units Dimension Limits Number of Pins N e Pitch e1 Outside lead pitch Overall Height A Molded Package Thickness A2 Standoff A1 E Overall Width E1 Molded Package Width D Overall Length L Foot Length Footprint L1 I Foot Angle c Lead Thickness b Lead Width MIN 0.90 0.89 - 0.30 0° 0.08 0.20 MILLIMETERS NOM 6 0.95 BSC 1.90 BSC 2.80 BSC 1.60 BSC 2.90 BSC 0.60 REF - MAX 1.45 1.30 0.15 0.60 10° 0.26 0.51 Notes: 1. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.25mm per side. 2. Dimensioning and tolerancing per ASME Y14.5M BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only. Microchip Technology Drawing C04-091D [OT] Sheet 2 of  2001-2017 Microchip Technology Inc. DS20001685E-page 29 MCP6021/1R/2/3/4 5-Lead Plastic Small Outline Transistor (OT) [SOT23] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging X SILK SCREEN 5 Y Z C G 1 2 E GX RECOMMENDED LAND PATTERN Units Dimension Limits E Contact Pitch C Contact Pad Spacing X Contact Pad Width (X5) Contact Pad Length (X5) Y Distance Between Pads G Distance Between Pads GX Overall Width Z MIN MILLIMETERS NOM 0.95 BSC 2.80 MAX 0.60 1.10 1.70 0.35 3.90 Notes: 1. Dimensioning and tolerancing per ASME Y14.5M BSC: Basic Dimension. Theoretically exact value shown without tolerances. Microchip Technology Drawing No. C04-2091A [OT] DS20001685E-page 30  2001-2017 Microchip Technology Inc. MCP6021/1R/2/3/4 8-Lead Plastic Dual In-Line (P) - 300 mil Body [PDIP] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging D A N B E1 NOTE 1 1 2 TOP VIEW E C A2 A PLANE L c A1 e eB 8X b1 8X b .010 C SIDE VIEW END VIEW Microchip Technology Drawing No. C04-018D Sheet 1 of 2  2001-2017 Microchip Technology Inc. DS20001685E-page 31 MCP6021/1R/2/3/4 8-Lead Plastic Dual In-Line (P) - 300 mil Body [PDIP] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging ALTERNATE LEAD DESIGN (VENDOR DEPENDENT) DATUM A DATUM A b b e 2 e 2 e Units Dimension Limits Number of Pins N e Pitch Top to Seating Plane A Molded Package Thickness A2 Base to Seating Plane A1 Shoulder to Shoulder Width E Molded Package Width E1 Overall Length D Tip to Seating Plane L c Lead Thickness Upper Lead Width b1 b Lower Lead Width Overall Row Spacing eB § e MIN .115 .015 .290 .240 .348 .115 .008 .040 .014 - INCHES NOM 8 .100 BSC .130 .310 .250 .365 .130 .010 .060 .018 - MAX .210 .195 .325 .280 .400 .150 .015 .070 .022 .430 Notes: 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. § Significant Characteristic 3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" per side. 4. Dimensioning and tolerancing per ASME Y14.5M BSC: Basic Dimension. Theoretically exact value shown without tolerances. Microchip Technology Drawing No. C04-018D Sheet 2 of 2 DS20001685E-page 32  2001-2017 Microchip Technology Inc. MCP6021/1R/2/3/4 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2001-2017 Microchip Technology Inc. DS20001685E-page 33 MCP6021/1R/2/3/4 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS20001685E-page 34  2001-2017 Microchip Technology Inc. MCP6021/1R/2/3/4      !"#$% &  ! "# $% &"'"" ($)  % *++&&&!  !+$  2001-2017 Microchip Technology Inc. DS20001685E-page 35 MCP6021/1R/2/3/4 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS20001685E-page 36  2001-2017 Microchip Technology Inc. MCP6021/1R/2/3/4 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2001-2017 Microchip Technology Inc. DS20001685E-page 37 MCP6021/1R/2/3/4 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS20001685E-page 38  2001-2017 Microchip Technology Inc. MCP6021/1R/2/3/4   '( ( )  '** !"' % &  ! "# $% &"'"" ($)  % *++&&&!  !+$ D N E E1 NOTE 1 1 2 b e c A φ A2 A1 L L1 @" !" A!" E#!7  )(" AA8 8 E E EG H  (  G3 K  L J;>? L  %%($ $""   1 1; % )) 1 ; L 1; 1 G3 N% 8  %%($N% 81 ?   %%($A