MCP601/1R/2/3/4
2.7V to 6.0V Single Supply CMOS Op Amps
Features
Description
•
•
•
•
•
•
•
•
Single-Supply: 2.7V to 6.0V
Rail-to-Rail Output
Input Range Includes Ground
Gain Bandwidth Product: 2.8 MHz (typical)
Unity-Gain Stable
Low Quiescent Current: 230 µA/amplifier (typical)
Chip Select (CS): MCP603 only
Temperature Ranges:
- Industrial: -40°C to +85°C
- Extended: -40°C to +125°C
• Available in Single, Dual, and Quad
The Microchip Technology Inc. MCP601/1R/2/3/4
family of low-power operational amplifiers (op amps)
are offered in single (MCP601), single with Chip Select
(CS) (MCP603), dual (MCP602), and quad (MCP604)
configurations. These op amps utilize an advanced
CMOS technology that provides low bias current, highspeed operation, high open-loop gain, and rail-to-rail
output swing. This product offering operates with a
single supply voltage that can be as low as 2.7V, while
drawing 230 µA (typical) of quiescent current per
amplifier. In addition, the common mode input voltage
range goes 0.3V below ground, making these
amplifiers ideal for single-supply operation.
Typical Applications
These devices are appropriate for low power, battery
operated circuits due to the low quiescent current, for
A/D convert driver amplifiers because of their wide
bandwidth or for anti-aliasing filters by virtue of their low
input bias current.
•
•
•
•
•
•
•
Portable Equipment
A/D Converter Driver
Photo Diode Pre-amp
Analog Filters
Data Acquisition
Notebooks and PDAs
Sensor Interface
The MCP601, MCP602, and MCP603 are available in
standard 8-lead PDIP, SOIC, and TSSOP packages.
The MCP601 and MCP601R are also available in a
standard 5-lead SOT-23 package, while the MCP603 is
available in a standard 6-lead SOT-23 package. The
MCP604 is offered in standard 14-lead PDIP, SOIC,
and TSSOP packages.
Available Tools
•
•
•
•
•
•
The MCP601/1R/2/3/4 family is available in the
Industrial and Extended temperature ranges and has a
power supply range of 2.7V to 6.0V.
SPICE Macro Models
FilterLab® Software
Mindi™ Simulation Tool
MAPS (Microchip Advanced Part Selector)
Analog Demonstration and Evaluation Boards
Application Notes
Package Types
MCP601
PDIP, SOIC, TSSOP
MCP602
PDIP, SOIC, TSSOP
MCP603
PDIP, SOIC, TSSOP
MCP604
PDIP, SOIC, TSSOP
NC 1
8 NC
VOUTA 1
8 VDD
NC 1
8 CS
VOUTA 1
14 VOUTD
VIN– 2
7 VDD
VINA– 2
7 VOUTB
VIN– 2
7 VDD
13 VIND–
6 VOUT
VINA+ 3
VSS 4
6 VINB–
VIN+ 3
VSS 4
6 VOUT
VINA– 2
VINA+ 3
VIN+ 3
VSS 4
5 NC
MCP601
SOT23-5
VOUT 1
MCP601R
SOT23-5
5 VDD
VOUT 1
4 VIN–
VIN+ 3
VSS 2
VIN+ 3
5 VINB+
5 VSS
VOUT 1
4 VIN–
VIN+ 3
VSS 2
VDD 4
6 VDD
12 VIND+
11 VSS
VINB– 6
10 VINC+
9 VINC–
VOUTB 7
8 VOUTC
VINB+ 5
MCP603
SOT23-6
VDD 2
© 2007 Microchip Technology Inc.
5 NC
5 CS
4 VIN–
DS21314G-page 1
MCP601/1R/2/3/4
1.0
ELECTRICAL
CHARACTERISTICS
VDD – VSS ........................................................................7.0V
† Notice: Stresses above those listed under “Absolute
Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of
the device at those or any other conditions above those
indicated in the operational listings of this specification is not
implied. Exposure to maximum rating conditions for extended
periods may affect device reliability.
Current at Input Pins .....................................................±2 mA
†† See Section 4.1.2 “Input Voltage and Current Limits”.
Absolute Maximum Ratings †
Analog Inputs (VIN+, VIN–) †† ........ VSS – 1.0V to VDD + 1.0V
All Other Inputs and Outputs ......... VSS – 0.3V to VDD + 0.3V
Difference Input Voltage ...................................... |VDD – VSS|
Output Short Circuit Current .................................Continuous
Current at Output and Supply Pins ............................±30 mA
Storage Temperature....................................–65°C to +150°C
Maximum Junction Temperature (TJ) ......................... .+150°C
ESD Protection On All Pins (HBM; MM) .............. ≥ 3 kV; 200V
DC CHARACTERISTICS
Electrical Specifications: Unless otherwise specified, TA = +25°C, VDD = +2.7V to +5.5V, VSS = GND, VCM = VDD/2,
VOUT ≈ VDD/2, VL = VDD/2, and RL = 100 kΩ to VL, and CS is tied low. (Refer to Figure 1-2 and Figure 1-3).
Parameters
Input Offset
Input Offset Voltage
Industrial Temperature
Extended Temperature
Input Offset Temperature Drift
Power Supply Rejection
Input Current and Impedance
Input Bias Current
Industrial Temperature
Extended Temperature
Input Offset Current
Common Mode Input Impedance
Differential Input Impedance
Common Mode
Common Mode Input Range
Common Mode Rejection Ratio
Open-loop Gain
DC Open-loop Gain (large signal)
Output
Maximum Output Voltage Swing
Linear Output Voltage Swing
Output Short Circuit Current
Sym
Min
Typ
Max
Units
VOS
VOS
VOS
ΔVOS/ΔTA
PSRR
-2
-3
-4.5
—
80
±0.7
±1
±1
±2.5
88
+2
+3
+4.5
—
—
mV
mV
mV
µV/°C
dB
IB
IB
IB
IOS
ZCM
—
—
—
—
—
1
20
450
±1
1013||6
—
60
5000
—
—
pA
pA TA = +85°C (Note 1)
pA TA = +125°C (Note 1)
pA
Ω||pF
ZDIFF
—
1013||3
—
Ω||pF
VCMR
CMRR
VSS – 0.3
75
—
90
VDD – 1.2
—
V
dB
AOL
100
115
—
dB
AOL
95
110
—
dB
—
—
—
—
±22
±12
VDD – 20
VDD – 60
VDD – 100
VDD – 100
—
—
mV
mV
mV
mV
mA
mA
VOL, VOH VSS + 15
VOL, VOH VSS + 45
VSS + 100
VOUT
VOUT
VSS + 100
ISC
—
—
ISC
Conditions
TA = -40°C to +85°C (Note 1)
TA = -40°C to +125°C (Note 1)
TA = -40°C to +125°C
VDD = 2.7V to 5.5V
VDD = 5.0V, VCM = -0.3V to 3.8V
RL = 25 kΩ to VL,
VOUT = 0.1V to VDD – 0.1V
RL = 5 kΩ to VL,
VOUT = 0.1V to VDD – 0.1V
RL = 25 kΩ to VL, Output overdrive = 0.5V
RL = 5 kΩ to VL, Output overdrive = 0.5V
RL = 25 kΩ to VL, AOL ≥ 100 dB
RL = 5 kΩ to VL, AOL ≥ 95 dB
VDD = 5.5V
VDD = 2.7V
Power Supply
Supply Voltage
VDD
2.7
—
6.0
V
(Note 2)
—
230
325
µA IO = 0
Quiescent Current per Amplifier
IQ
Note 1: These specifications are not tested in either the SOT-23 or TSSOP packages with date codes older than YYWW = 0408.
In these cases, the minimum and maximum values are by design and characterization only.
2: All parts with date codes November 2007 and later have been screened to ensure operation at VDD=6.0V. However, the
other minimum and maximum specifications are measured at 1.4V and/or 5.5V.
DS21314G-page 2
© 2007 Microchip Technology Inc.
MCP601/1R/2/3/4
AC CHARACTERISTICS
Electrical Specifications: Unless otherwise indicated, TA = +25°C, VDD = +2.7V to +5.5V, VSS = GND, VCM = VDD/2,
VOUT ≈ VDD/2, VL = VDD/2, and RL = 100 kΩ to VL, CL = 50 pF, and CS is tied low. (Refer to Figure 1-2 and Figure 1-3).
Parameters
Sym
Min
Typ
Max
Units
GBWP
—
2.8
—
MHz
PM
—
50
—
°
Conditions
Frequency Response
Gain Bandwidth Product
Phase Margin
G = +1 V/V
Step Response
Slew Rate
SR
—
2.3
—
V/µs
tsettle
—
4.5
—
µs
Input Noise Voltage
Eni
—
7
—
µVP-P
Input Noise Voltage Density
eni
—
29
—
nV/√Hz f = 1 kHz
eni
—
21
—
nV/√Hz f = 10 kHz
ini
—
0.6
—
fA/√Hz f = 1 kHz
Settling Time (0.01%)
G = +1 V/V
G = +1 V/V, 3.8V step
Noise
Input Noise Current Density
f = 0.1 Hz to 10 Hz
MCP603 CHIP SELECT (CS) CHARACTERISTICS
Electrical Specifications: Unless otherwise indicated, TA = +25°C, VDD = +2.7V to +5.5V, VSS = GND, VCM = VDD/2,
VOUT ≈ VDD/2, VL = VDD/2, and RL = 100 kΩ to VL, CL = 50 pF, and CS is tied low. (Refer to Figure 1-2 and Figure 1-3).
Parameters
Sym
Min
Typ
Max
Units
Conditions
CS Logic Threshold, Low
VIL
VSS
—
0.2 VDD
V
CS Input Current, Low
ICSL
-1.0
—
—
µA
CS Logic Threshold, High
VIH
0.8 VDD
—
VDD
V
CS Input Current, High
ICSH
—
0.7
2.0
µA
CS = VDD
Shutdown VSS current
IQ_SHDN
-2.0
-0.7
—
µA
CS = VDD
Amplifier Output Leakage in Shutdown
IO_SHDN
—
1
—
nA
tON
—
3.1
10
µs
CS ≤ 0.2VDD, G = +1 V/V
tOFF
—
100
—
ns
CS ≥ 0.8VDD, G = +1 V/V, No load.
VHYST
—
0.4
—
V
VDD = 5.0V
CS Low Specifications
CS = 0.2VDD
CS High Specifications
Timing
CS Low to Amplifier Output Turn-on Time
CS High to Amplifier Output High-Z Time
Hysteresis
CS
tON
VOUT
IDD
Hi-Z
tOFF
Output Active
2 nA
(typical)
ISS
-700 nA
(typical)
CS
Current
700 nA
(typical)
FIGURE 1-1:
Timing Diagram.
Hi-Z
230 µA
(typical)
-230 µA
(typical)
2 nA
(typical)
MCP603 Chip Select (CS)
© 2007 Microchip Technology Inc.
DS21314G-page 3
MCP601/1R/2/3/4
TEMPERATURE CHARACTERISTICS
Electrical Specifications: Unless otherwise indicated, VDD = +2.7V to +5.5V and VSS = GND.
Parameters
Sym
Min
Typ
Max
Units
Conditions
Specified Temperature Range
TA
-40
—
+85
°C
Industrial temperature parts
TA
-40
—
+125
°C
Extended temperature parts
Operating Temperature Range
TA
-40
—
+125
°C
Note
Storage Temperature Range
TA
-65
—
+150
°C
Temperature Ranges
Thermal Package Resistances
Thermal Resistance, 5L-SOT23
θJA
—
256
—
°C/W
Thermal Resistance, 6L-SOT23
θJA
—
230
—
°C/W
Thermal Resistance, 8L-PDIP
θJA
—
85
—
°C/W
Thermal Resistance, 8L-SOIC
θJA
—
163
—
°C/W
Thermal Resistance, 8L-TSSOP
θJA
—
124
—
°C/W
Thermal Resistance, 14L-PDIP
θJA
—
70
—
°C/W
Thermal Resistance, 14L-SOIC
θJA
—
120
—
°C/W
Thermal Resistance, 14L-TSSOP
θJA
—
100
—
°C/W
Note:
1.1
The Industrial temperature parts operate over this extended range, but with reduced performance. The
Extended temperature specs do not apply to Industrial temperature parts. In any case, the internal Junction
temperature (TJ) must not exceed the absolute maximum specification of 150°C.
Test Circuits
The test circuits used for the DC and AC tests are
shown in Figure 1-2 and Figure 1-2. The bypass
capacitors are laid out according to the rules discussed
in Section 4.5 “Supply Bypass”.
VDD
VIN
RN
0.1 µF 1 µF
VOUT
MCP60X
CL
VDD/2 RG
RL
RF
VL
FIGURE 1-2:
AC and DC Test Circuit for
Most Non-Inverting Gain Conditions.
VDD
VDD/2
RN
0.1 µF 1 µF
VOUT
MCP60X
CL
VIN
RG
RL
RF
VL
FIGURE 1-3:
AC and DC Test Circuit for
Most Inverting Gain Conditions.
DS21314G-page 4
© 2007 Microchip Technology Inc.
MCP601/1R/2/3/4
2.0
TYPICAL PERFORMANCE CURVES
Note:
The graphs and tables provided following this note are a statistical summary based on a limited number of
samples and are provided for informational purposes only. The performance characteristics listed herein
are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified
operating range (e.g., outside specified power supply range) and therefore outside the warranted range.
0
100
-30
Phase
80
Gain
300
-60
60
-90
40
-120
20
-150
0
-180
-20
-210
Quiescent Current
per Amplifier (µA)
120
Open-Loop Phase (°)
Open-Loop Gain (dB)
Note: Unless otherwise indicated, TA = +25°C, VDD = +2.7V to +5.5V, VSS = GND, VCM = VDD/2, VOUT ≈ VDD/2,
VL = VDD/2, RL = 100 kΩ to VL, CL = 50 pF and CS is tied low.
-40
-240
0.1 1.E+
1 1.E+
10 1.E+
100 1.E+
1k 1.E+
10k 100k
1M 10M
1.E1.E+ 1.E+
1.E+
01 00 01 Frequency
02 03 (Hz)
04 05 06 07
FIGURE 2-1:
Frequency.
Falling Edge
Quiescent Current
per Amplifier (µA)
Slew Rate (V/µs)
50
Quiescent Current vs.
300
Rising Edge
1.5
1.0
0.5
0.0
IO = 0
250
VDD = 5.5V
200
150
VDD = 2.7V
100
50
0
0
25
50
75
Ambient Temperature (°C)
FIGURE 2-2:
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
125
Slew Rate vs. Temperature.
GBWP
PM, G = +1
-50
100
-25
0
25
50
75 100
Ambient Temperature (°C)
110
100
90
80
70
60
50
40
30
20
10
0
125
-25
FIGURE 2-5:
Temperature.
0
25
50
75
100
Ambient Temperature (°C)
125
Quiescent Current vs.
1.E+04
10µ
FIGURE 2-3:
Gain Bandwidth Product,
Phase Margin vs. Temperature.
© 2007 Microchip Technology Inc.
-50
Input Noise Voltage Density
(V/√Hz)
-25
Phase Margin, G = +1 (°)
-50
Gain Bandwidth Product
(MHz)
TA = -40°C
TA = +25°C
TA = +85°C
TA = +125°C
100
FIGURE 2-4:
Supply Voltage.
3.0
2.0
150
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Supply Voltage (V)
VDD = 5.0V
2.5
200
0
Open-Loop Gain, Phase vs.
3.5
IO = 0
250
1µ
1.E+03
100n
1.E+02
10n
1.E+01
0.1
1
10
100
1k
10k 100k 1M
1.E- 1.E+0 1.E+0 1.E+0 1.E+0 1.E+0 1.E+0 1.E+0
01
0
1 Frequency
2
3 (Hz) 4
5
6
FIGURE 2-6:
vs. Frequency.
Input Noise Voltage Density
DS21314G-page 5
MCP601/1R/2/3/4
Note: Unless otherwise indicated, TA = +25°C, VDD = +2.7V to +5.5V, VSS = GND, VCM = VDD/2, VOUT ≈ VDD/2,
VL = VDD/2, RL = 100 kΩ to VL, CL = 50 pF and CS is tied low.
14%
18%
1200 Samples
Percentage of Occurrences
12%
10%
8%
6%
4%
2%
0%
16%
14%
12%
10%
8%
6%
4%
2%
0%
-2.0 -1.6 -1.2 -0.8 -0.4 0.0 0.4 0.8 1.2 1.6 2.0
Input Offset Voltage (mV)
-8
-6 -4 -2
0
2
4
6
8
Input Offset Voltage Drift (µV/°C)
10
Input Offset Voltage Drift.
100
0.5
0.4
0.3
0.2
0.1
0.0
-0.1
-0.2
-0.3
-0.4
-0.5
CMRR, PSRR (dB)
VDD = 5.5V
VDD = 2.7V
95
90
PSRR
85
CMRR
80
75
0
25
50
75
Ambient Temperature (°C)
Common Mode Input Voltage (V)
FIGURE 2-9:
Input Offset Voltage vs.
Common Mode Input Voltage with VDD = 2.7V.
125
VDD = 5.5V
TA = –40°C
TA = +25°C
TA = +85°C
5.0
4.5
4.0
3.5
TA = +125°C
3.0
800
700
600
500
400
300
200
100
0
-100
-200
100
CMRR, PSRR vs.
2.5
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.2
0.0
TA = +125°C
-0.2
-25
2.0
Input Offset Voltage (µV)
TA = –40°C
TA = +25°C
TA = +85°C
DS21314G-page 6
-50
FIGURE 2-11:
Temperature.
Input Offset Voltage vs.
VDD = 2.7V
-0.4
800
700
600
500
400
300
200
100
0
-100
-200
125
1.5
FIGURE 2-8:
Temperature.
100
1.0
0
25
50
75
Ambient Temperature (°C)
0.5
-25
-0.5
-50
Input Offset Voltage (µV)
-10
FIGURE 2-10:
Input Offset Voltage.
0.4
Input Offset Voltage (mV)
FIGURE 2-7:
1200 Samples
TA = –40 to +125°C
0.0
Percentage of Occurrences
16%
Common Mode Input Voltage (V)
FIGURE 2-12:
Input Offset Voltage vs.
Common Mode Input Voltage with VDD = 5.5V.
© 2007 Microchip Technology Inc.
MCP601/1R/2/3/4
Note: Unless otherwise indicated, TA = +25°C, VDD = +2.7V to +5.5V, VSS = GND, VCM = VDD/2, VOUT ≈ VDD/2,
VL = VDD/2, RL = 100 kΩ to VL, CL = 50 pF and CS is tied low.
140
130
120
110
100
10k
100k
1.E+04
1.E+05
Frequency (Hz)
80
70
CMRR
60
50
40
30
VDD = 5.0V
10
1
100
10k
1M
10
1k
100k
1.E+00 1.E+01 1.E+02 1.E+03 1.E+04 1.E+05 1.E+06
Frequency (Hz)
1M
1.E+06
FIGURE 2-13:
Channel-to-Channel
Separation vs. Frequency.
FIGURE 2-16:
Frequency.
CMRR, PSRR vs.
1000
VDD = 5.5V
VCM = 4.3V
Input Bias and Offset
Currents (pA)
Input Bias and Offset
Currents (pA)
PSRR+
PSRR–
90
20
90
1k
1.E+03
1000
100
No Load
Input Referred
CMRR, PSRR (dB)
Channel-to-Channel
Separation (dB)
150
100
IB
IOS
10
IB, +125°C
VDD = 5.5V
max. VCMR ≥ 4.3V
100
IB, +85°C
IOS, +125°C
10
IOS, +85°C
1
1
25
35
45 55 65 75 85 95 105 115 125
Ambient Temperature (°C)
FIGURE 2-14:
Input Bias Current, Input
Offset Current vs. Ambient Temperature.
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Common Mode Input Voltage (V)
FIGURE 2-17:
Input Bias Current, Input
Offset Current vs. Common Mode Input Voltage.
120
110
DC Open-Loop Gain (dB)
DC Open-Loop Gain (dB)
120
VDD = 5.5V
100
90
VDD = 2.7V
80
100
1.E+02
1k
1.E+03
10k
1.E+04
100k
1.E+05
RL = 25 kΩ
110
100
90
80
2.0
2.5
Load Resistance (Ω)
FIGURE 2-15:
Load Resistance.
DC Open-Loop Gain vs.
© 2007 Microchip Technology Inc.
FIGURE 2-18:
Supply Voltage.
3.0
3.5
4.0
4.5
Power Supply Voltage (V)
5.0
5.5
DC Open-Loop Gain vs.
DS21314G-page 7
MCP601/1R/2/3/4
Note: Unless otherwise indicated, TA = +25°C, VDD = +2.7V to +5.5V, VSS = GND, VCM = VDD/2, VOUT ≈ VDD/2,
VL = VDD/2, RL = 100 kΩ to VL, CL = 50 pF and CS is tied low.
100
3.0
90
GBWP
2.5
80
2.0
70
1.5
PM, G = +1
60
1.0
50
0.5
40
0.0
100
1.E+02
1k
10k
1.E+03
1.E+04
Load Resistance (Ω)
130
DC Open-Loop Gain (dB)
VDD = 5.0V
Phase Margin, G = +1 (°)
Gain Bandwidth Product
(MHz)
3.5
RL = 25 kΩ
120
VDD = 5.5V
110
100
90
VDD = 2.7V
80
30
100k
1.E+05
-50
FIGURE 2-19:
Gain Bandwidth Product,
Phase Margin vs. Load Resistance.
Output Headroom (mV);
VDD – V OH and V OL – V SS
Output Headroom (mV);
VDD – V OH and V OL – V SS
1000
100
VDD – VOH
VOL – VSS
10
1
0.01
125
DC Open-Loop Gain vs.
VDD – VOH
RL = 5 kΩ
10
RL = 25 kΩ
VOL – VSS
-50
VDD = 2.7V
1
100k
1.E+05
Frequency (Hz)
1M
1.E+06
FIGURE 2-21:
Maximum Output Voltage
Swing vs. Frequency.
-25
FIGURE 2-23:
vs. Temperature.
Output Short Circuit Current
Magnitude (mA)
Maximum Output Voltage
Swing (V P-P )
100
VDD = 5.5V
RL tied to VDD/2
100
10
VDD = 5.5V
DS21314G-page 8
0
25
50
75
Ambient Temperature (°C)
1
0.1
1
Output Current Magnitude (mA)
FIGURE 2-20:
Output Voltage Headroom
vs. Output Current.
0.1
10k
1.E+04
-25
FIGURE 2-22:
Temperature.
1,000
10
RL = 5 kΩ
0
25
50
75
100
Ambient Temperature (°C)
125
Output Voltage Headroom
30
25
20
TA = –40°C
TA = +25°C
TA = +85°C
TA = +125°C
15
10
5
0
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Supply Voltage (V)
FIGURE 2-24:
Output Short-Circuit Current
vs. Supply Voltage.
© 2007 Microchip Technology Inc.
MCP601/1R/2/3/4
Note: Unless otherwise indicated, TA = +25°C, VDD = +2.7V to +5.5V, VSS = GND, VCM = VDD/2, VOUT ≈ VDD/2,
VL = VDD/2, RL = 100 kΩ to VL, CL = 50 pF and CS is tied low.
Output Voltage (V)
4.5
4.0
5.0
VDD = 5.0V
G = +1
VDD = 5.0V
G = –1
4.5
Output Voltage (V)
5.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
0.0
Time (1 µs/div)
Time (1 µs/div)
Large Signal Non-Inverting
Output Voltage (20 mV/div)
VDD = 5.0V
G = +1
FIGURE 2-28:
Response.
Time (1 µs/div)
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
-0.5
Time (1 µs/div)
Small Signal Non-Inverting
0
-100
CS
VDD = 5.0V
G = +1
VIN = 2.5V
RL = 100 kΩ to GND
VOUT Active
Small Signal Inverting Pulse
VDD = 5.5V
-200
-300
-400
-500
-600
-700
VOUT High-Z
Time (5 µs/div)
FIGURE 2-27:
(MCP603).
FIGURE 2-29:
Response.
Quiescent Current
through V SS (µA)
Output Voltage,
Chip Select Voltage (V)
FIGURE 2-26:
Pulse Response.
Large Signal Inverting Pulse
VDD = 5.0V
G = –1
Output Voltage (20 mV/div)
FIGURE 2-25:
Pulse Response.
Chip Select Timing
© 2007 Microchip Technology Inc.
-800
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Chip Select Voltage (V)
FIGURE 2-30:
Quiescent Current Through
VSS vs. Chip Select Voltage (MCP603).
DS21314G-page 9
MCP601/1R/2/3/4
Note: Unless otherwise indicated, TA = +25°C, VDD = +2.7V to +5.5V, VSS = GND, VCM = VDD/2, VOUT ≈ VDD/2,
VL = VDD/2, RL = 100 kΩ to VL, CL = 50 pF and CS is tied low.
0.7
6
VDD = 5.5V
Input and Output Voltages (V)
Chip Select Pin Current (µA)
0.8
0.6
0.5
0.4
0.3
0.2
0.1
0.0
2.5
Amplifier On
VDD = 5.0V
2.0
1.5
CS Hi to Low
CS Low to Hi
1.0
0.5
Amplifier Hi-Z
0.0
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
Chip Select Voltage (V)
FIGURE 2-32:
Internal Switch.
DS21314G-page 10
Hysteresis of Chip Select’s
4
3
2
VIN
VOUT
1
0
Time (5 µs/div)
FIGURE 2-33:
The MCP601/1R/2/3/4
family of op amps shows no phase reversal
under input overdrive.
1.E-02
10m
1m
1.E-03
100µ
1.E-04
10µ
1.E-05
1µ
1.E-06
100n
1.E-07
10n
1.E-08
1n
1.E-09
100p
1.E-10
10p
1.E-11
1p
1.E-12
Input Current Magnitude (A)
Internal Chip Select Switch
Output Voltage (V)
3.0
VDD = +5.0V
G = +2
-1
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Chip Select Voltage (V)
FIGURE 2-31:
Chip Select Pin Input
Current vs. Chip Select Voltage.
5
+125°C
+85°C
+25°C
-40°C
-1.0 -0.9 -0.8 -0.7 -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0.0
Input Voltage (V)
FIGURE 2-34:
Measured Input Current vs.
Input Voltage (below VSS).
© 2007 Microchip Technology Inc.
MCP601/1R/2/3/4
3.0
PIN DESCRIPTIONS
Descriptions of the pins are listed in Table 3-1 (single op amps) and Table 3-2 (dual and quad op amps).
TABLE 3-1:
PIN FUNCTION TABLE FOR SINGLE OP AMPS
MCP601
PDIP, SOIC,
TSSOP
MCP601R
SOT-23-5
SOT-23-5
(Note 1)
SOT-23-6
1
1
6
6
VOUT
Analog Output
4
4
2
2
VIN–
Inverting Input
3
3
3
3
3
VIN+
Non-inverting Input
7
5
2
7
7
VDD
Positive Power Supply
4
2
5
4
4
VSS
Negative Power Supply
—
—
—
8
8
CS
Chip Select
1, 5, 8
—
—
1, 5
1
NC
No Internal Connection
The MCP601R is only available in the 5-pin SOT-23 package.
PIN FUNCTION TABLE FOR DUAL AND QUAD OP AMPS
MCP602
MCP604
PDIP, SOIC,
TSSOP
PDIP, SOIC,
TSSOP
Symbol
Description
1
1
VOUTA
Analog Output (op amp A)
2
2
VINA–
Inverting Input (op amp A)
3
3
VINA+
8
4
VDD
5
5
VINB+
Non-inverting Input (op amp B)
6
6
VINB–
Inverting Input (op amp B)
7
7
VOUTB
Analog Output (op amp B)
—
8
VOUTC
Analog Output (op amp C)
Non-inverting Input (op amp A)
Positive Power Supply
—
9
VINC–
Inverting Input (op amp C)
—
10
VINC+
Non-inverting Input (op amp C)
4
11
VSS
—
12
VIND+
Non-inverting Input (op amp D)
Negative Power Supply
—
13
VIND–
Inverting Input (op amp D)
—
14
VOUTD
Analog Output (op amp D)
Analog Outputs
The op amp output pins are low-impedance voltage
sources.
Analog Inputs
The op amp non-inverting and inverting inputs are highimpedance CMOS inputs with low bias currents.
3.3
Description
6
TABLE 3-2:
3.2
Symbol
PDIP, SOIC,
TSSOP
2
Note 1:
3.1
MCP603
Chip Select Digital Input
3.4
Power Supply Pins
The positive power supply pin (VDD) is 2.5V to 6.0V
higher than the negative power supply pin (VSS). For
normal operation, the other pins are at voltages
between VSS and VDD.
Typically, these parts are used in a single (positive)
supply configuration. In this case, VSS is connected to
ground and VDD is connected to the supply. VDD will
need bypass capacitors.
This is a CMOS, Schmitt-triggered input that places the
part into a low power mode of operation.
© 2007 Microchip Technology Inc.
DS21314G-page 11
MCP601/1R/2/3/4
4.0
APPLICATIONS INFORMATION
VDD
The MCP601/1R/2/3/4 family of op amps are fabricated
on Microchip’s state-of-the-art CMOS process. They
are unity-gain stable and suitable for a wide range of
general purpose applications.
4.1
D1
V1
R1
Inputs
4.1.1
PHASE REVERSAL
R2
INPUT VOLTAGE AND CURRENT
LIMITS
The ESD protection on the inputs can be depicted as
shown in Figure 4-1. This structure was chosen to
protect the input transistors, and to minimize input bias
current (IB). The input ESD diodes clamp the inputs
when they try to go more than one diode drop below
VSS. They also clamp any voltages that go too far
above VDD; their breakdown voltage is high enough to
allow normal operation, and low enough to bypass
quick ESD events within the specified limits.
VDD Bond
Pad
R3
VSS – (minimum expected V1)
2 mA
VSS – (minimum expected V2)
R2 >
2 mA
R1 >
FIGURE 4-2:
Inputs.
Input
Stage
Bond
VIN–
Pad
VSS Bond
Pad
FIGURE 4-1:
Structures.
Simplified Analog Input ESD
In order to prevent damage and/or improper operation
of these op amps, the circuit they are in must limit the
currents and voltages at the VIN+ and VIN– pins (see
Absolute Maximum Ratings † at the beginning of
Section 1.0 “Electrical Characteristics”). Figure 4-2
shows the recommended approach to protecting these
inputs. The internal ESD diodes prevent the input pins
(VIN+ and VIN–) from going too far below ground, and
the resistors R1 and R2 limit the possible current drawn
out of the input pins. Diodes D1 and D2 prevent the
input pins (VIN+ and VIN–) from going too far above
VDD, and dump any currents onto VDD. When
implemented as shown, resistors R1 and R2 also limit
the current through D1 and D2.
DS21314G-page 12
Protecting the Analog
It is also possible to connect the diodes to the left of
resistors R1 and R2. In this case, current through the
diodes D1 and D2 needs to be limited by some other
mechanism. The resistors then serve as in-rush current
limiters; the DC current into the input pins (VIN+ and
VIN–) should be very small.
A significant amount of current can flow out of the
inputs when the common mode voltage (VCM) is below
ground (VSS); see Figure 2-34. Applications that are
high impedance may need to limit the useable voltage
range.
4.1.3
VIN+ Bond
Pad
MCP60X
V2
The MCP601/1R/2/3/4 op amp is designed to prevent
phase reversal when the input pins exceed the supply
voltages. Figure 2-34 shows the input voltage
exceeding the supply voltage without any phase
reversal.
4.1.2
D2
NORMAL OPERATION
The Common Mode Input Voltage Range (VCMR)
includes ground in single-supply systems (VSS), but
does not include VDD. This means that the amplifier
input behaves linearly as long as the Common Mode
Input Voltage (VCM) is kept within the specified VCMR
limits (VSS–0.3V to VDD–1.2V at +25°C).
Figure 4-3 shows a unity gain buffer. Since VOUT is the
same voltage as the inverting input, VOUT must be kept
below VDD–1.2V for correct operation.
VIN
+
MCP60X
–
VOUT
FIGURE 4-3:
Unity Gain Buffer has a
Limited VOUT Range.
© 2007 Microchip Technology Inc.
MCP601/1R/2/3/4
Rail-to-Rail Output
There are two specifications that describe the output
swing capability of the MCP601/1R/2/3/4 family of op
amps. The first specification (Maximum Output Voltage
Swing) defines the absolute maximum swing that can
be achieved under the specified load conditions. For
instance, the output voltage swings to within 15 mV of
the negative rail with a 25 kΩ load to VDD/2. Figure 2-33
shows how the output voltage is limited when the input
goes beyond the linear region of operation.
The second specification that describes the output
swing capability of these amplifiers is the Linear Output
Voltage Swing. This specification defines the maximum
output swing that can be achieved while the amplifier is
still operating in its linear region. To verify linear
operation in this range, the large signal (DC Open-Loop
Gain (AOL)) is measured at points 100 mV inside the
supply rails. The measurement must exceed the
specified gains in the specification table.
4.3
MCP603 Chip Select
The MCP603 is a single amplifier with Chip Select
(CS). When CS is pulled high, the supply current drops
to -0.7 µA (typ.), which is pulled through the CS pin to
VSS. When this happens, the amplifier output is put into
a high-impedance state. Pulling CS low enables the
amplifier.
The CS pin has an internal 5 MΩ (typical) pull-down
resistor connected to VSS, so it will go low if the CS pin
is left floating. Figure 1-1 is the Chip Select timing
diagram and shows the output voltage, supply currents,
and CS current in response to a CS pulse. Figure 2-27
shows the measured output voltage response to a CS
pulse.
4.4
Capacitive Loads
Driving large capacitive loads can cause stability
problems for voltage feedback op amps. As the load
capacitance increases, the feedback loop’s phase
margin decreases and the closed-loop bandwidth is
reduced. This produces gain peaking in the frequency
response with overshoot and ringing in the step
response.
When driving large capacitive loads with these op
amps (e.g., > 40 pF when G = +1), a small series
resistor at the output (RISO in Figure 4-4) improves the
feedback loop’s phase margin (stability) by making the
output load resistive at higher frequencies. The
bandwidth will be generally lower than the bandwidth
with no capacitive load.
© 2007 Microchip Technology Inc.
+
MCP60X
–
RG
RISO
VOUT
CL
RF
FIGURE 4-4:
Output resistor RISO
stabilizes large capacitive loads.
Figure 4-5 gives recommended RISO values for
different capacitive loads and gains. The x-axis is the
normalized load capacitance (CL/GN) in order to make
it easier to interpret the plot for arbitrary gains. GN is the
circuit’s noise gain. For non-inverting gains, GN and the
gain are equal. For inverting gains, GN = 1 + |Gain|
(e.g., -1 V/V gives GN = +2 V/V).
1k
Recommended RISO (Ω)
4.2
100
GN = +1
GN ≥ +2
10
10p
100p
1n
Normalized Load Capacitance;
CL / GN (F)
10n
FIGURE 4-5:
Recommended RISO values
for capacitive loads.
Once you have selected RISO for your circuit, doublecheck the resulting frequency response peaking and
step response overshoot in your circuit. Evaluation on
the bench and simulations with the MCP601/1R/2/3/4
SPICE macro model are very helpful. Modify RISO’s
value until the response is reasonable.
4.5
Supply Bypass
With this family of op amps, the power supply pin (VDD
for single-supply) should have a local bypass capacitor
(i.e., 0.01 µF to 0.1 µF) within 2 mm for good highfrequency performance. It also needs a bulk capacitor
(i.e., 1 µF or larger) within 100 mm to provide large,
slow currents. This bulk capacitor can be shared with
nearby analog parts.
DS21314G-page 13
MCP601/1R/2/3/4
4.6
Unused Op Amps
2.
An unused op amp in a quad package (MCP604)
should be configured as shown in Figure 4-6. These
circuits prevent the output from toggling and causing
crosstalk. Circuits A sets the op amp at its minimum
noise gain. The resistor divider produces any desired
reference voltage within the output voltage range of the
op amp; the op amp buffers that reference voltage.
Circuit B uses the minimum number of components
and operates as a comparator, but it may draw more
current.
¼ MCP604 (A)
¼ MCP604 (B)
VDD
R1
VDD
4.8.1
Typical Applications
ANALOG FILTERS
Figure 4-8 and Figure 4-9 show low-pass, secondorder, Butterworth filters with a cutoff frequency of
10 Hz. The filter in Figure 4-8 has a non-inverting gain
of +1 V/V, and the filter in Figure 4-9 has an inverting
gain of -1 V/V.
FIGURE 4-6:
In applications where low input bias current is critical,
printed circuit board (PCB) surface leakage effects
need to be considered. Surface leakage is caused by
humidity, dust or other contamination on the board.
Under low humidity conditions, a typical resistance
between nearby traces is 1012Ω. A 5V difference
would cause 5 pA of current to flow. This is greater
than the MCP601/1R/2/3/4 family’s bias current at
+25°C (1 pA, typical).
The easiest way to reduce surface leakage is to use a
guard ring around sensitive pins (or traces). The guard
ring is biased at the same voltage as the sensitive pin.
An example of this type of layout is shown in
Figure 4-7.
FIGURE 4-7:
VIN– VIN+
Example Guard Ring layout.
Connect the guard ring to the inverting input pin
(VIN–) for non-inverting gain amplifiers, including unity-gain buffers. This biases the guard ring
to the common mode input voltage.
DS21314G-page 14
R2
R1
382 kΩ 641 kΩ
VIN
+
MCP60X
C2
22 nF
FIGURE 4-8:
Sallen-Key Filter.
VOUT
–
Unused Op Amps.
PCB Surface Leakage
Guard Ring
G = +1 V/V
fP = 10 Hz
C1
47 nF
VREF
R2
V REF = V DD ⋅ -----------------R1 + R2
1.
4.8
VDD
R2
4.7
Connect the guard ring to the non-inverting input
pin (VIN+) for inverting gain amplifiers and
transimpedance amplifiers (converts current to
voltage, such as photo detectors). This biases
the guard ring to the same reference voltage as
the op amp (e.g., VDD/2 or ground).
Second-Order, Low-Pass
G = -1 V/V
fP = 10 Hz
R2
618 kΩ
C1
8.2 nF
R3
R1
618 kΩ 1.00 MΩ
VOUT
VIN
C2
47 nF
–
MCP60X
VDD/2
+
FIGURE 4-9:
Second-Order, Low-Pass
Multiple-Feedback Filter.
The MCP601/1R/2/3/4 family of op amps have low
input bias current, which allows the designer to select
larger resistor values and smaller capacitor values for
these filters. This helps produce a compact PCB layout.
These filters, and others, can be designed using
Microchip’s Design Aids; see Section 5.2 “FilterLab®
Software” and Section 5.3 “Mindi™ Simulatior
Tool”.
© 2007 Microchip Technology Inc.
MCP601/1R/2/3/4
4.8.2
INSTRUMENTATION AMPLIFIER
CIRCUITS
Instrumentation amplifiers have a differential input that
subtracts one input voltage from another and rejects
common mode signals. These amplifiers also provide a
single-ended output voltage.
The three-op amp instrumentation amplifier is illustrated
in Figure 4-10. One advantage of this approach is unitygain operation, while one disadvantage is that the
common mode input range is reduced as R2/RG gets
larger.
V1
+
R3
MCP60X
R4
–
–
MCP60X
RG
R2
VOUT
4.8.3
PHOTO DETECTION
The MCP601/1R/2/3/4 op amps can be used to easily
convert the signal from a sensor that produces an
output current (such as a photo diode) into a voltage (a
transimpedance amplifier). This is implemented with a
single resistor (R2) in the feedback loop of the
amplifiers shown in Figure 4-12 and Figure 4-13. The
optional capacitor (C2) sometimes provides stability for
these circuits.
A photodiode configured in the Photovoltaic mode has
zero voltage potential placed across it (Figure 4-12). In
this mode, the light sensitivity and linearity is
maximized, making it best suited for precision
applications. The key amplifier specifications for this
application are: low input bias current, low noise,
common mode input voltage range (including ground),
and rail-to-rail output.
+
R2
R3
C2
R4
R2
–
V2
VOUT
ID1
VREF
MCP60X
+
2R R 4
V OUT = ( V 1 – V 2 ) ⎛⎝ 1 + --------2-⎞⎠ ⎛⎝ ------⎞⎠ + V REF
RG R3
D1
Light
–
VDD
MCP60X
+
VOUT = ID1 R2
FIGURE 4-10:
Three-Op Amp
Instrumentation Amplifier.
FIGURE 4-12:
The two-op amp instrumentation amplifier is shown in
Figure 4-11. While its power consumption is lower than
the three-op amp version, its main drawbacks are that
the common mode range is reduced with higher gains
and it must be configured in gains of two or higher.
RG
R2
R1
VREF
V2
VOUT
R2
R1
Photovoltaic Mode Detector.
In contrast, a photodiode that is configured in the
Photoconductive mode has a reverse bias voltage
across the photo-sensing element (Figure 4-13). This
decreases the diode capacitance, which facilitates
high-speed operation (e.g., high-speed digital
communications). The design trade-off is increased
diode leakage current and linearity errors. The op amp
needs to have a wide Gain Bandwidth Product
(GBWP).
-
-
C2
MCP60X
+
MCP60X
+
R2
ID1
V1
V OUT
R
2R
= ( V 1 – V 2 ) ⎛ 1 + -----1- + --------1-⎞ + V REF
⎝
R
R ⎠
2
D1
Light
VOUT
MCP60X
G
VBIAS
FIGURE 4-11:
Two-Op Amp
Instrumentation Amplifier.
Both instrumentation amplifiers should use a bulk
bypass capacitor of at least 1 µF. The CMRR of these
amplifiers will be set by both the op amp CMRR and
resistor matching.
© 2007 Microchip Technology Inc.
–
VDD
+
VOUT = ID1 R2
VBIAS < 0V
FIGURE 4-13:
Detector.
Photoconductive Mode
DS21314G-page 15
MCP601/1R/2/3/4
5.0
DESIGN AIDS
Microchip provides the basic design tools needed for
the MCP601/1R/2/3/4 family of op amps.
5.1
SPICE Macro Model
The latest SPICE macro model for the MCP601/1R/2/
3/4 op amps is available on the Microchip web site at
www.microchip.com. This model is intended to be an
initial design tool that works well in the op amp’s linear
region of operation over the temperature range. See
the model file for information on its capabilities.
Bench testing is a very important part of any design and
cannot be replaced with simulations. Also, simulation
results using this macro model need to be validated by
comparing them to the data sheet specifications and
characteristic curves.
5.2
FilterLab® Software
Microchip’s FilterLab® software is an innovative
software tool that simplifies analog active filter (using
op amps) design. Available at no cost from the
Microchip web site at www.microchip.com/filterlab, the
FilterLab design tool provides full schematic diagrams
of the filter circuit with component values. It also
outputs the filter circuit in SPICE format, which can be
used with the macro model to simulate actual filter
performance.
5.3
Mindi™ Simulatior Tool
Microchip’s Mindi™ simulator tool aids in the design of
various circuits useful for active filter, amplifier and
power-management applications. It is a free online
simulation tool available from the Microchip web site at
www.microchip.com/mindi. This interactive simulator
enables designers to quickly generate circuit diagrams,
simulate circuits. Circuits developed using the Mindi
simulation tool can be downloaded to a personal
computer or workstation.
5.4
5.5
Analog Demonstration and
Evaluation Boards
Microchip offers a broad spectrum of Analog
Demonstration and Evaluation Boards that are
designed to help you achieve faster time to market. For
a complete listing of these boards and their
corresponding user’s guides and technical information,
visit the Microchip web site at www.microchip.com/
analogtools.
Two of our boards that are especially useful are:
• P/N SOIC8EV: 8-Pin SOIC/MSOP/TSSOP/DIP
Evaluation Board
• P/N SOIC14EV: 14-Pin SOIC/TSSOP/DIP Evaluation Board
5.6
Application Notes
The following Microchip Application Notes are available on the Microchip web site at www.microchip. com/
appnotes and are recommended as supplemental
reference resources.
ADN003: “Select the Right Operational Amplifier for
your Filtering Circuits”, DS21821
AN722: “Operational Amplifier Topologies and DC
Specifications”, DS00722
AN723: “Operational Amplifier AC Specifications and
Applications”, DS00723
AN884: “Driving Capacitive Loads With Op Amps”,
DS00884
AN990: “Analog Sensor Conditioning Circuits – An
Overview”, DS00990
These application notes and others are listed in the
design guide:
“Signal Chain Design Guide”, DS21825
MAPS (Microchip Advanced Part
Selector)
MAPS is a software tool that helps semiconductor
professionals efficiently identify Microchip devices that
fit a particular design requirement. Available at no cost
from the Microchip website at www.microchip.com/
maps, the MAPS is an overall selection tool for
Microchip’s product portfolio that includes Analog,
Memory, MCUs and DSCs. Using this tool you can
define a filter to sort features for a parametric search of
devices and export side-by-side technical comparasion
reports. Helpful links are also provided for Datasheets,
Purchase, and Sampling of Microchip parts.
DS21314G-page 16
© 2007 Microchip Technology Inc.
MCP601/1R/2/3/4
6.0
PACKAGING INFORMATION
6.1
Package Marking Information
5-Lead SOT-23 (MCP601 and MCP601R only)
I-Temp
Code
E-Temp
Code
MCP601
SANN
SLNN
MCP601R
SJNN
SMNN
Device
XXNN
Example:
6-Lead SOT-23 (MCP603 only)
Device
XXNN
Legend: XX...X
Y
YY
WW
NNN
e3
*
Note:
MCP603
SJ25
Example:
I-Temp
Code
E-Temp
Code
AENN
AUNN
AU25
Customer-specific information
Year code (last digit of calendar year)
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code
Pb-free JEDEC designator for Matte Tin (Sn)
This package is Pb-free. The Pb-free JEDEC designator ( e3 )
can be found on the outer packaging for this package.
In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
© 2007 Microchip Technology Inc.
DS21314G-page 17
MCP601/1R/2/3/4
Package Marking Information (Continued)
8-Lead PDIP (300 mil)
MCP601
I/P256
0722
XXXXXXXX
XXXXXNNN
YYWW
8-Lead SOIC (150 mil)
OR
MCP601
E/P e3 256
0722
Example:
MCP601
I/SN0722
256
XXXXXXXX
XXXXYYWW
NNN
OR
MCP601E
SN e3 0722
256
Example:
8-Lead TSSOP
DS21314G-page 18
Example:
XXXX
601
XYWW
I722
NNN
256
© 2007 Microchip Technology Inc.
MCP601/1R/2/3/4
Package Marking Information (Continued)
Example:
14-Lead PDIP (300 mil) (MCP604)
MCP604-I/P
XXXXXXXXXXXXXX
XXXXXXXXXXXXXX
YYWWNNN
0722256
MCP604
E/P e3
0722256
OR
14-Lead SOIC (150 mil) (MCP604)
Example:
MCP604ISL
XXXXXXXXXX
XXXXXXXXXX
YYWWNNN
0722256
MCP604
e3
E/SL^^
0722256
OR
14-Lead TSSOP (MCP604)
Example:
XXXXXXXX
YYWW
604E
0722
NNN
256
© 2007 Microchip Technology Inc.
DS21314G-page 19
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