MCP619-I/SL

MCP616/7/8/9 2.3V to 5.5V Micropower Bi-CMOS Op Amps Features Description • • • • • • • • • • • The MCP616/7/8/9 family of operational amplifiers (op amps) from Microchip Technology Inc. are capable of precision, low-power, single-supply operation. These op amps are unity-gain stable, have low input offset voltage (±150 µV, maximum), rail-to-rail output swing and low input offset current (0.3 nA, typical). These features make this family of op amps well suited for battery-powered applications. Low Input Offset Voltage: ±150 µV (maximum) Low Noise: 2.2 µVP-P (typical, 0.1 Hz to 10 Hz) Rail-to-Rail Output Low Input Offset Current: 0.3 nA (typical) Low Quiescent Current: 25 µA (maximum) Power Supply Voltage: 2.3V to 5.5V Unity Gain Stable Chip Select (CS) Capability: MCP618 Industrial Temperature Range: -40°C to +85°C No Phase Reversal Available in Single, Dual and Quad Packages Typical Applications • • • • • Battery Power Instruments Weight Scales Strain Gauges Medical Instruments Test Equipment Package Types MCP616 PDIP, SOIC, MSOP Design Aids • • • • • SPICE Macro Models Microchip Advanced Part Selector (MAPS) Mindi™ Circuit Designer & Simulator Analog Demonstration and Evaluation Boards Application Notes 12% 598 Samples VDD = 5.5V 10% NC VIN– VIN+ VSS 1 2 3 4 8 7 6 5 VOUTA 1 NC VDD VINA– 2 VOUT VINA+ 3 NC VSS 4 MCP618 PDIP, SOIC, MSOP NC VIN– VIN+ VSS 1 2 3 4 8 7 6 5 MCP617 PDIP, SOIC, MSOP 8 7 6 5 VDD VOUTB VINB– VINB+ MCP619 PDIP, SOIC, TSSOP CS VOUTA VDD VINA– VOUT VINA+ VDD NC VINB+ VINB– VOUTB 1 2 3 4 5 6 7 14 VOUTD 13 VIND– 12 VIND+ 11 VSS 10 VINC+ 9 VINC– 8 VOUTC 8% 6% 4% 2% 100 80 60 40 0 20 -20 -40 -60 -80 0% -100 Percentage of Occurrences Input Offset Voltage 14% The single MCP616, the single MCP618 with Chip Select (CS) and the dual MCP617 are all available in standard 8-lead PDIP, SOIC and MSOP packages. The quad MCP619 is offered in standard 14-lead PDIP, SOIC and TSSOP packages. All devices are fully specified from -40°C to +85°C, with power supplies from 2.3V to 5.5V. Input Offset Voltage (µV)  2019 Microchip Technology Inc. DS20001613D-page 1 MCP616/7/8/9 NOTES: DS20001613D-page 2  2019 Microchip Technology Inc. MCP616/7/8/9 1.0 ELECTRICAL CHARACTERISTICS VDD – VSS ........................................................................7.0V † Notice: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. Current at Analog Input Pins (VIN+ and VIN–)................±2 mA †† See Section 4.1.2 “Input Voltage and Current Limits”. Absolute Maximum Ratings † Analog Inputs (VIN+ and VIN–) †† .. VSS – 0.3V to VDD + 0.3V All other Inputs and Outputs .......... VSS – 0.3V to VDD + 0.3V Difference Input Voltage ...................................... |VDD – VSS| Output Short Circuit Current ................................ Continuous Current at Output and Supply Pins ............................±30 mA Storage Temperature ................................... –65°C to +150°C Maximum Junction Temperature (TJ)......................... .+150°C ESD Protection On All Pins (HBM; MM)   4 kV; 400V DC ELECTRICAL CHARACTERISTICS Electrical Specifications: Unless otherwise indicated, VDD = +2.3V to +5.5V, VSS = GND, TA = +25°C, VCM = VDD/2, VOUT  VDD/2 and RL = 100 kto VDD/2. Parameters Sym Min Typ Max Units VOS VOS/TA PSRR -150 — 86 — ±2.5 105 +150 — — µV µV/°C dB IB IB IB IOS ZCM ZDIFF -35 -70 — — — — -15 -21 -12 ±0.15 600||4 3||2 -5 — — — — — VCMR CMRR VSS 80 100 VDD – 0.9 — V dB Open-Loop Gain DC Open-Loop Gain (large signal) AOL 100 120 — dB DC Open-Loop Gain (large signal) AOL 95 115 — dB VOL, VOH VSS + 15 — VDD - 20 mV VOL, VOH VSS + 45 — VDD - 60 mV VOUT VSS + 50 — VDD - 50 mV VOUT VSS + 100 — VDD - 100 mV ISC ISC — — ±7 ±17 — — mA mA RL = 25 k to VDD/2, 0.5V input overdrive RL = 5 k to VDD/2, 0.5V input overdrive RL = 25 k to VDD/2, AOL  100 dB RL = 5 k to VDD/2, AOL 95 dB VDD = 2.3V VDD = 5.5V VDD IQ 2.3 12 — 19 5.5 25 V µA IO = 0 Input Offset Input Offset Voltage Input Offset Drift with Temperature Power Supply Rejection Input Bias Current and Impedance Input Bias Current At Temperature At Temperature Input Offset Current Common-mode Input Impedance Differential Input Impedance Common-mode Common-mode Input Voltage Range Common-mode Rejection Ratio Output Maximum Output Voltage Swing Linear Output Voltage Range Output Short Circuit Current Power Supply Supply Voltage Quiescent Current per Amplifier  2019 Microchip Technology Inc. Conditions TA = -40°C to +85°C nA nA TA = -40°C nA TA = +85°C nA M||pF M||pF VDD = 5.0V, VCM = 0.0V to 4.1V RL = 25 kto VDD/2, VOUT = 0.05V to VDD – 0.05V RL = 5 k to VDD/2, VOUT = 0.1V to VDD – 0.1V DS20001613D-page 3 MCP616/7/8/9 AC ELECTRICAL CHARACTERISTICS Electrical Specifications: Unless otherwise indicated, VDD = +2.3V to +5.5V, VSS = GND, TA = 25°C, VCM = VDD/2, VOUT  VDD/2, RL = 100 kto VDD/2 and CL = 60 pF. Parameters Sym Min Typ Max Units kHz Conditions AC Response Gain Bandwidth Product GBWP — 190 — Phase Margin PM — 57 — ° Slew Rate SR — 0.08 — V/µs G = +1V/V Noise Input Noise Voltage Eni — 2.2 — µVP-P Input Noise Voltage Density eni — 32 — nV/Hz f = 1 kHz f = 0.1 Hz to 10 Hz Input Noise Current Density ini — 70 — fA/Hz f = 1 kHz MCP618 CHIP SELECT (CS) ELECTRICAL CHARACTERISTICS Electrical Specifications: Unless otherwise indicated, VDD = +2.3V to +5.5V, VSS = GND, TA = 25°C, VCM = VDD/2, VOUT  VDD/2, RL = 100 kto VDD/2 and CL = 60 pF. Parameters Sym Min Typ Max Units Conditions CS Logic Threshold, Low VIL VSS — 0.2 VDD V CS Input Current, Low ICSL -1.0 0.01 — µA CS Logic Threshold, High VIH 0.8 VDD — VDD V CS Input Current, High ICSH — 0.01 2 µA CS = VDD ISS -2 -0.05 — µA CS = VDD IO(LEAK) — 10 — nA CS = VDD CS Low to Amplifier Output Turn-on Time tON — 9 100 µs CS = 0.2VDD to VOUT = 0.9VDD/2, G = +1 V/V, RL = 1 k to VSS CS High to Amplifier Output High-Z tOFF — 0.1 — µs CS = 0.8VDD to VOUT = 0.1VDD/2, G = +1 V/V, RL = 1 k to VSS VHYST — 0.6 — V VDD = 5.0V CS Low Specifications CS = VSS CS High Specifications GND Current Amplifier Output Leakage CS Dynamic Specifications CS Hysteresis VIH VIL CS tOFF tON VOUT High-Z ISS -50 nA (typical) ICS 10 nA (typical) High-Z -19 µA (typical) -50 nA (typical) 10 nA (typical) FIGURE 1-1: Timing Diagram for the CS Pin on the MCP618. DS20001613D-page 4  2019 Microchip Technology Inc. MCP616/7/8/9 TEMPERATURE CHARACTERISTICS Electrical Specifications: Unless otherwise indicated, VDD = +2.3V to +5.5V and VSS = GND. Parameters Sym Min Typ Max Units Specified Temperature Range TA -40 — +85 °C Operating Temperature Range TA -40 — +125 °C Storage Temperature Range TA -65 — +150 °C Thermal Resistance, 8L-MSOP JA — 211 — °C/W Thermal Resistance, 8L-PDIP JA — 89.3 — °C/W Thermal Resistance, 8L-SOIC JA — 149.5 — °C/W Thermal Resistance, 14L-PDIP JA — 70 — °C/W Thermal Resistance, 14L-SOIC JA — 95.3 — °C/W Thermal Resistance, 14L-TSSOP JA — 100 — °C/W Conditions Temperature Ranges Note 1 Thermal Package Resistances Note 1: 1.1 The MCP616/7/8/9 operate over this extended temperature range, but with reduced performance. In any case, the Junction Temperature (TJ) must not exceed the Absolute Maximum specification of +150°C. Test Circuits The test circuits used for the DC and AC tests are shown in Figure 1-2 and Figure 1-3. The bypass capacitors are laid out according to the rules discussed in Section 4.6 “Supply Bypass”. VDD VIN RN 0.1 µF 1 µF VOUT MCP61X CL VDD/2 RG RL RF VL FIGURE 1-2: AC and DC Test Circuit for Most Non-Inverting Gain Conditions. VDD VDD/2 RN 0.1 µF 1 µF VOUT MCP61X CL VIN RG RL RF VL FIGURE 1-3: AC and DC Test Circuit for Most Inverting Gain Conditions.  2019 Microchip Technology Inc. DS20001613D-page 5 MCP616/7/8/9 NOTES: DS20001613D-page 6  2019 Microchip Technology Inc. MCP616/7/8/9 2.0 TYPICAL PERFORMANCE CURVES Note: The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore outside the warranted range. Input Offset Voltage (µV) FIGURE 2-4: VDD = 5.5V. 18% FIGURE 2-5: VDD = 2.3V. Input Bias Current (nA) Input Bias Current at  2019 Microchip Technology Inc. 10 8 4 6 0.7 0.6 0.5 0.4 0.3 0.2 0.1 -10 -11 -12 -13 -14 -15 -16 -17 -18 -19 -20 -21 0% 0.0 2% -0.1 4% -0.2 6% -0.3 8% -0.4 10% 600 Samples VDD = 5.5V -0.7 12% 20% 18% 16% 14% 12% 10% 8% 6% 4% 2% 0% Input Offset Voltage Drift at -0.5 Input Offset Voltage at 600 Samples VDD = 5.5V FIGURE 2-3: VDD = 5.5V. 10 2% Input Offset Voltage Drift (µV/°C) Percentage of Occurrences 14% -22 Percentage of Occurrences 16% 8 4% Offset Voltage (µV) FIGURE 2-2: VDD = 2.3V. 6 6% 0% 100 80 60 40 20 0 -20 -40 -60 -80 0% 8% 2 2% 10% 0 4% 12% -2 6% 598 Samples VDD = 2.3V TA = -40°C to +85°C -4 8% 14% Input Offset Voltage Drift at -6 10% 16% -8 598 Samples VDD = 2.3V -10 12% Input Offset Voltage at -0.6 14% Input Offset Voltage Drift (µV/°C) Percentage of Occurrences 16% -100 Percentage of Occurrences FIGURE 2-1: VDD = 5.5V. 4 80 100 60 40 0 20 -20 -40 -60 -80 0% 2 2% 0 4% -2 6% -4 8% 598 Samples VDD = 5.5V TA = -40°C to +85°C -6 10% 20% 18% 16% 14% 12% 10% 8% 6% 4% 2% 0% -8 598 Samples VDD = 5.5V -10 12% Percentage of Occurrences 14% -100 Percentage of Occurrences Note: Unless otherwise indicated, VDD = +2.3V to +5.5V, VSS = GND, TA = +25°C, VCM = VDD/2, VOUT  VDD/2, RL = 100 kΩ to VDD/2 and CL = 60 pF. Input Offset Current (nA) FIGURE 2-6: VDD = 5.5V. Input Offset Current at DS20001613D-page 7 MCP616/7/8/9 Note: Unless otherwise indicated, VDD = +2.3V to +5.5V, VSS = GND, TA = 25°C, VCM = VDD/2, VOUT  VDD/2, RL = 100 kΩ to VDD/2 and CL = 60 pF. Input Bias Current (nA) Input Offset Voltage (µV) VDD = 5.5V Representative Part 100 VDD = 5.5V 50 0 VDD = 2.3V -50 -100 -150 -5 0.8 IOS -10 -15 0.4 IB -20 -25 0 25 50 75 100 -50 Ambient Temperature (°C) 0.2 24 22 20 18 16 14 12 10 8 6 4 2 0 115 VDD = 5.5V VDD = 2.3V 25 100 95 CMRR 90 80 -25 0 25 50 75 Ambient Temperature (°C) RL = 5 kŸ -25 0 25 50 75 Ambient Temperature (°C) FIGURE 2-11: Temperature. 9 VDD – VOH VDD = 5.5V 15 10 -50 100 20 5 PSRR 105 Output Voltage Headroom (mV) 30 110 85 FIGURE 2-8: Quiescent Current vs. Ambient Temperature. 35 0.0 100 120 -50 40 -25 0 25 50 75 Ambient Temperature (°C) FIGURE 2-10: Input Bias, Offset Currents vs. Ambient Temperature. CMRR, PSRR (dB) Quiescent Current (µA/Amplifier) FIGURE 2-7: Input Offset Voltage vs. Ambient Temperature. Output Voltage Headroom (mV) 0.6 -25 -50 1.0 Input Offset Current (nA) 0 150 VOL – VSS VDD = 2.3V 8 100 CMRR, PSRR vs. Ambient RL = 25 kŸ VDD – VOH 7 VDD = 5.5V 6 5 4 3 2 VOL – VSS 1 VDD = 2.3V 0 0 -50 -25 0 25 50 75 Ambient Temperature (°C) 100 FIGURE 2-9: Maximum Output Voltage Swing vs. Ambient Temperature at RL = 5 k. DS20001613D-page 8 -50 -25 0 25 50 75 100 Ambient Temperature (°C) FIGURE 2-12: Maximum Output Voltage Swing vs. Ambient Temperature at RL = 25 k.  2019 Microchip Technology Inc. MCP616/7/8/9 100 -25 IOS IB 0.30 0.25 0.20 0.15 0.10 0.05 0.00 -0.05 -0.10 -0.15 -0.20 -0.25 -0.30 FIGURE 2-17: Input Offset Voltage vs. Common-mode Input Voltage. 50 40 30 20 10 0 -10 -20 -30 -40 -50 RL = 25 kŸ VDD = 5.5V VDD = 2.3V 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 Common Mode Input Voltage (V) FIGURE 2-15: Input Bias, Offset Currents vs. Common-mode Input Voltage.  2019 Microchip Technology Inc. Phase Margin (°) Common Mode Input Voltage (V) 5.5 5.0 4.5 4.0 3.5 3.0 2.5 1.5 VDD = 5.5V 1.0 100 Slew Rate vs. Ambient TA = +85°C TA = +25°C TA = -40°C 0.5 30 25 20 15 10 5 0 -5 -10 -15 -20 -25 -30 0.0 Input Bias Current (nA) FIGURE 2-14: Temperature. 0 25 50 75 Ambient Temperature (°C) Input Offset Current (nA) -50 TA = +85°C TA = +25°C TA = -40°C 5.5 VDD = 5.0V VDD = 5.5V 5.0 High-to-Low Transition 100 80 60 40 20 0 -20 -40 -60 -80 -100 4.5 Low-to-High Transition -25 0 25 50 75 Ambient Temperature (°C) 100 90 80 70 60 50 40 30 20 10 0 100 FIGURE 2-16: Gain Bandwidth Product, Phase Margin vs. Ambient Temperature. Input Offset Voltage (µV) 0.10 0.09 0.08 0.07 0.06 0.05 0.04 0.03 0.02 0.01 0.00 2.0 Slew Rate (V/µs) FIGURE 2-13: Output Short Circuit Current vs. Ambient Temperature. -50 4.0 0 25 50 75 Ambient Temperature (°C) 3.5 -25 -0.5 -50 3.0 VDD = 2.3V 0 2.5 | ISC– | 5 2.0 10 PM 1.5 15 1.0 VDD = 5.5V GBWP 0.5 20 200 180 160 140 120 100 80 60 40 20 0 0.0 ISC+ Gain Bandwidth Product (kHz) 25 Input Offset Voltage (μV) Output Short Circuit Current (mA) Note: Unless otherwise indicated, VDD = +2.3V to +5.5V, VSS = GND, TA = 25°C, VCM = VDD/2, VOUT  VDD/2, RL = 100 kΩ to VDD/2 and CL = 60 pF. Output Voltage (V) FIGURE 2-18: Output Voltage. Input Offset Voltage vs. DS20001613D-page 9 MCP616/7/8/9 Note: Unless otherwise indicated, VDD = +2.3V to +5.5V, VSS = GND, TA = 25°C, VCM = VDD/2, VOUT  VDD/2, RL = 100 kΩ to VDD/2 and CL = 60 pF. Output Voltage Headroom (mV) Quiescent Current (µA/Amplifier) 25 20 15 10 TA = +85°C TA = +25°C TA = -40°C 5 0 1,000 VDD = 2.3V 100 VDD – VOH 10 VOL – VSS 1 10µ 0.01 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 Power Supply Voltage (V) DC Open-Loop Gain (dB) 125 125 120 VDD = 5.5V 110 VDD = 2.3V 100 95 Gain Bandwidth Product (kHz) 115 110 100k 100 PM 10k 100k 10 100 Load Resistance () 100 90 80 70 60 50 40 30 20 10 0 1M 1,000 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 FIGURE 2-23: DC Open-Loop Gain vs. Power Supply Voltage. 140 FIGURE 2-21: Gain-Bandwidth Product, Phase Margin vs. Load Resistance. DS20001613D-page 10 1.5 Power Supply Voltage (V) DC Open-Loop Gain vs. GBWP 1k 1 RL = 25 kŸ 120 Channel-to-Channel Seperation (dB) 1k 10k 1 10 Load Resistance () FIGURE 2-20: Load Resistance. 200 180 160 140 120 100 80 60 40 20 0 10m 10 105 90 100 0.1 Phase Margin (°) DC Open-Loop Gain (dB) 130 105 100µ 1m 0.1 1 Output Current Magnitude (A) FIGURE 2-22: Output Voltage Headroom vs. Output Current Magnitude FIGURE 2-19: Quiescent Current vs. Power Supply Voltage. 115 VDD = 5.5V Referred to Input 130 120 110 100 90 80 70 100 1.E+02 1k 10k 1.E+03 1.E+04 Frequency (Hz) 100k 1.E+05 FIGURE 2-24: Channel-to-Channel Separation vs. Frequency (MCP617 and MCP619 only).  2019 Microchip Technology Inc. MCP616/7/8/9 0 120 -30 100 -60 Phase 80 -90 60 -120 40 -150 Gain 20 -180 0 -210 CMRR, PSRR (dB) 140 Open-Loop Phase (°) Open-Loop Gain (dB) Note: Unless otherwise indicated, VDD = +2.3V to +5.5V, VSS = GND, TA = 25°C, VCM = VDD/2, VOUT  VDD/2, RL = 100 kΩ to VDD/2 and CL = 60 pF. -20 -240 0.01 1.E0.1 1.E+ 1 1.E+ 10 1.E+ 100 1.E+ 1k 1.E+ 10k 100k 1M 1.E1.E+ 1.E+ 02 01 00 Frequency 01 02 03 (Hz) 04 05 06 Open-Loop Gain, Phase vs. 10,000 1,000 1,000 ini 100 100 eni FIGURE 2-28: Frequency. 10 10 0.1 1.E+0 1 1.E+0 10 1.E+0 100 1.E+0 1k 1.E+0 10k 1.E01 0 1 2 3 4 Frequency (Hz) FIGURE 2-26: Input Noise Voltage, Current Densities vs. Frequency. CMRR, PSRR vs. VDD = 5.5V VDD = 2.3V 1 0.1 100 1.E+02 1k 10k 1.E+03 1.E+04 Frequency (Hz) 100k 1.E+05 FIGURE 2-29: Maximum Output Voltage Swing vs. Frequency. Gain = -1 Output Voltage (20 mV/div) Output Voltage (20 mV/div) Gain = +1 Time (50 µs/div) FIGURE 2-27: Pulse Response. 10k 1.E+04 10 Maximum Output Voltage Swing (VP-P) 10,000 Input Noise Current Density (fA/Hz) Input Noise Voltage Density (nV/Hz) FIGURE 2-25: Frequency. 120 PSRR+ 110 CMRR 100 90 PSRR80 70 60 50 40 30 20 0.1 1 10 100 1k 1.E-01 1.E+00 1.E+01 1.E+02 1.E+03 Frequency (Hz) Small-Signal, Non-Inverting  2019 Microchip Technology Inc. Time (50 µs/div) FIGURE 2-30: Pulse Response. Small-Signal, Inverting DS20001613D-page 11 MCP616/7/8/9 Note: Unless otherwise indicated, VDD = +2.3V to +5.5V, VSS = GND, TA = 25°C, VCM = VDD/2, VOUT  VDD/2, RL = 100 kΩ to VDD/2 and CL = 60 pF. 5.0 Gain = +1 VDD = 5.0V 4 3 2 1 Gain = -1 VDD = 5.0V 4.5 Output Voltage (V) Output Voltage (V) 5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 0.0 Time (50 µs/div) Time (50 µs/div) 5.0 10 4.5 5 4.0 3.5 3.0 CS VDD = 5.0V Gain = +1 V/V RL = 1 kŸ to VSS 0 -5 -10 VOUT 2.5 2.0 1.5 1.0 -15 -20 Output High-Z Output On Output High-Z 0.5 -25 -30 -35 0.0 FIGURE 2-34: Pulse Response. 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 Internal CS Switch Output (V) Large-Signal, Non-Inverting Chip Select Voltage (V) Output Voltage (V) FIGURE 2-31: Pulse Response. VDD = 5.0V Hysteresis Output On CS swept High-to-Low Gain = +2 V/V VDD = 5.0V 5 4 3 2 VIN VOUT FIGURE 2-35: Chip Select (CS) Internal Hysteresis (MCP618 only). 1.E-02 10m 1.E-03 1m 1.E-04 100µ 1.E-05 10µ 1.E-06 1µ 100n 1.E-07 10n 1.E-08 1n 1.E-09 100p 1.E-10 10p 1.E-11 1p 1.E-12 Input Current Magnitude (A) Input, Output Voltages (V) 6 +125°C +85°C +25°C -40°C -1.0 -0.9 -0.8 -0.7 -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0.0 -1 Time (100 µs/div) FIGURE 2-33: The MCP616/7/8/9 Show No Phase Reversal. DS20001613D-page 12 Output High-Z Chip Select Voltage (V) FIGURE 2-32: Chip Select (CS) to Amplifier Output Response Time (MCP618 only). 0 CS swept Low-to-High 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 -40 Time (5 μs/div) 1 Large-Signal, Inverting Input Voltage (V) FIGURE 2-36: Measured Input Current vs. Input Voltage (below VSS).  2019 Microchip Technology Inc. MCP616/7/8/9 3.0 PIN DESCRIPTIONS Descriptions of the pins are listed in Table 3-1. TABLE 3-1: MCP616 PIN FUNCTION TABLE MCP617 MCP618 MSOP, MSOP, MSOP, PDIP, SOIC PDIP, SOIC PDIP, SOIC MCP619 PDIP, SOIC, TSSOP Symbol Description 6 1 6 1 VOUT, VOUTA Output (op amp A) 2 2 2 2 VIN–, VINA– Inverting Input (op amp A) 3 3 3 3 VIN+, VINA+ Non-inverting Input (op amp A) 7 8 7 4 VDD Positive Power Supply — 5 — 5 VINB+ Non-inverting Input (op amp B) — 6 — 6 VINB– Inverting Input (op amp B) — 7 — 7 VOUTB Output (op amp B) — — — 8 VOUTC Output (op amp B) — — — 9 VINC– Inverting Input (op amp C) — — — 10 VINC+ Non-inverting Input (op amp C) 4 4 4 11 VSS — — — 12 VIND+ Non-inverting Input (op amp D) — — — 13 VIND– Inverting Input (op amp D) — — — 14 VOUTD Output (op amp D) — — 8 — CS Chip Select 1, 5, 8 — 1, 5 — NC No Internal Connection 3.1 Analog Outputs The output pins are low-impedance voltage sources. 3.2 Analog Inputs The non-inverting and inverting inputs are high-impedance PNP inputs with low bias currents. 3.3 Chip Select Digital Input (CS) 3.4 Negative Power Supply Power Supply Pins (VDD, VSS) The positive power supply (VDD) is 2.3V to 5.5V higher than the negative power supply (VSS). For normal operation, the other pins are at voltages between VSS and VDD. Typically, these parts are used in a single-supply (positive) supply configuration. In this case, VSS is connected to ground and VDD is connected to the supply. VDD will need bypass capacitors. This is a CMOS, Schmitt-triggered input that places the MCP618 op amp into a low-power mode of operation.  2019 Microchip Technology Inc. DS20001613D-page 13 MCP616/7/8/9 NOTES: DS20001613D-page 14  2019 Microchip Technology Inc. MCP616/7/8/9 4.0 APPLICATIONS INFORMATION VDD The MCP616/7/8/9 family of op amps is manufactured using Microchip’s state-of-the-art CMOS process, which includes PNP transistors. These op amps are unity-gain stable and suitable for a wide range of general purpose applications. V1 4.1 V2 Rail-to-Rail Inputs 4.1.1 D1 R2 PHASE REVERSAL INPUT VOLTAGE AND CURRENT LIMITS The ESD protection on the inputs can be depicted as shown in Figure 4-1. This structure was chosen to protect the input transistors and to minimize input bias current (IB). The input ESD diodes clamp the inputs when they try to go more than one diode drop below VSS. They also clamp any voltages that go too far above VDD; their breakdown voltage is high enough to allow normal operation and low enough to bypass quick ESD events within the specified limits. VDD Bond Pad R3 VSS – (minimum expected V1) 2 mA VSS – (minimum expected V2) R2 > 2 mA R1 > FIGURE 4-2: Inputs. Input Stage Bond VIN– Pad VSS Bond Pad FIGURE 4-1: Structures. Simplified Analog Input ESD In order to prevent damage and/or improper operation of these op amps, the circuit they are in must limit the currents and voltages at the VIN+ and VIN– pins (see “Absolute Maximum Ratings †” at the beginning of Section 1.0 “Electrical Characteristics”). Figure 4-2 shows the recommended approach to protecting these inputs. The internal ESD diodes prevent the input pins (VIN+ and VIN–) from going too far below ground, and the resistors R1 and R2 limit the possible current drawn out of the input pins. Diodes D1 and D2 prevent the input pins (VIN+ and VIN–) from going too far above VDD, and dump any currents onto VDD. When implemented as shown, resistors R1 and R2 also limit the current through D1 and D2.  2019 Microchip Technology Inc. Protecting the Analog It is also possible to connect the diodes to the left of resistors R1 and R2. In this case, current through the diodes D1 and D2 needs to be limited by some other mechanism. The resistors then serve as in-rush current limiters; the DC current into the input pins (VIN+ and VIN–) should be very small. A significant amount of current can flow out of the inputs when the Common-mode voltage (VCM) is below ground (VSS) (see Figure 2-36). Applications that are high impedance may need to limit the usable voltage range. 4.1.3 VIN+ Bond Pad + MCP61X – R1 The MCP616/7/8/9 op amp is designed to prevent phase reversal when the input pins exceed the supply voltages. Figure 2-36 shows the input voltage exceeding the supply voltage without any phase reversal. 4.1.2 D2 NORMAL OPERATION The inputs of the MCP616/7/8/9 op amps connect to a differential PNP input stage. The Common-mode input voltage range (VCMR) includes ground in single-supply systems (VSS), but does not include VDD. This means that the amplifier input behaves linearly as long as the Common-mode input voltage (VCM) is kept within the specified VCMR limits (VSS to VDD–0.9V at +25°C). 4.2 DC Offsets The MCP616/7/8/9 family of op amps have a PNP input differential pair that gives good DC performance. They have very low input offset voltage (±150 µV, maximum) at TA = +25°C, with a typical bias current of -15 nA (sourced out of the inputs). There must be a DC path to ground (or power supply) from both inputs, or the op amp will not bias properly. The DC resistances seen by the op amp inputs (R1||R2 and R4||R5 in Figure 4-3) need to be equal and less than 100 kΩ, to minimize the total DC offset. DS20001613D-page 15 MCP616/7/8/9 EQUATION 4-1: R1 R2 GN = 1 + R2  R1 V1 VOOS = GN [VOS + IB ((R1 ||R2) – REQ) C3 R3 – MCP61X + – IOS ((R1 ||R2 ) + REQ ) / 2] VCM = VEQ – (IB + IOS /2) REQ VOUT V2 VOUT = VEQ (GN ) – V1 (GN – 1) + VOOS Where: R4 R5 FIGURE 4-3: Example Circuit for Calculating DC Offset. To calculate the DC bias point and DC offset, convert the circuit to its DC equivalent: • • • • • Replace capacitors with open circuits Replace inductors with short circuits Replace AC voltage sources with short circuits Replace AC current sources with open circuits Convert DC sources and resistances into their Thevenin equivalent form The DC equivalent circuit for Figure 4-3 is shown in Figure 4-4. R1 R2 REQ VEQ – MCP61X + VOUT R5 V EQ = V 2  -----------------R4 + R5 R EQ = R 4 || R 5 FIGURE 4-4: Equivalent DC Circuit. Now calculate the nominal DC bias point with offset: DS20001613D-page 16 = op amp’s noise gain (from the non-inverting input to the output) VOOS = circuit’s output offset voltage VOS = op amp’s input offset voltage IB = op amp’s input bias current IOS = op amp’s input offset current VCM = op amp’s Common-mode input voltage Use the worst-case specs and source values to determine the worst-case output voltage range and offset for your design. Make sure the Common-mode input voltage range and output voltage range are not exceeded. 4.3 V1 GN Rail-to-Rail Output There are two specifications that describe the output swing capability of the MCP616/7/8/9 family of op amps. The first specification (Maximum Output Voltage Swing) defines the absolute maximum swing that can be achieved under the specified load conditions. For instance, the output voltage swings to within 15 mV of the negative rail with a 25 k load tied to VDD/2. Figure 2-33 shows how the output voltage is limited when the input goes beyond the linear region of operation. The second specification that describes the output swing capability of these amplifiers is the Linear Output Voltage Range. This specification defines the maximum output swing that can be achieved while the amplifier still operates in its linear region. To verify linear operation in this range, the large-signal DC Open-Loop Gain (AOL) is measured at points inside the supply rails. The measurement must meet the specified AOL conditions in the specification table.  2019 Microchip Technology Inc. MCP616/7/8/9 4.4 Capacitive Loads 4.5 Driving large capacitive loads can cause stability problems for voltage feedback op amps. As the load capacitance increases, the feedback loop’s phase margin decreases and the closed-loop bandwidth is reduced. This produces gain peaking in the frequency response, with overshoot and ringing in the step response. A unity-gain buffer (G = +1) is the most sensitive to capacitive loads, though all gains show the same general behavior. When driving large capacitive loads with these op amps (e.g., > 60 pF when G = +1), a small series resistor at the output (RISO in Figure 4-5) improves the feedback loop’s phase margin (stability) by making the output load resistive at higher frequencies. The bandwidth will be generally lower than the bandwidth with no capacitive load. – VIN RISO VOUT MCP61X + CL FIGURE 4-5: Output Resistor, RISO stabilizes large capacitive loads. Figure 4-6 gives recommended RISO values for different capacitive loads and gains. The x-axis is the normalized load capacitance (CL/GN), where GN is the circuit’s noise gain. For non-inverting gains, GN and the Signal Gain are equal. For inverting gains, GN is 1+|Signal Gain| (e.g., -1 V/V gives GN = +2 V/V). MCP618 Chip Select (CS) The MCP618 is a single op amp with Chip Select (CS). When CS is pulled high, the supply current drops to 50 nA (typical) and flows through the CS pin to VSS. When this happens, the amplifier output is put into a high-impedance state. By pulling CS low, the amplifier is enabled. The CS pin has an internal 5 M (typical) pull-down resistor connected to VSS, so it will go low if the CS pins is left floating. Figure 1-1 shows the output voltage and supply current response to a CS pulse. 4.6 Supply Bypass With this family of operational amplifiers, the power supply pin (VDD for single supply) should have a local bypass capacitor (i.e., 0.01 µF to 0.1 µF) within 2 mm for good high-frequency performance. It may use a bulk capacitor (i.e., 1 µF or larger) within 100 mm to provide large, slow currents. This bulk capacitor is not required and can be shared with other analog parts. 4.7 Unused Op Amps An unused op amp in a quad package (MCP619) should be configured as shown in Figure 4-7. These circuits prevent the output from toggling and causing crosstalk. Circuits A sets the op amp at its minimum noise gain. The resistor divider produces any desired reference voltage within the output voltage range of the op amp; the op amp buffers that reference voltage. Circuit B uses the minimum number of components and operates as a comparator, but it may draw more current. ¼ MCP619 (A) Recommended RISO (Ÿ) 10,000 10k ¼ MCP619 (B) VDD VDD VDD R1 + 1k 1,000 GN = +1 GN t +2 100 100 10n 10p 100p 1n 1.E-11 1.E-10 1.E-09 1.E-08 Normalized Load Capacitance; C L/GN (F) FIGURE 4-6: Recommended RISO Values for Capacitive Loads. R2 – VREF + – R2 V REF = V DD  ------------------R1 + R2 FIGURE 4-7: Unused Op Amps. After selecting RISO for your circuit, double-check the resulting frequency response peaking and step response overshoot. Modify RISO’s value until the response is reasonable. Bench evaluation and simulations with the MCP616/7/8/9 SPICE macro model are helpful.  2019 Microchip Technology Inc. DS20001613D-page 17 MCP616/7/8/9 4.8 PCB Surface Leakage 4.9 In applications where low input bias current is critical, Printed Circuit Board (PCB) surface leakage effects need to be considered. Surface leakage is caused by humidity, dust or other contamination on the board. Under low humidity conditions, a typical resistance between nearby traces is 1012. A 5V difference would cause 5 pA of current to flow, which is greater than the MCP616/7/8/9 family’s bias current at 25°C (1 pA, typical). The easiest way to reduce surface leakage is to use a guard ring around sensitive pins (or traces). The guard ring is biased at the same voltage as the sensitive pin. An example is shown below in Figure 4-8. Guard Ring VIN– VIN+ 4.9.1 Application Circuits HIGH GAIN PRE-AMPLIFIER The MCP616/7/8/9 op amps are well suited to amplifying small signals produced by low-impedance sources/sensors. The low offset voltage, low offset current and low noise fit well in this role. Figure 4-9 shows a typical pre-amplifier connected to a low-impedance source (VS and RS). VS RS + 10 k RG VDD/2 VSS 11.0 k FIGURE 4-9: FIGURE 4-8: for Inverting Gain. 1. 2. Example Guard Ring Layout Non-inverting Gain and Unity Gain Buffer: a) Connect the non-inverting pin (VIN+) to the input with a wire that does not touch the PCB surface. b) Connect the guard ring to the inverting input pin (VIN–). This biases the guard ring to the Common-mode input voltage. Inverting Gain and Transimpedance gain (convert current to voltage, such as photo detectors) amplifiers: a) Connect the guard ring to the non-inverting input pin (VIN+). This biases the guard ring to the same reference voltage as the op amp (e.g., VDD/2 or ground). b) Connect the inverting pin (VIN–) to the input with a wire that does not touch the PCB surface. MCP616 – RF VOUT 100 k High Gain Pre-amplifier. For the best noise and offset performance, the source resistance RS needs to be less than 15 k. The DC resistances at the inputs are equal to minimize the offset voltage caused by the input bias currents (Section 4.2 “DC Offsets”). In this circuit, the DC gain is 10 V/V, which will give a typical bandwidth of 19 kHz. 4.9.2 TWO OP AMP INSTRUMENTATION AMPLIFIER The two-op amp instrumentation amplifier shown in Figure 4-10 serves the function of taking the difference of two input voltages, level-shifting it and gaining it to the output. This configuration is best suited for higher gains (i.e., gain > 3 V/V). The reference voltage (VREF) is typically at mid-supply (VDD/2) in a single-supply environment. 2R  R  VOUT =  V 1 – V 2  1 + ------1 + ---------1-  + V REF R  2 RG  RG R1 R2 R2 R1 VREF VOUT – V2 + – ½ MCP617 + ½ MCP617 V1 FIGURE 4-10: Two-Op Amp Instrumentation Amplifier. The key specifications that make the MCP616/7/8/9 family appropriate for this application circuit are low input bias current, low offset voltage and high Common-mode rejection. DS20001613D-page 18  2019 Microchip Technology Inc. MCP616/7/8/9 4.9.3 THREE OP AMP INSTRUMENTATION AMPLIFIER A classic, three-op amp instrumentation amplifier is illustrated in Figure 4-11. The two-input op amps provide differential signal gain and a Common-mode gain of +1. The output op amp is a difference amplifier, which converts its input signal from differential to a single-ended output; it rejects Common-mode signals at its input. The gain of this circuit is simply adjusted with one resistor (RG). The reference voltage (VREF) is typically referenced to mid-supply (VDD/2) in single-supply applications. 2R   R 4  VOUT =  V 1 – V 2  1 + ---------2   ------ + V REF R G   R 3  V2 + R4 The MCP606 is configured as a unity-gain buffer. It isolates the MCP616’s output from the load, increasing the high gain stage’s precision. Since the MCP606 has a higher output current, and the two amplifiers are housed in separate packages, there is minimal change in the MCP616’s offset voltage due to loading effect. VOUT = V IN 1 + R 2  R 1  VIN + R1 VOUT – RG + R2 + In Figure 4-12, the MCP616 op amp, R1 and R2 provide a high gain to the input signal (VIN). The MCP616’s low offset voltage makes this an accurate circuit. R3 MCP616 + – – R3 R2 V1 PRECISION GAIN WITH GOOD LOAD ISOLATION ½ MCP617 – – 4.9.4 FIGURE 4-12: Load Isolation. MCP606 VOUT R2 Precision Gain with Good MCP616 R4 VREF ½ MCP617 FIGURE 4-11: Three-Op Amp Instrumentation Amplifier.  2019 Microchip Technology Inc. DS20001613D-page 19 MCP616/7/8/9 NOTES: DS20001613D-page 20  2019 Microchip Technology Inc. MCP616/7/8/9 5.0 DESIGN AIDS Microchip provides the basic design tools needed for the MCP616/7/8/9 family of op amps. 5.1 SPICE Macro Model The latest SPICE macro model for the MCP616/7/8/9 op amps is available on the Microchip website at www.microchip.com. This model is intended to be an initial design tool that works well in the op amp’s linear region of operation over the temperature range. See the model file for information on its capabilities. Bench testing is a very important part of any design and cannot be replaced with simulations. Also, simulation results using this macro model need to be validated by comparing them to the data sheet specifications and characteristic curves. 5.2 Mindi™ Circuit Designer & Simulator Microchip’s Mindi™ Circuit Designer & Simulator aids in the design of various circuits useful for active filter, amplifier and power-management applications. It is a free online circuit designer & simulator available from the Microchip website at www.microchip.com/mindi. This interactive circuit designer & simulator enables designers to quickly generate circuit diagrams, simulate circuits. Circuits developed using the Mindi Circuit Designer & Simulator can be downloaded to a personal computer or workstation. 5.3 Microchip Advanced Part Selector (MAPS) MAPS is a software tool that helps semiconductor professionals efficiently identify Microchip devices that fit a particular design requirement. Available at no cost from the Microchip website at www.microchip.com/ maps, the MAPS is an overall selection tool for Microchip’s product portfolio that includes Analog, Memory, MCUs and DSCs. Using this tool you can define a filter to sort features for a parametric search of devices and export side-by-side technical comparison reports. Helpful links are also provided for Datasheets, Purchase, and Sampling of Microchip parts.  2019 Microchip Technology Inc. 5.4 Analog Demonstration and Evaluation Boards Microchip offers a broad spectrum of Analog Demonstration and Evaluation Boards that are designed to help you achieve faster time to market. For a complete listing of these boards and their corresponding user’s guides and technical information, visit the Microchip website at www.microchip.com/analogtools. Two of our boards that are especially useful are: • P/N SOIC8EV: 8-Pin SOIC/MSOP/TSSOP/DIP Evaluation Board • P/N SOIC14EV: 14-Pin SOIC/TSSOP/DIP Evaluation Board 5.5 Application Notes The following Microchip Application Notes are available on the Microchip website at www.microchip. com/appnotes and are recommended as supplemental reference resources. ADN003: “Select the Right Operational Amplifier for your Filtering Circuits,” DS21821 AN722: “Operational Amplifier Topologies and DC Specifications,” DS00722 AN723: “Operational Amplifier AC Specifications and Applications,” DS00723 AN884: “Driving Capacitive Loads With Op Amps,” DS00884 AN990: “Analog Sensor Conditioning Circuits – An Overview,” DS00990 These application notes and others are listed in the design guide: “Signal Chain Design Guide,” DS21825 DS20001613D-page 21 MCP616/7/8/9 NOTES: DS20001613D-page 22  2019 Microchip Technology Inc. MCP616/7/8/9 6.0 PACKAGING INFORMATION 6.1 Package Marking Information Example: 8-Lead MSOP 616I 931256 8-Lead PDIP (300 mil) XXXXXXXX XXXXXNNN YYWW MCP616 I/P256 1931 8-Lead SOIC (150 mil) XXXXXXXX XXXXYYWW NNN Legend: XX...X Y YY WW NNN e3 * Note: Examples: OR MCP616 I/P e^^3 256 1931 Examples: MCP616 I/SN1931 256 OR MCP616I e3 1931 SN^^ 256 Customer-specific information Year code (last digit of calendar year) Year code (last 2 digits of calendar year) Week code (week of January 1 is week ‘01’) Alphanumeric traceability code Pb-free JEDEC designator for Matte Tin (Sn) This package is Pb-free. The Pb-free JEDEC designator ( e3 ) can be found on the outer packaging for this package. In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information.  2019 Microchip Technology Inc. DS20001613D-page 23 MCP616/7/8/9 Package Marking Information (Continued) 14-Lead PDIP (300 mil) (MCP619) XXXXXXXXXXXXXX XXXXXXXXXXXXXX YYWWNNN 14-Lead SOIC (150 mil) (MCP619) Examples: MCP619-I/P XXXXXXXXXXXXXX 1931256 Examples: XXXXXXXXXX XXXXXXXXXX YYWWNNN 14-Lead TSSOP (MCP619) XXXXXXXX YYWW NNN DS20001613D-page 24 OR MCP619 e3 I/P^^ 1931256 MCP619ISL XXXXXXXXXX 1931256 OR MCP619 e3 I/SL ^^ 1931256 Example: 619IST 1931 256  2019 Microchip Technology Inc. MCP616/7/8/9 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2019 Microchip Technology Inc. DS20001613D-page 25 MCP616/7/8/9 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS20001613D-page 26  2019 Microchip Technology Inc. MCP616/7/8/9 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2019 Microchip Technology Inc. DS20001613D-page 27 MCP616/7/8/9 8-Lead Plastic Dual In-Line (P) - 300 mil Body [PDIP] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging D A N B E1 NOTE 1 1 2 TOP VIEW E C A2 A PLANE L c A1 e eB 8X b1 8X b .010 C SIDE VIEW END VIEW Microchip Technology Drawing No. C04-018-P Rev E Sheet 1 of 2 DS20001613D-page 28  2019 Microchip Technology Inc. MCP616/7/8/9 8-Lead Plastic Dual In-Line (P) - 300 mil Body [PDIP] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging ALTERNATE LEAD DESIGN (NOTE 5) DATUM A DATUM A b b e 2 e 2 e e Units Dimension Limits Number of Pins N e Pitch Top to Seating Plane A Molded Package Thickness A2 Base to Seating Plane A1 Shoulder to Shoulder Width E Molded Package Width E1 Overall Length D Tip to Seating Plane L c Lead Thickness b1 Upper Lead Width b Lower Lead Width eB Overall Row Spacing § MIN .115 .015 .290 .240 .348 .115 .008 .040 .014 - INCHES NOM 8 .100 BSC .130 .310 .250 .365 .130 .010 .060 .018 - MAX .210 .195 .325 .280 .400 .150 .015 .070 .022 .430 Notes: 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. § Significant Characteristic 3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" per side. 4. Dimensioning and tolerancing per ASME Y14.5M BSC: Basic Dimension. Theoretically exact value shown without tolerances. 5. Lead design above seating plane may vary, based on assembly vendor. Microchip Technology Drawing No. C04-018-P Rev E Sheet 2 of 2  2019 Microchip Technology Inc. DS20001613D-page 29 MCP616/7/8/9 8-Lead Plastic Small Outline (SN) - Narrow, 3.90 mm (.150 In.) Body [SOIC] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging 2X 0.10 C A–B D A D NOTE 5 N E 2 E1 2 E1 E NOTE 1 2 1 e B NX b 0.25 C A–B D NOTE 5 TOP VIEW 0.10 C C A A2 SEATING PLANE 8X A1 SIDE VIEW 0.10 C h R0.13 h R0.13 H SEE VIEW C VIEW A–A 0.23 L (L1) VIEW C Microchip Technology Drawing No. C04-057-SN Rev E Sheet 1 of 2 DS20001613D-page 30  2019 Microchip Technology Inc. MCP616/7/8/9 8-Lead Plastic Small Outline (SN) - Narrow, 3.90 mm (.150 In.) Body [SOIC] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging Units Dimension Limits Number of Pins N e Pitch Overall Height A Molded Package Thickness A2 § Standoff A1 Overall Width E Molded Package Width E1 Overall Length D Chamfer (Optional) h Foot Length L L1 Footprint Foot Angle c Lead Thickness b Lead Width Mold Draft Angle Top Mold Draft Angle Bottom MIN 1.25 0.10 0.25 0.40 0° 0.17 0.31 5° 5° MILLIMETERS NOM 8 1.27 BSC 6.00 BSC 3.90 BSC 4.90 BSC 1.04 REF - MAX 1.75 0.25 0.50 1.27 8° 0.25 0.51 15° 15° Notes: 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. § Significant Characteristic 3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.15mm per side. 4. Dimensioning and tolerancing per ASME Y14.5M BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only. 5. Datums A & B to be determined at Datum H. Microchip Technology Drawing No. C04-057-SN Rev E Sheet 2 of 2  2019 Microchip Technology Inc. DS20001613D-page 31 MCP616/7/8/9 8-Lead Plastic Small Outline (SN) - Narrow, 3.90 mm Body [SOIC] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging SILK SCREEN C Y1 X1 E RECOMMENDED LAND PATTERN Units Dimension Limits E Contact Pitch Contact Pad Spacing C Contact Pad Width (X8) X1 Contact Pad Length (X8) Y1 MIN MILLIMETERS NOM 1.27 BSC 5.40 MAX 0.60 1.55 Notes: 1. Dimensioning and tolerancing per ASME Y14.5M BSC: Basic Dimension. Theoretically exact value shown without tolerances. Microchip Technology Drawing C04-2057-SN Rev E DS20001613D-page 32  2019 Microchip Technology Inc. MCP616/7/8/9                 .  #/  #  $#/#  #,00#0#/ N NOTE 1 E1 1 3 2 D E A2 A L A1 c b1 b e eB 1 ! 5 3  234" $23 3 36$ $(7 '   -# ( 8 8 % $  /-/ ( *  % 9* +  ( %* 8 8     :  " 9%  %  * $  /:  " '% *% ;% 65 ! < *