MCP6274E-SL

MCP6271/1R/2/3/4/5 170 µA, 2 MHz Rail-to-Rail Op Amp Features Description • • • • • • • The Microchip Technology Inc. MCP6271/1R/2/3/4/5 family of operational amplifiers (op amps) provide wide bandwidth for the current. This family has a 2 MHz Gain Bandwidth Product (GBWP) and a 65° Phase Margin. This family also operates from a single supply voltage as low as 2.0V, while drawing 170 µA (typical) quiescent current. The MCP6271/1R/2/3/4/5 supports rail-to-rail input and output swing, with a Commonmode input voltage range of VDD + 300 mV to VSS – 300 mV. This family of op amps is designed with Microchip’s advanced CMOS process. Gain Bandwidth Product: 2 MHz (typical) Supply Current: IQ = 170 µA (typical) Supply Voltage: 2.0V to 6.0V Rail-to-Rail Input/Output Extended Temperature Range: –40°C to +125°C Available in Single, Dual and Quad Packages Parts with Chip Select (CS) - Single (MCP6273) - Dual (MCP6275) Applications • • • • • • The MCP6275 has a Chip Select input (CS) for dual op amps in an 8-pin package and is manufactured by cascading two op amps (the output of op amp A connected to the non-inverting input of op amp B). The CS input puts the device in low power mode. Automotive Portable Equipment Photodiode Amplifier Analog Filters Notebooks and PDAs Battery Powered Systems The MCP6271/1R/2/3/4/5 family operates over the Extended Temperature Range of –40°C to +125°C, with a power supply range of 2.0V to 6.0V. Available Tools • • • • • • SPICE Macro Models FilterLab® Software Mindi™ Circuit Designer & Simulator MAPS (Microchip Advanced Part Selector) Analog Demonstration and Evaluation Boards Application Notes Package Types MCP6271 PDIP, SOIC, MSOP NC 1 VIN– 2 VIN+ 3 MCP6271 SOT-23-5 VOUT 1 8 NC – + 7 VDD VSS 2 6 VOUT VIN+ 3 NC 1 VSS 4 VOUT 1 VDD 2 + – 4 VIN– 5 VSS 8 CS – + 7 VDD VOUTA 1 VINA– 2 + – VIN+ 3 MCP6272 PDIP, SOIC, MSOP 4 VIN– 8 VDD –+ 7 VOUTB –+ VINA+ 3 MCP6273 SOT-23-6 VOUT 1 VSS 2 6 VOUT VIN+ 3 5 NC MCP6274 PDIP, SOIC, TSSOP 6 VDD VOUTA 1 +– 5 CS VINA– 2 4 VIN– VINA+ 3 11 VSS VDD 4 VINB+ 5 VINB– 6 VOUTB 7  2019 Microchip Technology Inc. MCP6275 PDIP, SOIC, MSOP 14 VOUTD VOUTA/VINB+ 1 – + + – 13 VIND– 12 VIND+ 6 VINB– 5 VINB+ VSS 4 MCP6273 PDIP, SOIC, MSOP VIN– 2 5 VDD 5 NC VSS 4 VIN+ 3 MCP6271R SOT-23-5 VINA– 2 VINA+ 3 VSS 4 8 VDD –+ 7 VOUTB +– 6 VINB– 5 CS 10 VINC+ –+ +– 9 VINC– 8 VOUTC DS20001810G-page 1 MCP6271/1R/2/3/4/5 NOTES: DS20001810G-page 2  2019 Microchip Technology Inc. MCP6271/1R/2/3/4/5 1.0 ELECTRICAL CHARACTERISTICS VDD – VSS ........................................................................7.0V † Notice: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. Current at Input Pins ....................................................±2 mA †† See Section 4.1.2 “Input Voltage and Current Limits”. Absolute Maximum Ratings † Analog Inputs (VIN+ and VIN–) †† .. VSS – 1.0V to VDD + 1.0V All other Inputs and Outputs .......... VSS – 0.3V to VDD + 0.3V Difference Input Voltage ...................................... |VDD – VSS| Output Short Circuit Current ................................ Continuous Current at Output and Supply Pins ............................±30 mA Storage Temperature ................................... –65°C to +150°C Junction Temperature (TJ) .........................................+150°C ESD Protection On All Pins (HBM/MM)   4 kV/400V DC ELECTRICAL SPECIFICATIONS Electrical Characteristics: Unless otherwise indicated, TA = +25°C, VDD = +2.0V to +5.5V, VSS = GND, VCM = VDD/2, VOUT  VDD/2, VL = VDD/2, RL = 10 kto VL and CS is tied low. (Refer to Figure 1-2 and Figure 1-3). Parameters Sym Min Typ Max Units Conditions Input Offset Voltage VOS –3.0 — +3.0 mV VCM = VSS Input Offset Voltage (Extended Temperature) VOS –5.0 — +5.0 mV TA = –40°C to +125°C, VCM = VSS Input Offset (Note 1) Input Offset Temperature Drift VOS/TA — ±1.7 — Power Supply Rejection Ratio PSRR 70 90 — IB — ±1.0 — pA Note 2 IB — 50 200 pA TA= +85°C (Note 2) IB — 2 5 nA TA= +125°C (Note 2) IOS — ±1.0 — pA Note 3 13 µV/°C TA = –40°C to +125°C, VCM = VSS dB VCM = VSS Input Bias Current and Impedance Input Bias Current At Temperature At Temperature Input Offset Current Common-mode Input Impedance ZCM — 10 ||6 — ||pF Note 3 Differential Input Impedance ZDIFF — 1013||3 — ||pF Note 3 Common-mode Input Voltage Range VCMR VSS  0.15 — VDD + 0.15 VCMR VSS  0.30 — VDD + 0.30 V VDD = 5.5V (Note 5) Common-mode Rejection Ratio CMRR 70 85 — dB VCM = –0.3V to 2.5V, VDD = 5V (Note 6) Common-mode Rejection Ratio CMRR 65 80 — dB VCM = –0.3V to 5.3V, VDD = 5V (Note 6) AOL 90 110 — dB VOUT = 0.2V to VDD – 0.2V, VCM = VSS (Note 1) Common-mode (Note 4) V VDD = 2.0V (Note 5) Open-Loop Gain DC Open-Loop Gain (Large Signal) Note 1: 2: 3: 4: 5: 6: 7: The MCP6275’s VCM for op amp B (pins VOUTA/VINB+ and VINB–) is VSS + 100 mV. The current at the MCP6275’s VINB– pin is specified by IB only. This specification does not apply to the MCP6275’s VOUTA/VINB+ pin. The MCP6275’s VINB– pin (op amp B) has a Common-mode input voltage range (VCMR) of VSS + 100 mV to VDD – 100 mV. CMRR is not measured for op amp B of the MCP6275. The MCP6275’s VOUTA/VINB+ pin (op amp B) has a voltage range specified by VOH and VOL. Set by design and characterization. Does not apply to op amp B of the MCP6275. All parts with date codes November 2007 and later have been screened to ensure operation at VDD = 6.0V. However, the other minimum and maximum specifications are measured at 2.0V and 5.5V.  2019 Microchip Technology Inc. DS20001810G-page 3 MCP6271/1R/2/3/4/5 DC ELECTRICAL SPECIFICATIONS (CONTINUED) Electrical Characteristics: Unless otherwise indicated, TA = +25°C, VDD = +2.0V to +5.5V, VSS = GND, VCM = VDD/2, VOUT  VDD/2, VL = VDD/2, RL = 10 kto VL and CS is tied low. (Refer to Figure 1-2 and Figure 1-3). Parameters Sym Min Typ Max Units VOL, VOH VSS + 15 — VDD  15 mV ISC — ±25 — mA Conditions Output Maximum Output Voltage Swing Output Short Circuit Current 0.5V input overdrive (Note 4) Power Supply Supply Voltage Quiescent Current per Amplifier Note 1: 2: 3: 4: VDD 2.0 — 6.0 V IQ 100 170 240 µA IO = 0 The MCP6275’s VCM for op amp B (pins VOUTA/VINB+ and VINB–) is VSS + 100 mV. The current at the MCP6275’s VINB– pin is specified by IB only. This specification does not apply to the MCP6275’s VOUTA/VINB+ pin. The MCP6275’s VINB– pin (op amp B) has a Common-mode input voltage range (VCMR) of VSS + 100 mV to VDD – 100 mV. CMRR is not measured for op amp B of the MCP6275. The MCP6275’s VOUTA/VINB+ pin (op amp B) has a voltage range specified by VOH and VOL. Set by design and characterization. Does not apply to op amp B of the MCP6275. All parts with date codes November 2007 and later have been screened to ensure operation at VDD = 6.0V. However, the other minimum and maximum specifications are measured at 2.0V and 5.5V. 5: 6: 7: AC ELECTRICAL SPECIFICATIONS Electrical Characteristics: Unless otherwise indicated, TA = +25°C, VDD = +2.0V to +5.5V, VSS = GND, VCM = VDD/2, VOUT  VDD/2, VL = VDD/2, RL = 10 kto VL, CL = 60 pF and CS is tied low. (Refer to Figure 1-2 and Figure 1-3). Parameters Sym Min Typ Max Units Conditions GBWP — 2.0 — MHz Phase Margin PM — 65 — ° Slew Rate SR — 0.9 — V/µs Input Noise Voltage Eni — 4.6 — µVP-P Input Noise Voltage Density eni — 20 — nV/Hz f = 1 kHz Input Noise Current Density ini — 3 — fA/Hz f = 1 kHz AC Response Gain Bandwidth Product G = +1 V/V Noise CS VIL VIH tOFF tON VOUT High-Z High-Z -0.7 µA (typical) ISS 0.7 µA (typical) ICS f = 0.1 Hz to 10 Hz -170 µA (typical) 10 nA (typical) -0.7 µA (typical) 0.7 µA (typical) FIGURE 1-1: Timing Diagram for the Chip Select (CS) pin on the MCP6273 and MCP6275. DS20001810G-page 4  2019 Microchip Technology Inc. MCP6271/1R/2/3/4/5 TEMPERATURE SPECIFICATIONS Electrical Characteristics: Unless otherwise indicated, VDD = +2.0V to +5.5V and VSS = GND. Parameters Sym Min Typ Max Units Specified Temperature Range TA –40 — +125 °C Operating Temperature Range TA –40 — +125 °C Storage Temperature Range TA –65 — +150 °C Thermal Resistance, 5L-SOT-23 JA — 256 — °C/W Thermal Resistance, 6L-SOT-23 JA — 230 — °C/W Thermal Resistance, 8L-PDIP JA — 85 — °C/W Thermal Resistance, 8L-SOIC JA — 163 — °C/W Thermal Resistance, 8L-MSOP JA — 206 — °C/W Thermal Resistance, 14L-PDIP JA — 70 — °C/W Thermal Resistance, 14L-SOIC JA — 120 — °C/W Thermal Resistance, 14L-TSSOP JA — 100 — °C/W Conditions Temperature Ranges Note Thermal Package Resistances The Junction Temperature (TJ) must not exceed the Absolute Maximum specification of +150°C. Note: MCP6273/MCP6275 CHIP SELECT SPECIFICATIONS Electrical Characteristics: Unless otherwise indicated, TA = +25°C, VDD = +2.0V to +5.5V, VSS = GND, VCM = VDD/2, VOUT  VDD/2, VL = VDD/2, RL = 10 kto VDD/2, CL = 60 pF and CS is tied low. Parameters Sym Min Typ Max Units Conditions CS Logic Threshold, Low VIL VSS — 0.2VDD V CS Input Current, Low ICSL — 0.01 — µA CS Logic Threshold, High VIH 0.8VDD — VDD V CS Input Current, High ICSH — 0.7 2 µA CS = VDD GND Current per Amplifier ISS — –0.7 — µA CS = VDD Amplifier Output Leakage — — 0.01 — µA CS = VDD CS Low to Valid Amplifier Output, Turn on Time tON — 4 10 µs CS Low  0.2 VDD, G = +1 V/V, VIN = VDD/2, VOUT = 0.9 VDD/2, VDD = 5.0V CS High to Amplifier Output High-Z tOFF — 0.01 — µs CS High  0.8 VDD, G = +1 V/V, VIN = VDD/2, VOUT = 0.1 VDD/2 VHYST — 0.6 — V VDD = 5V CS Low Specifications CS = VSS CS High Specifications Dynamic Specifications (Note 1) Hysteresis Note 1: The input condition (VIN) specified applies to both op amp A and B of the MCP6275. The dynamic specification is tested at the output of op amp B (VOUTB).  2019 Microchip Technology Inc. DS20001810G-page 5 MCP6271/1R/2/3/4/5 1.1 Test Circuits The test circuits used for the DC and AC tests are shown in Figure 1-2 and Figure 1-3. The bypass capacitors are laid out according to the rules discussed in Section 4.7 “Supply Bypass”. VDD VIN RN 0.1 µF 1 µF VOUT MCP627X CL VDD/2 RG RL RF VL FIGURE 1-2: AC and DC Test Circuit for Most Non-Inverting Gain Conditions. VDD VDD/2 RN 0.1 µF 1 µF VOUT MCP627X CL VIN RG RL RF VL FIGURE 1-3: AC and DC Test Circuit for Most Inverting Gain Conditions. DS20001810G-page 6  2019 Microchip Technology Inc. MCP6271/1R/2/3/4/5 2.0 TYPICAL PERFORMANCE CURVES Note: The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore outside the warranted range. Note: Unless otherwise indicated, TA = +25°C, VDD = +2.0V to +5.5V, VSS = GND, VCM = VDD/2, VOUT  VDD/2, 14% 2% Input Offset Voltage (mV) FIGURE 2-3: Input Offset Voltage vs. Common-mode Input Voltage, with VDD = 2.0V.  2019 Microchip Technology Inc. 10 8 3.0 2.6 2.4 6.0 2.4 2.2 2.0 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0.0 -0.2 -0.4 Common Mode Input Voltage (V) TA = +125°C 100 50 TA = +85°C TA = +25°C TA = -40°C 0 -50 -100 5.0 -50 -100 150 4.5 0 200 4.0 TA = +125°C TA = +85°C TA = +25°C TA = -40°C VDD = 5.5V 250 3.5 150 Input Bias Current at 3.0 200 50 2.8 300 VDD = 2.0V 100 5.5 FIGURE 2-5: TA = +125°C. Input Bias Current at 2.5 250 Input Bias Current (nA) 2.0 Input Offset Voltage (µV) 300 90 100 1.5 FIGURE 2-2: TA = +85°C. 30 40 50 60 70 80 Input Bias Current (pA) 1.0 20 0.5 10 -0.5 0 2.2 0% 2.0 4% 1.8 8% 1.6 12% 1.4 16% 1.2 20% 422 Samples TA = +125°C 1.0 24% 22% 20% 18% 16% 14% 12% 10% 8% 6% 4% 2% 0% Input Offset Voltage Drift. 0.8 422 Samples TA = 85°C Percentage of Occurrences 28% FIGURE 2-4: Input Offset Voltage. Input Offset Voltage (µV) Percentage of Occurrences 32% Input Offset Voltage Drift (µV/°C) 0.6 FIGURE 2-1: 6 0% 4 3.0 2.4 1.8 1.2 0.6 0.0 -0.6 -1.2 -1.8 -2.4 0% 4% 2 2% 0 4% 6% -2 6% 8% -4 8% -6 10% 10% -8 12% 832 Samples VCM = VSS TA = -40°C to +125°C 12% -10 14% Percentage of Occurrences 832 Samples VCM = VSS 16% 0.0 18% -3.0 Percentage of Occurrences VL = VDD/2, RL = 10 k to VL, CL = 60 pF and CS is tied low. Common Mode Input Voltage (V) FIGURE 2-6: Input Offset Voltage vs. Common-mode Input Voltage, with VDD = 5.5V. DS20001810G-page 7 MCP6271/1R/2/3/4/5 Note: Unless otherwise indicated, TA = +25°C, VDD = +2.0V to +5.5V, VSS = GND, VCM = VDD/2, VOUT  VDD/2, Common Mode Input Voltage Range Limit (V) 0.00 -0.05 -0.10 -0.15 -0.20 -0.25 -0.30 -0.35 -0.40 -0.45 -0.50 Typical lower (VCM – VSS) limit VDD = 2.0V VDD = 5.5V -50 -25 0 25 50 75 100 Ambient Temperature (°C) FIGURE 2-7: Common-mode Input Voltage Range Lower Limit vs. Temperature. Input Offset Voltage (µV) 300 VCM = VSS Representative Part 250 200 150 100 50 0 VDD = 2.0V 0.50 0.45 0.40 0.35 0.30 0.25 0.20 0.15 0.10 0.05 0.00 125 VDD = 5.5V -50 -100 Input Offset Voltage vs. 0 25 50 75 100 Ambient Temperature (°C) 125 1,000 VCM = VDD VDD = 5.5V Input Bias Current 100 10 Input Offset Current 1 45 55 65 75 85 95 105 115 125 Ambient Temperature (°C) FIGURE 2-11: Input Bias, Input Offset Currents vs. Temperature. CMRR 90 80 70 PSRR– PSRR+ 40 30 20 1 10 1.E+02 100 1.E+03 1k 10k 1.E+05 100k 1.E+06 1M 1.E+00 1.E+01 1.E+04 Frequency (Hz) FIGURE 2-9: Frequency. DS20001810G-page 8 CMRR, PSRR vs. PSRR, CMRR (dB) CMRR, PSRR (dB) -25 120 100 50 Typical upper (VCM – VDD) limit 10,000 110 60 VDD = 2.0V FIGURE 2-10: Common-mode Input Voltage Range Upper Limit vs. Temperature. 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 Output Voltage (V) FIGURE 2-8: Output Voltage. VDD = 5.5V -50 Input Bias, Offset Currents (pA) Common Mode Input Voltage Range Limit (V) VL = VDD/2, RL = 10 k to VL, CL = 60 pF and CS is tied low. 110 100 CMRR 90 PSRR (VCM = VSS) 80 70 60 -50 -25 0 25 50 75 100 125 Ambient Temperature (°C) FIGURE 2-12: Temperature. CMRR, PSRR vs.  2019 Microchip Technology Inc. MCP6271/1R/2/3/4/5 Note: Unless otherwise indicated, TA = +25°C, VDD = +2.0V to +5.5V, VSS = GND, VCM = VDD/2, VOUT  VDD/2, VL = VDD/2, RL = 10 k to VL, CL = 60 pF and CS is tied low. 2.5 Input Bias, Offset Currents (nA) 45 Input Bias Current 35 25 15 5 Input Offset Current -5 TA = 85°C VDD = 5.5V -15 -25 2.0 1.5 0.5 0.0 -1.0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 Common Mode Input Voltage (V) FIGURE 2-16: Input Bias, Offset Currents vs. Common-mode Input Voltage, with TA = +125°C. Ouput Voltage Headroom (mV) Quiescent Current (µA/amplifier) Input Offset Current 1000 250 200 150 TA = +125°C TA = +85°C TA = +25°C TA = -40°C 100 50 0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 Power Supply Voltage (V) Quiescent Current vs. 0 100 -30 Gain 80 60 -60 -90 Phase 40 -120 20 -150 0 -180 FIGURE 2-15: Frequency. 1.E+08 1.E+07 1.E+06 1.E+05 1.E+04 1.E+03 1.E+02 1 1.E+01 0.1 1.E+00 -210 1.E-01 -20 10 100 1k 10k 100k 1M 10M 100M Frequency (Hz) Open-Loop Gain, Phase vs.  2019 Microchip Technology Inc. 10 VOL – VSS VDD – VOH 1 0.01 0.1 1 Output Current Magnitude (mA) 3.0 Gain Bandwidth Product (MHz) 120 100 10 FIGURE 2-17: Output Voltage Headroom vs. Output Current Magnitude. Open-Loop Phase (°) FIGURE 2-14: Supply Voltage. Open-Loop Gain (dB) TA = 125°C VDD = 5.5V -0.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 Common Mode Input Voltage (V) FIGURE 2-13: Input Bias, Offset Currents vs. Common-mode Input Voltage, with TA = +85°C. Input Bias Current 1.0 80 2.5 75 GBWP, VDD = 5.5V VDD = 2.0V 2.0 1.5 70 65 1.0 PM, VDD = 5.5V VDD = 2.0V 0.5 0.0 -50 -25 0 25 50 75 100 Ambient Temperature (°C) 60 Phase Margin (°) Input Bias, Offset Currents (pA) 55 55 50 125 FIGURE 2-18: Gain Bandwidth Product, Phase Margin vs. Temperature. DS20001810G-page 9 MCP6271/1R/2/3/4/5 Note: Unless otherwise indicated, TA = +25°C, VDD = +2.0V to +5.5V, VSS = GND, VCM = VDD/2, VOUT  VDD/2, VL = VDD/2, RL = 10 k to VL, CL = 60 pF and CS is tied low. 1.8 1.6 VDD = 5.5V Slew Rate (V/µs) VDD = 2.0V 1 Frequency (Hz) 1M 1.E+07 100k 1.E+06 10k 1.E+05 1.2 1.0 0.8 VDD = 2.0V 0.6 Rising Edge 0.4 10M FIGURE 2-19: Maximum Output Voltage Swing vs. Frequency. 0.0 -50 0 25 50 75 Ambient Temperature (°C) FIGURE 2-22: 100 125 Slew Rate vs. Temperature. 25 Input Noise Voltage Density (nV/¥Hz) 10 5 f = 1 kHz VDD = 5.0V 5.5 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 0 10 0.1 1 10 100 1k 10k 100k 1M 1.E- 1.E+ 1.E+ 1.E+ 1.E+ 1.E+ 1.E+ 1.E+ 01 00 01 Frequency 02 03(Hz) 04 05 06 Input Noise Voltage Density 15 1.0 100 20 0.5 1,000 FIGURE 2-20: vs. Frequency. -25 0.0 1.E+04 1.E+03 1k Input Noise Voltage Density (nV/—Hz) Falling Edge 0.2 0.1 Common Mode Input Voltage (V) FIGURE 2-23: Input Noise Voltage Density vs. Common-mode Input Voltage, with f = 1 kHz. 140 30 25 20 TA = +125°C TA = +85°C TA = +25°C TA = -40°C 15 10 5 Channel-to-Channel Separation (dB) 35 Ouptut Short-Circuit Current (mA) VDD = 5.5V 1.4 -0.5 Maximum Output Voltage Swing (V P-P ) 10 130 120 110 100 0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 Power Supply Voltage (V) FIGURE 2-21: Output Short Circuit Current vs. Supply Voltage. DS20001810G-page 10 1 10 Frequency (kHz) 100 FIGURE 2-24: Channel-to-Channel Separation vs. Frequency (MCP6272 and MCP6274).  2019 Microchip Technology Inc. MCP6271/1R/2/3/4/5 Note: Unless otherwise indicated, TA = +25°C, VDD = +2.0V to +5.5V, VSS = GND, VCM = VDD/2, VOUT  VDD/2, VL = VDD/2, RL = 10 k to VL, CL = 60 pF and CS is tied low. 700 200 Op Amp turns Off Op Amp turns On 150 Hysteresis 100 50 CS swept High-to-Low CS swept Low-to-High 600 Quiescent Current (µA/amplifier) Quiescent Current (µA/amplifier) VDD = 2.0V Hysteresis 500 CS swept Low-to-High 400 300 200 100 0 Op Amp turns On/Off 0 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 Chip Select Voltage (V) Chip Select Voltage (V) FIGURE 2-25: Quiescent Current vs. Chip Select (CS) Voltage, with VDD = 2.0V (MCP6273 and MCP6275 only). FIGURE 2-28: Quiescent Current vs. Chip Select (CS) Voltage, with VDD = 5.5V (MCP6273 and MCP6275 only). 5.0 5.0 G = +1 V/V VDD = 5.0V 4.5 4.0 4.5 Output Voltage (V) Output Voltage (V) VDD = 5.5V CS swept High-to-Low 250 3.5 3.0 2.5 2.0 1.5 1.0 0.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 0.0 Time (5 µs/div) Time (5 µs/div) FIGURE 2-26: Pulse Response. Large Signal Non-inverting FIGURE 2-29: Response. Large Signal Inverting Pulse G = -1 V/V Output Voltage (10 mV/div) Output Voltage (10 mV/div) G = +1 V/V Time (2 µs/div) Time (2 µs/div) FIGURE 2-27: Pulse Response. G = -1 V/V VDD = 5.0V Small Signal Non-inverting  2019 Microchip Technology Inc. FIGURE 2-30: Response. Small Signal Inverting Pulse DS20001810G-page 11 MCP6271/1R/2/3/4/5 Note: Unless otherwise indicated, TA = +25°C, VDD = +2.0V to +5.5V, VSS = GND, VCM = VDD/2, VOUT  VDD/2, VL = VDD/2, RL = 10 k to VL, CL = 60 pF and CS is tied low. CS 2.0 1.5 VOUT 1.0 0.5 VDD = 2.0V G = +1 V/V VIN = VSS Output On Output High-Z 6.0 5.5 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 Chip Select, Output Voltages (V) Chip Select, Output Voltages (V) 2.5 0.0 Time (5 µs/div) FIGURE 2-31: Chip Select (CS) to Amplifier Output Response Time, with VDD = 2.0V (MCP6273 and MCP6275 only). +125°C +85°C +25°C -40°C Input Voltage (V) DS20001810G-page 12 Output High-Z Input Current vs. Input Output On FIGURE 2-33: Chip Select (CS) to Amplifier Output Response Time, with VDD = 5,5V (MCP6273 and MCP6275 only). 6 -1.0 -0.9 -0.8 -0.7 -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0.0 FIGURE 2-32: Voltage. VOUT Time (5 µs/div) Input, Output Voltage (V) Input Current Magnitude (A) 1.E-02 10m 1.E-03 1m 1.E-04 100µ 1.E-05 10µ 1.E-06 1µ 100n 1.E-07 10n 1.E-08 1n 1.E-09 100p 1.E-10 10p 1.E-11 1p 1.E-12 VDD = 5.5V G = +1 V/V VIN = VSS CS VDD = 5.0V G = +2 V/V 5 4 3 2 1 0 VIN VOUT -1 Time (1 ms/div) FIGURE 2-34: The MCP6271/1R/2/3/4/5 Show no Phase Reversal.  2019 Microchip Technology Inc. MCP6271/1R/2/3/4/5 3.0 PIN DESCRIPTIONS Descriptions of the pins are listed in Table 3-1 (single op amps) and Table 3-2 (dual and quad op amps). TABLE 3-1: PIN FUNCTION TABLE FOR SINGLE OP AMPS MCP6271 MCP6271R MCP6273 Symbol Description PDIP, SOIC, MSOP SOT-23-5 SOT-23-5 PDIP, SOIC, MSOP SOT-23-6 2 4 4 2 4 VIN– 3 3 3 3 3 VIN+ Non-inverting Input 4 2 5 4 2 VSS Negative Power Supply 6 1 1 6 1 VOUT Analog Output 7 5 2 7 6 VDD Positive Power Supply Inverting Input — — — 8 5 CS Chip Select 1,5,8 — — 1,5 — NC No Internal Connection TABLE 3-2: PIN FUNCTION TABLE FOR DUAL AND QUAD OP AMPS MCP6272 MCP6274 MCP6275 Symbol 1 1 — VOUTA Analog Output (op amp A) 2 2 2 VINA– Inverting Input (op amp A) 3 3 3 VINA+ Non-inverting Input (op amp A) 8 4 8 VDD 5 5 — VINB+ Non-inverting Input (op amp B) 6 6 6 VINB– Inverting Input (op amp B) 7 7 7 VOUTB Analog Output (op amp B) — 8 — VOUTC Analog Output (op amp C) — 9 — VINC– Inverting Input (op amp C) — 10 — VINC+ 4 11 4 VSS 3.1 Description Positive Power Supply Non-inverting Input (op amp C) Negative Power Supply — 12 — VIND+ Non-inverting Input (op amp D) — 13 — VIND– Inverting Input (op amp D) — 14 — VOUTD — — 1 VOUTA / VINB+ — — 5 CS Analog Output (op amp D) Analog Output (op amp A)/Non-inverting Input (op amp B) Chip Select Analog Outputs The output pins are low impedance voltage sources. 3.2 Analog Inputs The non-inverting and inverting inputs are high impedance CMOS inputs with low bias currents. 3.3 MCP6275’s VOUTA/VINB+ Pin For the MCP6275 only, the output of op amp A is connected directly to the non-inverting input of op amp B; this is the VOUTA/VINB+ pin. This connection makes it possible to provide a CS pin for duals in 8-pin packages.  2019 Microchip Technology Inc. 3.4 Chip Select Digital Input This is a CMOS, Schmitt triggered input that places the part into a low power mode of operation. 3.5 Power Supply Pins The positive power supply (VDD) is 2.0V to 6.0V higher than the negative power supply (VSS). For normal operation, the other pins are at voltages between VSS and VDD. Typically, these parts are used in a single (positive) supply configuration. In this case, VSS is connected to ground and VDD is connected to the supply. VDD will need bypass capacitors. DS20001810G-page 13 MCP6271/1R/2/3/4/5 4.0 APPLICATION INFORMATION The MCP6271/1R/2/3/4/5 family of op amps is manufactured using Microchip’s state of the art CMOS process, specifically designed for low cost, low power and general purpose applications. The low supply voltage, low quiescent current and wide bandwidth make the MCP6271/1R/2/3/4/5 ideal for battery powered applications. dump any currents onto VDD. When implemented as shown, resistors R1 and R2 also limit the current through D1 and D2. VDD D1 V1 4.1 Rail-to-Rail Inputs 4.1.1 R1 The ESD protection on the inputs can be depicted as shown in Figure 4-1. This structure was chosen to protect the input transistors, and to minimize input bias current (IB). The input ESD diodes clamp the inputs when they try to go more than one diode drop below VSS. They also clamp any voltages that go too far above VDD; their breakdown voltage is high enough to allow normal operation, and low enough to bypass quick ESD events within the specified limits. VDD Bond Pad Input Stage Bond V – IN Pad VSS Bond Pad FIGURE 4-1: Structures. Simplified Analog Input ESD In order to prevent damage and/or improper operation of these amplifiers, the circuit must limit the currents (and voltages) at the input pins (see Absolute Maximum Ratings † at the beginning of Section 1.0 “Electrical Characteristics”). Figure 4-2 shows the recommended approach to protecting these inputs. The internal ESD diodes prevent the input pins (VIN+ and VIN–) from going too far below ground, and the resistors R1 and R2 limit the possible current drawn out of the input pins. Diodes D1 and D2 prevent the input pins (VIN+ and VIN–) from going too far above VDD, and DS20001810G-page 14 VOUT R2 R3 VSS – (minimum expected V1) 2 mA VSS – (minimum expected V2) R2 > 2 mA R1 > INPUT VOLTAGE AND CURRENT LIMITS VIN+ Bond Pad MCP627X V2 PHASE REVERSAL The input devices are designed to not exhibit phase inversion when the input pins exceed the supply voltages. Figure 2-34 shows an input voltage exceeding both supplies with no phase inversion. 4.1.2 D2 FIGURE 4-2: Inputs. Protecting the Analog It is also possible to connect the diodes to the left of the resistor R1 and R2. In this case, the currents through the diodes D1 and D2 need to be limited by some other mechanism. The resistors then serve as in-rush current limiters; the DC current into the input pins (VIN+ and VIN–) should be very small. A significant amount of current can flow out of the inputs (through the ESD diodes) when the Commonmode voltage (VCM) is below ground (VSS); see Figure 2-32. Applications that are high impedance may need to limit the usable voltage range. 4.1.3 NORMAL OPERATIONS The input stage of the MCP6271/1R/2/3/4/5 op amps uses two differential CMOS input stages in parallel. One operates at low Common-mode input voltage (VCM and the other at high VCM. With this topology, the input operates with VCM up to 0.3V past either supply rail (see Figure 2-7 and Figure 2-10). The input offset voltage (VOS) is measured at VCM = VSS – 0.3V and VDD + 0.3V to ensure proper operation. The transition between the two input stage occurs when VCM  VDD – 1.1V (see Figure 2-3 and Figure 26). For the best distortion and gain linearity, with noninverting gains, avoid this region of operation. 4.2 Rail-to-Rail Output The output voltage range of the MCP6271/1R/2/3/4/5 op amps is VDD – 15 mV (minimum) and VSS + 15 mV (maximum) when RL = 10 k is connected to VDD/2 and VDD = 5.5V. Refer to Figure 2-17 for more information.  2019 Microchip Technology Inc. MCP6271/1R/2/3/4/5 4.3 Capacitive Loads 4.4 Driving large capacitive loads can cause stability problems for voltage feedback op amps. As the load capacitance increases, the feedback loop’s phase margin decreases and the closed-loop bandwidth is reduced. This produces gain peaking in the frequency response, with overshoot and ringing in the step response. A unity gain buffer (G = +1) is the most sensitive to capacitive loads, though all gains show the same general behavior. When driving large capacitive loads with these op amps (e.g., > 100 pF when G = +1), a small series resistor at the output (RISO in Figure 4-3) improves the feedback loop’s phase margin (stability) by making the output load resistive at higher frequencies. The bandwidth will be generally lower than the bandwidth with no capacitive load. _ RISO VOUT MCP627X VIN + CL MCP6273/5 Chip Select The MCP6273 and MCP6275 are single and dual op amps with Chip Select (CS), respectively. When CS is pulled high, the supply current drops to 0.7 µA (typical) and flows through the CS pin to VSS. When this happens, the amplifier output is put into a high impedance state. By pulling CS low, the amplifier is enabled. The CS pin has an internal 5 M (typical) pulldown resistor connected to VSS, so it will go low if the CS pin is left floating. Figure 1-1 shows the output voltage and supply current response to a CS pulse. 4.5 Cascaded Dual Op Amps (MCP6275) The MCP6275 is a dual op amp with Chip Select (CS). The Chip Select input is available on what would be the non-inverting input of a standard dual op amp (pin 5). This pin is available because the output of op amp A connects to the non-inverting input of op amp B, as shown in Figure 4-5. The Chip Select input, which can be connected to a microcontroller I/O line, puts the device in low power mode. Refer to Section 4.4 “MCP6273/5 Chip Select (CS)”. Figure 4-4 gives recommended RISO values for different capacitive loads and gains. The x-axis is the normalized load capacitance (CL/GN), where GN is the circuit's noise gain. For non-inverting gains, GN and the Signal Gain are equal. For inverting gains, GN is 1+|Signal Gain| (e.g., –1 V/V gives GN = +2 V/V). VINB– VOUTA/VINB+ FIGURE 4-3: Output Resistor, RISO stabilizes large capacitive loads. 1 VINA– VINA+ 2 3 6 _ _ + + A B 7 VOUTB MCP6275 5 CS Recommended RISO (:) 1,000 FIGURE 4-5: The output of op amp A is loaded by the input impedance of op amp B, which is typically 10136 pF, as specified in the DC specification table (Refer to Section 4.3 “Capacitive Loads” for further details regarding capacitive loads). 100 GN = 1 V/V GN = 2 V/V GN t 4 V/V 10 10 100 1,000 Cascaded Gain Amplifier. 10,000 Normalized Load Capacitance; CL / GN (pF) FIGURE 4-4: Recommended RISO Values for Capacitive Loads. The Common-mode input range of these op amps is specified in the data sheet as VSS – 300 mV and VDD + 300 mV. However, since the output of op amp A is limited to VOL and VOH (20 mV from the rails with a 10 k load), the non-inverting input range of op amp B is limited to the Common-mode input range of VSS + 20 mV and VDD – 20 mV. After selecting RISO for your circuit, double check the resulting frequency response peaking and step response overshoot. Modify RISO's value until the response is reasonable. Bench evaluation and simulations with the MCP6271/1R/2/3/4/5 SPICE macro model are helpful.  2019 Microchip Technology Inc. DS20001810G-page 15 MCP6271/1R/2/3/4/5 4.6 Unused Amplifiers VIN– An unused op amp in a quad package (MCP6274) should be configured as shown in Figure 4-6. These circuits prevent the output from toggling and causing crosstalk. In Circuit A, R1 and R2 produce a voltage within its output voltage range (VOH, VOL). The op amp buffers this voltage, which can be used elsewhere in the circuit. Circuit B uses the minimum number of components and operates as a comparator. VIN+ VSS Guard Ring ¼ MCP6274 (A) ¼ MCP6274 (B) VDD VDD 1. VDD R1 + + R2 VREF – – R2 V REF = V DD  -----------------R1 + R2 FIGURE 4-6: 4.7 Unused Op Amps. Supply Bypass With this family of operational amplifiers, the power supply pin (VDD for single supply) should have a local bypass capacitor (i.e., 0.01 µF to 0.1 µF) within 2 mm for good, high frequency performance. It also needs a bulk capacitor (i.e., 1 µF or larger) within 100 mm to provide large, slow currents. This bulk capacitor can be shared with nearby analog parts. 4.8 FIGURE 4-7: for Inverting Gain. 2. Example Guard Ring Layout For Inverting Gain and Transimpedance Amplifiers (convert current to voltage, such as photo detectors): a) Connect the guard ring to the non-inverting input pin (VIN+). This biases the guard ring to the same reference voltage as the op amp (e.g., VDD/2 or ground). b) Connect the inverting pin (VIN–) to the input with a wire that does not touch the PCB surface. Non-inverting Gain and Unity Gain Buffer: a) Connect the non-inverting pin (VIN+) to the input with a wire that does not touch the PCB surface. b) Connect the guard ring to the inverting input pin (VIN–). This biases the guard ring to the Common-mode input voltage. PCB Surface Leakage In applications where low input bias current is critical, Printed Circuit Board (PCB) surface leakage effects need to be considered. Surface leakage is caused by humidity, dust or other contamination on the board. Under low humidity conditions, a typical resistance between nearby traces is 1012. A 5V difference would cause 5 pA of current to flow. This is greater than the MCP6271/1R/2/3/4/5 family’s bias current at 25°C (1 pA, typical). The easiest way to reduce surface leakage is to use a guard ring around sensitive pins (or traces). The guard ring is biased at the same voltage as the sensitive pin. An example of this type of layout is illustrated in Figure 4-7. DS20001810G-page 16  2019 Microchip Technology Inc. MCP6271/1R/2/3/4/5 4.9 Application Circuits 4.9.1 4.9.2 ACTIVE FULL-WAVE RECTIFIER The MCP6271/1R/2/3/4/5 family of amplifiers can be used in applications such as an Active Full-Wave Rectifier or an Absolute Value circuit, as shown in Figure 4-8. The amplifier and feedback loops in this active voltage rectifier circuit eliminate the diode drop problem that exists in a passive voltage rectifier. This circuit behaves as a follower (the output follows the input) as long as the input signal is more positive than the reference voltage. If the input signal is more negative than the reference voltage, however, the circuit behaves as an inverting amplifier. Therefore, the output voltage will always be above the reference voltage, regardless of the input signal. LOSSY NON-INVERTING INTEGRATOR The non-inverting integrator shown in Figure 4-9 is easy to build. It saves one op amp over the typical Miller integrator plus inverting amplifier configuration. The phase accuracy of this integrator depends on the matching of the input and feedback resistor-capacitor time constants. RF makes this a lossy integrator (it has finite gain at DC) and stable by itself. VIN R1 + C1 MCP6271 _ RF R2 C2 R1 VIN RF  R2 – R3 R4 Op Amp B VOUT + 1/2 MCP6272 R5 VREF D2 D1 R2 R 1 C 1 =  R 2 ||R F C 2 V OUT 1 -------------  ------------------ V IN s  R1 C1  FIGURE 4-9: 1 f  --------------------------------------------------2R 1 C 1  1 + R F  R 2  Non-Inverting Integrator. R1 = R2 = R3 – VREF VOUT Op Amp A + 1/2 MCP6272 V D1 R 4 < R 3  1 – ----------------------------  V REF – V SS R2 R4 R 5 = -----------2R 3 Input Output VREF VREF time FIGURE 4-8: time Active Full-wave Rectifier. The design equations give a gain of ±1 from VIN to VOUT, and produce rail-to-rail outputs.  2019 Microchip Technology Inc. DS20001810G-page 17 MCP6271/1R/2/3/4/5 4.9.3 CASCADED OP AMP APPLICATIONS R4 The MCP6275 provides the flexibility of Low power mode for dual op amps in an 8-pin package. The MCP6275 eliminates the added cost and space in a battery powered application by using two single op amps with Chip Select (CS) lines or a 10-pin device with one CS line for both op amps. Since the two op amps are internally cascaded, this device cannot be used in circuits that require active or passive elements between the two op amps. However, there are several applications where this op amp configuration with a CS line becomes suitable. The circuits below show possible applications for this device. 4.9.3.1 With the cascaded op amp configuration, op amp B can be used to isolate the load from op amp A. In applications where op amp A is driving capacitive or low resistive loads in the feedback loop (such as an integrator or filter circuit) the op amp may not have sufficient source current to drive the load. In this case, op amp B can be used as a buffer. – + + A – VOUTB B MCP6275 + A MCP6275 Cascaded Gain Circuit Difference Amplifier VIN2 R2 R2 R1 – + R4 + A Where: GA = op amp A gain GB = op amp B gain VOSA = op amp A input offset voltage VOSB = op amp B input offset voltage Therefore, it is recommended that you set most of the gain with op amp A and use op amp B with relatively small gain (e.g., a unity gain buffer). DS20001810G-page 18 B VOUT MCP6275 R1 CS FIGURE 4-12: V OUT = V IN G A G B + V OSA G A G B + V OSB G B R3 – Isolating the Load with a Figure 4-11 shows a cascaded gain circuit configuration with Chip Select. Op amps A and B are configured in a non-inverting amplifier configuration. In this configuration, it is important to note that the input offset voltage of op amp A is amplified by the gain of op amp A and B, as shown below: VOUT B Figure 4-12 shows op amp A configured as a difference amplifier with Chip Select. In this configuration, it is recommended that well matched resistors (e.g., 0.1%) be used to increase the Common-mode Rejection Ratio (CMRR). Op amp B can be used to provide additional gain and isolate the load from the difference amplifier. Load Cascaded Gain R1 – FIGURE 4-11: Configuration. CS 4.9.3.2 R2 CS VIN1 FIGURE 4-10: Buffer. + VIN 4.9.3.3 Load Isolation – R3 4.9.3.4 Difference Amplifier Circuit. Inverting Integrator with Active Compensation and Chip Select Figure 4-13 uses an active compensator (op amp B) to compensate for the non-ideal op amp characteristics introduced at higher frequencies. This circuit uses op amp B as a unity gain buffer to isolate the integration capacitor C1 from op amp A and drives the capacitor with a low impedance source. Since both op amps are matched very well, they provide a high quality integrator. VIN C1 R1 B – + – + VOUT A MCP6275 CS  2019 Microchip Technology Inc. MCP6271/1R/2/3/4/5 FIGURE 4-13: Compensation. 4.9.3.5 Integrator Circuit with Active Second Order MFB with an Extra Pole-Zero Pair Figure 4-14 is a second order multiple feedback lowpass filter with Chip Select. Use the FilterLab® software from Microchip Technology Inc. to determine the R and C values for op amp A’s second order filter. Op amp B can be used to add a pole-zero pair using C3, R6 and R7. C3 R6 R7 R1 VIN R3 VDD – C1 R2 – R5 + + 4.9.3.7 The low-pass filter shown in Figure 4-16 does not require external capacitors and uses only three external resistors; the op amp’s GBWP sets the corner frequency. R1 and R2 are used to set the circuit gain. R3 is used to set the Q. To avoid gain peaking in the frequency response, Q needs to be low (lower values need to be selected for R3). Note that the amplifier bandwidth varies greatly over temperature and process. This configuration, however, provides a low cost solution for applications with high bandwidth requirements. VIN R1 R2 – VOUT B Capacitorless Second Order Low-Pass filter with Chip Select + R3 A + – VREF A B VOUT MCP6275 MCP6275 R4 CS CS FIGURE 4-14: Second Order Multiple Feedback Low-Pass Filter with an Extra PoleZero Pair. 4.9.3.6 FIGURE 4-16: Capacitorless Second Order Low-Pass Filter with Chip Select. Second Order Sallen-Key with an Extra Pole-Zero Pair Figure 4-15 is a second order Sallen-Key low-pass filter with Chip Select. Use the Filterlab® software from Microchip to determine the R and C values for op amp A’s second order filter. Op amp B can be used to add a pole-zero pair using C3, R5 and R6. C3 R5 VIN R4 R3 C2 R6 R1 R2 – + – B + A VOUT MCP6275 C1 CS FIGURE 4-15: Second Order Sallen-Key Low-Pass Filter with an Extra Pole-Zero Pair and Chip Select.  2019 Microchip Technology Inc. DS20001810G-page 19 MCP6271/1R/2/3/4/5 NOTES: DS20001810G-page 20  2019 Microchip Technology Inc. MCP6271/1R/2/3/4/5 5.0 DESIGN TOOLS Microchip provides the basic design tools needed for the MCP6271/1R/2/3/4/5 family of op amps. 5.1 SPICE Macro Model The latest SPICE macro model for the MCP6271/1R/2/ 3/4/5 op amps is available on the Microchip web site at www.microchip.com. This model is intended to be an initial design tool that works well in the op amp’s linear region of operation over the temperature range. See the model file for information on its capabilities. Bench testing is a very important part of any design and cannot be replaced with simulations. Also, simulation results using this macro model need to be validated by comparing them to the data sheet specifications and characteristic curves. 5.2 FilterLab® Software Microchip’s FilterLab® software is an innovative software tool that simplifies analog active filter (using op amps) design. Available at no cost from the Microchip web site at www.microchip.com/filterlab, the FilterLab design tool provides full schematic diagrams of the filter circuit with component values. It also outputs the filter circuit in SPICE format, which can be used with the macro model to simulate actual filter performance. 5.3 Mindi™ Circuit Designer & Simulator Microchip’s Mindi™ Circuit Designer & Simulator aids in the design of various circuits useful for active filter, amplifier and power-management applications. It is a free online circuit designer & simulator available from the Microchip web site at www.microchip.com/mindi. This interactive circuit designer & simulator enables designers to quickly generate circuit diagrams, simulate circuits. Circuits developed using the Mindi Circuit Designer & Simulator can be downloaded to a personal computer or workstation. 5.4 5.5 Analog Demonstration and Evaluation Boards Microchip offers a broad spectrum of Analog Demonstration and Evaluation Boards that are designed to help you achieve faster time to market. For a complete listing of these boards and their corresponding user’s guides and technical information, visit the Microchip web site at www.microchip.com/ analogtools. Two of our boards that are especially useful are: • P/N SOIC8EV: 8-Pin SOIC/MSOP/TSSOP/DIP Evaluation Board • P/N SOIC14EV: 14-Pin SOIC/TSSOP/DIP Evaluation Board 5.6 Application Notes The following Microchip Application Notes are available on the Microchip web site at www.microchip. com/ appnotes and are recommended as supplemental reference resources. ADN003: “Select the Right Operational Amplifier for your Filtering Circuits,” DS21821 AN722: “Operational Amplifier Topologies and DC Specifications,” DS00722 AN723: “Operational Amplifier AC Specifications and Applications”, DS00723 AN884: “Driving Capacitive Loads With Op Amps,” DS00884 AN990: “Analog Sensor Conditioning Circuits – An Overview,” DS00990 These application notes and others are listed in the design guide: “Signal Chain Design Guide,” DS21825 MAPS (Microchip Advanced Part Selector) MAPS is a software tool that helps semiconductor professionals efficiently identify Microchip devices that fit a particular design requirement. Available at no cost from the Microchip web site at www.microchip.com/ maps, the MAPS is an overall selection tool for Microchip’s product portfolio that includes Analog, Memory, MCUs and DSCs. Using this tool you can define a filter to sort features for a parametric search of devices and export side-by-side technical comparison reports. Helpful links are also provided for Data sheets, Purchase, and Sampling of Microchip parts.  2019 Microchip Technology Inc. DS20001810G-page 21 MCP6271/1R/2/3/4/5 NOTES: DS20001810G-page 22  2019 Microchip Technology Inc. MCP6271/1R/2/3/4/5 6.0 PACKAGING INFORMATION 6.1 Package Marking Information Example: 5-Lead SOT-23 (MCP6271 and MCP6271R) Device XXNN Code MCP6271 CGNN MCP6271R ETNN CG25 Note: Applies to 5-Lead SOT-23 Example: 6-Lead SOT-23 (MCP6273) XXNN CK25 8-Lead MSOP Example: 6271E 644256 8-Lead PDIP (300 mil) XXXXXXXX XXXXXNNN YYWW MCP6271 E/P256 0437 Legend: XX...X Y YY WW NNN e3 * Note: Example: OR MCP6271 E/P^^256 e3 0644 Customer-specific information Year code (last digit of calendar year) Year code (last 2 digits of calendar year) Week code (week of January 1 is week ‘01’) Alphanumeric traceability code Pb-free JEDEC designator for Matte Tin (Sn) This package is Pb-free. The Pb-free JEDEC designator ( e3 ) can be found on the outer packaging for this package. In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information.  2019 Microchip Technology Inc. DS20001810G-page 23 MCP6271/1R/2/3/4/5 Package Marking Information (Continued) 8-Lead SOIC (150 mil) XXXXXXXX XXXXYYWW NNN 14-Lead PDIP (300 mil) (MCP6274) XXXXXXXXXXXXXX XXXXXXXXXXXXXX YYWWNNN Example: MCP6271 E/SN0437 256 MCP6271E e3 SN^^0644 256 OR Example: MCP6274-E/P 0437256 OR MCP6274 e3 E/P^^ 0644256 14-Lead SOIC (150 mil) (MCP6274) Example: XXXXXXXXXX XXXXXXXXXX YYWWNNN MCP6274ESL 0437256 OR MCP6274 e3 E/SL^^ 0644256 14-Lead TSSOP (MCP6274) XXXXXX YYWW NNN DS20001810G-page 24 Example: 6274EST 0437 256  2019 Microchip Technology Inc. MCP6271/1R/2/3/4/5 5-Lead Plastic Small Outline Transistor (OT) [SOT23] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging 0.20 C 2X D e1 A D N E/2 E1/2 E1 E (DATUM D) (DATUM A-B) 0.15 C D 2X NOTE 1 1 2 e B NX b 0.20 C A-B D TOP VIEW A A A2 0.20 C SEATING PLANE A SEE SHEET 2 A1 C SIDE VIEW Microchip Technology Drawing C04-091-OT Rev E Sheet 1 of 2  2019 Microchip Technology Inc. DS20001810G-page 25 MCP6271/1R/2/3/4/5 5-Lead Plastic Small Outline Transistor (OT) [SOT23] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging c T L L1 VIEW A-A SHEET 1 Units Dimension Limits Number of Pins N e Pitch e1 Outside lead pitch Overall Height A Molded Package Thickness A2 Standoff A1 E Overall Width E1 Molded Package Width D Overall Length L Foot Length Footprint L1 I Foot Angle c Lead Thickness b Lead Width MIN 0.90 0.89 - 0.30 0° 0.08 0.20 MILLIMETERS NOM 5 0.95 BSC 1.90 BSC 2.80 BSC 1.60 BSC 2.90 BSC 0.60 REF - MAX 1.45 1.30 0.15 0.60 10° 0.26 0.51 Notes: 1. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.25mm per side. 2. Dimensioning and tolerancing per ASME Y14.5M BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only. Microchip Technology Drawing C04-091-OT Rev E Sheet 2 of 2 DS20001810G-page 26  2019 Microchip Technology Inc. MCP6271/1R/2/3/4/5 5-Lead Plastic Small Outline Transistor (OT) [SOT23] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging X SILK SCREEN 5 Y Z C G 1 2 E GX RECOMMENDED LAND PATTERN Units Dimension Limits E Contact Pitch C Contact Pad Spacing X Contact Pad Width (X5) Contact Pad Length (X5) Y Distance Between Pads G Distance Between Pads GX Overall Width Z MIN MILLIMETERS NOM 0.95 BSC 2.80 MAX 0.60 1.10 1.70 0.35 3.90 Notes: 1. Dimensioning and tolerancing per ASME Y14.5M BSC: Basic Dimension. Theoretically exact value shown without tolerances. Microchip Technology Drawing No. C04-2091B [OT]  2019 Microchip Technology Inc. DS20001810G-page 27 MCP6271/1R/2/3/4/5 6-Lead Plastic Small Outline Transistor (CH, CHY) [SOT-23] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging 2X 0.15 C A-B D e1 A D E 2 E1 E E1 2 2X 0.15 C D 2X 0.20 C A-B e 6X b B 0.20 C A-B D TOP VIEW C A A2 SEATING PLANE 6X A1 0.10 C SIDE VIEW R1 L2 R c GAUGE PLANE L Ĭ (L1) END VIEW Microchip Technology Drawing C04-028C (CH) Sheet 1 of 2 DS20001810G-page 28  2019 Microchip Technology Inc. MCP6271/1R/2/3/4/5 6-Lead Plastic Small Outline Transistor (CH, CHY) [SOT-23] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging Units Dimension Limits N Number of Leads e Pitch Outside lead pitch e1 A Overall Height Molded Package Thickness A2 Standoff A1 Overall Width E Molded Package Width E1 Overall Length D Foot Length L Footprint L1 Seating Plane to Gauge Plane L1 φ Foot Angle c Lead Thickness Lead Width b MIN 0.90 0.89 0.00 0.30 0° 0.08 0.20 MILLIMETERS NOM 6 0.95 BSC 1.90 BSC 1.15 2.80 BSC 1.60 BSC 2.90 BSC 0.45 0.60 REF 0.25 BSC - MAX 1.45 1.30 0.15 0.60 10° 0.26 0.51 Notes: 1. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.25mm per side. 2. Dimensioning and tolerancing per ASME Y14.5M BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only. Microchip Technology Drawing C04-028C (CH) Sheet 2 of 2  2019 Microchip Technology Inc. DS20001810G-page 29 MCP6271/1R/2/3/4/5 6-Lead Plastic Small Outline Transistor (CH, CHY) [SOT-23] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging GX Y Z C G G SILK SCREEN X E RECOMMENDED LAND PATTERN Units Dimension Limits E Contact Pitch C Contact Pad Spacing X Contact Pad Width (X3) Y Contact Pad Length (X3) G Distance Between Pads Distance Between Pads GX Z Overall Width MIN MILLIMETERS NOM 0.95 BSC 2.80 MAX 0.60 1.10 1.70 0.35 3.90 Notes: 1. Dimensioning and tolerancing per ASME Y14.5M BSC: Basic Dimension. Theoretically exact value shown without tolerances. Microchip Technology Drawing No. C04-2028B (CH) DS20001810G-page 30  2019 Microchip Technology Inc. MCP6271/1R/2/3/4/5 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2019 Microchip Technology Inc. DS20001810G-page 31 MCP6271/1R/2/3/4/5 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS20001810G-page 32  2019 Microchip Technology Inc. MCP6271/1R/2/3/4/5 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2019 Microchip Technology Inc. DS20001810G-page 33 MCP6271/1R/2/3/4/5 8-Lead Plastic Dual In-Line (P) - 300 mil Body [PDIP] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging D A N B E1 NOTE 1 1 2 TOP VIEW E C A2 A PLANE L c A1 e eB 8X b1 8X b .010 C SIDE VIEW END VIEW Microchip Technology Drawing No. C04-018-P Rev E Sheet 1 of 2 DS20001810G-page 34  2019 Microchip Technology Inc. MCP6271/1R/2/3/4/5 8-Lead Plastic Dual In-Line (P) - 300 mil Body [PDIP] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging ALTERNATE LEAD DESIGN (NOTE 5) DATUM A DATUM A b b e 2 e 2 e e Units Dimension Limits Number of Pins N e Pitch Top to Seating Plane A Molded Package Thickness A2 Base to Seating Plane A1 Shoulder to Shoulder Width E Molded Package Width E1 Overall Length D Tip to Seating Plane L c Lead Thickness b1 Upper Lead Width b Lower Lead Width eB Overall Row Spacing § MIN .115 .015 .290 .240 .348 .115 .008 .040 .014 - INCHES NOM 8 .100 BSC .130 .310 .250 .365 .130 .010 .060 .018 - MAX .210 .195 .325 .280 .400 .150 .015 .070 .022 .430 Notes: 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. § Significant Characteristic 3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" per side. 4. Dimensioning and tolerancing per ASME Y14.5M BSC: Basic Dimension. Theoretically exact value shown without tolerances. 5. Lead design above seating plane may vary, based on assembly vendor. Microchip Technology Drawing No. C04-018-P Rev E Sheet 2 of 2  2019 Microchip Technology Inc. DS20001810G-page 35 MCP6271/1R/2/3/4/5 8-Lead Plastic Small Outline (SN) - Narrow, 3.90 mm (.150 In.) Body [SOIC] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging 2X 0.10 C A–B D A D NOTE 5 N E 2 E1 2 E1 E NOTE 1 2 1 e B NX b 0.25 C A–B D NOTE 5 TOP VIEW 0.10 C C A A2 SEATING PLANE 8X A1 SIDE VIEW 0.10 C h R0.13 h R0.13 H SEE VIEW C VIEW A–A 0.23 L (L1) VIEW C Microchip Technology Drawing No. C04-057-SN Rev E Sheet 1 of 2 DS20001810G-page 36  2019 Microchip Technology Inc. MCP6271/1R/2/3/4/5 8-Lead Plastic Small Outline (SN) - Narrow, 3.90 mm (.150 In.) Body [SOIC] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging Units Dimension Limits Number of Pins N e Pitch Overall Height A Molded Package Thickness A2 § Standoff A1 Overall Width E Molded Package Width E1 Overall Length D Chamfer (Optional) h Foot Length L L1 Footprint Foot Angle c Lead Thickness b Lead Width Mold Draft Angle Top Mold Draft Angle Bottom MIN 1.25 0.10 0.25 0.40 0° 0.17 0.31 5° 5° MILLIMETERS NOM 8 1.27 BSC 6.00 BSC 3.90 BSC 4.90 BSC 1.04 REF - MAX 1.75 0.25 0.50 1.27 8° 0.25 0.51 15° 15° Notes: 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. § Significant Characteristic 3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.15mm per side. 4. Dimensioning and tolerancing per ASME Y14.5M BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only. 5. Datums A & B to be determined at Datum H. Microchip Technology Drawing No. C04-057-SN Rev E Sheet 2 of 2  2019 Microchip Technology Inc. DS20001810G-page 37 MCP6271/1R/2/3/4/5 8-Lead Plastic Small Outline (SN) - Narrow, 3.90 mm Body [SOIC] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging SILK SCREEN C Y1 X1 E RECOMMENDED LAND PATTERN Units Dimension Limits E Contact Pitch Contact Pad Spacing C Contact Pad Width (X8) X1 Contact Pad Length (X8) Y1 MIN MILLIMETERS NOM 1.27 BSC 5.40 MAX 0.60 1.55 Notes: 1. Dimensioning and tolerancing per ASME Y14.5M BSC: Basic Dimension. Theoretically exact value shown without tolerances. Microchip Technology Drawing C04-2057-SN Rev E DS20001810G-page 38  2019 Microchip Technology Inc. MCP6271/1R/2/3/4/5                 J &' !&" &K# 3!*!!& K%&  &#& &&GQQ333'  'QK N NOTE 1 E1 1 3 2 D E A2 A L A1 c b1 b e eB U&! '! ['&! Y"'+  %! Y9Z