MCP6284-E/SL

MCP6281/1R/2/3/4/5 450 µA, 5 MHz Rail-to-Rail Op Amp Features Description • • • • • • • • The Microchip Technology Inc. MCP6281/1R/2/3/4/5 family of operational amplifiers (op amps) provide wide bandwidth for the current. This family has a 5 MHz Gain Bandwidth Product (GBWP) and a 65° phase margin. This family also operates from a single supply voltage as low as 2.2V, while drawing 450 µA (typical) quiescent current. Additionally, the MCP6281/1R/2/3/4/5 supports rail-to-rail input and output swing, with a common mode input voltage range of VDD + 300 mV to VSS – 300 mV. This family of operational amplifiers is designed with Microchip’s advanced CMOS process. Gain Bandwidth Product: 5 MHz (typical) Supply Current: IQ = 450 µA (typical) Supply Voltage: 2.2V to 6.0V Rail-to-Rail Input/Output Extended Temperature Range: -40°C to +125°C Available in Single, Dual, and Quad Packages Single with CS (MCP6283) Dual with CS (MCP6285) Applications • • • • • • The MCP6285 has a Chip Select (CS) input for dual op amps in an 8-pin package. This device is manufactured by cascading the two op amps (the output of op amp A connected to the non-inverting input of op amp B). The CS input puts the device in Low-power mode. Automotive Portable Equipment Photodiode Amplifier Analog Filters Notebooks and PDAs Battery-Powered Systems The MCP6281/1R/2/3/4/5 family operates over the Extended Temperature Range of -40°C to +125°C. It also has a power supply range of 2.2V to 6.0V. Design Aids • • • • • • SPICE Macro Models FilterLab® Software Mindi™ Circuit Designer & Simulator MAPS (Microchip Advanced Part Selector) Analog Demonstration and Evaluation Boards Application Notes Package Types NC 1 VIN _ MCP6281 SOT-23-5 8 NC 2 VIN+ 3 VSS 4 7 VDD VSS 2 6 VOUT 5 NC MCP6283 PDIP, SOIC, MSOP NC 1 VSS 4 8 CS + 7 VDD 6 VOUT 5 NC MCP6283 VOUT 1 VSS 2 VIN+ 3 6 VDD - VIN+ 3 5 CS _ 4 VIN VOUTA 1 VINA _ 2 VINA+ 3 VDD 4 VINB+ 5 VINB_ 6 VOUTB 7  2019 Microchip Technology Inc. - 14 VOUTD -+ + VINA_ 2 4 VIN– MCP6284 PDIP, SOIC, TSSOP SOT-23-6 + VIN_ 2 VIN+ 3 VDD 2 - VOUTA 1 5 VSS VOUT 1 4 VIN– VIN+ 3 MCP6282 PDIP, SOIC, MSOP SOT-23-5 5 VDD VOUT 1 + + MCP6281R + MCP6281 PDIP, SOIC, MSOP - 13 VIND_ 12 VIND+ 11 VSS 10 VINC+ 8 VDD -+ VINA+ 3 7 VOUTB +- VSS 4 6 VINB_ 5 VINB+ MCP6285 PDIP, SOIC, MSOP VOUTA/VINB+ 1 VINA_ 2 VINA+ 3 VSS 4 8 VDD 7 VOUTB - + +- _ 6 VINB 5 CS -+ +- 9 V _ INC 8 VOUTC DS20001811F-page 1 MCP6281/1R/2/3/4/5 1.0 ELECTRICAL CHARACTERISTICS VDD – VSS ........................................................................7.0V † Notice: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. Current at Input Pins ....................................................±2 mA †† See Section 4.1.2 “Input Voltage and Current Limits”. Absolute Maximum Ratings † Analog Inputs (VIN+, VIN–) †† ........ VSS – 1.0V to VDD + 1.0V All Other Inputs and Outputs ......... VSS – 0.3V to VDD + 0.3V Difference Input Voltage ...................................... |VDD – VSS| Output Short Circuit Current .................................Continuous Current at Output and Supply Pins ............................±30 mA Storage Temperature....................................–65°C to +150°C Maximum Junction Temperature (TJ) ......................... .+150°C ESD Protection On All Pins (HBM; MM)   4 kV; 400V DC ELECTRICAL SPECIFICATIONS Electrical Characteristics: Unless otherwise indicated, TA = +25 C, VDD = +2.2V to +5.5V, VSS = GND, VOUT  VDD/2, VCM = VDD/2, VL = VDD/2, RL = 10 kto VL and CS is tied low. (refer to Figure 1-2 and Figure 1-3). Parameters Sym Min Typ Max Units Conditions Input Offset Voltage VOS -3.0 — +3.0 mV VCM = VSS (Note 1) Input Offset Voltage (Extended Temperature) VOS -5.0 — +5.0 mV TA= -40°C to +125°C, VCM = VSS (Note 1) Input Offset Temperature Drift VOS/TA — ±1.7 — Power Supply Rejection Ratio PSRR 70 90 — Input Offset µV/°C TA= -40°C to +125°C, VCM = VSS (Note 1) dB VCM = VSS (Note 1) Input Bias, Input Offset Current and Impedance IB — ±1.0 — pA Note 2 At Temperature IB — 50 200 pA TA= +85°C (Note 2) At Temperature IB — 2 5 nA TA= +125°C (Note 2) Input Bias Current Input Offset Current IOS — ±1.0 — pA Note 3 Common Mode Input Impedance ZCM — 1013||6 — ||pF Note 3 Differential Input Impedance ZDIFF — 1013||3 — ||pF Note 3 Common Mode (Note 4) Common Mode Input Range VCMR VSS 0.3 — VDD + 0.3 V Common Mode Rejection Ratio CMRR 70 85 — dB VCM = -0.3V to 2.5V, VDD = 5V Common Mode Rejection Ratio CMRR 65 80 — dB VCM = -0.3V to 5.3V, VDD = 5V AOL 90 110 — dB VOUT = 0.2V to VDD – 0.2V, VCM = VSS (Note 1) VOL, VOH VSS + 15 — VDD – 15 mV 0.5V input overdrive ISC — ±25 — mA VDD 2.2 — 6.0 V (Note 5) IQ 300 450 570 µA IO = 0 Open-Loop Gain DC Open-Loop Gain (Large Signal) Output Maximum Output Voltage Swing Output Short Circuit Current Power Supply Supply Voltage Quiescent Current per Amplifier Note 1: 2: 3: 4: 5: The MCP6285’s VCM for op amp B (pins VOUTA/VINB+ and VINB–) is VSS + 100 mV. The current at the MCP6285’s VINB– pin is specified by IB only. This specification does not apply to the MCP6285’s VOUTA/VINB+ pin. The MCP6285’s VINB– pin (op amp B) has a common mode range (VCMR) of VSS + 100 mV to VDD – 100 mV. The MCP6285’s VOUTA/VINB+ pin (op amp B) has a voltage range specified by VOH and VOL. All parts with date codes November 2007 and later have been screened to ensure operation at VDD = 6.0V. However, the other minimum and maximum specifications are measured at 2.4V and/or 5.5V. DS20001811F-page 2  2019 Microchip Technology Inc. MCP6281/1R/2/3/4/5 AC ELECTRICAL SPECIFICATIONS Electrical Characteristics: Unless otherwise indicated, TA = +25°C, VDD = +2.2V to +5.5V, VSS = GND, VOUT  VDD/2, VCM = VDD/2, VL = VDD/2, RL = 10 kto VL, CL = 60 pF and CS is tied low. (refer to Figure 1-2 and Figure 1-3). Parameters Sym Min Typ Max Units MHz Conditions AC Response Gain Bandwidth Product GBWP — 5.0 — Phase Margin at Unity-Gain PM — 65 — ° Slew Rate SR — 2.5 — V/µs Input Noise Voltage Eni — 5.2 — µVP-P Input Noise Voltage Density eni — 16 — nV/Hz f = 1 kHz Input Noise Current Density ini — 3 — fA/Hz f = 1 kHz G = +1 V/V Noise f = 0.1 Hz to 10 Hz MCP6283/MCP6285 CHIP SELECT (CS) SPECIFICATIONS Electrical Characteristics: Unless otherwise indicated, TA = +25°C, VDD = +2.2V to +5.5V, VSS = GND, VOUT  VDD/2, VCM = VDD/2, VL = VDD/2, RL = 10 kto VL, CL = 60 pF and CS is tied low. (refer to Figure 1-2 and Figure 1-3). Parameters Sym Min Typ Max Units Conditions CS Logic Threshold, Low VIL VSS — 0.2 VDD V CS Input Current, Low ICSL — 0.01 — µA CS Logic Threshold, High VIH 0.8 VDD — VDD V CS Input Current, High ICSH — 0.7 2 µA CS = VDD GND Current per Amplifier ISS — -0.7 — µA CS = VDD Amplifier Output Leakage — — 0.01 — µA CS = VDD CS Low to Valid Amplifier Output, Turn-on Time tON — 4 10 µs CS Low  0.2 VDD, G = +1 V/V, VIN = VDD/2, VOUT = 0.9 VDD/2, VDD = 5.0V CS High to Amplifier Output High-Z tOFF — 0.01 — µs CS High  0.8 VDD, G = +1 V/V, VIN = VDD/2, VOUT = 0.1 VDD/2 VHYST — 0.6 — V VDD = 5V CS Low Specifications CS = VSS CS High Specifications Dynamic Specifications (Note 1) Hysteresis Note 1: The input condition (VIN) specified applies to both op amp A and B of the MCP6285. The dynamic specification is tested at the output of op amp B (VOUTB). CS VIL VIH tOFF tON VOUT ISS ICS Hi-Z Hi-Z -0.7 µA (typical) 0.7 µA (typical) -450 µA (typical) 10 nA (typical) -0.7 µA (typical) 0.7 µA (typical) FIGURE 1-1: Timing Diagram for the Chip Select (CS) pin on the MCP6283 and MCP6285.  2019 Microchip Technology Inc. DS20001811F-page 3 MCP6281/1R/2/3/4/5 TEMPERATURE SPECIFICATIONS Electrical Characteristics: Unless otherwise indicated, VDD = +2.2V to +5.5V and VSS = GND. Parameters Sym Min Typ Max Units Operating Temperature Range TA -40 — +125 °C Storage Temperature Range TA -65 — +150 °C Thermal Resistance, 5L-SOT-23 JA — 256 — °C/W Thermal Resistance, 6L-SOT-23 JA — 230 — °C/W Thermal Resistance, 8L-PDIP JA — 85 — °C/W Thermal Resistance, 8L-SOIC JA — 163 — °C/W Thermal Resistance, 8L-MSOP JA — 206 — °C/W Conditions Temperature Ranges Note Thermal Package Resistances Thermal Resistance, 14L-PDIP JA — 70 — °C/W Thermal Resistance, 14L-SOIC JA — 120 — °C/W Thermal Resistance, 14L-TSSOP JA — 100 — °C/W Note: 1.1 The Junction Temperature (TJ) must not exceed the Absolute Maximum specification of +150°C. Test Circuits The test circuits used for the DC and AC tests are shown in Figure 1-2 and Figure 1-2. The bypass capacitors are laid out according to the rules discussed in Section 4.6 “Supply Bypass”. VDD VIN RN 0.1 µF 1 µF + – VOUT MCP628X CL VDD/2 RG RL RF VL FIGURE 1-2: AC and DC Test Circuit for Most Non-Inverting Gain Conditions. VDD VDD/2 RN 0.1 µF 1 µF + VOUT MCP628X – VIN RG CL RL RF VL FIGURE 1-3: AC and DC Test Circuit for Most Inverting Gain Conditions. DS20001811F-page 4  2019 Microchip Technology Inc. MCP6281/1R/2/3/4/5 2.0 TYPICAL PERFORMANCE CURVES Note: The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore outside the warranted range. Note: Unless otherwise indicated, TA = +25°C, VDD = +2.2V to +6.0V, VSS = GND, VCM = VDD/2, VOUT  VDD/2, VL = VDD/2, RL = 10 k to VL, CL = 60 pF and CS is tied low. 30% 832 Samples VCM = VSS 10% 8% 6% 4% 2% 20% 15% 10% 5% 0% 2.8 2.4 2.0 1.6 -10 -8 Input Offset Voltage (mV) 35% FIGURE 2-5: TA = +125 °C. 300 100 TA = +125°C TA = +85°C TA = +25°C TA = -40°C -100 -0.5 0.0 0.5 1.0 1.5 3600 TA = +125°C TA = +85°C TA = +25°C TA = -40°C 0 -50 -100 2.0 2.5 Common Mode Input Voltage (V) FIGURE 2-3: Input Offset Voltage vs. Common Mode Input Voltage at VDD = 2.2V.  2019 Microchip Technology Inc. 50 1.0 -50 100 0.5 0 150 -0.5 50 200 6.0 150 5.5 200 VDD = 5.5V 250 5.0 VDD = 2.2V 250 Input Bias Current at 4.5 Input Bias Current at Input Offset Voltage (µV) Input Offset Voltage (µV) 300 Input Bias Current (pA) 0.0 FIGURE 2-2: TA = +85 °C. 3200 100 Input Bias Current (pA) 2800 90 0% 2400 80 5% 4.0 70 10 10% 3.5 60 8 15% 3.0 50 6 20% 2.5 40 4 25% 2000 0% 30 2 210 Samples TA = +125°C 30% 1600 5% 20 0 1200 10% 10 -2 Input Offset Voltage Drift. 800 15% 0 -4 2.0 20% Percentage of Occurrences 210 Samples TA = +85°C 0 25% Percentage of Occurrences FIGURE 2-4: Input Offset Voltage. 200 FIGURE 2-1: -6 Input Offset Voltage Drift (µV/°C) 400 1.2 0.8 0.4 0.0 -0.4 -0.8 -1.2 -1.6 -2.0 -2.4 -2.8 0% 832 Samples VCM = VSS TA = -40°C to +125°C 25% 1.5 12% Percentage of Occurrences Percentage of Occurrences 14% Common Mode Input Voltage (V) FIGURE 2-6: Input Offset Voltage vs. Common Mode Input Voltage at VDD = 5.5V. DS20001811F-page 5 MCP6281/1R/2/3/4/5 TYPICAL PERFORMANCE CURVES (CONTINUED) Note: Unless otherwise indicated, TA = +25°C, VDD = +2.2V to +6.0V, VSS = GND, VCM = VDD/2, VOUT  VDD/2, VL = VDD/2, RL = 10 k to VL, CL = 60 pF and CS is tied low. 10,000 VCM = VSS Representative Part 250 Input Bias, Offset Currents (pA) Input Offset Voltage (µV) 300 200 150 100 50 0 VDD = 5.5V VDD = 2.2V -50 -100 VCM = VDD VDD = 5.5V 1,000 Input Bias Current 100 Input Offset Current 10 1 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 25 35 45 Output Voltage (V) FIGURE 2-7: Output Voltage. 65 75 85 95 105 115 125 FIGURE 2-10: Input Bias, Input Offset Currents vs. Ambient Temperature. Input Offset Voltage vs. 120 110 PSRR- 90 CMRR 110 PSRR, CMRR (dB) 100 CMRR, PSRR (dB) 55 Ambient Temperature (°C) PSRR+ 80 70 60 50 40 CMRR 100 90 PSRR VCM = VSS 80 70 30 20 60 1.E+00 1.E+01 1 1.E+02 10 1.E+03 100 1.E+04 1k 1.E+05 10k -50 1.E+06 100k 1M -25 Frequency (Hz) FIGURE 2-8: Frequency. FIGURE 2-11: Temperature. CMRR, PSRR vs. 2.5 45 Input Bias, Offset Currents (nA) Input Bias, Offset Currents (pA) 55 Input Bias Current 35 25 15 5 Input Offset Current -5 TA = +85°C VDD = 5.5V -15 0 25 50 75 100 125 Ambient Temperature (°C) 2.0 CMRR, PSRR vs. Ambient TA = +125°C VDD = 5.5V 1.5 Input Bias Current 1.0 0.5 0.0 Input Offset Current -0.5 -1.0 -25 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 Common Mode Input Voltage (V) FIGURE 2-9: Input Bias, Offset Currents vs. Common Mode Input Voltage at TA = +85°C. DS20001811F-page 6 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 Common Mode Input Voltage (V) FIGURE 2-12: Input Bias, Offset Currents vs. Common Mode Input Voltage at TA = +125°C.  2019 Microchip Technology Inc. MCP6281/1R/2/3/4/5 TYPICAL PERFORMANCE CURVES (CONTINUED) Note: Unless otherwise indicated, TA = +25°C, VDD = +2.2V to +6.0V, VSS = GND, VCM = VDD/2, VOUT  VDD/2, VL = VDD/2, RL = 10 k to VL, CL = 60 pF and CS is tied low. 500 400 300 TA = +125°C TA = +85°C TA = +25°C TA = -40°C 100 0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 1000 100 10 VDD - VOH 1 0.01 Power Supply Voltage (V) 0 100 -30 -90 -180 90 VDD = 5.5V 5 85 Gain Bandwidth Product 4 1.E+08 75 VDD = 5.5V 2 70 VDD = 2.2V Phase Margin 1 65 -50 -25 0 25 50 75 100 60 125 Ambient Temperature (°C) Open-Loop Gain, Phase vs. FIGURE 2-17: Gain Bandwidth Product, Phase Margin vs. Ambient Temperature. 10 4.5 4.0 Slew Rate (V/µs) VDD = 5.5V VDD = 2.2V 1 3.5 Falling Edge, VDD = 2.2V Falling Edge, VDD = 5.5V 3.0 2.5 2.0 1.5 Rising Edge, VDD = 5.5V Rising Edge, VDD = 2.2V 1.0 0.5 1M 1.E+07 100k 1.E+06 10k 1.E+05 0.0 1k 1.E+04 0.1 1.E+03 Maximum Output Voltage Swing (VP-P) 80 3 Frequency (Hz) FIGURE 2-14: Frequency. VDD = 2.2V 0 -210 10k 100k 1M 10M 100M 1.E+07 1k 1.E+06 100 1.E+05 10 1.E+04 1 1.E+03 0 1.E+02 -150 1.E+01 20 1.E+00 -120 Gain Bandwidth Product (MHz) -60 Phase 0.1 10 6 40 -20 1 FIGURE 2-16: Output Voltage Headroom vs. Output Current Magnitude. Open-Loop Phase (°) Gain 1.E-01 Open-Loop Gain (dB) 120 60 0.1 Output Current Magnitude (mA) FIGURE 2-13: Quiescent Current vs. Power Supply Voltage. 80 VOL - VSS Phase Margin (°) 200 Ouput Voltage Headroom (mV) Quiescent Current (µA/amplifier) 600 10M -50 -25 FIGURE 2-15: Maximum Output Voltage Swing vs. Frequency.  2019 Microchip Technology Inc. 0 25 50 75 100 125 Ambient Temperature (°C) Frequency (Hz) FIGURE 2-18: Temperature. Slew Rate vs. Ambient DS20001811F-page 7 MCP6281/1R/2/3/4/5 TYPICAL PERFORMANCE CURVES (CONTINUED) Note: Unless otherwise indicated, TA = +25°C, VDD = +2.2V to +6.0V, VSS = GND, VCM = VDD/2, VOUT  VDD/2, VL = VDD/2, RL = 10 k to VL, CL = 60 pF and CS is tied low. 30 Input Noise Voltage Density (nV/Hz) Input Noise Voltage Density (nV/Hz) 1,000 100 10 1.E-01 1.E+00 0.1 1 1.E+01 1.E+02 10 100 1.E+03 1.E+04 1k 10k 1.E+05 1.E+06 100k f = 1 kHz VDD = 5.0V 25 20 15 10 5 0 0.0 1M 0.5 Frequency (Hz) FIGURE 2-19: vs. Frequency. Input Noise Voltage Density 30 25 20 15 TA = +125°C TA = +85°C TA = +25°C TA = -40°C 5 0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 1.5 4.0 4.5 5.0 3.0 3.5 4.0 4.5 5.0 130 120 110 100 5.5 1 10 100 Frequency (kHz) FIGURE 2-20: Output Short Circuit Current vs. Power Supply Voltage. FIGURE 2-23: Channel-to-Channel Separation vs. Frequency (MCP6282 and MCP6284 only). 1000 Op-Amp shuts off here 450 900 400 Quiescent Current (µA/Amplifier) Op-Amp turns on here 350 300 250 Hysteresis 200 150 CS swept high to low 100 CS swept low to high 0.2 0.4 0.8 1.0 1.2 1.4 1.6 1.8 2.0 FIGURE 2-21: Quiescent Current vs. Chip Select (CS) Voltage at VDD = 2.2V (MCP6283 and MCP6285 only). 2.2 CS swept low to high 600 500 400 300 200 Op Amp toggles On/Off here 0 0.6 Chip Select Voltage (V) DS20001811F-page 8 Hysteresis 700 100 VDD = 2.2V 0 0.0 VDD = 5.5V 800 CS swept high to low 500 Quiescent Current (µA/Amplifier) 2.5 140 Power Supply Voltage (V) 50 2.0 FIGURE 2-22: Input Noise Voltage Density vs. Common Mode Input Voltage at 1 kHz. Channel-to-Channel Separation (dB) Ouptut Short Circuit Current (mA) 35 10 1.0 Common Mode Input Voltage (V) 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 Chip Select Voltage (V) FIGURE 2-24: Quiescent Current vs. Chip Select (CS) Voltage at VDD = 5.5V (MCP6283 and MCP6285 only).  2019 Microchip Technology Inc. MCP6281/1R/2/3/4/5 TYPICAL PERFORMANCE CURVES (CONTINUED) Note: Unless otherwise indicated, TA = +25°C, VDD = +2.2V to +6.0V, VSS = GND, VCM = VDD/2, VOUT  VDD/2, VL = VDD/2, RL = 10 k to VL, CL = 60 pF and CS is tied low. 5.0 5.0 G = +1V/V VDD = 5.0V 4.5 Output Voltage (V) Output Voltage (V) 3.5 3.0 2.5 2.0 1.5 1.0 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.5 0.0 G = -1V/V VDD = 5.0V 4.5 4.0 0.E+00 2.E-06 4.E-06 6.E-06 8.E-06 1.E-05 1.E-05 1.E-05 2.E-05 2.E-05 0.0 2.E-05 0.E+00 2.E-06 4.E-06 6.E-06 8.E-06 FIGURE 2-25: Pulse Response. Large-Signal, Non-inverting FIGURE 2-28: Pulse Response. Output Voltage (10 mV/div) Output Voltage (10 mV/div) G = +1V/V Small-Signal, Non-inverting FIGURE 2-29: Pulse Response. 2.E-05 CS Voltage 2.0 1.5 VOUT Output On 1.0 0.5 Output High-Z 0.0E+00 5.0E-06 1.0E-05 1.5E-05 2.0E-05 2.5E-05 3.5E-05 4.0E-05 4.5E-05 VDD = 5.5V G = +1V/V VIN = VSS CS Voltage 5.0 4.5 4.0 3.5 VOUT 3.0 2.5 2.0 1.5 1.0 Output High-Z Output On 0.5 0.E+00 5.E-06 1.E-05 2.E-05 2.E-05 3.E-05 3.E-05 4.E-05 4.E-05 5.E-05 5.E-05 5.0E-05 Time (5 µs/div) FIGURE 2-27: Chip Select (CS) to Amplifier Output Response Time at VDD = 2.2V (MCP6283 and MCP6285 only).  2019 Microchip Technology Inc. 2.E-05 Small-Signal, Inverting 5.5 0.0 3.0E-05 2.E-05 Large-Signal, Inverting 6.0 VDD = 2.2V G = +1V/V VIN = VSS Chip Select, Output Voltages (V) Chip Select, Output Voltages (V) 1.E-05 Time (500 ns/div) 2.5 0.0 1.E-05 G = -1V/V Time (500 ns/div) FIGURE 2-26: Pulse Response. 1.E-05 Time (2 µs/div) Time (2 µs/div) Time (5 µs/div) FIGURE 2-30: Chip Select (CS) to Amplifier Output Response Time at VDD = 5.5V (MCP6283 and MCP6285 only). DS20001811F-page 9 MCP6281/1R/2/3/4/5 Note: Unless otherwise indicated, TA = +25°C, VDD = +2.2V to +6.0V, VSS = GND, VCM = VDD/2, VOUT  VDD/2, VL = VDD/2, RL = 10 k to VL, CL = 60 pF and CS is tied low. 6 +125°C +85°C +25°C -40°C -1.0 -0.9 -0.8 -0.7 -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0.0 Input Voltage (V) FIGURE 2-31: Measured Input Current vs. Input Voltage (below VSS). DS20001811F-page 10 Input, Output Voltage (V) Input Current Magnitude (A) 1.E-02 10m 1.E-03 1m 1.E-04 100µ 1.E-05 10µ 1.E-06 1µ 100n 1.E-07 10n 1.E-08 1n 1.E-09 100p 1.E-10 10p 1.E-11 1p 1.E-12 VDD = 5.0V G = +2 V/V 5 4 VOUT VIN 3 2 1 0 -1 -15 -14 -13 -12 -11 -10 -9 -8 -7 -6 -5 Time (1 ms/div) FIGURE 2-32: The MCP6281/1R/2/3/4/5 Show No Phase Reversal.  2019 Microchip Technology Inc. MCP6281/1R/2/3/4/5 3.0 PIN DESCRIPTIONS Descriptions of the pins are listed in Table 3-1 (single op amps) and Table 3-2 (dual and quad op amps). TABLE 3-1: PIN FUNCTION TABLE FOR SINGLE OP AMPS MCP6281 MCP6281R MCP6283 PDIP, SOIC, MSOP SOT-23-5 SOT-23-5 PDIP, SOIC, MSOP SOT-23-6 6 2 3 7 4 — 1,5,8 1 4 3 5 2 — — 1 4 3 2 5 — — 6 2 3 7 4 8 1,5 1 4 3 6 2 5 — TABLE 3-2: PDIP, SOIC, MSOP MCP6284 PDIP, SOIC, TSSOP 1 2 3 4 5 6 7 8 9 10 11 12 13 14 — — 3.1 MCP6285 PDIP, SOIC, MSOP — Analog Outputs The output pins are low-impedance voltage sources. 3.2 Analog Inputs The non-inverting and inverting inputs are highimpedance CMOS inputs with low bias currents. 3.3 VOUT VIN– VIN+ VDD VSS CS NC Description Analog Output Inverting Input Non-inverting Input Positive Power Supply Negative Power Supply Chip Select No Internal Connection PIN FUNCTION TABLE FOR DUAL AND QUAD OP AMPS MCP6282 1 2 3 8 5 6 7 — — — 4 — — — — Symbol MCP6285’s VOUTA/VINB+ Pin For the MCP6285 only, the output of op amp A is connected directly to the non-inverting input of op amp B; this is the VOUTA/VINB+ pin. This connection makes it possible to provide a Chip Select pin for duals in 8-pin packages.  2019 Microchip Technology Inc. — 2 3 8 — 6 7 — — — 4 — — — 1 Symbol VOUTA VINA– VINA+ VDD VINB+ VINB– VOUTB VOUTC VINC– VINC+ VSS VIND+ VIND– VOUTD VOUTA/ VINB+ CS 5 3.4 Description Analog Output (op amp A) Inverting Input (op amp A) Non-inverting Input (op amp A) Positive Power Supply Non-inverting Input (op amp B) Inverting Input (op amp B) Analog Output (op amp B) Analog Output (op amp C) Inverting Input (op amp C) Non-inverting Input (op amp C) Negative Power Supply Non-inverting Input (op amp D) Inverting Input (op amp D) Analog Output (op amp D) Analog Output (op amp A)/Noninverting Input (op amp B) Chip Select Chip Select Digital Input (CS) This is a CMOS, Schmitt-triggered input that places the part into a low-power mode of operation. 3.5 Power Supply Pins The positive power supply (VDD) is 2.2V to 6.0V higher than the negative power supply (VSS). For normal operation, the other pins are between VSS and VDD. Typically, these parts are used in a single (positive) supply configuration. In this case, VSS is connected to ground and VDD is connected to the supply. VDD will need bypass capacitors. DS20001811F-page 11 MCP6281/1R/2/3/4/5 4.0 APPLICATION INFORMATION The MCP6281/1R/2/3/4/5 family of op amps is manufactured using Microchip's state-of-the-art CMOS process. This family is specifically designed for lowcost, low-power and general purpose applications. The low supply voltage, low quiescent current and wide bandwidth makes the MCP6281/1R/2/3/4/5 ideal for battery-powered applications. 4.1 VDD, and dump any currents onto VDD. When implemented as shown, resistors R1 and R2 also limit the current through D1 and D2. VDD D1 V1 R1 Rail-to-Rail Inputs 4.1.1 R2 The MCP6281/1R/2/3/4/5 op amp is designed to prevent phase reversal when the input pins exceed the supply voltages. Figure 2-32 shows the input voltage exceeding the supply voltage without any phase reversal. 4.1.2 R3 VSS – (minimum expected V1) 2 mA VSS – (minimum expected V2) R2 > 2 mA R1 > INPUT VOLTAGE AND CURRENT LIMITS The ESD protection on the inputs can be depicted as shown in Figure 4-1. This structure was chosen to protect the input transistors, and to minimize input bias current (IB). The input ESD diodes clamp the inputs when they try to go more than one diode drop below VSS. They also clamp any voltages that go too far above VDD; their breakdown voltage is high enough to allow normal operation, and low enough to bypass quick ESD events within the specified limits. VDD Bond Pad VIN+ Bond Pad Input Stage Bond VIN– Pad VSS Bond Pad FIGURE 4-1: Structures. Simplified Analog Input ESD In order to prevent damage and/or improper operation of these op amps, the circuit they are in must limit the currents and voltages at the VIN+ and VIN– pins (see Absolute Maximum Ratings † at the beginning of Section 1.0 “Electrical Characteristics”). Figure 4-2 shows the recommended approach to protecting these inputs. The internal ESD diodes prevent the input pins (VIN+ and VIN–) from going too far below ground, and the resistors R1 and R2 limit the possible current drawn out of the input pins. Diodes D1 and D2 prevent the input pins (VIN+ and VIN–) from going too far above DS20001811F-page 12 + MCP628X – V2 PHASE REVERSAL D2 FIGURE 4-2: Inputs. Protecting the Analog It is also possible to connect the diodes to the left of resistors R1 and R2. In this case, current through the diodes D1 and D2 needs to be limited by some other mechanism. The resistors then serve as in-rush current limiters; the DC current into the input pins (VIN+ and VIN–) should be very small. A significant amount of current can flow out of the inputs when the common mode voltage (VCM) is below ground (VSS); see Figure 2-31. Applications that are high impedance may need to limit the usable voltage range. 4.1.3 NORMAL OPERATION The input stage of the MCP6281/1R/2/3/4/5 op amps use two differential CMOS input stages in parallel. One operates at low common mode input voltage (VCM), while the other operates at high VCM. With this topology, the device operates with VCM up to 0.3V above VDD and 0.3V below VSS. There is a transition in input behavior as VCM is changed. It occurs when VCM is near VDD – 1.2V (see Figure 2-3 and Figure 2-6). For the best distortion performance with non-inverting gains, avoid these regions of operation.  2019 Microchip Technology Inc. MCP6281/1R/2/3/4/5 4.2 Rail-to-Rail Output The output voltage range of the MCP6281/1R/2/3/4/5 op amp is VDD – 15 mV (min.) and VSS + 15 mV (max.) when RL = 10 k is connected to VDD/2 and VDD = 5.5V. Refer to Figure 2-16 for more information. After selecting RISO for your circuit, double-check the resulting frequency response peaking and step response overshoot. Modify RISO's value until the response is reasonable. Bench evaluation and simulations with the MCP6281/1R/2/3/4/5 SPICE macro model are helpful. 4.3 4.4 Capacitive Loads Driving large capacitive loads can cause stability problems for voltage feedback op amps. As the load capacitance increases, the feedback loop’s phase margin decreases and the closed-loop bandwidth is reduced. This produces gain peaking in the frequency response, with overshoot and ringing in the step response. A unity-gain buffer (G = +1) is the most sensitive to capacitive loads, though all gains show the same general behavior. When driving large capacitive loads with these op amps (e.g., > 100 pF when G = +1), a small series resistor at the output (RISO in Figure 4-3) improves the feedback loop’s phase margin (stability) by making the output load resistive at higher frequencies. The bandwidth will generally be lower than the bandwidth with no capacitive load. – RISO MCP628X VOUT + VIN CL MCP628X Chip Select (CS) The MCP6283 and MCP6285 are single and dual op amps with Chip Select (CS), respectively. When CS is pulled high, the supply current drops to 0.7 µA (typical) and flows through the CS pin to VSS. When this happens, the amplifier output is put into a high-impedance state. By pulling CS low, the amplifier is enabled. The CS pin has an internal 5 M (typical) pull-down resistor connected to VSS, so it will go low if the CS pin is left floating. Figure 1-1 shows the output voltage and supply current response to a CS pulse. 4.5 Cascaded Dual Op Amps (MCP6285) The MCP6285 is a dual op amp with Chip Select (CS). The Chip Select input is available on what would be the non-inverting input of a standard dual op amp (pin 5). This pin is available because the output of op amp A connects to the non-inverting input of op amp B, as shown in Figure 4-5. The Chip Select input, which can be connected to a microcontroller I/O line, puts the device in Low-power mode. Refer to Section 4.4 “MCP628X Chip Select (CS)”. Figure 4-4 gives recommended RISO values for different capacitive loads and gains. The x-axis is the normalized load capacitance (CL/GN), where GN is the circuit's noise gain. For non-inverting gains, GN and the Signal Gain are equal. For inverting gains, GN is 1+|Signal Gain| (e.g., -1 V/V gives GN = +2 V/V). VINB– VOUTA/VINB+ FIGURE 4-3: Output Resistor, RISO stabilizes large capacitive loads. 1 VINA– VINA+ 2 3 6 – – + + A B 7 VOUTB MCP6285 5 CS Recommended RISO (:) 1,000 FIGURE 4-5: The output of op amp A is loaded by the input impedance of op amp B, which is typically 1013||6 pF, as specified in the DC specification table (Refer to Section 4.3 “Capacitive Loads” for further details regarding capacitive loads). 100 GN = 1 V/V GN = 2 V/V GN t 4 V/V 10 10 100 1,000 10,000 Normalized Load Capacitance; CL / GN (pF) FIGURE 4-4: Recommended RISO Values for Capacitive Loads.  2019 Microchip Technology Inc. Cascaded Gain Amplifier. The common mode input range of these op amps is specified in the data sheet as VSS – 300 mV and VDD + 300 mV. However, since the output of op amp A is limited to VOL and VOH (20 mV from the rails with a 10 k load), the non-inverting input range of op amp B is limited to the common mode input range of VSS + 20 mV and VDD – 20 mV. DS20001811F-page 13 MCP6281/1R/2/3/4/5 4.6 Supply Bypass VIN– With this family of operational amplifiers, the power supply pin (VDD for single-supply) should have a local bypass capacitor (i.e., 0.01 µF to 0.1 µF) within 2 mm for good, high-frequency performance. It also needs a bulk capacitor (i.e., 1 µF or larger) within 100 mm to provide large, slow currents. This bulk capacitor can be shared with nearby analog parts. 4.7 Unused Op Amps VDD VDD VREF R2 FIGURE 4-7: for Inverting Gain. 1. ¼ MCP6284 (B) VDD R1 VSS Guard Ring An unused op amp in a quad package (MCP6284) should be configured as shown in Figure 4-6. These circuits prevent the output from toggling and causing crosstalk. Circuits A sets the op amp at its minimum noise gain. The resistor divider produces any desired reference voltage within the output voltage range of the op amp; the op amp buffers that reference voltage. Circuit B uses the minimum number of components and operates as a comparator, but it may draw more current. ¼ MCP6284 (A) VIN+ 2. Example Guard Ring Layout For Inverting Gain and Transimpedance Amplifiers (convert current to voltage, such as photo detectors): a.Connect the guard ring to the non-inverting input pin (VIN+). This biases the guard ring to the same reference voltage as the op amp (e.g., VDD/2 or ground). b.Connect the inverting pin (VIN–) to the input with a wire that does not touch the PCB surface. Non-inverting Gain and Unity-Gain Buffer: a.Connect the non-inverting pin (VIN+) to the input with a wire that does not touch the PCB surface. b.Connect the guard ring to the inverting input pin (VIN–). This biases the guard ring to the common mode input voltage. R2 V REF = V DD  -----------------R1 + R2 FIGURE 4-6: 4.8 Unused Op Amps. PCB Surface Leakage In applications where low input bias current is critical, Printed Circuit Board (PCB) surface-leakage effects need to be considered. Surface leakage is caused by humidity, dust or other contamination on the board. Under low humidity conditions, a typical resistance between nearby traces is 1012. A 5V difference would cause 5 pA of current to flow, which is greater than the MCP6281/1R/2/3/4/5 family’s bias current at +25°C (1 pA, typical). The easiest way to reduce surface leakage is to use a guard ring around sensitive pins (or traces). The guard ring is biased at the same voltage as the sensitive pin. An example of this type of layout is shown in Figure 4-7. DS20001811F-page 14  2019 Microchip Technology Inc. MCP6281/1R/2/3/4/5 4.9 Application Circuits 4.9.1 4.9.3 SALLEN-KEY HIGH-PASS FILTER The MCP6281/1R/2/3/4/5 op amps can be used in active-filter applications. Figure 4-8 shows a secondorder Sallen-Key high-pass filter with a gain of 1. The output bias voltage is set by the VDD/2 reference, which can be changed to any voltage within the output voltage range. R1 VIN C1 + C2 MCP6281 R2 – VOUT VDD/2 FIGURE 4-8: Sallen-Key High-Pass Filter. CASCADED OP AMP APPLICATIONS The MCP6285 provides the flexibility of Low-power mode for dual op amps in an 8-pin package. The MCP6285 eliminates the added cost and space in battery-powered applications by using two single op amps with Chip Select lines or a 10-pin device with one Chip Select line for both op amps. Since the two op amps are internally cascaded, this device cannot be used in circuits that require active or passive elements between the two op amps. However, there are several applications where this op amp configuration with Chip Select line becomes suitable. The circuits below show possible applications for this device. 4.9.3.1 Load Isolation With the cascaded op amp configuration, op amp B can be used to isolate the load from op amp A. In applications where op amp A is driving capacitive or low resistance loads in the feedback loop (such as an integrator circuit or filter circuit), the op amp may not have sufficient source current to drive the load. In this case, op amp B can be used as a buffer. This filter, and others, can be designed using Microchip’s Design Aids; see Section 5.2 “FilterLab® Software” and Section 5.3 “Mindi™ Circuit Designer & Simulator”. 4.9.2 INVERTING MILLER INTEGRATOR Analog integrators are used in filters, control loops and measurement circuits. Figure 4-9 shows the most common implementation, the inverting Miller integrator. The non-inverting input is at VDD/2 so that the op amp properly biases up. The switch (SW) is used to zero the output in some applications. Other applications use a feedback loop to keep the output within its linear range of operation. SW R C VOUT VIN + MCP6281 VDD/2 + + A B VOUTB Load MCP6285 CS FIGURE 4-10: Buffer. 4.9.3.2 Isolating the Load with a Cascaded Gain Figure 4-11 shows a cascaded gain circuit configuration with Chip Select. Op amps A and B are configured in a non-inverting amplifier configuration. In this configuration, it is important to note that the input offset voltage of op amp A is amplified by the gain of op amp A and B, as shown below: V OUT = V IN G A G B + V OSA G A G B + V OSB G B – VOUT 1 = sRC VIN FIGURE 4-9: – – Miller Integrator. Where: GA = op amp A gain GB = op amp B gain VOSA = op amp A input offset voltage VOSB = op amp B input offset voltage Therefore, it is recommended to set most of the gain with op amp A and use op amp B with relatively small gain (e.g., a unity-gain buffer).  2019 Microchip Technology Inc. DS20001811F-page 15 MCP6281/1R/2/3/4/5 R4 R3 – + VIN R2 – A R2 R1 B + VOUT 4.9.3.5 Difference Amplifier VIN1 R2 R2 + A VOUT B MCP6285 CS R3 Inverting Integrator with Active Compensation and Chip Select Figure 4-14 uses an active compensator (op amp B) to compensate for the non-ideal op amp characteristics introduced at higher frequencies. This circuit uses op amp B as a unity-gain buffer to isolate the integration capacitor C1 from op amp A and drives the capacitor with low-impedance source. Since both op amps are matched very well, they provide a higher quality integrator. R1 – – + + A R1 B VOUT VIN C1 R1 MCP6285 + – + CS FIGURE 4-12: 4.9.3.4 – FIGURE 4-13: Buffered Non-inverting Integrator with Chip Select. Cascaded Gain Circuit R4 + RF R 1 C 1 =  R 2  R F C 2 Figure 4-12 shows op amp A configured as a difference amplifier with Chip Select. In this configuration, it is recommended to use well-matched resistors (e.g., 0.1%) to increase the Common Mode Rejection Ratio (CMRR). Op amp B can be used to provide additional gain and isolate the load from the difference amplifier. VIN2 R1 MCP6285 FIGURE 4-11: Configuration. – C1 CS 4.9.3.3 VIN C2 – VOUT A MCP6285 Difference Amplifier Circuit. CS Buffered Non-inverting Integrator Figure 4-13 shows a lossy non-inverting integrator that is buffered and has a Chip Select input. Op amp A is configured as a non-inverting integrator. In this configuration, matching the impedance at each input is recommended. RF is used to provide a feedback loop at frequencies