MCP6291/1R/2/3/4/5
1.0 mA, 10 MHz Rail-to-Rail Op Amp
Features
Description
•
•
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•
•
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•
•
The Microchip Technology Inc. MCP6291/1R/2/3/4/5
family of operational amplifiers (op amps) provide wide
bandwidth for the current. This family has a 10 MHz
Gain Bandwidth Product (GBWP) and a 65° phase
margin. This family also operates from a single supply
voltage as low as 2.4V, while drawing 1 mA (typical)
quiescent current. In addition, the MCP6291/1R/2/3/4/5
supports rail-to-rail input and output swing, with a
common mode input voltage range of VDD + 300 mV to
VSS – 300 mV. This family of operational amplifiers is
designed with Microchip’s advanced CMOS process.
Gain Bandwidth Product: 10 MHz (typical)
Supply Current: IQ = 1.0 mA
Supply Voltage: 2.4V to 6.0V
Rail-to-Rail Input/Output
Extended Temperature Range: -40°C to +125°C
Available in Single, Dual and Quad Packages
Single with CS (MCP6293)
Dual with CS (MCP6295)
Applications
•
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The MCP6295 has a Chip Select (CS) input for dual op
amps in an 8-pin package. This device is manufactured
by cascading the two op amps, with the output of
op amp A being connected to the non-inverting input of
op amp B. The CS input puts the device in a Low-power
mode.
Automotive
Portable Equipment
Photodiode Amplifier
Analog Filters
Notebooks and PDAs
Battery-Powered Systems
The MCP6291/1R/2/3/4/5 family operates over the
Extended Temperature Range of -40°C to +125°C. It
also has a power supply range of 2.4V to 6.0V.
Design Aids
•
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SPICE Macro Models
FilterLab® Software
Mindi™ Simulation Tool
MAPS (Microchip Advanced Part Selector)
Analog Demonstration and Evaluation Boards
Application Notes
Package Types
NC 1
VIN
_
8 NC
2
VSS 4
7 VDD
VIN+ 3
7 VDD
6 VOUT
5 NC
4 VIN–
VIN+ 3
6 VDD
-
5 CS
4 VIN–
VOUTA 1
14 VOUTD
- + + - 13 VIND_
VINA+ 3
12 VIND+
VDD 4
VOUTB 7
VOUTA 1
_
VINA 2
4 VIN–
VINA_ 2
VINB+ 5
VINB_ 6
© 2007 Microchip Technology Inc.
-
MCP6294
PDIP, SOIC, TSSOP
SOT-23-6
VOUT 1
VSS 2
VIN+ 3
MCP6292
PDIP, SOIC, MSOP
5 VSS
VOUT 1
VDD 2
-
MCP6293
+
VSS 4
8 CS
+
5 VDD
VSS 2
6 VOUT
MCP6293
PDIP, SOIC, MSOP
VIN_ 2
VIN+ 3
SOT-23-5
VOUT 1
5 NC
NC 1
MCP6291R
SOT-23-5
+
+
VIN+ 3
MCP6291
+
MCP6291
PDIP, SOIC, MSOP
11 VSS
10 VINC+
-+ +- 9 V _
INC
VINA+ 3
8 VDD
7 VOUTB
- +
+ -
VSS 4
6 VINB_
5 VINB+
MCP6295
PDIP, SOIC, MSOP
VOUTA/VINB+ 1
VINA_ 2
VINA+ 3
VSS 4
8 VDD
7 VOUTB
- +
+ -
_
6 VINB
5 CS
8 VOUTC
DS21812E-page 1
MCP6291/1R/2/3/4/5
1.0
ELECTRICAL
CHARACTERISTICS
Absolute Maximum Ratings †
VDD – VSS ........................................................................7.0V
Current at Input Pins .....................................................±2 mA
† Notice: Stresses above those listed under “Absolute
Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of
the device at those or any other conditions above those
indicated in the operational listings of this specification is not
implied. Exposure to maximum rating conditions for extended
periods may affect device reliability.
†† See Section 4.1.2 “Input Voltage and Current Limits”.
Analog Inputs (VIN+, VIN–) †† ........ VSS – 1.0V to VDD + 1.0V
All Other Inputs and Outputs ......... VSS – 0.3V to VDD + 0.3V
Difference Input Voltage ...................................... |VDD – VSS|
Output Short Circuit Current .................................Continuous
Current at Output and Supply Pins ............................±30 mA
Storage Temperature....................................–65°C to +150°C
Maximum Junction Temperature (TJ) ......................... .+150°C
ESD Protection On All Pins (HBM; MM) .............. ≥ 4 kV; 400V
DC ELECTRICAL SPECIFICATIONS
Electrical Characteristics: Unless otherwise indicated, TA = +25°C, VDD = +2.4V to +5.5V, VSS = GND, VOUT ≈ VDD/2,
VCM = VDD/2, VL = VDD/2, RL = 10 kΩ to VL and CS is tied low (refer to Figure 1-2 and Figure 1-3).
Parameters
Sym
Min
Typ
Max
Units
Conditions
Input Offset Voltage
VOS
-3.0
—
+3.0
mV
VCM = VSS (Note 1)
Input Offset Voltage
(Extended Temperature)
VOS
-5.0
—
+5.0
mV
TA = -40°C to +125°C,
VCM = VSS (Note 1)
Input Offset Temperature Drift
ΔVOS/ΔTA
—
±1.7
—
µV/°C
TA = -40°C to +125°C,
VCM = VSS (Note 1)
Power Supply Rejection Ratio
PSRR
70
90
—
dB
VCM = VSS (Note 1)
IB
—
±1.0
—
pA
Note 2
At Temperature
IB
—
50
200
pA
TA = +85°C (Note 2)
At Temperature
IB
—
2
5
nA
TA = +125°C (Note 2)
Input Offset Current
IOS
—
±1.0
—
pA
Note 3
Common Mode Input Impedance
ZCM
—
1013||6
—
Ω||pF
Note 3
Differential Input Impedance
ZDIFF
—
1013||3
—
Ω||pF
Note 3
Common Mode Input Range
VCMR
VSS − 0.3
—
VDD + 0.3
V
Common Mode Rejection Ratio
CMRR
70
85
—
dB
VCM = -0.3V to 2.5V, VDD = 5V
Common Mode Rejection Ratio
CMRR
65
80
—
dB
VCM = -0.3V to 5.3V, VDD = 5V
AOL
90
110
—
dB
VOUT = 0.2V to VDD – 0.2V,
VCM = VSS (Note 1)
VOL, VOH
VSS + 15
—
VDD – 15
mV
0.5V Input Overdrive
ISC
—
±25
—
mA
VDD
2.4
—
6.0
V
IQ
0.7
1.0
1.3
mA
Input Offset
Input Bias, Input Offset Current and Impedance
Input Bias Current
Common Mode (Note 4)
Open-Loop Gain
DC Open-Loop Gain (Large Signal)
Output
Maximum Output Voltage Swing
Output Short Circuit Current
Power Supply
Supply Voltage
Quiescent Current per Amplifier
Note 1:
2:
3:
4:
5:
TA = -40°C to +125°C (Note 5)
IO = 0
The MCP6295’s VCM for op amp B (pins VOUTA/VINB+ and VINB–) is VSS + 100 mV.
The current at the MCP6295’s VINB– pin is specified by IB only.
This specification does not apply to the MCP6295’s VOUTA/VINB+ pin.
The MCP6295’s VINB– pin (op amp B) has a common mode range (VCMR) of VSS + 100 mV to VDD – 100 mV.
The MCP6295’s VOUTA/VINB+ pin (op amp B) has a voltage range specified by VOH and VOL.
All parts with date codes November 2007 and later have been screened to ensure operation at VDD = 6.0V. However,
the other minimum and maximum specifications are measured at 2.4V and or 5.5V.
DS21812E-page 2
© 2007 Microchip Technology Inc.
MCP6291/1R/2/3/4/5
AC ELECTRICAL SPECIFICATIONS
Electrical Characteristics: Unless otherwise indicated, TA = +25°C, VDD = +2.4V to +5.5V, VSS = GND, VCM = VDD/2,
VOUT ≈ VDD/2, VL = VDD/2, RL = 10 kΩ to VL, CL = 60 pF, and CS is tied low (refer to Figure 1-2 and Figure 1-3).
Parameters
Sym
Min
Typ
Max
Units
Conditions
AC Response
Gain Bandwidth Product
GBWP
—
10.0
—
MHz
Phase Margin at Unity-Gain
PM
—
65
—
°
Slew Rate
SR
—
7
—
V/µs
G = +1 V/V
Noise
Input Noise Voltage
Eni
—
4.2
—
µVP-P
Input Noise Voltage Density
eni
—
8.7
—
nV/√Hz
f = 0.1 Hz to 10 Hz
f = 10 kHz
Input Noise Current Density
ini
—
3
—
fA/√Hz
f = 1 kHz
MCP6293/MCP6295 CHIP SELECT (CS) SPECIFICATIONS
Electrical Characteristics: Unless otherwise indicated, TA = +25°C, VDD = +2.4V to +5.5V, VSS = GND, VCM = VDD/2,
VOUT ≈ VDD/2, VL = VDD/2, RL = 10 kΩ to VL, CL = 60 pF, and CS is tied low (refer to Figure 1-2 and Figure 1-3).
Parameters
Sym
Min
Typ
Max
Units
Conditions
CS Logic Threshold, Low
VIL
VSS
—
0.2 VDD
V
CS Input Current, Low
ICSL
—
0.01
—
µA
CS Logic Threshold, High
VIH
0.8 VDD
—
VDD
V
CS Input Current, High
ICSH
—
0.7
2
µA
CS = VDD
GND Current per Amplifier
ISS
—
-0.7
—
µA
CS = VDD
Amplifier Output Leakage
—
—
0.01
—
µA
CS = VDD
CS Low to Valid Amplifier Output,
Turn-on Time
tON
—
4
10
µs
CS Low ≤ 0.2 VDD, G = +1 V/V,
VIN = VDD/2, VOUT = 0.9 VDD/2,
VDD = 5.0V
CS High to Amplifier Output High-Z
tOFF
—
0.01
—
µs
CS High ≥ 0.8 VDD, G = +1 V/V,
VIN = VDD/2, VOUT = 0.1 VDD/2
VHYST
—
0.6
—
V
VDD = 5V
CS Low Specifications
CS = VSS
CS High Specifications
Dynamic Specifications (Note 1)
Hysteresis
Note 1:
The input condition (VIN) specified applies to both op amp A and B of the MCP6295. The dynamic specification is tested
at the output of op amp B (VOUTB).
© 2007 Microchip Technology Inc.
DS21812E-page 3
MCP6291/1R/2/3/4/5
TEMPERATURE SPECIFICATIONS
Electrical Characteristics: Unless otherwise indicated, VDD = +2.4V to +5.5V and VSS = GND.
Parameters
Sym
Min
Typ
Max
Units
Operating Temperature Range
TA
-40
—
+125
°C
Storage Temperature Range
TA
-65
—
+150
°C
Conditions
Temperature Ranges
Note
Thermal Package Resistances
Thermal Resistance, 5L-SOT-23
θJA
—
256
—
°C/W
Thermal Resistance, 6L-SOT-23
θJA
—
230
—
°C/W
Thermal Resistance, 8L-PDIP
θJA
—
85
—
°C/W
Thermal Resistance, 8L-SOIC
θJA
—
163
—
°C/W
Thermal Resistance, 8L-MSOP
θJA
—
206
—
°C/W
Thermal Resistance, 14L-PDIP
θJA
—
70
—
°C/W
Thermal Resistance, 14L-SOIC
θJA
—
120
—
°C/W
Thermal Resistance, 14L-TSSOP
θJA
—
100
—
°C/W
Note:
The Junction Temperature (TJ) must not exceed the Absolute Maximum specification of +150°C.
1.1
CS
VIL
VIH
tOFF
tON
VOUT
ISS
0.7 µA
(typical)
ICS
The test circuits used for the DC and AC tests are
shown in Figure 1-2 and Figure 1-2. The bypass
capacitors are laid out according to the rules discussed
in Section 4.6 “Supply Bypass”.
Hi-Z
Hi-Z
-0.7 µA
(typical)
Test Circuits
-1.0 mA
(typical)
10 nA
(typical)
-0.7 µA
(typical)
0.7 µA
(typical)
FIGURE 1-1:
Timing Diagram for the
Chip Select (CS) pin on the MCP6293 and
MCP6295.
VDD
VIN
RN
0.1 µF 1 µF
VOUT
MCP629X
CL
VDD/2 RG
RL
RF
VL
FIGURE 1-2:
AC and DC Test Circuit for
Most Non-Inverting Gain Conditions.
VDD
VDD/2
RN
0.1 µF 1 µF
VOUT
MCP629X
CL
VIN
RG
RL
RF
VL
FIGURE 1-3:
AC and DC Test Circuit for
Most Inverting Gain Conditions.
DS21812E-page 4
© 2007 Microchip Technology Inc.
MCP6291/1R/2/3/4/5
2.0
TYPICAL PERFORMANCE CURVES
Note:
The graphs and tables provided following this note are a statistical summary based on a limited number of
samples and are provided for informational purposes only. The performance characteristics listed herein
are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified
operating range (e.g., outside specified power supply range) and therefore outside the warranted range.
25%
Percentage of Occurrences
20%
840 Samples
VCM = VSS
TA = -40°C to +125°C
15%
10%
5%
Input Offset Voltage (mV)
FIGURE 2-4:
60
70
80
90
100
350
FIGURE 2-5:
TA = +125 °C.
Input Bias Current at
VDD = 2.4V
Input Offset Voltage (µV)
Input Offset Voltage (µV)
400
300
250
200
TA = -40°C
TA = +25°C
TA = +85°C
TA = +125°C
150
100
50
0
-0.5
0.0
0.5
1.0
1.5
2.0
2.5
Common Mode Input Voltage (V)
FIGURE 2-3:
Input Offset Voltage vs.
Common Mode Input Voltage at VDD = 2.4V.
© 2007 Microchip Technology Inc.
10
8
6
4
2
0
-2
Input Bias Current (pA)
Input Bias Current (pA)
FIGURE 2-2:
TA = +85 °C.
3000
50
2800
40
2600
30
2400
20
2200
10
2000
0
0%
1800
0%
1600
5%
5%
1400
10%
10%
1200
15%
15%
1000
20%
20%
800
25%
210 Samples
TA = +125°C
600
30%
25%
0
35%
Percentage of Occurrences
210 Samples
TA = 85°C
Input Offset Voltage Drift.
400
Input Offset Voltage.
30%
40%
Percentage of Occurrences
Input Offset Voltage Drift (µV/°C)
200
FIGURE 2-1:
-4
-6
-8
0%
2.8
2.4
2.0
1.6
1.2
0.8
0.4
0.0
-0.4
-0.8
-1.2
-1.6
-2.0
-2.4
840 Samples
VCM = VSS
-10
12%
11%
10%
9%
8%
7%
6%
5%
4%
3%
2%
1%
0%
-2.8
Percentage of Occurrences
Note: Unless otherwise indicated, TA = +25°C, VDD = +2.4V to +5.5V, VSS = GND, VCM = VDD/2, VOUT ≈ VDD/2,
VL = VDD/2, RL = 10 kΩ to VL, CL = 60 pF, and CS is tied low.
3.0
Input Bias Current at
800
VDD = 5.5V
750
700
650
600
550
500
450
400
350
300
250
200
-0.5 0.0 0.5 1.0 1.5 2.0
TA = +125°C
TA = +85°C
TA = +25°C
TA = -40°C
2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
Common Mode Input Voltage (V)
FIGURE 2-6:
Input Offset Voltage vs.
Common Mode Input Voltage at VDD = 5.5V.
DS21812E-page 5
MCP6291/1R/2/3/4/5
TYPICAL PERFORMANCE CURVES (CONTINUED)
700
650
600
550
500
450
400
350
300
250
200
150
100
10,000
VCM = VSS
Representative Part
Input Bias, Offset Currents
(pA)
Input Offset Voltage (µV)
Note: Unless otherwise indicated, TA = +25°C, VDD = +2.4V to +5.5V, VSS = GND, VCM = VDD/2, VOUT ≈ VDD/2,
VL = VDD/2, RL = 10 kΩ to VL, CL = 60 pF, and CS is tied low.
VDD = 5.5V
VDD = 2.4V
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
VCM = VDD
VDD = 5.5V
1,000
Input Bias Current
100
Input Offset Current
10
1
5.5
25
35
45
Output Voltage (V)
FIGURE 2-7:
Output Voltage.
Input Offset Voltage vs.
65
75
85
95
105 115 125
FIGURE 2-10:
Input Bias, Input Offset
Currents vs. Ambient Temperature.
120
110
100
110
90
PSRR, CMRR (dB)
CMRR, PSRR (dB)
55
Ambient Temperature (°C)
CMRR
80
PSRR-
70
PSRR+
60
50
40
100
CMRR
90
PSRR
VCM = VSS
80
70
30
20
60
1.E+00
1.E+01
1
10
1.E+02
1.E+03
100
1.E+04
1k
1.E+05
10k
-50
1.E+06
100k
1M
-25
0
Frequency (Hz)
CMRR, PSRR vs.
FIGURE 2-11:
Temperature.
55
2.5
45
2.0
Input Bias, Offset Currents
(nA)
Input Bias, Offset Currents
(pA)
FIGURE 2-8:
Frequency.
Input Bias Current
35
25
15
5
Input Offset Current
-5
TA = +85°C
VDD = 5.5V
-15
-25
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
Common Mode Input Voltage (V)
FIGURE 2-9:
Input Bias, Offset Currents
vs. Common Mode Input Voltage at TA = +85°C.
DS21812E-page 6
25
50
75
100
125
Ambient Temperature (°C)
CMRR, PSRR vs. Ambient
TA = +125°C
VDD = 5.5V
1.5
Input Bias Current
1.0
0.5
0.0
Input Offset Current
-0.5
-1.0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
Common Mode Input Voltage (V)
FIGURE 2-12:
Input Bias, Offset Currents
vs. Common Mode Input Voltage at TA = +125°C.
© 2007 Microchip Technology Inc.
MCP6291/1R/2/3/4/5
TYPICAL PERFORMANCE CURVES (CONTINUED)
Note: Unless otherwise indicated, TA = +25°C, VDD = +2.4V to +5.5V, VSS = GND, VCM = VDD/2, VOUT ≈ VDD/2,
VL = VDD/2, RL = 10 kΩ to VL, CL = 60 pF, and CS is tied low.
1000
1.2
1.0
0.8
TA = +125°C
TA = +85°C
TA = +25°C
TA = -40°C
0.6
0.4
0.2
0.0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
100
10
VOL - VSS
VDD - VOH
1
0.01
0.1
Power Supply Voltage (V)
FIGURE 2-13:
Quiescent Current vs.
Power Supply Voltage.
16
-30
14
80
-60
Phase
60
-90
1k
10k 100k
1M
90
-210
10M 100M
75
8
70
6
65
4
60
PM, VDD = 5.5V
PM, VDD = 2.4V
2
-50
-25
0
25
50
75
100
50
125
Open-Loop Gain, Phase vs.
FIGURE 2-17:
Gain Bandwidth Product,
Phase Margin vs. Ambient Temperature.
12
Slew Rate (V/µs)
10
VDD = 5.5V
VDD = 2.4V
1
Falling Edge, VDD = 5.5V
VDD = 2.4V
8
6
4
2
Rising Edge, VDD = 5.5V
VDD = 2.4V
1M
1.E+07
100k
1.E+06
10k
1.E+05
1k
1.E+04
0
1.E+03
Maximum Output Voltage
Swing (V P-P)
55
Ambient Temperature (°C)
10
0.1
80
10
Frequency (Hz)
FIGURE 2-14:
Frequency.
85
GBWP, VDD = 5.5V
GBWP, VDD = 2.4V
12
0
1.E+08
100
1.E+07
1.E-01
10
1.E+06
-180
1.E+05
0
1.E+04
-150
1.E+03
20
1.E+02
-120
1.E+01
40
Gain Bandwidth Product
(MHz)
0
Gain
1.E+00
Open-Loop Gain (dB)
100
1
10
FIGURE 2-16:
Output Voltage Headroom
vs. Output Current Magnitude.
Open-Loop Phase (°)
120
-20
0.1
1
Output Current Magnitude (mA)
Phase Margin (°)
Quiescent Current
(mA/Amplifier)
1.4
Ouput Voltage Headroom (mV)
1.6
10M
-50
-25
Frequency (Hz)
FIGURE 2-15:
Maximum Output Voltage
Swing vs. Frequency.
© 2007 Microchip Technology Inc.
0
25
50
75
100
125
Ambient Temperature (°C)
FIGURE 2-18:
Temperature.
Slew Rate vs. Ambient
DS21812E-page 7
MCP6291/1R/2/3/4/5
TYPICAL PERFORMANCE CURVES (CONTINUED)
Note: Unless otherwise indicated, TA = +25°C, VDD = +2.4V to +5.5V, VSS = GND, VCM = VDD/2, VOUT ≈ VDD/2,
VL = VDD/2, RL = 10 kΩ to VL, CL = 60 pF, and CS is tied low.
11
Input Noise Voltage Density
(nV/ √ Hz)
Input Noise Voltage Density
(nV/ √ Hz)
1,000
100
10
1
0.1
1.E-01
1.E+00
1
1.E+01
1.E+02
10
100
1.E+03
1.E+04
1k
10k
1.E+05
1.E+06
100k
10
9
8
f = 10 kHz
VDD = 5.0V
7
6
5
4
3
2
1
0
1M
0.0
0.5
Frequency (Hz)
FIGURE 2-19:
vs. Frequency.
Input Noise Voltage Density
1.5
2.5
3.0
3.5
4.0
4.5
5.0
140
Channel-to-Channel
Separation (dB)
30
25
20
15
TA = +125°C
TA = +85°C
TA = +25°C
TA = -40°C
10
5
0
130
120
110
100
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
1
10
Power Supply Voltage (V)
1.2
1.4
Op-Amp turns on here
0.8
Hysteresis
0.6
0.4
0.2
1.6
CS swept
high to low
CS swept
low to high
Quiescent Current
(mA/Amplifier)
1.0
FIGURE 2-23:
Channel-to-Channel
Separation vs. Frequency (MCP6292, MCP6294
and MCP6295 only).
VDD = 2.4V
Op-Amp shuts off here
100
Frequency (kHz)
FIGURE 2-20:
Output Short Circuit Current
vs. Power Supply Voltage.
Quiescent Current
(mA/Amplifier)
2.0
FIGURE 2-22:
Input Noise Voltage Density
vs. Common Mode Input Voltage at 10 kHz.
35
Ouptut Short Circuit Current
(mA)
1.0
Common Mode Input Voltage (V)
VDD = 5.5V
Op Amp shuts off
Op Amp turns on
Hysteresis
1.2
1.0
0.8
CS swept
high to low
0.6
CS swept
low to high
0.4
0.2
0.0
0.0
0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4
Chip Select Voltage (V)
FIGURE 2-21:
Quiescent Current vs.
Chip Select (CS) Voltage at VDD = 2.4V
(MCP6293 and MCP6295 only).
DS21812E-page 8
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
Chip Select Voltage (V)
FIGURE 2-24:
Quiescent Current vs.
Chip Select (CS) Voltage at VDD = 5.5V
(MCP6293 and MCP6295 only).
© 2007 Microchip Technology Inc.
MCP6291/1R/2/3/4/5
TYPICAL PERFORMANCE CURVES (CONTINUED)
Note: Unless otherwise indicated, TA = +25°C, VDD = +2.4V to +5.5V, VSS = GND, VCM = VDD/2, VOUT ≈ VDD/2,
VL = VDD/2, RL = 10 kΩ to VL, CL = 60 pF, and CS is tied low.
5.0
5.0
G = +1V/V
VDD = 5.0V
4.5
Output Voltage (V)
Output Voltage (V)
4.0
3.5
3.0
2.5
2.0
1.5
1.0
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.5
0.0
G = -1V/V
VDD = 5.0V
4.5
0.E+00
1.E-06
2.E-06
3.E-06
4.E-06
5.E-06
6.E-06
7.E-06
8.E-06
9.E-06
0.0
1.E-05
0.E+00
1.E-06
2.E-06
3.E-06
4.E-06
FIGURE 2-25:
Pulse Response.
5.E-06
6.E-06
7.E-06
Large-Signal Non-inverting
FIGURE 2-28:
Response.
9.E-06
1.E-05
Large-Signal Inverting Pulse
G = -1V/V
Output Voltage (10 mV/div)
Output Voltage (10 mV/div)
G = +1V/V
Time (200 ns/div)
Time (200 ns/div)
Small-Signal Non-inverting
3.0
2.0
1.5
Output On
VOUT
1.0
0.5
Output High-Z
0.0
0.E+00
5.E-06
1.E-05
2.E-05
2.E-05
3.E-05
3.E-05
4.E-05
4.E-05
5.E-05
5.E-05
Time (5 µs/div)
FIGURE 2-27:
Chip Select (CS) to
Amplifier Output Response Time at VDD = 2.4V
(MCP6293 and MCP6295 only).
© 2007 Microchip Technology Inc.
Small-Signal Inverting Pulse
6.0
VDD = 2.4V
G = +1V/V
VIN = VSS
CS Voltage
2.5
FIGURE 2-29:
Response.
Chip Select, Output Voltages
(V)
FIGURE 2-26:
Pulse Response.
Chip Select, Output Voltages
(V)
8.E-06
Time (1 µs/div)
Time (1 µs/div)
VDD = 5.5V
G = +1V/V
VIN = VSS
5.5
CS Voltage
5.0
4.5
4.0
3.5
VOUT
3.0
Output On
2.5
2.0
1.5
1.0
Output High-Z
0.5
0.0
0.E+00
5.E-06
1.E-05
2.E-05
2.E-05
3.E-05
3.E-05
4.E-05
4.E-05
5.E-05
5.E-05
Time (5 µs/div)
FIGURE 2-30:
Chip Select (CS) to
Amplifier Output Response Time at VDD = 5.5V
(MCP6293 and MCP6295 only).
DS21812E-page 9
MCP6291/1R/2/3/4/5
TYPICAL PERFORMANCE CURVES (CONTINUED)
Note: Unless otherwise indicated, TA = +25°C, VDD = +2.4V to +5.5V, VSS = GND, VCM = VDD/2, VOUT ≈ VDD/2,
VL = VDD/2, RL = 10 kΩ to VL, CL = 60 pF, and CS is tied low.
6
+125°C
+85°C
+25°C
-40°C
-1.0 -0.9 -0.8 -0.7 -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0.0
Input Voltage (V)
FIGURE 2-31:
Measured Input Current vs.
Input Voltage (below VSS).
DS21812E-page 10
Input, Output Voltage (V)
Input Current Magnitude (A)
1.E-02
10m
1m
1.E-03
100µ
1.E-04
10µ
1.E-05
1µ
1.E-06
100n
1.E-07
10n
1.E-08
1n
1.E-09
100p
1.E-10
10p
1.E-11
1p
1.E-12
VDD = 5.0V
G = +2V/V
5
4
VOUT
VIN
3
2
1
0
-1
-15
-14
-13
-12
-11
-10
-9
-8
-7
-6
-5
Time (1 ms/div)
FIGURE 2-32:
The MCP6291/1R/2/3/4/5
Show No Phase Reversal.
© 2007 Microchip Technology Inc.
MCP6291/1R/2/3/4/5
3.0
PIN DESCRIPTIONS
Descriptions of the pins are listed in Table 3-1 (single op amps) and Table 3-2 (dual and quad op amps).
TABLE 3-1:
PIN FUNCTION TABLE FOR SINGLE OP AMPS
MCP6291
MCP6293
MCP6291R
SOT-23-6
1
6
1
4
4
2
3
3
3
7
5
2
4
2
5
SOT-23-5
6
1
2
3
VOUT
Analog Output
4
VIN–
Inverting Input
3
VIN+
Non-inverting Input
7
6
VDD
Positive Power Supply
4
2
VSS
Negative Power Supply
—
—
—
8
5
CS
Chip Select
—
—
1,5
—
NC
No Internal Connection
MCP6292
PIN FUNCTION TABLE FOR DUAL AND QUAD OP AMPS
MCP6294
MCP6295
Symbol
1
1
—
VOUTA
Analog Output (op amp A)
2
2
2
VINA–
Inverting Input (op amp A)
Non-inverting Input (op amp A)
3
3
3
VINA+
8
4
8
VDD
Description
Positive Power Supply
5
5
—
VINB+
Non-inverting Input (op amp B)
6
6
6
VINB–
Inverting Input (op amp B)
7
7
7
VOUTB
Analog Output (op amp B)
—
8
—
VOUTC
Analog Output (op amp C)
—
9
—
VINC–
Inverting Input (op amp C)
—
10
—
VINC+
Non-inverting Input (op amp C)
Negative Power Supply
4
11
4
VSS
—
12
—
VIND+
Non-inverting Input (op amp D)
—
13
—
VIND–
Inverting Input (op amp D)
—
14
—
VOUTD
Analog Output (op amp D)
—
—
1
VOUTA/VINB+
—
—
5
CS
Analog Output (op amp A)/Non-inverting Input (op amp B)
Chip Select
Analog Outputs
The output pins are low-impedance voltage sources.
3.2
Analog Inputs
The non-inverting and inverting inputs are highimpedance CMOS inputs with low bias currents.
3.3
Description
1,5,8
TABLE 3-2:
3.1
Symbol
PDIP, SOIC,
MSOP
PDIP, SOIC,
MSOP
MCP6295’s VOUTA/VINB+ Pin
For the MCP6295 only, the output of op amp A is
connected directly to the non-inverting input of
op amp B; this is the VOUTA/VINB+ pin. This connection
makes it possible to provide a Chip Select pin for duals
in 8-pin packages.
© 2007 Microchip Technology Inc.
3.4
Chip Select Digital Input
This is a CMOS, Schmitt-triggered input that places the
part into a low power mode of operation.
3.5
Power Supply Pins
The positive power supply (VDD) is 2.4V to 6.0V higher
than the negative power supply (VSS). For normal
operation, the other pins are between VSS and VDD.
Typically, these parts are used in a single (positive)
supply configuration. In this case, VSS is connected to
ground and VDD is connected to the supply. VDD will
need bypass capacitors
DS21812E-page 11
MCP6291/1R/2/3/4/5
4.0
APPLICATION INFORMATION
The MCP6291/1R/2/3/4/5 family of op amps is
manufactured using Microchip’s state of the art CMOS
process, specifically designed for low-cost, low-power
and general purpose applications. The low supply
voltage, low quiescent current and wide bandwidth
makes the MCP6291/1R/2/3/4/5 ideal for battery-powered applications.
4.1
VDD, and dump any currents onto VDD. When
implemented as shown, resistors R1 and R2 also limit
the current through D1 and D2.
VDD
D1
V1
Rail-to-Rail Inputs
4.1.1
R1
INPUT VOLTAGE AND CURRENT
LIMITS
The ESD protection on the inputs can be depicted as
shown in Figure 4-1. This structure was chosen to
protect the input transistors, and to minimize input bias
current (IB). The input ESD diodes clamp the inputs
when they try to go more than one diode drop below
VSS. They also clamp any voltages that go too far
above VDD; their breakdown voltage is high enough to
allow normal operation, and low enough to bypass
quick ESD events within the specified limits.
VDD Bond
Pad
Input
Stage
Bond
VIN–
Pad
VSS Bond
Pad
FIGURE 4-1:
Structures.
Simplified Analog Input ESD
In order to prevent damage and/or improper operation
of these op amps, the circuit they are in must limit the
currents and voltages at the VIN+ and VIN– pins (see
Absolute Maximum Ratings †” at the beginning of
Section 1.0 “Electrical Characteristics”). Figure 4-2
shows the recommended approach to protecting these
inputs. The internal ESD diodes prevent the input pins
(VIN+ and VIN–) from going too far below ground, and
the resistors R1 and R2 limit the possible current drawn
out of the input pins. Diodes D1 and D2 prevent the
input pins (VIN+ and VIN–) from going too far above
DS21812E-page 12
VOUT
R2
VSS – (minimum expected V1)
2 mA
VSS – (minimum expected V2)
R2 >
2 mA
R1 >
FIGURE 4-2:
Inputs.
Protecting the Analog
It is also possible to connect the diodes to the left of the
resistor R1 and R2. In this case, the currents through
the diodes D1 and D2 need to be limited by some other
mechanism. The resistors then serve as in-rush current
limiters; the DC current into the input pins (VIN+ and
VIN–) should be very small.
A significant amount of current can flow out of the
inputs when the common mode voltage (VCM) is below
ground (VSS); see Figure 2-31. Applications that are
high impedance may need to limit the usable voltage
range.
4.1.3
VIN+ Bond
Pad
MCP629X
V2
PHASE REVERSAL
The MCP6291/1R/2/3/4/5 op amp is designed to
prevent phase reversal when the input pins exceed the
supply voltages. Figure 2-32 shows the input voltage
exceeding the supply voltage without any phase reversal.
4.1.2
D2
NORMAL OPERATION
The input stage of the MCP6291/1R/2/3/4/5 op amps
use two differential CMOS input stages in parallel. One
operates at low common mode input voltage (VCM),
while the other operates at high VCM. WIth this topology, the device operates with VCM up to 0.3V past
either supply rail. The input offset voltage (VOS) is measured at VCM = VSS - 0.3V and VDD + 0.3V to ensure
proper operation.
The transition between the two input stages occurs
when VCM = VDD - 1.1V. For the best distortion and gain
linearity, with non-inverting gains, avoid this region of
operation.
4.2
Rail-to-Rail Output
The output voltage range of the MCP6291/1R/2/3/4/5
op amp is VDD – 15 mV (min.) and VSS + 15 mV
(maximum) when RL = 10 kΩ is connected to VDD/2
and VDD = 5.5V. Refer to Figure 2-16 for more
information.
© 2007 Microchip Technology Inc.
MCP6291/1R/2/3/4/5
4.3
Capacitive Loads
4.4
Driving large capacitive loads can cause stability
problems for voltage feedback op amps. As the load
capacitance increases, the feedback loop’s phase
margin decreases and the closed-loop bandwidth is
reduced. This produces gain peaking in the frequency
response, with overshoot and ringing in the step
response. A unity-gain buffer (G = +1) is the most
sensitive to capacitive loads, though all gains show the
same general behavior.
When driving large capacitive loads with these op
amps (e.g., > 100 pF when G = +1), a small series
resistor at the output (RISO in Figure 4-3) improves the
feedback loop’s phase margin (stability) by making the
output load resistive at higher frequencies. The
bandwidth will be generally lower than the bandwidth
with no capacitive load.
–
RISO
MCP629X
VOUT
+
VIN
CL
MCP629X Chip Select
The MCP6293 and MCP6295 are single and dual op
amps with Chip Select (CS), respectively. When CS is
pulled high, the supply current drops to 0.7 µA (typical)
and flows through the CS pin to VSS. When this
happens, the amplifier output is put into a high-impedance state. By pulling CS low, the amplifier is enabled.
The CS pin has an internal 5 MΩ (typical) pull-down
resistor connected to VSS, so it will go low if the CS pin
is left floating. Figure 1-1 shows the output voltage and
supply current response to a CS pulse.
4.5
Cascaded Dual Op Amps
(MCP6295)
The MCP6295 is a dual op amp with Chip Select (CS).
The Chip Select input is available on what would be the
non-inverting input of a standard dual op amp (pin 5).
This is available because the output of op amp A
connects to the non-inverting input of op amp B, as
shown in Figure 4-5. The Chip Select input, which can
be connected to a microcontroller I/O line, puts the
device in Low-power mode. Refer to Section 4.4
“MCP629X Chip Select”.
VOUTA/VINB+ VINB–
FIGURE 4-3:
Output Resistor, RISO
stabilizes large capacitive loads.
1
Figure 4-4 gives recommended RISO values for
different capacitive loads and gains. The x-axis is the
normalized load capacitance (CL/GN), where GN is the
circuit's noise gain. For non-inverting gains, GN and the
Signal Gain are equal. For inverting gains, GN is
1+|Signal Gain| (e.g., -1 V/V gives GN = +2 V/V).
VINA–
VINA+
6
2
3
B
A
7
VOUTB
MCP6295
5
CS
100
Recommended R ISO (Ω)
FIGURE 4-5:
The output of op amp A is loaded by the input impedance of op amp B, which is typically 1013Ω||6 pF, as
specified in the DC specification table (Refer to
Section 4.3 “Capacitive Loads” for further details
regarding capacitive loads).
GN = 1 V/V
GN ≥ 2 V/V
10
10
100
1,000
Cascaded Gain Amplifier.
10,000
Normalized Load Capacitance; CL/GN (pF)
FIGURE 4-4:
Recommended RISO Values
for Capacitive Loads.
The common mode input range of these op amps is
specified in the data sheet as VSS – 300 mV and
VDD + 300 mV. However, since the output of op amp A
is limited to VOL and VOH (20 mV from the rails with a
10 kΩ load), the non-inverting input range of op amp B
is limited to the common mode input range of
VSS + 20 mV and VDD – 20 mV.
After selecting RISO for your circuit, double-check the
resulting frequency response peaking and step
response overshoot. Modify RISO's value until the
response is reasonable. Bench evaluation and
simulations with the MCP6291/1R/2/3/4/5 SPICE
macro model are helpful.
© 2007 Microchip Technology Inc.
DS21812E-page 13
MCP6291/1R/2/3/4/5
4.6
Supply Bypass
4.8
With this family of operational amplifiers, the power
supply pin (VDD for single supply) should have a local
bypass capacitor (i.e., 0.01 µF to 0.1 µF) within 2 mm
for good high-frequency performance. It also needs a
bulk capacitor (i.e., 1 µF or larger) within 100 mm to
provide large, slow currents. This bulk capacitor can be
shared with nearby analog parts.
4.7
Unused Op Amps
An unused op amp in a quad package (MCP6294)
should be configured as shown in Figure 4-6. These
circuits prevent the output from toggling and causing
crosstalk. Circuits A sets the op amp at its minimum
noise gain. The resistor divider produces any desired
reference voltage within the output voltage range of the
op amp; the op amp buffers that reference voltage.
Circuit B uses the minimum number of components
and operates as a comparator, but it may draw more
current.
¼ MCP6294 (A)
In applications where low input bias current is critical,
Printed Circuit Board (PCB) surface-leakage effects
need to be considered. Surface leakage is caused by
humidity, dust or other contamination on the board.
Under low humidity conditions, a typical resistance
between nearby traces is 1012Ω. A 5V difference would
cause 5 pA of current to flow, which is greater than the
MCP6291/1R/2/3/4/5 family’s bias current at 25°C
(1 pA, typical).
The easiest way to reduce surface leakage is to use a
guard ring around sensitive pins (or traces). The guard
ring is biased at the same voltage as the sensitive pin.
An example of this type of layout is shown in
Figure 4-7.
VIN–
VIN+
VSS
¼ MCP6294 (B)
VDD
R1
PCB Surface Leakage
VDD
Guard Ring
VDD
R2
VREF
FIGURE 4-7:
for Inverting Gain.
1.
R2
V REF = V DD ⋅ -----------------R1 + R2
FIGURE 4-6:
Unused Op Amps.
2.
DS21812E-page 14
Example Guard Ring Layout
For Inverting Gain and Transimpedance
Amplifiers (convert current to voltage, such as
photo detectors):
a. Connect the guard ring to the non-inverting
input pin (VIN+). This biases the guard ring
to the same reference voltage as the op
amp (e.g., VDD/2 or ground).
b. Connect the inverting pin (VIN–) to the input
with a wire that does not touch the PCB
surface.
Non-inverting Gain and Unity-Gain Buffer:
a. Connect the non-inverting pin (VIN+) to the
input with a wire that does not touch the
PCB surface.
b. Connect the guard ring to the inverting input
pin (VIN–). This biases the guard ring to the
common mode input voltage.
© 2007 Microchip Technology Inc.
MCP6291/1R/2/3/4/5
4.9
Application Circuits
4.9.1
4.9.3
MULTIPLE FEEDBACK LOW-PASS
FILTER
The MCP6291/1R/2/3/4/5 op amp can be used in
active-filter applications. Figure 4-8 shows an inverting,
third-order, multiple feedback low-pass filter that can be
used as an anti-aliasing filter.
R1
R2
R4
VOUT
VIN
C1
R3
C4
C3
CASCADED OP AMP
APPLICATIONS
The MCP6295 provides the flexibility of Low-power
mode for dual op amps in an 8-pin package. The
MCP6295 eliminates the added cost and space in
battery-powered applications by using two single op
amps with Chip Select lines or a 10-pin device with one
Chip Select line for both op amps. Since the two op
amps are internally cascaded, this device cannot be
used in circuits that require active or passive elements
between the two op amps. However, there are several
applications where this op amp configuration with
Chip Select line becomes suitable. The circuits below
show possible applications for this device.
4.9.3.1
MCP6291
VDD/2
FIGURE 4-8:
Pass Filter.
Multiple Feedback Low-
Load Isolation
With the cascaded op amp configuration, op amp B can
be used to isolate the load from op amp A. In applications where op amp A is driving capacitive or low
resistance loads in the feedback loop (such as an
integrator circuit or filter circuit), the op amp may not
have sufficient source current to drive the load. In this
case, op amp B can be used as a buffer.
This filter, and others, can be designed using
Microchip’s Filter design software. Refer to Section 5.0
“Design Aids”
4.9.2
B
PHOTODIODE AMPLIFIER
VOUTB
A
Figure 4-9 shows a photodiode biased in the photovoltaic mode for high precision. The resistor R converts
the diode current ID to the voltage VOUT. The capacitor
is used to limit the bandwidth or to stabilize the circuit
against the diode’s capacitance (it is not always
needed).
MCP6295
Load
CS
FIGURE 4-10:
Buffer.
Isolating the Load with a
C
R
ID
VOUT
light
MCP6291
VDD/2
FIGURE 4-9:
Photodiode Amplifier.
© 2007 Microchip Technology Inc.
DS21812E-page 15
MCP6291/1R/2/3/4/5
4.9.3.2
Cascaded Gain
4.9.3.4
Figure 4-11 shows a cascaded gain circuit configuration with Chip Select. Op amps A and B are configured
in a non-inverting amplifier configuration. In this configuration, it is important to note that the input offset voltage of op amp A is amplified by the gain of op amp A
and B, as shown below:
V OUT = V IN G A G B + V OSA G A G B + V OSB G B
Buffered Non-inverting Integrator
Figure 4-13 shows a lossy non-inverting integrator that
is buffered and has a Chip Select input. Op amp A is
configured as a non-inverting integrator. In this configuration, matching the impedance at each input is
recommended. R F is used to provide a feedback loop
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