MCP6566/6R/6U/7/9
1.8V Low-Power Open-Drain Output Comparator
Features
Description
• Propagation Delay at 1.8 VDD:
- 56 ns (typical) high-to-low
• Low Quiescent Current: 100 µA (typical)
• Input Offset Voltage: ±3 mV (typical)
• Rail-to-Rail Input: VSS – 0.3V to VDD + 0.3V
• Open-Drain Output
• Wide Supply Voltage Range: 1.8V to 5.5V
• Available in Single, Dual and Quad
• Packages: SC70, SOT-23, SOIC, MSOP, TSSOP
The Microchip MCP6566/6R/6U/7/9 family of opendrain output comparators is offered in single, dual and
quad configurations.
Typical Applications
Laptop Computers
Mobile Phones
Handheld Electronics
RC Timers
Alarm and Monitoring Circuits
Window Comparators
Multivibrators
This family operates with a single-supply voltage of 1.8V
to 5.5V while drawing less than 100 µA/comparator of
quiescent current (typical).
Package Types
MCP6566R
5-Lead SOT-23
+IN 3
VDD
R2
5 VSS
OUTA 1
-INA 2
4 -IN
R3
14 OUTD
+INA 3
VOUT
13 -IND
12 +IND
VDD 4
11 VSS
+INB 5
10 +INC
-INB 6
9 -INC
OUTB 7
MCP656X
+
5 +INB
–
+
–
6 -INB
MCP6569
14-Lead SOIC, TSSOP
+5 VDD
VIN
7 OUTB
+
–
+INA 3
+
–
+3 VPU
4 -IN
VSS 4
OUT 1
VDD 2
Typical Application Circuit
-INA 2
+
–
• Push-Pull Output: MCP6561/1R/1U/2/4
+IN 3
8 VDD
OUTA 1
5 VDD
–
+
Related Device
OUT 1
VSS 2
MCP6567
8-Lead SOIC, MSOP
+
–
Microchip Advanced Part Selector (MAPS)
Analog Demonstration and Evaluation Boards
Application Notes
SPICE Macro Model
MCP6566
5-Lead SOT-23, SC70
+
–
Design Aids
•
•
•
•
The open-drain output of the MCP6566/6R/6U/7/9
family requires a pull-up resistor. It supports pull-up
voltages that are above and below VDD, which can be
used to level shift. The output toggle frequency can
reach a typical 4 MHz (typical) while limiting supply
current surges and dynamic power consumption during
switching.
+
–
•
•
•
•
•
•
•
These comparators are optimized for low-power 1.8V,
single-supply applications with greater than rail-to-rail
input operation. The internal input hysteresis eliminates
output switching due to internal input noise voltage,
reducing current draw.
8 OUTC
MCP6566U
5-Lead SOT-23
RF
2009-2020 Microchip Technology Inc.
VIN+ 1
VSS 2
VIN- 3
+
–
5 VDD
4 OUT
DS20002143G-page 1
MCP6566/6R/6U/7/9
NOTES:
DS20002143G-page 2
2009-2020 Microchip Technology Inc.
MCP6566/6R/6U/7/9
1.0
ELECTRICAL
CHARACTERISTICS
1.1
Absolute Maximum Ratings†
†
Notice: Stresses above those listed under “Maximum
Ratings” may cause permanent damage to the device.
This is a stress rating only and functional operation of the
device at those or any other conditions above those
indicated in the operational listings of this specification is
not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability.
†† See Section 4.1.2 “Input Voltage and Current Limits”.
VDD – VSS ........................................................................6.5V
Open-Drain Output.............................................. VSS + 10.5V
All Other Inputs and Outputs.......... VSS – 0.3V to VDD + 0.3V
Analog Input (VIN)†† ...................... VSS – 1.0V to VDD + 1.0V
Difference Input voltage ...................................... |VDD – VSS|
Output Short-Circuit Current ......................................±25 mA
Current at Input Pins ....................................................±2 mA
Current at Output and Supply Pins ............................±50 mA
Storage Temperature ....................................-65°C to +150°C
Ambient Temperature with Power Applied.......-40°C to +125°C
Junction Temperature ................................................. +150°C
ESD Protection on All Pins (HBM/MM) 4 kV/300V
DC CHARACTERISTICS
Electrical Characteristics: Unless otherwise indicated: VDD = +1.8V to +5.5V, VSS = GND, TA = +25°C, VIN+ = VDD/2, VIN- = VSS
and RPULL_UP = 20 k to VPU = VDD (see Figure 1-1).
Parameters
Symbol
Min
Typ
Max
Units
Conditions
VDD
1.8
—
5.5
V
IQ
60
100
130
µA
IOUT = 0
PSRR
63
70
—
dB
VCM = VSS
VCM = VSS (Note 1)
Power Supply
Supply Voltage
Quiescent Current per Comparator
Power Supply Rejection Ratio
Input
Input Offset Voltage
Input Offset Drift
Input Offset Current
Input Bias Current
Input Hysteresis Voltage
VOS
-10
3
+10
mV
VOS/T
—
2
—
µV/°C
VCM = VSS
IOS
—
1
—
pA
VCM = VSS
IB
—
1
—
pA
TA = +25°C, VIN- = VDD/2
—
60
—
pA
TA = +85°C, VIN- = VDD/2
—
1500
5000
pA
TA = +125°C, VIN- = VDD/2
VHYST
1.0
—
5.0
mV
VCM = VSS (Notes 1, 2)
Input Hysteresis Linear Temp. Co.
TC1
—
10
—
µV/°C
Input Hysteresis Quadratic Temp. Co.
TC2
—
0.3
—
µV/°C2
Common-Mode Input Voltage Range
VCMR
VSS – 0.2
—
VDD + 0.2
V
VDD = 1.8V
VSS – 0.3
—
VDD + 0.3
V
VDD = 5.5V
54
66
—
dB
VCM = -0.3V to VDD + 0.3V, VDD = 5.5V
50
63
—
dB
VCM = VDD/2 to VDD + 0.3V, VDD = 5.5V
54
65
—
dB
VCM = -0.3V to VDD/2, VDD = 5.5V
—
1013||4
—
||pF
—
1013||2
—
||pF
Common-Mode Rejection Ratio
Common-Mode Input Impedance
Differential Input Impedance
Note 1:
CMRR
ZCM
ZDIFF
The input offset voltage is the center of the input referred trip points. The input hysteresis is the difference between the
input referred trip points.
2:
VHYST at different temperatures is estimated using VHYST (TA) = VHYST @ +25°C + (TA – 25°C) TC1 + (TA – 25°C)2 TC2.
3:
Limit the output current to an absolute maximum rating of 50 mA.
4:
The pull-up voltage for the open-drain output VPULL_UP can be as high as the absolute maximum rating of 10.5V. In this
case, IOH_leak can be higher than 1 µA (see Figure 2-30).
2009-2020 Microchip Technology Inc.
DS20002143G-page 3
MCP6566/6R/6U/7/9
DC CHARACTERISTICS (CONTINUED)
Electrical Characteristics: Unless otherwise indicated: VDD = +1.8V to +5.5V, VSS = GND, TA = +25°C, VIN+ = VDD/2, VIN- = VSS
and RPULL_UP = 20 k to VPU = VDD (see Figure 1-1).
Parameters
Symbol
Min
Typ
Max
Units
VPULL_UP
1.6
VOH
—
—
5.5
V
—
VPULL_UP
V
IOH_leak
—
VOL
—
—
1
µA
—
0.6
V
ISC
—
±30
—
mA
COUT
—
8
—
pF
Conditions
Push-Pull Output
Pull-up Voltage
High-Level Output Voltage
High-Level Output Current Leakage
Low-Level Output Voltage
Short-Circuit Current (Note 3)
Output Pin Capacitance
Note 1:
See Figure 1-1 (Notes 3, 4)
Note 4
IOUT = 3 mA/8 mA @ VDD = 1.8V/5.5V
Not to exceed absolute max. rating
The input offset voltage is the center of the input referred trip points. The input hysteresis is the difference between the
input referred trip points.
2:
VHYST at different temperatures is estimated using VHYST (TA) = VHYST @ +25°C + (TA – 25°C) TC1 + (TA – 25°C)2 TC2.
3:
Limit the output current to an absolute maximum rating of 50 mA.
4:
The pull-up voltage for the open-drain output VPULL_UP can be as high as the absolute maximum rating of 10.5V. In this
case, IOH_leak can be higher than 1 µA (see Figure 2-30).
AC CHARACTERISTICS
Electrical Characteristics: Unless otherwise indicated: VDD = +1.8V to +5.5V, VSS = GND, TA = +25°C,
VIN+ = VDD/2, VIN- = VSS, RPULL_UP = 20 k to VPU = VDD and CL = 25 pF (see Figure 1-1).
Parameters
Symbol
Min
Typ
Max
Units
Conditions
tPHL
—
56
80
ns
VCM = VDD/2, VDD = 1.8V (Note 2)
—
34
80
ns
VCM = VDD/2, VDD = 5.5V
Propagation Delay
High-to-Low,100 mV Overdrive
Output
tF
—
20
—
ns
Maximum Toggle Frequency
fTG
—
4
—
MHz
VDD = 5.5V
—
2
—
MHz
VDD = 1.8V
Input Voltage Noise
ENI
—
350
—
µVP-P
10 Hz to 10 MHz (Note 1)
Fall Time
Note 1:
2:
ENI is based on SPICE simulation.
Rise time, tR and tPLH, depend on the load (RL and CL). These specifications are valid for the specified
load only.
TEMPERATURE SPECIFICATIONS
Electrical Characteristics: Unless otherwise indicated: VDD = +1.8V to +5.5V and VSS = GND.
Parameters
Symbol
Min
Typ
Max
Units
Specified Temperature Range
TA
-40
—
+125
°C
Operating Temperature Range
TA
-40
—
+125
°C
Storage Temperature Range
TA
-65
—
+150
°C
Thermal Resistance, 5-Lead SC70
JA
—
331
—
°C/W
Thermal Resistance, 5-Lead SOT-23
JA
—
201
—
°C/W
Thermal Resistance, 8-Lead MSOP
JA
—
211
—
°C/W
Thermal Resistance, 8-Lead SOIC
JA
—
149
—
°C/W
Thermal Resistance, 14-Lead SOIC
JA
—
91
—
°C/W
Thermal Resistance, 14-Lead TSSOP
JA
—
100
—
°C/W
Conditions
Temperature Ranges
Thermal Package Resistances
DS20002143G-page 4
2009-2020 Microchip Technology Inc.
MCP6566/6R/6U/7/9
1.2
Test Circuit Configuration
This test circuit configuration is used to determine the
AC and DC specifications.
VDD
MCP656X
VPU = VDD
200 k
+
IOUT
VOUT
25 pF
200 k
–
VIN = VSS
RPU
20 k
VSS = 0V
FIGURE 1-1:
AC and DC Test Circuit for
the Open-Drain Output Comparators.
2009-2020 Microchip Technology Inc.
DS20002143G-page 5
MCP6566/6R/6U/7/9
NOTES:
DS20002143G-page 6
2009-2020 Microchip Technology Inc.
MCP6566/6R/6U/7/9
2.0
TYPICAL PERFORMANCE CURVES
Note:
The graphs and tables provided following this note are a statistical summary based on a limited number of
samples and are provided for informational purposes only. The performance characteristics listed herein
are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified
operating range (e.g., outside specified power supply range) and therefore outside the warranted range.
Note: Unless otherwise indicated, VDD = +1.8V to +5.5V, VSS = GND, TA = +25°C, VIN+ = VDD /2, VIN - = GND,
RL = 20 k to VPU = VDD and CL = 25 pF.
40%
30%
30%
VDD = 5.5V
VCM = VSS
Avg. = -0.9 mV
StDev = 2.1 mV
3588 units
VDD = 1.8V
VCM = VSS
Avg. = -0.1 mV
StDev = 2.1 mV
3588 units
Occurrences (%)
Occurrences (%)
50%
20%
10%
0%
-6
FIGURE 2-1:
40%
-4
-2 0
2
VOS (mV)
4
6
8
Input Offset Voltage.
10%
1.0
0%
36
48
Input Offset Voltage Drift.
VDD = 5.5V
VIN -
VOUT
3.0
2.0
1.0
0.0
2.5 3.0 3.5
VHYST (mV)
4.0
4.5
5.0
Input Hysteresis Voltage.
Time (3 µs/div)
Input vs. Output Signal, No
2009-2020 Microchip Technology Inc.
VDD = 1.8V
Avg. = 12 µV/°C
StDev = 0.6 µV/°C
20%
1380 Units
TA = -40°C to 125°C
VCM = VSS
10%
2
4
6
8 10 12 14 16
VHYST Drift, TC1 (µV/°C)
18
20
FIGURE 2-5:
Input Hysteresis Voltage
Drift – Linear Temp. Co. (TC1).
30%
20%
10%
VDD = 5.5V
VDD = 1.8V
Avg. = 0.25 µV/°C2
2
StDev = 0.1 µV/°C
Avg. = 0.3 µV/°C
StDev = 0.2 µV/°C 2
2
1380 Units
TA = -40°C to +125°C
VCM = VSS
0%
-0.50
-1.0
FIGURE 2-3:
Phase Reversal.
2.0
30%
0
VIN+ = VDD /2
5.0
VOUT (V)
40%
60
Occurrences (%)
FIGURE 2-2:
1.5
VDD = 5.5V
Avg. = 10.4 µV/°C
StDev = 0.6 µV/°C
50%
0%
-60 -48 -36 -24 -12 0 12 24
VOS Drift (µV/°C)
4.0
5%
60%
VCM = VSS
Avg. = 0.9 µV/°C
StDev = 6.6 µV/°C
1380 Units
TA = -40°C to +125°C
20%
6.0
10%
FIGURE 2-4:
30%
7.0
15%
10
Occurrences (%)
Occurrences (%)
50%
20%
VDD = 5.5V
Avg. = 3.6 mV
StDev = 0.1 mV
3588 units
0%
-10 -8
60%
VDD = 1.8V
Avg. = 3.4 mV
StDev = 0.2 mV
3588 units
25%
-0.25
0.00
0.25
0.50
0.75
2
VHYST Drift, TC2 (µV/°C )
1.00
FIGURE 2-6:
Input Hysteresis Voltage
Drift – Quadratic Temp. Co. (TC2).
DS20002143G-page 7
MCP6566/6R/6U/7/9
Note: Unless otherwise indicated, VDD = +1.8V to +5.5V, VSS = GND, TA = +25°C, VIN+ = VDD /2, VIN - = GND,
RL = 20 k to VPU = VDD and CL = 25 pF.
3.0
5.0
VCM = VSS
2.0
VCM = VSS
VDD = 1.8V
VHYST (mV)
V OS (mV)
4.0
1.0
0.0
-1.0
3.0
VDD= 1.8V
2.0
VDD = 5.5V
-2.0
VDD= 5.0V
-3.0
1.0
-50
-25
0
FIGURE 2-7:
Temperature.
4.0
25
50
75
Temperature (°C)
100
125
Input Offset Voltage vs.
-50
-25
0
FIGURE 2-10:
Temperature.
25
50
75
Temperature (°C)
5.0
VDD = 1.8V
2.0
TA= +125°C
4.0
V HYST (mV)
TA= +85°C
0.0
TA= +25°C
TA= -40°C
-2.0
3.0
TA= +25°C
2.0
TA= +85°C
VDD = 1.8V
-4.0
-0.3
0.0
0.3
0.6
0.9 1.2
VCM (V)
1.5
1.8
1.0
-0.3
2.1
FIGURE 2-8:
Input Offset Voltage vs.
Common-Mode Input Voltage.
3.0
TA= +25°C
0.0
-1.0
0.9
1.2
VCM (V)
1.5
1.8
2.1
-2.0
3.0
TA= -40°C
TA= +25°C
TA= +85°C
TA= +125°C
2.0
TA= +85°C
TA= +125°C
1.0
2.0
3.0
VCM (V)
4.0
5.0
FIGURE 2-9:
Input Offset Voltage vs.
Common-Mode Input Voltage.
DS20002143G-page 8
0.6
4.0
TA= -40°C
1.0
0.0
0.3
5.0
VDD = 5.5V
V HYST (mV)
VOS (mV)
0.0
TA= -40°C
FIGURE 2-11:
Input Hysteresis Voltage vs.
Common-Mode Input Voltage.
2.0
-3.0
-1.0
125
Input Hysteresis Voltage vs.
TA= +125°C
VOS (mV)
100
6.0
1.0
-0.5
0.5
1.5
VDD = 5.5V
2.5
3.5
VCM (V)
4.5
5.5
FIGURE 2-12:
Input Hysteresis Voltage vs.
Common-Mode Input Voltage.
2009-2020 Microchip Technology Inc.
MCP6566/6R/6U/7/9
Note: Unless otherwise indicated, VDD = +1.8V to +5.5V, VSS = GND, TA = +25°C, VIN+ = VDD /2, VIN - = GND,
RL = 20 k to VPU = VDD and CL = 25 pF.
3.0
5.0
0.0
TA= +125°C
TA= +85°C
4.0
TA= -40°C
TA= +25°C
TA= +85°C
TA= +125°C
1.0
V HYST (mV)
VOS (mV)
2.0
-1.0
TA= +25°C
3.0
TA= -40°C
2.0
-2.0
-3.0
1.0
1.5
2.5
3.5
VDD (V)
4.5
5.5
1.5
FIGURE 2-13:
Input Offset Voltage vs.
Supply Voltage vs. Temperature.
4.5
5.5
140.0
VDD = 5.5V
Avg. = 97 µA
StDev= 4 µA
1794 units
VDD = 1.8V
Avg. = 88 µA
StDev= 4 µA
1794 units
40%
30%
20%
120.0
100.0
IQ (µA)
Occurrences (%)
3.5
VDD (V)
FIGURE 2-16:
Input Hysteresis Voltage vs.
Supply Voltage vs. Temperature.
50%
80.0
60.0
TA= -40°C
TA= +25°C
TA= +85°C
TA= +125°C
40.0
10%
20.0
0%
0.0
60
70
FIGURE 2-14:
130
120
80
90
100
IQ (µA)
110
120
130
Quiescent Current.
0.0
130
VDD = 1.8V
120
2.0
IQ (µA)
Sweep VIN+ ,VIN - = VDD/2
90
80
0.0
0.5
1.0
VCM (V)
1.5
2.0
FIGURE 2-15:
Quiescent Current vs.
Common-mode Input Voltage.
2009-2020 Microchip Technology Inc.
4.0
5.0
6.0
Sweep VIN+ ,VIN - = VDD/2
100
90
Sweep VIN - ,VIN+ = VDD/2
80
Sweep VIN- ,VIN+ = VDD /2
V /2
70
3.0
V DD (V)
VDD = 5.5V
110
100
60
-0.5
1.0
FIGURE 2-17:
Quiescent Current vs.
Supply Voltage vs. Temperature.
110
IQ (µA)
2.5
70
2.5
60
-1.0
0.0
1.0
2.0
3.0
VCM (V)
4.0
5.0
6.0
FIGURE 2-18:
Quiescent Current vs.
Common-mode Input Voltage.
DS20002143G-page 9
MCP6566/6R/6U/7/9
Note: Unless otherwise indicated, VDD = +1.8V to +5.5V, VSS = GND, TA = +25°C, VIN+ = VDD /2, VIN - = GND,
RL = 20 k to VPU = VDD and CL = 25 pF.
150
150
IDD Spike near VPU = 0.9V
VDD = 5.5 V
VDD = 5.5V
VDD = 4.5V
VDD = 3.5V
100
VDD = 1.8 V
Quiescent Current vs.
100 mV Over-Drive
VCM = VDD/2
RL = Open
350
-0.5
1.5
3.5
VPU - V DD (V)
5.5
7.5
9.5
100,000
0dB Output Attenuation
TA = +125°C
10,000
VDD = 5.5V
250
200
VDD = 1.8V
150
-2.5
FIGURE 2-22:
Quiescent Current vs.
Pull-up to Supply Voltage Difference.
IOH_leak (pA)
IQ (µA)
300
VDD = 2.0 V
50
-4.5
0.5 1.5 2.5 3.5 4.5 5.5 6.5 7.5 8.5 9.5 10.5
V PU (V)
400
VDD = 2.5 V
75
50
FIGURE 2-19:
Pull-up Voltage.
VDD = 3.5 V
100
VDD = 2.5V
VDD = 2.0V
VDD = 1.8V
75
VDD = 4.5 V
125
IQ (µA)
IQ (µA)
125
1,000
TA = +85°C
100
TA = +25°C
10
100
1
50
10
10
100
100
FIGURE 2-20:
Quiescent Current vs.
Toggle Frequency.
1000
1.5 2.5 3.5 4.5 5.5 6.5 7.5 8.5 9.5 10.5
VPU (V)
1k
10k 100000
100k 100000
1M
10M
1000
10000
1E+07
Toggle Frequency (Hz)
0
FIGURE 2-23:
Pull-up Voltage.
1000
VDD= 1.8V
VDD= 5.5V
800
VOL (mV)
VOL (mV)
800
Output Leakage Current vs.
600
TA = +125°C
TA = +85°C
TA = +25°C
TA = -40°C
400
200
TA = +125°C
125°C
TA = +85°C
TA = +25°C
TA = -40°C
600
400
200
0
0
0.0
3.0
FIGURE 2-21:
Output Current.
DS20002143G-page 10
6.0
9.0
IOUT (mA)
12.0
Output Headroom vs.
15.0
0
FIGURE 2-24:
Output Current.
5
10
15
IOUT (mA)
20
25
Output Headroom vs.
2009-2020 Microchip Technology Inc.
MCP6566/6R/6U/7/9
Note: Unless otherwise indicated, VDD = +1.8V to +5.5V, VSS = GND, TA = +25°C, VIN+ = VDD /2, VIN - = GND,
RL = 20 k to VPU = VDD and CL = 25 pF.
50%
VDD = 1.8V
100 mV Over-Drive
VCM = VDD /2
40%
Occurrences (%)
Occurrences (%)
50%
tPHL
Avg. = 54.4 ns
StDev= 2 ns
198 units
30%
20%
10%
0%
40%
30%
20%
10%
0%
30
35
40
45
50
55
60
65
70
75
80
30
35
40
45
Prop. Delay (ns)
FIGURE 2-25:
Delays.
High-to-Low Propagation
FIGURE 2-28:
Delays.
260
70
75
80
High-to-Low Propagation
100 mV Over-Drive
VCM = VDD/2
70
210
Prop. Delay (ns)
Prop. Delay (ns)
50 55 60 65
Prop. Delay (ns)
80
VCM = VDD/2
tPHL , VDD = 1.8V
160
110
tPHL , VDD = 5.5V
60
tPHL , VDD = 1.8V
60
50
40
30
10
tPHL , VDD = 5.5V
20
1
10
100
1000
-50
-25
Over-Drive (mV)
FIGURE 2-26:
Overdrive.
Propagation Delay vs. Input
FIGURE 2-29:
Temperature.
120
140
VCM = VDD /2
120
100
tPHL , 10 mV Over-Drive
80
60
tPHL , 100 mV Over-Drive
0
25
50
75
Temperature (°C)
20
40
0
-40
TA= -40°C
TA= +25°C
TA= +85°C
TA= +125°C
-120
1.5
FIGURE 2-27:
Supply Voltage.
2.5
3.5
V DD (V)
4.5
Propagation Delay vs.
2009-2020 Microchip Technology Inc.
5.5
125
Propagation Delay vs.
-80
40
100
TA= -40°C
TA= +25°C
TA= +85°C
TA= +125°C
80
ISC (mA)
Prop. Delay (ns)
VDD= 5.5V
100mV Over-Drive
VCM = VDD/2
tPHL
Avg. = 33 ns
StDev= 1 ns
198 units
0.0
1.0
2.0
3.0
VDD (V)
4.0
5.0
6.0
FIGURE 2-30:
Short-Circuit Current vs.
Supply Voltage vs. Temperature.
DS20002143G-page 11
MCP6566/6R/6U/7/9
Note: Unless otherwise indicated, VDD = +1.8V to +5.5V, VSS = GND, TA = +25°C, VIN+ = VDD /2, VIN - = GND,
RL = 20 k to VPU = VDD and CL = 25 pF.
80
80
VDD= 1.8V
100 mV Over-Drive
70
Prop. Delay (ns)
Prop. Delay (ns)
70
tPHL
60
50
40
20
0.00
tPHL
50
40
20
0.50
1.00
VCM (V)
1.50
2.00
FIGURE 2-31:
Propagation Delay vs.
Common-Mode Input Voltage.
0.0
10000
100mV Over-Drive
VCM = VDD /2
VDD = 1.8V, tPHL
Prop. Delay (ns)
100
10
VDD = 5.5V, tPHL
1
0.1
0.01
0.001
1
0.01
10
1000
5.0
6.0
tPLH
tPHL
10000
Prop. Delay (ns)
TA= -40°C
TA= +25°C
TA= +85°C
TA= +125°C
10p
1E+01
1.0
10.0
100.0
RPU (kΩ)
FIGURE 2-35:
Pull-up Resistor.
Propagation Delay vs.
10µ
1E+07
0.1p
1E-01
-0.8
4.0
100
1m
1E+09
1n
1E+03
3.0
VCM (V)
100 mV Over-Drive
VCM = VDD/2
0.1
10m
1E+11
100n
1E+05
2.0
10
0.1
1
10
100 1E+06
1000
100
1000
10000
100000
Capacitive Load (nf)
FIGURE 2-32:
Capacitive Load.
1.0
FIGURE 2-34:
Propagation Delay vs.
Common-Mode Input Voltage.
1000
Prop. Delay (µs)
60
30
30
Input Current (A)
VDD= 5.5V
100 mV Over-Drive
Propagation Delay vs.
100 mV Over-Drive
VCM = VDD /2
tPLH, VDD = 5.5V
1000
tPLH, VDD = 1.8V
tPHL, VDD = 1.8V
100
tPLH, VDD = 5.5V
10
-0.6
-0.4
-0.2
0
Input Voltage (V)
FIGURE 2-33:
Input Bias Current vs. Input
Voltage vs. Temperature.
DS20002143G-page 12
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
V PU (V)
FIGURE 2-36:
Pull-up Voltage.
Propagation Delay vs.
2009-2020 Microchip Technology Inc.
MCP6566/6R/6U/7/9
Note: Unless otherwise indicated, VDD = +1.8V to +5.5V, VSS = GND, TA = +25°C, VIN+ = VDD /2, VIN - = GND,
RL = 20 k to VPU = VDD and CL = 25 pF.
80
30%
78
VCM = VSS
VDD = 1.8V to 5.5V
76
Occurrences (%)
CMRR/PSRR (dB)
Input Referred
PSRR
74
CMRR
72
VCM = -0.3V to VDD + 0.3V
VDD = 5.5V
20%
10%
70
0
25
50
75
Temperature (°C)
100
125
30%
VDD = 1.8V
3588 units
20%
-4
-3
-2
-1
0
1
2
3
4
5
CMRR (mV/V)
VCM = VSS
Avg. = 200 µV/V
StDev= 94 µV/V
3588 units
25%
-5
15%
10%
FIGURE 2-40:
Ratio (CMRR).
30%
Occurrences (%)
-25
FIGURE 2-37:
Common-Mode Rejection
Ratio and Power Supply Rejection Ratio vs.
Temperature.
Occurrences (%)
VCM = -0.2V to VDD /2
Avg. = 0.5 mV
StDev= 0.1 mV
0%
-50
Common-Mode Rejection
VCM = VDD/2 to VDD+ 0.3V
Avg. = 0.03 mV
StDev= 0.7 mV
V CM = -0.3V to V DD + 0.3V
Avg. = 0.1 mV
StDev= 0.4 mV
20%
10%
VCM = -0.3V to VDD/2
Avg. = 0.2 mV
StDev= 0.4 mV
VDD = 5.5V
3588 units
5%
0%
-2.5 -2.0 -1.5 -1.0 -0.5 0.0 0.5 1.0 1.5 2.0 2.5
0%
-600
-400
-200
0
200
400
600
CMRR (mV/V)
PSRR (µV/V)
FIGURE 2-38:
Ratio (PSRR).
Power Supply Rejection
1000
FIGURE 2-41:
Ratio (CMRR).
Common-Mode Rejection
10000
IOS and IB (pA)
100
IB
10
1
|I OS|
IB @ TA= +85°C
100
10
1
|IOS| @ TA= +125°C
0.1
|IOS|@ TA= +85°C
0.01
0.1
VDD = 5.5V
IB @ TA= +125°C
1000
IOS and IB (pA)
VCM = -0.2V to VDD + 0.2V
Avg. = 0.6 mV
StDev= 0.1 mV
VCM = VDD/2 to VDD+ 0.2V
Avg. = 0.7 mV
StDev= 1 mV
0.001
25
50
75
100
Temperature (°C)
125
FIGURE 2-39:
Input Offset Current and
Input Bias Current vs. Temperature.
2009-2020 Microchip Technology Inc.
0
1
2
3
V CM (V)
4
5
6
FIGURE 2-42:
Input Offset Current and
Input Bias Current vs. Common-Mode Input
Voltage vs. Temperature.
DS20002143G-page 13
MCP6566/6R/6U/7/9
Note: Unless otherwise indicated, VDD = +1.8V to +5.5V, VSS = GND, TA = +25°C, VIN+ = VDD /2, VIN - = GND,
RL = 20 k to VPU = VDD and CL = 25 pF.
Output Jitter pk-pk (ns)
10000
VDD = 5.5V
1000
VIN+ = 2Vpp (sine)
100
10
1
0.1
100
100
1k
1000
10k
100k
1M
10000
100000
100000
Input Frequency (Hz) 0
FIGURE 2-43:
Frequency.
DS20002143G-page 14
10M
1E+07
Output Jitter vs. Input
2009-2020 Microchip Technology Inc.
MCP6566/6R/6U/7/9
3.0
PIN DESCRIPTIONS
Descriptions of the pins are listed in Table 3-1.
TABLE 3-1:
PIN FUNCTION TABLE
MCP6566 MCP6566R MCP6566U MCP6567 MCP6569
Symbol
Description
SC70,
SOT-23
SOT-23
SOT-23
MSOP,
SOIC
SOIC,
TSSOP
1
1
4
1
1
OUT, OUTA Digital Output (Comparator A)
4
4
3
2
2
VIN-, VINA-
3
3
1
3
3
VIN+, VINA+
5
2
5
8
4
VDD
—
—
—
5
5
VINB+
Noninverting Input (Comparator B)
—
—
—
6
6
VINB-
Inverting Input (Comparator B)
—
—
—
7
7
OUTB
Digital Output (Comparator B)
—
—
—
—
8
OUTC
Digital Output (Comparator C)
3.1
Noninverting Input (Comparator A)
Positive Power Supply
—
—
—
—
9
VINC-
Inverting Input (Comparator C)
—
—
—
—
10
VINC+
Noninverting Input (Comparator C)
2
5
2
4
11
VSS
—
—
—
—
12
VIND+
Noninverting Input (Comparator D)
Inverting Input (Comparator D)
Digital Output (Comparator D)
—
—
—
—
13
VIND-
—
—
—
—
14
OUTD
Analog Inputs
The comparator noninverting and inverting inputs are
high-impedance CMOS inputs with low bias currents.
3.2
Inverting Input (Comparator A)
Digital Outputs
The comparator outputs are CMOS, open-drain digital
outputs. They are designed to make level shifting and
wired-OR easy to implement.
2009-2020 Microchip Technology Inc.
3.3
Negative Power Supply
Power Supply (VSS and VDD)
The positive power supply pin (VDD) is 1.8V to 5.5V
higher than the negative power supply pin (VSS). For
normal operation, the other pins are at voltages
between VSS and VDD.
Typically, these parts are used in a single (positive)
supply configuration. In this case, VSS is connected to
ground and VDD is connected to the supply. VDD will
need a local bypass capacitor (typically 0.01 µF to
0.1 µF) within 2 mm of the VDD pin. These pins can
share a bulk capacitor with nearby analog parts (within
100 mm), but it is not required.
DS20002143G-page 15
MCP6566/6R/6U/7/9
NOTES:
DS20002143G-page 16
2009-2020 Microchip Technology Inc.
MCP6566/6R/6U/7/9
4.0
APPLICATION INFORMATION
The MCP6566/6R/6U/7/9 family of open-drain output
comparators is fabricated on Microchip’s state-ofthe-art CMOS process. They are suitable for a wide
range of high-speed applications requiring low-power
consumption.
4.1
Comparator Inputs
4.1.1
NORMAL OPERATION
The input stage of this family of devices uses two different input stages in parallel. This configuration provides
three regions of operation; one operates at low input
voltages, one at high input voltages, and one at mid
input voltage. With this topology, the input voltage
range is 0.3V above VDD and 0.3V below VSS, while
providing low offset voltage throughout the Commonmode range. The input offset voltage is measured at
both VSS – 0.3V and VDD + 0.3V to ensure proper
operation.
8
7
6
5
4
3
2
1
0
-1
-2
-3
VDD = 5.0V
VIN–
VOUT
Hysteresis
25
20
15
10
5
0
-5
-10
-15
-20
-25
-30
Input Voltage (10 mV/div)
Output Voltage (V)
The MCP6566/6R/6U/7/9 family has an internally set
hysteresis, VHYST, which is small enough to maintain
input offset accuracy and large enough to eliminate output chattering caused by the comparator’s own input
noise voltage, ENI. Figure 4-1 depicts this behavior.
Input offset voltage (VOS) is the center (average) of the
(input referred) low-high and high-low trip points. Input
hysteresis voltage (VHYST) is the difference between
the same trip points.
4.1.2
INPUT VOLTAGE AND CURRENT
LIMITS
The ESD protection on the inputs can be depicted as
shown in Figure 4-2. This structure was chosen to
protect the input transistors and to minimize input bias
current (IB). The input ESD diodes clamp the inputs
when they try to go more than one diode drop below
VSS. They also clamp any voltages that go too far
above VDD. The diodes’ breakdown voltage is high
enough to allow normal operation, but low enough to
bypass ESD events within the specified limits.
VDD Bond
Pad
VIN+
Bond
Pad
Input
Stage
Bond
VINPad
VSS Bond
Pad
FIGURE 4-2:
Structures.
Simplified Analog Input ESD
In order to prevent damage and/or improper operation
of these amplifiers, the circuits they are in must limit the
currents (and voltages) at the VIN+ and VIN- pins (see
Section 1.1 “Absolute Maximum Ratings†” at the
beginning of Section 1.0 “Electrical Characteristics”). Figure 4-3 shows the recommended approach
to protecting these inputs. The internal ESD diodes
prevent the input pins (VIN+ and VIN-) from going too far
below ground, and the resistors, R1 and R2, limit the
possible current drawn out of the input pin. Diodes, D1
and D2, prevent the input pin (VIN+ and VIN-) from
going too far above VDD. When implemented as
shown, resistors, R1 and R2, also limit the current
through D1 and D2.
Time (100 ms/div)
FIGURE 4-1:
The MCP6566/6R/6U/7/9
Comparators’ Internal Hysteresis Eliminates
Output Chatter Caused by Input Noise Voltage.
2009-2020 Microchip Technology Inc.
DS20002143G-page 17
MCP6566/6R/6U/7/9
VDD
D1
V1
MCP656X
D2
V2
VPU
R4
+
R1
4.3
–
R2
R3
R1
VSS – (minimum expected V1)
2 mA
R2
VSS – (minimum expected V2)
2 mA
FIGURE 4-3:
Inputs.
VOUT
A significant amount of current can flow out of the
inputs when the Common-mode voltage (VCM) is below
ground (VSS); see Figure 4-3. Applications that are
high-impedance may need to limit the usable voltage
range.
PHASE REVERSAL
The MCP6566/6R/6U/7/9 comparator family uses
CMOS transistors at the input. They are designed to
prevent phase inversion when the input pins exceed
the supply voltages. Figure 2-3 shows an input voltage
exceeding both supplies with no resulting phase
inversion.
4.2
Greater flexibility in selecting hysteresis (or input trip
points) is achieved by using external resistors.
Hysteresis reduces output chattering when one input is
slowly moving past the other. It also helps in systems in
which it is best not to cycle between high and low states
too frequently (e.g., air conditioner thermostatic control). Output chatter also increases the dynamic supply
current.
4.3.1
NONINVERTING CIRCUIT
Figure 4-4 shows a noninverting circuit for singlesupply applications using just two resistors. The
resulting hysteresis diagram is shown in Figure 4-5.
Open-Drain Output
The open-drain output is designed to make level
shifting and wired-OR logic easy to implement. The
output stage minimizes switching current (shootthrough current from supply-to-supply) when the
output changes state. See Figures 2-15, 2-18, 2-35
and 2-36 for more information.
VPU
VDD
Protecting the Analog
It is also possible to connect the diodes to the left of the
resistors, R1 and R2. In this case, the currents through
the diodes, D1 and D2, need to be limited by some other
mechanism. The resistor then serves as an inrush
current limiter; the DC current into the input pins (VIN+
and VIN-) should be very small.
4.1.3
Externally Set Hysteresis
RPU
–
VREF
VOUT
MCP656X
+
VIN
R1
RF
FIGURE 4-4:
Noninverting Circuit with
Hysteresis for Single Supply.
VOUT
VDD
VOH
High-to-Low
VOL
VSS
VSS
Low-to-High
VIN
VTHL VTLH
VDD
FIGURE 4-5:
Hysteresis Diagram for the
Noninverting Circuit.
The trip points for Figures 4-4 and 4-5 are:
EQUATION 4-1:
R1
R1
VTLH = V REF 1 + ------- – V OL -------
RF
RF
R1
R 1
VTHL = V REF 1 + ------- – V OH -------
RF
RF
Where:
VTLH = Trip Voltage from Low-to-High
VTHL = Trip Voltage from High-to-Low
DS20002143G-page 18
2009-2020 Microchip Technology Inc.
MCP6566/6R/6U/7/9
4.3.2
INVERTING CIRCUIT
Where:
R2R3
R 23 = ------------------R2 + R3
Figure 4-6 shows an inverting circuit for single supply
using three resistors. The resulting hysteresis diagram
is shown in Figure 4-7.
VPU
VDD
VIN
RPU
–
VDD
R3
V23 = ------------------- V DD
R2 + R3
VOUT
MCP656X
+
Using this simplified circuit, the trip voltage can be
calculated using the following equation:
EQUATION 4-2:
R2
RF
R 23
V THL = V OH ----------------------- + V 23 ----------------------
R
+
R
R
23
23 + R F
F
RF
R3
FIGURE 4-6:
Hysteresis.
RF
R23
V TLH = V OL ----------------------- + V 23 ----------------------
R
+
R
R
23
23 + R F
F
Where:
Inverting Circuit with
VTLH = Trip Voltage from Low-to-High
VTHL = Trip Voltage from High-to-Low
VOUT
Figure 2-21 and Figure 2-24 can be used to determine
typical values for VOH and VOL.
VDD
VOH
Low-to-High
High-to-Low
4.4
VIN
VOL
VSS
VSS
VTLH VTHL
FIGURE 4-7:
Inverting Circuit.
VDD
Hysteresis Diagram for the
In order to determine the trip voltages (VTHL and VTLH)
for the circuit shown in Figure 4-6, R2 and R3 can be
simplified to the Thevenin equivalent circuit with
respect to VDD, as shown in Figure 4-8.
VPU
VDD
Bypass Capacitors
With this family of comparators, the power supply pin
(VDD for single supply) should have a local bypass
capacitor (i.e., 0.01 µF to 0.1 µF) within 2 mm for good
edge rate performance.
4.5
Capacitive Loads
Reasonable capacitive loads (e.g., logic gates) have little
impact on propagation delay (see Figure 2-32). The supply current increases with increasing toggle frequency
(Figure 2-20), especially with higher capacitive loads.
The output slew rate and propagation delay performance
will be reduced with higher capacitive loads.
RPU
–
MCP656X
+
VSS
VOUT
V23
R23
FIGURE 4-8:
RF
Thevenin Equivalent Circuit.
2009-2020 Microchip Technology Inc.
DS20002143G-page 19
MCP6566/6R/6U/7/9
4.6
PCB Surface Leakage
4.7
In applications where low input bias current is critical,
PCB (Printed Circuit Board) surface leakage effects
need to be considered. Surface leakage is caused by
humidity, dust or other contamination on the board.
Under low humidity conditions, a typical resistance
between nearby traces is 1012. A 5V difference would
cause 5 pA of current to flow. This is greater than the
MCP6566/6R/6U/7/9 family’s bias current at +25°C
(1 pA, typical).
The easiest way to reduce surface leakage is to use a
guard ring around sensitive pins (or traces). The guard
ring is biased at the same voltage as the sensitive pin.
An example of this type of layout is shown in
Figure 4-9.
IN-
IN+
VSS
PCB Layout Technique
When designing the PCB layout, it is critical to note that
analog and digital signal traces are adequately
separated to prevent signal coupling. If the comparator
output trace is at close proximity to the input traces,
then large output voltage changes, from VSS to VDD or
visa versa, may couple to the inputs and cause the
device output to oscillate. To prevent such oscillation,
the output traces must be routed away from the input
pins. The SC70 and SOT-23 are relatively immune
because the output pin OUT (Pin 1) is separated by the
power pin VDD/VSS (Pin 2) from the input pin +IN (as
long as the analog and digital traces remain separated
throughout the PCB). However, the pinouts for the dual
and quad packages (SOIC, MSOP, TSSOP) have OUT
and -IN pins (Pins 1 and 2) close to each other. The
recommended layout for these packages is shown in
Figure 4-10.
VDD
OUTA
Guard Ring
-INA
OUTB
+INA
-INB
VSS
+INB
FIGURE 4-9:
Example Guard Ring Layout
for Inverting Circuit.
FIGURE 4-10:
1.
4.8
2.
Inverting Configuration (Figures 4-6 and 4-9):
a) Connect the guard ring to the noninverting
input pin (VIN+). This biases the guard ring
to the same reference voltage as the
comparator (e.g., VDD/2 or ground).
b) Connect the inverting pin (VIN-) to the input
pad without touching the guard ring.
Noninverting Configuration (Figure 4-4):
a) Connect the noninverting pin (VIN+) to the
input pad without touching the guard ring.
b) Connect the guard ring to the inverting input
pin (VIN-).
Recommended Layout.
Unused Comparators
An unused amplifier in a quad package (MCP6569)
should be configured as shown in Figure 4-11. This
circuit prevents the output from toggling and causing
crosstalk. It uses the minimum number of components
and draws minimal current (see Figure 2-14 and
Figure 2-15).
¼ MCP6569
VDD
–
+
FIGURE 4-11:
DS20002143G-page 20
Unused Comparators.
2009-2020 Microchip Technology Inc.
MCP6566/6R/6U/7/9
4.9
Typical Applications
4.9.1
4.9.3
PRECISE COMPARATOR
Some applications require higher DC precision. An
easy way to solve this problem is to use an amplifier
(such as the MCP6291) to gain-up the input signal
before it reaches the comparator. Figure 4-12 shows
an example of this approach.
R2
VDD
+
VDD
R1
R2
VREF
FIGURE 4-12:
Comparator.
RPU
+
VPU
–
4.9.2
VPU
VREF
MCP6291
VIN
A simple bistable multivibrator design is shown in
Figure 4-14. VREF needs to be between the power
supplies (VSS = GND and VDD) to achieve oscillation.
The output duty cycle changes with VREF.
R1
VDD
VREF
BISTABLE MULTIVIBRATOR
MCP656X
–
RPU
VOUT
+
VOUT
MCP656X
–
C1
FIGURE 4-14:
Precise Inverting
R3
Bistable Multivibrator.
WINDOWED COMPARATOR
Figure 4-13 shows one approach to designing a
windowed comparator. The AND gate produces a logic
‘1’ when the input voltage is between VRB and VRT
(where VRT > VRB).
VRT
+
VPU
1/2
MCP6567
RPU
VOUT
–
VIN
+
VRB
FIGURE 4-13:
–
1/2
MCP6567
Windowed Comparator.
2009-2020 Microchip Technology Inc.
DS20002143G-page 21
MCP6566/6R/6U/7/9
NOTES:
DS20002143G-page 22
2009-2020 Microchip Technology Inc.
MCP6566/6R/6U/7/9
5.0
DESIGN AIDS
5.3
5.1
Microchip Advanced Part Selector
(MAPS)
The following Microchip Application Note is available
on the Microchip website at www.microchip.com and is
recommended as a supplemental reference resource:
MAPS is a software tool that helps semiconductor
professionals efficiently identify Microchip devices that
fit a particular design requirement.
Available at no cost from the Microchip website at
www.microchip.com/maps, the MAPS is an overall
selection tool for Microchip’s product portfolio that
includes Analog, Memory, MCUs and DSCs. Using this
tool you can define a filter to sort features for a
parametric search of devices and export side-by-side
technical comparison reports. Helpful links are also
provided for data sheets, purchase and sampling of
Microchip parts.
5.2
Analog Demonstration and
Evaluation Boards
Microchip offers a broad spectrum of Analog
Demonstration and Evaluation Boards that are
designed to help you achieve faster time to market.
For a listing of these boards, and their corresponding
user’s guides and technical information, visit the
Microchip website at www.microchip.com/analogtools.
Three of our boards that are especially useful are:
• 8-Pin SOIC/MSOP/TSSOP/DIP Evaluation Board,
P/N SOIC8EV
• 14-Pin SOIC/TSSOP/DIP Evaluation Board,
P/N SOIC14EV
• 5/6-Pin SOT23 Evaluation Board, P/N VSUPEV2
2009-2020 Microchip Technology Inc.
Application Notes
• AN895 – “Oscillator Circuits For RTD Temperature
Sensors” (DS00895).
5.4
SPICE Macro Model
The latest SPICE macro model for the MCP6566/7/9
op amp is available on the Microchip website at
www.microchip.com. The model was written and tested
in the official Cadence® (OrCAD™) PSpice®. For the
other simulators, translation may be required.
The model covers a wide aspect of the comparator’s
electrical specifications. Not only does the model cover
voltage, current and resistance of the comparator, but it
also covers the temperature and noise effects on the
behavior of the comparator. The model has not been
verified outside of the specification range listed in the
comparator data sheet. The model behaviors under
these conditions cannot ensure it will match the actual
comparator performance. Moreover, the model is
intended to be an initial design tool. Bench testing is a
very important part of any design and cannot be
replaced with simulations. Also, simulation results
using this macro model need to be validated by
comparing them to the data sheet specifications and
characteristic curves.
DS20002143G-page 23
MCP6566/6R/6U/7/9
NOTES:
DS20002143G-page 24
2009-2020 Microchip Technology Inc.
MCP6566/6R/6U/7/9
6.0
PACKAGING INFORMATION
6.1
Package Marking Information
5-Lead SC70 (MCP6566)
Example:
BJ25
XXNN
5-Lead SOT-23 (MCP6566, MCP6566R)
Device
XXNN
Example:
Code
MCP6566T
JYNN
MCP6566RT
JZNN
MCP6566UT
WLNN
JY25
Note: Applies to 5-Lead SOT-23.
8-Lead MSOP (MCP6567)
XXXXXX
YWWNNN
Example:
6567E
933256
8-Lead SOIC (150 mil) (MCP6567)
Example:
XXXXXXXX
MCP6567E
NNN
256
XXXXYYWW
Legend: XX...X
Y
YY
WW
NNN
e3
*
Note:
SN e3 1933
Customer-specific information
Year code (last digit of calendar year)
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code
Pb-free JEDEC designator for Matte Tin (Sn)
This package is Pb-free. The Pb-free JEDEC designator ( e3 )
can be found on the outer packaging for this package.
In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
2009-2020 Microchip Technology Inc.
DS20002143G-page 25
MCP6566/6R/6U/7/9
Package Marking Information (Continued)
14-Lead SOIC (150 mil) (MCP6569)
XXXXXXXXXXX
XXXXXXXXXXX
YYWWNNN
Example:
MCP6569
E/SL e3
1933256
14-Lead TSSOP (MCP6569)
Example:
XXXXXXXX
YYWW
NNN
MCP6569E
1933
256
DS20002143G-page 26
2009-2020 Microchip Technology Inc.
MCP6566/6R/6U/7/9
5-Lead Plastic Small Outline Transistor (LT) [SC70]
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
D
A
e
e
3
B
1
E1
E
2X
0.15 C
4
N
5X TIPS
0.30 C
NOTE 1
2X
0.15 C
5X b
0.10
C A B
TOP VIEW
C
c
A2
A
SEATING
PLANE
A1
L
SIDE VIEW
END VIEW
Microchip Technology Drawing C04-061-LT Rev E Sheet 1 of 2
2009-2020 Microchip Technology Inc.
DS20002143G-page 27
MCP6566/6R/6U/7/9
5-Lead Plastic Small Outline Transistor (LT) [SC70]
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Units
Dimension Limits
Number of Pins
N
e
Pitch
Overall Height
A
Standoff
A1
A2
Molded Package Thickness
Overall Length
D
Overall Width
E
Molded Package Width
E1
b
Terminal Width
Terminal Length
L
c
Lead Thickness
MIN
0.80
0.00
0.80
0.15
0.10
0.08
MILLIMETERS
NOM
5
0.65 BSC
2.00 BSC
2.10 BSC
1.25 BSC
0.20
-
MAX
1.10
0.10
1.00
0.40
0.46
0.26
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or
protrusions shall not exceed 0.15mm per side.
3. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
Microchip Technology Drawing C04-061-LT Rev E Sheet 2 of 2
DS20002143G-page 28
2009-2020 Microchip Technology Inc.
MCP6566/6R/6U/7/9
5-Lead Plastic Small Outline Transistor (LT) [SC70]
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
E
Gx
SILK SCREEN
3
2
1
C
G
4
5
Y
X
RECOMMENDED LAND PATTERN
Units
Dimension Limits
E
Contact Pitch
Contact Pad Spacing
C
Contact Pad Width
X
Contact Pad Length
Y
Distance Between Pads
G
Distance Between Pads
Gx
MIN
MILLIMETERS
NOM
0.65 BSC
2.20
MAX
0.45
0.95
1.25
0.20
Notes:
1. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
Microchip Technology Drawing No. C04-2061-LT Rev E
2009-2020 Microchip Technology Inc.
DS20002143G-page 29
MCP6566/6R/6U/7/9
5-Lead Plastic Small Outline Transistor (OT) [SOT23]
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
0.20 C 2X
D
e1
A
D
N
E/2
E1/2
E1
E
(DATUM D)
(DATUM A-B)
0.15 C D
2X
NOTE 1
1
2
e
B
NX b
0.20
C A-B D
TOP VIEW
A
A A2
0.20 C
SEATING PLANE
A
SEE SHEET 2
A1
C
SIDE VIEW
Microchip Technology Drawing C04-091-OT Rev F Sheet 1 of 2
DS20002143G-page 30
2009-2020 Microchip Technology Inc.
MCP6566/6R/6U/7/9
5-Lead Plastic Small Outline Transistor (OT) [SOT23]
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
c
T
L
L1
VIEW A-A
SHEET 1
Units
Dimension Limits
N
Number of Pins
e
Pitch
e1
Outside lead pitch
A
Overall Height
A2
Molded Package Thickness
Standoff
A1
Overall Width
E
Molded Package Width
E1
Overall Length
D
Foot Length
L
Footprint
L1
I
Foot Angle
c
Lead Thickness
b
Lead Width
MIN
0.90
0.89
-
0.30
0°
0.08
0.20
MILLIMETERS
NOM
5
0.95 BSC
1.90 BSC
2.80 BSC
1.60 BSC
2.90 BSC
0.60 REF
-
MAX
1.45
1.30
0.15
0.60
10°
0.26
0.51
Notes:
1. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or
protrusions shall not exceed 0.25mm per side.
2. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
Microchip Technology Drawing C04-091-OT Rev F Sheet 2 of 2
2009-2020 Microchip Technology Inc.
DS20002143G-page 31
MCP6566/6R/6U/7/9
5-Lead Plastic Small Outline Transistor (OT) [SOT23]
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
X
SILK SCREEN
5
Y
Z
C
G
1
2
E
GX
RECOMMENDED LAND PATTERN
Units
Dimension Limits
E
Contact Pitch
C
Contact Pad Spacing
X
Contact Pad Width (X5)
Contact Pad Length (X5)
Y
Distance Between Pads
G
Distance Between Pads
GX
Overall Width
Z
MIN
MILLIMETERS
NOM
0.95 BSC
2.80
MAX
0.60
1.10
1.70
0.35
3.90
Notes:
1. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
Microchip Technology Drawing No. C04-2091-OT Rev F
DS20002143G-page 32
2009-2020 Microchip Technology Inc.
MCP6566/6R/6U/7/9
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2009-2020 Microchip Technology Inc.
DS20002143G-page 33
MCP6566/6R/6U/7/9
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS20002143G-page 34
2009-2020 Microchip Technology Inc.
MCP6566/6R/6U/7/9
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2009-2020 Microchip Technology Inc.
DS20002143G-page 35
MCP6566/6R/6U/7/9
8-Lead Plastic Small Outline (SN) - Narrow, 3.90 mm (.150 In.) Body [SOIC]
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2X
0.10 C A–B
D
A
D
NOTE 5
N
E
2
E1
2
E1
E
NOTE 1
2
1
e
B
NX b
0.25
C A–B D
NOTE 5
TOP VIEW
0.10 C
C
A A2
SEATING
PLANE
8X
A1
SIDE VIEW
0.10 C
h
R0.13
h
R0.13
H
SEE VIEW C
VIEW A–A
0.23
L
(L1)
VIEW C
Microchip Technology Drawing No. C04-057-SN Rev E Sheet 1 of 2
DS20002143G-page 36
2009-2020 Microchip Technology Inc.
MCP6566/6R/6U/7/9
8-Lead Plastic Small Outline (SN) - Narrow, 3.90 mm (.150 In.) Body [SOIC]
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Units
Dimension Limits
Number of Pins
N
e
Pitch
Overall Height
A
Molded Package Thickness
A2
§
Standoff
A1
Overall Width
E
Molded Package Width
E1
Overall Length
D
Chamfer (Optional)
h
Foot Length
L
L1
Footprint
Foot Angle
c
Lead Thickness
b
Lead Width
Mold Draft Angle Top
Mold Draft Angle Bottom
MIN
1.25
0.10
0.25
0.40
0°
0.17
0.31
5°
5°
MILLIMETERS
NOM
8
1.27 BSC
6.00 BSC
3.90 BSC
4.90 BSC
1.04 REF
-
MAX
1.75
0.25
0.50
1.27
8°
0.25
0.51
15°
15°
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. § Significant Characteristic
3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or
protrusions shall not exceed 0.15mm per side.
4. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
5. Datums A & B to be determined at Datum H.
Microchip Technology Drawing No. C04-057-SN Rev E Sheet 2 of 2
2009-2020 Microchip Technology Inc.
DS20002143G-page 37
MCP6566/6R/6U/7/9
8-Lead Plastic Small Outline (SN) - Narrow, 3.90 mm Body [SOIC]
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
SILK SCREEN
C
Y1
X1
E
RECOMMENDED LAND PATTERN
Units
Dimension Limits
E
Contact Pitch
Contact Pad Spacing
C
Contact Pad Width (X8)
X1
Contact Pad Length (X8)
Y1
MIN
MILLIMETERS
NOM
1.27 BSC
5.40
MAX
0.60
1.55
Notes:
1. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
Microchip Technology Drawing C04-2057-SN Rev E
DS20002143G-page 38
2009-2020 Microchip Technology Inc.
MCP6566/6R/6U/7/9
14-Lead Plastic Small Outline (SL) - Narrow, 3.90 mm Body [SOIC]
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2X
0.10 C A–B
D
A
NOTE 5
D
N
E
2
E2
2
E1
E
2X
0.10 C D
NOTE 1
1
2
2X N/2 TIPS
0.20 C
3
e
NX b
B
0.25
NOTE 5
C A–B D
TOP VIEW
0.10 C
C
A A2
SEATING
PLANE
14X
h
0.10 C
SIDE VIEW
A1
h
R0.13
H
R0.13
c
SEE VIEW C
L
VIEW A–A
(L1)
VIEW C
Microchip Technology Drawing No. C04-065-SL Rev D Sheet 1 of 2
2009-2020 Microchip Technology Inc.
DS20002143G-page 39
MCP6566/6R/6U/7/9
14-Lead Plastic Small Outline (SL) - Narrow, 3.90 mm Body [SOIC]
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Units
Dimension Limits
Number of Pins
N
e
Pitch
Overall Height
A
Molded Package Thickness
A2
§
Standoff
A1
Overall Width
E
Molded Package Width
E1
Overall Length
D
Chamfer (Optional)
h
Foot Length
L
Footprint
L1
Lead Angle
Foot Angle
c
Lead Thickness
Lead Width
b
Mold Draft Angle Top
Mold Draft Angle Bottom
MIN
1.25
0.10
0.25
0.40
0°
0°
0.10
0.31
5°
5°
MILLIMETERS
NOM
14
1.27 BSC
6.00 BSC
3.90 BSC
8.65 BSC
1.04 REF
-
MAX
1.75
0.25
0.50
1.27
8°
0.25
0.51
15°
15°
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. § Significant Characteristic
3. Dimension D does not include mold flash, protrusions or gate burrs, which shall
not exceed 0.15 mm per end. Dimension E1 does not include interlead flash
or protrusion, which shall not exceed 0.25 mm per side.
4. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
5. Datums A & B to be determined at Datum H.
Microchip Technology Drawing No. C04-065-SL Rev D Sheet 2 of 2
DS20002143G-page 40
2009-2020 Microchip Technology Inc.
MCP6566/6R/6U/7/9
14-Lead Plastic Small Outline (SL) - Narrow, 3.90 mm Body [SOIC]
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
14
SILK SCREEN
C
Y
1
2
X
E
RECOMMENDED LAND PATTERN
Units
Dimension Limits
E
Contact Pitch
Contact Pad Spacing
C
Contact Pad Width (X14)
X
Contact Pad Length (X14)
Y
MIN
MILLIMETERS
NOM
1.27 BSC
5.40
MAX
0.60
1.55
Notes:
1. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
Microchip Technology Drawing No. C04-2065-SL Rev D
2009-2020 Microchip Technology Inc.
DS20002143G-page 41
MCP6566/6R/6U/7/9
14Lead Thin Shrink Small Outline Package [ST] 4.4 mm Body [TSSOP]
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
D
A
B
N
E
2
E1
2
E1
E
1
2X 7 TIPS
0.20 C B A
2
e
TOP VIEW
A
C
A2 A
SEATING
PLANE
14X
0.10 C
14X b
0.10
A1
A
C B A
SIDE VIEW
SEE DETAIL B
VIEW A–A
Microchip Technology Drawing C04-087 Rev D Sheet 1 of 2
DS20002143G-page 42
2009-2020 Microchip Technology Inc.
MCP6566/6R/6U/7/9
14Lead Thin Shrink Small Outline Package [ST] 4.4 mm Body [TSSOP]
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
(ș2)
R1
H
R2
c
L
ș1
(L1)
(ș3)
DETAIL B
Number of Terminals
Pitch
Overall Height
Standoff
Molded Package Thickness
Overall Length
Overall Width
Molded Package Width
Terminal Width
Terminal Thickness
Terminal Length
Footprint
Lead Bend Radius
Lead Bend Radius
Foot Angle
Mold Draft Angle
Mold Draft Angle
Notes:
Units
Dimension Limits
N
e
A
A1
A2
D
E
E1
b
c
L
L1
R1
R2
ș1
ș2
ș3
MIN
–
0.05
0.80
4.90
4.30
0.19
0.09
0.45
0.09
0.09
0°
–
–
MILLIMETERS
NOM
14
0.65 BSC
–
–
1.00
5.00
6.40 BSC
4.40
–
–
0.60
1.00 REF
–
–
–
12° REF
12° REF
MAX
1.20
0.15
1.05
5.10
4.50
0.30
0.20
0.75
–
–
8°
–
–
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
Microchip Technology Drawing C04-087 Rev D Sheet 2 of 2
2009-2020 Microchip Technology Inc.
DS20002143G-page 43
MCP6566/6R/6U/7/9
14Lead Thin Shrink Small Outline Package [ST] 4.4 mm Body [TSSOP]
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
G
SILK SCREEN
C
Y
X
E
RECOMMENDED LAND PATTERN
Units
Dimension Limits
Contact Pitch
E
Contact Pad Spacing
C
Contact Pad Width (Xnn)
X
Contact Pad Length (Xnn)
Y
Contact Pad to Contact Pad (Xnn)
G
MIN
MILLIMETERS
NOM
0.65 BSC
5.90
MAX
0.45
1.45
0.20
Notes:
1. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
Microchip Technology Drawing C04-2087 Rev D
DS20002143G-page 44
2009-2020 Microchip Technology Inc.
MCP6566/6R/6U/7/9
APPENDIX A:
REVISION HISTORY
Revision G (March 2020)
The following is the list of modifications:
1.
Updated package drawings for the 5-Lead SC70
and 14-lead TSSOP packages in Section 6.0
“Packaging Information”.
Revision F (August 2019)
The following is the list of modifications:
1.
Updated Section 6.0 “Packaging
Information”.
Revision E (September 2014)
The following is the list of modifications:
1.
2.
3.
4.
Added SPICE Macro Model in the Related
Device features section.
Updated Temperature Specifications table.
Corrected pin table in Section 3.0 “Pin
Descriptions”.
Added new Section 5.4, SPICE Macro Model.
Revision D (February 2013)
The following is the list of modifications:
1.
Added the Analog Input (VIN) parameter in
Section 1.0 “Electrical Characteristics”.
Revision C (February 2011)
The following is the list of modifications:
1.
Replaced the MCP5468 package name with the
correct MCP6567 package name on page 1 and
in Table 3-1.
Revision B (August 2009)
The following is the list of modifications:
1.
2.
Added MCP6566U throughout the document.
Updated package outline drawings.
Revision A (March 2009)
• Original Release of this Document.
2009-2020 Microchip Technology Inc.
DS20002143G-page 45
MCP6566/6R/6U/7/9
NOTES:
DS20002143G-page 46
2009-2020 Microchip Technology Inc.
MCP6566/6R/6U/7/9
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
PART NO.
Device
Device:
–
X
/XX
Temperature
Range
Package
MCP6566T:
Single Comparator (Tape and Reel)
(SC70, SOT-23)
MCP6566RT: Single Comparator (Tape and Reel)
(SOT-23 only)
MCP6566UT: Single Comparator (Tape and Reel)
(SOT-23 only)
MCP6567:
Dual Comparator
MCP6567T:
Dual Comparator (Tape and Reel)
MCP6569:
Quad Comparator
MCP6569T:
Quad Comparator (Tape and Reel)
Temperature
Range:
E
Package:
LT
OT
MS
SN
ST
SL
= -40C to +125C
=
=
=
=
=
=
Plastic Small Outline Transistor (SC70), 5-Lead
Plastic Small Outline Transistor (SOT-23), 5-Lead
Plastic Micro Small Outline Transistor, 8-Lead
Plastic Small Outline Transistor, 8-Lead
Plastic Thin Shrink Small Outline Transistor, 14-Lead
Plastic Small Outline Transistor, 14-Lead
2009-2020 Microchip Technology Inc.
Examples:
a)
MCP6566T-E/LT:
Tape and Reel,
Extended Temperature,
5-Lead SC70 Package.
Tape and Reel,
Extended Temperature,
5-Lead SOT-23 Package.
b)
MCP6566T-E/OT:
a)
MCP6566RT-E/OT:
Tape and Reel,
Extended Temperature,
5-Lead SOT-23 Package.
a)
MCP6566UT-E/OT:
Tape and Reel,
Extended Temperature,
5-Lead SOT-23 Package.
a)
MCP6567-E/MS:
b)
MCP6567-E/SN:
Extended Temperature,
8-Lead MSOP Package.
Extended Temperature,
8-Lead SOIC Package.
a)
MCP6569T-E/SL:
b)
MCP6569T-E/ST:
Tape and Reel,
Extended Temperature,
14-Lead SOIC Package.
Tape and Reel,
Extended Temperature,
14-Lead TSSOP Package.
DS20002143G-page 47
MCP6566/6R/6U/7/9
NOTES:
DS20002143G-page 48
2009-2020 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
•
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
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hold harmless Microchip from any and all damages, claims,
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Trademarks
The Microchip name and logo, the Microchip logo, Adaptec,
AnyRate, AVR, AVR logo, AVR Freaks, BesTime, BitCloud, chipKIT,
chipKIT logo, CryptoMemory, CryptoRF, dsPIC, FlashFlex,
flexPWR, HELDO, IGLOO, JukeBlox, KeeLoq, Kleer, LANCheck,
LinkMD, maXStylus, maXTouch, MediaLB, megaAVR, Microsemi,
Microsemi logo, MOST, MOST logo, MPLAB, OptoLyzer,
PackeTime, PIC, picoPower, PICSTART, PIC32 logo, PolarFire,
Prochip Designer, QTouch, SAM-BA, SenGenuity, SpyNIC, SST,
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are registered trademarks of Microchip Technology Incorporated in
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APT, ClockWorks, The Embedded Control Solutions Company,
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IntelliMOS, Libero, motorBench, mTouch, Powermite 3, Precision
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TimePictra, TimeProvider, Vite, WinPath, and ZL are registered
trademarks of Microchip Technology Incorporated in the U.S.A.
Adjacent Key Suppression, AKS, Analog-for-the-Digital Age, Any
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CryptoAuthentication, CryptoAutomotive, CryptoCompanion,
CryptoController, dsPICDEM, dsPICDEM.net, Dynamic Average
Matching, DAM, ECAN, EtherGREEN, In-Circuit Serial
Programming, ICSP, INICnet, Inter-Chip Connectivity, JitterBlocker,
KleerNet, KleerNet logo, memBrain, Mindi, MiWi, MPASM, MPF,
MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach,
Omniscient Code Generation, PICDEM, PICDEM.net, PICkit,
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Blocker, SAM-ICE, Serial Quad I/O, SMART-I.S., SQI,
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USBCheck, VariSense, ViewSpan, WiperLock, Wireless DNA, and
ZENA are trademarks of Microchip Technology Incorporated in the
U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated in
the U.S.A.
The Adaptec logo, Frequency on Demand, Silicon Storage
Technology, and Symmcom are registered trademarks of Microchip
Technology Inc. in other countries.
GestIC is a registered trademark of Microchip Technology Germany
II GmbH & Co. KG, a subsidiary of Microchip Technology Inc., in
other countries.
All other trademarks mentioned herein are property of their
respective companies.
© 2009-2020, Microchip Technology Incorporated, All Rights
Reserved.
For information regarding Microchip’s Quality Management Systems,
please visit www.microchip.com/quality.
2009-2020 Microchip Technology Inc.
ISBN: 978-1-5224-5718-3
DS20002143G-page 49
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DS20002143G-page 50
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05/14/19
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