MCP661T-E/OT

MCP660/1/2/3/4/5/9 60 MHz, 32 V/µs Rail-to-Rail Output (RRO) Op Amps Features: Description: • • • • • • The Microchip Technology Inc. MCP660/1/2/3/4/5/9 family of operational amplifiers (op amps) features high gain-bandwidth product and high slew rate. Some also provide a Chip Select pin (CS) that supports a lowpower mode of operation. These amplifiers are optimized for high speed, low noise and distortion, single-supply operation with rail-to-rail output and an input that includes the negative rail. • • • • • • Gain-Bandwidth Product: 60 MHz (typical) Slew Rate: 32 V/µs (typical) Noise: 6.8 nV/Hz (typical, at 1 MHz) Short Circuit Current: 90 mA (typical) Low Input Bias Current: 4 pA (typical) Ease of Use: - Unity-Gain Stable - Rail-to-Rail Output - Input Range including Negative Rail - No Phase Reversal Supply Voltage Range: +2.5V to +5.5V High Output Current: ±70 mA Supply Current: 6.0 mA/ch (typical) Low-Power Mode: 1 µA/ch Small Packages: SOT23-5, DFN Extended Temperature Range: -40°C to +125°C This family is offered in single (MCP661), single with CS pin (MCP663), dual (MCP662) and dual with two CS pins (MCP665), triple (MCP660), quad (MCP664) and quad with two CS pins (MCP669). All devices are fully specified from -40°C to +125°C. Typical Application Circuit VREF RG RF RISO VOUT - Typical Applications: Multi-Pole Active Filter Driving A/D Converters Power Amplifier Control Loops Line Driver Video Amplifier Barcode Scanners Optical Detector Amplifier CL RL + MCP66X 100 Recommended RISO (ȍ • • • • • • • VIN Design Aids: • • • • SPICE Macro Models FilterLab® Software Microchip Advanced Part Selector (MAPS) Analog Demonstration and Evaluation Boards - MCP661DM-LD • Application Notes 10 GN = +1 GN • 1 10p 1.E-11 100p 1n 1.E-10 1.E-09 Normalized Capacitance; CL/GN (F) 10n 1.E-08 High Gain-Bandwidth Op Amp Portfolio Model Family Channels/Package Gain-Bandwidth VOS (max.) IQ/Ch (typ.) MCP621/1S/2/3/4/5/9 1, 2, 4 20 MHz 0.2 mV 2.5 mA MCP631/2/3/4/5/9 1, 2, 4 24 MHz 8.0 mV 2.5 mA 1, 2, 4 50 MHz 0.2 mV 6.0 mA 1, 2, 3, 4 60 MHz 8.0 mV 6.0 mA MCP651/1S/2/3/4/5/9 MCP660/1/2/3/4/5/9  2009-2014 Microchip Technology Inc. DS20002194E-page 1 MCP660/1/2/3/4/5/9 Package Types MCP660 SOIC, TSSOP 11 VSS EP 17 VDD 3 VDD 4 VINA+ 5 10 VINB+ VINA- VOUTA 7 8 NC 6 VOUTB 5 MCP661 SOIC NC 1 8 NC 7 VDD VIN– 2 VIN+ 3 6 VOUT VIN+ 3 VSS 4 NC 1 5 NC VSS 4 EP 9 MCP662 MSOP, SOIC VOUTA 1 8 VDD 7 VDD VINA- 2 VINA+ 3 7 VOUTB VINA- 2 6 VINB5 VINB+ VINA+ 3 6 VOUT 5 NC 8 CS 7 VDD VSS 4 5 NC 6 VOUT MCP665 3x3 DFN* 1 2 3 4 5 EP 11 VSS 4 VOUTA 1 6 VDD VSS 5 CS 4 VIN- VIN+ 3 VOUTA 1 9 8 7 6 VINA- 2 VINA+ 3 VSS 4 VOUTB VINBVINB+ CSB CSA 5 6 VINB5 VINB+ VOUTA 1 14 VOUTD VINA- 2 VINA+ 3 VDD 4 13 VIND- VINB+ 5 VINB- 6 10 VINC+ VOUTB 7 8 VOUTC MCP665 MSOP 10 VDD 8 VDD 7 VOUTB MCP664 SOIC, TSSOP VOUT 1 2 EP 9 VSS 4 MCP663 SOT-23-6 VIN- 2 VIN+ 3 VOUTA VINAVINA+ VSS CSA MCP662 3x3 DFN* 8 CS MCP663 SOIC NC 1 4 VIN- VIN+ 3 9 VINB8 VOUTB MCP661 2x3 TDFN* VIN- 2 VSS 2 10 VINB+ VINA- 6 VOUTA 7 9 VINB- VINA+ 4 5 VDD VOUT 1 12 VIND+ 11 VSS 9 VINC- MCP669 4x4 QFN* 10 VDD 9 VOUTB VOUTA NC 2 13 VINC12 VINC+ 11 VSS CSAD 12 VINC+ 14 VOUTC NC 2 NC 3 VIND- 16 15 14 13 NC 1 NC 1 MCP661 SOT-23-5 VOUTD VINC- VOUTC NC NC MCP660 4x4 QFN* 16 15 14 13 8 VINB7 VINB+ VINA- 1 6 CSB VINA+ 2 12 VIND+ 11 VSS EP 17 VDD 3 10 VINC+ 9 VINC- 5 6 7 8 VINB- VOUTB CSBC VOUTC VINB+ 4 * Includes Exposed Thermal Pad (EP); see Table 3-1. DS20002194E-page 2  2009-2014 Microchip Technology Inc. MCP660/1/2/3/4/5/9 1.0 ELECTRICAL CHARACTERISTICS 1.1 Absolute Maximum Ratings † † Notice: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. VDD – VSS .......................................................................6.5V Current at Input Pins ....................................................±2 mA Analog Inputs (VIN+ and VIN–) †† . VSS – 1.0V to VDD + 1.0V All Other Inputs and Outputs ......... VSS – 0.3V to VDD + 0.3V Output Short Circuit Current ................................ Continuous Current at Output and Supply Pins ..........................±150 mA Storage Temperature ...................................-65°C to +150°C Maximum Junction Temperature ................................ +150°C ESD protection on all pins (HBM, MM)  1 kV, 200V 1.2 †† See Section 4.1.2 “Input Voltage and Current Limits”. Specifications DC ELECTRICAL SPECIFICATIONS Electrical Characteristics: Unless otherwise indicated, TA = +25°C, VDD = +2.5V to +5.5V, VSS = GND, VCM = VDD/3, VOUT  VDD/2, VL = VDD/2, RL = 1 k to VL and CS = VSS (refer to Figure 1-2). Parameters Sym. Min. Typ. Max. Units Conditions Input Offset Input Offset Voltage VOS -8 ±1.8 +8 VOS/TA — ±2.0 — PSRR 61 76 — dB IB — 6 — pA Across Temperature IB — 130 — TA = +85°C Across Temperature IB — 1700 5000 TA = +125°C Input Offset Voltage Drift Power Supply Rejection Ratio mV µV/°C TA = -40°C to +125°C Input Current and Impedance Input Bias Current Input Offset Current IOS — ±10 — pA Common-Mode Input Impedance ZCM — 1013||9 — ||pF Differential Input Impedance ZDIFF — 1013||2 — ||pF Common-Mode Input Voltage Range VCMR VSS  0.3 — VDD  1.3 V Note 1 Common-Mode Rejection Ratio CMRR 64 79 — dB VDD = 2.5V, VCM = -0.3V to 1.2V 66 81 — dB VDD = 5.5V, VCM = -0.3V to 4.2V 88 117 — dB VDD = 2.5V, VOUT = 0.3V to 2.2V 94 126 — dB VDD = 5.5V, VOUT = 0.3V to 5.2V VSS + 25 — VDD  25 mV VDD = 2.5V, G = +2, 0.5V Input Overdrive VSS + 50 — VDD  50 ±45 ±90 ±145 ±40 ±80 ±150 Common Mode Open-Loop Gain DC Open-Loop Gain (large signal) AOL Output Maximum Output Voltage Swing VOL, VOH Output Short-Circuit Current Note 1: 2: ISC VDD = 5.5V, G = +2, 0.5V Input Overdrive mA VDD = 2.5V (Note 2) VDD = 5.5V (Note 2) See Figure 2-5 for temperature effects. The ISC specifications are for design guidance only; they are not tested.  2009-2014 Microchip Technology Inc. DS20002194E-page 3 MCP660/1/2/3/4/5/9 DC ELECTRICAL SPECIFICATIONS (CONTINUED) Electrical Characteristics: Unless otherwise indicated, TA = +25°C, VDD = +2.5V to +5.5V, VSS = GND, VCM = VDD/3, VOUT  VDD/2, VL = VDD/2, RL = 1 k to VL and CS = VSS (refer to Figure 1-2). Parameters Sym. Min. Typ. Max. Units VDD 2.5 — 5.5 V IQ 3 6 9 mA Conditions Power Supply Supply Voltage Quiescent Current per Amplifier Note 1: 2: No Load Current See Figure 2-5 for temperature effects. The ISC specifications are for design guidance only; they are not tested. AC ELECTRICAL SPECIFICATIONS Electrical Characteristics: Unless otherwise indicated, TA = +25°C, VDD = +2.5V to +5.5V, VSS = GND, VCM = VDD/2, VOUT  VDD/2, VL = VDD/2, RL = 1 k to VL, CL = 20 pF and CS = VSS (refer to Figure 1-2). Parameters Sym. Min. Typ. Max. Units Conditions AC Response Gain-Bandwidth Product GBWP — 60 — MHz PM — 65 — ° ROUT — 10 —  THD + N — 0.003 — % G = +1, VOUT = 2VP-P, f = 1 kHz, VDD = 5.5V, BW = 80 kHz Differential Gain, Positive Video (Note 1) DG — 0.3 — % NTSC, VDD = +2.5V, VSS = -2.5V, G = +2, VL = 0V, DC VIN = 0V to 0.7V Differential Gain, Negative Video (Note 1) DG — 0.3 — % NTSC, VDD = +2.5V, VSS = -2.5V, G = +2, VL = 0V, DC VIN = 0V to -0.7V Differential Phase, Positive Video (Note 1) DP — 0.3 — ° NTSC, VDD = +2.5V, VSS = -2.5V, G = +2, VL = 0V, DC VIN = 0V to 0.7V Differential Phase, Negative Video (Note 1) DP — 0.9 — ° NTSC, VDD = +2.5V, VSS = -2.5V, G = +2, VL = 0V, DC VIN = 0V to -0.7V Phase Margin Open-Loop Output Impedance G = +1 AC Distortion Total Harmonic Distortion plus Noise Step Response Rise Time, 10% to 90% tr — 5 — ns SR — 32 — V/µs G = +1 Eni — 14 — µVP-P f = 0.1 Hz to 10 Hz Input Noise Voltage Density eni — 6.8 — nV/Hz f = 1 MHz Input Noise Current Density ini 4 — fA/Hz f = 1 kHz Slew Rate G = +1, VOUT = 100 mVP-P Noise Input Noise Voltage Note 1: These specifications are described in detail in Section 4.3 “Distortion”. (NTSC refers to a National Television Standards Committee signal.) DS20002194E-page 4  2009-2014 Microchip Technology Inc. MCP660/1/2/3/4/5/9 DIGITAL ELECTRICAL SPECIFICATIONS Electrical Characteristics: Unless indicated, TA = +25°C, VDD = +2.5V to +5.5V, VSS = GND, VCM = VDD/2, VOUT  VDD/2, VL = VDD/2, RL = 1 k to VL, CL = 20 pF and CS = VSS (refer to Figures 1-1 and 2-1). Parameters Sym. Min. Typ. Max. Units Conditions CS Logic Threshold, Low VIL VSS — 0.2VDD V CS Input Current, Low ICSL — -0.1 — nA CS Logic Threshold, High VIH 0.8VDD — VDD V CS Input Current, High ICSH — -0.7 — µA GND Current ISS -2 -1 — µA CS Internal Pull-Down Resistor RPD — 5 — M IO(LEAK) — 40 — nA VHYST — 0.25 — V CS High to Amplifier Off Time (output goes High Z) tOFF — 200 — ns G = +1 V/V, VL = VSS CS = 0.8VDD to VOUT = 0.1(VDD/2) CS Low to Amplifier On Time tON — 2 10 µs G = +1 V/V, VL = VSS CS = 0.2VDD to VOUT = 0.9(VDD/2) CS Low Specifications CS = 0V CS High Specifications Amplifier Output Leakage CS = VDD CS = VDD, TA = +125°C CS Dynamic Specifications CS Input Hysteresis TEMPERATURE SPECIFICATIONS Electrical Characteristics: Unless otherwise indicated, all limits are specified for VDD = +2.5V to +5.5V, VSS = GND. Parameters Sym. Min. Typ. Max. Units Specified Temperature Range TA -40 — +125 °C Operating Temperature Range TA -40 — +125 °C Storage Temperature Range TA -65 — +150 °C Thermal Resistance, 5L-SOT-23 θJA — 201.0 — °C/W Thermal Resistance, 6L-SOT-23 θJA — 190.5 — °C/W Conditions Temperature Ranges Note 1 Thermal Package Resistances Thermal Resistance, 8L-3x3 DFN θJA — 56.7 — °C/W Thermal Resistance, 8L-MSOP θJA — 211 — °C/W Thermal Resistance, 8L-SOIC θJA — 149.5 — °C/W Thermal Resistance, 8L-2x3 TDFN θJA — 52.5 — °C/W Thermal Resistance, 10L-3x3 DFN θJA — 54.0 — °C/W Thermal Resistance, 10L-MSOP θJA — 202 — °C/W Thermal Resistance, 14L-SOIC θJA — 90.8 — °C/W Thermal Resistance, 14L-TSSOP θJA — 100 — °C/W Thermal Resistance, 16L-QFN θJA — 52.1 — °C/W Note 1: 2: Note 2 Note 2 Operation must not cause TJ to exceed the Maximum Junction Temperature specification (+150°C). Measured on a standard JC51-7, four-layer printed circuit board with ground plane and vias.  2009-2014 Microchip Technology Inc. DS20002194E-page 5 MCP660/1/2/3/4/5/9 1.3 Timing Diagram ICS 0 nA (typical) 1 µA (typical) 1 µA (typical) VIH VIL CS CF 6.8 pF tON VOUT 1.4 High Z On -6 mA (typical) -1 µA ISS (typical) RF 10 k VP tOFF High Z FIGURE 1-1: RG 10 k -1 µA (typical) Timing Diagram. Test Circuits The circuit used for most DC and AC tests is shown in Figure 1-2. This circuit can independently set VCM and VOUT; see Equation 1-1. Note that VCM is not the circuit’s common-mode voltage ((VP + VM)/2) and that VOST includes VOS plus the effects (on the input offset error, VOST) of temperature, CMRR, PSRR and AOL. VDD VIN+ MCP66X CB1 100 nF + - VDD/2 CB2 2.2 µF VINVM RG 10 k RL 1 k RF 10 k CF 6.8 pF VOUT CL 20 pF VL FIGURE 1-2: AC and DC Test Circuit for Most Specifications. EQUATION 1-1: RF G DM = ------RG V CM V DD VP + ----------2 = ------------------------2 V OST = V IN- – V IN+ VDD VOUT = ----------- +  VP – VM  + V OST  1 + G DM  2 Where: GDM = Differential Mode Gain (V/V) VCM = Op Amp’s Common-Mode (V) Input Voltage VOST = Op Amp’s Total Input Offset Voltage DS20002194E-page 6 (mV)  2009-2014 Microchip Technology Inc. MCP660/1/2/3/4/5/9 2.0 TYPICAL PERFORMANCE CURVES Note: The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore outside the warranted range. Note: Unless otherwise indicated, TA = +25°C, VDD = +2.5V to 5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2, VL = VDD/2, RL = 1 kto VL, CL = 20 pF and CS = VSS. DC Signal Inputs 22% 20% 18% 16% 14% 12% 10% 8% 6% 4% 2% 0% 1.4 100 Samples TA = +25°C VDD = 2.5V and 5.5V Input Offset Voltage (mV) Percentage of Occurrences 2.1 FIGURE 2-1: VDD = 5.5V 1.1 1.0 0.9 0.8 VDD = 2.5V 0.7 4 5 6 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 Output Voltage (V) FIGURE 2-4: Output Voltage. Input Offset Voltage. 0.0 100 Samples VDD = 2.5V and 5.5V TA = -40°C to +125°C Low Input Common Mode Headroom (V) Percentage of Occurrences 1.2 0.6 -6 -5 -4 -3 -2 -1 0 1 2 3 Input Offset Voltage (mV) 24% 22% 20% 18% 16% 14% 12% 10% 8% 6% 4% 2% 0% Representative Part 1.3 1 Lot Low (VCMR_L – VSS) -0.1 -0.2 VDD = 2.5V -0.3 VDD = 5.5V -0.4 -0.5 -12 -10 -8 -6 -4 -2 0 2 4 6 8 -50 10 12 -25 Input Offset Voltage Drift (µV/°C) Input Offset Voltage Drift. 1.4 Representative Part VCM = VSS +125°C +85°C +25°C -40°C 0 25 50 75 100 Ambient Temperature (°C) 125 FIGURE 2-5: Low-Input Common-Mode Voltage Headroom vs. Ambient Temperature. High Input Common Mode Headroom (V) Input Offset Voltage (mV) FIGURE 2-2: 0.0 -0.2 -0.4 -0.6 -0.8 -1.0 -1.2 -1.4 -1.6 -1.8 -2.0 Input Offset Voltage vs. 1 Lot High (VDD – VCMR_H) 1.3 VDD = 2.5V 1.2 1.1 VDD = 5.5V 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 Power Supply Voltage (V) FIGURE 2-3: Input Offset Voltage vs. Power Supply Voltage with VCM = 0V.  2009-2014 Microchip Technology Inc. -50 -25 0 25 50 75 100 Ambient Temperature (°C) 125 FIGURE 2-6: High-Input Common-Mode Voltage Headroom vs. Ambient Temperature. DS20002194E-page 7 MCP660/1/2/3/4/5/9 Note: Unless otherwise indicated, TA = +25°C, VDD = +2.5V to 5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2, VL = VDD/2, RL = 1 kto VL, CL = 20 pF and CS = VSS. 130 VDD = 2.5V Representative Part 1.5 1.0 DC Open-Loop Gain (dB) Input Offset Voltage (mV) 2.0 -40°C +25°C +85°C +125° C 0.5 0.0 -0.5 -1.0 -1.5 115 105 -50 1.0 0.5 +125° C +85°C +25°C 40°C 0.0 -0.5 -1.0 -1.5 6.0 5.5 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 -0.5 -2.0 Input Common Mode Voltage (V) 100 125 VDD = 5.5V 125 120 115 VDD = 2.5V 110 105 100 95 100 1.E+02 1k 10k 1.E+03 1.E+04 Load Resistance (Ω) FIGURE 2-11: Load Resistance. 1.E-08 10n Input Bias, Offset Currents (pA) CMRR, PSRR (dB) FIGURE 2-8: Input Offset Voltage vs. Common-Mode Voltage with VDD = 5.5V. 110 105 100 95 90 85 80 75 70 65 60 0 25 50 75 Ambient Temperature (°C) 130 VDD = 5.5V Representative Part 1.5 -25 FIGURE 2-10: DC Open-Loop Gain vs. Ambient Temperature. DC Open-Loop Gain (dB) Input Offset Voltage (mV) 2.0 VDD = 2.5V 110 Input Common Mode Voltage (V) FIGURE 2-7: Input Offset Voltage vs. Common-Mode Voltage with VDD = 2.5V. VDD = 5.5V 120 100 3.0 2.5 2.0 1.5 1.0 0.5 -0.5 0.0 -2.0 125 100k 1.E+05 DC Open-Loop Gain vs. VDD = 5.5V VCM = VCMR_H 1n 1.E-09 PSRR 100p 1.E-10 CMRR, VDD = 2.5V CMRR, VDD = 5.5V IB 10p 1.E-11 | IOS | 1p 1.E-12 -50 -25 0 25 50 75 Ambient Temperature (°C) 100 FIGURE 2-9: CMRR and PSRR vs. Ambient Temperature. DS20002194E-page 8 125 25 45 65 85 105 Ambient Temperature (°C) 125 FIGURE 2-12: Input Bias and Offset Currents vs. Ambient Temperature with VDD = 5.5V.  2009-2014 Microchip Technology Inc. MCP660/1/2/3/4/5/9 Note: Unless otherwise indicated, TA = +25°C, VDD = +2.5V to 5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2, VL = VDD/2, RL = 1 kto VL, CL = 20 pF and CS = VSS. 1000 Input Bias, Offset Currents (pA) Input Current Magnitude (A) 1.E-03 1m 100µ 1.E-04 10µ 1.E-05 1µ 1.E-06 100n 1.E-07 10n 1.E-08 1n 1.E-09 100p 1.E-10 +125°C +85°C +25°C -40°C 10p 1.E-11 1p 1.E-12 600 Representative Part TA = +125°C VDD = 5.5V 400 200 0 IOS -200 FIGURE 2-13: Input Bias Current vs. Input Voltage (below VSS). 60 6.0 5.5 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 -400 -1.0 -0.9 -0.8 -0.7 -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0.0 Input Voltage (V) Input Bias, Offset Currents (pA) IB 800 Common Mode Input Voltage (V) FIGURE 2-15: Input Bias and Offset Currents vs. Common-Mode Input Voltage with TA = +125°C. IB 40 20 0 IOS -20 -40 -60 -80 -100 Representative Part TA = +85°C VDD = 5.5V 5.5 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 -120 Common Mode Input Voltage (V) FIGURE 2-14: Input Bias and Offset Currents vs. Common-Mode Input Voltage with TA = +85°C.  2009-2014 Microchip Technology Inc. DS20002194E-page 9 MCP660/1/2/3/4/5/9 Note: Unless otherwise indicated, TA = +25°C, VDD = +2.5V to 5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2, VL = VDD/2, RL = 1 kto VL, CL = 20 pF and CS = VSS. Other DC Voltages and Currents 9 8 Supply Current (mA/amplifier) VDD = 5.5V 100 VDD = 2.5V VOL – VSS 10 6.5 6.0 5.5 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 FIGURE 2-19: Supply Voltage. Supply Current vs. Power 6 Supply Current (mA/amplifier) VDD = 5.5V 20 15 10 VDD = 5.5V 5 VDD = 2.5V 4 3 2 1 VDD – VOH FIGURE 2-17: Output Voltage Headroom vs. Ambient Temperature. 100 80 60 40 20 0 -20 -40 -60 -80 -100 6.0 5.5 5.0 4.5 4.0 3.5 125 3.0 100 2.5 0 25 50 75 Ambient Temperature (°C) 2.0 -25 1.5 -50 1.0 0 0 0.5 VDD = 2.5V -0.5 Output Headroom (mV) Power Supply Voltage (V) VOL – VSS 25 Common Mode Input Voltage (V) FIGURE 2-20: Supply Current vs. Common-Mode Input Voltage. 6.5 6.0 5.5 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 +125°C +85°C +25°C -40°C 0.0 Output Short Circuit Current (mA) 2 7 35 5 +125°C +85°C +25°C -40°C 3 100 RL = 1 kΩ 30 4 0.0 1 10 Output Current Magnitude (mA) FIGURE 2-16: Output Voltage Headroom vs. Output Current. 40 5 0 1 45 6 1 VDD – VOH 0.1 7 0.5 Output Voltage Headroom (mV) 1000 0.0 2.2 Power Supply Voltage (V) FIGURE 2-18: Output Short Circuit Current vs. Power Supply Voltage. DS20002194E-page 10  2009-2014 Microchip Technology Inc. MCP660/1/2/3/4/5/9 Note: Unless otherwise indicated, TA = +25°C, VDD = +2.5V to 5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2, VL = VDD/2, RL = 1 kto VL, CL = 20 pF and CS = VSS. 80 80 90 75 75 Gain Bandwidth Product (MHz) 100 80 70 60 50 CMRR PSRR+ PSRR- 30 20 65 VDD = 5.5V VDD = 2.5V 60 60 55 55 50 50 GBWP 45 45 FIGURE 2-21: Frequency. CMRR and PSRR vs. 6.0 5.5 5.0 4.5 4.0 3.5 3.0 2.5 40 2.0 10M 1.E+7 1.5 1M 1.E+6 1.0 100k 1.E+5 Frequency (Hz) 0.5 10k 1.E+4 0.0 1k 1.E+3 -0.5 40 10 100 1.E+2 Common Mode Input Voltage (V) FIGURE 2-24: Gain-Bandwidth Product and Phase Margin vs. Common-Mode Input Voltage. 80 80 120 -30 75 75 100 -60 AOL 80 -90 60 -120 40 -150 | AOL | 20 -180 0 -210 -20 -240 1 1.E+ 10 1.E+ 100 1.E+ 1k 10k 1M 10M 1G 1.E+ 1.E+ 100k 1.E+ 1.E+ 1.E+ 100M 1.E+ 1.E+ 0 1 2 3 4 5 6 7 8 9 Frequency (Hz) Gain Bandwidth Product (MHz) FIGURE 2-22: Frequency. 80 75 75 70 PM 60 55 65 VDD = 5.5V VDD = 2.5V 60 55 50 50 GBWP 45 40 -50 -25 0 25 50 75 100 Ambient Temperature (°C) 65 VDD = 5.5V VDD = 2.5V 60 60 55 55 50 50 GBWP 45 45 40 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 Output Voltage (V) 45 40 125 FIGURE 2-23: Gain-Bandwidth Product and Phase Margin vs. Ambient Temperature.  2009-2014 Microchip Technology Inc. 70 PM 65 FIGURE 2-25: Gain-Bandwidth Product and Phase Margin vs. Output Voltage. 80 65 70 40 Open-Loop Gain vs. 70 Gain Bandwidth Product (MHz) 0 Open-Loop Phase (°) 140 Phase Margin (°) Open-Loop Gain (dB) 70 PM 65 Phase Margin (°) 40 70 Phase Margin (°) Frequency Response Closed-Loop Output Impedance (Ω) CMRR, PSRR (dB) 2.3 100 10 G = 101 V/V G = 11 V/V G = 1 V/V 1 0.1 10k 1.0E+04 100k 1.0E+05 1M 10M 1.0E+06 1.0E+07 Frequency (Hz) 100M 1.0E+08 FIGURE 2-26: Closed-Loop Output Impedance vs. Frequency. DS20002194E-page 11 MCP660/1/2/3/4/5/9 10 150 9 8 140 7 6 5 GN = 1 V/V GN = 2 V/V GN  4 V/V 4 3 2 1 0 10p 1.0E-11 Channel-to-Channel Separation; RTI (dB) Gain Peaking (dB) Note: Unless otherwise indicated, TA = +25°C, VDD = +2.5V to 5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2, VL = VDD/2, RL = 1 kto VL, CL = 20 pF and CS = VSS. 130 FIGURE 2-27: Gain Peaking vs. Normalized Capacitive Load. DS20002194E-page 12 VCM = VDD/2 G = +1 V/V 120 110 100 90 80 70 60 100p 1n 1.0E-10 1.0E-09 Normalized Capacitive Load; CL/GN (F) RS = 0Ω RS = 100Ω RS = 1 kΩ RS = 10 kΩ RS = 100 kΩ 50 1k 1.E+03 10k 1.E+04 100k 1M 1.E+05 1.E+06 Frequency (Hz) 10M 1.E+07 FIGURE 2-28: Channel-to-Channel Separation vs. Frequency.  2009-2014 Microchip Technology Inc. MCP660/1/2/3/4/5/9 Note: Unless otherwise indicated, TA = +25°C, VDD = +2.5V to 5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2, VL = VDD/2, RL = 1 kto VL, CL = 20 pF and CS = VSS. Noise and Distortion 1.E+4 10µ Input Noise; eni(t) (µV) 20 1.E+3 1µ 1.E+2 100n 1.E+1 10n 1 1.E+0 100 1.E+2 10 1.E+1 1k 1.E+3 10k 1.E+4 10 5 0 -5 -10 Analog NPBW = 0.1 Hz Sample Rate = 2 SPS VOS = -953 µV -15 0 1M 1.E+7 100k 10M 1.E+5 1.E+6 Frequency (Hz) FIGURE 2-29: vs. Frequency. 200 180 160 140 120 100 80 60 40 20 0 Representative Part 15 -20 1.E+0 1n 0.1 1.E-1 Input Noise Voltage Density Input Noise Voltage Density (nV/Hz) THD + Noise (%) VDD = 2.5V VDD = 5.5V 5 10 15 20 25 30 35 40 45 50 55 60 65 Time (min) FIGURE 2-32: 0.1 Hz Filter. 1 VDD = 5.0V VOUT = 2 VP-P 0.1 0.01 0.001 BW = 22 Hz to 80 kHz 0.0001 100 1.E+2 Change in Gain Magnitude (%) VDD = 2.5V VDD = 5.5V 5.5 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 -0.5 f = 1 MHz Common Mode Input Voltage (V) FIGURE 2-31: Input Noise Voltage Density vs. Input Common-Mode Voltage with f = 1 MHz.  2009-2014 Microchip Technology Inc. FIGURE 2-33: 1k 1.E+3 10k 1.E+4 Frequency (Hz) 100k 1.E+5 THD+N vs. Frequency. 0.2 0.2 Positive Video Negative Video 0.1 0.1 0.0 0.0 -0.1 -0.1 -0.2 -0.2 -0.3 -0.3 ∆(|G|) Representative Part -0.4 -0.4 VDD = 2.5V -0.5 -0.5 VSS = -2.5V -0.6 -0.6 VL = 0V -0.7 -0.7 RL = 150Ω -0.8 -0.8 Normalized to DC VIN = 0V NTSC -0.9 -0.9 ∆(G) -1.0 -1.0 -0.8 -0.6 -0.4 -0.2 0.0 0.2 0.4 0.6 0.8 DC Input Voltage (V) Change in Gain Phase (°) 6.0 5.5 5.0 4.5 4.0 3.5 3.0 2.5 1.5 1.0 0.5 0.0 -0.5 FIGURE 2-30: Input Noise Voltage Density vs. Input Common-Mode Voltage with f = 100 Hz. Input Noise Voltage Density (nV/Hz) G = 1 V/V G = 11 V/V BW = 22 Hz to > 500 kHz Common Mode Input Voltage (V) 20 18 16 14 12 10 8 6 4 2 0 Input Noise vs. Time with f = 100 Hz 2.0 Input Noise Voltage Density (V/Hz) 2.4 FIGURE 2-34: Change in Gain Magnitude and Phase vs. DC Input Voltage. DS20002194E-page 13 MCP660/1/2/3/4/5/9 Note: Unless otherwise indicated, TA = +25°C, VDD = +2.5V to 5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2, VL = VDD/2, RL = 1 kto VL, CL = 20 pF and CS = VSS. 2.5 Time Response VIN 0 Output Voltage (V) Output Voltage (10 mV/div) VDD = 5.5V G=1 VOUT 20 40 60 5.5 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 80 100 120 140 160 180 200 Time (ns) Non-Inverting Small Signal VIN VOUT 100 200 FIGURE 2-38: Response. 300 400 Time (ns) 500 Input, Output Voltages (V) VIN VOUT 600 Inverting Large Signal Step 7 VDD = 5.5V G=1 VDD = 5.5V G=2 6 VOUT 5 VIN 4 3 2 1 0 -1 0 100 200 FIGURE 2-36: Step Response. 300 400 500 Time (ns) 600 700 800 Non-Inverting Large Signal 0 Output Voltage (10 mV/div) VDD = 5.5V G = -1 RF = 402Ω VOUT 50 100 150 200 250 300 350 400 450 500 Time (ns) FIGURE 2-37: Response. DS20002194E-page 14 Inverting Small Signal Step 1 2 3 4 5 6 Time (µs) 7 8 9 10 FIGURE 2-39: The MCP660/1/2/3/4/5/9 Family Shows No Input Phase Reversal with Overdrive. VIN 0 VDD = 5.5V G = -1 RF = 402Ω 0 Slew Rate (V/µs) Output Voltage (V) FIGURE 2-35: Step Response. 5.5 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 50 45 40 35 30 25 20 15 10 5 0 Falling Edge VDD = 5.5V VDD = 2.5V Rising Edge -50 -25 FIGURE 2-40: Temperature. 0 25 50 75 Ambient Temperature (°C) 100 125 Slew Rate vs. Ambient  2009-2014 Microchip Technology Inc. MCP660/1/2/3/4/5/9 Note: Unless otherwise indicated, TA = +25°C, VDD = +2.5V to 5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2, VL = VDD/2, RL = 1 kto VL, CL = 20 pF and CS = VSS. Maximum Output Voltage Swing (VP-P) 10 VDD = 5.5V VDD = 2.5V 1 0.1 100k 1.E+05 1M 10M 1.E+06 1.E+07 Frequency (Hz) 100M 1.E+08 FIGURE 2-41: Maximum Output Voltage Swing vs. Frequency.  2009-2014 Microchip Technology Inc. DS20002194E-page 15 MCP660/1/2/3/4/5/9 Note: Unless otherwise indicated, TA = +25°C, VDD = +2.5V to 5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2, VL = VDD/2, RL = 1 kto VL, CL = 20 pF and CS = VSS. Chip Select Response 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0.0 0.40 CS = VDD 0.35 CS Hysteresis (V) CS Current (µA) 2.6 0.30 0.20 0.10 0.05 0.00 FIGURE 2-42: Supply Voltage. -50 CS 2.0 1.5 VOUT 1.0 On 0.5 0.0 Off 100 125 CS Hysteresis vs. Ambient 4 3 VDD = 2.5V 2 1 VDD = 5.5V Off 0 -0.5 0 2 4 6 8 10 12 Time (µs) 14 16 18 20 FIGURE 2-43: CS and Output Voltages vs. Time with VDD = 2.5V. 6 3 VOUT On 1 -25 Off Off 0 25 50 75 Ambient Temperature (°C) 100 125 FIGURE 2-46: CS Turn-On Time vs. Ambient Temperature. CS Pull-down Resistor (MΩ) 4 2 -50 8 VDD = 5.5V G= 1 VL = 0V CS 5 0 0 25 50 75 Ambient Temperature (°C) 5 VDD = 2.5V G=1 VL = 0V CS Turn On Time (µs) 2.5 -25 FIGURE 2-45: Temperature. CS Current vs. Power 3.0 CS, VOUT (V) VDD = 2.5V 0.15 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 Power Supply Voltage (V) CS, VOUT (V) VDD = 5.5V 0.25 Representative Part 7 6 5 4 3 2 1 0 -1 0 1 2 3 4 5 6 Time (µs) 7 8 9 10 FIGURE 2-44: CS and Output Voltages vs. Time with VDD = 5.5V. DS20002194E-page 16 -50 -25 0 25 50 75 Ambient Temperature (°C) 100 125 FIGURE 2-47: CS’s Pull-Down Resistor (RPD) vs. Ambient Temperature.  2009-2014 Microchip Technology Inc. MCP660/1/2/3/4/5/9 CS = VDD 1.E-06 1µ Output Leakage Current (A) 0.0 -0.2 -0.4 -0.6 -0.8 -1.0 -1.2 -1.4 -1.6 -1.8 -2.0 CS = VDD = 5.5V 100n 1.E-07 10n 1.E-08 1n 1.E-09 +125°C +85°C Power Supply Voltage (V) FIGURE 2-48: Quiescent Current in Shutdown vs. Power Supply Voltage.  2009-2014 Microchip Technology Inc. 6.5 6.0 5.5 5.0 4.5 4.0 3.5 100p 1.E-10 3.0 2.5 2.0 1.5 1.0 0.5 +125°C +85°C +25°C -40°C 0.0 Negative Power Supply Current; ISS (µA) Note: Unless otherwise indicated, TA = +25°C, VDD = +2.5V to 5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2, VL = VDD/2, RL = 1 kto VL, CL = 20 pF and CS = VSS. +25°C 10p 1.E-11 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 Output Voltage (V) FIGURE 2-49: Output Voltage. Output Leakage Current vs. DS20002194E-page 17 MCP660/1/2/3/4/5/9 NOTES: DS20002194E-page 18  2009-2014 Microchip Technology Inc. PIN DESCRIPTIONS Descriptions of the pins are listed in Table 3-1. TABLE 3-1: PIN FUNCTION TABLE SOT-23 SOIC, TSSOP MSOP DFN 4x4 QFN Symbol 5 6 2 2 4 2 2 2 4 2 2 2 1 VIN-, VINA- Inverting Input (op amp A) 4 5 3 3 3 3 3 3 3 3 3 3 2 VIN+, VINA+ Non-inverting Input (op amp A) 3 4 7 7 5 8 8 7 6 4 10 10 3 VDD 10 10 — — — 5 5 — — 5 7 7 4 VINB+ Non-inverting Input (op amp B) 9 9 — — — 6 6 — — 6 8 8 5 VINB- Inverting Input (op amp B) 8 8 — — — 7 7 — — 7 9 9 6 VOUTB Output (op amp B) — — — — — — — — — — — — 7 CSBC Chip Select Digital Input (op amps B and C) 14 14 — — — — — — — 8 — — 8 VOUTC Output (op amp C) 13 13 — — — — — — — 9 — — 9 VINC- Inverting Input (op amp C) 12 12 — — — — — — — 10 — — 10 VINC+ Non-inverting Input (op amp C) 11 11 4 4 2 4 4 4 2 11 4 4 11 VSS — — — — — — — — — 12 — — 12 VIND+ Inverting Input (op amp D) — — — — — — — — — 13 — — 13 VIND- Inverting Input (op amp D) — — — — — — — — — 14 — — 14 VOUTD Output (op amp D) — — — — — — — — — — — — 15 CSAD Chip Select Digital Input (op amps A and D) 6 7 6 6 1 1 1 6 1 1 1 1 16 VOUT, VOUTA 17 — — 9 — — 9 — — — — 11 17 EP Exposed Thermal Pad (EP); must be connected to VSS — — — 8 — — — 8 5 — 5 5 — CS, CSA Chip Select Digital Input (op amp A) — — — — — — — — — — 6 6 — CSB Chip Select Digital Input (op amp B) 1, 5 — — — 1, 5 — — — — — NC No Internal Connection 1, 2, 7, 1, 2, 3 1, 5, 8 15, 16 Description Positive Power Supply Negative Power Supply Output (op amp A) MCP660/1/2/3/4/5/9 DS20002194E-page 19 SOIC MCP669 DFN MCP665 MSOP, SOIC MCP664 SOT-23 MCP663 2x3 TDFN MCP662 SOIC MCP661 SOIC, TSSOP MCP660 4x4 QFN  2009-2014 Microchip Technology Inc. 3.0 MCP660/1/2/3/4/5/9 3.1 Analog Outputs 3.4 Chip Select Digital Input (CS) The analog output pins (VOUT) are low-impedance voltage sources. The input (CS) is a CMOS, Schmitt-triggered input that places the part into a low-power mode of operation. 3.2 3.5 Analog Inputs Exposed Thermal Pad (EP) The non-inverting and inverting inputs (VIN+, VIN-, …) are high-impedance CMOS inputs with low bias currents. There is an internal connection between the exposed thermal pad (EP) and the VSS pin; they must be connected to the same potential on the printed circuit board (PCB). 3.3 This pad can be connected to a PCB ground plane to provide a larger heat sink. This improves the package thermal resistance (JA). Power Supply Pins The positive power supply (VDD) is 2.5V to 5.5V higher than the negative power supply (VSS). For normal operation, the other pins are between VSS and VDD. Typically, these parts are used in a single (positive) supply configuration. In that case, VSS is connected to Ground and VDD is connected to the supply. VDD will need bypass capacitors. DS20002194E-page 20  2009-2014 Microchip Technology Inc. MCP660/1/2/3/4/5/9 4.0 APPLICATIONS The MCP660/1/2/3/4/5/9 family is manufactured using the Microchip state-of-the-art CMOS process. It is designed for low-cost, low-power and high-speed applications. Its low supply voltage, low quiescent current and wide bandwidth make the MCP660/1/2/3/4/5/9 ideal for battery-powered applications. 4.1 When implemented as shown, resistors R1 and R2 also limit the current through D1 and D2. VDD V1 Input 4.1.1 V2 PHASE REVERSAL INPUT VOLTAGE AND CURRENT LIMITS The electrostatic discharge (ESD) protection on the inputs can be depicted as shown in Figure 4-1. This structure was chosen to protect the input transistors and to minimize input bias current (IB). The input ESD diodes clamp the inputs when they try to go more than one diode drop below VSS. They also clamp any voltages that go too far above VDD; their breakdown voltage is high enough to allow normal operation and low enough to bypass quick ESD events within the specified limits. VDD Bond Pad VIN+ Bond Pad Bond V IN Pad VSS Bond Pad FIGURE 4-1: Structures. MCP66X VOUT R2 V SS –  minimum expected V2  R2  -----------------------------------------------------------------------2 mA FIGURE 4-2: Inputs. Protecting the Analog It is also possible to connect the diodes to the left of the resistors R1 and R2. If so, the currents through the diodes D1 and D2 need to be limited by some other mechanism. The resistors then serve as in-rush current limiters; the DC current into the input pins (VIN+ and VIN-) should be very small. A significant amount of current can flow out of the inputs (through the ESD diodes) when the common-mode voltage (VCM) is below ground (VSS); see Figure 2-13. Applications that are high-impedance may need to limit the usable voltage range. 4.1.3 Input Stage D2 V SS –  minimum expected V1  R1  -----------------------------------------------------------------------2 mA The input devices are designed to not exhibit phase inversion when the input pins exceed the supply voltages. Figure 2-39 shows an input voltage exceeding both supplies with no phase inversion. 4.1.2 D1 R1 NORMAL OPERATION The input stage of the MCP660/1/2/3/4/5/9 op amps uses a differential PMOS input stage. It operates at low common-mode input voltages (VCM), with VCM between VSS – 0.3V and VDD – 1.3V. To ensure proper operation, the input offset voltage (VOS) is measured at both VCM = VSS – 0.3V and VCM = VDD – 1.3V. See Figures 2-5 and 2-6 for temperature effects. When operating at very low non-inverting gains, the output voltage is limited at the top by the VCM range (< VDD – 1.3V); see Figure 4-3. Simplified Analog Input ESD In order to prevent damage and/or improper operation of these amplifiers, the circuit must limit the currents (and voltages) at the input pins (see Section 1.1 “Absolute Maximum Ratings †”). Figure 4-2 shows the recommended approach to protecting these inputs. The internal ESD diodes prevent the input pins (VIN+ and VIN-) from going too far below ground, while the resistors R1 and R2 limit the possible current drawn out of the input pins. Diodes D1 and D2 prevent the input pins (VIN+ and VIN-) from going too far above VDD and dump any currents onto VDD.  2009-2014 Microchip Technology Inc. VDD VIN + - MCP66X VOUT V SS  V IN V OUT  V DD – 1.3V FIGURE 4-3: Unity-Gain Voltage Limitations for Linear Operation. DS20002194E-page 21 MCP660/1/2/3/4/5/9 4.2 Rail-to-Rail Output 4.2.1 Figure 4-5 shows the power calculations used for a single op amp: MAXIMUM OUTPUT VOLTAGE The Maximum Output Voltage (see Figures 2-16 and 2-17) describes the output range for a given load. For example, the output voltage swings to within 50 mV of the negative rail with a 1 k load tied to VDD/2. 4.2.2 OUTPUT CURRENT • RSER is 0 in most applications and can be used to limit IOUT. • VOUT is the op amp’s output voltage. • VL is the voltage at the load. • VLG is the load’s ground point. • VSS is usually ground (0V). The input currents are assumed to be negligible. The currents shown in Figure 4-5 can be approximated using Equation 4-1: IOUT is positive when it flows out of the op amp into the external circuit. EQUATION 4-1: 6.0 5.5 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 -0.5 V OUT – V LG I OUT = IL = -----------------------------R SER + R L VOH Limited I DD  I Q + max  0, IOUT  (VDD = 5.5V) RL = 1 kΩ I SS  – I Q + min  0, IOUT  +ISC Limited -ISC Limited RL = 100Ω RL = 10Ω Where: IQ = Quiescent supply current 120 100 80 60 40 20 0 IOUT (mA) FIGURE 4-4: 4.2.3 -20 -40 -60 -100 -80 VOL Limited -120 VOUT (V) Figure 4-4 shows the possible combinations of output voltage (VOUT) and output current (IOUT), when VDD = 5.5V. EQUATION 4-2: Output Current. POA(t) = IDD (VDD – VOUT) + ISS (VSS – VOUT) POWER DISSIPATION PRSER(t) = IOUT2RSER Since the output short circuit current (ISC) is specified at ±90 mA (typical), these op amps are capable of both delivering and dissipating significant power. VDD IOUT + MCP66X - ISS The maximum op amp power, for resistive loads, occurs when VOUT is halfway between VDD and VLG or halfway between VSS and VLG. 2 max  V DD – V LG – V SS  POAmax  -----------------------------------------------------------4  RSER + RL  RSER VL IL RL VLG VSS FIGURE 4-5: Calculations. PL(t) = IL2RL EQUATION 4-3: VOUT IDD The instantaneous op amp power (POA(t)), RSER power (PRSER(t)) and load power (PL(t)) are calculated in Equation 4-2: Diagram for Power The maximum ambient to junction temperature rise (TJA) and junction temperature (TJ) can be calculated using POAmax, the ambient temperature (TA), the package thermal resistance (JA, found in the Temperature Specifications table) and the number of op amps in the package (assuming equal power dissipations), as shown in Equation 4-4: EQUATION 4-4: TJA = POA  t   JA  nP OAmax  JA T J = T A + T JA Where: n = DS20002194E-page 22 Number of op amps in the package (1, 2)  2009-2014 Microchip Technology Inc. MCP660/1/2/3/4/5/9 The power derating across temperature for an op amp in a particular package can be easily calculated (assuming equal power dissipations): EQUATION 4-5: T Jmax – T A P OAmax  -------------------------n  JA Where: TJmax = Absolute maximum junction temperature Several techniques are available to reduce TJA for a given POAmax: • Lower JA - Use another package - PCB layout (ground plane, etc.) - Heat sinks and air flow • Reduce POAmax - Increase RL - Limit IOUT (using RSER) - Decrease VDD Improving Stability 4.4.1 CAPACITIVE LOADS Driving large capacitive loads can cause stability problems for voltage feedback op amps. As the load capacitance increases, the phase margin (stability) of the feedback loop decreases and the closed-loop bandwidth is reduced. This produces gain peaking in the frequency response, with overshoot and ringing in the step response. A unity-gain buffer (G = +1) is the most sensitive to capacitive loads, though all gains show the same general behavior. When driving large capacitive loads with these op amps (e.g., > 20 pF when G = +1), a small series resistor at the output (RISO in Figure 4-6) improves the phase margin of the feedback loop by making the output load resistive at higher frequencies. The bandwidth will generally be lower than bandwidth without the capacitive load. RG DG is the peak-to-peak change in the AC gain magnitude (color hue), as the DC level (luminance) is changed, in percentile units (%). DP is the peak-to-peak change in the AC gain phase (color saturation), as the DC level (luminance) is changed, in degree (°) units. RISO VOUT Distortion Differential gain (DG) and differential phase (DP) refer to the nonlinear distortion produced by an NTSC or a phase-alternating line (PAL) video component. The AC Electrical Specifications table and Figure 2-34 show the typical performance of the MCP661, configured as a gain of +2 amplifier (see Figure 4-10), when driving one back-matched video load (150, for 75 cable). Microchip tests use a sine wave at NTSC’s color sub-carrier frequency of 3.58 MHz, with a 0.286VP-P magnitude. The DC input voltage is changed over a +0.7V range (positive video) or a -0.7V range (negative video). RF + RN CL MCP66X FIGURE 4-6: Output Resistor, RISO, Stabilizes Large Capacitive Loads. Figure 4-7 gives recommended RISO values for different capacitive loads and gains. The x-axis is the normalized load capacitance (CL/GN), where GN is the circuit’s noise gain. For non-inverting gains, GN and the Signal Gain are equal. For inverting gains, GN is 1 + |Signal Gain| (e.g., -1 V/V gives GN = +2 V/V). 100 Recommended RISO (Ω) 4.3 4.4 10 GN = +1 GN  +2 1 10p 1.E-11 100p 1n 1.E-10 1.E-09 Normalized Capacitance; CL/GN (F) 10n 1.E-08 FIGURE 4-7: Recommended RISO Values for Capacitive Loads. After selecting RISO for the circuit, double-check the resulting frequency response peaking and step response overshoot. Modify the value of RISO until the response is reasonable. Bench evaluation and simulations with the MCP660/1/2/3/4/5/9 SPICE macro model are helpful.  2009-2014 Microchip Technology Inc. DS20002194E-page 23 MCP660/1/2/3/4/5/9 4.4.2 GAIN PEAKING Figure 4-8 shows an op amp circuit that represents non-inverting amplifiers (VM is a DC voltage and VP is the input) or inverting amplifiers (VP is a DC voltage and VM is the input). The capacitances CN and CG represent the total capacitance at the input pins; they include the op amp’s common-mode input capacitance (CCM), board parasitic capacitance and any capacitor placed in parallel. VP RN CN + VM RG FIGURE 4-8: Capacitance. CG Figures 2-37 and 2-38 show the small signal and large signal step responses at G = -1 V/V. Since the noise gain is 2 V/V and CG  10 pF, the resistors were chosen to be RF = RG = 401 and RN = 200. It is also possible to add a capacitor (CF) in parallel with RF to compensate for the destabilizing effect of CG. This makes it possible to use larger values of RF. The conditions for stability are summarized in Equation 4-6. EQUATION 4-6: MCP66X Given: VOUT - Figures 2-35 and 2-36 show the small signal and large signal step responses at G = +1 V/V. The unity-gain buffer usually has RF = 0 and RG open. RF G N1 = 1 + ------RG CG G N2 = 1 + ------CF RF 1 f F = --------------------2  R F CF G N1 fZ = f F  ----------  G N2 Amplifier with Parasitic CG acts in parallel with RG (except for a gain of +1 V/V), which causes an increase in gain at high frequencies. CG also reduces the phase margin of the feedback loop, which becomes less stable. This effect can be reduced by either reducing CG or RF. CN and RN form a low-pass filter that affects the signal at VP. This filter has a single real pole at 1/(2RN/CN). We need: f GBWP fF  ---------------, G N1  G N2 2G N2 f GBWP fF  ---------------, G N1  G N2 4G N1 1.E+05 100k Maximum Recommended R (Ω) F The largest value of RF that should be used depends on the noise gain (see GN in Section 4.4.1 “Capacitive Loads”), CG and the open-loop gain’s phase shift. Figure 4-9 shows the maximum recommended RF for several CG values. Some applications may modify these values to reduce either output loading or gain peaking (step response overshoot). CG = 10 pF CG = 32 pF CG = 100 pF CG = 320 pF CG = 1 nF 10k 1.E+04 GN > +1 V/V 1k 1.E+03 100 1.E+02 1 FIGURE 4-9: RF vs. Gain. DS20002194E-page 24 10 Noise Gain; GN (V/V) 100 Maximum Recommended  2009-2014 Microchip Technology Inc. MCP660/1/2/3/4/5/9 4.5 MCP663 and MCP665 Chip Select 4.7 High Speed PCB Layout The MCP663 is a single amplifier with Chip Select (CS). When CS is pulled high, the supply current drops to 1 µA (typical) and flows through the CS pin to VSS. When this happens, the amplifier output is put into a high-impedance state. By pulling CS low, the amplifier is enabled. The CS pin has an internal 5 M (typical) pulldown resistor connected to VSS, so it will go low if the CS pin is left floating. Figures 1-1, 2-43 and 2-44 show the output voltage and supply current response to a CS pulse. These op amps are fast enough that a little extra care in the printed circuit board (PCB) layout can make a significant difference in performance. Good PC board layout techniques will help you achieve the performance shown in the specifications and typical performance curves; it will also help minimize electromagnetic compatibility (EMC) issues. The MCP665 is a dual amplifier with two CS pins; CSA controls op amp A and CSB controls op amp B. These op amps are controlled independently, with an enabled quiescent current (IQ) of 6 mA/amplifier (typical) and a disabled IQ of 1 µA/amplifier (typical). The IQ seen at the supply pins is the sum of the two op amps’ IQ; the typical value for the IQ of the MCP665 will be 2 µA, 6 mA or 12 mA when there are 0, 1 or 2 amplifiers enabled, respectively. Separate digital from analog, low-speed from high-speed and low-power from high-power. This will reduce interference. 4.6 Power Supply With this family of operational amplifiers, the power supply pin (VDD for single supply) should have a local bypass capacitor (i.e., 0.01 µF to 0.1 µF) within 2 mm for good high-frequency performance. Surface mount, multilayer ceramic capacitors, or their equivalent, should be used. Use a solid ground plane. Connect the bypass local capacitor(s) to this plane with minimal length traces. This cuts down inductive and capacitive crosstalk. Keep sensitive traces short and straight. Separate them from interfering components and traces. This is especially important for high-frequency (low rise time) signals. Sometimes, it helps to place guard traces next to victim traces. They should be on both sides of the victim trace and as close as possible. Connect guard traces to ground plane at both ends and in the middle for long traces. Use coax cables, or low inductance wiring, to route signal and power to and from the PCB. Mutual and self inductance of power wires is often a cause of crosstalk and unusual behavior. These op amps require a bulk capacitor (i.e., 2.2 µF or larger) within 50 mm to provide large, slow currents. Tantalum capacitors, or their equivalent, may be a good choice. This bulk capacitor can be shared with other nearby analog parts as long as crosstalk through the power supplies does not prove to be a problem.  2009-2014 Microchip Technology Inc. DS20002194E-page 25 MCP660/1/2/3/4/5/9 4.8 Typical Applications 4.8.1 4.8.3 50 LINE DRIVER Figure 4-10 shows the MCP661 driving a 50 line. The large output current (e.g., see Figure 2-18) makes it possible to drive a back-matched line (RM2, the 50 line and the 50 load at the far end) to more than ±2V (the load at the far end sees ±1V). It is worth mentioning that the 50 line and the 50 load at the far end together can be modeled as a simple 50 resistor to ground. -2.5V RM2 49.9 50 Figure 4-11 shows a transimpedance amplifier, using the MCP661 op amp, in a photo detector circuit. The photo detector is a capacitive current source. RF provides enough gain to produce 10 mV at VOUT. CF stabilizes the gain and limits the transimpedance bandwidth to about 1.1 MHz. The parasitic capacitance of RF (e.g., 0.2 pF for a 0805 SMD) acts in parallel with CF. CF 1.5 pF ID 100 nA CD 30 pF - RF VDD/2 RF 100 k RL RF VOB ½ MCP662 H-Bridge Driver. This circuit automatically makes the noise gains (GN) equal, when the gains are set properly, so that the frequency responses match well (in magnitude and in phase). Equation 4-7 shows how to calculate RGT and RGB so that both op amps have the same DC gains; GDM needs to be selected first. EQUATION 4-7: VOT – V OB G DM  --------------------------  1 V/V VDD V IN – ----------2 RF R GT = --------------------G DM ------------ – 1 2 RF R GB = -----------GDM -----------2 Equation 4-8 gives the resulting common-mode and differential mode output voltages. EQUATION 4-8: VOT + V OB VDD --------------------------- = ----------2 2 VOUT + VOT RF + FIGURE 4-12: OPTICAL DETECTOR AMPLIFIER Photo Detector ½ MCP662 - The output headroom limits would be VOL = -2.3V and VOH = +2.3V (see Figure 2-16), leaving some design room for the ±2V signal. The open-loop gain (AOL) typically does not decrease significantly with a 100 load (see Figure 2-11). The maximum power dissipated is about 48 mW (see Section 4.2.3 “Power Dissipation”), so the temperature rise (for the MCP661 in the SOIC-8 package) is under 8°C. 4.8.2 + RGB 50 Line Driver. FIGURE 4-10: VIN RGT RF 301 RG 301 Figure 4-12 shows the MCP662 dual op amp used as an H-bridge driver. The load could be a speaker or a DC motor. 50 Line MCP66X +2.5V + RM1 49.9 H-BRIDGE DRIVER V DD V OT – VOB = G DM  V IN – -----------  2  MCP661 VDD/2 FIGURE 4-11: Transimpedance Amplifier for an Optical Detector. DS20002194E-page 26  2009-2014 Microchip Technology Inc. MCP660/1/2/3/4/5/9 5.0 DESIGN AIDS Microchip provides the basic design aids needed for the MCP660/1/2/3/4/5/9 family of op amps. 5.1 SPICE Macro Model The latest SPICE macro model for the MCP660/1/2/3/4/5/9 op amps is available on the Microchip web site at www.microchip.com. This model is intended to be an initial design tool that works well in the linear region of operation over the temperature range of the op amp. See the model file for information on its capabilities. Bench testing is a very important part of any design and cannot be replaced with simulations. Also, simulation results using this macro model need to be validated, by comparing them to the data sheet specifications and characteristic curves. 5.2 FilterLab® Software Microchip’s FilterLab® software is an innovative software tool that simplifies analog active filter (using op amps) design. Available at no cost from the Microchip web site at www.microchip.com/filterlab, the FilterLab design tool provides full schematic diagrams of the filter circuit with component values. It also outputs the filter circuit in SPICE format, which can be used with the macro model to simulate actual filter performance. 5.3 Microchip Advanced Part Selector (MAPS) MAPS is a software tool that helps efficiently identify Microchip devices that fit a particular design requirement. Available at no cost from the Microchip web site at www.microchip.com/maps, the MAPS is an overall selection tool for Microchip’s product portfolio that includes Analog, Memory, MCUs and DSCs. Using this tool, a filter can be defined to sort features for a parametric search of device and export side-by-side technical comparison reports. Helpful links are also provided for data sheets, purchase and sampling of Microchip parts. 5.4 Analog Demonstration and Evaluation Boards Microchip offers a broad spectrum of analog demonstration and evaluation boards that are designed to help customers achieve faster time to market. For a complete listing of these boards and their corresponding user’s guides and technical information, visit the Microchip web site at www.microchip.com/analog tools. Some boards that are especially useful are: • MCP6XXX Amplifier Evaluation Board 1, part number: MCP6XXXEV-AMP1 • MCP6XXX Amplifier Evaluation Board 2, part number: MCP6XXXEV-AMP2 • MCP6XXX Amplifier Evaluation Board 3, part number: MCP6XXXEV-AMP3 • MCP6XXX Amplifier Evaluation Board 4, part number: MCP6XXXEV-AMP4 • Active Filter Demo Board Kit, part number: MCP6XXXDM-FLTR • 8-Pin SOIC/MSOP/TSSOP/DIP Evaluation Board, part number: SOIC8EV • MCP661 Line Driver Demo Board, part number: MCP661DM-LD 5.5 Design and Application Notes The following Microchip Analog Design Note and Application Notes are recommended as supplemental reference resources. They are available on the Microchip web site at www.microchip.com/appnotes. • ADN003: “Select the Right Operational Amplifier for your Filtering Circuits”, DS21821 • AN722: “Operational Amplifier Topologies and DC Specifications”, DS00722 • AN723: “Operational Amplifier AC Specifications and Applications”, DS00723 • AN884: “Driving Capacitive Loads With Op Amps”, DS00884 • AN990: “Analog Sensor Conditioning Circuits – An Overview”, DS00990 • AN1228: “Op Amp Precision Design: Random Noise”, DS01228 Some of these application notes, and others, are listed in the “Signal Chain Design Guide”, DS21825.  2009-2014 Microchip Technology Inc. DS20002194E-page 27 MCP660/1/2/3/4/5/9 NOTES: DS20002194E-page 28  2009-2014 Microchip Technology Inc. MCP660/1/2/3/4/5/9 6.0 PACKAGING INFORMATION 6.1 Package Marking Information Example 5-Lead SOT-23 (MCP661) XXNN YX25 6-Lead SOT-23 (MCP663) Example XXNN JE25 8-Lead TDFN (2x3x0.75 mm) (MCP661) Example ABJ 423 25 8-Lead DFN (3x3x0.9 mm) (MCP662) Device Code MCP662T-E/MF DABQ Note 1: Legend: XX...X Y YY WW NNN e3 * Note: Example DABQ 1423 256 Applies to 8-lead 3x3 DFN Customer-specific information Year code (last digit of calendar year) Year code (last 2 digits of calendar year) Week code (week of January 1 is week ‘01’) Alphanumeric traceability code Pb-free JEDEC® designator for Matte Tin (Sn) This package is Pb-free. The Pb-free JEDEC designator ( e3 ) can be found on the outer packaging for this package. In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information.  2009-2014 Microchip Technology Inc. DS20002194E-page 29 MCP660/1/2/3/4/5/9 8-Lead MSOP (3x3 mm) (MCP662) Example 662E 423256 8-Lead SOIC (3.90 mm) (MCP661, MCP662, MCP663) Example MCP661E e3 SN^^1423 256 NNN 10-Lead DFN (3x3x0.9 mm) (MCP665) Example Device Code MCP665T-E/MF BAFD Note 1: 10-Lead MSOP (3x3 mm) (MCP665) BAFD 1423 256 Applies to 10-lead 3x3 DFN Example 665EUN 423256 Legend: XX...X Y YY WW NNN e3 * Note: DS20002194E-page 30 Customer-specific information Year code (last digit of calendar year) Year code (last 2 digits of calendar year) Week code (week of January 1 is week ‘01’) Alphanumeric traceability code Pb-free JEDEC® designator for Matte Tin (Sn) This package is Pb-free. The Pb-free JEDEC designator ( e3 ) can be found on the outer packaging for this package. In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information.  2009-2014 Microchip Technology Inc. MCP660/1/2/3/4/5/9 14-Lead SOIC (3.90 mm) (MCP660, MCP664) Example MCP660 e3 E/SL^^ 1423256 14-Lead TSSOP (4.4 mm) (MCP660, MCP664) Example XXXXXXXX YYWW NNN 664E/ST 14/23 256 16-Lead QFN (4x4x0.9 mm) (MCP669) PIN 1 PIN 1 Legend: XX...X Y YY WW NNN e3 * Note: Example 669 e3 E/ML^^ 1423256 Customer-specific information Year code (last digit of calendar year) Year code (last 2 digits of calendar year) Week code (week of January 1 is week ‘01’) Alphanumeric traceability code Pb-free JEDEC® designator for Matte Tin (Sn) This package is Pb-free. The Pb-free JEDEC designator ( e3 ) can be found on the outer packaging for this package. In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information.  2009-2014 Microchip Technology Inc. DS20002194E-page 31 MCP660/1/2/3/4/5/9        .#  #$ # / !- 0    #  1/ %## !# ## +22--- 2 / b N E E1 3 2 1 e e1 D A2 A c φ A1 L L1 3#   4# 5$8 %1 44"" 5 56 7 5 ( 4 !1# ()* 6$# ! 4 !1#  6, 9 #   : ! !1/ /  ; :  #!%%   : ( 6,  : > 4 !/  ; : = 4 !