MCP6D11
Low-Noise, Precision, 90 MHz Differential I/O Amplifier
Features
General Description
• Low Power
- IQ: 1.4 mA
- Supply Voltage Range: 2.5V to 5.5V
• Gain-Bandwidth Product: 90 MHz
• Slew Rate: 25V/µs
• Low Noise: 5.0 nV/√Hz, f = 10 kHz
• Low Distortion (2Vp-p, 10 kHz):
- HD2: -138 dBc
- HD3: -137 dBc
• Fast Settling: 200 ns to 0.01%
• Low Offset: 150 µV Max.
• Power-Down Function
• Input Vcm-Range Includes Negative Rail
• Rail-to-Rail Output
• Small Packages: MSOP-8, 3 x 3 mm QFN-16
• Extended Temperature Range: -40°C to +125°C
The MCP6D11 from Microchip Technology is a lownoise, low-distortion Differential I/O Amplifier optimized
for driving high-performance 14-, and 16-Bit SAR
ADCs, such as the MCP331x1D ADC family. Featuring
a low 5.0 nV/√Hz input-referred voltage noise and distortion of less than -116 dBc with an input signal of up
to 100 kHz (2Vpp), the MCP6D11 consumes only
3.5 mW of quiescent power on a 2.5V supply. For
power sensitive applications, a Power-Down function
reduces the power consumption to less than 13 µW.
Typical Applications
• Precision ADC Driver:
- 14/16/18-bit SAR ADCs
- Delta-Sigma ADCs
• Single-Ended to Differential Conversion
• Differential Active Filter
• Line Drivers
Through its VOCM pin, the MCP6D11 allows easy
control of its output common-mode voltage, which can
be set independently of the input common-mode
voltage. This, coupled with an input common-mode
range that extends below the negative supply rail, and
a near rail-to-rail output swing capability, results in a
simple driver amplifier solution for a variety of ADCs.
The MCP6D11 is the ideal interface solution for
converting single-ended, ground-referenced signal
sources into a fully differential output signal required to
preserve the high performance of today’s ultra-low
distortion, single-supply ADCs.
The MCP6D11 is specified for the -40°C to +125°C
temperature range and is available in QFN-16
(3 x 3 mm) and MSOP-8 package options.
MCP6D11 Harmonic Distortion with a
10 kHz, 2Vpp Signal
Design Aids
• Microchip Advanced Part Selector (MAPS)
• Application Notes
Related Parts
• MCP331x1D SAR ADCs
2019 Microchip Technology Inc.
DS20006162A-page 1
MCP6D11
NOTES:
DS20006162A-page 2
2019 Microchip Technology Inc.
MCP6D11
1.0
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings †
VDD – VSS .................................................................................................................................................................6.0V
Supply Voltage Turn-on/off max. dV/dt at +25°C .............................................................................................. ±0.35V/µs
Supply Voltage Turn-on/off max. dV/dt at +125°C .............................................................................................. ±0.2V/µs
Current at all Inputs (continuous) ........................................................................................................................ ±10 mA
Voltage at all Inputs and Outputs ...............................................................................................VSS – 0.3V to VDD+0.3V
Differential Input Voltage ......................................................................................................................................... ±1.0V
Current at Output and Supply Pins (continuous)...................................................................................................±20 mA
Storage Temperature .............................................................................................................................-65°C to +150°C
Maximum Junction Temperature .......................................................................................................................... +155°C
ESD protection on all pins (HBM, CDM) 4 kV, 2 kV
† Notice: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions above those
indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability.
AC ELECTRICAL CHARACTERISTICS
Electrical Characteristics: Unless otherwise indicated, TA = 25°C, VDD = +2.5V to 5.5V, VSS = 0V, PD\ = VDD, VOCM = open,
VICM = VDD/2, Single-ended input, G = 1V/V, RF = RG = 1 k, RL = 1 k between differential outputs.
Parameters
Sym.
Min.
Typ. Max.
Units
Test
Level
(Note 1)
Conditions
AC Response
Gain-Bandwidth Product
Bandwidth
(Small-signal, -3 dB)
Bandwidth
(Large-signal, -3 dB)
GBWP
—
90
—
MHz
C
G = 10V/V
BW
—
82
—
MHz
C
G = 1V/V, VOUT_DM = 20mVpp, VDD = 5V
—
80
—
G = 1V/V, VOUT_DM = 20mVpp, VDD = 3V
—
48
—
G = 2V/V, VOUT_DM = 20mVpp, VDD = 5V
—
10
—
—
6.4
—
MHz
C
G = 1V/V, VOUT_DM = 2Vpp, VDD = 5V
—
4
—
MHz
C
G = 1V/V, VOUT_DM = 2Vpp, VDD = 5V
—
27
—
V/µs
C
G = 1V/V, VOUT_DM = 2V step, VDD = 5V
—
26
—
G = 2V/V, VOUT_DM = 2V step, VDD = 5V
—
24
—
G = 1V/V, VOUT_DM = 2V step, VDD = 3V
—
23
—
—
160
—
BW
Bandwidth for 0.1 dB
Gain Flatness
Slew Rate (differential)
Settling Time to 0.1%
SR
tS
Settling Time to 0.01%
Rise and Fall Times
Overdrive Recovery Time
G = 10V/V, VOUT_DM = 20mVpp, VDD = 5V
G = 2V/V, VOUT_DM = 2V step, VDD = 3V
ns
C
G = 1V/V, VOUT_DM = 2V step, VDD = 5V
—
170
—
G = 1V/V, VOUT_DM = 2V step, VDD = 3V
—
200
—
G = 1V/V, VOUT_DM = 2V step, VDD = 5V
G = 1V/V, VOUT_DM = 2V step, VDD = 3V
—
215
—
tR, tF
—
34
—
ns
C
VOUT_DM = 1Vpp step
trec
—
150
—
ns
C
VDD = 5V, 0.5V overdrive
—
200
—
VDD = 3V, 0.5V overdrive
Closed-Loop Output Impedance
Rout
—
0.1
—
C
f = 1 MHz, differential
Output Balance Error
BAL
—
85
—
dB
C
At DC
Note 1:
“Test Level” designation: A = 100% production tested at 25°C; B = not production tested, limits set by characterization
and/or simulation, C = values for information only (based on characterization or design).
2019 Microchip Technology Inc.
DS20006162A-page 3
MCP6D11
AC ELECTRICAL CHARACTERISTICS (CONTINUED)
Electrical Characteristics: Unless otherwise indicated, TA = 25°C, VDD = +2.5V to 5.5V, VSS = 0V, PD\ = VDD, VOCM = open,
VICM = VDD/2, Single-ended input, G = 1V/V, RF = RG = 1 k, RL = 1 k between differential outputs.
Parameters
Sym.
Min.
eni
—
Units
Test
Level
(Note 1)
—
nV/√Hz
C
Typ. Max.
Conditions
Noise and Distortion
Input Noise Voltage Density
Input Noise Current Density
2nd Order Harmonic Distortion
3rd Order Harmonic Distortion
Note 1:
5.0
at f > 10 kHz
ini
—
0.6
—
pA/√Hz
C
at f ≥ 100 kHz
HD2
—
-137
—
dBc
C
f = 10 kHz, 2Vpp, VDD = 3V
—
-138
—
f = 10 kHz, 2Vpp, VDD = 5V
—
-118
—
f = 100 kHz, 2Vpp, VDD = 3V
HD3
f = 100 kHz, 2Vpp, VDD = 5V
—
-120
—
—
-137
—
—
-137
—
f = 10 kHz, 2Vpp, VDD = 5V
—
-116
—
f = 100 kHz, 2Vpp, VDD = 3V
—
-116
—
f = 100 kHz, 2Vpp, VDD = 5V
dBc
C
f = 10 kHz, 2Vpp, VDD = 3V
“Test Level” designation: A = 100% production tested at 25°C; B = not production tested, limits set by characterization
and/or simulation, C = values for information only (based on characterization or design).
DC ELECTRICAL CHARACTERISTICS
Electrical Characteristics: Unless otherwise indicated, TA = 25°C, VDD = +2.5V to 5.5V, VSS = 0V, PD\ = VDD, VOCM = open,
VICM = VDD/2, Single-ended input, G = 1V/V, RF = RG = 1 kRL = 1 kbetween differential outputs.
Parameters
Sym.
Min.
Typ.
Max.
Units
Test
Level
(Note 1)
Conditions
Input Offset
VOS
-150
±25
+150
µV
A
Input Offset Voltage Drift
VOS/TA
-2.0
±0.5
+2.0
µV/°C
B
Power Supply Rejection
PSRR
100
117
—
dB
A
IB+, IB-
-1.7
-0.7
—
µA
A
(Note 3)
-1.9
-0.8
-0.4
µA
B
TA = +85°C
Input Offset Voltage
TA = -40°C to +125°C
(Note 4)
Input Bias Current and Impedance
Input Bias Current
Input Bias Current,
across Temperature
Input Bias Current Drift
Input Offset Current
Input Offset Current Drift
Differential Input Impedance
Note 1:
2:
3:
4:
IB/TA
-2.1
-1.1
-0.5
µA
B
TA = +125°C
-3.6
±2.75
+3.6
nA/°C
B
TA = -40°C to +125°C
(QFN) (Note 4)
IOS
-60
±10
+60
nA
A
IOS/TA
-130
±40
+130
pA/°C
B
ZDIFF
—
88||1.0
—
k||pF
C
TA = -40°C to +125°C
(QFN) (Note 4)
“Test Level” designation: A = 100% production tested at 25°C; B = not production tested, limits set by characterization
and/or simulation, C = values for information only (based on characterization or design).
The VICM spec is supported by the CMRR tests.
Negative polarity sign indicates current flowing out of node.
Based on data taken at the temperature range end-points (-40°C, +125°C) and calculated deltas are divided by the temperature range. The Max./Min. specifications are set using +/-4 standard deviations on the device distribution.
DS20006162A-page 4
2019 Microchip Technology Inc.
MCP6D11
DC ELECTRICAL CHARACTERISTICS (CONTINUED)
Electrical Characteristics: Unless otherwise indicated, TA = 25°C, VDD = +2.5V to 5.5V, VSS = 0V, PD\ = VDD, VOCM = open,
VICM = VDD/2, Single-ended input, G = 1V/V, RF = RG = 1 kRL = 1 kbetween differential outputs.
Sym.
Min.
Typ.
Max.
Units
Test
Level
(Note 1)
Common-Mode Input Range, high
VICM_H
VDD - 1.0
VDD - 0.9
—
V
A
VDD - 1.0
—
B
TA = -40°C to + 125°C
Common-Mode Input Range, low
VICM_L
—
VSS - 0.25 VSS - 0.15
V
A
(Note 2)
—
VSS - 0.1
VSS
B
TA = -40°C to + 125°C
Common-Mode Rejection Ratio
CMRR
95
112
—
dB
A
VDD = 5.5V
95
110
—
B
VDD = 5.5V
TA = -40°C to + 125°C
90
107
—
A
VDD = 2.5V
90
105
—
B
VDD = 2.5V
TA = -40°C to + 125°C
106
124
—
A
VDD = 5.5V
VOUT = 0.4V to
VDD – 0.4V
102
118
—
B
VDD = 5.5V,
TA = -40°C to +125°C
106
121
—
A
VDD = 2.5V,
VOUT = 0.25V to
VDD – 0.25V
102
114
—
B
VDD = 2.5V,
TA = -40°C to +125°C
Internal Feedback Trace Resistance
—
3
—
C
QFN package only;
pins 10-4, 11-1
Internal Feedback Trace Resistance
Mismatch
—
0.05
—
C
QFN package only;
pins 10-4, 11-1
—
VSS + 75
VSS + 100
mV
A
VDD = 5.5V,
0.5V overdrive
—
VSS + 33
VSS + 50
VDD = 2.5V,
0.5V overdrive
VDD - 150
VDD - 100
—
VDD = 5.5V,
0.5V overdrive
VDD - 75
VDD - 50
—
VDD = 2.5V,
0.5V overdrive
—
±66
—
—
±75
—
Parameters
Conditions
Common-Mode
VDD - 1.2
(Note 2)
Open Loop Gain
DC Open Loop Gain
AOL
dB
Output
Maximum Output Voltage Swing
VOL
VOH
Output Short Circuit Current
Note 1:
2:
3:
4:
ISC
mA
C
VDD = 2.5V
VDD = 5.5V
“Test Level” designation: A = 100% production tested at 25°C; B = not production tested, limits set by characterization
and/or simulation, C = values for information only (based on characterization or design).
The VICM spec is supported by the CMRR tests.
Negative polarity sign indicates current flowing out of node.
Based on data taken at the temperature range end-points (-40°C, +125°C) and calculated deltas are divided by the temperature range. The Max./Min. specifications are set using +/-4 standard deviations on the device distribution.
2019 Microchip Technology Inc.
DS20006162A-page 5
MCP6D11
DC ELECTRICAL CHARACTERISTICS (CONTINUED)
Electrical Characteristics: Unless otherwise indicated, TA = 25°C, VDD = +2.5V to 5.5V, VSS = 0V, PD\ = VDD, VOCM = open,
VICM = VDD/2, Single-ended input, G = 1V/V, RF = RG = 1 kRL = 1 kbetween differential outputs.
Parameters
Min.
Typ.
Max.
Units
Test
Level
(Note 1)
VCM
1.0
0.9 to
VDD - 1.0
VDD - 1.1
V
A
GOCM
0.99
1
1.01
V/V
B
VOS
-5
±0.8
+5
mV
A
VOCM pin driven to
(VDD/2)
-10
±2
+10
VOS/TA
-45
±15
+30
µV/°C
B
TA = -40°C to +125°C,
VDD = 2.5V (QFN)
(Note 4)
-25
±6.9
+25
B
TA = -40°C to +125°C,
VDD = 5.5V (QFN)
(Note 4)
Sym.
Conditions
Output Common-Mode Voltage Control (VOCM)
Input Voltage Range
Gain
Input Offset Voltage
Input Offset Voltage Drift
Input Bias Current
Input Impedance
Bandwidth (Small-Signal, -3 dB)
Slew Rate
VOCM pin floating
IB
—
±0.01
+1.5
µA
B
ZCM
—
46k||2
—
||pF
B
For internal VDD/2
reference
BWss
—
45
—
MHz
C
VOCM = 100mVpp
SR
—
14
—
V/µs
C
1V step
VDD
2.5
—
5.5
V
A
VSS = 0V
IQ
1.0
1.49
1.8
mA
A
VDD = 5.5V, IO = 0
0.9
—
2.1
B
VDD = 5.5V,
TA = -40°C to +125°C
Power Supply
Supply Voltage
Quiescent Current
Quiescent Current Drift
Power-Up Time
1.0
1.4
1.8
A
VDD = 2.5V, IO = 0
0.8
—
2.0
B
VDD = 2.5V,
TA = -40°C to +125°C
IQ/TA
—
3.8
—
µA/°C
C
TA = -40°C to +125°C
(Note 4)
tup
—
30
—
µs
C
Power-Down (PD\)
IQ_PD
—
5
7
µA
A
Input Voltage, Logic High
VIH
0.8 VDD
—
VDD
V
A
Input Voltage, Logic Low
VIL
VSS
—
0.2 VDD
V
A
Input Current, Logic High
IIH
—
+5
—
nA
B
Input Current, Logic Low
IIL
—
-5
—
nA
B
PD\ = VSS
Turn-on Time
ton
—
1.0
1.5
µs
B
VDD = 5.5V, Vout = 90%
of final value
—
2.5
3
—
0.04
0.05
—
0.05
0.06
Quiescent Current
Turn-off Time
Note 1:
2:
3:
4:
toff
PD\ = VSS
PD\ = VDD
VDD = 2.5V, Vout = 90%
of final value
µs
B
VDD = 5.5V, Vout = 10%
of final value
VDD = 2.5V, Vout = 10%
of final value
“Test Level” designation: A = 100% production tested at 25°C; B = not production tested, limits set by characterization
and/or simulation, C = values for information only (based on characterization or design).
The VICM spec is supported by the CMRR tests.
Negative polarity sign indicates current flowing out of node.
Based on data taken at the temperature range end-points (-40°C, +125°C) and calculated deltas are divided by the temperature range. The Max./Min. specifications are set using +/-4 standard deviations on the device distribution.
DS20006162A-page 6
2019 Microchip Technology Inc.
MCP6D11
TEMPERATURE SPECIFICATIONS
Electrical Characteristics: Unless otherwise indicated, all limits are specified for VDD - VSS = 2.5V to 5.5V
Parameters
Sym
Min
Typ
Max
Units
Conditions
Temperature Ranges
Specified Temperature Range
TA
-40
—
+125
°C
Operating Temperature Range
TA
-40
—
+125
°C
Storage Temperature Range
TA
-65
—
+150
°C
Thermal Resistance, 8L-MSOP
JA
—
170
—
°C/W
Thermal Resistance, 16L-QFN
JA
—
60
—
°C/W
(Note 1)
Thermal Package Resistances
Note 1:
The MCP6D11 operates over this temperature range, but the Junction Temperature (TJ) must not exceed the Absolute
Maximum specification of +155°C.
2019 Microchip Technology Inc.
DS20006162A-page 7
MCP6D11
NOTES:
DS20006162A-page 8
2019 Microchip Technology Inc.
MCP6D11
2.0
PIN DESCRIPTIONS
TABLE 2-1:
PIN FUNCTION TABLE
MCP6D11
Symbol
Description
MSOP-8
QFN-16
1
3
IN-
Negative input (Summing Junction)
2
9
VOCM
Output common-mode voltage; a high impedance input
3
5,6,7,8
4
10
VDD
Positive Power Supply
OUT+
Positive output
OUT-
Negative output
5
11
6
13,14,15,16
VSS
Negative Power Supply
7
12
PD\
Power-Down (Low = VSS = Low Power mode;
High = VDD = normal operation)
Positive Input (Summing Junction)
8
2
IN+
--
1
FB-
Negative feedback; same signal as negative output (OUT-)
--
4
FB+
Positive feedback; same signal as positive output (OUT+)
17
EP
‘Exposed Thermal Pad’ on bottom side of QFN package only (Note 1)
-Note 1:
The exposed thermal pad should be soldered to a low-noise ground or power plane. This pad is
electrically isolated from the die (using non-conductive die attach), however the pad must be connected
to a power or ground and can not be left floating.
Package Types
MCP6D11,
MSOP-8
13 VSS
14 VSS
15 VSS
16 VSS
MCP6D11,
QFN-16
IN- 1
8 IN+
VOCM 2
7 PD
FB- 1
6 VSS
IN+ 2
11 OUT-
5 OUT-
IN- 3
10 OUT+
FB+ 4
9 VOCM
12 PD
VDD 8
VDD 7
VDD 5
2019 Microchip Technology Inc.
VDD 6
VDD 3
OUT+ 4
EP(17)
DS20006162A-page 9
MCP6D11
NOTES:
DS20006162A-page 10
2019 Microchip Technology Inc.
MCP6D11
3.0
TYPICAL PERFORMANCE CURVES
Note:
The graphs and tables provided following this note are a statistical summary based on a limited number of
samples and are provided for informational purposes only. The performance characteristics listed herein
are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified
operating range (e.g., outside specified power supply range) and therefore outside the warranted range.
Note: Unless otherwise indicated, TA = 25°C, VDD - VSS = 2.5V to 5.5V, VOCM = open, VICM = mid-supply, PD\ = VDD,
single-ended input, 50 input match, G = 1V/V, RF = RG = 1 kCL = 0 pF and RL = 1 k between the differential
outputs.
3.1
Frequency Response
12
3
VDD = 3.0V
VOUT = 20mVpp
VOUT = 100mVpp
VDD = 5.0V
Normalized Gain (dB)
9
G = 0.1V/V
0
6
Gain (dB)
3
0
-3
-6
-3
-6
G = 1V/V
G = 2V/V
G = 10V/V
-9
-9
-12
100k
1M
VOUT = 1Vpp
VOUT = 2Vpp
VOUT = 4Vpp
100
-12
100M
100k
1M
Frequency (Hz)
FIGURE 3-1:
Small-Signal Frequency
Response vs. Gain, VOUTDM = 20mVpp.
100M
FIGURE 3-4:
Small-Signal Frequency
Response vs. VOUTDM (Gain = 1V/V).
9
3
VDD = 5.0V
VDD = 3.0V
2
6
1
G = 0.1V/V
0
3
VOCM = 0.90V
VOCM = 1.25V
VOCM = 1.50V
VOCM = 1.75V
VOCM = 2.00V
-1
Gain (dB)
Normalized Gain (dB)
100
Frequency (Hz)
0
-3
-6
100
1M
1M
-4
-5
-7
-8
-12
100k
-3
-6
G = 1V/V
G = 2V/V
G = 10V/V
-9
-2
-9
100M
100k
1M
Frequency (Hz)
100
100M
Frequency (Hz)
FIGURE 3-2:
Small-Signal Frequency
Response vs. Gain, VOUTDM = 20mVpp.
FIGURE 3-5:
Small-Signal Frequency
Response vs VOCM, Gain = 1V/V.
3
3
VOUT = 100mVpp
VOUT = 20mVpp
VDD = 3.0V
2
VDD = 5.0V
1
0
Gain (dB)
Gain (dB)
0
-1
-3
-6
-9
VOUT = 1Vpp
VOUT = 2Vpp
VOUT = 4Vpp
-2
-3
-4
VOCM = 0.90V
VOCM = 1.50V
VOCM = 2.50V
VOCM = 3.50V
VOCM = 4.00V
-5
-6
-7
-8
-12
100k
-9
1M
10M
100M
100k
FIGURE 3-3:
Small-Signal Frequency
Response vs. VOUTDM (Gain = 1V/V).
2019 Microchip Technology Inc.
1M
100
100M
Frequency (Hz)
Frequency (Hz)
FIGURE 3-6:
Small-Signal Frequency
Response vs VOCM, Gain = 1V/V.
DS20006162A-page 11
MCP6D11
Note: Unless otherwise indicated, TA = 25°C, VDD - VSS = 2.5V to 5.5V, VOCM = open, VICM = mid-supply, PD\ = VDD,
single-ended input, 50 input match, G = 1V/V, RF = RG = 1 kCL = 0 pF and RL = 1 k between the differential
outputs.
9
6
VDD = 5.0V
6
3
3
0
Gain (dB)
Gain (dB)
VDD = 3.0V
0
RL = 50:
RL = 100:
RL = 200:
RL = 500:
RL = 1 k:
-3
-6
-3
CL = 2 pF, RISO = 0:
CL = 10 pF, RISO = 191:
CL = 47 pF, RISO = 75:
CL = 100 pF, RISO = 62:
CL = 330 pF, RISO = 33:
-6
-9
-12
-9
100k
1M
100
100k
100M
1M
1M
100M
Frequency (Hz)
Frequency (Hz)
FIGURE 3-7:
Small-Signal Frequency
Response vs. R-Loads, Gain = 1V/V.
FIGURE 3-10:
Small-Signal Frequency
Response vs. C-Loads.
9
3
VDD = 5.0V
2
6
1
3
-1
VDD = 3.0V
Gain (dB)
Gain (dB)
0
0
RL = 50:
RL = 100:
RL = 200:
RL = 500:
RL = 1 k:
-3
-6
-2
-3
-4
RL = 50:
RL = 100:
RL = 200:
RL = 500:
RL = 1 k:
-5
-6
-7
-8
-9
-9
100k
1M
100
100k
100M
1M
1M
100M
Frequency (Hz)
Frequency (Hz)
FIGURE 3-8:
Small-Signal Frequency
Response vs R-Loads, Gain = 1V/V.
FIGURE 3-11:
Large-Signal Frequency
Response vs. R-Loads, VOUTDM = 2Vpp.
3
6
VDD = 3.0V
2
3
1
0
-1
VDD = 5.0V
Gain (dB)
Gain (dB)
0
-3
-6
CL = 2 pF, RISO = 0:
CL = 10 pF, RISO = 191:
CL = 47 pF, RISO = 93:
CL = 100 pF, RISO = 62:
CL = 330 pF, RISO = 36:
-9
-2
-3
-4
RL = 50:
RL = 100:
RL = 200:
RL = 500:
RL = 1 k:
-5
-6
-7
-8
-9
-12
100k
1M
1M
100M
Frequency (Hz)
FIGURE 3-9:
Small-Signal Frequency
Response vs C-Loads.
DS20006162A-page 12
100k
1M
100
100M
Frequency (Hz)
FIGURE 3-12:
Large-Signal Frequency
Response vs. R-Loads, VOUTDM = 2Vpp.
2019 Microchip Technology Inc.
MCP6D11
6
Open-loop Gain (dB)
3
Gain (dB)
0
-3
-6
-9
100mVpp, 2.5V
100mVpp, 5.5V
1Vpp, 2.5V
1Vpp, 5.5V
-12
-15
0
140
-30
120
-60
100
-90
80
-120
60
-150
Gain 5.5V
40
1M
10M
-270
1
100M
100
10N
100M
10
)UHquency(H])
FIGURE 3-16:
Differential Open-Loop Gain
and Phase vs. Frequency (Simulation).
90
110
85
Output Balance (dB)
120
100
CMRR (dB)
-240
Phase 2.5V
-20
FIGURE 3-13:
VOCM Small- and Large-Signal
Frequency Response, Gain = 1V/V.
90
80
70
60
CMRR 2.5V
CMRR 5.5V
80
75
70
65
60
55
VDD = 5.V
VDD = V
50
45
40
40
10k
100k
1M
10M
10k
100M
100k
FIGURE 3-14:
(Simulation).
1M
10M
Frequency (Hz)
Frequency (Hz)
FIGURE 3-17:
Output Balance vs. Frequency,
VOUTDM = 100mVpp, Gain = 1V/V (Simulation).
CMRR vs. Frequency
10000
140
100
80
60
40
10k
100k
1M
10M
100M
Frequency (Hz)
FIGURE 3-15:
(Simulation).
+PSRR, -PSRR vs. Frequency,
2019 Microchip Technology Inc.
VDD = 2.5V
Output Impedance (Ohm)
PSRR+ 2.5V
PSRR+ 5.5V
PSRR- 2.5V
PSRR- 5.5V
120
PSRR (dB)
-210
Phase 5.5V
Frequency (Hz)
50
-180
Gain 2.5V
20
0
-18
100k
160
Open-loop Phase (deg)
Note: Unless otherwise indicated, TA = 25°C, VDD - VSS = 2.5V to 5.5V, VOCM = open, VICM = mid-supply, PD\ = VDD,
single-ended input, 50 input match, G = 1V/V, RF = RG = 1 kCL = 0 pF and RL = 1 k between the differential
outputs.
1000
100
10
1
G = 1V/V
G = 2V/V
G = 5V/V
0.1
0.01
0.001
0.0001
100
1k
10k
10k
1M
10M
100M
Frequency (Hz)
FIGURE 3-18:
Closed-Loop, Differential
Output Impedance vs. Frequency (Simulation).
DS20006162A-page 13
MCP6D11
Note: Unless otherwise indicated, TA = 25°C, VDD - VSS = 2.5V to 5.5V, VOCM = open, VICM = mid-supply, PD\ = VDD,
single-ended input, 50 input match, G = 1V/V, RF = RG = 1 kCL = 0 pF and RL = 1 k between the differential
outputs.
10000
Output Impedance (Ohm)
VDD = 5.5V
1000
100
10
1
G = 1V/V
G = 2V/V
G = 5V/V
0.1
0.01
0.001
0.0001
100
1k
10k
100k
1M
10M
100M
Frequency (Hz)
FIGURE 3-19:
Closed-Loop, Differential
Output Impedance vs. Frequency (Simulation).
DS20006162A-page 14
2019 Microchip Technology Inc.
MCP6D11
Note: Unless otherwise indicated, TA = 25°C, VDD - VSS = 2.5V to 5.5V, VOCM = open, VICM = mid-supply, PD\ = VDD,
single-ended input, 50 input match, G = 1V/V, RF = RG = 1 kCL = 0 pF and RL = 1 k between the differential
outputs.
3.2
Input Noise and Distortion
-80
100
Single-ended Input
MSOP package
-90
Distortion (dBc)
Voltage Noise (nV/√Hz),
Current Noise (pA/√Hz)
VDD = 5.5V
VDD = 2.5V
10
V-Noise
1
I-Noise
-100
-110
-120
HD2, 3V
HD2, 5V
-130
-140
0.1
10
HD3, 3V
HD3, 5V
-150
100
1k
10k
100k
1M
1k
10k
Frequency (Hz)
FIGURE 3-23:
VOUTDM = 2Vpp.
FIGURE 3-20:
Input Noise Voltage and
Current Density vs. Frequency.
10000
HD2 and HD3 vs. Frequency,
-60
Single-ended input
QFN-16 package
-70
VDD = 3.0V
-80
Distortion (dBc)
VOCM Voltage Noise (nV/Hz)
100k
Frequency (Hz)
VOCM Pin floating
VOCM Pin driven
1000
100
VDD = 5.5V
VDD = 2.5V
HD3, 100 kHz
HD2, 100 kHz
-90
-100
-110
-120
-130
HD3, 10 kHz
HD2, 10 kHz
-140
-150
10
10
100
1N
10N
100k
0
1M
1
2
3
4
5
6
7
8
9
10
Gain (V/V)
)requency (Hz)
FIGURE 3-21:
VOCM Noise Voltage Density
vs. Frequency,; a) Pin Floating, b) Pin Driven.
FIGURE 3-24:
VOUTDM = 2Vpp.
HD2, HD3 vs Gain,
-60
-80
Single-ended input
QFN-16 package
-90
Single-ended input
QFN-16 package
-70
VDD = 5.0V
-110
-120
HD3, 5V
HD3, 3V
-130
HD2, 3V
HD2, 5V
Distortion (dBc)
Distortion (dBc)
-80
-100
HD3, 100 kHz
HD2, 100 kHz
-90
-100
-110
-120
-130
-140
HD3, 10 kHz
HD2, 10 kHz
-140
-150
1k
10k
100k
)UHquency (Hz)
FIGURE 3-22:
VOUTDM = 2Vpp.
HD2, HD3 vs Frequency,
2019 Microchip Technology Inc.
-150
0
1
2
3
4
5
6
7
8
9
10
Gain (V/V)
FIGURE 3-25:
VOUTDM = 2Vpp.
HD2, HD3 vs Gain,
DS20006162A-page 15
MCP6D11
Note: Unless otherwise indicated, TA = 25°C, VDD - VSS = 2.5V to 5.5V, VOCM = open, VICM = mid-supply, PD\ = VDD,
single-ended input, 50 input match, G = 1V/V, RF = RG = 1 kCL = 0 pF and RL = 1 k between the differential
outputs.
-60
-80
VDD = 3.0V
Single-ended input
QFN-16 package
-90
Single-ended input
QFN-16 package
-70
VDD = 5.0V
Distortion (dBc)
Distortion (dBc)
-80
-100
HD3, 100 kHz
HD2, 100 kHz
-110
-120
HD3, 10 kHz
HD2, 10 kHz
-130
-90
HD2, 100 kHz
HD3, 100 kHz
-100
-110
-120
HD2, 10 kHz
HD3, 10 kHz
-130
-140
-140
-150
200
400
600
800
-150
1000
0
Differential Load Resistance (:)
FIGURE 3-26:
VOUTDM = 2Vpp.
HD2, HD3 vs RL,
4
FIGURE 3-29:
G = 1V/V.
6
8
HD2, HD3 vs VOUTDM,
-60
-80
VDD = 5.0V
Single-ended input
QFN-16 package
-90
Single-ended input
QFN-16 package
-70
VDD = 3.0V
-80
-100
Distortion (dBc)
Distortion (dBc)
2
Differential Output Voltage (Vpp)
HD3, 100 kHz
HD2, 100 kHz
-110
-120
HD3, 10 kHz
HD2, 10 kHz
-130
-140
-90
-100
HD3, 100kHz
HD2, 100kHz
-110
-120
-130
-140
HD2, 10kHz
HD3, 10kHz
-150
-150
200
400
600
800
1000
-160
Differential Load Resistance (:
:)
0.5
0.7
0.9
1.1
1.3
1.5
1.7
1.9
2.1
External VOCM Voltage (V)
FIGURE 3-27:
VOUTDM = 2Vpp.
FIGURE 3-30:
HD2, HD3 vs VOCM,
VOUTDM = 2Vpp, Gain = 1V/V.
HD2, HD3 vs RL,
-60
-60
Single-ended input
QFN-16 package
-70
VDD = 3.0V
VDD = 5.0V
-80
Distortion (dBc)
-80
Distortion (dBc)
Single-ended input
QFN-16 package
-70
-90
HD3, 100 kHz
HD2, 100 kHz
-100
-110
-120
-90
-100
-110
HD3, 100 kHz
HD2, 100 kHz
-120
-130
-140
-130
HD3, 10 kHz
HD2, 10 kHz
-140
HD2, 10 kHz
HD3, 10 kHz
-150
-160
-150
0
1
2
3
4
5
Differential Output Voltage (Vpp)
FIGURE 3-28:
G = 1V/V.
DS20006162A-page 16
HD2, HD3 vs VOUTDM,
6
0.5
1
1.5
2
2.5
3
3.5
4
4.5
External VOCM Voltage (V)
FIGURE 3-31:
HD2, HD3 vs VOCM,
VOUTDM = 2Vpp, Gain = 1V/V.
2019 Microchip Technology Inc.
MCP6D11
Note: Unless otherwise indicated, TA = 25°C, VDD - VSS = 2.5V to 5.5V, VOCM = open, VICM = mid-supply, PD\ = VDD,
single-ended input, 50 input match, G = 1V/V, RF = RG = 1 kCL = 0 pF and RL = 1 k between the differential
outputs.
FIGURE 3-32:
G = 1V/V, VDD = 3V.
10 kHz FFT, VOUTDM = 2Vpp,
FIGURE 3-34:
G = 1V/V, VDD = 3V.
100 kHz FFT, VOUTDM = 2Vpp,
FIGURE 3-33:
G = 1V/V, VDD = 5V.
10 kHz FFT, VOUTDM = 2Vpp,
FIGURE 3-35:
G = 1V/V, VDD = 5V.
100 kHz FFT, VOUTDM = 2Vpp,
2019 Microchip Technology Inc.
DS20006162A-page 17
MCP6D11
Note: Unless otherwise indicated, TA = 25°C, VDD - VSS = 2.5V to 5.5V, VOCM = open, VICM = mid-supply, PD\ = VDD,
single-ended input, 50 input match, G = 1V/V, RF = RG = 1 kCL = 0 pF and RL = 1 k between the differential
outputs.
Time Response
2.5
Differential Output Voltage (V)
0.08
0.06
0.04
0.02
0.00
-0.02
VDD = 5.5V
-0.04
-0.06
VDD = 2.5V
-0.08
Differential Output Voltage (V)
3.3
1.0
0.5
0.0
-0.5
-1.0
-1.5
-2.0
FIGURE 3-39:
G = 1V/V.
Large Signal Step Response,
2.5
VDD = 3.0V
0.10
0.05
CL = 2 pF
CL = 10 pF
CL = 15 pF
-0.05
-0.10
Differential Output Voltage (V)
0.15
-0.15
VDD = 5.0V
2.0
1.5
1.0
0.5
0.0
-0.5
-1.0
-1.5
-2.0
VOUT = 1Vpp
VOUT = 2Vpp
VOUT = 4Vpp
-2.5
Time (50 ns/Div.)
Time (100 ns/Div.)
FIGURE 3-37:
Small Signal Step Response
vs. C-Load, VOUTDM = 200mVpp, G = 1V/V.
FIGURE 3-40:
G = 1V/V.
0.15
Large Signal Step Response,
6
VDD = 5.0V
VDD = 3.0V
0.10
4
Differential,QSXW [
Differential Output
0.05
0.00
-0.05
CL = 2 pF
CL = 10 pF
CL = 15 pF
-0.10
2
0
-2
-4
-0.15
Time (100 ns/Div.)
FIGURE 3-38:
Small Signal Step Response
vs. C-Load, VOUTDM = 200mVpp, G = 1V/V.
DS20006162A-page 18
Amplitude (V)
Differential Output Voltage (V)
VOUT = 1Vpp
VOUT = 2Vpp
VOUT = 4Vpp
Time (50 ns/Div.)
FIGURE 3-36:
Small Signal Step Response,
VOUTDM = 100mVpp, G = 1V/V.
Differential Output Voltage (V)
1.5
-2.5
Time (20 ns/Div)
0.00
VDD = 3.0V
2.0
-6
Time (1 μs/Div)
FIGURE 3-41:
Time, G = 2V/V.
Output Overdrive Recovery vs.
2019 Microchip Technology Inc.
MCP6D11
Note: Unless otherwise indicated, TA = 25°C, VDD - VSS = 2.5V to 5.5V, VOCM = open, VICM = mid-supply, PD\ = VDD,
single-ended input, 50 input match, G = 1V/V, RF = RG = 1 kCL = 0 pF and RL = 1 k between the differential
outputs.
0.20
8
VDD = 5.0V
Differential Input [
Differential Output
0.10
2
Error (%)
Amplitude (V)
4
VDD = 5.5V
G = 1V/V
0.15
6
0
-2
0.05
0.00
-0.05
VStep = 0.1Vpp
VStep = 1.0Vpp
VStep = 2.0Vpp
-0.10
-4
-0.15
-6
-0.20
-8
0
30
FIGURE 3-42:
Time, G = 2V/V.
60
90
120
150
180
210
240
270
300
'Time (ns), from 50% of Input Edge
Time (1μs/Div)
Output Overdrive Recovery vs.
FIGURE 3-45:
(Simulation).
Settling Time vs VOUTDM
3.0
0.50
Amplitde (V)
Output Common-mode Voltage
0.75
0.25
0.00
VDD = 3.0V
VDD = 5.0V
-0.25
2.0
VPD\ at 5VDD
1.0
VPD\ at 3VDD
0.0
-1.0
-2.0
-0.50
VOUT at 5VDD
VOUT at 3VDD
-3.0
-0.75
Time (0.5 μs/Div)
Time (100 ns/Div)
FIGURE 3-43:
VOCM Small- (0.2V Step) and
Large (1V step) Signal Step Response.
FIGURE 3-46:
PD\ Turn-On Transient
Response, Input Signal: 1 MHz Sine, 2Vpp.
0.20
VDD = 2.5V
G = 1V/V
0.15
3.0
2.0
0.05
Amplitde (V)
Error (%)
0.10
0.00
-0.05
VStep = 0.1Vpp
VStep = 1.0Vpp
VStep = 2.0Vpp
-0.10
1.0
-1.0
-2.0
-0.15
-0.20
VOUT at 5VDD
0.0
VOUT at 3VDD
VPD\ at 3VDD
VPD\ at 5VDD
-3.0
0
30
60
90
120
150
180
210
240
270
'Time (ns), from 50% of Input Edge
FIGURE 3-44:
(Simulation).
Settling Time vs. VOUTDM
2019 Microchip Technology Inc.
300
Time (0.5 μs/Div)
FIGURE 3-47:
PD\ Turn-Off Transient
Response, Input Signal: 1 MHz Sine, 2Vpp.
DS20006162A-page 19
MCP6D11
Note: Unless otherwise indicated, TA = 25°C, VDD - VSS = 2.5V to 5.5V, VOCM = open, VICM = mid-supply, PD\ = VDD,
single-ended input, 50 input match, G = 1V/V, RF = RG = 1 kCL = 0 pF and RL = 1 k between the differential
outputs.
3.4
DC Precision
FIGURE 3-48:
Input Offset Voltage Histogram
(Factory Trimmed), VDD = 2.5V.
FIGURE 3-51:
Input Offset Voltage Drift
Histogram, VDD = 5.5V.
150
Offset Voltage (μV)
100
50
0
-50
-100
-150
-40
-20
0
20
40
60
80
100
120
Temperature (qC)
FIGURE 3-49:
Input Offset Voltage Histogram
(Factory Trimmed), VDD = 5.5V.
FIGURE 3-52:
Input Offset Voltage vs
Temperature (45 Units), VDD = 2.5V and 5.5V.
150
Offset Voltage (μV)
VDD = 2.5V
+125 qC
+85 qC
+25 qC
-40 qC
100
50
0
-50
Specified Min./Max.Range
over Temperature
-100
Representative Part
-150
-0.4
-0.2
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
2
Input Common-mode Voltage (V)
FIGURE 3-50:
Input Offset Voltage Drift
histogram; VDD = 2.5V.
DS20006162A-page 20
FIGURE 3-53:
Input Offset Voltage vs. Input
Common-Mode Voltage.
2019 Microchip Technology Inc.
MCP6D11
Note: Unless otherwise indicated, TA = 25°C, VDD - VSS = 2.5V to 5.5V, VOCM = open, VICM = mid-supply, PD\ = VDD,
single-ended input, 50 input match, G = 1V/V, RF = RG = 1 kCL = 0 pF and RL = 1 k between the differential
outputs.
150
Offset Voltage (μV)
VDD = 5.5V
+125qC
+85qC
+25qC
-40qC
100
50
0
-50
Specified Min./Max.Range
over Temperature
-100
Representative Part
-150
-0.4
0
0.4
0.8
1.2
1.6
2
2.4
2.8
3.2
3.6
4
4.4
4.8
Input Common-mode Voltage (V)
FIGURE 3-54:
Input Offset Voltage vs. Input
Common-Mode Voltage.
FIGURE 3-57:
VDD = 2.5V.
Input Offset Current Histogram,
FIGURE 3-58:
VDD = 5.5V.
Input Offset Current Histogram,
3.0
VDD = 5.5V
Input Bias Current (μA)
2.5
2.0
1.5
1.0
0.5
0.0
+125 qC
+25 qC
- 40 qC
-0.5
-1.0
-1.5
-2.0
-0.5
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
Input Common-mode Voltage (V)
FIGURE 3-55:
Input Bias Current vs. Input
Common-Mode Voltage.
10.0
250
6.0
Population (Units)
4.0
2.0
0.0
-2.0
+125 qC
+25 qC
- 40 qC
-4.0
-6.0
-8.0
608 Samples
QFN-16 package
VDD = 5.5V
200
VDD = 2.5V
150
100
50
4.5
5
2019 Microchip Technology Inc.
0.3
0.1
-0.1
Input Offset Current Drift (nA/qqC)
Input Common-mode Voltage (V)
FIGURE 3-56:
Input Offset Current vs. Input
Common-mode Voltage.
0.26
4
0.22
3.5
0.18
3
0.14
2.5
0.06
2
0.02
1.5
-0.02
1
-0.06
0.5
-0.14
0
-0.18
-0.5
-0.22
-0.3
0
-10.0
-0.26
Input Offset Current (nA)
300
VDD = 5.5V
8.0
FIGURE 3-59:
Histogram.
Input Offset Current Drift
DS20006162A-page 21
MCP6D11
Note: Unless otherwise indicated, TA = 25°C, VDD - VSS = 2.5V to 5.5V, VOCM = open, VICM = mid-supply, PD\ = VDD,
single-ended input, 50 input match, G = 1V/V, RF = RG = 1 kCL = 0 pF and RL = 1 k between the differential
outputs.
600
400
350
Population (Units)
Population (Units)
500
400
300
200
100
0
-10
300
250
200
150
100
50
0
-5
0
5
10
-4
-3
-2
-1
0
1
2
3
Common Mode Offset Voltage (mV)
Common Mode Offset Voltage (mV)
FIGURE 3-60:
VOCM Offset Voltage
Histogram, VOCM Pin Floating, VDD = 2.5V.
FIGURE 3-62:
VOCM Offset Voltage
Histogram, VOCM Pin Driven to Mid-Supply,
VDD = 2.5V.
600
400
350
Population (Units)
Population (Units)
500
400
300
200
100
0
-10
4
300
250
200
150
100
50
0
-5
0
5
10
-4
-3
-2
-1
0
1
2
3
Common Mode Offset Voltage (mV)
Common Mode Offset Voltage (mV)
FIGURE 3-61:
VOCM Offset Voltage
Histogram, VOCM Pin Floating, VDD = 5.5V.
FIGURE 3-63:
VOCM Offset Voltage
Histogram, VOCM Pin Driven to Mid-Supply,
VDD = 5.5V.
DS20006162A-page 22
4
2019 Microchip Technology Inc.
MCP6D11
Note: Unless otherwise indicated, TA = 25°C, VDD - VSS = 2.5V to 5.5V, VOCM = open, VICM = mid-supply, PD\ = VDD,
single-ended input, 50 input match, G = 1V/V, RF = RG = 1 kCL = 0 pF and RL = 1 k between the differential
outputs.
Other DC Voltages and Currents
2.0
2.0
1.8
1.8
1.6
Qiescent Current (mA)
Qiescent Current (mA)
3.5
+125 qC
+25 qC
-40 qC
1.4
1.2
1.0
0.8
0.6
0.4
1.6
1.4
VDD = 5.5V
1.2
1.0
0.8
0.6
VDD = 2.5V
0.4
0.2
0.2
0.0
0.0
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
0
5.5
0.5
1
Supply Voltage (V)
FIGURE 3-66:
Supply Current vs. Power
Quiescent current (mA)
2.0
1.8
1.6
VDD = 5.5V
1.4
VDD = 2.5V
1.2
1.0
0.8
-40
-20
0
20
40
60
80
Supply Current vs.
2019 Microchip Technology Inc.
2.5
3
3.5
4
4.5
5
5.5
100
120
Supply Current vs. PD\ Voltage.
400
350
300
250
VOH
200
VDD = 5.5V
150
VOL
100
VDD = 2.5V
50
0
0
5
Temperature (qC)
FIGURE 3-65:
Temperature.
2
Voltage at PD\ Pin (V)
Output Voltage Headroom (mV)
FIGURE 3-64:
Supply Voltage.
1.5
10
15
20
25
30
Output Current (+/-mA)
FIGURE 3-67:
Output Current.
Output Voltage Headroom vs.
DS20006162A-page 23
MCP6D11
NOTES:
DS20006162A-page 24
2019 Microchip Technology Inc.
MCP6D11
4.0
FUNCTIONAL DESCRIPTION
4.1
Overview
Differential Input/Output amplifiers, also called Fully
Differential Amplifiers (FDA), have become common
driver amplifier for Precision ADCs (SAR, Delta-Sigma)
as well as High-Speed ADCs. Compared to more
discrete driver circuits built from standard op amps,
integrated Differential I/O amplifiers have a number of
advantages:
• They allow the signal path to be DC coupled. Other,
passive solutions may rely on RF-transformers that
are noiseless, but effectively have a band-pass
frequency response. Simple AC-coupling creates a
high-pass response.
• They provide superior common-mode rejection
performance.
• The input and output common-mode operating
points are largely independent of the signal gain
setting.
• They suppress even-order harmonic distortion.
• They allow the output common-mode voltage to
be set independently of the input common-mode
voltage, which provides for design flexibility when
interfacing to ADCs requiring a certain Vcm for
best dynamic performance.
• They increase the dynamic range by a factor of 2
(6 dB) due to their differential, complementary
output signals.
• They allow the gain to be set in a wide range,
including attenuation (G < 1V/V).
An integrated, differential I/O amplifier is very similar in
architecture to a standard, voltage-feedback
operational amplifier, with a few differences. Both types
of amplifiers have differential inputs. Differential I/O
amplifiers have balanced differential outputs, while a
standard operational amplifier's output is single-ended.
In a differential I/O amplifier the output common-mode
voltage can be controlled independently of the
differential output voltage through an additional input,
the VOCM pin. The purpose of the VOCM input is to set
the output common-mode voltage for the two
differential output pins. In a standard operational
amplifier with single-ended output, the output
common-mode voltage and the signal are the same.
VDD
* 3Ω
MCP6D11
* FB+
0.7 pF
OUT+
93 kΩ
26 kΩ
IN-
-
pF
CIN_DM
Diff I/O
Amp.
Commonmode
Feedback
Loop
+
-
+
IN+
VOCM
93 kΩ
26 kΩ
OUT-
* 3Ω
0.7 pF
* FB-
PD
VSS
FIGURE 4-1:
MCP6D11 Block Diagram; (*) Internal Metal-Trace Impedances (3) and Pins FB+/Apply to QFN-16 Package Only.
2019 Microchip Technology Inc.
DS20006162A-page 25
MCP6D11
The differential feedback, set with external resistors,
controls only the differential output voltage. The
common-mode
feedback
controls
only
the
common-mode output voltage. This architecture
makes it easy to arbitrarily set the output
common-mode level in level shifting applications. It is
forced, by internal common-mode feedback, to be
equal to the voltage applied to the VOCM input pin,
without affecting the differential output voltage. The
result is nearly perfectly balanced differential outputs of
identical amplitude and exactly 180° apart in phase
over a wide frequency range. The circuit can be used
with either a differential or a single-ended input, and the
voltage gain is equal to the ratio of RF to RG.
As a general rule, differential I/O amplifier circuits will
benefit from matched feedback networks (RF/RG) to
eliminate any common-mode input signal to differential
output conversion. However, even if the external
feedback networks are mismatched, the internal
common-mode feedback loop will still force the outputs
to remain balanced. The amplitudes of the signals at
each output will remain equal and 180° out of phase.
The input-to-output differential-mode gain will vary
proportionately to the feedback mismatch, but the
output balance will be unaffected. Ratio matching
errors in the external resistors will result in a
degradation of the circuit's ability to reject input
common-mode signals, similar to a four-resistor
difference amplifier made from a conventional op amp.
The output common-mode voltage is generated at the
mid point of the internal resistor string that is between
VOUT+ and VOUT-. This voltage is fed into the
common-mode feedback loop amplifier and compared
to the reference voltage, VOCM.
The VOCM input pin connects to an internal resistor
divider (2 x 93 k). If the VOCM pin is left open, a
voltage approximately halfway between VDD and VSS
will develop due to this internal resistor network. An
externally applied voltage at the VOCM pin can be used
to overdrive the internal bias voltage if better accuracy
or flexibility is desired.
For a standard operational amplifier, there is typically
one feedback path from the output to the negative
input. The fully differential amplifier operates with two
feedback paths as established with the feedback
resistors RF, each from one of the outputs to its
respective input.
The input stage of the MCP6D11 uses bipolar devices
for superior noise performance compared to CMOS
devices with the trade-off that the input bias current is
higher, typically less than 1 µA. The MCP6D11 has a
differential input capacitance of about 1 pF (CIN_DM),
which interacts with the feedback resistor, typically
1 k. To optimize the frequency response two internal
0.7 pF feedback capacitors were added to the design
as a default compensation.
The MCP6D11 uses a proportional to absolute
temperature (PTAT) biasing circuit, which is designed
such that the device's quiescent current (IQ) increases
with an increase in temperature (see Figure 3-65).
4.2
Terminology and Definitions
The basic representation of a differential I/O amplifier
with its two feedback networks, output load and with its
associated voltage nodes is shown in Figure 4-2. The
differential signal source is represented showing the
signal as VIN- and VIN+, which combine to form the
differential input signal VIN_DM. An associated
common-mode signal is given as VICM. Being an ideal
source, the source impedance is zero and therefore not
shown.
VOCM
RG1
RF1
RL/2
VINVSJ-
VICM
VOUT+
INOUT+
VIN_DM
VOCM
VOCM
(VIN_CM)
VSJ+
IN+
VOUT_DM
VOUT_CM
OUTVOUT-
VIN+
RL/2
RG2
RF2
VOCM
FIGURE 4-2:
DS20006162A-page 26
Differential I/O Amplifier (Basic Representation).
2019 Microchip Technology Inc.
MCP6D11
As described earlier, the voltage on the VOCM pin sets
up the DC output common-mode voltage, and the AC
signal will swing around this VOCM voltage, as
illustrated in Figure 4-2. The internal common-mode
feedback loop forces the VOUT+ and VOUT- outputs to
be balanced, i.e. the signals at the two outputs are
equal in amplitude but 180° out of phase.
4.2.1
DIFFERENTIAL I/O VOLTAGES
The differential input voltage is the voltage applied
between the VIN+ and VIN- inputs and the differential
output voltage is the voltage seen across the OUT+
and OUT- pins. Equations for input and output
differential voltages are listed below:
EQUATION 4-1:
V
IN_DM
4.2.2
SIGNAL GAIN, NOISE GAIN
While more complex, any circuit analysis of differential
I/O amplifiers follows essentially the same rules as
standard op-amp analysis. One of the important
elements of an analysis is to identify the feedback
factor (beta, ); in the case of the differential I/O
amplifier there are two: 1 and 2. Equations 4-5 and
4-6 show the expressions for each of the feedback
factors based on the circuit configuration of Figure 4-2.
EQUATION 4-5:
R G1
1 = ---------------------------R
G1
+R
F1
EQUATION 4-6:
= V
IN+
–V
IN-
RG2
R G2 + R F2
EQUATION 4-2:
RF
V OUT_DM = V OUT+ – V OUT- V IN_DM -------R
G
Aside from describing the source-related input
voltages, it is important to also consider the amplifier's
summing junction input voltages, VSJ- and VSJ+. Note
that these depend on both the input voltage and the
output voltage, as shown in Equations 4-3 and 4-4:
EQUATION 4-3:
R F2
R G2
V SJ+ = V IN+ ----------------------------- + V OUT- ----------------------------R +R
R +R
F2
G2
F2
G2
EQUATION 4-4:
R F1
R G1
V SJ- = V IN- ---------------------------- + V OUT+ ---------------------------R F1 + R G1
R F1 + R G1
2 = ----------------------------
Note that any source impedance present in an actual
circuit will add a resistor term in series to the RG values.
Here, RG represents the total DC impedance seen by
the respective amplifier input (IN+, IN-) back to the
source or a DC reference (e.g. ground).
These feedback divider ratios will become useful for
any output referred noise or error calculation and will
be helpful in simplifying the algebra. Most circuit
designs for differential I/O amplifiers, for example A/D
converter drivers, will require matched feedback
factors, 1 = 2, to maintain optimum AC and DC
performance (see Section 5.1.3 “Mismatches and
DC Errors”).
Other beta related terms that can be useful for error calculations are AVG and , with AVG being defined as
the average feedback factor and defined as the difference in the feedback factors; see Equations 4-7 and
4-8:
EQUATION 4-7:
1 + 2
AVG = -------------------2
EQUATION 4-8:
= 1 – 2
2019 Microchip Technology Inc.
DS20006162A-page 27
MCP6D11
The differential-mode signal gain of the differential I/O
amplifier is given in Equation 4-9, which includes the
finite frequency dependent open-loop gain of the
amplifier A(S) and the average feedback factor.
EQUATION 4-9:
RF
V
1
OUT_DM
Gain(G) = ---------------------------- = -------- ------------------------------------
1
R
V IN_DM
G
1 + --------------------------
A
(S) AVG
Recall that A(S) x is the loop gain of a single-ended
amplifier; for the differential I/O amplifier the loop gain
is based on AVG. Setting the open loop gain to infinite
(A(S) → ∞) simplifies the equation, resulting in the
expression for the ideal closed loop gain of the
differential I/O amplifier. Equation 4-10 is used to select
the feedback network resistors RF and RG and set the
closed loop gain of the amplifier circuit for the
differential input and output signal configuration. In the
case of the single-ended input to differential output
configuration, the equation becomes more complex as
additional terms need to be considered; Section 5.1.2
“Interfacing to a Single-Ended Source”.
EQUATION 4-10:
RF
V OUT_DM
G = ---------------------------- = -------RG
V IN_DM
While the signal gain of a differential I/O amplifier is
determined by G = RF/RG, the noise gain (GN) is given
to:
EQUATION 4-11:
2
G N = -------------------1 + 2
Where:
RF
1
1 = 2 G N = --- = 1 + -------RG
This is important to remember as the noise gain needs
to be considered when calculating total errors, like
offsets or noise, that need to be referred to the output.
Source impedance plays a factor and needs to be
considered for maintaining matching between the two
sides (1 = 2).
DS20006162A-page 28
4.2.3
INPUT AND OUTPUT
COMMON-MODE VOLTAGES
The input common-mode voltage (VIN_CM) for the
differential I/O amplifier is defined as the average
voltage of the two input pins IN+ and IN-.
EQUATION 4-12:
V
IN_CM
V
+V
IN+
IN= -------------------------------2
The input common-mode voltage of the MCP6D11
typically ranges from VCM_L = VSS - 0.25V to
VCM_H = VDD - 0.9V. Because of the external resistive
divider formed by the feedback and gain resistors, the
effective VIN_CM range is wider than the specified
range. The input common-mode range of the amplifier
depends on the Gain (G), the VOCM voltage, any
externally applied common-mode voltage (VICM) and
the circuit configuration.
For fully differential input configurations, where
VIN+ = -VIN-, the common-mode input voltage can be
estimated using Equation 4-13:
EQUATION 4-13:
RG
RF
V IN_CM V OCM ---------------------- + V ICM ---------------------R +R
R +R
F
G
F
G
For single-ended input configurations there will be an
additional input signal component (either on VIN+ or
VIN-, depending on how the source is connected) to the
input common-mode voltage, as there is no
out-of-phase signal applied to the other input. Applying
the signal to VIN+ (connecting VIN- to ground), the
common-mode input voltage can be approximated
using Equation 4-14:
EQUATION 4-14:
V IN+
RF
RG
V IN_CM V OCM ---------------------- + V ICM + ------------- ---------------------
2
R F + RG
RF + R G
Note:
Here the input voltage VIN+ is equal to the
peak input signal, VIN_P = VIN_PP/2. The
result yields the upper value for the input
common-mode voltage. To estimate the
lower value use the negative term: -VIN+ in
Equation 4-14.
2019 Microchip Technology Inc.
MCP6D11
The output common-mode voltage (VOUT_CM) for the
differential I/O amplifier is defined as the average of the
two output voltages VOUT+ and VOUT-; see Figure 4-2.
The output common-mode voltage VOUT_CM is
primarily determined by the voltage at the VOCM pin,
but they are not identical due to an offset component,
the common-mode offset voltage.
EQUATION 4-15:
V
4.2.4
OUT_CM
V
+V
OUT+
OUT= ------------------------------------------------- V OCM
2
COMMON-MODE OFFSET
VOLTAGE
The common-mode offset voltage (VOS_CM) is defined
as the difference between the output common-mode
voltage and the VOCM voltage.
EQUATION 4-16:
V OS_CM = V OUT_CM – VOCM
4.2.5
OUTPUT HEADROOM
Once the VOCM voltage has been defined for a given
amplifier configuration, verify that the desired
maximum differential output swing (VOUT_PP) falls
within the linear output voltage range of the differential
I/O amplifier. As listed in the DC Electrical
Characteristics table, the MCP6D11 requires a
minimum output headroom (VOH, VOL) of 150 mV.
EQUATION 4-17:
V OUTpp
V OUTmax = V OCM + --------------------4
EQUATION 4-18:
V OUTpp
V OUTmin = V OCM – --------------------4
2019 Microchip Technology Inc.
4.2.6
OUTPUT BALANCE
An ideal differential output signal implies the two
outputs of the differential amplifier should be exactly
equal in amplitude and shifted 180° in phase. Hence,
any imbalance in amplitude or phase between the two
output signals results in an undesirable common-mode
signal on the output. The Output Balance error is the
measure of how well the outputs are balanced and is
defined as the ratio of the output common-mode
voltage (VOUT_CM) to the output differential signal
(VOUT_DM). It is generally expressed as dB in
logarithmic scale:
EQUATION 4-19:
VOUT_CM
Output Balance error = 20log ---------------------V OUT_DM
The function of the internal common-mode feedback
loop circuit drives the output common-mode voltage
(VOUT_CM) to equal the voltage level present at the
VOCM pin. This ensures a very good output balance
over a wide bandwidth (see Figure 3-17). Note that this
figure is derived from simulation results to show the
best-case output balance of the MCP6D11 itself. For
this, the resistor tolerance was set to zero. However, at
lower frequencies, the dominant contribution to the
output balance error comes from the resistor tolerance
of the external feedback network (1 ≠ 2) as the
imbalance creates a common-mode to differential
conversion (see Section 5.1.3 “Mismatches and DC
Errors”). At higher frequencies capacitive and
parasitic effects come into play.
4.2.7
STABILITY CONSIDERATIONS
One of the primary applications for differential I/O
amplifiers like the MCP6D11 is as a high-bandwidth
driver amplifier for Analog-to-Digital converters, as
described in Section 5.3.1 “Driving High Precision
ADCs”. Here, the amplifier’s stability is of particular
concern as the output of the amplifier not only has to
drive a fairly large capacitive load, isolated by only
small value resistors, but also has to respond quickly to
transient currents resulting from the ADC's sampling
effects. In order to analyze the amplifier’s stability in a
closed-loop configuration, the open-loop gain (AOL)
and phase frequency response need to be examined.
Figure 4-3 shows the simulated differential input to output open-loop gain and phase of the MCP6D11 under
two loading conditions: 1k load and no-load. The
no-load condition removes any effect of the open-loop
output impedance interacting with any external load
element.
DS20006162A-page 29
MCP6D11
-60
Open-loop Gain (dB)
-90
Phase
80
-120
AOL
60
-150
40
-180
No Load
20
-210
Noise Gain = 6 dB
0
-240
Open-loop Phase (deg.)
VDD = 5.0V
100
1 k: Load
-20
-270
10k
100k
1M
10M
100M
1G
Frequency (Hz)
FIGURE 4-3:
Simulated Open-Loop Gain
and Phase Response with No-Load and 1 k
Load Condition.
For the simulation to show only the amplifier's forward
path signal response, the two internal 0.7 pF feedback
capacitors were removed. When operating the actual
device, those 0.7 pF integrated capacitors (see
Figure 4-3) are part of the feedback network that sets
the noise gain and phase in the specific application.
This also includes any external feedback capacitors
and parasitic elements which can quickly lead to stability problems, effectively a result of insufficient phase
margin. In general, the phase margin can be found at
the frequency where the noise gain (GN) and the
open-loop gain magnitude intersect; the loop-gain
equals unity (0 dB) at this point. The difference
between the phase at that point and -180 degrees is
defined as the phase margin. Using Figure 4-3 the
extracted phase margin is about 63 degrees for the
1 k load condition. Since the MCP6D11 operates as
an inverting amplifier the noise gain remains at greater
or equal to 1V/V (GN = 1 + RF/RG). This allows the user
to set the signal gain to a fractional gain
(G = RF/RG < 1V/V), with the amplifier's phase margin
at approximately ≥ 30 degrees. The effect of this
reduced phase margin for a G = 0.1V/V configuration
can be seen from in increased gain peaking shown in
Figure 3-1 and Figure 3-2.
Operating the MCP6D11 with a high loop gain will result
in the lowest distortion performance. Therefore, most
ADC driver applications operate the amplifier at a low
signal gain of 1V/V. The loop gain will decrease as AOL
decreases with higher frequencies. Equation 4-20
describes the loop gain for the differential I/O amplifier
having two feedback factors (as discussed in
Section 4.2.2 “Signal Gain, Noise Gain”).
EQUATION 4-20:
A OL
Loop Gain = ----------- = A OL AVG ,
GN
with
1 + 2
AVG = --------------------
DS20006162A-page 30
2
Figure 4-4 shows the simulated differential open-loop
output impedance of the MCP6D11. Starting at the
lower frequencies, the output impedance of the
rail-to-rail output stage is high, then declines with a rate
of -20 dB/decade until flattening out in a mid-range frequency section. The high impedance section will be
significantly reduced when the amplifier is operated in
a closed-loop configuration, as shown in Figure 3-18
and Figure 3-19. At higher frequencies, the open-loop
output impedance starts to increase again at a rate of
+20 dB/decade, resembling a first-order inductive
behavior, indicating that purely capacitive loads can
lead to stability issues (see Section 5.2.4 “Capacitive
Loads”).
2SHQ/RRS2XWSXW,PSHGDQFH
120
10000
VDD = 5.0V
1000
100
10
1
10
100
1k
10k
100k
1M
10M
100M
1G
Frequency (Hz)
FIGURE 4-4:
Simulated Open-Loop
Differential Output Impedance.
Figure 4-3 shows the effect of the output impedance
interacting with the load by comparing the frequency
response of the no-load condition to the 1 k load
condition. The load causes the AOL curve to have its
0 dB cross-over point at lower frequencies as well as
increasing the phase shift.
4.3
Operation
Differential I/O Amplifiers (or Fully Differential
Amplifiers) resemble standard operational amplifiers
configured in an inverting gain configuration. It should
be noted that the polarity signs on the inputs (VIN-,
VIN+) and outputs (VOUT-, VOUT+) typically shown on
differential I/O amplifiers only indicate their phase
relationship, and therefore may be misleading for
correctly identifying input impedances. For this, is it
useful to consider that both signal inputs on the
differential I/O amplifier are in fact summing junctions,
indicated by the labels VSJ- and VSJ+ shown in
Figure 4-5. Because of the closed-loop feedback
around the amplifier, these summing junctions
represent a virtual ground and the resistors RG1 and
RG2 set the input impedance seen by the source. If the
input configuration is for a differential signal, the input
impedance analysis is as simple as it is for an inverting
op amp circuit, but more difficult in the case the input
configuration is for a single-ended signal. Both
situations will be discussed later in Section 5.1
2019 Microchip Technology Inc.
MCP6D11
“Amplifier Configuration Options”. Figure 4-5
shows the typical representation of a differential I/O
amplifier with its feedback resistor network, and also
showing an equivalent circuit implementation based on
standard op amps that illustrates more clearly the
inverting amplifier configuration for the differential
signal path.
RG1
VSJ-
+
VOCM
VIN+
-
VIN-
VOUT+
-
VSJ-
VIN-
RF1
RG1
RF1
-
+
VOUT-
RG2
RF2
VOUT+
+
VOUT-
VOCM
Equivalent
VSJ+
+
VIN+
RG2
VSJ+
RF2
FIGURE 4-5:
Equivalent Basic Circuit Functions.
Comparing the two equivalent differential circuits of
Figure 4-5, the key difference is that in the case of the
two inverting operational amplifiers, the common-mode
voltage is controlled by the voltage applied to the
non-inverting inputs. For the differential I/O amplifier
the output common-mode voltage is controlled using
an independent feedback loop circuit (see Figure 4-1).
4.3.1
VOCM INPUT
As mentioned earlier (see Section 4.1 “Overview”),
the internal feedback control-loop drives the output
common-mode voltage (VOUT_CM) to be equal to the
voltage present at the VOCM pin. When the pin is left
open, VOCM defaults approximately to a mid-supply
voltage level set by the internal resistor divider (see
Figure 4-1).
EQUATION 4-21:
V OUT+ + V OUT-
V OUT_CM = ------------------------------------------------- V OCM
2
The VOCM input can be connected to an external reference voltage and varied within the specified range to
accommodate specific output common-mode levels
and achieve tighter control and higher accuracy. Refer
to Figure 3-30 and Figure 3-31 for the impact on the
achievable distortion when setting the VOCM voltage
away from mid-supply. In any case, an external decoupling capacitor is recommended to be added on the
VOCM pin to reduce the otherwise high output noise for
this high impedance node.
2019 Microchip Technology Inc.
DS20006162A-page 31
MCP6D11
4.3.2
INPUT AND ESD PROTECTION
The inputs have a primary and secondary ESD
protection using diodes connected from each input
terminal to the supply rails.
The design of the MCP6D11 includes comprehensive
circuitry to protect the device against ESD, overvoltage
and reverse-voltage events, as shown in Figure 4-6.
VDD
VSS
MCP6D11
ESD
Clamp
VDD
VDD
VDD
50Ω
-
INVDD
VDD
VSS
OUT+
+
VSS
VSS
IN+
VDD
-
+
OUT-
50Ω
VSS
VSS
VSS
VDD
VSS
VDD
VSS
VOCM
FIGURE 4-6:
ESD and Input Protection Scheme for the MCP6D11.
The input stage of the MCP6D11 is protected against
differential input voltages which exceed approximately
1.4V by two pairs of series diodes connected
back-to-back between the differential amplifier inputs. If
the differential input voltage exceeds 1.4V, the input
current should be limited to 10 mA or less to prevent
damage. Moreover, all pins have clamping diodes to
both power supplies. If any pin is driven to voltages
which exceed either supply, the current should be
limited to under 10 mA. Internal protection diodes
remain present across the input pins in both the
operating and Power-Down mode. Large input signals
during power-down can turn on the input differential
protection diodes, thus producing a load current in the
supply even with the device in Power-Down mode.
The MCP6D11 is protected with an edge-triggered
ESD clamp between the supply pins, VDD and VSS.
Care should be taken to ensure a power supply
turn-on/off edge rate (dV/dt) that does not exceed the
rates stated in Section “Absolute Maximum
Ratings †” to avoid activating this clamp circuit.
4.3.3
POWER-DOWN FUNCTION (PD\)
The design of the MCP6D11 includes a power-down
function which will reduce the quiescent current (IQ)
down to about 5 µA (typical). The PD\ pin is referenced
to the negative supply (VSS). Therefore, when
operating the MCP6D11 with a negative supply voltage
ensure that the voltage applied to the PD\ pin can be
pulled down to within 0.4V of the negative rail. Similarly,
pulling the PD\ high to within 0.4V of the positive rail will
DS20006162A-page 32
PD\
ensure normal operation. Applying voltages at
intermediate levels to the PD\ pin may result in an
increase in quiescent current. When this pin is pulled
low ( VSS) the amplifier is disabled and placed in
Power-Down mode. Tying this pin to a high potential
( VDD) will enable normal operation. There is no
internal pull-up or pull-down resistor and the PD\ pin
should not be left floating. Note that when disabling the
amplifier the signal path is still present for the source
signal through the external resistors, which results in
relatively poor signal isolation from the input to output
in Power-Down mode. The Power-Down circuit of the
MCP6D11 offers very fast turn-on and turn-off times,
with typically 1 µs for the turn-on time and only 40 ns
for the turn-off time (see Figure 3-48 and Figure 3-49).
4.4
Test Circuits
Since most test equipment is specified for a 50
impedance, it requires the characterization circuit for
the device-under-test (DUT) to include proper input and
output termination or impedance matching. In addition,
most equipment also has single-ended signal inputs or
outputs. The basic characterization circuit therefore
has the MCP6D11 configured for a singled-ended input
with matched, 50 input termination, as shown in
Figure 4-7. The amplifier's differential outputs drive the
load resistor, which is split in order to facilitate a differential to single-ended signal conversion using a miniature RF-transformer (or Balun) while also providing a
2019 Microchip Technology Inc.
MCP6D11
50 output impedance. The 50 input impedance from
the network analyzer reflects through the transformer
to be in parallel with the 52.3 resistor.
a slightly higher attenuation due to the transformer
insertion loss. The standard output load used for most
tests is 1 k which results in approximately 31.8 dB of
loss. This signal loss is normalized out for the typical
frequency response curves to show the gain response
to the amplifier output pins. Note that the 1:1
RF-transformer acts as a bandpass filter with a usable
range from about 100 kHz to 500 MHz for this
application.
The total load impedance seen by the differential I/O
amplifier is RL = 2 x RO + (ROT || 50). Due to the
voltage divider on the output formed by the load
component values, the amplifier's output is attenuated,
see column “Attenuation” in Table 4-1. When using a
transformer as shown in Figure 4-7, the signal will see
50Ω Source Impedance
(Network Analyzer Output)
VDD
RG1
1 kΩ
-
VIN-
RS
RT1
52.3Ω
VS
C1
0.1 μF
RO1
487Ω
PD\
VOCM
+
N1
VOUT+
ROT
52.3Ω
MCP6D11
VOUT-
-
ADTL1-4-75+
N2
+
RO2
487Ω
VSS
VIN+
RG2
RT2 1 kΩ
52.3Ω
RS1
50Ω
FIGURE 4-7:
RF2
1 kΩ
Basic Characterization Circuit Configuration for Frequency Domain Tests.
Furthermore, the components on the non-signal input
side match very closely the components on the signal
input side. This has the advantage of closely matching
the two divider networks on each side of the amplifier.
Alternatively, the three resistors on the non-signal input
side, RG2, RT2, RS2, can be replaced by a single
resistor to ground using a standard E96 value of
1.02 k with some loss in gain balancing between the
two sides. For any active channel tests the power-down
pin PD\ is tied to the positive supply (VDD).
Most characterization plots are based on a 1 k value
for RF (RF1 = RF2). While this resistor value can be
adapted for a specific application purpose, the 1 k
value offers a good compromise with issues related to
this resistor value, specifically:
• Output loading: both feedback resistors contribute
to the total load seen across the outputs; for
TABLE 4-1:
50 Ω Load
(Network Analyzer Input)
RF1
1 kΩ
example the total differential loads shown in
Figure 4-7 is 1 k || 2 k = 667. The 1 k value
also reduces the power dissipated in the feedback
networks.
• Noise contribution: appears as the (4kTRF) term
and the current noise multiplied by the resistor
value (see paragraph Noise Analysis).
• Feedback pole at the summing junction inputs:
this pole is created by the feedback resistor (RF)
value and the 1.0 pF differential input capacitance, CIN_DM, (plus any PC-board parasitic) and
adds a zero in the noise gain, resulting in a
reduced phase margin in most cases. The two
internal 0.7 pF feedback capacitors (see
Figure 4-1) combine with the external feedback
resistors to introduce a zero in the noise gain,
reducing the effect of the feedback pole.
COMPONENT VALUES FOR DIFFERENTIAL TO SINGLE-ENDED OUTPUT USING A
1:1 TRANSFORMER
RL
RO1, RO2
ROT
Attenuation
100
25
open
6 dB
200
86.6
69.8
16.8 dB
499
237
56.2
25.5 dB
1 k
487
52.3
31.8 dB
2 k
976
51.1
37.9 dB
2019 Microchip Technology Inc.
DS20006162A-page 33
MCP6D11
4.4.1
DUAL-SUPPLY VERSUS SINGLE
SUPPLY CHARACTERIZATION
Although most end-equipment applications use a
single-supply implementation, the factory device
characterization is
typically
done using a
dual-balanced supply. For example, a 5V test uses a
±2.5V supply and a 3V test uses a ±1.5V supply with
the VOCM input pin at ground. Using a dual supply
keeps the input and output common-mode voltages
near mid-supply with optimal headroom for the output
swing and no DC bias currents for level shifting. It also
avoids the need for additional DC blocking capacitors
that could restrict the signal bandwidth. This setup is
used for characterizations such as the frequency
response, harmonic distortion, and noise plots. Some
of the time domain plots are done with a single supply
to obtain the correct movement of the input
common-mode voltage.
4.4.2
SIMULATED CHARACTERIZATION
CURVES
Some of the characterization data can only be
generated through simulation in order to reflect the
actual performance of the device without being
constrained by hardware and measurement errors.
One example of such a case is the output balance plot
of Figure 3-17, which shows the best-case output
balance by using exact matching on the external
resistors for the single-ended input to differential output
configuration. As discussed earlier, in practice the
output balance is being constrained by the resistor
value mismatch primarily at low frequencies but will
converge with the high frequency portion of Figure 3-17
due to parasitic effects.
Other Performance Figures that are based on
simulations are:
• AOL gain and phase, see Figure 3-16.
• Settling times, see Figure 3-44 and Figure 3-45.
• Closed loop output impedance versus frequency,
see Figure 3-18 and Figure 3-19.
• CMRR vs frequency, see Figure 3-14.
• PSRR vs frequency, Figure 3-15.
DS20006162A-page 34
2019 Microchip Technology Inc.
MCP6D11
5.0
APPLICATION INFORMATION
5.1.1
5.1
Amplifier Configuration Options
A differential signal source VSDiff, with its associated
output impedances RS1 and RS2, is directly connected
(dc-coupled) to the differential I/O amplifier, as shown
in Figure 5-1. Alternatively, two capacitors can be
inserted in series with each RG resistor to achieve an
ac-coupled configuration. Because the voltage
between the two amplifier summing junction inputs is
driven to a null by negative feedback, they are virtually
connected, and the differential input resistance,
ZIN_AMP, is simply RG1 + RG2. Keep in mind that there
is a frequency dependency to ZIN_AMP which may
require for some applications to place a termination
resistor, RT, between the signal inputs, as shown in
Figure 5-2. When calculating the amplifier gain the
source impedance, RS (shown here split in half for symmetry) needs to be added to the RG value; assuming a
balanced design the gain is given to:
When applying Differential I/O amplifiers there are two
common configurations: interfacing to a differential
source and driving the output differentially, or
interfacing to a single-ended source and converting the
signal into a differential output. Depending on the
nature and impedance of the source, an input
impedance match needs to be implemented.
Accomplishing the optimum matching will be different
for each configuration. As mentioned earlier, operating
the differential I/O amplifier in a lab environment often
requires configuration for matched 50 single-ended
inputs and outputs (see Section 4.4 “Test Circuits”).
However, for many signal chain applications the issue
of impedance matching may be neglected as the
source has sufficiently low impedance in the bandwidth
of interest. But it is generally important to understand
the interaction between a source impedance and the
gain-setting network of a differential I/O amplifier.
INTERFACING TO A DIFFERENTIAL
SOURCE
EQUATION 5-1:
RF
G = ---------------------RG + R S
ZSource
ZIN_Amp
RF1
RG1
VSDiff
RS1
-
VINVOCM
RS2
+
VOUT+
MCP6D11
VIN+
-
+
VOUT-
RG2
RF2
FIGURE 5-1:
Differential I/O Amplifier Driven by a Differential Source with DC-Coupling.
When driving a signal over a longer distance, for
example twisted-pair cables, termination with a resistor
across the differential inputs may be required, as
illustrated in Figure 5-2. The termination resistor, RT,
will appear in parallel to the sum of the two RG
resistors. The calculation of RT is shown in
Equation 5-2:
For example, with RG1 = RG2 = 500, and if the source
impedance to match up to is RS = 100
(RS1 = RS2 = 50), then the required value for RT is
111. Hence, the amplifiers input impedance ZIN_AMP,
as
seen
by
the
source
will
be
(RT || (RG1 + RG2)) = 100.
EQUATION 5-2:
1
R T = ----------------------------------------------1
1
------ – ---------------------------------R S R G1 + R G2
2019 Microchip Technology Inc.
DS20006162A-page 35
MCP6D11
ZIN_Amp
RF1
VSDiff
VIN-
RG1
-
+
RS1
RT
VOCM
MCP6D11
RS2
VIN+
VOUT+
-
+
VOUT-
RG2
RF2
FIGURE 5-2:
Differential I/O Amplifier in Differential Configuration with Input Termination.
5.1.2
The DC biasing levels are determined as described in
Section 4.2 “Terminology and Definitions”. For a
true differential input, the common-mode voltages on
the summing junction inputs of the amplifier remain
fixed and do not move with the input signal (unlike the
single-ended input configurations where the input common-mode voltages do vary with the input signal). For
the AC coupled configuration the VOCM voltage also is
the input biasing voltage since there is no DC current
path through the feedback and gain resistors. In either
case, setting the VOCM voltage to a mid-supply value,
which is the default value if this pin is not externally
driven, assures symmetry and therefore maximizes the
achievable output swing.
ZSource
INTERFACING TO A
SINGLE-ENDED SOURCE
If the source is single-ended and referenced to ground,
the differential I/O amplifier can be used to convert a
single-ended input signal into a differential output
signal while also providing a DC level shift; Figure 5-3
shows the basic circuit for this configuration. Again, VS
is the input source with the associated source
impedance ZSource = RS.
ZIN_Amp
RF1
RS
VS
VIN-
-
+
RG1
VOCM
VOUT+
MCP6D11
VIN+
-
+
VOUT-
RG2
RF2
FIGURE 5-3:
DS20006162A-page 36
Differential I/O Amplifier Driven by a Single-Ended Source with DC-Coupling.
2019 Microchip Technology Inc.
MCP6D11
As discussed earlier, any source resistance (ZSource)
will change the gain of the amplifier. For a single-ended
input this occurs in an unbalanced way such that it
affects only one side, for example RG1 as shown in
Figure 5-3. To maintain balance between the
amplifier's two feedback paths the user must set
RF1 = RF2 and (RG1 + RS) = RG2. The effect of resistor
mismatching
is
discussed
in
Section 5.1.3
“Mismatches and DC Errors”. For the circuit shown
in Figure 5-3 the differential output voltage is given by
Equation 5-3:
EQUATION 5-3:
and
R
Use Equation 5-4 to determine the effective input
impedance for the single-ended input configuration:
EQUATION 5-4:
2V S 1 – 1 + 2V OCM 1 – 2
V OUT_DM = ---------------------------------------------------------------------------------- +
1
2
Where:
resistor RG1 is reduced by the moving common-mode
voltage component, therefore resulting in an increased
input impedance. The amplifier's common-mode
feedback loop is a critical component in developing a
differential output from a single-ended input signal, as
it needs to dynamically adjust the input common-mode
voltage in order to maintain balanced outputs.
Meanwhile, the differential loop of the amplifier is
forcing the voltages at the summing junctions to remain
equal.
R G1
Z IN_AMP = ---------------------------------------------RF
1 – ------------------------------------2 RG1 + R F
+R
S
G1
1 = ------------------------------------------- ,
R
G1
+R +R
S
F1
Figure 5-4 shows the single-ended input circuit of
Figure 5-3 extended for matching input termination,
which adds resistor RT1. The input impedance as seen
by the source (ZIN) therefore becomes:
R
G2
2 = ---------------------------- .
R G2 + R F2
In order to calculate the amplifier's input impedance,
ZIN_AMP, for this single-ended configuration it is
important to recognize that the impedance looking in at
the VIN- point is actually higher than just the physical
RG1 value, as it could be assumed based on a standard
inverting op amp circuit. Compared to the differential
input configuration, here the input common-mode
voltage has an additional signal dependent term (see
Equation 4-14) resulting in a portion of the input signal
moving the summing junctions of the differential I/O
amplifier in the same direction as the applied signal.
This creates a signal related current flow in the
non-signal side RG2 resistor and produces the inverted
output signal. The current flow in the signal-side gain
To retain balance between the feedback resistor networks it is necessary to adjust the gain resistor RG2
accordingly, here shown by adding RT2 which can be
calculated as RT2 = RS || RT1. If the resistor ratios are
matched, the ratio of single-ended input to differential
output gain is given by Equation 5-5:
EQUATION 5-5:
VOUT_DM
R F1
2RT1
Gain (G) = ---------------------- = ----------------------------------------- ---------------------VS
R G1 + R S R T1 R T1 + R S
ZIN_Amp
ZIN
VIN-
RS
RF1
-
+
RG1
VOCM
RT1
VS
ZIN = RT1 || ZIN_AMP.
MCP6D11
VIN+
-
+
RT2
FIGURE 5-4:
VOUT+
VOUT-
RG2
RF2
Single-Ended Configuration with Input Termination and Resistor Ratio Matching.
2019 Microchip Technology Inc.
DS20006162A-page 37
MCP6D11
For the single-ended configuration with input
impedance matching to a 50 source, Table 5-1
provides the required resistors using 1% standard
values.
TABLE 5-1:
RF, RG, RT VALUES (1%) FOR SINGLE-ENDED INPUT PER Figure 5-4
Ideal Gain
(V/V)
Act. Gain
(V/V)
RF1, RF2
()
RG1
()
RG1* ()
(Note 1)
RT1
()
RG2
()
RT2 ()
(Note 2)
ZIN_AMP
()
ZIN
()
1
0.997
1000
1000
1025.5
52.3
1020
25.5
1333
50.3
1
1.010
1000
976
1001.2
51.1
1020
25.2
1307
49.2
2
1.988
1020
499
524.5
52.3
523
25.5
754
48.9
5
5.057
1000
187
214.1
59.0
215
27.1
336
50.2
10
10.009
1020
88.7
117.4
68.1
118
28.7
183
50.6
Note 1:
2:
5.1.3
Effective gain resistor value: RG1* = RG1 + (RS || RT1); RS = 50.
RT2 = RT1 || RS.
MISMATCHES AND DC ERRORS
Compared to a standard op amp, the differential I/O
amplifier has an additional output error term that arises
from the effects of mismatching of the resistor values
and feedback ratios, see Section 4.2.2 “Signal Gain,
Noise Gain”. The user must select from standard
resistor values (e.g. E96) and define the tolerance (e.g.
1% or 0.1%) suitable for the application, which will in
almost all cases lead to some degree of imbalance, or
difference in the feedback factors (). For example,
when selecting 1% tolerance resistors the worst case
gain mismatch will be +/-2%; one side of the feedback
path is at +2%, the other at -2%. Any such mismatch
will cause a common-mode to differential conversion
creating additional differential error terms. Opting for
resistor values with a 0.1% tolerance is a good compromise between DC precision and cost.
The parameters that are affected and need to be
considered for a DC error analysis are the VOCM
voltage, any input common-mode voltage from the
source (VICM), and the input bias current.
The input bias current (IB) contributes two error terms,
one based on the resistor tolerance (±T; for
1% T = 0.01) and the other based on the gain mismatch. Estimate the first error term by multiplying the
input bias current by (±2 x T x RF_Nom), with RF_Nom
being the nominal feedback resistor value, for example
1 k. To estimate the IB error due to the gain mismatch
multiply IB by the average RF value times the (/AVG)
is the conversion gain factor.
Additional terms for a comprehensive DC error analysis
should include the input offset voltage (VOS) and the
input offset current (IOS). Before adding to the total differential output error the input offset voltage needs to
be multiplied by the noise gain (GN), which in the case
of the differential I/O amplifier is the average of the two
noise gains resulting from the two mismatched RG/RF
ratios. The error resulting from the input offset current
is simply referred to the output by multiplying with the
average feedback resistor value (RF_AVG).
To estimate the error contribution from VICM and VOCM
to the differential output voltage (VOUT_DM) and
assuming the differential input voltage is zero, use
Equation 5-6 where the term (/AVG) is the
conversion gain factor to the output for the gain ratio
mismatch.
EQUATION 5-6:
V OUT_DM V OCM – V ICM -------------- AVG
DS20006162A-page 38
2019 Microchip Technology Inc.
MCP6D11
5.2
Noise and Distortion
5.2.1
referred differential noise (eno) of an amplifier stage the
surrounding resistor network contributions need to be
considered. Shown in Figure 5-5 is the general noise
model of a differential I/O amplifier and its resistor
feedback components.
NOISE ANALYSIS
The MCP6D11 features very low noise with the voltage
noise density at 5.0 nV/√Hz and the current noise
density at 0.6 pA/√Hz. When analyzing the total output
enRG1
enRF1
RF1
RG1
inenVocm
in+
-
+
VOCM
+
eno
-
eni
enRG2
FIGURE 5-5:
RG2
RF2
enRF2
Differential I/O Amplifier Noise Analysis Model.
The analysis starts by identifying each voltage- and
current-noise term and its corresponding multiplication
factor (noise gain) in order to derive its contribution to
the total output noise (eno). The individual
output-referred noise terms are then squared to
combine noise as powers and are subsequently
combined as a root-sum-of-squares (RSS). For the
Differential I/O amplifier the voltage- and current-noise
terms from each feedback path result in a 2 x
contribution to the total noise as shown in Equation 5-7
below. One additional term is the common-mode
voltage noise (envocm), which normally reflects to the
output as a common-mode term, unless the two
feedback ratios are mismatched. Then a conversion
from common-mode to differential will occur. For envocm
the gain multiplier when referred to the output is:
GN x (1 - 2), which will be zero when 1 = 2.
EQUATION 5-7:
e no =
2
2
2
2
2
2
2e ni + 2i n R eq1 + 2i n R eq2 + 2e nvocm 1 – 2 + 2e nRG1 1 – 1 + 2e nRG2 1 – 2
2
2
------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + e nRF1 + e nRF2
2
1 + 2
Where:
R
eq1
= R
G1
R
F2
R eq2 = R G2 R F2
If the feedback ratios, 1 and 2 (RG = RG1 = RG2,
RF = RF1 = RF2) are equal, the equation simplifies considerably to an expression very similar to a common
voltage-feedback op amp's noise equation, as shown
in Equation 5-8. Also, the current noise terms are
assumed to be equal (in+ = in-) and uncorrelated.
2019 Microchip Technology Inc.
DS20006162A-page 39
MCP6D11
EQUATION 5-8:
e
no =
R 2
R 2
2
2
F
F
e 1 + -------- + 2 i R + 2 4kTR -------- + 2 4kTR
ni
n F
GR
F
R G
G
Where: 4kT = 1.64-20J at 298K (25°C)
The noise contribution from resistors RG1, RF1, RG2
and RF2 can be calculated based on the Johnson noise
equation: enR = √4kTR, where k is Boltzmann's
constant (1.38065 x 10-23J/K), T is the resistor's
absolute temperature in Kelvin, and R is the resistor
value in ohms ().
The last term is the output noise resulting from both the
RF and RG resistors, at again twice the value for the
output noise power of each side added together.
The input referred noise of the MCP6D11 can be
equated to that of a 1.6 k resistor. The recommended
value for the feedback resistor RF is 1k, which results
in the total output referred noise to be dominated by the
amplifier's voltage noise. While there is flexibility in
selecting different values for RF (and similarly for RG),
lowering the feedback resistor value in order to lower
its noise contribution will increase the amplifier's total
output load and eventually result in an increase in
distortion. Scaling the resistor value up will have the
opposite effect of potentially improving distortion at the
expense of higher noise contribution. However,
because the feedback resistor interacts with the
amplifier's input capacitance large values can lead to a
noticeable reduction in phase margin and cause
stability issues. A typical approach is to start with the
recommended feedback resistor value and set the
desired gain by scaling the gain resistor (RG)
accordingly; Table 5-2 shows some example resistor
values and corresponding noise results.
By using the noise gain (GN = 1+ RF/RG) the two
resistor noise terms can be combined into a single term
of (4kTRFGN) resulting in a much simplified equation
for the amplifier's differential output noise:
EQUATION 5-9:
e no =
2
2
e ni G N + 2 i n R F + 2 4kTR F G N
The first term of Equation 5-9 is the differential input
noise times the noise gain. The second term is the
input current noise times the feedback resistor - twice,
since there are two uncorrelated current noise terms.
TABLE 5-2:
EXAMPLE OUTPUT NOISE RESULTS FOR THE SINGLE-ENDED INPUT
CONFIGURATION WITH 50 INPUT MATCHING PER Figure 5-4
Ideal Gain
(V/V)
Act. Gain
(V/V)
RF1, RF2
()
RG1
()
RT1
()
RG2
()
ZIN
()
Diff-Out Noise
eno (nV/√Hz)
Noise RTI
(nV/√Hz)
1
0.997
1000
1000
52.3
1020
50.3
12.90
12.90
2
1.988
1020
499
52.3
523
48.9
18.02
9.06
5
5.057
1000
187
59.0
215
50.2
31.99
6.33
10
10.009
1020
88.7
68.1
118
50.6
52.60
5.26
5.2.2
FACTORS AFFECTING HARMONIC
DISTORTION
In general, an amplifier's output harmonic distortion
mainly relates to the open loop linearity in the output
stage corrected by the loop gain at the fundamental
frequency. Reducing the total load impedance,
including the effect of the feedback resistor as
discussed previously, the output stage open loop
linearity degrades, causing an increase in harmonic
distortion. Secondly, harmonic distortion will degrade
as a function of the amplifier's output swing due to fine
scale open loop output stage nonlinearities. A nominal
swing of 2Vpp is typically used for harmonic distortion
testing where Figure 3-29 illustrates the effect of going
up to an 8Vpp differential swing that is more common
with SAR-type ADC converters. An increase in the
DS20006162A-page 40
amplifiers' gain correspondingly reduces the available
loop gain to correct errors resulting in an increase in
harmonic distortion terms.
The MCP6D11 has a nearly constant distortion level
when the VOCM operating point is moved within the
allowed range; see Figure 3-30 and Figure 3-31.
Driving the VOCM voltage beyond this range or the
output voltages close to the supply rails will rapidly
degrade the distortion performance.
The device characterization used primarily resistors
with a 1% tolerance. The resulting imbalance of the
feedback factors does not directly degrade the
distortion performance of the amplifier, but rather DC
related
errors
(see
section
Section 5.1.3
“Mismatches and DC Errors”).
2019 Microchip Technology Inc.
MCP6D11
5.2.3
SIGNAL BANDWIDTH LIMITATIONS
Even when the application may not require the use of
series RISO resistors, good practice is to leave a
footprint for the RISO components on the PC-board
layout (a 0 value initially) for later adjustment in case
the response appears unacceptable.
5.2.4
Isolation Resistance (Ω)
Although the MCP6D11 has a unity gain bandwidth of
90 MHz, it is primarily intended as driver for lower
sample rate, high-precision ADCs with baseband input
signal bandwidths in the DC to 100 kHz range. The
high open loop gain and bandwidth of the MCP6D11
provides ultra-low distortion and fast settling times.
Maximum power bandwidth is limited by the slew rate
capability, which is typically 25V/µs. Operation with
input signals above 100 kHz with near full output
swings will see an increase in distortion levels (see
Figure 3-22).
CAPACITIVE LOADS
Directly connecting a capacitive load to the output pins
of a closed loop amplifier such as the MCP6D11 can
lead to an unstable response; see the step response
plots into a capacitive load Figure 3-37 and
Figure 3-38. As illustrated in Figure 4-4, the rail-to-rail
output stage of the MCP6D11 exhibits an inductive
characteristic in the open loop output impedance at
higher frequencies. This inductive open loop output
impedance will interact with any capacitance present at
the amplifier's outputs causing an additional phase
shift, i.e. phase margin reduction. Account for the total
capacitive load by considering all contributions from
sources including feedback capacitors, next-stage
input capacitance and PC-board parasitics. Larger values of feedback capacitors (CF greater than 10 pF) can
risk a low phase margin. Including a 10 to 15 series
resistor with a feedback capacitor can be used to
reduce this effect.
220
200
180
160
140
120
100
80
60
40
20
0
G = 1V/V
G = 2V/V
1
10
100
Differential Load Capacitor (pF)
FIGURE 5-6:
Capacitor.
5.3
1,000
RISO vs. Differential Load
Application Example
5.3.1
DRIVING HIGH PRECISION ADCS
The MCP6D11 differential I/O amplifier was designed
primarily as an integrated front-end driver amplifier
solution for high resolution ADCs, such as the SAR
ADC MCP33131D. The 16-bit MCP33131D is part of a
family of low-power 16-/14-/12-Bit, 1Msps SAR ADCs
that feature differential inputs which are preferably
driven by an amplifier with differential outputs to preserve their full performance.
In most cases, inserting small value resistors (RISO) in
series with each of the amplifier's outputs will isolate
the capacitive load and can help avoiding or eliminating
stability problems. Refer to Figure 5-6 for suggested
RISO values. In general, as the noise gain (GN) of the
device increases the value of the RISO resistor can be
reduced while still obtaining a dampened response.
The circuit in Figure 5-7 shows the MCP6D11 amplifier
in a dc-coupled differential-input to differential-output
configuration driving the MCP33131D while operating
on a single-supply. The circuit can easily be adapted for
a single-ended input to differential output configuration.
MCP1501
Voltage
Reference
VDC
VREF
CR
10 µF
RF2
Differential Input Signal
VREF
VIN+
0V
1k
RG2
1 k
VREF/2
+
VREF VIN-
RG1 1 k
Gain = 1V/V
FIGURE 5-7:
-
VOCM
0.1 µF
0V
VDD
+
VSS
1.8V to 5.5V
VREF
5.0V
VREF/2
0V
VREF AVDD DVIO
AIN+
Riso
24
MCP6D11
-
1.8V
C1
1.8 nF
Riso
24
SDI
MCP331x1D-XX
AIN-
C1
1.8 nF
VREF
VREF/2
0V
GND
CNVST
SCLK
SDO
Host Device
(PIC32MZ)
RF1
1 k
Circuit Example for the MCP6D11 Driving the 16-bit 1Msps SAR ADC MCP33131D.
2019 Microchip Technology Inc.
DS20006162A-page 41
MCP6D11
In almost all cases, a single-pole RC low-pass filter
should be placed between the driver amplifier and the
ADC, as shown in Figure 5-7. The input stage of the
ADC is a sample-and-hold and the internal capacitor
appears as a capacitive load to the driver amplifier. The
typical sampling capacitor of the MCP33131D is 62 pF
(differential). As part of the sampling process,
significant charge injection occurs, resulting in fast
current pulses that the amplifier output needs to react
to while settling from this transient load condition to the
new signal value within the allowed acquisition time.
Here, the RC components serve a number of purposes.
The capacitor (C1) helps to dampen the charge
injection effects by providing a charge reservoir for an
instantaneous current transfer with the ADC's sampling
capacitor. Therefore, the value of this charge capacitor
(C1) needs to be several times larger than the ADC
sampling capacitor, however too high values will load
the amplifier and result in increased distortion. The
capacitor should be a NP0- or C0G -type due to their
superior electrical and temperature stability.
The two series resistors (RISO) primarily serve to
isolate the capacitive loading due to capacitor C1 plus
the sampling capacitor from the amplifier outputs and
improved stability. Their value, along with the value of
C1, should be chosen to achieve the desired settling
behavior. For example, settling to 15-bit accuracy will
require approximately 10 RC time constants. The
number of time constants may vary between ADC
models,
depending
on
how
the
internal
Sample-and-Hold circuit operates. It is generally best
to keep the resistor value as low as possible while
maintaining stability. High resistor values can be
detrimental and lead to increased distortion. The RC
network also performs a low-pass function and sets a
bandwidth limit for the noise. However, as a single-pole
filter, it is of limited use as an anti-aliasing filter. To
implement a higher-order anti-aliasing filter, the
MCP6D11 differential I/O amplifier can be configured to
perform this function, such as an MFB-type filter.
Shown in Figure 5-8 is the FFT of the MCP6D11 driving
the MCP33131 differentially using a 4V ADC reference
voltage resulting in an 8Vpp full-scale range (FSR).
The 9.674 kHz input signal is set to -1 dBFS and the
second and third harmonic is down at -113.3 dBc and
-111.3 dBc respectively, with THD at -104.9 dBc.
FIGURE 5-8:
FFT Result of the MCP6D11
driving the MCP33131D, FSR = 8Vpp,
fin = 9.7 kHz at -1dBFS.
Figure 5-9 shows the FFT for the same configuration as
in Figure 5-8, now with the input signal at 100 kHz. The
highest harmonic is HD3 at -92.8 dBc while the second
harmonic is at -101.6 dBc. THD is measured at
-91.3 dBc.
The -3 dB frequency of the RC filter is calculated using
Equation 5-10:
EQUATION 5-10:
1
f -3dB = ----------------------------------------------------------2 R ISO C1 + C Sampling
Note:
The ADC input capacitance should be
factored into the frequency response of the
input filter.
DS20006162A-page 42
FIGURE 5-9:
FFT Result of the MCP6D11
Driving the MCP33131D, FSR = 8Vpp,
fin = 100 kHz at -1 dBFS.
2019 Microchip Technology Inc.
MCP6D11
5.4
5.4.1
Application Tips
SUPPLY BYPASSING CAPACITORS
When operating the MCP6D11 in a single-supply
configuration (VSS = Ground), only the VDD pin will
require supply bypass capacitors. Using split supplies
ensure that both amplifier supply pins have similar
bypass capacitors tied to a low-noise analog ground.
The QFN-16 package has four pins for the VDD and
VSS supply connections, which are usually tied
together on the PCB and the bypass capacitor can be
shared for each set of four supply pins. The primary
high-frequency bypass capacitors should be placed as
close to the amplifier's supply pins as possible with
direct connection to a low impedance analog ground.
Use a 1 nF and a 0.1 µF leadless surface mount (e.g.
size 0603), ceramic capacitor in parallel for each
supply. For best high-frequency decoupling, consider
X2Y-type capacitors that offer a much higher
self-resonance frequency over standard capacitors.
Most applications benefit from adding a bulk capacitor
(e.g. 2.2 µF to 10 µF, tantalum or ceramic) within
approximately 20 mm (0.8 inch) of the supply pins,
which can be shared among multiple MCP6D11
devices.
5.4.2
VOCM BYPASSING
• When using the QFN-16 package, note that the
FB+ and FB- pins are duplicates of the output pins
(OUT+, OUT-) but are placed conveniently close
to the corresponding inputs such that the external
feedback resistor (RF) can be placed with
minimum trace length. This minimizes potential
parasitic capacitances affecting sensitive device
pins. Note that the internal trace adds about 3 to
the external feedback resistor value.
• When routing differential/complementary signals,
ensure a highly symmetric layout placement with
identical trace length. Even small amounts of
asymmetry can lead to distortion and balance
errors. Routing such signal traces over a longer
distance will in most cases require microstrip
layout and impedance matching techniques.
• Use surface mount small geometry 0603 or 0402
size resistors and capacitors to minimize parasitic
capacitance effects.
• The exposed thermal pad on the QFN-16
package should be soldered to a low-noise
ground or power plane. While the pad is
electrically isolated from the die it must be
connected preferably to a ground plane
(alternatively a power plane) and not be left
floating.
In addition to the supply decoupling, the VOCM pin
should be bypassed with a 0.1 µF leadless surface
mount, ceramic capacitor for either case, externally
driven or left open. This will reduce the noise
feedthrough to the amplifier's output from this high
impedance input.
5.4.3
PCB LAYOUT
While the MCP6D11 amplifier may be used to for relatively low signal frequencies (f < 500 kHz), it is critical
to apply high-frequency PC-board techniques in order
to preserve the low distortion and fast step response
capabilities of the device. The input summing junctions
and the differential outputs in particular of the
MCP6D11 are very sensitive to parasitic capacitances
even as low as 0.5 pF.
Following are some specific recommendations:
• Continuous ground planes usually work well to
establish a low impedance analog ground
potential. Also, multi-layer PCB designs often use
power planes. When used, the user must make
sure that both power and ground planes include
keep-out areas under and around the device and
around sensitive nodes on the feedback and gain
setting components (e.g. RG, RF, CF).
• The feedback resistors (RF) should be placed with
minimum trace length between the amplifier's
output and summing function input pins.
• The gain resistors (RG) should connect to the
summing junction pins with minimum trace length.
2019 Microchip Technology Inc.
DS20006162A-page 43
MCP6D11
NOTES:
DS20006162A-page 44
2019 Microchip Technology Inc.
MCP6D11
6.0
DESIGN AIDS
Microchip provides the basic design aids needed for
the MCP6D11 family of op amps.
6.1
Microchip Advanced Part Selector
(MAPS)
MAPS is a software tool that helps efficiently identify
Microchip devices that fit a particular design
requirement. Available at no cost from the Microchip
web site at www.microchip.com/maps, MAPS is an
overall selection tool for Microchip’s product portfolio
that includes Analog, Memory, MCUs and DSCs. Using
this tool, a customer can define a filter to sort features
for a parametric search of devices and export
side-by-side technical comparison reports. Helpful links
are also provided for data sheets, purchase and
sampling of Microchip parts.
6.2
Application Notes
The following Microchip Application Notes are
available on the Microchip web site at www.microchip.
com/appnotes and are recommended as supplemental
reference resources.
ADN003: “Select the Right Operational Amplifier for
your Filtering Circuits”, DS21821
AN722: “Operational Amplifier Topologies and DC
Specifications”, DS00722
AN723: “Operational Amplifier AC Specifications and
Applications”, DS00723
AN884: “Driving Capacitive Loads With Op Amps”,
DS00884
AN990: “Analog Sensor Conditioning Circuits –
An Overview”, DS00990
AN1177: “Op Amp Precision Design: DC Errors”,
DS01177
AN1228: “Op Amp Precision Design: Random Noise”,
DS01228
AN1258: “Op Amp Precision Design: PCB Layout
Techniques”, DS01258
2019 Microchip Technology Inc.
DS20006162A-page 45
MCP6D11
NOTES:
DS20006162A-page 46
2019 Microchip Technology Inc.
MCP6D11
7.0
PACKAGING INFORMATION
7.1
Package Marking Information
8-Lead MSOP
Example
6D11
908256
16-Lead, 3x3 mm QFN
Example
Part Number
Legend: XX...X
Y
YY
WW
NNN
e3
*
Note:
ACC
1908
256
Code
MCP6D11-E/MG
ACC
MCP6D11T-E/MG
ACC
Customer-specific information
Year code (last digit of calendar year)
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code
Pb-free JEDEC® designator for Matte Tin (Sn)
This package is Pb-free. The Pb-free JEDEC designator ( e3 )
can be found on the outer packaging for this package.
In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
2019 Microchip Technology Inc.
DS20006162A-page 47
MCP6D11
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS20006162A-page 48
2019 Microchip Technology Inc.
MCP6D11
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2019 Microchip Technology Inc.
DS20006162A-page 49
MCP6D11
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS20006162A-page 50
2019 Microchip Technology Inc.
MCP6D11
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2019 Microchip Technology Inc.
DS20006162A-page 51
MCP6D11
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS20006162A-page 52
2019 Microchip Technology Inc.
MCP6D11
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2019 Microchip Technology Inc.
DS20006162A-page 53
MCP6D11
NOTES:
DS20006162A-page 54
2019 Microchip Technology Inc.
MCP6D11
APPENDIX A:
REVISION HISTORY
Revision A (February 2019)
• Initial release of this Data Sheet.
2019 Microchip Technology Inc.
DS20006162A-page 55
MCP6D11
NOTES:
2019 Microchip Technology Inc.
DS20006162A-page 56
MCP6D11
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
[X](1)
-X
/XX
Tape and Reel
Option
Temperature
Range
Package
PART NO.
Device
Device:
MCP6D11 - Low Noise, Precision, 90 MHz
Differential I/O Amplifier
Tape and Reel
Option:
Blank
T
= Standard packaging (tube or tray)
= Tape and Reel(1)
Temperature
Range:
E
= -40C to +125C
Package:
MS
MG
=
=
(Extended)
8-Lead Plastic Micro Small Outline Package (MSOP)
16-Lead Quad Flat No Lead Package (QFN)
2019 Microchip Technology Inc.
Examples:
a)
MCP6D11-E/MS
Extended temperature,
MSOP package
b)
MCP6D11-E/MG
Extended temperature,
QFN package
c)
MCP6D11T-E/MS
Extended temperature,
MSOP package,
Tape and Reel
d)
MCP6D11T-E/MG
Extended temperature,
QFN package,
Tape and Reel
Note 1:
Tape and Reel identifier only appears in the
catalog part number description. This
identifier is used for ordering purposes and
is not printed on the device package. Check
with your Microchip Sales Office for package
availability with the Tape and Reel option.
DS20006162A-page 57
MCP6D11
NOTES:
DS20006162A-page 58
2019 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
•
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights unless otherwise stated.
Trademarks
Microchip received ISO/TS-16949:2009 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
SQTP is a service mark of Microchip Technology Incorporated in
the U.S.A.
QUALITY MANAGEMENT SYSTEM
CERTIFIED BY DNV
The Microchip name and logo, the Microchip logo, AnyRate, AVR,
AVR logo, AVR Freaks, BitCloud, chipKIT, chipKIT logo,
CryptoMemory, CryptoRF, dsPIC, FlashFlex, flexPWR, Heldo,
JukeBlox, KeeLoq, Kleer, LANCheck, LINK MD, maXStylus,
maXTouch, MediaLB, megaAVR, MOST, MOST logo, MPLAB,
OptoLyzer, PIC, picoPower, PICSTART, PIC32 logo, Prochip
Designer, QTouch, SAM-BA, SpyNIC, SST, SST Logo,
SuperFlash, tinyAVR, UNI/O, and XMEGA are registered
trademarks of Microchip Technology Incorporated in the U.S.A.
and other countries.
ClockWorks, The Embedded Control Solutions Company,
EtherSynch, Hyper Speed Control, HyperLight Load, IntelliMOS,
mTouch, Precision Edge, and Quiet-Wire are registered
trademarks of Microchip Technology Incorporated in the U.S.A.
Adjacent Key Suppression, AKS, Analog-for-the-Digital Age, Any
Capacitor, AnyIn, AnyOut, BodyCom, CodeGuard,
CryptoAuthentication, CryptoAutomotive, CryptoCompanion,
CryptoController, dsPICDEM, dsPICDEM.net, Dynamic Average
Matching, DAM, ECAN, EtherGREEN, In-Circuit Serial
Programming, ICSP, INICnet, Inter-Chip Connectivity,
JitterBlocker, KleerNet, KleerNet logo, memBrain, Mindi, MiWi,
motorBench, MPASM, MPF, MPLAB Certified logo, MPLIB,
MPLINK, MultiTRAK, NetDetach, Omniscient Code Generation,
PICDEM, PICDEM.net, PICkit, PICtail, PowerSmart, PureSilicon,
QMatrix, REAL ICE, Ripple Blocker, SAM-ICE, Serial Quad I/O,
SMART-I.S., SQI, SuperSwitcher, SuperSwitcher II, Total
Endurance, TSHARC, USBCheck, VariSense, ViewSpan,
WiperLock, Wireless DNA, and ZENA are trademarks of
Microchip Technology Incorporated in the U.S.A. and other
countries.
Silicon Storage Technology is a registered trademark of Microchip
Technology Inc. in other countries.
GestIC is a registered trademark of Microchip Technology
Germany II GmbH & Co. KG, a subsidiary of Microchip
Technology Inc., in other countries.
All other trademarks mentioned herein are property of their
respective companies.
© 2019, Microchip Technology Incorporated, All Rights Reserved.
ISBN: 978-1-5224-4195-3
== ISO/TS 16949 ==
2019 Microchip Technology Inc.
DS20006162A-page 59
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