MCP6H84T-E/STVAO

MCP6H81/2/4 5.5 MHz, 12V Op Amps Features: Description: • • • • • • Microchip’s MCP6H81/2/4 family of operational amplifiers (op amps) has a wide supply voltage range of 3.5V to 12V and rail-to-rail output operation. This family is unity gain stable and has a gain bandwidth product of 5.5 MHz (typical). These devices operate with a single-supply voltage as high as 12V, while only drawing 0.7 mA/amplifier (typical) of quiescent current. • • • • • Input Offset Voltage: ±1 mV (typical) Quiescent Current: 0.7 mA (typical) Common Mode Rejection Ratio: 100 dB (typical) Power Supply Rejection Ratio: 102 dB (typical) Rail-to-Rail Output Supply Voltage Range: - Single-Supply Operation: 3.5V to 12V - Dual-Supply Operation: ±1.75V to ±6V Gain Bandwidth Product: 5.5 MHz (typical) Slew Rate: 5 V/µs (typical) Unity Gain Stable Extended Temperature Range: -40°C to +125°C No Phase Reversal The MCP6H81/2/4 family is offered in single (MCP6H81), dual (MCP6H82) and quad (MCP6H84) configurations. All devices are fully specified in extended temperature range from -40°C to +125°C. Package Types MCP6H81 SOIC Applications: • • • • Automotive Power Electronics Industrial Control Equipment Battery Powered Systems Sensor Conditioning NC 1 8 NC VOUTA 1 8 VDD VIN– 2 7 VDD VINA– 2 7 VOUTB VIN+ 3 6 VOUT 5 NC VINA+ 3 6 VINB– 5 VINB+ VSS 4 VSS 4 MCP6H82 2x3 TDFN MCP6H81 2x3 TDFN Design Aids: • • • • • MCP6H82 SOIC SPICE Macro Models FilterLab® Software MAPS (Microchip Advanced Part Selector) Analog Demonstration and Evaluation Boards Application Notes NC 1 VIN– 2 VIN+ 3 VSS 4 EP 9 8 NC VOUTA 1 7 VDD VINA– 2 6 VOUT VINA+ 3 5 NC 8 VDD EP 9 VSS 4 7 VOUTB 6 VINB– 5 VINB+ MCP6H84 SOIC, TSSOP Typical Application R1 R2 V1 VREF VDD MCP6H81 VOUT VOUTA 1 14 VOUTD VINA– 2 13 VIND– VINA+ 3 VDD 4 12 VIND+ 11 VSS VINB+ 5 10 VINC+ VINB– 6 9 VINC– 8 VOUTC VOUTB 7 V2 * Includes Exposed Thermal Pad (EP); see Table 3-1. R1 R2 Difference Amplifier  2012 Microchip Technology Inc. DS22320B-page 1 MCP6H81/2/4 NOTES: DS22320B-page 2  2012 Microchip Technology Inc. MCP6H81/2/4 1.0 ELECTRICAL CHARACTERISTICS 1.1 Absolute Maximum Ratings † † Notice: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. †† See Section 4.1.2, Input Voltage Limits. VDD – VSS.......................................................................13.2V Current at Input Pins......................................................±2 mA Analog Inputs (VIN+, VIN-)††.............VSS – 1.0V to VDD + 1.0V All Other Inputs and Outputs ............VSS – 0.3V to VDD + 0.3V Difference Input Voltage..........................................VDD – VSS Output Short-Circuit Current...................................continuous Current at Output and Supply Pins ..............................±65 mA Storage Temperature.....................................-65°C to +150°C Maximum Junction Temperature (TJ)...........................+150°C ESD protection on all pins (HBM; MM) 2 kV; 200V DC ELECTRICAL SPECIFICATIONS Electrical Characteristics: Unless otherwise indicated, VDD = +3.5V to +12V, VSS = GND, TA = +25°C, VCM = VDD/2 - 1.4V, VOUT  VDD/2, VL = VDD/2 and RL = 10 kto VL. (Refer to Figure 1-1). Parameters Sym Min Typ Max Units Conditions Input Offset Input Offset Voltage Input Offset Drift with Temperature Power Supply Rejection Ratio VOS -4 ±1 4 VOS/TA — ±2.5 — PSRR 82 102 — IB — 10 — pA — 400 — pA TA = +85°C TA = +125°C mV µV/°C TA = -40°C to +125°C dB Input Bias Current and Impedance Input Bias Current — 9 25 nA Input Offset Current IOS — ±1 — pA Common Mode Input Impedance ZCM — 1013||6 — ||pF ZDIFF — 1013||6 — ||pF Common Mode Input Voltage Range VCMR VSS – 0.3 — VDD – 2.5 V Common Mode Rejection Ratio CMRR 76 95 — dB VCM = -0.3V to 1.0V, VDD = 3.5V 80 97 — dB VCM = -0.3V to 2.5V, VDD = 5V 80 100 — dB VCM = -0.3V to 9.5V, VDD = 12V 100 120 — dB 0.2V < VOUT 2 mA Simplified Analog Input ESD The input ESD diodes clamp the inputs when they try to go more than one diode drop below VSS. They also clamp any voltages that go well above VDD. Their breakdown voltage is high enough to allow normal operation, but not low enough to protect against slow overvoltage (beyond VDD) events. Very fast ESD events (that meet the specification) are limited so that damage does not occur. In some applications, it may be necessary to prevent excessive voltages from reaching the op amp inputs; Figure 4-2 shows one approach to protecting these inputs. R1 > FIGURE 4-3: Inputs. 4.1.4 Protecting the Analog NORMAL OPERATION The inputs of the MCP6H81/2/4 op amps connect to a differential PMOS input stage. It operates at a low common mode input voltage (VCM), including ground. With this topology, the device operates with a VCM up to VDD – 2.5V and 0.3V below VSS (refer to Figures 2-3 through 2-5). The input offset voltage is measured at VCM = VSS – 0.3V and VDD – 2.5V to ensure proper operation. For a unity gain buffer, VIN must be maintained below VDD – 2.5V for correct operation.  2012 Microchip Technology Inc. DS22320B-page 17 MCP6H81/2/4 Rail-to-Rail Output 1000 The output voltage range of the MCP6H81/2/4 op amps is 0.020V (typical) and 11.980V (typical) when RL = 10 k is connected to VDD/2 and VDD = 12V. Refer to Figures 2-24 through 2-29 for more information. 4.3 Capacitive Loads Driving large capacitive loads can cause stability problems for voltage feedback op amps. As the load capacitance increases, the feedback loop’s phase margin decreases, and the closed-loop bandwidth is reduced. This produces gain peaking in the frequency response, with overshoot and ringing in the step response. While a unity-gain buffer (G = +1V/V) is the most sensitive to capacitive loads, all gains show the same general behavior. When driving large capacitive loads with these op amps (e.g., > 100 pF when G = + 1V/V), a small series resistor at the output (RISO in Figure 4-4) improves the feedback loop’s phase margin (stability) by making the output load resistive at higher frequencies. The bandwidth will generally be lower than the bandwidth with no capacitance load. Reco ommended R ISO (:) 4.2 VDD = 12 V RL = 10 k 100 1 10p 100p 1n 10n 0.1μ 1.E-06 1μ 1.E-11 1.E-10 1.E-09 1.E-08 1.E-07 Normalized Load Capacitance; CL/GN (F) FIGURE 4-5: Recommended RISO Values for Capacitive Loads. 4.4 Supply Bypass With this family of operational amplifiers, the power supply pin (VDD for single supply) should have a local bypass capacitor (i.e., 0.01 µF to 0.1 µF) within 2 mm for good high-frequency performance. It can use a bulk capacitor (i.e., 1 µF or larger) within 100 mm to provide large, slow currents. This bulk capacitor can be shared with other analog parts. 4.5 – VIN MCP6H8X + RISO VOUT CL FIGURE 4-4: Output Resistor, RISO Stabilizes Large Capacitive Loads. Figure 4-5 gives the recommended RISO values for different capacitive loads and gains. The x-axis is the normalized load capacitance (CL/GN), where GN is the circuit’s noise gain. For non-inverting gains, GN and the Signal Gain are equal. For inverting gains, GN is 1 + |Signal Gain| (e.g., -1V/V gives GN = +2V/V). After selecting RISO for your circuit, double check the resulting frequency response peaking and step response overshoot. Modify RISO’s value until the response is reasonable. Bench evaluation and simulations with the MCP6H81/2/4 SPICE macro model are helpful. GN: 1 V/V 2 V/V t 5 V/V 10 Unused Op Amps An unused op amp in a quad package (MCP6H84) should be configured as shown in Figure 4-6. These circuits prevent the output from toggling and causing crosstalk. Circuit A sets the op amp at its minimum noise gain. The resistor divider produces any desired reference voltage within the output voltage range of the op amp, and the op amp buffers that reference voltage. Circuit B uses the minimum number of components and operates as a comparator, but it may draw more current. ¼ MCP6H84 (A) ¼ MCP6H84 (B) VDD R1 VDD VDD R2 VREF R2 V REF = VDD  -------------------R1 + R2 FIGURE 4-6: DS22320B-page 18 Unused Op Amps.  2012 Microchip Technology Inc. MCP6H81/2/4 4.6 PCB Surface Leakage 4.7 In applications where low input bias current is critical, PCB surface leakage effects need to be considered. Surface leakage is caused by humidity, dust or other contamination on the board. Under low-humidity conditions, a typical resistance between nearby traces is 1012. A 15V difference would cause 15 pA of current to flow, which is greater than the MCP6H81/2/4 family’s bias current at +25°C (10 pA, typical). The easiest way to reduce surface leakage is to use a guard ring around sensitive pins (or traces). The guard ring is biased at the same voltage as the sensitive pin. An example of this type of layout is shown in Figure 4-7. Guard Ring VIN– VIN+ VSS 4.7.1 Application Circuits DIFFERENCE AMPLIFIER The MCP6H81/2/4 op amps can be used in current sensing applications. Figure 4-8 shows a resistor (RSEN) that converts the sensor current (ISEN) to voltage, as well as a difference amplifier that amplifies the voltage across the resistor while rejecting common mode noise. R1 and R2 must be well matched to obtain an acceptable Common Mode Rejection Ratio (CMRR). Moreover, RSEN should be much smaller than R1 and R2 in order to minimize the resistive loading of the source. To ensure proper operation, the op amp common mode input voltage must be kept within the allowed range. The reference voltage (VREF) is supplied by a low-impedance source. In single-supply applications, VREF is typically VDD/2. . R1 R2 VREF VDD FIGURE 4-7: for Inverting Gain. 1. 2. Example Guard Ring Layout Non-Inverting Gain and Unity-Gain Buffer: a.Connect the non-inverting pin (VIN+) to the input with a wire that does not touch the PCB surface. b.Connect the guard ring to the inverting input pin (VIN–). This biases the guard ring to the Common mode input voltage. Inverting Gain and Transimpedance Gain Amplifiers (convert current to voltage, such as photo detectors): a.Connect the guard ring to the non-inverting input pin (VIN+). This biases the guard ring to the same reference voltage as the op amp (e.g., VDD/2 or ground). b.Connect the inverting pin (VIN–) to the input with a wire that does not touch the PCB surface.  2012 Microchip Technology Inc. RSEN VOUT ISEN MCP6H81 R1 R2 RSEN