MCP6L71/1R/2/4
2 MHz, 150 µA Op Amps
Features
Description
•
•
•
•
•
•
The Microchip Technology Inc. MCP6L71/1R/2/4 family
of operational amplifiers (op amps) supports general
purpose applications. The combination of rail-to-rail
input and output, low quiescent current and bandwidth
fit into many applications.
Gain Bandwidth Product: 2 MHz (typical)
Supply Current: IQ = 150 µA (typical)
Supply Voltage: 2.0V to 6.0V
Rail-to-Rail Input/Output
Extended Temperature Range: -40°C to +125°C
Available in Single, Dual and Quad Packages
Typical Applications
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•
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Portable Equipment
Photodiode Amplifier
Analog Filters
Notebooks and PDAs
Battery-Powered Systems
This family has a 2 MHz Gain Bandwidth Product
(GBWP) and a low 150 µA per amplifier quiescent
current. These op amps operate on supply voltages
between 2.0V and 6.0V, with rail-to-rail input and output
swing. They are available in the extended temperature
range.
Package Types
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•
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FilterLab® Software
MAPS (Microchip Advanced Part Selector)
Analog Demonstration and Evaluation Boards
Application Notes
R1
R3
VREF
VOUT 1
5 VDD
VOUT 1
4 VIN-
VIN+ 3
R2
VOUT
–
+
MCP6L71
Inverting Amplifier
4 VIN-
MCP6L72
SOIC, MSOP
NC 1
8 NC
VOUTA 1
VIN- 2
7 VDD
VINA- 2
8 VDD
7 VOUTB
VIN+ 3
6 VOUT VINA+ 3
VSS 4
5 NC
6 VINB5 VINB+
VSS 4
MCP6L74
SOIC, TSSOP
VOUTA 1
14 VOUTD
VINA- 2
13 VIND-
VINA+ 3
12 VIND+
VDD 4
2009-2019 Microchip Technology Inc.
5 VSS
VDD 2
VSS 2
VIN+ 3
MCP6L71
SOIC, MSOP
Typical Application
VIN
MCP6L71R
SOT-23-5
MCP6L71
SOT-23-5
Design Aids
11 VSS
VINB+ 5
10 VINC+
VINB- 6
9 VINC-
VOUTB 7
8 VOUTC
DS20002145B-page 1
MCP6L71/1R/2/4
NOTES:
DS20002145B-page 2
2009-2019 Microchip Technology Inc.
MCP6L71/1R/2/4
1.0
ELECTRICAL CHARACTERISTICS
1.1
Absolute Maximum Ratings†
All Other Inputs and Outputs ......... VSS – 0.3V to VDD + 0.3V
† Notice: Stresses above those listed under “Absolute
Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of
the device at those or any other conditions above those
indicated in the operational listings of this specification is not
implied. Exposure to maximum rating conditions for extended
periods may affect device reliability.
Difference Input Voltage ...................................... |VDD – VSS|
†† See Section 4.1.2 “Input Voltage and Current Limits”.
VDD – VSS ........................................................................7.0V
Current at Input Pins ....................................................±2 mA
Analog Inputs (VIN+ and VIN-)†† ...... VSS – 1.0V to VDD + 1.0V
Output Short-Circuit Current ................................ Continuous
Current at Output and Supply Pins ............................±30 mA
Storage Temperature ....................................-65°C to +150°C
Junction Temperature (TJ) .........................................+150°C
ESD Protection on All Pins (HBM/MM) 4 kV/400V
1.2
Specifications
TABLE 1-1:
DC ELECTRICAL SPECIFICATIONS
Electrical Characteristics: Unless otherwise indicated, TA = +25°C, VDD = 5.0V, VSS = GND, VCM = VDD/2,
VOUT VDD/2, VL = VDD/2 and RL = 10 kto VL. (Refer to Figure 1-1.)
Parameters
Sym
Min(1)
Typ
Max(1)
Units
Conditions
Input Offset
VOS
–4
±1
+4
Input Offset Temperature Drift
Input Offset Voltage
VOS/TA
—
±1.3
—
Power Supply Rejection Ratio
PSRR
—
89
—
mV
µV/°C TA = -40°C to +125°C
dB
Input Bias Current and Impedance
Input Bias Current
IB
—
1
—
pA
IB
—
50
—
pA
TA = +85°C
TA = +125°C
IB
—
2000
—
pA
Input Offset Current
IOS
—
±1
—
pA
Common-mode Input Impedance
ZCM
—
1013||6
—
||pF
Differential Input Impedance
ZDIFF
—
1013||3
—
||pF
Common-mode Input Voltage
Range
VCMR
-0.3
—
+5.3
V
Common-mode Rejection Ratio
CMRR
—
91
—
dB
VCM = -0.3V to 5.3V
AOL
—
105
—
dB
VOUT = 0.2V to 4.8V,
VCM = VSS
VOL
—
—
0.020
V
G = +2 V/V,
0.5V input overdrive
VOH
4.980
—
—
V
G = +2 V/V,
0.5V input overdrive
ISC
—
±25
—
mA
Common-mode
Open-Loop Gain
DC Open-Loop Gain (large signal)
Output
Maximum Output Voltage Swing
Output Short-Circuit Current
Note 1:
For design guidance only; not tested.
2009-2019 Microchip Technology Inc.
DS20002145B-page 3
MCP6L71/1R/2/4
TABLE 1-1:
DC ELECTRICAL SPECIFICATIONS (CONTINUED)
Electrical Characteristics: Unless otherwise indicated, TA = +25°C, VDD = 5.0V, VSS = GND, VCM = VDD/2,
VOUT VDD/2, VL = VDD/2 and RL = 10 kto VL. (Refer to Figure 1-1.)
Parameters
Sym
Min(1)
Typ
Max(1)
Units
VDD
2.0
—
6.0
V
IQ
50
150
240
µA
Conditions
Power Supply
Supply Voltage
Quiescent Current per Amplifier
Note 1:
IO = 0
For design guidance only; not tested.
TABLE 1-2:
AC ELECTRICAL SPECIFICATIONS
Electrical Characteristics: Unless otherwise indicated, TA = +25°C, VDD = +2.0V to +5.5V, VSS = GND,
VCM = VDD/2, VOUT VDD/2, VL = VDD/2, RL = 10 kto VL and CL = 60 pF. (Refer to Figure 1-1.)
Parameters
Sym
Min
Typ
Max
Units
Conditions
GBWP
—
2.0
—
MHz
Phase Margin
PM
—
65
—
°
Slew Rate
SR
—
0.9
—
V/µs
Input Noise Voltage
Eni
—
4.6
—
µVP-P
Input Noise Voltage Density
eni
—
19
—
nV/Hz
f = 10 kHz
ini
—
3
—
fA/Hz
f = 1 kHz
AC Response
Gain Bandwidth Product
G = +1 V/V
Noise
Input Noise Current Density
TABLE 1-3:
f = 0.1 Hz to 10 Hz
TEMPERATURE SPECIFICATIONS
Electrical Characteristics: Unless otherwise indicated, VDD = +2.0V to +5.5V and VSS = GND.
Parameters
Sym
Min
Typ
Max
Units
Specified Temperature Range
TA
-40
—
+125
°C
Operating Temperature Range
TA
-40
—
+125
°C
TA
-65
—
+150
°C
Conditions
Temperature Ranges
Storage Temperature Range
Note 1
Thermal Package Resistances
Thermal Resistance, 5-Lead SOT-23
JA
—
256
—
°C/W
Thermal Resistance, 8-Lead SOIC
JA
—
163
—
°C/W
Thermal Resistance, 8-Lead MSOP
JA
—
206
—
°C/W
Thermal Resistance, 14-Lead SOIC
JA
—
120
—
°C/W
Thermal Resistance, 14-Lead TSSOP
JA
—
100
—
°C/W
Note 1:
The Junction Temperature (TJ) must not exceed the absolute maximum specification of +150°C.
DS20002145B-page 4
2009-2019 Microchip Technology Inc.
MCP6L71/1R/2/4
1.3
Test Circuits
The circuit used for most DC and AC tests is shown in
Figure 1-1. This circuit can independently set VCM and
VOUT; see Equation 1-1. Note that VCM is not the
circuit’s Common-mode voltage ((VP + VM)/2), and that
VOST includes VOS plus the effects (on the input offset
error, VOST) of temperature, CMRR, PSRR and AOL.
CF
6.8 pF
RG
100 k
VP
VDD
VIN+
EQUATION 1-1:
G DM = R F R G
MCP6L7X
V CM = VP + VDD 2 2
CB1
100 nF
+
–
VDD/2
CB2
1 µF
VIN-
V OST = V IN– – V IN+
V OUT = V DD 2 + V P – V M + V OST 1 + G DM
Where:
GDM = Differential-mode Gain
(V/V)
VCM = Op Amp’s Common-mode
Input Voltage
(V)
VOST = Op Amp’s Total Input Offset
Voltage
(mV)
2009-2019 Microchip Technology Inc.
RF
100 k
VM
RG
100 k
RL
10 k
RF
100 k
CF
6.8 pF
VOUT
CL
60 pF
VL
FIGURE 1-1:
AC and DC Test Circuit for
Most Specifications.
DS20002145B-page 5
MCP6L71/1R/2/4
NOTES:
DS20002145B-page 6
2009-2019 Microchip Technology Inc.
MCP6L71/1R/2/4
2.0
TYPICAL PERFORMANCE CURVES
Note:
The graphs and tables provided following this note are a statistical summary based on a limited number of
samples and are provided for informational purposes only. The performance characteristics listed herein
are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified
operating range (e.g., outside specified power supply range) and therefore outside the warranted range.
Note: Unless otherwise indicated, TA = +25°C, VDD = 5.0V, VSS = GND, VCM = VDD/2, VOUT VDD/2, VL = VDD/2,
RL = 10 k to VL and CL = 60 pF.
250
VDD = 2.0V
Representitive Part
Common Mode Range (V)
Input Offset Voltage (µV)
300
200
150
100
TA = +125°C
TA = +85°C
TA = +25°C
TA = -40°C
50
0
-50
2.4
2.2
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
-0.2
-0.4
-100
0.5
0.4
0.3
0.2
0.1
0.0
-0.1
-0.2
-0.3
-0.4
-0.5
VCMRH – VDD
One Wafer Lot
VCMRL – VSS
-50
-25
Common Mode Input Voltage (V)
200
150
TA = +125°C
100
50
TA = +85°C
TA = +25°C
TA = -40°C
0
-50
110
100
CMRR (V CM = -0.3V to +5.3V)
90
PSRR
(VCM = VSS)
80
70
60
-50
6.0
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
-0.5
-100
-25
Input Offset Voltage (µV)
300
VCM = VSS
Representative Part
250
200
150
100
50
VDD = 2.0V
VDD = 5.5V
-50
FIGURE 2-5:
Temperature.
25
50
75
100
125
CMRR, PSRR vs.
110
100
CMRR, PSRR (dB)
FIGURE 2-2:
Input Offset Voltage vs.
Common-mode Input Voltage at VDD = 5.5V.
0
Ambient Temperature (°C)
Common Mode Input Voltage (V)
0
125
120
VDD = 5.5V
Representitive Part
PSRR, CMRR (dB)
Input Offset Voltage (µV)
250
100
FIGURE 2-4:
Input Common-mode Range
Voltage vs. Ambient Temperature.
FIGURE 2-1:
Input Offset Voltage vs.
Common-mode Input Voltage at VDD = 2.0V.
300
0
25
50
75
Ambient Temperature (°C)
CMRR
90
80
70
60
50
PSRR–
PSRR+
40
30
-100
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Output Voltage (V)
FIGURE 2-3:
Output Voltage.
Input Offset Voltage vs.
2009-2019 Microchip Technology Inc.
20
1
10 1.E+02
100 1.E+03
1k
10k 1.E+05
100k 1.E+06
1M
1.E+00
1.E+01
1.E+04
Frequency (Hz)
FIGURE 2-6:
Frequency.
CMRR, PSRR vs.
DS20002145B-page 7
MCP6L71/1R/2/4
Note: Unless otherwise indicated, TA = +25°C, VDD = 5.0V, VSS = GND, VCM = VDD/2, VOUT VDD/2, VL = VDD/2,
RL = 10 k to VL and CL = 60 pF.
1.E-02
10m
1.E-03
1m
1.E-04
100µ
10µ
1.E-05
1µ
1.E-06
100n
1.E-07
10n
1.E-08
1n
1.E-09
100p
1.E-10
10p
1.E-11
1p
1.E-12
Input, Output Voltage (V)
Input Current Magnitude (A)
6
+125°C
+85°C
+25°C
-40°C
-1.0 -0.9 -0.8 -0.7 -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0.0
VDD = 5.0V
G = +2 V/V
5
4
3
2
VIN
1
VOUT
0
-1
Input Voltage (V)
Input Current vs. Input
0
100
-30
80
-60
Phase
60
40
-90
-120
Gain
20
-150
0
-180
FIGURE 2-8:
Frequency.
1k 10k 100k 1M 10M
Frequency (Hz)
Open-Loop Gain, Phase vs.
50
FIGURE 2-11:
Supply Voltage.
10
0.1
1
10
100
1k
10k 100k 1M
1.E- 1.E+0 1.E+0 1.E+0 1.E+0 1.E+0 1.E+0 1.E+0
01
0
1 Frequency
2
3(Hz) 4
5
6
Input Noise Voltage Density
Ouptut Short-Circuit Current
(mA)
Input Noise Voltage Density
(nV/ Hz)
TA = +125°C
TA = +85°C
TA = +25°C
TA = -40°C
100
Quiescent Current vs.
35
100
DS20002145B-page 8
150
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Power Supply Voltage (V)
1,000
FIGURE 2-9:
vs. Frequency.
200
0
1.E+07
1.E+06
1.E+05
1.E+04
100
1.E+03
10
1.E+02
1
1.E+01
0.1
1.E+00
-210
1.E-01
-20
250
Quiescent Current
(µA/amplifier)
120
FIGURE 2-10:
The MCP6L71/1R/2/4 Show
No Phase Reversal.
Open-Loop Phase (°)
Open-Loop Gain (dB)
FIGURE 2-7:
Voltage.
Time (1 ms/div)
30
25
20
15
10
5
TA = +125°C
TA = +85°C
TA = +25°C
TA = -40°C
0
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Power Supply Voltage (V)
FIGURE 2-12:
Output Short-Circuit Current
vs. Supply Voltage.
2009-2019 Microchip Technology Inc.
MCP6L71/1R/2/4
50
45
40
35
30
25
20
15
10
5
0
1.8
1.6
VOL – VSS
-IOUT
Slew Rate (V/µs)
VDD – VOH
IOUT
Falling Edge
1.2
1.0
0.8
VDD = 2.0V
0.6
Rising Edge
0.4
0.2
0.0
1
Output Current Magnitude (mA)
10
FIGURE 2-13:
Ratio of Output Voltage
Headroom vs. Output Current Magnitude.
-50
0
25
50
75
Ambient Temperature (°C)
FIGURE 2-16:
Temperature.
5.0
100
125
Slew Rate vs. Ambient
4.0
3.5
3.0
2.5
2.0
1.5
1.0
Maximum Output Voltage
Swing (V P-P)
10
G = +1 V/V
VDD = 5.0V
4.5
VDD = 5.5V
VDD = 2.0V
1
Time (5 µs/div)
Large-Signal Noninverting
10k
100k
1M
Frequency (Hz)
1.E+07
1.E+03
1k
0.0
1.E+06
0.1
0.5
FIGURE 2-14:
Pulse Response.
-25
1.E+05
0.1
Output Voltage (V)
V DD = 5.5V
1.4
1.E+04
Ratio of Output Headroom to
Output Current (mV/mA)
Note: Unless otherwise indicated, TA = +25°C, VDD = 5.0V, VSS = GND, VCM = VDD/2, VOUT VDD/2, VL = VDD/2,
RL = 10 k to VL and CL = 60 pF.
10M
FIGURE 2-17:
Maximum Output Voltage
Swing vs. Frequency.
Output Voltage (10 mV/div)
G = +1 V/V
Time (2 µs/div)
FIGURE 2-15:
Pulse Response.
Small-Signal Noninverting
2009-2019 Microchip Technology Inc.
DS20002145B-page 9
MCP6L71/1R/2/4
NOTES:
DS20002145B-page 10
2009-2019 Microchip Technology Inc.
MCP6L71/1R/2/4
3.0
PIN DESCRIPTIONS
Descriptions of the pins are listed in Table 3-1 (single op amps) and Table 3-2 (dual and quad op amps).
TABLE 3-1:
PIN FUNCTION TABLE FOR SINGLE OP AMPS
MCP6L71
MSOP, SOIC
MCP6L71R
SOT-23
SOT-23
Symbol
Description
2
4
4
VIN-
Inverting Input
3
3
3
VIN+
Noninverting Input
4
2
5
VSS
Negative Power Supply
6
1
1
VOUT
Analog Output
7
5
2
VDD
Positive Power Supply
1,5,8
—
—
NC
No Internal Connection
TABLE 3-2:
PIN FUNCTION TABLE FOR DUAL AND QUAD OP AMPS
MCP6L72
MCP6L74
MSOP, SOIC
SOIC,
TSSOP
Symbol
1
1
VOUTA
Analog Output (Op Amp A)
2
2
VINA-
Inverting Input (Op Amp A)
3
3
VINA+
Noninverting Input (Op Amp A)
8
4
VDD
Description
Positive Power Supply
5
5
VINB+
Noninverting Input (Op Amp B)
6
6
VINB-
Inverting Input (Op Amp B)
7
7
VOUTB
Analog Output (Op Amp B)
—
8
VOUTC
Analog Output (Op Amp C)
—
9
VINC-
Inverting Input (Op Amp C)
—
10
VINC+
Noninverting Input (Op Amp C)
4
11
VSS
—
12
VIND+
—
13
VIND-
Inverting Input (Op Amp D)
—
14
VOUTD
Analog Output (Op Amp D)
2009-2019 Microchip Technology Inc.
Negative Power Supply
Noninverting Input (Op Amp D)
DS20002145B-page 11
MCP6L71/1R/2/4
3.1
Analog Outputs
The output pins are low-impedance voltage sources.
3.2
Analog Inputs
The noninverting and inverting inputs are
high-impedance CMOS inputs with low bias currents.
DS20002145B-page 12
3.3
Power Supply Pins
The positive power supply (VDD) is 2.0V to 6.0V higher
than the negative power supply (VSS). For normal
operation, the other pins are at voltages between VSS
and VDD.
Typically, these parts are used in a single (positive)
supply configuration. In this case, VSS is connected to
ground and VDD is connected to the supply. VDD will
need bypass capacitors.
2009-2019 Microchip Technology Inc.
MCP6L71/1R/2/4
4.0
APPLICATION INFORMATION
4.1.3
NORMAL OPERATIONS
The MCP6L71/1R/2/4 family of op amps is manufactured
using Microchip’s state-of-the-art CMOS process, specifically designed for low-cost, low-power and general
purpose applications. The low supply voltage, low
quiescent current and wide bandwidth make the
MCP6L71/1R/2/4 ideal for battery-powered applications.
The input stage of the MCP6L71/1R/2/4 op amps uses
two differential CMOS input stages in parallel. One
operates at low Common-mode input voltage (VCM),
while the other at high VCM. With this topology, and at
room temperature, the device operates with VCM up to
0.3V above VDD and 0.3V below VSS (typically at +25°C).
4.1
The transition between the two input stages occurs
when VCM = VDD – 1.1V. For the best distortion and
gain linearity, with noninverting gains, avoid this region
of operation.
4.1.1
Rail-to-Rail Inputs
PHASE REVERSAL
The MCP6L71/1R/2/4 op amps are designed to prevent phase inversion when the input pins exceed the
supply voltages. Figure 2-10 shows an input voltage
exceeding both supplies without any phase reversal.
4.1.2
INPUT VOLTAGE AND CURRENT
LIMITS
In order to prevent damage and/or improper operation
of these amplifiers, the circuit they are in must limit
the currents (and voltages) at the input pins (see
Section 1.1 “Absolute Maximum Ratings†”).
Figure 4-1 shows the recommended approach to protecting these inputs. The internal ESD diodes prevent
the input pins (VIN+ and VIN-) from going too far below
ground, and the resistors, R1 and R2, limit the possible
current drawn out of the input pins. Diodes, D1 and D2,
prevent the input pins (VIN+ and VIN-) from going too far
above VDD, and dump any currents onto VDD.
VDD
D1
V1
+
R1
V2
D2
MCP6L7X
VOUT
4.2
Rail-to-Rail Output
The output voltage range of the MCP6L71/1R/2/4
op amps is VDD – 20 mV (minimum), and VSS + 20 mV
(maximum) when RL = 10 k is connected to VDD/2 and
VDD = 5.0V. Refer to Figure 2-13 for more information.
4.3
Capacitive Loads
Driving large capacitive loads can cause stability
problems for voltage feedback op amps. As the load
capacitance increases, the feedback loop’s phase
margin decreases and the closed-loop bandwidth is
reduced. This produces gain peaking in the frequency
response, with overshoot and ringing in the step
response.
When driving large capacitive loads with these
op amps (e.g., > 100 pF when G = +1), a small series
resistor at the output (RISO in Figure 4-2) improves the
feedback loop’s phase margin (stability) by making the
output load resistive at higher frequencies. The
bandwidth will be generally lower than the bandwidth
with no capacitive load.
RG
–
R2
RN
R3
VSS – (minimum expected V1)
2 mA
VSS – (minimum expected V2)
R2 >
2 mA
R1 >
Protecting the Analog
RISO
VOUT
–
FIGURE 4-1:
Inputs.
RF
CL
MCP6L7X
+
FIGURE 4-2:
Output Resistor, RISO
Stabilizes Large Capacitive Loads.
Bench measurements are helpful in choosing RISO.
Adjust RISO so that a small-signal step response (see
Figure 2-15) has reasonable overshoot (e.g., 4%).
A significant amount of current can flow out of the
inputs (through the ESD diodes) when the
Common-mode voltage (VCM) is below ground (VSS);
see Figure 2-7. Applications that are high-impedance
may need to limit the usable voltage range.
2009-2019 Microchip Technology Inc.
DS20002145B-page 13
MCP6L71/1R/2/4
4.4
Supply Bypass
Guard Ring
With this family of operational amplifiers, the power
supply pin (VDD for single supply) should have a local
bypass capacitor (i.e., 0.01 µF to 0.1 µF) within 2 mm
for good, high-frequency performance. It also needs a
bulk capacitor (i.e., 1 µF or larger) within 100 mm to
provide large, slow currents. This bulk capacitor can be
shared with nearby analog parts.
4.5
Unused Amplifiers
FIGURE 4-4:
An unused op amp in a quad package (MCP6L74)
should be configured as shown in Figure 4-3. These
circuits prevent the output from toggling and causing
crosstalk. In Circuit A, R1 and R2 produce a voltage
within its output voltage range (VOH, VOL). The op amp
buffers this voltage, which can be used elsewhere in
the circuit. Circuit B uses the minimum number of
components and operates as a comparator.
¼ MCP6L74 (A)
¼ MCP6L74 (B)
VDD
VDD
2.
VDD
R1
+
+
R2
1.
VREF
–
–
FIGURE 4-3:
4.6
Unused Op Amps.
PCB Surface Leakage
In applications where low input bias current is critical,
Printed Circuit Board (PCB) surface leakage effects
need to be considered. Surface leakage is caused by
humidity, dust or other contamination on the board.
Under low humidity conditions, a typical resistance
between nearby traces is 1012. A 5V difference would
cause 5 pA of current to flow. This is greater than the
MCP6L71/1R/2/4 family’s bias current at +25°C (1 pA,
typical).
VIN+
Example Guard Ring Layout.
For Inverting Gain and Transimpedance Amplifiers
(convert current to voltage, such as photo
detectors):
a) Connect the guard ring to the noninverting
input pin (VIN+). This biases the guard ring
to the same reference voltage as the
op amp (e.g., VDD/2 or ground).
b) Connect the inverting pin (VIN-) to the input
with a wire that does not touch the PCB
surface.
Noninverting Gain and Unity Gain Buffer:
a) Connect the guard ring to the inverting input
pin (VIN-). This biases the guard ring to the
Common-mode input voltage.
b) Connect the noninverting pin (VIN+) to the
input with a wire that does not touch the
PCB surface.
4.7
R2
V REF = VDD -----------------R1 + R 2
VIN-
Application Circuits
4.7.1
INVERTING INTEGRATOR
An inverting integrator is shown in Figure 4-5. The
circuit provides an output voltage that is proportional to
the negative time integral of the input. The additional
resistor R2 limits DC gain and controls output clipping.
To minimize the integrator’s error for slow signals, the
value of R2 should be much larger than the value of R1.
+
MCP6L71
_
VIN
The easiest way to reduce surface leakage is to use a
guard ring around sensitive pins (or traces). The guard
ring is biased at the same voltage as the sensitive pin.
Figure 4-4 shows an example of this type of layout.
VOUT
C1
R1
R2
t
1
V OUT = – ------------- VIN dt
R1 C1 0
R2 » R 1
FIGURE 4-5:
DS20002145B-page 14
Inverting Integrator.
2009-2019 Microchip Technology Inc.
MCP6L71/1R/2/4
5.0
DESIGN TOOLS
Microchip provides the basic design tools needed for
the MCP6L71/1R/2/4 family of op amps.
5.1
FilterLab® Software
Microchip’s FilterLab® software is an innovative software
tool that simplifies analog active filter (using op amps)
design. Available at no cost from the Microchip website
at www.microchip.com/filterlab, the FilterLab design tool
provides full schematic diagrams of the filter circuit with
component values. It also outputs the filter circuit in
SPICE format, which can be used with the macro model
to simulate actual filter performance.
5.2
MAPS (Microchip Advanced Part
Selector)
5.4
Application Notes
The following Microchip Application Notes are available
on the Microchip website at www.microchip.com/
appnotes and are recommended as supplemental
reference resources.
• ADN003: “Select the Right Operational Amplifier
for your Filtering Circuits”, DS21821
• AN722: “Operational Amplifier Topologies and DC
Specifications”, DS00722
• AN723: “Operational Amplifier AC Specifications
and Applications”, DS00723
• AN884: “Driving Capacitive Loads With Op Amps”,
DS00884
• AN990: “Analog Sensor Conditioning
Circuits – An Overview”, DS00990
MAPS is a software tool that helps efficiently identify
Microchip devices that fit a particular design requirement. Available at no cost from the Microchip website
at www.microchip.com/maps, the MAPS is an overall
selection tool for Microchip’s product portfolio that
includes Analog, Memory, MCUs and DSCs. Using this
tool you can define a filter to sort features for a
parametric search of devices and export side-by-side
technical comparison reports. Helpful links are also
provided for data sheets, purchase and sampling of
Microchip parts.
5.3
Analog Demonstration and
Evaluation Boards
Microchip offers a broad spectrum of Analog Demonstration and Evaluation Boards that are designed to help you
achieve faster time to market. For a complete listing of
these boards, and their corresponding user’s guides and
technical information, visit the Microchip website at
www.microchip.com/analogtools.
Some boards that are especially useful are:
•
•
•
•
•
•
•
MCP6XXX Amplifier Evaluation Board 1
MCP6XXX Amplifier Evaluation Board 2
MCP6XXX Amplifier Evaluation Board 3
MCP6XXX Amplifier Evaluation Board 4
Active Filter Demo Board Kit
5/6-Pin SOT-23 Evaluation Board, P/N VSUPEV2
8-Pin SOIC/MSOP/TSSOP/DIP Evaluation Board,
P/N SOIC8EV
• 14-Pin SOIC/TSSOP/DIP Evaluation Board,
P/N SOIC14EV
2009-2019 Microchip Technology Inc.
DS20002145B-page 15
MCP6L71/1R/2/4
NOTES:
DS20002145B-page 16
2009-2019 Microchip Technology Inc.
MCP6L71/1R/2/4
6.0
PACKAGING INFORMATION
6.1
Package Marking Information
5-Lead SOT-23 (MCP6L71, MCP6L71R)
Device
XXNN
Example
Code
MCP6L71
WGNN
MCP6L71R
WFNN
WG25
Note: Applies to 5-Lead SOT-23.
8-Lead MSOP (MCP6L71, MCP6L72)
XXXXXX
YWWNNN
6L72E
911256
8-Lead SOIC (3.90 mm) (MCP6L71, MCP6L72)
XXXXXXXX
Example
MCP6L72E
XXXXYYWW
SN
NNN
e3
1911
256
Legend: XX...X
Y
YY
WW
NNN
e3
*
Note:
Example
Customer-specific information
Year code (last digit of calendar year)
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code
Pb-free JEDEC designator for Matte Tin (Sn)
This package is Pb-free. The Pb-free JEDEC designator ( e3 )
can be found on the outer packaging for this package.
In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
2009-2019 Microchip Technology Inc.
DS20002145B-page 17
MCP6L71/1R/2/4
Package Marking Information (Continued)
14-Lead SOIC (3.90 mm) (MCP6L74)
XXXXXXXXXXX
XXXXXXXXXXX
YYWWNNN
14-Lead TSSOP (4.4 mm) (MCP6L74)
XXXXXXXX
YYWW
NNN
DS20002145B-page 18
Example
MCP6L74
E/SL e3
1911256
Example
6L74EST
1911
256
2009-2019 Microchip Technology Inc.
MCP6L71/1R/2/4
5-Lead Plastic Small Outline Transistor (OT) [SOT23]
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
0.20 C 2X
D
e1
A
D
N
E/2
E1/2
E1
E
(DATUM D)
(DATUM A-B)
0.15 C D
2X
NOTE 1
1
2
e
B
NX b
0.20
C A-B D
TOP VIEW
A
A A2
0.20 C
SEATING PLANE
A
SEE SHEET 2
A1
C
SIDE VIEW
Microchip Technology Drawing C04-091-OT Rev F Sheet 1 of 2
2009-2019 Microchip Technology Inc.
DS20002145B-page 19
MCP6L71/1R/2/4
5-Lead Plastic Small Outline Transistor (OT) [SOT23]
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
c
T
L
L1
VIEW A-A
SHEET 1
Units
Dimension Limits
N
Number of Pins
e
Pitch
e1
Outside lead pitch
A
Overall Height
A2
Molded Package Thickness
Standoff
A1
Overall Width
E
Molded Package Width
E1
Overall Length
D
Foot Length
L
Footprint
L1
I
Foot Angle
c
Lead Thickness
b
Lead Width
MIN
0.90
0.89
-
0.30
0°
0.08
0.20
MILLIMETERS
NOM
5
0.95 BSC
1.90 BSC
2.80 BSC
1.60 BSC
2.90 BSC
0.60 REF
-
MAX
1.45
1.30
0.15
0.60
10°
0.26
0.51
Notes:
1. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or
protrusions shall not exceed 0.25mm per side.
2. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
Microchip Technology Drawing C04-091-OT Rev F Sheet 2 of 2
DS20002145B-page 20
2009-2019 Microchip Technology Inc.
MCP6L71/1R/2/4
5-Lead Plastic Small Outline Transistor (OT) [SOT23]
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
X
SILK SCREEN
5
Y
Z
C
G
1
2
E
GX
RECOMMENDED LAND PATTERN
Units
Dimension Limits
E
Contact Pitch
C
Contact Pad Spacing
X
Contact Pad Width (X5)
Contact Pad Length (X5)
Y
Distance Between Pads
G
Distance Between Pads
GX
Overall Width
Z
MIN
MILLIMETERS
NOM
0.95 BSC
2.80
MAX
0.60
1.10
1.70
0.35
3.90
Notes:
1. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
Microchip Technology Drawing No. C04-2091-OT Rev F
2009-2019 Microchip Technology Inc.
DS20002145B-page 21
MCP6L71/1R/2/4
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS20002145B-page 22
2009-2019 Microchip Technology Inc.
MCP6L71/1R/2/4
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2009-2019 Microchip Technology Inc.
DS20002145B-page 23
MCP6L71/1R/2/4
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS20002145B-page 24
2009-2019 Microchip Technology Inc.
MCP6L71/1R/2/4
8-Lead Plastic Small Outline (SN) - Narrow, 3.90 mm (.150 In.) Body [SOIC]
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2X
0.10 C A–B
D
A
D
NOTE 5
N
E
2
E1
2
E1
E
NOTE 1
2
1
e
B
NX b
0.25
C A–B D
NOTE 5
TOP VIEW
0.10 C
C
A A2
SEATING
PLANE
8X
A1
SIDE VIEW
0.10 C
h
R0.13
h
R0.13
H
SEE VIEW C
VIEW A–A
0.23
L
(L1)
VIEW C
Microchip Technology Drawing No. C04-057-SN Rev E Sheet 1 of 2
2009-2019 Microchip Technology Inc.
DS20002145B-page 25
MCP6L71/1R/2/4
8-Lead Plastic Small Outline (SN) - Narrow, 3.90 mm (.150 In.) Body [SOIC]
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Units
Dimension Limits
Number of Pins
N
e
Pitch
Overall Height
A
Molded Package Thickness
A2
§
Standoff
A1
Overall Width
E
Molded Package Width
E1
Overall Length
D
Chamfer (Optional)
h
Foot Length
L
L1
Footprint
Foot Angle
c
Lead Thickness
b
Lead Width
Mold Draft Angle Top
Mold Draft Angle Bottom
MIN
1.25
0.10
0.25
0.40
0°
0.17
0.31
5°
5°
MILLIMETERS
NOM
8
1.27 BSC
6.00 BSC
3.90 BSC
4.90 BSC
1.04 REF
-
MAX
1.75
0.25
0.50
1.27
8°
0.25
0.51
15°
15°
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. § Significant Characteristic
3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or
protrusions shall not exceed 0.15mm per side.
4. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
5. Datums A & B to be determined at Datum H.
Microchip Technology Drawing No. C04-057-SN Rev E Sheet 2 of 2
DS20002145B-page 26
2009-2019 Microchip Technology Inc.
MCP6L71/1R/2/4
8-Lead Plastic Small Outline (SN) - Narrow, 3.90 mm Body [SOIC]
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
SILK SCREEN
C
Y1
X1
E
RECOMMENDED LAND PATTERN
Units
Dimension Limits
E
Contact Pitch
Contact Pad Spacing
C
Contact Pad Width (X8)
X1
Contact Pad Length (X8)
Y1
MIN
MILLIMETERS
NOM
1.27 BSC
5.40
MAX
0.60
1.55
Notes:
1. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
Microchip Technology Drawing C04-2057-SN Rev E
2009-2019 Microchip Technology Inc.
DS20002145B-page 27
MCP6L71/1R/2/4
14-Lead Plastic Small Outline (SL) - Narrow, 3.90 mm Body [SOIC]
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2X
0.10 C A–B
D
A
NOTE 5
D
N
E
2
E2
2
E1
E
2X
0.10 C D
NOTE 1
1
2
2X N/2 TIPS
0.20 C
3
e
NX b
B
0.25
NOTE 5
C A–B D
TOP VIEW
0.10 C
C
A A2
SEATING
PLANE
14X
A1
h
0.10 C
SIDE VIEW
h
R0.13
H
R0.13
c
SEE VIEW C
L
VIEW A–A
(L1)
VIEW C
Microchip Technology Drawing No. C04-065-SL Rev D Sheet 1 of 2
DS20002145B-page 28
2009-2019 Microchip Technology Inc.
MCP6L71/1R/2/4
14-Lead Plastic Small Outline (SL) - Narrow, 3.90 mm Body [SOIC]
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Units
Dimension Limits
Number of Pins
N
e
Pitch
Overall Height
A
Molded Package Thickness
A2
§
Standoff
A1
Overall Width
E
Molded Package Width
E1
Overall Length
D
Chamfer (Optional)
h
Foot Length
L
Footprint
L1
Lead Angle
Foot Angle
c
Lead Thickness
Lead Width
b
Mold Draft Angle Top
Mold Draft Angle Bottom
MIN
1.25
0.10
0.25
0.40
0°
0°
0.10
0.31
5°
5°
MILLIMETERS
NOM
14
1.27 BSC
6.00 BSC
3.90 BSC
8.65 BSC
1.04 REF
-
MAX
1.75
0.25
0.50
1.27
8°
0.25
0.51
15°
15°
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. § Significant Characteristic
3. Dimension D does not include mold flash, protrusions or gate burrs, which shall
not exceed 0.15 mm per end. Dimension E1 does not include interlead flash
or protrusion, which shall not exceed 0.25 mm per side.
4. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
5. Datums A & B to be determined at Datum H.
Microchip Technology Drawing No. C04-065-SL Rev D Sheet 2 of 2
2009-2019 Microchip Technology Inc.
DS20002145B-page 29
MCP6L71/1R/2/4
14-Lead Plastic Small Outline (SL) - Narrow, 3.90 mm Body [SOIC]
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
14
SILK SCREEN
C
Y
1
2
X
E
RECOMMENDED LAND PATTERN
Units
Dimension Limits
E
Contact Pitch
Contact Pad Spacing
C
Contact Pad Width (X14)
X
Contact Pad Length (X14)
Y
MIN
MILLIMETERS
NOM
1.27 BSC
5.40
MAX
0.60
1.55
Notes:
1. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
Microchip Technology Drawing No. C04-2065-SL Rev D
DS20002145B-page 30
2009-2019 Microchip Technology Inc.
MCP6L71/1R/2/4
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2009-2019 Microchip Technology Inc.
DS20002145B-page 31
MCP6L71/1R/2/4
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS20002145B-page 32
2009-2019 Microchip Technology Inc.
MCP6L71/1R/2/4
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2009-2019 Microchip Technology Inc.
DS20002145B-page 33
MCP6L71/1R/2/4
NOTES:
DS20002145B-page 34
2009-2019 Microchip Technology Inc.
MCP6L71/1R/2/4
APPENDIX A:
REVISION HISTORY
Revision B (October 2019)
The following is the list of modifications:
1.
Updated Section 6.0 “Packaging
Information”.
Revision A (March 2009)
• Original data sheet release.
2009-2019 Microchip Technology Inc.
DS20002145B-page 35
MCP6L71/1R/2/4
NOTES:
DS20002145B-page 36
2009-2019 Microchip Technology Inc.
MCP6L71/1R/2/4
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
PART NO.
Device
–
X
/XX
Temperature
Range
Package
Device:
MCP6L71T:
MCP6L71RT:
MCP6L72T:
MCP6L74T:
Single Op Amp (Tape and Reel)
(MSOP, SOIC, SOT-23)
Single Op Amp (Tape and Reel)
(SOT-23)
Dual Op Amp (Tape and Reel)
(MSOP, SOIC)
Quad Op Amp (Tape and Reel)
(SOIC, TSSOP)
Temperature Range:
E
= -40°C to +125°C
Package:
OT = Plastic Small Outline Transistor (SOT-23), 5-Lead
(MCP6L71, MCP6L71R)
MS = Plastic MSOP, 8-Lead
SN = Plastic SOIC (3.90 mm Body), 8-Lead
SL = Plastic SOIC (3.90 mm Body), 14-Lead
ST = Plastic TSSOP (4.4 mm Body), 14-Lead
2009-2019 Microchip Technology Inc.
Examples:
a) MCP6L71T-E/OT: Tape and Reel,
5-Lead SOT-23 package.
b) MCP6L71T-E/MS: Tape and Reel,
8-Lead MSOP package.
c) MCP6L71T-E/SN: Tape and Reel,
8-Lead SOIC package.
a) MCP6L71RT-E/OT: Tape and Reel,
5-Lead SOT-23 package.
a) MCP6L72T-E/MS: Tape and Reel,
8-Lead MSOP package.
b) MCP6L72T-E/SN: Tape and Reel,
8-Lead SOIC package.
a) MCP6L74T-E/SL: Tape and Reel,
14-Lead SOIC package.
b) MCP6L74-E/ST: Tape and Reel,
14-Lead TSSOP package.
DS20002145B-page 37
MCP6L71/1R/2/4
NOTES:
DS20002145B-page 38
2009-2019 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
•
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights unless otherwise stated.
Trademarks
The Microchip name and logo, the Microchip logo, Adaptec,
AnyRate, AVR, AVR logo, AVR Freaks, BesTime, BitCloud, chipKIT,
chipKIT logo, CryptoMemory, CryptoRF, dsPIC, FlashFlex,
flexPWR, HELDO, IGLOO, JukeBlox, KeeLoq, Kleer, LANCheck,
LinkMD, maXStylus, maXTouch, MediaLB, megaAVR, Microsemi,
Microsemi logo, MOST, MOST logo, MPLAB, OptoLyzer,
PackeTime, PIC, picoPower, PICSTART, PIC32 logo, PolarFire,
Prochip Designer, QTouch, SAM-BA, SenGenuity, SpyNIC, SST,
SST Logo, SuperFlash, Symmetricom, SyncServer, Tachyon,
TempTrackr, TimeSource, tinyAVR, UNI/O, Vectron, and XMEGA
are registered trademarks of Microchip Technology Incorporated in
the U.S.A. and other countries.
APT, ClockWorks, The Embedded Control Solutions Company,
EtherSynch, FlashTec, Hyper Speed Control, HyperLight Load,
IntelliMOS, Libero, motorBench, mTouch, Powermite 3, Precision
Edge, ProASIC, ProASIC Plus, ProASIC Plus logo, Quiet-Wire,
SmartFusion, SyncWorld, Temux, TimeCesium, TimeHub,
TimePictra, TimeProvider, Vite, WinPath, and ZL are registered
trademarks of Microchip Technology Incorporated in the U.S.A.
Adjacent Key Suppression, AKS, Analog-for-the-Digital Age, Any
Capacitor, AnyIn, AnyOut, BlueSky, BodyCom, CodeGuard,
CryptoAuthentication, CryptoAutomotive, CryptoCompanion,
CryptoController, dsPICDEM, dsPICDEM.net, Dynamic Average
Matching, DAM, ECAN, EtherGREEN, In-Circuit Serial
Programming, ICSP, INICnet, Inter-Chip Connectivity, JitterBlocker,
KleerNet, KleerNet logo, memBrain, Mindi, MiWi, MPASM, MPF,
MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach,
Omniscient Code Generation, PICDEM, PICDEM.net, PICkit,
PICtail, PowerSmart, PureSilicon, QMatrix, REAL ICE, Ripple
Blocker, SAM-ICE, Serial Quad I/O, SMART-I.S., SQI,
SuperSwitcher, SuperSwitcher II, Total Endurance, TSHARC,
USBCheck, VariSense, ViewSpan, WiperLock, Wireless DNA, and
ZENA are trademarks of Microchip Technology Incorporated in the
U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated in
the U.S.A.
The Adaptec logo, Frequency on Demand, Silicon Storage
Technology, and Symmcom are registered trademarks of Microchip
Technology Inc. in other countries.
GestIC is a registered trademark of Microchip Technology Germany
II GmbH & Co. KG, a subsidiary of Microchip Technology Inc., in
other countries.
All other trademarks mentioned herein are property of their
respective companies.
© 2009-2019, Microchip Technology Incorporated, All Rights
Reserved.
For information regarding Microchip’s Quality Management Systems,
please visit www.microchip.com/quality.
2009-2019 Microchip Technology Inc.
ISBN: 978-1-5224-5292-8
DS20002145B-page 39
Worldwide Sales and Service
AMERICAS
ASIA/PACIFIC
ASIA/PACIFIC
EUROPE
Corporate Office
2355 West Chandler Blvd.
Chandler, AZ 85224-6199
Tel: 480-792-7200
Fax: 480-792-7277
Technical Support:
http://www.microchip.com/
support
Web Address:
www.microchip.com
Australia - Sydney
Tel: 61-2-9868-6733
India - Bangalore
Tel: 91-80-3090-4444
China - Beijing
Tel: 86-10-8569-7000
India - New Delhi
Tel: 91-11-4160-8631
Austria - Wels
Tel: 43-7242-2244-39
Fax: 43-7242-2244-393
China - Chengdu
Tel: 86-28-8665-5511
India - Pune
Tel: 91-20-4121-0141
Denmark - Copenhagen
Tel: 45-4450-2828
Fax: 45-4485-2829
China - Chongqing
Tel: 86-23-8980-9588
Japan - Osaka
Tel: 81-6-6152-7160
Finland - Espoo
Tel: 358-9-4520-820
China - Dongguan
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Japan - Tokyo
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China - Guangzhou
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Korea - Daegu
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Tel: 33-1-69-53-63-20
Fax: 33-1-69-30-90-79
China - Hangzhou
Tel: 86-571-8792-8115
Korea - Seoul
Tel: 82-2-554-7200
China - Hong Kong SAR
Tel: 852-2943-5100
Malaysia - Kuala Lumpur
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China - Nanjing
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Thailand - Bangkok
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Vietnam - Ho Chi Minh
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Atlanta
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Fax: 774-760-0088
Chicago
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Fax: 630-285-0075
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Tel: 408-735-9110
Tel: 408-436-4270
Canada - Toronto
Tel: 905-695-1980
Fax: 905-695-2078
DS20002145B-page 40
China - Xiamen
Tel: 86-592-2388138
China - Zhuhai
Tel: 86-756-3210040
Germany - Garching
Tel: 49-8931-9700
Germany - Haan
Tel: 49-2129-3766400
Germany - Heilbronn
Tel: 49-7131-72400
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Tel: 49-721-625370
Germany - Munich
Tel: 49-89-627-144-0
Fax: 49-89-627-144-44
Germany - Rosenheim
Tel: 49-8031-354-560
Israel - Ra’anana
Tel: 972-9-744-7705
Italy - Milan
Tel: 39-0331-742611
Fax: 39-0331-466781
Italy - Padova
Tel: 39-049-7625286
Netherlands - Drunen
Tel: 31-416-690399
Fax: 31-416-690340
Norway - Trondheim
Tel: 47-7288-4388
Poland - Warsaw
Tel: 48-22-3325737
Romania - Bucharest
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Spain - Madrid
Tel: 34-91-708-08-90
Fax: 34-91-708-08-91
Sweden - Gothenberg
Tel: 46-31-704-60-40
Sweden - Stockholm
Tel: 46-8-5090-4654
UK - Wokingham
Tel: 44-118-921-5800
Fax: 44-118-921-5820
2009-2019 Microchip Technology Inc.
05/14/19
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