MCP6L91/1R/2/4
10 MHz, 850 µA Op Amps
Features
Description
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•
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The Microchip Technology Inc. MCP6L91/1R/2/4 family
of operational amplifiers (op amps) provides wide
bandwidth for the current. The input bias currents and
voltage ranges make it easier to fit into many
applications.
Available in SOT-23 Package
Gain Bandwidth Product: 10 MHz (typical)
Rail-to-Rail Input/Output
Supply Voltage: 2.4V to 6.0V
Supply Current: IQ = 0.85 mA/Amplifier (typical)
Extended Temperature Range: -40°C to +125°C
Available in Single, Dual and Quad Packages
Typical Applications
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Portable Equipment
Photodiode Amplifier
Analog Filters
Notebooks and PDAs
Battery-Powered Systems
This family has a 10 MHz Gain Bandwidth Product
(GBWP) and a low 850 µA per amplifier quiescent
current. These op amps operate on supply voltages
between 2.4V and 6.0V, with rail-to-rail input and output
swing. They are available in the extended temperature
range.
Package Types
MCP6L91
SOT-23
VOUT 1
Design Aids
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•
•
•
•
Typical Application
R1
R2
3.01 k 6.81 k
VIN
MCP6L91
–
C2
12 nF
VIN+ 3
VOUTA 1
4 VIN-
VINA- 2
VINA+ 3
VSS 4
MCP6L91
SOIC, MSOP
NC 1
8 NC
7 VDD
VOUTA 1
6 VOUT
VINA- 2
VINA+ 3
R3
9.31 k
C3
27 nF
5 NC
MCP6L91R
SOT-23
VOUT
VOUT 1
5 VSS
8 VDD
7 VOUTB
6 VINB5 VINB+
MCP6L94
SOIC, TSSOP
VIN- 2
VIN+ 3
VSS 4
+
C1
120 nF
5 VDD
VSS 2
SPICE Macro Model
FilterLab® Software
Microchip Advanced Part Selector (MAPS)
Analog Demonstration and Evaluation Boards
Application Notes
MCP6L92
SOIC, MSOP
14 VOUTD
13 VIND12 VIND+
VDD 4
VINB+ 5
10 VINC+
VINB- 6
9 VINC-
VOUTB 7
8 VOUTC
11 VSS
VDD 2
VIN+ 3
4 VIN-
Low-Pass Filter
2009-2019 Microchip Technology Inc.
DS20002141C-page 1
MCP6L91/1R/2/4
NOTES:
DS20002141C-page 2
2009-2019 Microchip Technology Inc.
MCP6L91/1R/2/4
1.0
ELECTRICAL
CHARACTERISTICS
1.1
Absolute Maximum Ratings†
† Notice: Stresses above those listed under “Absolute
Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of
the device at those or any other conditions above those
indicated in the operational listings of this specification is not
implied. Exposure to maximum rating conditions for extended
periods may affect device reliability.
VDD – VSS .......................................................................7.0V
Current at Input Pins ....................................................±2 mA
Analog Inputs (VIN+, VIN-)†† ......... VSS – 1.0V to VDD + 1.0V
All Inputs and Outputs ................... VSS – 0.3V to VDD + 0.3V
Difference Input Voltage ...................................... |VDD – VSS|
Output Short-Circuit Current ................................ Continuous
Current at Output and Supply Pins ............................±30 mA
Storage Temperature ...................................-65°C to +150°C
Max. Junction Temperature ........................................ +150°C
ESD Protection on All Pins (HBM, MM) 4 kV, 400V
1.2
†† See Section 4.1.2 “Input Voltage and Current Limits”.
Specifications
TABLE 1-1:
DC ELECTRICAL SPECIFICATIONS
Electrical Characteristics: Unless otherwise indicated: TA = +25°C, VDD = 5.0V, VSS = GND, VCM = VSS,
VOUT VDD/2, VL = VDD/2 and RL = 10 k to VL (refer to Figure 1-1).
Parameters
Sym
Min(1)
Typ
Max(1)
Units
Conditions
Input Offset
Input Offset Voltage
Input Offset Voltage Drift
VOS
-4
±1
+4
VOS/TA
—
±1.3
—
PSRR
—
89
—
dB
IB
—
1
—
pA
IB
—
50
—
pA
TA = +85°C
TA = +125°C
Power Supply Rejection Ratio
mV
µV/°C TA= -40°C to +125°C
Input Current and Impedance
Input Bias Current
Across Temperature
IB
—
2000
—
pA
Input Offset Current
Across Temperature
IOS
—
±1
—
pA
Common-mode Input Impedance
ZCM
—
1013||6
—
||pF
Differential Input Impedance
ZDIFF
—
1013||3
—
||pF
Common-mode Input Voltage
Range
VCMR
-0.3
—
5.3
V
Common-mode Rejection Ratio
CMRR
—
91
—
dB
VCM = -0.3V to 5.3V
AOL
—
105
—
dB
VOUT = 0.2V to 4.8V
VOL
—
—
0.020
V
G = +2, 0.5V input overdrive
VOH
4.980
—
—
V
G = +2, 0.5V input overdrive
ISC
—
±25
—
mA
VDD
2.4
—
6.0
V
IQ
0.35
0.85
1.35
mA
Common-mode
Open-Loop Gain
DC Open-Loop Gain (large signal)
Output
Maximum Output Voltage Swing
Output Short-Circuit Current
Power Supply
Supply Voltage
Quiescent Current per Amplifier
Note 1:
IO = 0
For design guidance only; not tested.
2009-2019 Microchip Technology Inc.
DS20002141C-page 3
MCP6L91/1R/2/4
TABLE 1-2:
AC ELECTRICAL SPECIFICATIONS
Electrical Characteristics: Unless otherwise indicated: TA = +25°C, VDD = +5.0V, VSS = GND, VCM = VSS,
VOUT VDD/2, VL = VDD/2, RL = 10 k to VL and CL = 60 pF (refer to Figure 1-1).
Parameters
Sym
Min
Typ
Max
Units
GBWP
—
10
—
MHz
Conditions
AC Response
Gain Bandwidth Product
Phase Margin
PM
—
65
—
°
Slew Rate
SR
—
7
—
V/µs
G = +1
Input Noise Voltage
Eni
—
2.5
—
µVP-P
Input Noise Voltage Density
eni
—
9.4
—
nV/Hz f = 10 kHz
Input Noise Current Density
ini
—
3
—
fA/Hz f = 1 kHz
Noise
TABLE 1-3:
f = 0.1 Hz to 10 Hz
TEMPERATURE SPECIFICATIONS
Electrical Characteristics: Unless otherwise indicated, all limits are specified for: VDD = +2.4V to +6.0V, VSS = GND.
Parameters
Sym
Min
Typ
Max
Units
TA
-40
—
+125
°C
Operating Temperature Range
TA
-40
—
+125
°C
Storage Temperature Range
TA
-65
—
+150
°C
Thermal Resistance, 5-Lead SOT-23
JA
—
256
—
°C/W
Thermal Resistance, 8-Lead SOIC (150 mil)
JA
—
163
—
°C/W
Thermal Resistance, 8-Lead MSOP
JA
—
206
—
°C/W
Thermal Resistance, 14-Lead SOIC
JA
—
120
—
°C/W
Thermal Resistance, 14-Lead TSSOP
JA
—
100
—
°C/W
Conditions
Temperature Ranges
Specified Temperature Range
(Note 1)
Thermal Package Resistances
Note 1:
Operation must not cause TJ to exceed maximum junction temperature specification (+150°C).
DS20002141C-page 4
2009-2019 Microchip Technology Inc.
MCP6L91/1R/2/4
1.3
Test Circuit
The circuit used for most DC and AC tests is shown in
Figure 1-1. This circuit can independently set VCM and
VOUT; see Equation 1-1. Note that VCM is not the
circuit’s Common-mode voltage ((VP + VM)/2) and that
VOST includes VOS plus the effects (on the input offset
error, VOST) of temperature, CMRR, PSRR and AOL.
CF
6.8 pF
RG
100 k
VP
VDD
VIN+
EQUATION 1-1:
G DM = RF R G
MCP6L9X
VCM = VP + V DD 2 2
CB1
100 nF
+
–
VDD/2
CB2
1 µF
VIN-
VOST = V IN– – VIN+
VOUT = V DD 2 + V P – V M + V OST 1 + G DM
Where:
GDM = Differential-mode Gain
(V/V)
VCM = Op Amp’s Common-mode
Input Voltage
(V)
VOST = Op Amp’s Total Input Offset
Voltage
(mV)
2009-2019 Microchip Technology Inc.
RF
100 k
VM
RG
100 k
RL
10 k
RF
100 k
CF
6.8 pF
VOUT
CL
60 pF
VL
FIGURE 1-1:
AC and DC Test Circuit for
Most Specifications.
DS20002141C-page 5
MCP6L91/1R/2/4
NOTES:
DS20002141C-page 6
2009-2019 Microchip Technology Inc.
MCP6L91/1R/2/4
2.0
TYPICAL PERFORMANCE CURVES
Note:
The graphs and tables provided following this note are a statistical summary based on a limited number of
samples and are provided for informational purposes only. The performance characteristics listed herein
are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified
operating range (e.g., outside specified power supply range) and therefore outside the warranted range.
VDD = 2.4V
Representative Part
3.0
2.5
2.0
1.5
1.0
0.5
0.0
-40°C
+25°C
+85°C
+125°C
Common Mode Range (V)
1.0
0.8
0.6
0.4
0.2
0.0
-0.2
-0.4
-0.6
-0.8
-1.0
-0.5
Input Offset Voltage (mV)
Note: Unless otherwise indicated, TA = +25°C, VDD = 5.0V, VSS = GND, VCM = VSS, VOUT = VDD/2, VL = VDD/2,
RL = 10 kto VL and CL = 60 pF.
0.5
0.4
0.3
0.2
0.1
0.0
-0.1
-0.2
-0.3
-0.4
-0.5
VCMRH – VDD
One Wafer Lot
VCMRL – VSS
-50
-25
Common Mode Input Voltage (V)
CMRR, PSRR (dB)
CMRR (VCM = VCMRL to VCMRH)
90
PSRR (VCM = VSS)
85
80
75
70
6.0
5.5
5.0
4.5
4.0
3.5
3.0
2.5
95
-50
-25
Common Mode Input Voltage (V)
0
25
50
75
Ambient Temperature (°C)
FIGURE 2-5:
Temperature.
100
125
CMRR, PSRR vs. Ambient
100
Representative Part
90
VDD = 1.8V
VDD = 5.5V
CMRR, PSRR (dB)
Input Offset Voltage (mV)
FIGURE 2-2:
Input Offset Voltage vs.
Common-mode Input Voltage at VDD = 5.5V.
0.5
0.4
0.3
0.2
0.1
0.0
-0.1
-0.2
-0.3
-0.4
-0.5
125
100
+125°C
+85°C
+25°C
-40°C
2.0
1.5
1.0
0.5
0.0
-0.5
Input Offset Voltage (mV)
VDD = 5.5V
Representative Part
100
FIGURE 2-4:
Input Common-mode Range
Voltage vs. Ambient Temperature.
FIGURE 2-1:
Input Offset Voltage vs.
Common-mode Input Voltage at VDD = 2.4V.
1.0
0.8
0.6
0.4
0.2
0.0
-0.2
-0.4
-0.6
-0.8
-1.0
0
25
50
75
Ambient Temperature (°C)
80
CMRR
70
60
50
PSRR–
PSRR+
40
30
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Output Voltage (V)
FIGURE 2-3:
Output Voltage.
Input Offset Voltage vs.
2009-2019 Microchip Technology Inc.
20
10
1.E+01
FIGURE 2-6:
Frequency.
100
1.E+02
1k
10k
1.E+03
1.E+04
Frequency (Hz)
100k
1.E+05
CMRR, PSRR vs.
DS20002141C-page 7
MCP6L91/1R/2/4
Note: Unless otherwise indicated, TA = +25°C, VDD = 5.0V, VSS = GND, VCM = VSS, VOUT = VDD/2, VL = VDD/2,
RL = 10 kto VL and CL = 60 pF.
Input Current Magnitude (A)
Input, Output Voltages (V)
6
10m
1.E-02
1m
1.E-03
100µ
1.E-04
10µ
1.E-05
1µ
1.E-06
100n
1.E-07
10n
1.E-08
1n
1.E-09
100p
1.E-10
10p
1.E-11
1p
1.E-12
+125°C
+85°C
+25°C
-40°C
-1.0 -0.9 -0.8 -0.7 -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0.0
Input Voltage (V)
0
100
-30
80
Phase
60
-60
-90
40
Gain
-120
20
-150
0
-180
VOUT
3
2
1
0
-1
0.E+00
4.E-03
5.E-03
6.E-03
7.E-03
8.E-03
9.E-03
1.E-02
1.2
1.1
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.0
+125°C
+85°C
+25°C
-40°C
FIGURE 2-11:
Quiescent Current vs.
Power Supply Voltage.
40
100
10
1
0.1
1
10
100 1.E+0
1k
10k 1.E+0
100k
1.E-01
1.E+0
1.E+0
1.E+0
1.E+0
0
1Frequency
2 (Hz)3
4
5
DS20002141C-page 8
3.E-03
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
Power Supply Voltage (V)
1,000
FIGURE 2-9:
vs. Frequency.
2.E-03
FIGURE 2-10:
The MCP6L91/1R/2/4 Show
No Phase Reversal.
Short Circuit Current (mA)
Input Noise Voltage Density
(nV/ Hz)
Open-Loop Gain, Phase vs.
1.E-03
Time (1 ms/div)
-20
-210
1 1.E+
10 1.E+
100 1.E+
1k 1.E+
10k 100k
1M 1.E+
10M 100M
1.E+
1.E+ 1.E+
1.E+
00 01 02 Frequency
03 04 (Hz)
05 06 07 08
FIGURE 2-8:
Frequency.
G = +2 V/V
4
Quiescent Current
per amplifier (mA)
120
Open-Loop Phase (°)
Open-Loop Gain (dB)
FIGURE 2-7:
Measured Input Current vs.
Input Voltage (below VSS).
VIN
5
Input Noise Voltage Density
30
20
10
0
-10
-40°C
+25°C
+85°C
+125°C
-20
-30
-40
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Power Supply Voltage (V)
FIGURE 2-12:
Output Short-Circuit Current
vs. Power Supply Voltage.
2009-2019 Microchip Technology Inc.
MCP6L91/1R/2/4
Note: Unless otherwise indicated, TA = +25°C, VDD = 5.0V, VSS = GND, VCM = VSS, VOUT = VDD/2, VL = VDD/2,
RL = 10 kto VL and CL = 60 pF.
VDD – VOH
IOUT
25
Slew Rate (V/µs)
Ratio of Output Headroom
to Output Current (mV/mA)
30
20
VOL – VSS
-IOUT
15
10
5
0
100µ
1.E-04
1m
1.E-03
Output Current Magnitude (A)
10m
1.E-02
FIGURE 2-13:
Ratio of Output Voltage
Headroom to Output Current vs. Output Current.
P-P )
0.02
0.01
0.00
-0.01
-0.02
-0.03
-0.04
0.E+00
2.E-07
4.E-07
6.E-07
8.E-07
1.E-06
1.E-06
1.E-06
2.E-06
2.E-06
2.E-06
Time (200 ns/div)
FIGURE 2-14:
Pulse Response.
5.0
VDD = 2.4V
Rising Edge
-25
10
0
25
50
75
Ambient Temperature (°C)
100
125
Slew Rate vs. Ambient
VDD = 5.5V
VDD = 2.4V
1
0.1
10k
1.E+04
FIGURE 2-17:
Frequency.
100k
1M
1.E+05
1.E+06
Frequency (Hz)
10M
1.E+07
Output Voltage Swing vs.
G = +1 V/V
4.5
Output Voltage (V)
Small Signal, Noninverting
Falling Edge
FIGURE 2-16:
Temperature.
Output Voltage Swing (V
Output Voltage (10 mV/div)
G = +1 V/V
VDD = 5.5V
-50
0.04
0.03
12
11
10
9
8
7
6
5
4
3
2
1
0
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
0.E+00
1.E-06
2.E-06
3.E-06
4.E-06
5.E-06
6.E-06
7.E-06
8.E-06
9.E-06
1.E-05
Time (1 µs/div)
FIGURE 2-15:
Pulse Response.
Large Signal, Noninverting
2009-2019 Microchip Technology Inc.
DS20002141C-page 9
MCP6L91/1R/2/4
NOTES:
DS20002141C-page 10
2009-2019 Microchip Technology Inc.
MCP6L91/1R/2/4
3.0
PIN DESCRIPTIONS
Descriptions of the pins are listed in Table 3-1.
TABLE 3-1:
PIN FUNCTION TABLE
MCP6L91
MCP6L91R
MCP6L92
MCP6L94
5-Lead
SOT-23
8-Lead
MSOP,
SOIC
5-Lead
SOT-23
8-Lead
MSOP,
SOIC
14-Lead
SOIC,
TSSOP
1
6
1
1
1
3.1
Description
VOUT, VOUTA
Output (Op Amp A)
4
2
4
2
2
VIN-, VINA-
Inverting Input (Op Amp A)
3
3
3
3
3
VIN+, VINA+
Noninverting Input (Op Amp A)
5
7
2
8
4
VDD
Positive Power Supply
—
—
—
5
5
VINB+
Noninverting Input (Op Amp B)
—
—
—
6
6
VINB-
Inverting Input (Op Amp B)
—
—
—
7
7
VOUTB
Output (Op Amp B)
—
—
—
—
8
VOUTC
Output (Op Amp C)
—
—
—
—
9
VINC-
Inverting Input (Op Amp C)
—
—
—
—
10
VINC+
Noninverting Input (Op Amp C)
2
4
5
4
11
VSS
Negative Power Supply
—
—
—
—
12
VIND+
Noninverting Input (Op Amp D)
—
—
—
—
13
VIND-
Inverting Input (Op Amp D)
—
—
—
—
14
VOUTD
Output (Op Amp D)
—
1, 5, 8
—
—
—
NC
No Internal Connection
Analog Outputs
The analog output pins (VOUT) are low-impedance
voltage sources.
3.2
Symbol
Analog Inputs
The noninverting and inverting inputs (VIN+, VIN-, …)
are high-impedance CMOS inputs with low bias
currents.
2009-2019 Microchip Technology Inc.
3.3
Power Supply Pins
The positive power supply (VDD) is 2.4V to 6.0V higher
than the negative power supply (VSS). For normal
operation, the other pins are between VSS and VDD.
Typically, these parts are used in a single (positive)
supply configuration. In this case, VSS is connected to
ground and VDD is connected to the supply. VDD will
need bypass capacitors.
DS20002141C-page 11
MCP6L91/1R/2/4
NOTES:
DS20002141C-page 12
2009-2019 Microchip Technology Inc.
MCP6L91/1R/2/4
4.0
APPLICATION INFORMATION
4.1.3
NORMAL OPERATION
The MCP6L91/1R/2/4 family of op amps is manufactured using Microchip’s state-of-the-art CMOS process.
It is designed for low-cost, low-power and general
purpose applications. The low supply voltage, low
quiescent current and wide bandwidth makes the
MCP6L91/1R/2/4 ideal for battery-powered applications.
The input stage of the MCP6L91/1R/2/4 op amps use
two differential CMOS input stages in parallel. One
operates at low Common-mode input voltage (VCM),
while the other operates at high VCM. With this
topology, and at room temperature, the device
operates with VCM up to 0.3V above VDD and 0.3V
below VSS (typical at +25°C).
4.1
The transition between the two input stages occurs
when VCM = VDD – 1.1V. For the best distortion and
gain linearity, with noninverting gains, avoid this region
of operation.
Rail-to-Rail Inputs
4.1.1
PHASE REVERSAL
The MCP6L91/1R/2/4 op amps are designed to
prevent phase inversion when the input pins exceed
the supply voltages. Figure 2-10 shows an input
voltage exceeding both supplies without any phase
reversal.
4.1.2
INPUT VOLTAGE AND CURRENT
LIMITS
In order to prevent damage and/or improper operation
of these amplifiers, the circuit they are in must limit the
currents (and voltages) at the input pins (see
Section 1.1 “Absolute Maximum Ratings†”).
Figure 4-1 shows the recommended approach to
protecting these inputs. The internal ESD diodes
prevent the input pins (VIN+ and VIN-) from going too far
below ground, and the resistors, R1 and R2, limit the
possible current drawn out of the input pins. Diodes, D1
and D2, prevent the input pins (VIN+ and VIN-) from
going too far above VDD, and dump any currents onto
VDD.
VDD
D1
V1
V2
Rail-to-Rail Output
The output voltage range of the MCP6L91/1R/2/4
op amps is VDD – 20 mV (minimum) and VSS + 20 mV
(maximum) when RL = 10 k, and is connected to VDD/2
and VDD = 5.0V. Refer to Figure 2-13 for more
information.
4.3
Capacitive Loads
Driving large capacitive loads can cause stability
problems for voltage feedback op amps. As the load
capacitance increases, the feedback loop’s phase
margin decreases and the closed-loop bandwidth is
reduced. This produces gain peaking in the frequency
response, with overshoot and ringing in the step
response.
When driving large capacitive loads with these
op amps (e.g., >100 pF when G = +1), a small series
resistor at the output (RISO in Figure 4-2) improves the
feedback loop’s stability by making the output load
resistive at higher frequencies; the bandwidth will
usually be decreased.
D2
+
R1
4.2
RG
RF
RISO
VOUT
MCP6L9X
–
–
RN
R2
CL
MCP6L9X
+
R3
R1 >
VSS – (minimum expected V1)
2 mA
R2 >
VSS – (minimum expected V2)
2 mA
FIGURE 4-1:
Protecting the Analog Inputs.
FIGURE 4-2:
Output Resistor, RISO,
Stabilizes Large Capacitive Loads.
Bench measurements are helpful in choosing RISO.
Adjust RISO so that a small signal step response (see
Figure 2-14) has reasonable overshoot (e.g., 4%).
A significant amount of current can flow out of the
inputs (through the ESD diodes) when the Commonmode voltage (VCM) is below ground (VSS); see
Figure 2-7. Applications that are high-impedance may
need to limit the usable voltage range.
2009-2019 Microchip Technology Inc.
DS20002141C-page 13
MCP6L91/1R/2/4
4.4
Supply Bypass
Guard Ring
With this family of operational amplifiers, the power
supply pin (VDD for single supply) should have a local
bypass capacitor (i.e., 0.01 µF to 0.1 µF) within 2 mm
for good high-frequency performance. It also needs a
bulk capacitor (i.e., 1 µF or larger) within 100 mm to
provide large, slow currents. This bulk capacitor can be
shared with other nearby analog parts.
FIGURE 4-4:
4.5
1.
Unused Op Amps
An unused op amp in a quad package (e.g., MCP6L94)
should be configured as shown in Figure 4-3. These
circuits prevent the output from toggling and causing
crosstalk. Circuit A sets the op amp at its minimum
noise gain. The resistor divider produces any desired
reference voltage within the output voltage range of the
op amp; the op amp buffers that reference voltage.
Circuit B uses the minimum number of components
and operates as a comparator, but it may draw more
current.
¼ MCP6L94 (A)
VDD
+
+
R2
VREF
–
–
4.7
4.7.1
R2
VREF = V DD -----------------R 1 + R2
FIGURE 4-3:
4.6
2.
VDD
R1
Example Guard Ring Layout.
Inverting Amplifiers (Figure 4-4) and TransImpedance Gain Amplifiers (convert current to
voltage, such as photo detectors).
a) Connect the guard ring to the noninverting
input pin (VIN+); this biases the guard ring
to the same reference voltage as the
op amp’s input (e.g., VDD/2 or ground).
b) Connect the inverting pin (VIN-) to the input
with a wire that does not touch the PCB
surface.
Noninverting Gain and Unity Gain Buffer.
a) Connect the guard ring to the inverting input
pin (VIN-); this biases the guard ring to the
Common-mode input voltage.
b) Connect the noninverting pin (VIN+) to the
input with a wire that does not touch the
PCB surface.
¼ MCP6L94 (B)
VDD
VIN- VIN+
Unused Op Amps.
PCB Surface Leakage
In applications where low input bias current is critical,
Printed Circuit Board (PCB) surface leakage effects
need to be considered. Surface leakage is caused by
humidity, dust or other contamination on the board.
Under low humidity conditions, a typical resistance
between nearby traces is 1012. A 5V difference would
cause 5 pA of current to flow; this is greater than this
family’s bias current at +25°C (1 pA, typical).
The easiest way to reduce surface leakage is to use a
guard ring around sensitive pins (or traces). The guard
ring is biased at the same voltage as the sensitive pin.
Figure 4-4 is an example of this type of layout.
Application Circuit
ACTIVE LOW-PASS FILTER
The MCP6L91/1R/2/4 op amp’s low input noise and
good output current drive make it possible to design
low noise filters. Reducing the resistors’ values also
reduces the noise and increases the frequency at
which parasitic capacitances affect the response.
These trade-offs need to be considered when selecting
circuit elements.
Figure 4-5 shows a third-order Chebyshev filter with a
1 kHz bandwidth, 0.2 dB ripple and a gain of +1 V/V.
The component values were selected using
Microchip’s FilterLab® software. Resistor R3 was
reduced in value by increasing C3 in FilterLab.
R1
R2
3.01 k 6.81 k
VIN
–
R3
9.31 k
+
C1
120 nF
FIGURE 4-5:
DS20002141C-page 14
MCP6L91
C2
12 nF
C3
27 nF
VOUT
Chebyshev Filter.
2009-2019 Microchip Technology Inc.
MCP6L91/1R/2/4
5.0
DESIGN AIDS
Microchip provides the basic design aids needed for
the MCP6L91/1R/2/4 family of op amps.
5.1
SPICE Macro Model
The latest SPICE macro model for the MCP6L91/1R/2/4
op amps is available on the Microchip website at
www.microchip.com. The model was written and tested
in official Orcad (Cadence) owned PSPICE. For other
simulators, translation may be required.
The model covers a wide aspect of the op amp’s
electrical specifications. Not only does the model cover
voltage, current and resistance of the op amp, but it
also covers the temperature and noise effects on the
behavior of the op amp. The model has not been
verified outside of the specification range listed in the
op amp data sheet. The model behaviors under these
conditions cannot be ensured to match the actual
op amp performance.
Moreover, the model is intended to be an initial design
tool. Bench testing is a very important part of any
design and cannot be replaced with simulations. Also,
simulation results using this macro model need to be
validated by comparing them to the data sheet
specifications and characteristic curves.
5.2
FilterLab® Software
Microchip’s FilterLab® software is an innovative software tool that simplifies analog active filter (using op
amps) design. Available at no cost from the Microchip
website at www.microchip.com/filterlab, the FilterLab
design tool provides full schematic diagrams of the filter
circuit with component values. It also outputs the filter
circuit in SPICE format, which can be used with the
macro model to simulate actual filter performance.
5.3
Microchip Advanced Part Selector
(MAPS)
5.4
Analog Demonstration and
Evaluation Boards
Microchip offers a broad spectrum of Analog Demonstration and Evaluation Boards that are designed to
help customers achieve faster time to market. For a
complete listing of these boards and their corresponding user’s guides and technical information, visit the
Microchip website at www.microchip.com/analogtools.
Some boards that are especially useful are:
•
•
•
•
•
•
•
MCP6XXX Amplifier Evaluation Board 1
MCP6XXX Amplifier Evaluation Board 2
MCP6XXX Amplifier Evaluation Board 3
MCP6XXX Amplifier Evaluation Board 4
Active Filter Demo Board Kit
5/6-Pin SOT-23 Evaluation Board, P/N VSUPEV2
8-Pin SOIC/MSOP/TSSOP/DIP Evaluation Board,
P/N SOIC8EV
• 14-Pin SOIC/TSSOP/DIP Evaluation Board,
P/N SOIC14EV
5.5
Application Notes
The following Microchip Application Notes are available
on the Microchip website at www.microchip.com/
appnotes and are recommended as supplemental
reference resources.
• ADN003: “Select the Right Operational Amplifier
for your Filtering Circuits”, DS21821
• AN722: “Operational Amplifier Topologies and DC
Specifications”, DS00722
• AN723: “Operational Amplifier AC Specifications
and Applications”, DS00723
• AN884: “Driving Capacitive Loads With Op Amps”,
DS00884
• AN990: “Analog Sensor Conditioning Circuits –
An Overview”, DS00990
MAPS is a software tool that helps efficiently identify
Microchip devices that fit a particular design requirement. Available at no cost from the Microchip website
at www.microchip.com/maps, the MAPS is an overall
selection tool for Microchip’s product portfolio that
includes Analog, Memory, MCUs and DSCs. Using this
tool, a customer can define a filter to sort features for a
parametric search of devices and export side-by-side
technical comparison reports. Helpful links are also
provided for data sheets, purchase and sampling of
Microchip parts.
2009-2019 Microchip Technology Inc.
DS20002141C-page 15
MCP6L91/1R/2/4
NOTES:
DS20002141C-page 16
2009-2019 Microchip Technology Inc.
MCP6L91/1R/2/4
6.0
PACKAGING INFORMATION
6.1
Package Marking Information
Example:
5-Lead SOT-23 (MCP6L91/1R)
4
5
Device
XXNN
Code
MCP6L91
UUNN
MCP6L91R
UVNN
4
5
UU25
Note: Applies to 5-Lead SOT-23.
1
2
3
1
8-Lead MSOP (MCP6L92)
XXXXXX
YWWNNN
3
Example:
6L92E
934256
8-Lead SOIC (150 mil) (MCP6L92)
XXXXXXXX
Example:
MCP6L92E
XXXXYYWW
SN e 1934
3
NNN
256
Legend: XX...X
Y
YY
WW
NNN
e3
*
Note:
2
Customer-specific information
Year code (last digit of calendar year)
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code
Pb-free JEDEC designator for Matte Tin (Sn)
This package is Pb-free. The Pb-free JEDEC designator ( e3 )
can be found on the outer packaging for this package.
In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
2009-2019 Microchip Technology Inc.
DS20002141C-page 17
MCP6L91/1R/2/4
Package Marking Information (Continued)
14-Lead SOIC (150 mil) (MCP6L94)
XXXXXXXXXXX
XXXXXXXXXXX
YYWWNNN
14-Lead TSSOP (MCP6L94)
XXXXXXXX
YYWW
NNN
DS20002141C-page 18
Example:
MCP6L94
E/SL e3
1934256
Example:
6L94EST
1934
256
2009-2019 Microchip Technology Inc.
MCP6L91/1R/2/4
5-Lead Plastic Small Outline Transistor (OT) [SOT23]
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
0.20 C 2X
D
e1
A
D
N
E/2
E1/2
E1
E
(DATUM D)
(DATUM A-B)
0.15 C D
2X
NOTE 1
1
2
e
B
NX b
0.20
C A-B D
TOP VIEW
A
A A2
0.20 C
SEATING PLANE
A
SEE SHEET 2
A1
C
SIDE VIEW
Microchip Technology Drawing C04-091-OT Rev F Sheet 1 of 2
2009-2019 Microchip Technology Inc.
DS20002141C-page 19
MCP6L91/1R/2/4
5-Lead Plastic Small Outline Transistor (OT) [SOT23]
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
c
T
L
L1
VIEW A-A
SHEET 1
Units
Dimension Limits
N
Number of Pins
e
Pitch
e1
Outside lead pitch
A
Overall Height
A2
Molded Package Thickness
Standoff
A1
Overall Width
E
Molded Package Width
E1
Overall Length
D
Foot Length
L
Footprint
L1
I
Foot Angle
c
Lead Thickness
b
Lead Width
MIN
0.90
0.89
-
0.30
0°
0.08
0.20
MILLIMETERS
NOM
5
0.95 BSC
1.90 BSC
2.80 BSC
1.60 BSC
2.90 BSC
0.60 REF
-
MAX
1.45
1.30
0.15
0.60
10°
0.26
0.51
Notes:
1. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or
protrusions shall not exceed 0.25mm per side.
2. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
Microchip Technology Drawing C04-091-OT Rev F Sheet 2 of 2
DS20002141C-page 20
2009-2019 Microchip Technology Inc.
MCP6L91/1R/2/4
5-Lead Plastic Small Outline Transistor (OT) [SOT23]
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
X
SILK SCREEN
5
Y
Z
C
G
1
2
E
GX
RECOMMENDED LAND PATTERN
Units
Dimension Limits
E
Contact Pitch
C
Contact Pad Spacing
X
Contact Pad Width (X5)
Contact Pad Length (X5)
Y
Distance Between Pads
G
Distance Between Pads
GX
Overall Width
Z
MIN
MILLIMETERS
NOM
0.95 BSC
2.80
MAX
0.60
1.10
1.70
0.35
3.90
Notes:
1. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
Microchip Technology Drawing No. C04-2091-OT Rev F
2009-2019 Microchip Technology Inc.
DS20002141C-page 21
MCP6L91/1R/2/4
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS20002141C-page 22
2009-2019 Microchip Technology Inc.
MCP6L91/1R/2/4
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2009-2019 Microchip Technology Inc.
DS20002141C-page 23
MCP6L91/1R/2/4
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS20002141C-page 24
2009-2019 Microchip Technology Inc.
MCP6L91/1R/2/4
8-Lead Plastic Small Outline (SN) - Narrow, 3.90 mm (.150 In.) Body [SOIC]
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2X
0.10 C A–B
D
A
D
NOTE 5
N
E
2
E1
2
E1
E
NOTE 1
2
1
e
B
NX b
0.25
C A–B D
NOTE 5
TOP VIEW
0.10 C
C
A A2
SEATING
PLANE
8X
A1
SIDE VIEW
0.10 C
h
R0.13
h
R0.13
H
SEE VIEW C
VIEW A–A
0.23
L
(L1)
VIEW C
Microchip Technology Drawing No. C04-057-SN Rev E Sheet 1 of 2
2009-2019 Microchip Technology Inc.
DS20002141C-page 25
MCP6L91/1R/2/4
8-Lead Plastic Small Outline (SN) - Narrow, 3.90 mm (.150 In.) Body [SOIC]
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Units
Dimension Limits
Number of Pins
N
e
Pitch
Overall Height
A
Molded Package Thickness
A2
§
Standoff
A1
Overall Width
E
Molded Package Width
E1
Overall Length
D
Chamfer (Optional)
h
Foot Length
L
L1
Footprint
Foot Angle
c
Lead Thickness
b
Lead Width
Mold Draft Angle Top
Mold Draft Angle Bottom
MIN
1.25
0.10
0.25
0.40
0°
0.17
0.31
5°
5°
MILLIMETERS
NOM
8
1.27 BSC
6.00 BSC
3.90 BSC
4.90 BSC
1.04 REF
-
MAX
1.75
0.25
0.50
1.27
8°
0.25
0.51
15°
15°
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. § Significant Characteristic
3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or
protrusions shall not exceed 0.15mm per side.
4. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
5. Datums A & B to be determined at Datum H.
Microchip Technology Drawing No. C04-057-SN Rev E Sheet 2 of 2
DS20002141C-page 26
2009-2019 Microchip Technology Inc.
MCP6L91/1R/2/4
8-Lead Plastic Small Outline (SN) - Narrow, 3.90 mm Body [SOIC]
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
SILK SCREEN
C
Y1
X1
E
RECOMMENDED LAND PATTERN
Units
Dimension Limits
E
Contact Pitch
Contact Pad Spacing
C
Contact Pad Width (X8)
X1
Contact Pad Length (X8)
Y1
MIN
MILLIMETERS
NOM
1.27 BSC
5.40
MAX
0.60
1.55
Notes:
1. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
Microchip Technology Drawing C04-2057-SN Rev E
2009-2019 Microchip Technology Inc.
DS20002141C-page 27
MCP6L91/1R/2/4
14-Lead Plastic Small Outline (SL) - Narrow, 3.90 mm Body [SOIC]
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2X
0.10 C A–B
D
A
NOTE 5
D
N
E
2
E2
2
E1
E
2X
0.10 C D
NOTE 1
1
2
2X N/2 TIPS
0.20 C
3
e
NX b
B
0.25
NOTE 5
C A–B D
TOP VIEW
0.10 C
C
A A2
SEATING
PLANE
14X
A1
h
0.10 C
SIDE VIEW
h
R0.13
H
R0.13
c
SEE VIEW C
L
VIEW A–A
(L1)
VIEW C
Microchip Technology Drawing No. C04-065-SL Rev D Sheet 1 of 2
DS20002141C-page 28
2009-2019 Microchip Technology Inc.
MCP6L91/1R/2/4
14-Lead Plastic Small Outline (SL) - Narrow, 3.90 mm Body [SOIC]
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Units
Dimension Limits
Number of Pins
N
e
Pitch
Overall Height
A
Molded Package Thickness
A2
§
Standoff
A1
Overall Width
E
Molded Package Width
E1
Overall Length
D
Chamfer (Optional)
h
Foot Length
L
Footprint
L1
Lead Angle
Foot Angle
c
Lead Thickness
Lead Width
b
Mold Draft Angle Top
Mold Draft Angle Bottom
MIN
1.25
0.10
0.25
0.40
0°
0°
0.10
0.31
5°
5°
MILLIMETERS
NOM
14
1.27 BSC
6.00 BSC
3.90 BSC
8.65 BSC
1.04 REF
-
MAX
1.75
0.25
0.50
1.27
8°
0.25
0.51
15°
15°
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. § Significant Characteristic
3. Dimension D does not include mold flash, protrusions or gate burrs, which shall
not exceed 0.15 mm per end. Dimension E1 does not include interlead flash
or protrusion, which shall not exceed 0.25 mm per side.
4. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
5. Datums A & B to be determined at Datum H.
Microchip Technology Drawing No. C04-065-SL Rev D Sheet 2 of 2
2009-2019 Microchip Technology Inc.
DS20002141C-page 29
MCP6L91/1R/2/4
14-Lead Plastic Small Outline (SL) - Narrow, 3.90 mm Body [SOIC]
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
14
SILK SCREEN
C
Y
1
2
X
E
RECOMMENDED LAND PATTERN
Units
Dimension Limits
E
Contact Pitch
Contact Pad Spacing
C
Contact Pad Width (X14)
X
Contact Pad Length (X14)
Y
MIN
MILLIMETERS
NOM
1.27 BSC
5.40
MAX
0.60
1.55
Notes:
1. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
Microchip Technology Drawing No. C04-2065-SL Rev D
DS20002141C-page 30
2009-2019 Microchip Technology Inc.
MCP6L91/1R/2/4
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2009-2019 Microchip Technology Inc.
DS20002141C-page 31
MCP6L91/1R/2/4
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS20002141C-page 32
2009-2019 Microchip Technology Inc.
MCP6L91/1R/2/4
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2009-2019 Microchip Technology Inc.
DS20002141C-page 33
MCP6L91/1R/2/4
NOTES:
DS20002141C-page 34
2009-2019 Microchip Technology Inc.
MCP6L91/1R/2/4
APPENDIX A:
REVISION HISTORY
Revision C (October 2019)
The following is the list of modifications:
1.
Updated Section 6.0 “Packaging
Information”.
Revision B (September 2011)
The following is the list of modifications:
2.
3.
Updated the value for the Current at Output and
Supply Pins parameter in the Section 1.1
“Absolute Maximum Ratings†”section.
Added Section 5.1 “SPICE Macro Model”.
Revision A (March 2009)
• Original Release of this Document.
2009-2019 Microchip Technology Inc.
DS20002141C-page 35
MCP6L91/1R/2/4
NOTES:
DS20002141C-page 36
2009-2019 Microchip Technology Inc.
MCP6L91/1R/2/4
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
PART NO.
X
/XX
Device
Temperature
Range
Package
Device:
MCP6L91T:
MCP6L91RT:
MCP6L92T:
MCP6L94T:
Single Op Amp (Tape and Reel)
(SOT-23, SOIC, MSOP)
Single Op Amp (Tape and Reel) (SOT-23)
Dual Op Amp (Tape and Reel)
(SOIC, MSOP)
Quad Op Amp (Tape and Reel)
(SOIC, TSSOP)
Temperature Range:
E
= -40°C to +125°C
Package:
OT
MS
SN
SL
ST
=
=
=
=
=
Plastic Small Outline Transistor (SOT-23), 5-Lead
Plastic MSOP, 8-Lead
Plastic SOIC (3.90 mm body), 8-Lead
Plastic SOIC (3.90 mm body), 14-Lead
Plastic TSSOP (4.4 mm body), 14-Lead
Examples:
a) MCP6L91T-E/OT:
Tape and Reel,
Extended Temperature,
5-Lead SOT-23 Package.
b) MCP6L91T-E/MS: Tape and Reel,
Extended Temperature,
8-Lead MSOP Package.
c) MCP6L91T-E/SN: Tape and Reel,
Extended Temperature,
8-Lead SOIC Package.
a) MCP6L91RT-E/OT: Tape and Reel,
Extended Temperature,
5-Lead SOT-23 Package.
a) MCP6L92T-E/MS: Tape and Reel,
Extended Temperature,
8-Lead MSOP Package.
b) MCP6L92T-E/SN: Tape and Reel,
Extended Temperature,
8-Lead SOIC Package.
a) MCP6L94T-E/SL:
b) MCP6L94T-E/ST:
2009-2019 Microchip Technology Inc.
Tape and Reel,
Extended Temperature,
14-Lead SOIC Package.
Tape and Reel,
Extended Temperature,
14-Lead TSSOP Package.
DS20002141C-page 37
MCP6L91/1R/2/4
NOTES:
DS20002141C-page 38
2009-2019 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
•
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights unless otherwise stated.
Trademarks
The Microchip name and logo, the Microchip logo, Adaptec,
AnyRate, AVR, AVR logo, AVR Freaks, BesTime, BitCloud, chipKIT,
chipKIT logo, CryptoMemory, CryptoRF, dsPIC, FlashFlex,
flexPWR, HELDO, IGLOO, JukeBlox, KeeLoq, Kleer, LANCheck,
LinkMD, maXStylus, maXTouch, MediaLB, megaAVR, Microsemi,
Microsemi logo, MOST, MOST logo, MPLAB, OptoLyzer,
PackeTime, PIC, picoPower, PICSTART, PIC32 logo, PolarFire,
Prochip Designer, QTouch, SAM-BA, SenGenuity, SpyNIC, SST,
SST Logo, SuperFlash, Symmetricom, SyncServer, Tachyon,
TempTrackr, TimeSource, tinyAVR, UNI/O, Vectron, and XMEGA
are registered trademarks of Microchip Technology Incorporated in
the U.S.A. and other countries.
APT, ClockWorks, The Embedded Control Solutions Company,
EtherSynch, FlashTec, Hyper Speed Control, HyperLight Load,
IntelliMOS, Libero, motorBench, mTouch, Powermite 3, Precision
Edge, ProASIC, ProASIC Plus, ProASIC Plus logo, Quiet-Wire,
SmartFusion, SyncWorld, Temux, TimeCesium, TimeHub,
TimePictra, TimeProvider, Vite, WinPath, and ZL are registered
trademarks of Microchip Technology Incorporated in the U.S.A.
Adjacent Key Suppression, AKS, Analog-for-the-Digital Age, Any
Capacitor, AnyIn, AnyOut, BlueSky, BodyCom, CodeGuard,
CryptoAuthentication, CryptoAutomotive, CryptoCompanion,
CryptoController, dsPICDEM, dsPICDEM.net, Dynamic Average
Matching, DAM, ECAN, EtherGREEN, In-Circuit Serial
Programming, ICSP, INICnet, Inter-Chip Connectivity, JitterBlocker,
KleerNet, KleerNet logo, memBrain, Mindi, MiWi, MPASM, MPF,
MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach,
Omniscient Code Generation, PICDEM, PICDEM.net, PICkit,
PICtail, PowerSmart, PureSilicon, QMatrix, REAL ICE, Ripple
Blocker, SAM-ICE, Serial Quad I/O, SMART-I.S., SQI,
SuperSwitcher, SuperSwitcher II, Total Endurance, TSHARC,
USBCheck, VariSense, ViewSpan, WiperLock, Wireless DNA, and
ZENA are trademarks of Microchip Technology Incorporated in the
U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated in
the U.S.A.
The Adaptec logo, Frequency on Demand, Silicon Storage
Technology, and Symmcom are registered trademarks of Microchip
Technology Inc. in other countries.
GestIC is a registered trademark of Microchip Technology Germany
II GmbH & Co. KG, a subsidiary of Microchip Technology Inc., in
other countries.
All other trademarks mentioned herein are property of their
respective companies.
© 2009-2019, Microchip Technology Incorporated, All Rights
Reserved.
For information regarding Microchip’s Quality Management Systems,
please visit www.microchip.com/quality.
2009-2019 Microchip Technology Inc.
ISBN: 978-1-5224-5291-1
DS20002141C-page 39
Worldwide Sales and Service
AMERICAS
ASIA/PACIFIC
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EUROPE
Corporate Office
2355 West Chandler Blvd.
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Technical Support:
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Web Address:
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Canada - Toronto
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DS20002141C-page 40
China - Xiamen
Tel: 86-592-2388138
China - Zhuhai
Tel: 86-756-3210040
Germany - Garching
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Germany - Haan
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2009-2019 Microchip Technology Inc.
05/14/19
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