MCP6S26T-I/SL

MCP6S21/2/6/8 Single-Ended, Rail-to-Rail I/O, Low Gain PGA Features Description • Multiplexed Inputs: 1, 2, 6 or 8 channels • 8 Gain Selections: - +1, +2, +4, +5, +8, +10, +16 or +32 V/V • Serial Peripheral Interface (SPI) • Rail-to-Rail Input and Output • Low Gain Error: ±1% (max) • Low Offset: ±275 µV (max) • High Bandwidth: 2 to 12 MHz (typ) • Low Noise: 10 nV/Hz @ 10 kHz (typ) • Low Supply Current: 1.0 mA (typ) • Single Supply: 2.5V to 5.5V The Microchip Technology Inc. MCP6S21/2/6/8 are analog Programmable Gain Amplifiers (PGA). They can be configured for gains from +1 V/V to +32 V/V and the input multiplexer can select one of up to eight channels through an SPI port. The serial interface can also put the PGA into shutdown to conserve power. These PGAs are optimized for high speed, low offset voltage and single-supply operation with rail-to-rail input and output capability. These specifications support single supply applications needing flexible performance or multiple inputs. The one channel MCP6S21 and the two channel MCP6S22 are available in 8-pin PDIP, SOIC and MSOP packages. The six channel MCP6S26 is available in 14-pin PDIP, SOIC and TSSOP packages. The eight channel MCP6S28 is available in 16-pin PDIP and SOIC packages. All parts are fully specified from -40°C to +85°C. Typical Applications • • • • • • A/D Converter Driver Multiplexed Analog Applications Data Acquisition Industrial Instrumentation Test Equipment Medical Instrumentation Block Diagram VDD Package Types MCP6S22 PDIP, SOIC, MSOP VOUT 1 8 VDD VOUT 1 8 VDD CH0 2 7 SCK CH0 2 7 SCK VREF 3 6 SI CH1 3 6 SI VSS 4 5 CS VSS 4 5 CS MCP6S26 PDIP, SOIC, TSSOP MCP6S28 PDIP, SOIC VOUT 1 14 VDD VOUT 1 16 VDD CH0 2 13 SCK CH0 2 15 SCK CH1 3 12 SO CH1 3 14 SO CH2 4 11 SI CH2 4 13 SI CH3 5 10 CS CH3 5 12 CS CH4 6 9 VSS CH4 6 CH5 7 8 VREF CH5 7 11 VSS 10 VREF CH6 8 9 CH7  2003-2012 Microchip Technology Inc. MUX CS SI SO SCK SPI™ Logic + VOUT RF Gain Switches 8 RG Resistor Ladder (RLAD) MCP6S21 PDIP, SOIC, MSOP CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 POR VSS VREF DS21117B-page 1 MCP6S21/2/6/8 1.0 ELECTRICAL CHARACTERISTICS PIN FUNCTION TABLE Name Absolute Maximum Ratings † VDD - VSS .........................................................................7.0V Function VOUT Analog Output CH0-CH7 Analog Inputs All inputs and outputs ....................... VSS - 0.3V to VDD +0.3V VSS Negative Power Supply Difference Input voltage ........................................ |VDD - VSS| VDD Positive Power Supply Output Short Circuit Current...................................continuous SCK Current at Input Pin 2 mA SI Current at Output and Supply Pins  30 mA SO SPI Serial Data Output Storage temperature .....................................-65°C to +150°C CS SPI Chip Select Junction temperature .................................................. +150°C VREF ESD protection on all pins (HBM;MM) 2 kV; 200V SPI Clock Input SPI Serial Data Input External Reference Pin † Notice: Stresses above those listed under "Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. DC CHARACTERISTICS Electrical Specifications: Unless otherwise indicated, TA = +25°C, VDD = +2.5V to +5.5V, VSS = GND, VREF = VSS, G = +1 V/V, Input = CH0 = (0.3V)/G, CH1 to CH7 = 0.3V, RL = 10 kto VDD/2, SI and SCK are tied low and CS is tied high. Parameters Sym Min Typ Max Units Conditions Amplifier Input Input Offset Voltage Input Offset Voltage Drift Power Supply Rejection Ratio VOS -275 — +275 µV VOS/TA — ±4 — µV/°C G = +1, VDD = 4.0V TA = -40 to +85°C PSRR 70 85 — dB G = +1 (Note 1) Input Bias Current IB — ±1 — pA CHx = VDD/2 Input Bias Current over Temperature IB — — 250 pA TA = -40 to +85°C, CHx = VDD/2 ZIN — 1013||15 — ||pF VIVR VSS0.3 — VDD+0.3 V Input Impedance Input Voltage Range Amplifier Gain Nominal Gains — — 1 to 32 — V/V gE -0.1 — +0.1 % G  +2 gE -1.0 — +1.0 % G = +1 G/TA — ±0.0002 — %/°C TA = -40 to +85°C G  +2 G/TA — ±0.0004 — %/°C TA = -40 to +85°C RLAD 3.4 4.9 6.4 k RLAD/TA — +0.028 — %/°C DC Output Non-linearity G = +1 VONL — ±0.003 — % of FSR VOUT = 0.3V to VDD 0.3V, VDD = 5.0V G  +2 VONL — ±0.001 — % of FSR VOUT = 0.3V to VDD 0.3V, VDD = 5.0V VOH, VOL VSS+20 — VDD-100 VSS+60 — VDD-60 — ±30 — DC Gain Error DC Gain Drift G = +1 Internal Resistance Internal Resistance over Temperature +1, +2, +4, +5, +8, +10, +16 or +32 VOUT  0.3V to VDD 0.3V VOUT  0.3V to VDD 0.3V (Note 1) (Note 1) TA = -40 to +85°C Amplifier Output Maximum Output Voltage Swing Short-Circuit Current IO(SC) mV G  +2; 0.5V output overdrive G  +2; 0.5V output overdrive, VREF = VDD/2 mA Note 1: RLAD (RF + RG in Figure 4-1) connects VREF, VOUT and the inverting input of the internal amplifier. The MCP6S22 has VREF tied internally to VSS, so VSS is coupled to the internal amplifier and the PSRR spec describes PSRR+ only. We recommend the MCP6S22’s VSS pin be tied directly to ground to avoid noise problems. 2: IQ includes current in RLAD (typically 60 µA at VOUT = 0.3V). Both IQ and IQ_SHDN exclude digital switching currents. 3: The output goes Hi-Z and the registers reset to their defaults; see Section 5.4, “Power-On Reset”. DS21117B-page 2  2003-2012 Microchip Technology Inc. MCP6S21/2/6/8 DC CHARACTERISTICS (CONTINUED) Electrical Specifications: Unless otherwise indicated, TA = +25°C, VDD = +2.5V to +5.5V, VSS = GND, VREF = VSS, G = +1 V/V, Input = CH0 = (0.3V)/G, CH1 to CH7 = 0.3V, RL = 10 kto VDD/2, SI and SCK are tied low and CS is tied high. Parameters Sym Min Typ Max Units Conditions VDD 2.5 — 5.5 V IQ 0.5 1.0 1.35 mA IO = 0 (Note 2) IQ_SHDN — 0.5 1.0 µA IO = 0 (Note 2) VPOR 1.2 1.7 2.2 V (Note 3) VPOR/T — -3.0 — mV/°C Power Supply Supply Voltage Quiescent Current Quiescent Current, Shutdown mode Power-On Reset POR Trip Voltage POR Trip Voltage Drift TA = -40°C to+85°C Note 1: RLAD (RF + RG in Figure 4-1) connects VREF, VOUT and the inverting input of the internal amplifier. The MCP6S22 has VREF tied internally to VSS, so VSS is coupled to the internal amplifier and the PSRR spec describes PSRR+ only. We recommend the MCP6S22’s VSS pin be tied directly to ground to avoid noise problems. 2: IQ includes current in RLAD (typically 60 µA at VOUT = 0.3V). Both IQ and IQ_SHDN exclude digital switching currents. 3: The output goes Hi-Z and the registers reset to their defaults; see Section 5.4, “Power-On Reset”. AC CHARACTERISTICS Electrical Specifications: Unless otherwise indicated, TA = +25°C, VDD = +2.5V to +5.5V, VSS = GND, VREF = VSS, G = +1 V/V, Input = CH0 =(0.3V)/G, CH1 to CH7=0.3V, RL = 10 kto VDD/2, CL = 60 pF, SI and SCK are tied low, and CS is tied high. Parameters Sym Min Typ Max Units Conditions Frequency Response All gains; VOUT < 100 mVP-P (Note 1) -3 dB Bandwidth BW — 2 to 12 — MHz Gain Peaking GPK — 0 — dB All gains; VOUT < 100 mVP-P f = 1 kHz, G = +1 V/V THD+N — 0.0015 — % VOUT = 1.5V ± 1.0VPK, VDD = 5.0V, BW = 22 kHz f = 1 kHz, G = +4 V/V THD+N — 0.0058 — % VOUT = 1.5V ± 1.0VPK, VDD = 5.0V, BW = 22 kHz f = 1 kHz, G = +16 V/V THD+N — 0.023 — % VOUT = 1.5V ± 1.0VPK, VDD = 5.0V, BW = 22 kHz f = 20 kHz, G = +1 V/V THD+N — 0.0035 — % VOUT = 1.5V ± 1.0VPK, VDD = 5.0V, BW = 80 kHz f = 20 kHz, G = +4 V/V THD+N — 0.0093 — % VOUT = 1.5V ± 1.0VPK, VDD = 5.0V, BW = 80 kHz f = 20 kHz, G = +16 V/V THD+N — 0.036 — % VOUT = 1.5V ± 1.0VPK, VDD = 5.0V, BW = 80 kHz SR — 4.0 — V/µs G = 1, 2 — 11 — V/µs G = 4, 5, 8, 10 — 22 — V/µs G = 16, 32 — 3.2 — µVP-P — 26 — Total Harmonic Distortion plus Noise Step Response Slew Rate Noise Input Noise Voltage Eni f = 0.1 Hz to 10 kHz (Note 2) f = 0.1 Hz to 200 kHz (Note 2) Input Noise Voltage Density eni — 10 — nV/Hz f = 10 kHz (Note 2) Input Noise Current Density ini — 4 — fA/Hz f = 10 kHz Note 1: See Table 4-1 for a list of typical numbers. 2: Eni and eni include ladder resistance noise. See Figure 2-33 for eni vs. G data.  2003-2012 Microchip Technology Inc. DS21117B-page 3 MCP6S21/2/6/8 DIGITAL CHARACTERISTICS Electrical Specifications: Unless otherwise indicated, TA = +25°C, VDD = +2.5V to +5.5V, VSS = GND, VREF = VSS, G = +1 V/V, Input = CH0 = (0.3V)/G, CH1 to CH7 = 0.3V, RL = 10 kto VDD/2, CL = 60 pF, SI and SCK are tied low, and CS is tied high. Parameters Sym Min Typ Max Units Conditions SPI Inputs (CS, SI, SCK) Logic Threshold, Low VIL 0 — 0.3VDD V Input Leakage Current IIL -1.0 — +1.0 µA Logic Threshold, High VIH 0.7VDD — VDD V Amplifier Output Leakage Current — -1.0 — +1.0 µA In Shutdown mode SPI Output (SO, for MCP6S26 and MCP6S28) Logic Threshold, Low VOL VSS — VSS+0.4 V IOL = 2.1 mA, VDD = 5V Logic Threshold, High VOH VDD-0.5 — VDD V IOH = -400 µA Pin Capacitance CPIN — 10 — pF All digital I/O pins Input Rise/Fall Times (CS, SI, SCK) tRFI — — 2 µs Note 1 Output Rise/Fall Times (SO) tRFO — 5 — ns MCP6S26 and MCP6S28 CS high time tCSH 40 — — ns SCK edge to CS fall setup time tCS0 10 — — ns CS fall to first SCK edge setup time tCSSC 40 — — ns SCK Frequency fSCK — — 10 MHz tHI 40 — — ns SPI Timing SCK high time SCK edge when CS is high VDD = 5V (Note 2) tLO 40 — — ns tSCCS 30 — — ns tCS1 100 — — ns SI set-up time tSU 40 — — ns SI hold time tHD 10 — — ns SCK to SO valid propagation delay tDO — — 80 ns MCP6S26 and MCP6S28 CS rise to SO forced to zero tSOZ — — 80 ns MCP6S26 and MCP6S28 Channel Select Time tCH — 1.5 — µs CHx = 0.6V, CHy =0.3V, G = 1, CHx to CHy select CS = 0.7VDD to VOUT 90% point Gain Select Time tG — 1 — µs CHx = 0.3V, G = 5 to G = 1 select, CS = 0.7VDD to VOUT 90% point Out of Shutdown mode (CS goes high) to Amplifier Output Turn-on Time tON — 3.5 10 µs CS = 0.7VDD to VOUT 90% point Into Shutdown mode (CS goes high) to Amplifier Output High-Z Turn-off Time tOFF — 1.5 — µs CS = 0.7VDD to VOUT 90% point Power-On Reset power-up time tRPU — 30 — µs VDD = VPOR - 0.1V to VPOR + 0.1V, 50% VDD to 90% VOUT point Power-On Reset power-down time tRPD — 10 — µs VDD = VPOR + 0.1V to VPOR - 0.1V, 50% VDD to 90% VOUT point SCK low time SCK last edge to CS rise setup time CS rise to SCK edge setup time SCK edge when CS is high Channel and Gain Select Timing Shutdown Mode Timing POR Timing Note 1: Not tested in production. Set by design and characterization. 2: When using the device in the daisy chain configuration, maximum clock frequency is determined by a combination of propagation delay time (tDO  80 ns), data input setup time (tSU  40 ns), SCK high time (tHI  40 ns), and SCK rise and fall times of 5 ns. Maximum fSCK is, therefore,  5.8 MHz. DS21117B-page 4  2003-2012 Microchip Technology Inc. MCP6S21/2/6/8 TEMPERATURE CHARACTERISTICS Electrical Specifications: Unless otherwise indicated, VDD = +2.5V to +5.5V, VSS = GND. Parameters Sym Min Typ Max Units Specified Temperature Range TA -40 — +85 °C Operating Temperature Range TA -40 — +125 °C Storage Temperature Range TA -65 — +150 °C Thermal Resistance, 8L-PDIP JA — 85 — °C/W Thermal Resistance, 8L-SOIC JA — 163 — °C/W Thermal Resistance, 8L-MSOP JA — 206 — °C/W Thermal Resistance, 14L-PDIP JA — 70 — °C/W Thermal Resistance, 14L-SOIC JA — 120 — °C/W Thermal Resistance, 14L-TSSOP JA — 100 — °C/W Thermal Resistance, 16L-PDIP JA — 70 — °C/W Thermal Resistance, 16L-SOIC JA — 90 — °C/W Conditions Temperature Ranges (Note 1) Thermal Package Resistances Note 1: The MCP6S21/2/6/8 family of PGAs operates over this extended temperature range, but with reduced performance. Operation in this range must not cause TJ to exceed the Maximum Junction Temperature (150°C). CS CS tCH VOUT FIGURE 1-1: Diagram. tG 0.6V Channel Select Timing CS VOUT Gain Select Timing VPOR - 0.1V tOFF Hi-Z VPOR + 0.1V VPOR - 0.1V tRPU Hi-Z 0.3V 1.0 mA (typ) ISS 0.3V FIGURE 1-3: Diagram. VDD tON 1.5V VOUT 0.3V VOUT ISS tRPD Hi-Z Hi-Z 0.3V 1.0 mA (typ) 500 nA (typ) 500 nA (typ) FIGURE 1-2: PGA Shutdown timing diagram (must enter correct commands before CS goes high).  2003-2012 Microchip Technology Inc. FIGURE 1-4: POR power-up and powerdown timing diagram. DS21117B-page 5 MCP6S21/2/6/8 tCSH CS tCSSC tSCCS tCS1 tCS0 tLO tHI SCK tSU tHD 1/fSCK SI tDO tSOZ SO (first 16 bits out are always zeros) FIGURE 1-5: Detailed SPI Serial Interface Timing, SPI 0,0 mode. tCSH CS tCSSC tSCCS tCS1 tHI tCS0 tLO SCK tSU tHD 1/fSCK SI tDO tSOZ SO (first 16 bits out are always zeros) FIGURE 1-6: DS21117B-page 6 Detailed SPI Serial Interface Timing, SPI 1,1 mode.  2003-2012 Microchip Technology Inc. MCP6S21/2/6/8 1.1 DC Output Voltage Specs / Model 1.1.1 VOUT (V) IDEAL MODEL The ideal PGA output voltage (VOUT) is: EQUATION V2 VDD-0.3 VREF = V SS = 0V O UT O _l in V ear O _i de al V O_ideal = GV IN VDD V V where: G is the nominal gain (see Figure 1-7). This equation holds when there are no gain or offset errors and when the VREF pin is tied to a low impedance source ( VPOR). A 0.1 µF bypass capacitor mounted as close as possible to the VDD pin provides additional transient immunity. DS21117B-page 24  2003-2012 Microchip Technology Inc. MCP6S21/2/6/8 6.0 APPLICATIONS INFORMATION 6.1 Changing External Reference Voltage Figure 6-1 shows a MCP6S21 with the VREF pin at 2.5V and VDD = 5.0V. This allows the PGA to amplify signals centered on 2.5V, instead of ground-referenced signals. The voltage reference MCP1525 is buffered by a MCP6021, which gives a low output impedance reference voltage from DC to high frequencies. The source driving the VREF pin should have an output impedance of  0.1 to maintain reasonable gain accuracy. VDD VDD VIN MCP1525 VDD VOUT MCP6S21 VREF For CL  100 pF, a good estimate for RISO is 50. This value can be fine-tuned on the bench. Adjust RISO so that the step response overshoot and frequency response peaking are acceptable at all gains. 6.3 Layout Considerations Good PC board layout techniques will help achieve the performance shown in the Electrical Characteristics and Typical Performance Curves. It will also help minimize EMC (Electro-Magnetic Compatibility) issues. 6.3.1 COMPONENT PLACEMENT Separate circuit functions; digital from analog, low speed from high speed, and low power from high power, as this will reduce crosstalk. Keep sensitive traces short and straight, separating them from interfering components and traces. This is especially important for high frequency (low rise time) signals. Use a 0.1 µF supply bypass capacitor within 0.1 inch (2.5 mm) of the VDD pin. It must connect directly to the ground plane. A multi-layer ceramic chip capacitor, or high-frequency equivalent, works best. 2.5V REF MCP6021 6.3.2 1 µF FIGURE 6-1: PGA with Different External Reference Voltage. 6.2 Capacitive Load and Stability Large capacitive loads can cause both stability problems and reduced bandwidth for the MCP6S21/2/6/8 family of PGAs (Figure 2-17 and Figure 2-18). This happens because a large load capacitance decreases the internal amplifier’s phase margin and bandwidth. If the PGA drives a large capacitive load, the circuit in Figure 6-2 can be used. A small series resistor (RISO) at the VOUT improves the phase margin by making the load resistive at high frequencies. It will not, however, improve the bandwidth. The input pins of the MCP6S21/2/6/8 family of operational amplifiers (op amps) are high-impedance. This makes them especially susceptible to capacitively-coupled noise. Using a ground plane helps reduce this problem. When noise is capacitively-coupled, the ground plane provides additional shunt capacitance to ground. When noise is magnetically coupled, the ground plane reduces the mutual inductance between traces. Increasing the separation between traces makes a significant difference. Changing the direction of one of the traces can also reduce magnetic coupling. It may help to locate guard traces next to the victim trace. They should be on both sides of the victim trace and be as close as possible. Connect the guard traces to the ground plane at both ends, and in the middle, of long traces. 6.3.3 RISO VIN MCP6S2X VOUT CL FIGURE 6-2: Capacitive Loads. PGA Circuit for Large  2003-2012 Microchip Technology Inc. SIGNAL COUPLING HIGH FREQUENCY ISSUES Because the MCP6S21/2/6/8 PGAs reach unity gain near 64 MHz when G = 16 and 32, it is important to use good PCB layout techniques. Any parasitic coupling at high frequency might cause undesired peaking. Filtering high frequency signals (i.e., fast edge rates) can help. To minimize high frequency problems: • • • • • Use complete ground and power planes Use HF, surface mount components Provide clean supply voltages and bypassing Keep traces short and straight Try a linear power supply (e.g., an LDO) DS21117B-page 25 MCP6S21/2/6/8 6.4 Typical Applications 6.4.1 VIN  GAIN RANGING MCP6021 Figure 6-3 shows a circuit that measures the current IX. It benefits from changing the gain on the PGA. Just as a hand-held multimeter uses different measurement ranges to obtain the best results, this circuit makes it easy to set a high gain for small signals and a low gain for large signals. As a result, the required dynamic range at the PGA’s output is less than at its input (by up to 30 dB).  10.0 k VOUT MCP6S21 1.11 k FIGURE 6-5: MCP6S2X IX 6.4.3 VOUT FIGURE 6-3: Wide Dynamic Range Current Measurement Circuit. SHIFTED GAIN RANGE PGA Figure 6-4 shows a circuit using an MCP6021 at a gain of +10 in front of an MCP6S21. This changes the overall gain range to +10 V/V to +320 V/V (from +1 V/V to +32 V/V). VIN EXTENDED GAIN RANGE PGA Figure 6-6 gives a +1 V/V to +1024 V/V gain range, which is much greater than the range for a single PGA (+1 V/V to +32 V/V). The first PGA provides input multiplexing capability, while the second PGA only needs one input. These devices can be daisy chained (Section 5.3, “Daisy Chain Configuration”). RS 6.4.2 PGA with lower gain range. MCP6S21 VOUT  PGA with Modified Gain It is also easy to shift the gain range to lower gains (see Figure 6-6). The MCP6021 acts as a unity gain buffer, and the resistive voltage divider shifts the gain range down to +0.1 V/V to +3.2 V/V (from +1 V/V to +32 V/V). DS21117B-page 26 6.4.4 MCP6S21 VOUT PGA with Extended Gain MULTIPLE SENSOR AMPLIFIER The multiple channel PGAs (except the MCP6S21) allow the user to select which sensor appears on the output (see Figure 6-7). These devices can also change the gain to optimize performance for each sensor. 10.0 k 1.11 k FIGURE 6-4: Range. MCP6S28 FIGURE 6-6: Range.  MCP6021 VIN Sensor # 0 Sensor # 1 MCP6S26 VOUT Sensor # 5 FIGURE 6-7: Inputs. PGA with Multiple Sensor  2003-2012 Microchip Technology Inc. MCP6S21/2/6/8 6.4.5 6.4.7 EXPANDED INPUT PGA Figure 6-8 shows cascaded MCP6S28s that provide up to 15 input channels. Obviously, Sensors #7-14 have a high total gain range available, as explained in Section 6.4.3, “Extended Gain Range”. These devices can be daisy chained (Section 5.3, “Daisy Chain Configuration”). ADC DRIVER The family of PGA’s is well suited for driving Analog-toDigital Converters (ADC). The binary gains (1, 2, 4, 8, 16 and 32) effectively add five more bits to the input range (see Figure 6-10). This works well for applications needing relative accuracy more than absolute accuracy (e.g., power monitoring). Lowpass Filter Sensors # 0-6 MCP6S28 Sensors # 7-14 VOUT VIN 12 MCP6S28 FIGURE 6-8: PGA with Expanded Inputs. PIC MCU WITH EXPANDED INPUT CAPABILITY Figure 6-9 shows an MCP6S28 driving an analog input to a PIC microcontroller. This greatly expands the input capacity of the microcontroller, while adding the ability to select the appropriate gain for each source. VIN OUT MCP6S28 FIGURE 6-10: 6.4.6 MCP3201 MCP6S28 PGA as an ADC Driver. At low gains, the ADC’s Signal-to-Noise Ratio (SNR) will dominate since the PGAs input noise voltage density is so low (10 nV/Hz @ 10 kHz, typ.). At high gains, the PGA’s noise will dominate the SNR, but its low noise supports most applications. Again, these PGAs add the flexibility of selecting the best gain for an application. The low pass filter in the block diagram reduces the integrated noise at the MCP6S28’s output and serves as an anti-aliasing filter. This filter may be designed using Microchip’s FilterLab® software, available at www.microchip.com. PIC® Microcontroller SPI™ FIGURE 6-9: Microcontroller. Expanded Input for a PIC®  2003-2012 Microchip Technology Inc. DS21117B-page 27 MCP6S21/2/6/8 7.0 PACKAGING INFORMATION 7.1 Package Marking Information 8-Lead PDIP (300 mil) (MCP6S21, MCP6S22) XXXXXXXX XXXXXNNN YYWW MCP6S21 I/P256 0345 8-Lead SOIC (150 mil) (MCP6S21, MCP6S22) XXXXXXXX XXXXYYWW NNN Note: * Example: MCP6S21I 345256 XXXXX YWWNNN XX...X YY WW NNN Example: MCP6S21 I/SN0345 256 8-Lead MSOP (MCP6S21, MCP6S22) Legend: Example: Customer specific information* Year code (last 2 digits of calendar year) Week code (week of January 1 is week ‘01’) Alphanumeric traceability code In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line thus limiting the number of available characters for customer specific information. Standard marking consists of Microchip part number, year code, week code, traceability code (facility code, mask rev#, and assembly code). For marking beyond this, certain price adders apply. Please check with your Microchip Sales Office. DS21117B-page 28  2003-2012 Microchip Technology Inc. MCP6S21/2/6/8 Package Marking Information (Con’t) 14-Lead PDIP (300 mil) (MCP6S26) XXXXXXXXXXXXXX XXXXXXXXXXXXXX YYWWNNN 14-Lead SOIC (150 mil) (MCP6S26) XXXXXXXXXXX XXXXXXXXXXX YYWWNNN 14-Lead TSSOP (4.4mm) (MCP6S26) XXXXXXXX Example: MCP6S26-I/P XXXXXXXXXXXXXX 0345256 Example: MCP6S26ISL XXXXXXXXXXXXXXXXXXXXXXXXX 0345256 Example: MCP6S26IST YYWW 0345 NNN 256  2003-2012 Microchip Technology Inc. DS21117B-page 29 MCP6S21/2/6/8 Package Marking Information (Con’t) 16-Lead PDIP (300 mil) (MCP6S28) Example: XXXXXXXXXXXXXX XXXXXXXXXXXXXX YYWWNNN 16-Lead SOIC (150 mil) (MCP6S28) XXXXXXXXXXXXX XXXXXXXXXXXXX YYWWNNN DS21117B-page 30 MCP6S28-I/P XXXXXXXXXXXXXX 0345256 Example: MCP6S28-I/SL XXXXXXXXXXXXXXXXXXXXXXXX 0345256  2003-2012 Microchip Technology Inc. MCP6S21/2/6/8 8-Lead Plastic Dual In-line (P) – 300 mil (PDIP) Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging E1 D 2 n 1  E A2 A L c A1  B1 p eB B Units Dimension Limits n p Number of Pins Pitch Top to Seating Plane Molded Package Thickness Base to Seating Plane Shoulder to Shoulder Width Molded Package Width Overall Length Tip to Seating Plane Lead Thickness Upper Lead Width Lower Lead Width Overall Row Spacing Mold Draft Angle Top Mold Draft Angle Bottom * Controlling Parameter § Significant Characteristic A A2 A1 E E1 D L c § B1 B eB   MIN .140 .115 .015 .300 .240 .360 .125 .008 .045 .014 .310 5 5 INCHES* NOM MAX 8 .100 .155 .130 .170 .145 .313 .250 .373 .130 .012 .058 .018 .370 10 10 .325 .260 .385 .135 .015 .070 .022 .430 15 15 MILLIMETERS NOM 8 2.54 3.56 3.94 2.92 3.30 0.38 7.62 7.94 6.10 6.35 9.14 9.46 3.18 3.30 0.20 0.29 1.14 1.46 0.36 0.46 7.87 9.40 5 10 5 10 MIN MAX 4.32 3.68 8.26 6.60 9.78 3.43 0.38 1.78 0.56 10.92 15 15 Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side. JEDEC Equivalent: MS-001 Drawing No. C04-018  2003-2012 Microchip Technology Inc. DS21117B-page 31 MCP6S21/2/6/8 8-Lead Plastic Small Outline (SN) – Narrow, 150 mil (SOIC) Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging E E1 p D 2 B n 1  h 45 c A2 A   L Units Dimension Limits n p Number of Pins Pitch Overall Height Molded Package Thickness Standoff § Overall Width Molded Package Width Overall Length Chamfer Distance Foot Length Foot Angle Lead Thickness Lead Width Mold Draft Angle Top Mold Draft Angle Bottom * Controlling Parameter § Significant Characteristic A A2 A1 E E1 D h L  c B   MIN .053 .052 .004 .228 .146 .189 .010 .019 0 .008 .013 0 0 A1 INCHES* NOM 8 .050 .061 .056 .007 .237 .154 .193 .015 .025 4 .009 .017 12 12 MAX .069 .061 .010 .244 .157 .197 .020 .030 8 .010 .020 15 15 MILLIMETERS NOM 8 1.27 1.35 1.55 1.32 1.42 0.10 0.18 5.79 6.02 3.71 3.91 4.80 4.90 0.25 0.38 0.48 0.62 0 4 0.20 0.23 0.33 0.42 0 12 0 12 MIN MAX 1.75 1.55 0.25 6.20 3.99 5.00 0.51 0.76 8 0.25 0.51 15 15 Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side. JEDEC Equivalent: MS-012 Drawing No. C04-057 DS21117B-page 32  2003-2012 Microchip Technology Inc. MCP6S21/2/6/8 8-Lead Plastic Micro Small Outline Package (MS) (MSOP) Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging E p E1 D 2 B n 1  A2 A c  A1 (F) L  INCHES Units Number of Pins Pitch Dimension Limits n p Overall Height MILLIMETERS* NOM MIN MAX NOM MIN .026 0.65 1.18 .044 A 0.86 0.97 4.67 4.90 .5.08 .122 2.90 3.00 3.10 .122 2.90 3.00 3.10 .022 .028 0.40 0.55 0.70 .037 .039 0.90 0.95 1.00 6 0 .006 .008 0.10 0.15 0.20 .012 .016 0.25 0.30 0.40 .038 0.76 .006 0.05 .193 .200 .114 .118 .114 .118 L .016 .035 Foot Angle F  Lead Thickness c .004 Lead Width B  .010 Mold Draft Angle Top Mold Draft Angle Bottom  Molded Package Thickness A2 .030 Standoff A1 .002 E .184 Molded Package Width E1 Overall Length D Foot Length Footprint (Reference) § Overall Width MAX 8 8 .034 0 0.15 6 7 7 7 7 *Controlling Parameter § Significant Characteristic Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" (0.254mm) per side. Drawing No. C04-111  2003-2012 Microchip Technology Inc. DS21117B-page 33 MCP6S21/2/6/8 14-Lead Plastic Dual In-line (P) – 300 mil (PDIP) Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging E1 D 2 n 1  E A2 A L c A1  B1 eB p B Units Dimension Limits n p MIN INCHES* NOM 14 .100 .155 .130 MAX MILLIMETERS NOM 14 2.54 3.56 3.94 2.92 3.30 0.38 7.62 7.94 6.10 6.35 18.80 19.05 3.18 3.30 0.20 0.29 1.14 1.46 0.36 0.46 7.87 9.40 5 10 5 10 MIN Number of Pins Pitch Top to Seating Plane A .140 .170 Molded Package Thickness A2 .115 .145 Base to Seating Plane A1 .015 Shoulder to Shoulder Width E .300 .313 .325 Molded Package Width E1 .240 .250 .260 Overall Length D .740 .750 .760 Tip to Seating Plane L .125 .130 .135 c Lead Thickness .008 .012 .015 Upper Lead Width B1 .045 .058 .070 Lower Lead Width B .014 .018 .022 Overall Row Spacing § eB .310 .370 .430  Mold Draft Angle Top 5 10 15  Mold Draft Angle Bottom 5 10 15 * Controlling Parameter § Significant Characteristic Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side. JEDEC Equivalent: MS-001 Drawing No. C04-005 DS21117B-page 34 MAX 4.32 3.68 8.26 6.60 19.30 3.43 0.38 1.78 0.56 10.92 15 15  2003-2012 Microchip Technology Inc. MCP6S21/2/6/8 14-Lead Plastic Small Outline (SL) – Narrow, 150 mil (SOIC) Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging E E1 p D 2 B n 1  h 45 c A2 A  A1 L  Units Dimension Limits n p Number of Pins Pitch Overall Height Molded Package Thickness Standoff § Overall Width Molded Package Width Overall Length Chamfer Distance Foot Length Foot Angle Lead Thickness Lead Width Mold Draft Angle Top Mold Draft Angle Bottom * Controlling Parameter § Significant Characteristic A A2 A1 E E1 D h L  c B   MIN .053 .052 .004 .228 .150 .337 .010 .016 0 .008 .014 0 0 INCHES* NOM 14 .050 .061 .056 .007 .236 .154 .342 .015 .033 4 .009 .017 12 12 MAX .069 .061 .010 .244 .157 .347 .020 .050 8 .010 .020 15 15 MILLIMETERS NOM 14 1.27 1.35 1.55 1.32 1.42 0.10 0.18 5.79 5.99 3.81 3.90 8.56 8.69 0.25 0.38 0.41 0.84 0 4 0.20 0.23 0.36 0.42 0 12 0 12 MIN MAX 1.75 1.55 0.25 6.20 3.99 8.81 0.51 1.27 8 0.25 0.51 15 15 Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side. JEDEC Equivalent: MS-012 Drawing No. C04-065  2003-2012 Microchip Technology Inc. DS21117B-page 35 MCP6S21/2/6/8 14-Lead Plastic Thin Shrink Small Outline (ST) – 4.4 mm (TSSOP) Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging E E1 p D 2 1 n B  A c   A1 L Units Dimension Limits n p Number of Pins Pitch Overall Height Molded Package Thickness Standoff § Overall Width Molded Package Width Molded Package Length Foot Length Foot Angle Lead Thickness Lead Width Mold Draft Angle Top Mold Draft Angle Bottom * Controlling Parameter § Significant Characteristic A A2 A1 E E1 D L  c B1   MIN .033 .002 .246 .169 .193 .020 0 .004 .007 0 0 INCHES NOM 14 .026 .035 .004 .251 .173 .197 .024 4 .006 .010 5 5 A2 MAX .043 .037 .006 .256 .177 .201 .028 8 .008 .012 10 10 MILLIMETERS* NOM MAX 14 0.65 1.10 0.85 0.90 0.95 0.05 0.10 0.15 6.25 6.38 6.50 4.30 4.40 4.50 4.90 5.00 5.10 0.50 0.60 0.70 0 4 8 0.09 0.15 0.20 0.19 0.25 0.30 0 5 10 0 5 10 MIN Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .005” (0.127mm) per side. JEDEC Equivalent: MO-153 Drawing No. C04-087 DS21117B-page 36  2003-2012 Microchip Technology Inc. MCP6S21/2/6/8 16-Lead Plastic Dual In-line (P) – 300 mil (PDIP) Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging E1 D 2 n  1 E A2 A L c  A1 B1 eB p B Units Dimension Limits n p MIN INCHES* NOM 16 .100 .155 .130 MAX MILLIMETERS NOM 16 2.54 3.56 3.94 2.92 3.30 0.38 7.62 7.94 6.10 6.35 18.80 19.05 3.18 3.30 0.20 0.29 1.14 1.46 .036 0.46 7.87 9.40 5 10 5 10 MIN Number of Pins Pitch Top to Seating Plane A .140 .170 Molded Package Thickness A2 .115 .145 Base to Seating Plane .015 A1 Shoulder to Shoulder Width E .300 .313 .325 Molded Package Width E1 .240 .250 .260 Overall Length D .740 .750 .760 Tip to Seating Plane L .125 .130 .135 c Lead Thickness .008 .012 .015 Upper Lead Width B1 .045 .058 .070 Lower Lead Width B .014 .018 .022 Overall Row Spacing § eB .310 .370 .430  Mold Draft Angle Top 5 10 15  Mold Draft Angle Bottom 5 10 15 * Controlling Parameter § Significant Characteristic Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side. JEDEC Equivalent: MS-001 Drawing No. C04-017  2003-2012 Microchip Technology Inc. MAX 4.32 3.68 8.26 6.60 19.30 3.43 0.38 1.78 0.56 10.92 15 15 DS21117B-page 37 MCP6S21/2/6/8 16-Lead Plastic Small Outline (SL) – Narrow 150 mil (SOIC) Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging E E1 p D 2 B n 1  h 45 c A2 A  L A1  Units Dimension Limits n p Number of Pins Pitch Overall Height Molded Package Thickness Standoff § Overall Width Molded Package Width Overall Length Chamfer Distance Foot Length Foot Angle Lead Thickness Lead Width Mold Draft Angle Top Mold Draft Angle Bottom * Controlling Parameter § Significant Characteristic A A2 A1 E E1 D h L  c B   INCHES* NOM 16 .050 .053 .061 .052 .057 .004 .007 .228 .237 .150 .154 .386 .390 .010 .015 .016 .033 0 4 .008 .009 .013 .017 0 12 0 12 MIN MAX .069 .061 .010 .244 .157 .394 .020 .050 8 .010 .020 15 15 MILLIMETERS NOM 16 1.27 1.35 1.55 1.32 1.44 0.10 0.18 5.79 6.02 3.81 3.90 9.80 9.91 0.25 0.38 0.41 0.84 0 4 0.20 0.23 0.33 0.42 0 12 0 12 MIN MAX 1.75 1.55 0.25 6.20 3.99 10.01 0.51 1.27 8 0.25 0.51 15 15 Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side. JEDEC Equivalent: MS-012 Drawing No. C04-108 DS21117B-page 38  2003-2012 Microchip Technology Inc. MCP6S21/2/6/8 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. -X /XX Device Temperature Range Package Device: Examples: a) MCP6S21-I/P: One Channel PGA, PDIP package. b) MCP6S21-I/SN: One Channel PGA, SOIC package. c) MCP6S21-I/MS: One Channel PGA, MSOP package. d) MCP6S22-I/MS: Two Channel PGA, MSOP package. e) MCP6S22T-I/MS: Tape and Reel, Two Channel PGA, MSOP package. MCP6S21: One Channel PGA MCP6S21T: One Channel PGA (Tape and Reel for SOIC and MSOP) MCP6S22: Two Channel PGA MCP6S22T: Two Channel PGA (Tape and Reel for SOIC and MSOP) MCP6S26: Six Channel PGA MCP6S26T: Six Channel PGA (Tape and Reel for SOIC and TSSOP) MCP6S28: Eight Channel PGA MCP6S28T: Eight Channel PGA (Tape and Reel for SOIC) f) MCP6S26-I/P: Six Channel PGA, PDIP package. g) MCP6S26-I/SN: Six Channel PGA, SOIC package. Temperature Range: I = -40°C to +85°C h) MCP6S26T-I/ST: Tape and Reel, Six Channel PGA, TSSOP package. Package: MS P SN SL ST = = = = = i) MCP6S28T-I/SL: Tape and Reel, Eight Channel PGA, SOIC package. Plastic Micro Small Outline (MSOP), 8-lead Plastic DIP (300 mil Body), 8, 14, and 16-lead Plastic SOIC, (150 mil Body), 8-lead Plastic SOIC (150 mil Body), 14, 16-lead Plastic TSSOP (4.4mm Body), 14-lead Sales and Support Data Sheets Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and recommended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following: 1. 2. Your local Microchip sales office The Microchip Worldwide Site (www.microchip.com) Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using. New Customer Notification System Register on our web site (www.microchip.com/cn) to receive the most current information on our products.  2003-2012 Microchip Technology Inc. DS21117B-page 39 MCP6S21/2/6/8 NOTES: DS21117B-page 40  2003-2012 Microchip Technology Inc. Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. • Microchip is willing to work with the customer who is concerned about the integrity of their code. • Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer’s risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights. Trademarks The Microchip name and logo, the Microchip logo, dsPIC, FlashFlex, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART, PIC32 logo, rfPIC, SST, SST Logo, SuperFlash and UNI/O are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor, MTP, SEEVAL and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. Silicon Storage Technology is a registered trademark of Microchip Technology Inc. in other countries. Analog-for-the-Digital Age, Application Maestro, BodyCom, chipKIT, chipKIT logo, CodeGuard, dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN, ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial Programming, ICSP, Mindi, MiWi, MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK, mTouch, Omniscient Code Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit, PICtail, REAL ICE, rfLAB, Select Mode, SQI, Serial Quad I/O, Total Endurance, TSHARC, UniWinDriver, WiperLock, ZENA and Z-Scale are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. GestIC and ULPP are registered trademarks of Microchip Technology Germany II GmbH & Co. & KG, a subsidiary of Microchip Technology Inc., in other countries. All other trademarks mentioned herein are property of their respective companies. © 2003-2012, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. ISBN: 9781620767504 QUALITY MANAGEMENT SYSTEM CERTIFIED BY DNV == ISO/TS 16949 ==  2003-2012 Microchip Technology Inc. Microchip received ISO/TS-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company’s quality system processes and procedures are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified. DS21117B-page 41 Worldwide Sales and Service AMERICAS ASIA/PACIFIC ASIA/PACIFIC EUROPE Corporate Office 2355 West Chandler Blvd. Chandler, AZ 85224-6199 Tel: 480-792-7200 Fax: 480-792-7277 Technical Support: http://www.microchip.com/ support Web Address: www.microchip.com Asia Pacific Office Suites 3707-14, 37th Floor Tower 6, The Gateway Harbour City, Kowloon Hong Kong Tel: 852-2401-1200 Fax: 852-2401-3431 India - Bangalore Tel: 91-80-3090-4444 Fax: 91-80-3090-4123 India - New Delhi Tel: 91-11-4160-8631 Fax: 91-11-4160-8632 Austria - Wels Tel: 43-7242-2244-39 Fax: 43-7242-2244-393 Denmark - Copenhagen Tel: 45-4450-2828 Fax: 45-4485-2829 India - Pune Tel: 91-20-2566-1512 Fax: 91-20-2566-1513 France - Paris Tel: 33-1-69-53-63-20 Fax: 33-1-69-30-90-79 Japan - Osaka Tel: 81-66-152-7160 Fax: 81-66-152-9310 Germany - Munich Tel: 49-89-627-144-0 Fax: 49-89-627-144-44 Atlanta Duluth, GA Tel: 678-957-9614 Fax: 678-957-1455 Boston Westborough, MA Tel: 774-760-0087 Fax: 774-760-0088 Chicago Itasca, IL Tel: 630-285-0071 Fax: 630-285-0075 Cleveland Independence, OH Tel: 216-447-0464 Fax: 216-447-0643 Dallas Addison, TX Tel: 972-818-7423 Fax: 972-818-2924 Detroit Farmington Hills, MI Tel: 248-538-2250 Fax: 248-538-2260 Indianapolis Noblesville, IN Tel: 317-773-8323 Fax: 317-773-5453 Los Angeles Mission Viejo, CA Tel: 949-462-9523 Fax: 949-462-9608 Santa Clara Santa Clara, CA Tel: 408-961-6444 Fax: 408-961-6445 Toronto Mississauga, Ontario, Canada Tel: 905-673-0699 Fax: 905-673-6509 Australia - Sydney Tel: 61-2-9868-6733 Fax: 61-2-9868-6755 China - Beijing Tel: 86-10-8569-7000 Fax: 86-10-8528-2104 China - Chengdu Tel: 86-28-8665-5511 Fax: 86-28-8665-7889 China - Chongqing Tel: 86-23-8980-9588 Fax: 86-23-8980-9500 Netherlands - Drunen Tel: 31-416-690399 Fax: 31-416-690340 Korea - Daegu Tel: 82-53-744-4301 Fax: 82-53-744-4302 Spain - Madrid Tel: 34-91-708-08-90 Fax: 34-91-708-08-91 China - Hangzhou Tel: 86-571-2819-3187 Fax: 86-571-2819-3189 Korea - Seoul Tel: 82-2-554-7200 Fax: 82-2-558-5932 or 82-2-558-5934 China - Hong Kong SAR Tel: 852-2401-1200 Fax: 852-2401-3431 Malaysia - Kuala Lumpur Tel: 60-3-6201-9857 Fax: 60-3-6201-9859 China - Nanjing Tel: 86-25-8473-2460 Fax: 86-25-8473-2470 Malaysia - Penang Tel: 60-4-227-8870 Fax: 60-4-227-4068 China - Qingdao Tel: 86-532-8502-7355 Fax: 86-532-8502-7205 Philippines - Manila Tel: 63-2-634-9065 Fax: 63-2-634-9069 China - Shanghai Tel: 86-21-5407-5533 Fax: 86-21-5407-5066 Singapore Tel: 65-6334-8870 Fax: 65-6334-8850 China - Shenyang Tel: 86-24-2334-2829 Fax: 86-24-2334-2393 Taiwan - Hsin Chu Tel: 886-3-5778-366 Fax: 886-3-5770-955 China - Shenzhen Tel: 86-755-8203-2660 Fax: 86-755-8203-1760 Taiwan - Kaohsiung Tel: 886-7-213-7828 Fax: 886-7-330-9305 China - Wuhan Tel: 86-27-5980-5300 Fax: 86-27-5980-5118 Taiwan - Taipei Tel: 886-2-2508-8600 Fax: 886-2-2508-0102 China - Xian Tel: 86-29-8833-7252 Fax: 86-29-8833-7256 Thailand - Bangkok Tel: 66-2-694-1351 Fax: 66-2-694-1350 UK - Wokingham Tel: 44-118-921-5869 Fax: 44-118-921-5820 China - Xiamen Tel: 86-592-2388138 Fax: 86-592-2388130 China - Zhuhai Tel: 86-756-3210040 Fax: 86-756-3210049 DS21117B-page 42 Italy - Milan Tel: 39-0331-742611 Fax: 39-0331-466781 Japan - Yokohama Tel: 81-45-471- 6166 Fax: 81-45-471-6122 10/26/12  2003-2012 Microchip Technology Inc.