MCP6V26T-E/MSVAO

MCP6V26/7/8 620 µA, 2 MHz Auto-Zeroed Op Amps Features Description • High DC Precision: - VOS Drift: ±50 nV/°C (maximum) - VOS: ±2 µV (maximum) - AOL: 125 dB (minimum) - PSRR: 125 dB (minimum) - CMRR: 120 dB (minimum) - Eni: 1.0 µVP-P (typical), f = 0.1 Hz to 10 Hz - Eni: 0.32 µVP-P (typical), f = 0.01 Hz to 1 Hz • Low Power and Supply Voltages: - IQ: 620 µA/amplifier (typical) - Wide Supply Voltage Range: 2.3V to 5.5V • Easy to Use: - Rail-to-Rail Input/Output - Gain Bandwidth Product: 2 MHz (typical) - Unity Gain Stable - Available in Single and Dual - Single with Chip Select (CS): MCP6V28 • Extended Temperature Range: -40°C to +125°C The Microchip Technology Inc. MCP6V26/7/8 family of operational amplifiers provides input offset voltage correction for very low offset and offset drift. These devices have a wide gain bandwidth product (2 MHz, typical) and strongly reject switching noise. They are unity gain stable, have no 1/f noise, and have good power supply rejection ratio (PSRR) and common mode rejection ratio (CMRR). These products operate with a single supply voltage as low as 2.3V, while drawing 620 µA/amplifier (typical) of quiescent current. Typical Applications • • • • • Portable Instrumentation Sensor Conditioning Temperature Measurement DC Offset Correction Medical Instrumentation Design Aids • • • • • SPICE Macro Models FilterLab® Software Microchip Advanced Part Selector (MAPS) Analog Demonstration and Evaluation Boards Application Notes Related Parts Parts with lower power, lower bandwidth and higher noise: The Microchip Technology Inc. MCP6V26/7/8 op amps are offered as a single (MCP6V26), single with Chip Select (CS) (MCP6V28) and dual (MCP6V27). They were designed using an advanced CMOS process. Package Types (top view) MCP6V26 MSOP, SOIC NC 1 VIN– 2 VIN+ 3 VSS 4 8 NC 7 VDD 6 VOUT 5 NC MCP6V26 2×3 TDFN * NC VIN– VIN+ VSS 1 2 3 4 8 7 6 5 VDD V OUTA VOUTB V – INA VINB– VINA+ VINB+ V 1 2 3 SS 4 MCP6V28 MSOP, SOIC NC 1 VIN– 2 VIN+ 3 VSS 4 EP 9 8 7 6 5 NC VDD VOUT NC MCP6V27 4×4 DFN * MCP6V27 MSOP, SOIC VOUTA VINA– VINA+ VSS 1 2 3 4 8 CS 7 VDD 6 VOUT 5 NC EP 9 8 7 6 5 VDD VOUTB VINB– VINB+ MCP6V28 2×3 TDFN * NC VIN– VIN+ VSS 1 2 3 4 EP 9 8 7 6 5 CS VDD VOUT NC * Includes Exposed Thermal Pad (EP); see Table 3-1. • MCP6V01/2/3: Spread clock • MCP6V06/7/8: Non-spread clock © 2011 Microchip Technology Inc. DS25007B-page 1 MCP6V26/7/8 Typical Application Circuit 10 kΩ 10 kΩ VIN VOUT 10 kΩ 10 nF 500 kΩ 5 kΩ 10 kΩ VDD/2 U1 MCP6V26 U2 MCP661 VDD/2 Offset Voltage Correction for Power Driver DS25007B-page 2 © 2011 Microchip Technology Inc. MCP6V26/7/8 1.0 ELECTRICAL CHARACTERISTICS 1.1 Absolute Maximum Ratings † † Notice: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. †† See Section 4.2.1, Rail-to-Rail Inputs. VDD – VSS ..............................................................................6.5V Current at Input Pins †† ......................................................±2 mA Analog Inputs (VIN+ and VIN–) †† .......... VSS – 1.0V to VDD+1.0V All other Inputs and Outputs .................. VSS – 0.3V to VDD+0.3V Difference Input voltage ............................................. |VDD – VSS| Output Short Circuit Current ....................................... Continuous Current at Output and Supply Pins ...................................±30 mA Storage Temperature ..........................................-65°C to +150°C Max. Junction Temperature .............................................. +150°C ESD protection on all pins (HBM, CDM, MM) ≥ 4 kV,1.5 kV, 300V 1.2 Specifications TABLE 1-1: DC ELECTRICAL SPECIFICATIONS Electrical Characteristics: Unless otherwise indicated, TA = +25°C, VDD = +2.3V to +5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2, VL = VDD/2, RL = 10 kΩ to VL and CS = GND (refer to Figure 1-5 and Figure 1-6). Parameters Sym Min Typ Max Units Conditions Input Offset Voltage VOS -2 — +2 µV Input Offset Voltage Drift with Temperature (linear Temp. Co.) TC1 -50 — +50 nV/°C TA = -40 to +125°C (Note 1) Input Offset Voltage Quadratic Temperature Coefficient TC2 — ±0.2 — nV/°C2 TA = -40 to +125°C PSRR 125 142 — dB Input Bias Current IB — +7 — pA Input Bias Current across Temperature IB — +110 — pA TA = +85°C IB — +1.2 +5 nA TA = +125°C Input Offset Current IOS — ±70 — pA Input Offset Current across Temperature IOS — ±50 — pA TA = +85°C IOS — ±60 — pA TA = +125°C — Ω||pF — Ω||pF Input Offset Power Supply Rejection TA = +25°C (Note 1) (Note 1) Input Bias Current and Impedance Common Mode Input Impedance ZCM — 1013||12 Differential Input Impedance ZDIFF — 1013||12 Note 1: 2: Set by design and characterization. Due to thermal junction and other effects in the production environment, these parts can only be screened in production (except TC1; see Appendix B: “Offset Related Test Screens”). Figure 2-18 shows how VCML and VCMH changed across temperature for the first production lot. © 2011 Microchip Technology Inc. DS25007B-page 3 MCP6V26/7/8 TABLE 1-1: DC ELECTRICAL SPECIFICATIONS (CONTINUED) Electrical Characteristics: Unless otherwise indicated, TA = +25°C, VDD = +2.3V to +5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2, VL = VDD/2, RL = 10 kΩ to VL and CS = GND (refer to Figure 1-5 and Figure 1-6). Parameters Sym Min Typ Max Units Conditions Common-Mode Input Voltage Range Low VCML — — VSS − 0.15 V (Note 2) Common-Mode Input Voltage Range High VCMH VDD + 0.2 — — V (Note 2) Common-Mode Rejection CMRR 120 136 — dB VDD = 2.3V, VCM = -0.15V to 2.5V (Note 1, Note 2) CMRR 125 142 — dB VDD = 5.5V, VCM = -0.15V to 5.7V (Note 1, Note 2) AOL 125 147 — dB VDD = 2.3V, VOUT = 0.2V to 2.1V (Note 1) AOL 133 155 — dB VDD = 5.5V, VOUT = 0.2V to 5.3V (Note 1) Minimum Output Voltage Swing VOL — VSS + 5 VSS + 15 mV G = +2, 0.5V input overdrive Maximum Output Voltage Swing VOH — mV G = +2, 0.5V input overdrive Output Short Circuit Current ISC — ±12 — mA VDD = 2.3V ISC — ±22 — mA VDD = 5.5V Common Mode Open-Loop Gain DC Open-Loop Gain (large signal) Output VDD – 15 VDD − 5 Power Supply Supply Voltage Quiescent Current per amplifier POR Trip Voltage Note 1: 2: VDD 2.3 — 5.5 V IQ 450 620 800 µA VPOR 1.15 — 1.65 V IO = 0 Set by design and characterization. Due to thermal junction and other effects in the production environment, these parts can only be screened in production (except TC1; see Appendix B: “Offset Related Test Screens”). Figure 2-18 shows how VCML and VCMH changed across temperature for the first production lot. DS25007B-page 4 © 2011 Microchip Technology Inc. MCP6V26/7/8 TABLE 1-2: AC ELECTRICAL SPECIFICATIONS Electrical Characteristics: Unless otherwise indicated, TA = +25°C, VDD = +2.3V to +5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2, VL = VDD/2, RL = 10 kΩ to VL, CL = 60 pF and CS = GND (refer to Figure 1-5 and Figure 1-6). Parameters Sym Min Typ Max Units Conditions Amplifier AC Response Gain Bandwidth Product GBWP — 2.0 — MHz Slew Rate SR — 1.0 — V/µs Phase Margin PM — 65 — ° Eni — 0.32 — µVP-P f = 0.01 Hz to 1 Hz Eni — 1.0 — µVP-P f = 0.1 Hz to 10 Hz eni — 50 — nV/√Hz f < 5 kHz eni — 29 — nV/√Hz f = 100 kHz ini — 0.6 — fA/√Hz IMD — 40 — µVPK Start Up Time tSTR — 75 — µs G = +1, VOS within 50 µV of its final value (Note 2) Offset Correction Settling Time tSTL — 150 — µs G = +1, VIN step of 2V, VOS within 50 µV of its final value Output Overdrive Recovery Time tODR — 45 — µs G = -100, ±0.5V input overdrive to VDD/2, VIN 50% point to VOUT 90% point (Note 3) G = +1 Amplifier Noise Response Input Noise Voltage Input Noise Voltage Density Input Noise Current Density Amplifier Distortion (Note 1) Intermodulation Distortion (AC) VCM tone = 50 mVPK at 1 kHz, GN = 1 Amplifier Step Response Note 1: 2: 3: These parameters were characterized using the circuit in Figure 1-7. In Figure 2-37 and Figure 2-38, there is an IMD tone at DC, a residual tone at 1 kHz, other IMD tones and clock tones. High gains behave differently; see Section 4.3.3, Offset at Power Up. tODR includes some uncertainty due to clock edge timing. © 2011 Microchip Technology Inc. DS25007B-page 5 MCP6V26/7/8 TABLE 1-3: DIGITAL ELECTRICAL SPECIFICATIONS Electrical Characteristics: Unless otherwise indicated, TA = +25°C, VDD = +2.3V to +5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2, VL = VDD/2, RL = 10 kW to VL, CL = 60 pF, and CS = GND (refer to Figure 1-5 and Figure 1-6). Parameters Sym Min Typ Max Units RPD 3 5 — MΩ CS Logic Threshold, Low VIL VSS — 0.3VDD V CS Input Current, Low ICSL — 5 — pA Conditions CS Pull-Down Resistor (MCP6V28) CS Pull-Down Resistor CS Low Specifications (MCP6V28) CS = VSS CS High Specifications (MCP6V28) CS Logic Threshold, High VIH 0.7VDD — VDD V CS Input Current, High ICSH — VDD/RPD — pA CS = VDD CS Input High, GND Current per amplifier ISS — -0.4 — µA CS = VDD, VDD = 2.3V ISS — -1 — µA CS = VDD, VDD = 5.5V Amplifier Output Leakage, CS High IO_LEAK — 20 — pA CS = VDD CS Dynamic Specifications (MCP6V28) CS Low to Amplifier Output On Turn-on Time tON — 4 50 µs CS Low = VSS+0.3 V, G = +1 V/V, VOUT = 0.9 VDD/2 CS High to Amplifier Output High-Z tOFF — 1 — µs CS High = VDD – 0.3 V, G = +1 V/V, VOUT = 0.1 VDD/2 VHYST — 0.2 — V Internal Hysteresis TABLE 1-4: TEMPERATURE SPECIFICATIONS Electrical Characteristics: Unless otherwise indicated, all limits are specified for: VDD = +2.3V to +5.5V, VSS = GND. Parameters Sym Min Typ Max Units Specified Temperature Range TA -40 — +125 °C Operating Temperature Range TA -40 — +125 °C Storage Temperature Range TA -65 — +150 °C Thermal Resistance, 8L-4x4 DFN θJA — 48 — °C/W Thermal Resistance, 8L-MSOP θJA — 211 — °C/W Thermal Resistance, 8L-SOIC θJA — 150 — °C/W Thermal Resistance, 8L-2x3 TDFN θJA — 53 — °C/W Conditions Temperature Ranges (Note 1) Thermal Package Resistances Note 1: 2: (Note 2) (Note 2) Operation must not cause TJ to exceed Maximum Junction Temperature specification (+150°C). Measured on a standard JC51-7, four layer printed circuit board with ground plane and vias. DS25007B-page 6 © 2011 Microchip Technology Inc. MCP6V26/7/8 1.3 Timing Diagrams 1.4 2.3V to 5.5V 2.3V VDD 0V tSTR VOS + 50 µV VOS Test Circuits The circuits used for the DC and AC tests are shown in Figure 1-5 and Figure 1-6. Lay the bypass capacitors out as discussed in Section 4.3.10, Supply Bypassing and Filtering. RN is equal to the parallel combination of RF and RG to minimize bias current effects. VOS – 50 µV VDD RN VIN FIGURE 1-1: Amplifier Start Up. MCP6V2X RISO U1 100 nF VDD/3 VIN tSTL RG VOS + 50 µV VOS VOS + 50 µV Offset Correction Settling tODR VDD/2 VSS Output Overdrive Recovery. VIL VIH tON IDD tOFF ISS -2 µA (typical) ICS V /5 MΩ DD (typical) FIGURE 1-4: 300 µA (typical) 300 µA (typical) 5 pA (typical) VL 20.0 kΩ 20.0 kΩ 50Ω 0.1% 0.1% 25 turn 1 µA (typical) -2 µA (typical) VDD/5 MΩ (typical) Chip Select (MCP6V28). © 2011 Microchip Technology Inc. RL RF VREF High-Z High-Z 1 µA (typical) CL The circuit in Figure 1-7 tests the op amp input’s dynamic behavior (i.e., IMD, tSTR, tSTL and tODR). The potentiometer balances the resistor network (VOUT should equal VREF at DC). The op amp’s common mode input voltage is VCM = VIN/2. The error at the input (VERR) appears at VOUT with a noise gain of 10 V/V. VIN 2.49 kΩ 2.49 kΩ CS VOUT 100 nF VOUT FIGURE 1-6: AC and DC Test Circuit for Most Inverting Gain Conditions. tODR FIGURE 1-3: VL RISO U1 RG VOUT RL 1 µF VDD/3 RN VIN VDD CL FIGURE 1-5: AC and DC Test Circuit for Most Non-Inverting Gain Conditions. MCP6V2X VIN VOUT RF VDD FIGURE 1-2: Time. 1 µF VDD 1 µF RISO 100 nF U1 MCP6V2X VOUT CL RL VL 20.0 kΩ 20.0 kΩ 24.9 Ω 0.1% 0.1% FIGURE 1-7: Input Behavior. Test Circuit for Dynamic DS25007B-page 7 MCP6V26/7/8 2.0 TYPICAL PERFORMANCE CURVES Note: The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore outside the warranted range. Note: Unless otherwise indicated, TA = +25°C, VDD = +2.3V to 5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2, VL = VDD/2, RL = 10 kΩ to VL, CL = 60 pF and CS = GND. 2.1 DC Input Precision Percentage of Occurrences 40% 35% 30% 20 Samples TA = +25°C VDD = 2.3V and 5.5V 25% 20% 15% 10% 5% 2.0 1.0 0.0 -1.0 -2.0 0% Input Offset Voltage (µV) FIGURE 2-1: Percentage of Occurrences 30% 25% Input Offset Voltage. FIGURE 2-4: Input Offset Voltage vs. Power Supply Voltage with VCM = VCML. 20 Samples VDD = 2.3V and 5.5V 20% 15% 10% 5% 50 40 30 20 0 10 -10 -20 -30 -40 -50 0% Input Offset Voltage Drift; TC1 (nV/°C) Input Offset Voltage Drift. FIGURE 2-5: Input Offset Voltage vs. Power Supply Voltage with VCM = VCMH. Input Offset Voltage (µV) FIGURE 2-2: 5 4 3 2 1 0 -1 -2 -3 -4 -5 Representative Part VDD = 2.3V VDD = 5.5V 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 Output Voltage (V) FIGURE 2-3: Input Offset Voltage Quadratic Temperature Coefficient. DS25007B-page 8 FIGURE 2-6: Output Voltage. Input Offset Voltage vs. © 2011 Microchip Technology Inc. MCP6V26/7/8 Note: Unless otherwise indicated, TA = +25°C, VDD = +2.3V to 5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2, VL = VDD/2, RL = 10 kΩ to VL, CL = 60 pF and CS = GND. 30% FIGURE 2-10: 0.4 0.3 0.2 0.1 0.0 0.4 0.3 0.2 0.1 0.0 155 25% VDD = 5.5V 15% DC Open-Loop Gain. 160 CMRR, PSRR (dB) Percentage of Occurrences FIGURE 2-11: 20 Samples TA = +25°C 20% -0.1 1/AOL (µV/V) FIGURE 2-8: Input Offset Voltage vs. Common Mode Voltage with VDD = 5.5V. 30% VDD = 5.5V VDD = 2.3V -0.2 Percentage of Occurrences 20 Samples TA = +25°C 6.0 5.5 5.0 4.5 4.0 3.5 3.0 2.5 100% 90% 80% 70% 60% 50% 40% 30% 20% 10% 0% PSRR. Input Common Mode Voltage (V) 35% -0.1 1/PSRR (µV/V) -40°C +25°C +85°C +125°C 2.0 1.5 1.0 0.5 0.0 -0.5 Input Offset Voltage (µV) VDD = 5.5V Representative Part 0% 3.0 FIGURE 2-7: Input Offset Voltage vs. Common Mode Voltage with VDD = 2.3V. 5 4 3 2 1 0 -1 -2 -3 -4 -5 5% -0.2 0.5 1.0 1.5 2.0 2.5 Input Common Mode Voltage (V) 10% -0.3 0.0 15% -0.4 -4 -5 -0.5 20% -0.4 -40°C +25°C +85°C +125°C 20 Samples TA = +25°C 25% -0.3 VDD = 2.3V Representative Part 4 3 2 1 0 -1 -2 -3 Percentage of Occurrences Input Offset Voltage (µV) 5 VDD = 2.3V 10% 5% PSRR 150 145 140 135 130 VDD = 5.5V VDD = 2.3V CMRR 125 1/CMRR (µV/V) FIGURE 2-9: CMRR. © 2011 Microchip Technology Inc. 0.5 0.3 0.0 -0.3 -0.5 0% 120 -50 -25 0 25 50 75 100 Ambient Temperature (°C) 125 FIGURE 2-12: CMRR and PSRR vs. Ambient Temperature. DS25007B-page 9 MCP6V26/7/8 Note: Unless otherwise indicated, TA = +25°C, VDD = +2.3V to 5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2, VL = VDD/2, RL = 10 kΩ to VL, CL = 60 pF and CS = GND. 10n 10,000 Input Bias, Offset Currents (A) DC Open-Loop Gain (dB) 160 155 150 1n 1,000 VDD = 5.5V VDD = 2.3V 145 140 135 130 125 120 -50 -25 0 25 50 75 100 Ambient Temperature (°C) 1p 1 25 35 45 55 65 75 85 95 105 115 125 Ambient Temperature (°C) Input Current Magnitude (A) 1.E-04 100µ 1.E-05 10µ 100 IB 50 1.E-06 1µ 1.E-07 100n 0 1.E-08 10n IOS -50 1.E-09 1n 1.E-10 100p 6.0 5.5 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.0 0.5 -100 -0.5 Input Bias, Offset Currents (pA) IB 1.E-02 10m 1.E-03 1m Common Mode Input Voltage (V) FIGURE 2-14: Input Bias and Offset Currents vs. Common Mode Input Voltage with TA = +85°C. +125°C +85°C +25°C -40°C 10p 1.E-11 -1.0 -0.9 -0.8 -0.7 -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0.0 Input Voltage (V) FIGURE 2-17: Input Bias Current vs. Input Voltage (below VSS). TA = +125°C VDD = 5.5V IB 6.0 5.5 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 IOS 0.0 2000 1800 1600 1400 1200 1000 800 600 400 200 0 -200 -400 -0.5 Input Bias, Offset Currents (pA) 10p 10 FIGURE 2-16: Input Bias and Offset Currents vs. Ambient Temperature with VDD = +5.5V. TA = +85°C VDD = 5.5V 150 -IOS 100p 100 125 FIGURE 2-13: DC Open-Loop Gain vs. Ambient Temperature. 200 VDD = 5.5V Common Mode Input Voltage (V) FIGURE 2-15: Input Bias and Offset Currents vs. Common Mode Input Voltage with TA = +125°C. DS25007B-page 10 © 2011 Microchip Technology Inc. MCP6V26/7/8 Note: Unless otherwise indicated, TA = +25°C, VDD = +2.3V to 5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2, VL = VDD/2, RL = 10 kΩ to VL, CL = 60 pF and CS = GND. Other DC Voltages and Currents -25 0 25 50 75 100 Ambient Temperature (°C) 125 FIGURE 2-20: Output Voltage Headroom vs. Ambient Temperature. © 2011 Microchip Technology Inc. 6.0 5.5 5.0 6.5 6.5 6.0 5.5 5.0 4.5 4.0 15% 10% 5% 0% 1.35 -50 20% 1.34 0 25% 1.33 VDD = 2.3V 30% 820 Samples 1 Wafer Lot TA = +25°C 1.32 VOL – VSS 35% Supply Current vs. Power 1.31 1 FIGURE 2-22: Supply Voltage. 1.30 VDD – VOH 3 2 0 1.25 VDD = 5.5V 4 100 Power Supply Voltage (V) Percentage of Occurrences Output Headroom (mV) 7 5 200 40% RL = 10 kΩ 8 6 +125°C +85°C +25°C -40°C 300 3.5 10 FIGURE 2-19: Output Voltage Headroom vs. Output Current. 400 0.0 10 500 3.0 VOL – VSS 600 2.5 VDD – VOH 700 1.29 100 800 2.0 Supply Current (µA/amplifier) Output Voltage Headroom (mV) VDD = 5.5V VDD = 2.3V 10 9 4.5 FIGURE 2-21: Output Short Circuit Current vs. Power Supply Voltage. 1000 1 Output Current Magnitude (mA) 4.0 Power Supply Voltage (V) FIGURE 2-18: Input Common Mode Voltage Headroom (Range) vs. Ambient Temperature. 0.1 -40 125 1.28 0 25 50 75 100 Ambient Temperature (°C) 1.5 -25 1.27 -50 +125°C +85°C +25°C -40°C -30 0.0 -0.4 -20 3.5 Lower (VCML – VSS) -0.3 1.0 -0.2 0 -10 3.0 -0.1 10 2.5 0.0 20 2.0 0.1 1.5 0.2 -40°C +25°C +85°C +125°C 30 1.0 Upper ( VCMH – VDD) 1.26 0.3 40 0.5 1 Wafer Lot 0.5 Input Common Mode Voltage Headroom (V) 0.4 Output Short Circuit Current (mA) 2.2 POR Trip Voltage (V) FIGURE 2-23: Voltage. Power On Reset Trip DS25007B-page 11 MCP6V26/7/8 Note: Unless otherwise indicated, TA = +25°C, VDD = +2.3V to 5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2, VL = VDD/2, RL = 10 kΩ to VL, CL = 60 pF and CS = GND. 1.8 POR Trip Voltage (V) 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0.0 -50 -25 0 25 50 75 100 Ambient Temperature (°C) 125 FIGURE 2-24: Power On Reset Voltage vs. Ambient Temperature. DS25007B-page 12 © 2011 Microchip Technology Inc. MCP6V26/7/8 Note: Unless otherwise indicated, TA = +25°C, VDD = +2.3V to 5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2, VL = VDD/2, RL = 10 kΩ to VL, CL = 60 pF and CS = GND. PSRR+ PSRR- CMRR and PSRR vs. -240 -270 10M 1.E+07 Open-Loop Gain (dB) 0 -30 50 -60 40 -90 ∠AOL 30 20 10 0 -120 -150 -180 | AOL | -210 -10 -20 1k 1.E+03 -240 10k 100k 1M 1.E+04 1.E+05 1.E+06 Frequency (Hz) -270 10M 1.E+07 FIGURE 2-27: Open-Loop Gain vs. Frequency with VDD = 5.5V. © 2011 Microchip Technology Inc. 3.0 100 VDD = 5.5V GBWP VDD = 2.3V 2.5 90 20 2.0 80 1.5 70 1.0 60 Ph hase Margin (°) 120 110 PM 0.5 50 0.0 40 FIGURE 2-29: Gain Bandwidth Product and Phase Margin vs. Common Mode Input Voltage. Open-Loop Phase (°) VDD = 5.5V CL = 60 pF 60 4.0 3.5 Common Mode Input Voltage (V) FIGURE 2-26: Open-Loop Gain vs. Frequency with VDD = 2.3V. 70 125 4.0 120 3.5 110 3.0 2.5 100 VDD = 2.3V PM VDD = 5.5V 90 20 2.0 80 1.5 70 1.0 60 GBWP 0.5 Ph hase Ma argin (°°) 10k 100k 1M 1.E+04 1.E+05 1.E+06 Frequency (Hz) 0 25 50 75 100 Ambient Temperature (°C) 6.0 6 -20 1k 1.E+03 -25 25 5.5 5 -10 40 50 -50 5.0 5 -210 0.0 4.5 4 0 -180 | AOL | 50 -0 0.5 10 0.5 4.0 4 -150 60 3.5 3 -120 20 PM 1.0 3.0 3 30 70 VDD = 2.3V 2.5 2 -30 -90 15 1.5 FIGURE 2-28: Gain Bandwidth Product and Phase Margin vs. Ambient Temperature. 0 -60 ∠AOL 40 80 2.0 2 50 2.0 1.5 60 90 VDD = 5.5V GBWP 1.0 VDD = 2.3V CL = 60 pF 2.5 0.5 0 70 Open-Loop Gain (dB) 1M 1.E+06 100 0.0 0 FIGURE 2-25: Frequency. 10k 100k 1.E+04 1.E+05 Frequency (Hz) ain Ban ndwidth h Produ uct (MH Hz) Ga 1k 1.E+03 3.0 Ph hase Ma argin (°°) CMRR Gaiin Band dwidth Produ uct (MH Hz) 110 100 90 80 70 60 50 40 30 20 10 0 100 1.E+02 Gain Band dwidth Produ uct (MH Hz) Frequency Response Open-Loop Phase (°) CMRR, PSRR (dB) 2.3 50 0.0 40 0 0 0.5 0.0 0 5 1.0 10 1 1.5 5 2.0 2 0 2.5 2 5 3.0 3 0 3.5 3 5 4.0 4 0 4.5 4 5 5.0 5 0 5.5 55 Output Voltage (V) FIGURE 2-30: Gain Bandwidth Product and Phase Margin vs. Output Voltage. DS25007B-page 13 MCP6V26/7/8 Note: Unless otherwise indicated, TA = +25°C, VDD = +2.3V to 5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2, VL = VDD/2, RL = 10 kΩ to VL, CL = 60 pF and CS = GND. VDD = 2.3V Closed-Loop Output Impedance (Ω) 1.E+04 10k 1.E+03 1k 1.E+02 100 10 1.E+01 1.E+001 100k 1.0E+05 G = 1 V/V G = 11 V/V G = 101 V/V 1M 10M 1.0E+06 1.0E+07 Frequency (Hz) 100M 1.0E+08 FIGURE 2-31: Closed-Loop Output Impedance vs. Frequency with VDD = 2.3V. 10 VDD = 2.3V Maximum Output Voltage Swing (VP-P) 1.E+04 10k 1.E+03 1k 1.E+02 100 1.E+01 10 1.E+001 100k 1.0E+05 G = 1 V/V G = 11 V/V G = 101 V/V 1M 10M 1.0E+06 1.0E+07 Frequency (Hz) 100M 1.0E+08 FIGURE 2-32: Closed-Loop Output Impedance vs. Frequency with VDD = 5.5V. DS25007B-page 14 FIGURE 2-33: Channel-to-Channel Separation vs. Frequency. VDD = 5.5V VDD = 2.3V 1 0.1 1k 1.E+03 10k 100k 1.E+04 1.E+05 Frequency (Hz) 1M 1.E+06 FIGURE 2-34: Maximum Output Voltage Swing vs. Frequency. © 2011 Microchip Technology Inc. MCP6V26/7/8 Note: Unless otherwise indicated, TA = +25°C, VDD = +2.3V to 5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2, VL = VDD/2, RL = 10 kΩ to VL, CL = 60 pF and CS = GND. Input Noise and Distortion VDD = 5.5V VDD = 2.3V 1,000 100 100 1,000 100 eni 10 Eni(0 Hz to f) 10 1 100 100k 110E 01 1 1.E+01 1.E+02 E 02 1.E+03 1 1k E 03 1.E+04 1 10k E 04 1 1.E+05 E 05 Frequency (Hz) 100 90 80 70 60 50 40 30 20 10 0 1 kHz tone VDD = 5.5V VDD = 2.3V 10 1 GDM = 1 V/V VDD tone = 50 mVP-P, f = 1 kHz 0.1 100 1.E+02 1k 10k 1.E+03 1.E+04 Frequency (Hz) VDD = 2.3V Input Noise Voltage; eni(t) (0.2 µV/div) VDD = 5.5V VDD = 2.3V NPBW = 10 Hz 6.0 5.5 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 NPBW = 1 Hz 0 10 20 30 40 Common Mode Input Voltage (V) FIGURE 2-36: Input Noise Voltage Density vs. Input Common Mode Voltage. 50 60 t (s) 70 80 90 100 FIGURE 2-39: Input Noise vs. Time with 1 Hz and 10 Hz Filters and VDD =2.3V. 100 VDD = 5.5V IMD tone at DC Input Noise Voltage; eni(t) (0.2 µV/div) IMD Spectrum, RTI (µV PK) 100k 1.E+05 FIGURE 2-38: Intermodulation Distortion vs. Frequency with VDD Disturbance (see Figure 1-7). f < 5 kHz -0.5 Input Noise Voltage Density (nV/Hz) FIGURE 2-35: Input Noise Voltage Density and Integrated Input Noise Voltage vs. Frequency. IMD tone at DC IMD Spectrum, RTI (µVPK) Inp put Noise Volltage D Density;; eni (nV//Hz) 10,000 Integrrated In nput No oise Vo oltage; Eni (μVP-P) 2.4 residual 1 kHz tone 10 VDD = 2.3V VDD = 5.5V 1 GDM = 1 V/V VCM tone = 50 mVPK, f = 1 kHz 0.1 100 1.E+02 1k 10k 1.E+03 1.E+04 Frequency (Hz) NPBW = 1 Hz 100k 1.E+05 FIGURE 2-37: Intermodulation Distortion vs. Frequency with VCM Disturbance (see Figure 1-7). © 2011 Microchip Technology Inc. NPBW = 10 Hz 0 10 20 30 40 50 60 t (s) 70 80 90 100 FIGURE 2-40: Input Noise vs. Time with 1 Hz and 10 Hz Filters and VDD =5.5V. DS25007B-page 15 MCP6V26/7/8 Note: Unless otherwise indicated, TA = +25°C, VDD = +2.3V to 5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2, VL = VDD/2, RL = 10 kΩ to VL, CL = 60 pF and CS = GND. Time Response 2 0 -2 90 80 70 60 VOS -4 -6 -8 -10 100 50 40 30 20 TPCB -12 10 -14 0 20 40 60 0 80 100 120 140 160 180 Time (s) 0 FIGURE 2-41: Input Offset Voltage vs. Time with Temperature Change. 6 G=1 80 5 VDD 70 4 60 3 50 2 40 1 POR Trip Point 30 0 20 -1 10 -2 VOS 0 -3 -10 -4 5 10 VOUT 3 2 1 0 5 6 Time (µs) 7 8 9 10 15 20 25 30 Time (µs) 35 40 45 50 Non-inverting Large Signal VDD = 5.5V G = -1 Output Voltage (10 mV/div) Input, Output Voltages (V) 5 4 4 Non-inverting Small Signal FIGURE 2-45: Step Response. VDD = 5.5V G=1 VIN 3 VDD = 5.5V G=1 0 FIGURE 2-42: Input Offset Voltage vs. Time at Power Up. 6 2 5.5 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 Time (ms) 7 1 FIGURE 2-44: Step Response. Power Supply Voltage (V) Input Offset Voltage (µV) 90 VDD = 5.5V G=1 Output Voltage (10 mV/div) Temperature increased by using heat gun for 10 seconds. 4 Output Voltage (V) Input Offset Voltage (µV) 6 PCB Temperature (°C) 2.5 -1 0 1 2 3 4 5 6 Time (ms) 7 8 9 10 FIGURE 2-43: The MCP6V26/7/8 Device Shows No Input Phase Reversal with Overdrive. DS25007B-page 16 0 1 2 FIGURE 2-46: Response. 3 4 5 6 Time (µs) 7 8 9 10 Inverting Small Signal Step © 2011 Microchip Technology Inc. MCP6V26/7/8 Note: Unless otherwise indicated, TA = +25°C, VDD = +2.3V to 5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2, 6.0 VDD = 5.5V G = -1 5.0 5 G VIN VOUT 4.0 4 3.0 3 2.0 VDD = 5.5V G = -100 V/V 0.5V Overdrive 1.0 VOUT 2 G VIN 0.0 0 5 10 15 FIGURE 2-47: Response. 20 25 30 Time (µs) 35 40 45 Inverting Large Signal Step 1.4 Falling Edge 1.2 1.0 0.8 0.6 VDD = 2.3V Rising Edge 0.4 0.2 0.0 -50 -25 FIGURE 2-48: Temperature. 0 25 50 75 100 Ambient Temperature (°C) Slew Rate vs. Ambient © 2011 Microchip Technology Inc. 125 -1 Time (50 µs/div) FIGURE 2-49: Output Overdrive Recovery vs. Time with G = -100 V/V. Overdrive Recovery Time (µs) VDD = 5.5V 1 0 -1.0 50 1.6 Slew Rate (V/µs) 6 Input Voltage × G (V/V) 5.5 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 Output Voltage (V) Output Voltage (V) VL = VDD/2, RL = 10 kΩ to VL, CL = 60 pF and CS = GND. 1000 0.5V Output Overdrive 100 VDD = 5.5V t ODR, high 10 tODR, low VDD = 2.3V 1 1 10 100 Inverting Gain Magnitude (V/V) 1000 FIGURE 2-50: Output Overdrive Recovery Time vs. Inverting Gain. DS25007B-page 17 MCP6V26/7/8 Note: Unless otherwise indicated, TA = +25°C, VDD = +2.3V to 5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2, VL = VDD/2, RL = 10 kΩ to VL, CL = 60 pF, and CS = GND. 2.6 Chip Select Response (MCP6V28 only) 1.0 CS = VDD 0.9 Chip Select Current (μA) Chip Select Current (μA) 1.0 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0.0 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0.0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 Power Supply Voltage (V) FIGURE 2-51: Chip Select Current vs. Power Supply Voltage. 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 Chip Select Voltage (V) FIGURE 2-54: Select Voltage. VDD = 2.3V G=1 VIN = 1.15V VL = 0V 600 500 400 Op Amp turns on here Op Amp turns off here 300 Hysteresis 200 Chip Select Current vs. Chip 2.5 Outtput Votage (V) Power Supply Current (μA) 700 100 0 VOUT On 2.0 1.5 VOUT Off VOUT Off 1.0 VDD = 2.3V G = +1 V/V VIN = VDD RL = 10 k tied to VDD/2 0.5 CS 0.0 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 Chip Select Voltage (V) FIGURE 2-52: Power Supply Current vs. Chip Select Voltage with VDD = 2.3V. 0 600 Op Amp turns on here 500 400 Op Amp turns off here 300 Hysteresis 200 100 0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 Chip Select Voltage (V) FIGURE 2-53: Power Supply Current vs. Chip Select Voltage with VDD = 5.5V. DS25007B-page 18 Ou utput Votage (V) VDD = 5.5V G=1 VIN = 2.75V VL = 0V 700 5 10 15 20 25 30 35 Time (5 μs/div) 40 45 50 FIGURE 2-55: Chip Select Voltage, Output Voltage vs. Time with VDD = 2.3V. 800 Power Supply Current (μA) VDD = 5.5V 0.9 5.5 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 VOUT On VOUT Off VOUT Off VDD = 5.5V 5 5V G = +1 V/V VIN = VDD RL = 10 k tied to VDD/2 0 5 10 15 CS 20 25 30 35 Time (5 μs/div) 40 45 50 FIGURE 2-56: Chip Select Voltage, Output Voltage vs. Time with VDD = 5.5V. © 2011 Microchip Technology Inc. MCP6V26/7/8 Note: Unless otherwise indicated, TA = +25°C, VDD = +2.3V to 5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2, VL = VDD/2, RL = 10 kΩ to VL, CL = 60 pF, and CS = GND. 7 65% Pull-down Resistor (M) Relative Chip Select Logic Levels; Low and High (V/V) 70% VDD = 5.5V VIH/VDD 60% 55% 50% 45% 40% VDD = 2.3V VIL/VDD 35% -50 -25 0 25 50 75 100 Ambient Temperature (°C) 4 3 2 1 -50 125 -25 0 25 50 75 Ambient Temperature (°C) 100 125 FIGURE 2-60: Chip Select’s Pull-down Resistor (RPD) vs. Ambient Temperature. 1.4 Power Supply Current (μA) 0.40 Chip Select Hysteresis (V) 5 0 30% FIGURE 2-57: Chip Select Relative Logic Thresholds vs. Ambient Temperature. 0.35 0.30 0.25 VDD = 5.5V 0.20 0.15 VDD = 2.3V 0.10 0.05 1.2 1.0 0.8 CS = VDD Representative Part +125°C +85°C +25°C -40°C 0.6 0.4 0.2 0.0 0.00 -50 -25 FIGURE 2-58: Chip Select Turn On Time (μs) 6 0 25 50 75 100 Ambient Temperature (°C) 125 Chip Select Hysteresis. 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 Power Supply Voltage (V) FIGURE 2-61: Quiescent Current in Shutdown vs. Power Supply Voltage. 7 6 5 VDD = 5.5V 4 3 2 VDD = 2.3V 1 0 -50 -25 0 25 50 75 Ambient Temperature (°C) 100 125 FIGURE 2-59: Chip Select Turn On Time vs. Ambient Temperature. © 2011 Microchip Technology Inc. DS25007B-page 19 MCP6V26/7/8 3.0 PIN DESCRIPTIONS Descriptions of the pins are listed in Table 3-1. TABLE 3-1: PIN FUNCTION TABLE MCP6V26 TDFN MSOP, SOIC MCP6V27 DFN MCP6V28 MSOP, SOIC TDFN MSOP, SOIC Symbol Description 6 6 1 1 6 6 VOUT, VOUTA Output (op amp A) 2 2 2 2 2 2 VIN–, VINA– 3 3 3 3 3 3 VIN+, VINA+ 4 4 4 4 4 4 VSS — — 5 5 — — VINB+ Non-inverting Input (op amp B) — — 6 6 — — VINB– Inverting Input (op amp B) — — 7 7 — — VOUTB Output (op amp B) 7 7 8 8 7 7 VDD Positive Power Supply — — — — 8 8 CS Chip Select (op amp A) 1, 5, 8 1, 5, 8 — — 1, 5 1, 5 NC No Internal Connection 9 — 9 — 9 — EP Exposed Thermal Pad (EP); must be connected to VSS 3.1 Analog Outputs The analog output pins (VOUT) are low-impedance voltage sources. 3.2 Analog Inputs The non-inverting and inverting inputs (VIN+, VIN–, …) are high-impedance CMOS inputs with low bias currents. 3.3 Power Supply Pins The positive power supply (VDD) is 2.3V to 5.5V higher than the negative power supply (VSS). For normal operation, the other pins are between VSS and VDD. 3.4 Inverting Input (op amp A) Non-inverting Input (op amp A) Negative Power Supply Chip Select (CS) Digital Input This pin (CS) is a CMOS, Schmitt-triggered input that places the MCP6V28 op amp into a low power mode of operation. 3.5 Exposed Thermal Pad (EP) There is an internal connection between the Exposed Thermal Pad (EP) and the VSS pin; they must be connected to the same potential on the Printed Circuit Board (PCB). This pad can be connected to a PCB ground plane to provide a larger heat sink. This improves the package thermal resistance (θJA). Typically, these parts are used in a single (positive) supply configuration. In this case, VSS is connected to ground and VDD is connected to the supply. VDD will need bypass capacitors. DS25007B-page 20 © 2011 Microchip Technology Inc. MCP6V26/7/8 4.0 APPLICATIONS 4.1 The MCP6V26/7/8 family of auto-zeroed op amps are manufactured using Microchip’s state-of-the-art CMOS process. This family is designed for low cost, low power and high precision applications. Its low supply voltage, low quiescent current and wide bandwidth make the MCP6V26/7/8 devices ideal for battery-powered applications. Overview of Auto-Zeroing Operation Figure 4-1 shows a simplified diagram of the MCP6V26/7/8 auto-zeroed op amps. This will be used to explain how the DC voltage errors are reduced in this architecture. VIN+ VIN– Main Amp. CFW NC Output Buffer VOUT VREF Null Input Switches φ1 Null Output Switches Null Amp. CH POR Null Correct Switches φ2 FIGURE 4-1: 4.1.1 φ1 φ2 Digital Control Oscillator Simplified Auto-Zeroed Op Amp Functional Diagram. BUILDING BLOCKS The Null Amplifier and Main Amplifier are designed for high gain and accuracy using a differential topology. They have a main input pair (+ and - pins at their top left) used for the signal. They have an auxiliary input pair (+ and - pins at their bottom left) used for correcting the offset voltages. Both input pairs are added together internally. The capacitors at the auxiliary inputs (CFW and CH) hold the corrected values during normal operation. The Output Buffer is designed to drive external loads at the VOUT pin. It also produces a single-ended output voltage (VREF is an internal reference voltage). © 2011 Microchip Technology Inc. All of these switches are make-before-break in order to minimize glitch-induced errors. They are driven by two clock phases (φ1 and φ2) that select between normal mode and auto-zeroing mode. The clock is derived from an internal R-C oscillator running at a rate of fOSC1 = 850 kHz. The oscillator’s output is divided down to the desired rate. The internal POR ensures the part starts up in a known good state. It also provides protection against power supply brown-out events. The Digital Control circuitry takes care of all of the housekeeping details of the switching operation. It also takes care of POR events. DS25007B-page 21 MCP6V26/7/8 4.1.2 AUTO-ZEROING ACTION Figure 4-2 shows the connections between amplifiers during the Normal Mode of operation (φ1). The hold capacitor (CH) corrects the Null Amplifier’s input offset. Since the Null Amplifier has very high gain, it dominates the signal seen by the Main Amplifier. This greatly reduces the impact of the Main Amplifier’s input offset voltage on overall performance. Essentially, the Null Amplifier and Main Amplifier behave as a regular op amp with very high gain (AOL) and very low offset voltage (VOS). VIN+ VIN– CFW CH Main Amp. NC Output Buffer VOUT VREF Null Amp. Normal Mode of Operation (φ1); Equivalent Amplifier Diagram. FIGURE 4-2: Figure 4-3 shows the connections between amplifiers during the Auto-zeroing Mode of operation (φ2). The signal goes directly through the Main Amplifier, and the flywheel capacitor (CFW) maintains a constant correction on the Main Amplifier’s offset. Since these corrections happen every 40 µs, or so, we also minimize slow errors, including offset drift with temperature (ΔVOS/ΔTA), 1/f noise, and input offset aging. The Null Amplifier uses its own high open loop gain to drive the voltage across CH to the point where its input offset voltage is almost zero. Because the signal input pair is connected to VIN+, the auto-zeroing action corrects the offset at the current common mode input voltage (VCM) and supply voltage (VDD). This makes the DC CMRR and PSRR very high also. VIN+ VIN– CFW CH FIGURE 4-3: 4.1.3 Null Amp. Main Amp. NC Output Buffer VOUT VREF Auto-zeroing Mode of Operation (φ2); Equivalent Diagram. INTERMODULATION DISTORTION (IMD) The MCP6V26/7/8 op amps will show intermodulation distortion (IMD), products when an AC signal is present. frequencies. Each of the square wave clock’s harmonics has a series of IMD tones centered on it. See Figure 2-37 and Figure 2-38. The signal and clock can be decomposed into sine wave tones (Fourier series components). These tones interact with the auto-zeroing circuitry’s non-linear response to produce IMD tones at sum and difference DS25007B-page 22 © 2011 Microchip Technology Inc. MCP6V26/7/8 4.2 Other Functional Blocks 4.2.1 RAIL-TO-RAIL INPUTS The input stage of the MCP6V26/7/8 op amps use two differential CMOS input stages in parallel. One operates at low common mode input voltage (VCM, which is approximately equal to VIN+ and VIN– in normal operation) and the other at high VCM. With this topology, the input operates with VCM up to VDD + 0.2V, and down to VSS – 0.15V, at +25°C (see Figure 2-18). The input offset voltage (VOS) is measured at VCM = VSS – 0.15V and VDD + 0.2V to ensure proper operation. The transition between the input stages occurs when VCM ≈ VDD – 1.2V (see Figure 2-7 and Figure 2-8). For the best distortion and gain linearity, with non-inverting gains, avoid this region of operation. 4.2.1.1 The input ESD diodes clamp the inputs when they try to go more than one diode drop below VSS. They also clamp any voltages that are well above VDD; their breakdown voltage is high enough to allow normal operation, but not low enough to protect against slow over-voltage (beyond VDD) events. Very fast ESD events (that meet the spec) are limited so that damage does not occur. In some applications, it may be necessary to prevent excessive voltages from reaching the op amp inputs; Figure 4-5 shows one approach to protecting these inputs. D1 and D2 may be small signal silicon diodes, Schottky diodes for lower clamping voltages or diodeconnected FETs for low leakage. VDD Phase Reversal The input devices are designed to not exhibit phase inversion when the input pins exceed the supply voltages. Figure 2-43 shows an input voltage exceeding both supplies with no phase inversion. 4.2.1.2 U1 D1 Input Voltage Limits In order to prevent damage and/or improper operation of these amplifiers, the circuit must limit the voltages at the input pins (see Section 1.1, Absolute Maximum Ratings †). This requirement is independent of the current limits discussed later on. The ESD protection on the inputs can be depicted as shown in Figure 4-4. This structure was chosen to protect the input transistors against many (but not all) over-voltage conditions, and to minimize input bias current (IB). VDD Bond Pad MCP6V2X V1 D2 VOUT V2 FIGURE 4-5: Protecting the Analog Inputs Against High Voltages. 4.2.1.3 Input Current Limits In order to prevent damage and/or improper operation of these amplifiers, the circuit must limit the currents into the input pins (see Section 1.1, Absolute Maximum Ratings †). This requirement is independent of the voltage limits previously discussed. Figure 4-6 shows one approach to protecting these inputs. The resistors R1 and R2 limit the possible current in or out of the input pins (and into D1 and D2). The diode currents will dump onto VDD. VDD VIN+ Bond Pad Input Stage Bond V – IN Pad V1 V2 VSS Bond Pad FIGURE 4-4: Structures. Simplified Analog Input ESD U1 D1 R1 MCP6V2X D2 VOUT R2 VSS – min(V1, V2) 2 mA max(V1, V2) – VDD min(R1, R2) > 2 mA min(R1, R2) > FIGURE 4-6: Protecting the Analog Inputs Against High Currents. © 2011 Microchip Technology Inc. DS25007B-page 23 MCP6V26/7/8 It is also possible to connect the diodes to the left of resistors R1 and R2. In this case, the currents through diodes D1 and D2 need to be limited by some other mechanism. The resistors then serve as in-rush current limiters; the DC current into the input pins (VIN+ and VIN–) should be very small. A significant amount of current can flow out of the inputs (through the ESD diodes) when the common mode voltage (VCM) is below ground (VSS); see Figure 2-17. 4.2.2 RAIL-TO-RAIL OUTPUT The output voltage range of the MCP6V26/7/8 zero-drift op amps is VDD – 15 mV (minimum) and VSS + 15 mV (maximum) when RL = 10 kΩ is connected to VDD/2 and VDD = 5.5V. Refer to Figure 2-19 and Figure 2-20. This op amp is designed to drive light loads; use another amplifier to buffer the output from heavy loads. 4.2.3 CHIP SELECT (CS) The single MCP6V28 has a Chip Select (CS) pin. When CS is pulled high, the supply current for the corresponding op amp drops to about 1 µA (typical), and is pulled through the CS pin to VSS. When this happens, the amplifier is put into a high impedance state. By pulling CS low, the amplifier is enabled. If the CS pin is left floating, the internal pull-down resistor (about 5 MΩ) will keep the part on. Figure 1-4 shows the output voltage and supply current response to a CS pulse. 4.3 Application Tips 4.3.1 INPUT OFFSET VOLTAGE OVER TEMPERATURE Table 1-1 gives both the linear and quadratic temperature coefficients (TC1 and TC2) of input offset voltage. The input offset voltage, at any temperature in the specified range, can be calculated as follows: EQUATION 4-1: V OS ( T A ) = VOS + TC1 ΔT + TC 2 ΔT 2 Where: 4.3.2 DC GAIN PLOTS Figure 2-9, Figure 2-10 and Figure 2-11 are histograms of the reciprocals (in units of µV/V) of CMRR, PSRR and AOL, respectively. They represent the change in input offset voltage (VOS) with a change in common mode input voltage (VCM), power supply voltage (VDD) and output voltage (VOUT). The 1/AOL histogram is centered near 0 µV/V because the measurements are dominated by the op amp’s input noise. The negative values shown represent noise, not unstable behavior. We validate the op amps’ stability by making multiple measurements of VOS; an unstable part would fail, because it would show either greater variability in VOS, or the output stuck at one of the rails. 4.3.3 OFFSET AT POWER UP When these parts power up, the input offset (VOS) starts at its uncorrected value (usually less than ±5 mV). Circuits with high DC gain can cause the output to reach one of the two rails. In this case, the time to a valid output is delayed by an output overdrive time (like tODR), in addition to the startup time (like tSTR). It can be simple to avoid this extra startup time. Reducing the gain is one method. Adding a capacitor across the feedback resistor (RF) is another method. 4.3.4 SOURCE RESISTANCES The input bias currents have two significant components; switching glitches that dominate at room temperature and below, and input ESD diode leakage currents that dominate at +85°C and above. Make the resistances seen by the inputs small and equal. This minimizes the output offset caused by the input bias currents. The inputs should see a resistance on the order of 10Ω to 1 kΩ at high frequencies (i.e., above 1 MHz). This helps minimize the impact of switching glitches, which are very fast, on overall performance. In some cases, it may be necessary to add resistors in series with the inputs to achieve this improvement in performance. Small input resistances are needed for high gains. Without them, parasitic capacitances can cause positive feedback and instability. ΔT = TA – 25°C VOS(TA) = input offset voltage at TA 4.3.5 VOS = input offset voltage at +25°C TC1 = linear temperature coefficient TC2 = quadratic temperature coefficient The capacitances seen by the two inputs should be small and matched. The internal switches connected to the inputs dump charges on these capacitors; an offset can be created if the capacitances do not match. Large input capacitances and source resistances, together with high gain, can lead to positive feedback and instability. DS25007B-page 24 SOURCE CAPACITANCE © 2011 Microchip Technology Inc. MCP6V26/7/8 4.3.6 CAPACITIVE LOADS 4.3.7 Driving large capacitive loads can cause stability problems for voltage feedback op amps. As the load capacitance increases, the feedback loop’s phase margin decreases and the closed-loop bandwidth is reduced. This produces gain peaking in the frequency response, with overshoot and ringing in the step response. These auto-zeroed op amps have a different output impedance than most op amps, due to their unique topology. When driving a capacitive load with these op amps, a series resistor at the output (RISO in Figure 4-7) improves the feedback loop’s phase margin (stability) by making the output load resistive at higher frequencies. The bandwidth will be generally lower than the bandwidth with no capacitive load. STABILIZING OUTPUT LOADS This family of auto-zeroed op amps has an output impedance (Figure 2-31 and Figure 2-32) that has a double zero when the gain is low. This can cause a large phase shift in feedback networks that have low resistance near the part’s bandwidth. This large phase shift can cause stability problems. Figure 4-9 shows that the load on the output is (RL + RISO)||(RF + RG), where RISO is before the load (like Figure 4-7). This load needs to be large enough to maintain stability; it should be at least (2 kΩ)/GN. RG RF RL CL U1 MCP6V2X RISO VOUT CL FIGURE 4-9: 4.3.8 U1 MCP6V2X FIGURE 4-7: Output Resistor, RISO, Stabilizes Capacitive Loads. Figure 4-8 gives recommended RISO values for different capacitive loads and gains. The x-axis is the normalized load capacitance (CL/GN2). The y-axis is the normalized resistance (GNRISO). Output Load. GAIN PEAKING Figure 4-10 shows an op amp circuit that represents non-inverting amplifiers (VM is a DC voltage and VP is the input) or inverting amplifiers (VP is a DC voltage and VM is the input). The capacitances CN and CG represent the total capacitance at the input pins; they include the op amp’s common mode input capacitance (CCM), board parasitic capacitance and any capacitor placed in parallel. The capacitance CFP represents the parasitic capacitance coupling the output and non-inverting input pins. GN is the circuit’s noise gain. For non-inverting gains, GN and the Signal Gain are equal. For inverting gains, GN is 1+|Signal Gain| (e.g., -1 V/V gives GN = +2 V/V). CN RN VP 1000 1k Recommended GNRISO () VOUT CFP U1 MCP6V2X 100 100 VM 10 11 100p 1.E-10 RF VOUT CG GN = 1 GN = 2 GN = 5 GN  10 1n 1.E-09 RG 10n 100n 1.E-08 2 1.E-07 CL/GN (F) 1μ 1.E-06 FIGURE 4-8: Recommended RISO values for Capacitive Loads. After selecting RISO for your circuit, double check the resulting frequency response peaking and step response overshoot. Modify RISO's value until the response is reasonable. Bench evaluation and simulations with the MCP6V26/7/8 SPICE macro model are helpful. © 2011 Microchip Technology Inc. FIGURE 4-10: Capacitance. Amplifier with Parasitic CG acts in parallel with RG (except for a gain of +1 V/V), which causes an increase in gain at high frequencies. CG also reduces the phase margin of the feedback loop, which becomes less stable. This effect can be reduced by either reducing CG or RF||RG. CN and RN form a low-pass filter that affects the signal at VP. This filter has a single real pole at 1/(2πRNCN). DS25007B-page 25 MCP6V26/7/8 The largest value of RF that should be used depends on noise gain (see GN in Section 4.3.6, Capacitive Loads), CG and the open-loop gain’s phase shift. An approximate limit for RF is: EQUATION 4-2: 12 pF 2 R F ≤ 2 k Ω × --------------- × G N CG Some applications may modify these values to reduce either output loading or gain peaking (step response overshoot). At high gains, RG and CG need to be small in order to prevent positive feedback and oscillations. 4.3.9 REDUCING UNDESIRED NOISE AND SIGNALS Reduce undesired noise and signals with: • Low bandwidth signal filters: - Minimizes random analog noise - Reduces interfering signals • Good PCB layout techniques: - Minimizes crosstalk - Minimizes parasitic capacitances and inductances that interact with fast switching edges • Good power supply design: - Provides isolation from other parts - Filters interference on supply line(s) 4.3.10 SUPPLY BYPASSING AND FILTERING With this family of op amps, the power supply pin (VDD for single supply) should have a local bypass capacitor (i.e., 0.01 µF to 0.1 µF) within 2 mm of the pin for good high-frequency performance. These parts also need a bulk capacitor (i.e., 1 µF or larger) within 100 mm to provide large, slow currents. This bulk capacitor can be shared with other low noise, analog parts. In some cases, high-frequency power supply noise (e.g., switched mode power supplies) may cause undue intermodulation distortion, with a DC offset shift; this noise needs to be filtered. Adding a resistor into the supply connection can be helpful. This resistor needs to be small enough to prevent a large drop in VDD for the op amp, which would cause a reduced output range and possible load-induced power supply noise. It also needs to be large enough to dissipate little power when VDD is turned on and off quickly. Figure 4-11 shows a circuit with resistors in the supply connections. It gives good rejection out to 1 MHz for switched mode power DS25007B-page 26 supplies. Smaller resistors and capacitors are a better choice for designs where the power supply is not as noisy. VS_ANA 50Ω 1/4W 50Ω 1/10W 100 µF 100 µF 0.1 µF U1 MCP6V2X to other analog parts FIGURE 4-11: 4.3.11 Additional Supply Filtering. PCB DESIGN FOR DC PRECISION In order to achieve DC precision on the order of ±1 µV, many physical errors need to be minimized. The design of the Printed Circuit Board (PCB), the wiring and the thermal environment has a strong impact on the precision achieved. A poor PCB design can easily be more than 100 times worse than the MCP6V26/7/8 op amps minimum and maximum specifications. 4.3.11.1 PCB Layout Any time two dissimilar metals are joined together, a temperature dependent voltage appears across the junction (the Seebeck or thermo-junction effect). This effect is used in thermocouples to measure temperature. The following are examples of thermo-junctions on a PCB: • Components (resistors, op amps, …) soldered to a copper pad • Wires mechanically attached to the PCB • Jumpers • Solder joints • PCB vias Typical thermo-junctions have temperature to voltage conversion coefficients of 10 to 100 µV/°C (sometimes higher). Microchip’s AN1258 (“Op Amp Precision Design: PCB Layout Techniques”) contains in depth information on PCB layout techniques that minimize thermo-junction effects. It also discusses other effects, such as crosstalk, impedances, mechanical stresses and humidity. © 2011 Microchip Technology Inc. MCP6V26/7/8 4.3.11.2 Crosstalk DC crosstalk causes offsets that appear as a larger input offset voltage. Common causes include: • Common mode noise (remote sensors) • Ground loops (current return paths) • Power supply coupling Interference from the mains (usually 50 Hz or 60 Hz), and other AC sources, can also affect the DC performance. Non-linear distortion can convert these signals to multiple tones, including a DC shift in voltage. When the signal is sampled by an ADC, these AC signals can also be aliased to DC, causing an apparent shift in offset. To reduce interference: - Keep traces and wires as short as possible Use shielding (e.g., encapsulant) Use ground plane (at least a star ground) Place the input signal source near to the DUT Use good PCB layout techniques Use a separate power supply filter (bypass capacitors) for these auto-zeroed op amps 4.3.11.3 Miscellaneous Effects Keep the resistances seen by the input pins as small and as near to equal as possible, to minimize bias current-related offsets. Make the (trace) capacitances seen by the input pins small and equal. This is helpful in minimizing switching glitch-induced offset voltages. 4.4 Typical Applications 4.4.1 WHEATSTONE BRIDGE Many sensors are configured as Wheatstone bridges. Strain gauges and pressure sensors are two common examples. These signals can be small and the common mode noise large. Amplifier designs with high differential gain are desirable. Figure 4-12 shows how to interface to a Wheatstone bridge with a minimum of components. Because the circuit is not symmetric, the ADC input is single ended, there is a minimum of filtering, and the CMRR is good enough for moderate common mode noise. R R Humidity can cause electro-chemical potential voltages to appear in a circuit. Proper PCB cleaning helps, as does the use of encapsulants. 0.2R R R 3 kΩ 100R VDD ADC 0.2R U1 MCP6V26 FIGURE 4-12: Simple Design. Figure 4-13 shows a higher performance circuit for Wheatstone bridges. This circuit is symmetric and has high CMRR. Using a differential input to the ADC helps with the CMRR. U1A ½ MCP6V27 Bending a coax cable with a radius that is too small causes a small voltage drop to appear on the center conductor (the tribo-electric effect). Make sure the bending radius is large enough to keep the conductors and insulation in full contact. Mechanical stresses can make some capacitor types (such as ceramic) to output small voltages. Use more appropriate capacitor types in the signal path and minimize mechanical stresses and vibration. 0.01C VDD 200 Ω VDD R R 1 µF 20 kΩ 10 nF 200Ω R R 3 kΩ 1 µF 200Ω 10 nF VDD ADC 3 kΩ 20 kΩ 1 µF 200 Ω U1B ½ MCP6V27 FIGURE 4-13: © 2011 Microchip Technology Inc. High Performance Design. DS25007B-page 27 MCP6V26/7/8 4.4.2 RTD SENSOR 4.4.3 The ratiometric circuit in Figure 4-14 conditions a three wire RTD. It corrects for the sensor’s wiring resistance by subtracting the voltage across the middle RW. The top R1 does not change the output voltage; it balances the op amp inputs. Failure (open) of the RTD is detected by an out-of-range voltage. U1A ½ MCP6V27 2.49 kΩ VDD RW 10 nF R1 2.49 kΩ 1 µF RRTD 100Ω 10 nF RW R1 2.49 kΩ RB 20 kΩ V1 ≈ THJ(40 µV/°C) R3 100 kΩ R2 2.55 kΩ V2 = (1.00V) 3 kΩ VDD R3 100 kΩ V3 = TCJ(10 mV/°C) + (0.50V) V4 = 250V1 + (V2 – V3) ≈ (10 mV/°C) (THJ – TCJ) + (0.50V) ADC R2 2.55 kΩ 3 kΩ 100 nF RW Figure 4-15 shows a simplified diagram of an amplifier and temperature sensor used in a thermocouple application. The type K thermocouple senses the temperature at the hot junction (THJ), and produces a voltage at V1 proportional to THJ (in °C). The amplifier’s gain is set so that V4/THJ is 10 mV/°C. V3 represents the output of a temperature sensor, which produces a voltage proportional to the temperature (in °C) at the cold junction (TCJ), and with a 0.50V offset. V2 is set so that V4 is 0.50V when THJ – TCJ is 0°C. EQUATION 4-3: 100 nF RT 20 kΩ THERMOCOUPLE SENSOR (hot junction RTH = Thevenin Equivalent Resistance at THJ) (RTH) (RTH) V2 40 µV/°C C Type K U1 Thermocouple (RTH)/250 MCP6V26 V1 2.49 kΩ U1B ½ MCP6V27 FIGURE 4-14: RTD Sensor. The voltages at the input of the ADC can be calculated with the following: G RTD = 1 + 2 ⋅ R3 ⁄ R 2 G W = G RTD – R3 ⁄ R 1 VDM = G RTD ( VT – V B ) + G W VW V T + V B + ( G RTD + 1 – G W )VW VCM = -----------------------------------------------------------------------------2 Where: VT = Voltage at the top of RRTD VB = Voltage at the bottom of RRTD VW = Voltage across top and middle RW’s VCM = ADC’s common mode input VDM = ADC’s differential mode input (cold junction at TCJ) V3 FIGURE 4-15: Simplified Circuit. (RTH) C (RTH) Thermocouple Sensor; Figure 4-16 shows a more complete implementation of this circuit. The dashed red arrow indicates a thermally conductive connection between the thermocouple and the MCP9700A; it needs to be very short and have low thermal resistance. RTH = Thevenin Equivalent Resistance (e.g., 10 kΩ) VDD 4.100(RTH) 0.5696(RTH) VREF U1 C MCP1541 (RTH)/250 Type K U3 MCP6V26 V1 U2 VDD MCP9700A (RTH)/250 C Temp.Sensor (RTH) FIGURE 4-16: DS25007B-page 28 V4 (RTH)/250 (RTH) V4 3 kΩ Thermocouple Sensor. © 2011 Microchip Technology Inc. MCP6V26/7/8 The MCP9700A senses the temperature at its physical location. It needs to be at the same temperature as the cold junction (TCJ), and produces V3 (Figure 4-15). The MCP1541 produces a 4.10V output, assuming VDD is at 5.0V. This voltage, tied to a resistor ladder of 4.100(RTH) and 1.3224(RTH), would produce a Thevenin equivalent of 1.00V and 250(RTH). The 1.3224(RTH) resistor is combined in parallel with the top right RTH resistor (in Figure 4-15), producing the 0.5696(RTH) resistor. V4 should be converted to digital, then corrected for the thermocouple’s non-linearity. The ADC can use the MCP1541 as its voltage reference. Alternately, an absolute reference inside a PICmicro® device can be used instead of the MCP1541. 4.4.4 OFFSET VOLTAGE CORRECTION Figure 4-17 shows an MCP6V27 correcting the input offset voltage of another op amp. R2 and C2 integrate the offset error seen at the other op amp’s input; the integration needs to be slow enough to be stable (with the feedback provided by R1 and R3). VIN R1 R2 R3 R4 C2 VDD/2 U1 MCP6V26 FIGURE 4-17: 4.4.5 U2 MCP661 R5 R2 VDD/2 VOUT Offset Correction. PRECISION COMPARATOR Use high gain before a comparator to improve the latter’s performance. Do not use MCP6V26/7/8 as a comparator by itself; the VOS correction circuitry does not operate properly without a feedback loop. U1 MCP6V26 VIN R1 R2 R3 R4 R5 1 kΩ VOUT VDD/2 U2 MCP6541 FIGURE 4-18: Precision Comparator. © 2011 Microchip Technology Inc. DS25007B-page 29 MCP6V26/7/8 NOTES: DS25007B-page 30 © 2011 Microchip Technology Inc. MCP6V26/7/8 5.0 DESIGN AIDS Microchip provides the basic design aids needed for the MCP6V26/7/8 family of op amps. 5.1 SPICE Macro Model The latest SPICE macro model for the MCP6V26/7/8 family of op amps is available on the Microchip web site at www.microchip.com. This model is intended to be an initial design tool that works well in the op amp’s linear region of operation over the temperature range. See the model file for information on its capabilities. Bench testing is a very important part of any design and cannot be replaced with simulations. Also, simulation results using this macro model need to be validated by comparing them to the data sheet specifications and characteristic curves. 5.2 FilterLab® Software Microchip’s FilterLab® software is an innovative software tool that simplifies analog active filter (using op amps) design. Available at no cost from the Microchip web site at www.microchip.com/filterlab, the Filter-Lab design tool provides full schematic diagrams of the filter circuit with component values. It also outputs the filter circuit in SPICE format, which can be used with the macro model to simulate actual filter performance. 5.3 Microchip Advanced Part Selector (MAPS) MAPS is a software tool that helps efficiently identify Microchip devices that fit a particular design requirement. Available at no cost from the Microchip website at www.microchip.com/maps, the MAPS is an overall selection tool for Microchip’s product portfolio that includes Analog, Memory, MCUs and DSCs. Using this tool, a customer can define a filter to sort features for a parametric search of devices and export side-by-side technical comparison reports. Helpful links are also provided for Data sheets, Purchase and Sampling of Microchip parts. 5.4 Analog Demonstration and Evaluation Boards Microchip offers a broad spectrum of Analog Demonstration and Evaluation Boards that are designed to help customers achieve faster time to market. For a complete listing of these boards and their corresponding user’s guides and technical information, visit the Microchip web site at www.microchip.com/analogtools. Some boards that are especially useful are: • MCP6V01 Thermocouple Auto-Zeroed Reference Design • MCP6XXX Amplifier Evaluation Board 1 • MCP6XXX Amplifier Evaluation Board 2 • MCP6XXX Amplifier Evaluation Board 3 • MCP6XXX Amplifier Evaluation Board 4 • Active Filter Demo Board Kit • P/N SOIC8EV: 8-Pin SOIC/MSOP/TSSOP/DIP Evaluation Board • P/N SOIC14EV: 14-Pin SOIC/TSSOP/DIP Evaluation Board 5.5 Application Notes The following Microchip Application Notes are available on the Microchip web site at www.microchip. com/appnotes and are recommended as supplemental reference resources. ADN003: “Select the Right Operational Amplifier for your Filtering Circuits”, DS21821 AN722: “Operational Amplifier Topologies and DC Specifications”, DS00722 AN723: “Operational Amplifier AC Specifications and Applications”, DS00723 AN884: “Driving Capacitive Loads With Op Amps”, DS00884 AN990: “Analog Sensor Conditioning Circuits – An Overview”, DS00990 AN1177: “Op Amp Precision Design: DC Errors”, DS01177 AN1228: “Op Amp Precision Design: Random Noise”, DS01228 AN1258: “Op Amp Precision Design: PCB Layout Techniques”, DS01258 These application notes and others are listed in the design guide: “Signal Chain Design Guide”, DS21825 © 2011 Microchip Technology Inc. DS25007B-page 31 MCP6V26/7/8 NOTES: DS25007B-page 32 © 2011 Microchip Technology Inc. MCP6V26/7/8 6.0 PACKAGING INFORMATION 6.1 Package Marking Information 8-Lead DFN (4x4x0.9 mm) (MCP6V27) Example XXXXXX XXXXXX YYWW NNN 6V27 E/MDe3 1129 256 PIN 1 PIN 1 8-Lead MSOP (3x3 mm) Example 6V27E 129256 8-Lead SOIC (3.90 mm) Example MCP6V27E SN^^ e3 1129 256 NNN 8-Lead TDFN (2x3x0.75 mm) (MCP6V26, MCP6V28) Device Legend: XX...X Y YY WW NNN e3 * Note: Code MCP6V26T-E/MNY ABA MCP6V28T-E/MNY ABB Example ABA 129 25 Customer-specific information Year code (last digit of calendar year) Year code (last 2 digits of calendar year) Week code (week of January 1 is week ‘01’) Alphanumeric traceability code Pb-free JEDEC designator for Matte Tin (Sn) This package is Pb-free. The Pb-free JEDEC designator ( e3 ) can be found on the outer packaging for this package. In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. © 2011 Microchip Technology Inc. DS25007B-page 33 MCP6V26/7/8 8-Lead Plastic Dual Flat, No Lead Package (MD) – 4x4x0.9 mm Body [DFN] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging Microchip Technology Drawing C04-131E Sheet 1 of 2 DS25007B-page 34 © 2011 Microchip Technology Inc. MCP6V26/7/8 8-Lead Plastic Dual Flat, No Lead Package (MD) – 4x4x0.9 mm Body [DFN] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging Microchip Technology Drawing C04-131E Sheet 2 of 2 © 2011 Microchip Technology Inc. DS25007B-page 35 MCP6V26/7/8 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS25007B-page 36 © 2011 Microchip Technology Inc. MCP6V26/7/8              1 %& %! %2" ) '  % 2$%  %"% %%033)))&  &32 D N E E1 NOTE 1 1 2 e b A2 A c φ L L1 A1 4% &  5&% 6!&(  $ 55* * 6 6 67 8 9 %  7 ;%  < :+./ <  ""2 2  + 9+ + %" $$   < + 7 ="% *  ""2="% * ,./ 7 5%  ,./ 1 %5% 5 1 % % 5  ./  : 9 +*1 1 %  > < 9> 5" 2  9 < , 5"="% (  <      !"#$%! & '(!%&! %( %")%%%"   &   "*"  %!"& "$   % !    "$   % !     %#"+&&  " , &  "%   *-+ ./0 . &    %#%!  ))% !%%    *10 $ &  '! !)% !%%  '$ $ &% !           ) /. © 2011 Microchip Technology Inc. DS25007B-page 37 MCP6V26/7/8 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS25007B-page 38 © 2011 Microchip Technology Inc. MCP6V26/7/8 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging © 2011 Microchip Technology Inc. DS25007B-page 39 MCP6V26/7/8 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS25007B-page 40 © 2011 Microchip Technology Inc. MCP6V26/7/8        !" #$%&  '( )*   1 %& %! %2" ) '  % 2$%  %"% %%033)))&  &32 © 2011 Microchip Technology Inc. DS25007B-page 41 MCP6V26/7/8 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS25007B-page 42 © 2011 Microchip Technology Inc. MCP6V26/7/8 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging © 2011 Microchip Technology Inc. DS25007B-page 43 MCP6V26/7/8    + , "     -.#.&$/0  '( 1+,   1 %& %! %2" ) '  % 2$%  %"% %%033)))&  &32 DS25007B-page 44 © 2011 Microchip Technology Inc. MCP6V26/7/8 APPENDIX A: REVISION HISTORY Revision B (August 2011) The following is the list of modifications: 1. 2. 3. 4. Added the MCP6V26 and MCP6V28 single op amps. a) Updated package drawings on page 1. b) Updated the pinout table (Table 3-1). c) Added 8-lead, 2×3 TDFN package to the Thermal Characteristics Table (Table 1-4). d) Added 8-lead, 2×3 TDFN package to Section 6.0 “Packaging Information”. e) Added parts numbers to Product Identification System. Added Chip Select (CS) information. a) Added Digital Electrical Specifications table (Table 1-3). b) Added Timing Diagram (Figure 1-4). c) Added Section 2.6 “Chip Select Response (MCP6V28 only)” to the Typical Performance Curves. d) Added Section 4.2.3 “Chip Select (CS)” to the applications write up. Added information on positive feedback and parasitic feedback capacitance. a) Added to Section 4.3.4 “Source Resistances”. b) Added to Section 4.3.5 “Source Capacitance”. c) Modified Figure 4-10. d) Added to Section 4.3.8 “Gain Peaking”. Other minor typographical corrections. Revision A (March 2011) • Original data sheet for the MCP6V27 dual op amps. © 2011 Microchip Technology Inc. DS25007B-page 45 MCP6V26/7/8 APPENDIX B: OFFSET RELATED TEST SCREENS We use production screens to ensure the quality of our outgoing products. These screens are set at wider limits to eliminate any fliers; see Table B-1. Input offset voltage-related specifications in the DC spec table (Table 1-1) are based on bench measurements (see Section 2.1 “DC Input Precision”). These measurements are much more accurate because: • More compact circuit • Soldered parts on the PCB (to validate other measurements) • More time spent averaging (reduces noise) • Better temperature control - Reduced temperature gradients - Greater accuracy TABLE B-1: OFFSET RELATED TEST SCREENS Electrical Characteristics: Unless otherwise indicated, TA = +25°C, VDD = +2.3V to +5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2, VL = VDD/2, RL = 10 kΩ to VL and CS = GND (refer to Figure 1-5 and Figure 1-6). Parameters Sym Min Max Units Conditions Input Offset Voltage VOS -10 +10 Input Offset Voltage Drift with Temperature (linear Temp. Co.) TC1 — — PSRR 115 — dB (Note 1) CMRR 106 — dB VDD = 2.3V, VCM = -0.15V to 2.5V (Note 1) CMRR 116 — dB VDD = 5.5V, VCM = -0.15V to 5.7V (Note 1) AOL 114 — dB VDD = 2.3V, VOUT = 0.2V to 2.1V (Note 1) AOL 122 — dB VDD = 5.5V, VOUT = 0.2V to 5.3V (Note 1) Input Offset Power Supply Rejection µV TA = +25°C (Note 1, Note 2) nV/°C TA = -40 to +125°C (Note 3) Common Mode Common Mode Rejection Open-Loop Gain DC Open-Loop Gain (large signal) Note 1: 2: 3: Due to thermal junctions and other errors in the production environment, these specifications are only screened in production. VOS is also sample screened at +125°C. TC1 is not measured in production. DS25007B-page 46 © 2011 Microchip Technology Inc. MCP6V26/7/8 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. –X /XX Device Temperature Range Package Device: MCP6V26 MCP6V26T MCP6V27 MCP6V27T MCP6V28 MCP6V28T Temperature Range: E Package: MD MNY * MS SN Single Op Amp Single Op Amp (Tape and Reel) Dual Op Amp Dual Op Amp (Tape and Reel) Single Op Amp with Chip Select Single Op Amp with Chip Select (Tape and Reel) Examples: a) MCP6V26T-E/MNY: b) MCP6V26-E/MS: a) MCP6V26T-E/SN: a) MCP6V27-E/MD: b) MCP6V27-E/MS: c) MCP6V27-E/SN: a) MCP6V28T-E/MNY: b) MCP6V28-E/MS: c) MCP6V28T-E/SN: = -40°C to +125°C = = = = Plastic Dual Flat, No-Lead (4×4x0.9), 8-lead Plastic Dual Flat, No-Lead (2×3x0.75), 8-lead Plastic Micro Small Outline Package, 8-lead Plastic SOIC (150mil Body), 8-lead * Y = Nickel Palladium gold manufacturing designator. Only available on the TDFN package. © 2011 Microchip Technology Inc. Extended temperature, 8LD 2×3 TDFN package Extended temperature, 8LD MSOP package Tape and Reel, Extended temperature, 8LD SOIC package Extended temperature, 8LD 4x4 DFN package Extended temperature, 8LD MSOP package Extended temperature, 8LD SOIC package Extended temperature, 8LD 2×3 TDFN package Extended temperature, 8LD MSOP package Tape and Reel, Extended temperature, 8LD SOIC package DS25007B-page 47 MCP6V26/7/8 NOTES: DS25007B-page 48 © 2011 Microchip Technology Inc. Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. • Microchip is willing to work with the customer who is concerned about the integrity of their code. • Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer’s risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights. Trademarks The Microchip name and logo, the Microchip logo, dsPIC, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART, PIC32 logo, rfPIC and UNI/O are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor, MXDEV, MXLAB, SEEVAL and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. Analog-for-the-Digital Age, Application Maestro, chipKIT, chipKIT logo, CodeGuard, dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN, ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial Programming, ICSP, Mindi, MiWi, MPASM, MPLAB Certified logo, MPLIB, MPLINK, mTouch, Omniscient Code Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit, PICtail, REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. © 2011, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. ISBN: 978-1-61341-503-0 Microchip received ISO/TS-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company’s quality system processes and procedures are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified. © 2011 Microchip Technology Inc. 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