MCP6V36T-E/OT

MCP6V36/6U/7/9 23 µA, 300 kHz Zero-Drift Op Amps Features Description • High DC Precision: - VOS Drift: ±150 nV/°C (maximum) - VOS: ±25 µV (maximum) - AOL: 110 dB (minimum, VDD = 5.5V) - PSRR: 110 dB (minimum, VDD = 5.5V) - CMRR: 110 dB (minimum, VDD = 5.5V) - Eni: 1.0 µVP-P (typical), f = 0.1 Hz to 10 Hz - Eni: 0.33 µVP-P (typical), f = 0.01 Hz to 1 Hz • Low Power and Supply Voltages: - IQ: 23 µA/amplifier (typical) - Wide Supply Voltage Range: 1.8V to 5.5V • Small Packages: - Singles in SC70, SOT-23 - Duals in MSOP-8, 2×3 TDFN - Quads in TSSOP-14 • Easy to Use: - Rail-to-Rail Input/Output - Gain Bandwidth Product: 300 kHz (typical) - Unity Gain Stable • Extended Temperature Range: -40°C to +125°C The Microchip Technology Inc. MCP6V36/6U/7/9 family of operational amplifiers provides input offset voltage correction for very low offset and offset drift. These are low-power devices, with a gain bandwidth product of 300 kHz (typical). They are unity gain stable, have virtually no 1/f noise, and have good Power Supply Rejection Ratio (PSRR) and Common Mode Rejection Ratio (CMRR). These products operate with a single supply voltage as low as 1.8V, while drawing 23 µA/amplifier (typical) of quiescent current. Typical Applications • • • • • Portable Instrumentation Sensor Conditioning Temperature Measurement DC Offset Correction Medical Instrumentation Design Aids • • • • SPICE Macro Models Microchip Advanced Part Selector (MAPS) Analog Demonstration and Evaluation Boards Application Notes Related Parts • • • • • MCP6V01/2/3: Auto-Zeroed, Spread Clock MCP6V06/7/8: Auto-Zeroed MCP6V26/7/8: Auto-Zeroed, Low Noise MCP6V11/1U/2/4: Zero-Drift, Low Power MCP6V31/1U/2/4: Zero-Drift, Low Power  2019 Microchip Technology Inc. The Microchip Technology Inc. MCP6V36/6U/7/9 op amps are offered in single (MCP6V36 and MCP6V36U), dual (MCP6V37) and quad (MCP6V39) packages. They were designed using an advanced CMOS process. Package Types MCP6V36 SOT-23 VOUT 1 VSS 2 VIN+ 3 MCP6V37 MSOP 5 VDD VOUTA VINA– V 4 VIN– INA+ VSS MCP6V36U SC70, SOT-23 1 2 3 4 8 7 6 5 VDD VOUTB VINB– VINB+ MCP6V37 2×3 TDFN * VOUTA 1 VIN+ 1 5 VDD VSS 2 VIN– 3 VINA– 2 4 VOUT VINA+ 3 VSS 4 8 VDD EP 9 7 VOUTB 6 VINB– 5 VINB+ MCP6V39 TSSOP 1 2 3 4 VINB+ 5 VINB– 6 VOUTB 7 VOUTA VINA– VINA+ VDD 14 VOUTD 13 VIND– 12 VIND+ 11 VSS 10 VINC+ 9 VINC– 8 VOUTC * Includes Exposed Thermal Pad (EP); see Table 3-1. DS20006209A-page 1 MCP6V36/6U/7/9 Typical Application Circuit VIN R1 R2 R3 VOUT R4 C2 U1 R5 R2 VDD/2 U2 MCP6XXX VDD/2 MCP6V36 Offset Voltage Correction for Power Driver DS20006209A-page 2  2019 Microchip Technology Inc. MCP6V36/6U/7/9 1.0 ELECTRICAL CHARACTERISTICS 1.1 Absolute Maximum Ratings † VDD – VSS .................................................................................................................................................................6.5V Current at Input Pins ..............................................................................................................................................±2 mA Analog Inputs (VIN+ and VIN–) (Note 1) .....................................................................................VSS – 1.0V to VDD+1.0V All other Inputs and Outputs .......................................................................................................VSS – 0.3V to VDD+0.3V Difference Input voltage .................................................................................................................................|VDD – VSS| Output Short Circuit Current ........................................................................................................................... Continuous Current at Output and Supply Pins ...................................................................................................................... ±30 mA Storage Temperature .............................................................................................................................-65°C to +150°C Maximum Junction Temperature .......................................................................................................................... +150°C ESD protection on all pins (HBM, CDM, MM)   2 kV, 1.5 kV, 400V Note 1: See Section 4.2.1, Rail-to-Rail Inputs. † Notice: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. 1.2 Specifications TABLE 1-1: DC ELECTRICAL SPECIFICATIONS Electrical Characteristics: Unless otherwise indicated, TA = +25°C, VDD = +1.8V to +5.5V, VSS = GND, VCM = VDD/3,VOUT = VDD/2, VL = VDD/2, RL = 100 kΩ to VL and CL = 20 pF (refer to Figure 1-4 and Figure 1-5). Parameters Sym. Min. Typ. Max. Units Conditions Input Offset Voltage VOS -25 — +25 µV Input Offset Voltage Drift with Temperature (Linear Temp. Co.) TC1 -150 — +150 nV/°C TA = -40 to +125°C (Note 1) Input Offset Voltage Quadratic Temp. Co. TC2 — ±0.08 — nV/°C2 TA = -40 to +125°C Power Supply Rejection Ratio PSRR 110 135 — Input Bias Current IB — +5 — pA Input Bias Current across Temperature IB — +20 — pA TA = +85°C +2.9 +5 nA TA = +125°C — pA Input Offset TA = +25°C dB Input Bias Current and Impedance IB 0 Input Offset Current IOS — ±130 Input Offset Current across Temperature IOS — ±140 — pA TA = +85°C IOS -1 ±0.4 +1 nA TA = +125°C — Ω||pF — Ω||pF Common-Mode Input Impedance ZCM — 1013||6 Differential Input Impedance ZDIFF — 1013||6 Note 1: 2: For Design Guidance only; not tested. Figure 2-15 shows how VCML and VCMH changed across temperature for the first production lot.  2019 Microchip Technology Inc. DS20006209A-page 3 MCP6V36/6U/7/9 TABLE 1-1: DC ELECTRICAL SPECIFICATIONS (CONTINUED) Electrical Characteristics: Unless otherwise indicated, TA = +25°C, VDD = +1.8V to +5.5V, VSS = GND, VCM = VDD/3,VOUT = VDD/2, VL = VDD/2, RL = 100 kΩ to VL and CL = 20 pF (refer to Figure 1-4 and Figure 1-5). Parameters Sym. Min. Typ. Max. Units Conditions Common-Mode Input Voltage Range Low VCML — — VSS  0.15 V (Note 2) Common-Mode Input Voltage Range High VCMH VDD + 0.2 — — V (Note 2) Common-Mode Rejection Ratio CMRR 100 125 — dB VDD = 1.8V, VCM = -0.15V to 2.0V (Note 2) CMRR 110 135 — dB VDD = 5.5V, VCM = -0.15V to 5.7V (Note 2) AOL 93 125 — dB VDD = 1.8V, VOUT = 0.3V to 1.6V AOL 110 135 — dB VDD = 5.5V, VOUT = 0.3V to 5.3V VOL VSS VSS + 14 VSS + 45 mV RL = 10 kΩ, G = +2, 0.5V input overdrive VOL — VSS + 1.4 — mV RL = 100 kΩ, G = +2, 0.5V input overdrive VOH VDD – 45 VDD – 14 VDD mV RL = 10 kΩ, G = +2, 0.5V input overdrive VOH — VDD – 1.4 — mV RL = 100 kΩ, G = +2, 0.5V input overdrive ISC — ±6 — mA VDD = 1.8V ISC — ±21 — mA VDD = 5.5V VDD 1.8 — 5.5 V IQ 12 23 34 µA 10 21 34 0.9 — 1.6 Common-Mode Open-Loop Gain DC Open-Loop Gain (large signal) Output Minimum Output Voltage Swing Maximum Output Voltage Swing Output Short Circuit Current Power Supply Supply Voltage Quiescent Current per amplifier POR Trip Voltage Note 1: 2: VPOR IO = 0, MCP6V36/6U IO = 0, MCP6V37/9 V For Design Guidance only; not tested. Figure 2-15 shows how VCML and VCMH changed across temperature for the first production lot. DS20006209A-page 4  2019 Microchip Technology Inc. MCP6V36/6U/7/9 TABLE 1-2: AC ELECTRICAL SPECIFICATIONS Electrical Characteristics: Unless otherwise indicated, TA = +25°C, VDD = +1.8V to +5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2, VL = VDD/2, RL = 100 kΩ to VL and CL = 20 pF (refer to Figure 1-4 and Figure 1-5). Parameters Sym. Min. Typ. Max. Units Conditions GBWP — 300 — kHz Slew Rate SR — 0.13 — V/µs Phase Margin PM — 70 — ° Eni — 0.33 — µVP-P f = 0.01 Hz to 1 Hz µVP-P f = 0.1 Hz to 10 Hz Amplifier AC Response Gain Bandwidth Product G = +1 Amplifier Noise Response Input Noise Voltage Eni — 1.0 — Input Noise Voltage Density eni — 50 — nV/√Hz f < 2 kHz Input Noise Current Density ini — 5 — fA/√Hz IMD — 52 — µVPK Amplifier Distortion (Note 1) Intermodulation Distortion (AC) VCM tone = 50 mVPK at 100 Hz, GN = 1 Amplifier Step Response Start Up Time tSTR — 2 — ms G = +1, 0.1% VOUT settling (Note 2) Offset Correction Settling Time tSTL — 100 — µs G = +1, VIN step of 2V, VOS within 100 µV of its final value Output Overdrive Recovery Time tODR — 120 — µs G = -10, ±0.5V input overdrive to VDD/2, VIN 50% point to VOUT 90% point (Note 3) Note 1: 2: 3: These parameters were characterized using the circuit in Figure 1-6. In Figure 2-33 and Figure 2-34, there is an IMD tone at DC, a residual tone at 100 Hz and other IMD tones and clock tones. High gains behave differently; see Section 4.3.3, Offset at Power Up. tODR includes some uncertainty due to clock edge timing. TABLE 1-3: TEMPERATURE SPECIFICATIONS Electrical Characteristics: Unless otherwise indicated, all limits are specified for: VDD = +1.8V to +5.5V, VSS = GND. Parameters Sym. Min. Typ. Max. Units Specified Temperature Range TA -40 — +125 °C Operating Temperature Range TA -40 — +125 °C Storage Temperature Range TA -65 — +150 °C Thermal Resistance, 5L-SC-70 JA — 209 — °C/W Thermal Resistance, 5L-SOT-23 JA — 201 — °C/W Thermal Resistance, 8L-2×3 TDFN θJA — 53 — °C/W Thermal Resistance, 8L-MSOP θJA — 211 — °C/W Thermal Resistance, 14L-TSSOP θJA — 100 — °C/W Conditions Temperature Ranges (Note 1) Thermal Package Resistances Note 1: Operation must not cause TJ to exceed Maximum Junction Temperature specification (+150°C).  2019 Microchip Technology Inc. DS20006209A-page 5 MCP6V36/6U/7/9 1.3 Timing Diagrams 1.4 1.8V to 5.5V 1.8V VDD 0V tSTR 1.001(VDD/3) VOUT Test Circuits The circuits used for most DC and AC tests are shown in Figure 1-4 and Figure 1-5. Lay the bypass capacitors out as discussed in Section 4.3.10 “Supply Bypassing and Filtering”. RN is equal to the parallel combination of RF and RG to minimize bias current effects. 0.999(VDD/3) VDD FIGURE 1-1: Amplifier Start Up. 1 µF RN VIN RISO VOUT MCP6V3X VIN tSTL VOS + 100 µV VOS RG VOS – 100 µV FIGURE 1-2: Time. Offset Correction Settling 100 nF VDD/3 1 µF tODR VDD/2 VSS FIGURE 1-3: RISO VOUT MCP6V3X VDD VOUT VL FIGURE 1-4: AC and DC Test Circuit for Most Noninverting Gain Conditions. VDD/3 RN tODR RL RF VDD VIN CL Output Overdrive Recovery. 100 nF VIN RG CL RL VL RF FIGURE 1-5: AC and DC Test Circuit for Most Inverting Gain Conditions. The circuit in Figure 1-6 tests the input’s dynamic behavior (i.e., IMD, tSTR, tSTL and tODR). The potentiometer balances the resistor network (VOUT should equal VREF at DC). The op amp’s Commonmode input voltage is VCM = VIN/2. The error at the input (VERR) appears at VOUT with a noise gain of 10 V/V. 11.0 kΩ 100 kΩ 500 Ω 0.1% 0.1% 25 turn VREF = VDD/3 VDD 1 µF VIN 100 nF MCP6V3X 11.0 kΩ 100 kΩ 249 Ω 1% 0.1% 0.1% FIGURE 1-6: Input Behavior. DS20006209A-page 6 RISO 0Ω VOUT CL 20 pF RL open VL Test Circuit for Dynamic  2019 Microchip Technology Inc. MCP6V36/6U/7/9 2.0 TYPICAL PERFORMANCE CURVES Note: The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore outside the warranted range. Note: Unless otherwise indicated, TA = +25°C, VDD = +1.8V to 5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2, VL = VDD/2, RL = 100 kΩ to VL and CL = 20 pF. 2.1 DC Input Precision 50% 45% 8 56 Samples TA = +25°C VDD = 1.6V and 5.5V Input O Offset V Voltage e (µV) Percentage of Occurrences 55% 40% 35% 30% 25% 20% 15% 10% VCM = VCML Representative Part 6 4 2 0 +125°C +85°C +85 C +25°C -40°C -2 -4 -6 5% FIGURE 2-1: Input O Offset V Voltage e (µV) 20% 15% 10% 5% 6.5 6.0 5.5 5.0 4.5 4.0 VCM = VCMH Representative p Part 6 4 2 0 +125°C +85°C 85 C +25°C -40°C -2 -4 -6 FIGURE 2-2: Input Offset Voltage Drift. 6.5 6.0 5.5 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 20 0.5 -8 -20 -16 -12 -8 -4 0 4 8 12 16 Input Offset Voltage Drift; TC1 (nV/°C) 0.0 Percentage of Occurrences 8 56 Samples VDD = 1.6V and 5.5V 0% Power Supply Voltage (V) FIGURE 2-5: Input Offset Voltage vs. Power Supply Voltage with VCM = VCMH. 30% 8 56 Samples VDD = 1.6V and 5.5V 20% 15% 10% 5% Representative Part IInput O Offset V Voltage e (µV) Percentage of Occurrences 3.5 FIGURE 2-4: Input Offset Voltage vs. Power Supply Voltage with VCM = VCML. Input Offset Voltage. 25% 25% 3.0 Power Supply Voltage (V) 35% 30% 2.5 8 2.0 6 1.5 -4 -2 0 2 4 Input Offset Voltage (µV) 1.0 -6 0.0 -8 0.5 -8 0% 6 4 2 VDD = 1.8V 0 VDD = 5.5V -2 -4 -6 0% -100 -80 -60 -40 -20 0 20 40 60 80 100 Input Offset Voltage's Quadratic Temp Co; TC2 (pV/°C2) FIGURE 2-3: Input Offset Voltage Quadratic Temp. Co.  2019 Microchip Technology Inc. -8 8 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 Output Voltage (V) FIGURE 2-6: Output Voltage. Input Offset Voltage vs. DS20006209A-page 7 MCP6V36/6U/7/9 Note: Unless otherwise indicated, TA = +25°C, VDD = +1.8V to 5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2, VL = VDD/2, RL = 100 kΩ to VL and CL = 20 pF. 160 VDD = 1.8V Representative Part 6 155 DC Ope D en-Loo op Gain n (dB) 4 2 0 -2 +125°C +85°C +25°C +25 C -40°C -4 -6 -8 -0.5 140 135 130 125 120 110 0.0 0.5 1.0 1.5 2.0 Input Common Mode Voltage (V) 2.5 -50 -25 0 25 50 75 Ambient Temperature (°C) 200 Inpu ut Bias s, Offse et Currents (p pA) VDD = 5.5V Representative Part 6 4 2 0 -2 +125°C +85°C +25 C +25°C -40°C -4 -6 100 125 FIGURE 2-10: DC Open-Loop Gain vs. Ambient Temperature. 8 100 50 IB 0 -50 -100 IOS -150 Input Common Mode Voltage (V) FIGURE 2-8: Input Offset Voltage vs. Common-Mode Voltage with VDD = 5.5V. 6.0 5.5 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 -0.5 6.0 5.5 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 -200 -0.5 -8 TA = +85°C VDD = 5.5V 150 0.0 Common Mode Input Voltage (V) FIGURE 2-11: Input Bias and Offset Currents vs. Common-Mode Input Voltage with TA = +85°C. 160 150 PSRR 145 140 135 130 125 120 VDD = 5.5V 5 5V VDD = 1.8V 115 CMRR Inpu ut Bias s, Offse et Currrents (p pA) 5000 155 4000 TA = +125°C VDD = 5.5V 5 5V 3000 2000 IB 1000 0 IOS 1000 -1000 FIGURE 2-9: CMRR and PSRR vs. Ambient Temperature. DS20006209A-page 8 6.0 5.5 5.0 4.5 4.0 3.5 3.0 125 2.5 100 2.0 0 25 50 75 Ambient Temperature (°C) 1.5 -25 1.0 -50 -0.5 -2000 110 0.5 Input O Offset V Voltage e (µV) VDD = 5.5V VDD = 1.8V 145 115 FIGURE 2-7: Input Offset Voltage vs. Common-Mode Voltage with VDD = 1.8V. CMRR, PS SRR (dB) 150 0.0 Input O Offset V Voltage e (µV) 8 Common Mode Input Voltage (V) FIGURE 2-12: Input Bias and Offset Currents vs. Common-Mode Input Voltage with TA = +125°C.  2019 Microchip Technology Inc. MCP6V36/6U/7/9 Note: Unless otherwise indicated, TA = +25°C, VDD = +1.8V to 5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2, VL = VDD/2, RL = 100 kΩ to VL and CL = 20 pF. Input Bias s, Offse et Currrents (A A) 10000 1n VDD = 5.5V 1000 1n IOS 100 100 100p IB 10 10p 1 1p 25 35 45 55 65 75 85 95 105 115 125 Ambient Temperature (°C) FIGURE 2-13: Input Bias and Offset Currents vs. Ambient Temperature with VDD = +5.5V. 1.E-02 10m Input Cu urrent M Magnitude (A A) 1.E-03 1.E 03 1m 1.E-04 100µ 1.E-05 10µ 1.E-06 1µ 1.E-07 100n 1.E-08 1 E-08 10n 1.E-09 1n +125°C +85°C +85 C +25°C -40°C 1.E-10 100p 1.E-11 p 10p -1.0 -0.9 -0.8 -0.7 -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0.0 Input Voltage (V) FIGURE 2-14: Input Bias Current vs. Input Voltage (below VSS).  2019 Microchip Technology Inc. DS20006209A-page 9 MCP6V36/6U/7/9 Note: Unless otherwise indicated, TA = +25°C, VDD = +1.8V to 5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2, VL = VDD/2, RL = 100 kΩ to VL and CL = 20 pF. Other DC Voltages and Currents VDD – VOH VDD = 5.5V VDD = 1.8V Supply C Current (µA/amplifier) 6.5 25 20 15 10 +125°C +85°C +25°C -40°C 5 6.5 6.0 5.5 5.0 4.5 4.0 3.5 3.0 2.5 10 2.0 1 Output Current Magnitude (mA) 0.0 0.1 1.5 0 1 Power Supply Voltage (V) FIGURE 2-16: Output Voltage Headroom vs. Output Current. FIGURE 2-19: Supply Voltage. Supply Current vs. Power 1.6 RL = 25 kȍ 1.4 POR R Trip Voltage (V) Outpu ut Headroom (mV) Representative Part 30 1.0 Outtput Vo oltage H Headro oom (m mV) 35 10 12 11 10 9 8 7 6 5 4 3 2 1 0 6.0 FIGURE 2-18: Output Short Circuit Current vs. Power Supply Voltage. 1000 VOL – VSS 5.5 Power Supply Voltage (V) FIGURE 2-15: Input Common-Mode Voltage Headroom (Range) vs. Ambient Temperature. 100 5.0 -40 125 4.5 0 25 50 75 100 Ambient Temperature (°C) 4.0 -25 3.5 -50 -30 3.0 -0.4 +125°C +85°C +25°C -40°C -20 2.5 -0.3 0 -10 2.0 Lower (VCML – VSS) -0.2 10 1.5 00 0.0 -0.1 20 1.0 0.1 -40°C +25°C +85°C +125°C 30 0.5 Upper ( VCMH – VDD) 0.2 40 0.5 Inp put Com mmon Mode Voltag ge Headroo H om (V) 1 Wafer Lot 03 0.3 0.0 0.4 Output Sho ort Circuit Current (mA) 2.2 VDD = 5.5V VOL – VSS VDD – VOH 1.2 1.0 0.8 0.6 0.4 0.2 VDD = 1.8V 0.0 -50 -25 0 25 50 75 Ambient Temperature (°C) 100 125 FIGURE 2-17: Output Voltage Headroom vs. Ambient Temperature. DS20006209A-page 10 -50 -25 0 25 50 75 Ambient Temperature (°C) 100 125 FIGURE 2-20: Power-on Reset Voltage vs. Ambient Temperature.  2019 Microchip Technology Inc. MCP6V36/6U/7/9 Note: Unless otherwise indicated, TA = +25°C, VDD = +1.8V to 5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2, VL = VDD/2, RL = 100 kΩ to VL and CL = 20 pF. Frequency Response 700 80 70 60 CMRR 40 30 PSRR 60 200 50 VDD = 1.8V GBWP 100 40 50 -30 -60 ‘AOL 40 30 -90 -120 20 -150 | AOL | 10 180 -180 0 -210 -10 -240 10k 100k 1.E+04 1.E+05 Frequency (Hz) -270 1M 1.E+06 FIGURE 2-23: Open-Loop Gain vs. Frequency with VDD = 5.5V.  2019 Microchip Technology Inc. 50 VDD = 1.8V GBWP 100 40 0 30 Common Mode Input Voltage (V) 700 0 Open n-Loop Phase (°) VDD = 5.5V CL = 20 pF 60 200 FIGURE 2-25: Gain Bandwidth Product and Phase Margin vs. Common-Mode Input Voltage. FIGURE 2-22: Open-Loop Gain vs. Frequency with VDD = 1.8V. 70 60 6.0 -270 1M 1.E+06 10k 100k 1.E+04 1.E+05 Frequency (Hz) 300 5.5 -240 70 5.0 -210 | AOL | 80 400 4.5 0 500 4.0 180 -180 VDD = 5.5V 3.5 -150 10 90 PM 3.0 20 600 2.5 -120 100 RF = 1 Mȍ 2.0 30 125 700 -30 -90 0 25 50 75 100 Ambient Temperature (°C) 1.5 ‘AOL 40 -25 FIGURE 2-24: Gain Bandwidth Product and Phase Margin vs. Ambient Temperature. 0 -60 30 -50 -0.5 Open n-Loop Gain (dB) 50 -10 Open n-Loop Gain (dB) 300 1.0 VDD = 1.8V CL = 20 pF 60 -20 1k 1.E+03 70 100k 1.E+05 CMRR and PSRR vs. 70 -20 1k 1.E+03 80 400 0.5 1k 10k 1.E+03 1.E+04 Frequency (Hz) Gain Bandwidth Product (kHz) FIGURE 2-21: Frequency. 500 VDD = 5.5V 0 100 1.E+02 Open n-Loop Phase (°) 10 10 1.E+01 90 PM hase Margin (°) Ph 20 600 600 100 VDD = 5.5V PM 90 500 80 400 70 300 60 200 50 Ph hase Margin (°) 50 Gain Bandwidth Product (kHz) CMR RR, PSRR (dB) 90 100 Ph hase Margin (°) Gain Band dwidth Product (kHz) 110 100 0.0 2.3 GBWP 100 VDD = 1.8V 0 40 30 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 Output Voltage (V) FIGURE 2-26: Gain Bandwidth Product and Phase Margin vs. Output Voltage. DS20006209A-page 11 MCP6V36/6U/7/9 Note: Unless otherwise indicated, TA = +25°C, VDD = +1.8V to 5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2, VL = VDD/2, RL = 100 kΩ to VL and CL = 20 pF. Closed-Loo op Output Impedance (Ÿ) 1.E+05 100k 140 VDD = 1.8V 120 Chan nnel-to o-Chan nnel Sepa aration n, RTI (d dB) 1.E+04 10k 1.E+03 1k 1.E+02 100 1.E+01 10 1.E+001 100 1.E+02 G = 1 V/V G = 11 V/V G = 101 V/V 1k 1.E+03 100k 10k 1.E+04 1.E+05 Frequency (Hz) 60 40 0 1k 1.E+03 1M 1.E+06 10k 100k 1.E+04 1.E+05 Frequency (Hz) 1M 1.E+06 FIGURE 2-29: Channel-to-Channel Separation vs. Frequency. 10 VDD = 5.5V Max ximum Outputt Voltag ge Swiing (VP--P) Closed-Loo op Output Impedance (Ÿ) MCP6V3 MCP6V3 80 20 FIGURE 2-27: Closed-Loop Output Impedance vs. Frequency with VDD = 1.8V. 1.E+05 100k 100 1.E+04 10k 1.E+03 1k 1.E+02 100 1.E+01 10 1.E+00 10 100 1.E+02 G = 1 V/V G = 11 V/V G = 101 V/V 1k 1.E+03 10k 100k 1.E+04 1.E+05 Frequency (Hz) 1M 1.E+06 FIGURE 2-28: Closed-Loop Output Impedance vs. Frequency with VDD = 5.5V. DS20006209A-page 12 VDD = 5.5V VDD = 1.8V 1 0.1 0 1 1k 1.E+03 10k 100k 1.E+04 1.E+05 Frequency (Hz) 1M 1.E+06 FIGURE 2-30: Maximum Output Voltage Swing vs. Frequency.  2019 Microchip Technology Inc. MCP6V36/6U/7/9 Note: Unless otherwise indicated, TA = +25°C, VDD = +1.8V to 5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2, VL = VDD/2, RL = 100 kΩ to VL and CL = 20 pF. Input Noise and Distortion 1000 1000 eni 100 100 10 VDD = 5.5V VDD = 1.8V 10 Eni(0 Hz to f) 1 1 1 10 1.E+02 100 1.E+03 1k 1.E+04 10k 1.E+05 100k 1.E+00 1.E+01 Frequency (Hz) IMD Sp pectrum m, RTI ((µVPK) Input Noise Voltage Density; eni (nV/¥Hz) 1000 Integrated d Input Noise Voltage; Eni (µVP-P) 2.4 100 IMD tone at DC 10 100 Hz tone 1 10 1.E+01 Input N Noise Voltage; eni(t) (0.2 µV/div) VDD = 1.8V 50 40 VDD = 5.5V 30 20 100k 1.E+05 10 NPBW = 10 Hz NPBW = 1 Hz 6.0 5.5 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 -0.5 0 0 10 20 30 Common Mode Input Voltage (V) FIGURE 2-32: Input Noise Voltage Density vs. Input Common-Mode Voltage. 40 50 60 Time (s) 70 80 90 100 FIGURE 2-35: Input Noise vs. Time with 1 Hz and 10 Hz Filters and VDD = 1.8V. 1.4 GDM = 1 V/V VCM tone = 50 mVPK, f = 100 Hz VDD = 5.5V 1.2 Input N Noise Voltage; eni(t) (0.2 µV/div) IMD Sp pectrum m, RTI ((µVPK) 10k 1.E+04 VDD = 1.8V f < 2 kHz 70 1000 100 1k 1.E+02 1.E+03 Frequency (Hz) FIGURE 2-34: Intermodulation Distortion vs. Frequency with VDD Disturbance (see Figure 1-6). 80 In nput No oise Vo oltage D Density y (nV/¥ ¥Hz) VDD = 1.8V VDD = 5.5V 5 5V 0.1 0 1 1 1.E+00 FIGURE 2-31: Input Noise Voltage Density and Integrated Input Noise Voltage vs. Frequency. 60 GDM = 1 V/V VDD tone = 50 mVPK, f = 100 Hz 1.0 100 0.8 0.6 10 0.4 residual 100 Hz tone 0.2 0.0 NPBW = 10 Hz -0.2 1 -0.4 0.1 0 1 1 1.E+00 VDD = 1.8V VDD = 5.5V 10 1.E+01 100 1k 1.E+02 1.E+03 Frequency (Hz) -0.6 100k 1.E+05 FIGURE 2-33: Intermodulation Distortion vs. Frequency with VCM Disturbance (see Figure 1-6).  2019 Microchip Technology Inc. NPBW = 1 Hz -0.8 10k 1.E+04 0 10 20 30 40 50 60 Time (s) 70 80 90 100 FIGURE 2-36: Input Noise vs. Time with 1 Hz and 10 Hz Filters and VDD = 5.5V. DS20006209A-page 13 MCP6V36/6U/7/9 Note: Unless otherwise indicated, TA = +25°C, VDD = +1.8V to 5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2, VL = VDD/2, RL = 100 kΩ to VL and CL = 20 pF. Time Response G=1 Input O Offset Voltage (mV) 5 VDD 4 5.5 5 5.0 4 POR Trip Point 3 6 3 2 2 1 1 0 0 VOS -1 -1 4.0 3.5 3.0 2.5 2.0 1.5 -2 -2 -3 -3 0.5 -4 -4 0.0 1.0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 Time (ms) 0 50 100 FIGURE 2-40: Step Response. FIGURE 2-37: Input Offset Voltage vs. Time at Power Up. 150 200 250 Time (µs) 300 350 400 Noninverting Large Signal 90 7 VDD = 5.5V G=1 VIN 6 VDD = 5.5V G = -1 80 0 Output V Voltage (10 mV/div) Input, O Output Voltage (V) VDD = 5.5V G=1 4.5 Outtput Voltage (V) 6 Power Supply Voltage (V) 2.5 -1 -10 70 5 60 VOUT 4 50 3 40 30 2 20 1 10 0 0 1 2 3 4 5 6 Time (ms) 7 8 9 10 FIGURE 2-38: The MCP6V36/6U/7/9 Family Shows No Input Phase Reversal with Overdrive. 0 10 20 30 FIGURE 2-41: Response. VDD = 5.5V G=1 60 50 40 30 20 80 90 100 VDD = 5.5V G = -1 5.0 4.5 Outtput Voltage (V) Output V Voltage (10 mV/div) 70 70 Inverting Small Signal Step 5.5 80 40 50 60 Time (µs) 4.0 3.5 3.0 2.5 2.0 1.5 1.0 10 0.5 0.0 0 0 10 20 30 FIGURE 2-39: Step Response. DS20006209A-page 14 40 50 60 Time (µs) 70 80 90 100 Noninverting Small Signal 0 50 FIGURE 2-42: Response. 100 150 200 250 Time (µs) 300 350 400 Inverting Large Signal Step  2019 Microchip Technology Inc. MCP6V36/6U/7/9 Note: Unless otherwise indicated, TA = +25°C, VDD = +1.8V to 5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2, VL = VDD/2, RL = 100 kΩ to VL and CL = 20 pF. 0.30 VDD = 5.5V 0.25 Sle ew Rate (V/µs) Falling Edge 0.20 0.15 0 10 0.10 VDD = 1.8V 0.05 Rising Edge 0.00 -50 -25 0 25 50 75 Ambient Temperature (°C) 125 Slew Rate vs. Ambient 7 7 6 6 Input Voltage × G (1 V/div) Outp put Voltage (V) FIGURE 2-43: Temperature. 100 5 5 VOUT G VIN 4 4 3 3 2 2 VDD = 5 5.5V 5V G = -10 V/V 0.5V Overdrive 1 G VIN 1 VOUT 0 -1 0 -1 0 100 200 300 Time 400 500 700 800 900 10001100 (100600 µs/div) FIGURE 2-44: Output Overdrive Recovery vs. Time with G = -10 V/V. 1.E-02 10m Overdriv ve Recovery Time (s) 0.5V Input Overdrive VDD = 1.8V 1.E-03 1m tODR, high VDD = 5.5V 1.E-04 1 E 04 100µ tODR, low 1.E-05 10µ 1 10 100 Inverting Gain Magnitude (V/V) 1000 FIGURE 2-45: Output Overdrive Recovery Time vs. Inverting Gain.  2019 Microchip Technology Inc. DS20006209A-page 15 MCP6V36/6U/7/9 3.0 PIN DESCRIPTIONS Descriptions of the pins are listed in Table 3-1. TABLE 3-1: PIN FUNCTION TABLE MCP6V36 MCP6V36U SOT-23 SOT-23, SC-70 2×3 TDFN MSOP TSSOP 1 4 1 1 1 4 3 2 2 2 VIN–, VINA– Inverting Input (Op Amp A) 3 1 3 3 3 VIN+, VINA+ Noninverting Input (Op Amp A) 5 5 8 8 4 VDD — — 5 5 5 VINB+ Noninverting Input (Op Amp B) 3.1 MCP6V37 MCP6V39 VOUT, VOUTA Output (Op Amp A) Positive Power Supply — — 6 6 6 VINB– Inverting Input (Op Amp B) — 7 7 7 VOUTB Output (Op Amp B) — — — — 8 VOUTC Output (Op Amp C) — — — — 9 VINC– Inverting Input (Op Amp C) — — — — 10 VINC+ 2 2 4 4 11 VSS Noninverting Input (Op Amp C) Negative Power Supply — — — — 12 VIND+ Noninverting Input (Op Amp D) — — — — 13 VIND– Inverting Input (Op Amp D) — — — — 14 VOUTD Output (Op Amp D) — — 9 — — EP Analog Outputs Analog Inputs The noninverting and inverting inputs (VIN+, VIN–, …) are high-impedance CMOS inputs with low bias currents. 3.3 Description — The analog output pins (VOUT) are low-impedance voltage sources. 3.2 Symbol 3.4 Exposed Thermal Pad (EP); must be connected to VSS Exposed Thermal Pad (EP) There is an internal connection between the exposed thermal pad (EP) and the VSS pin; they must be connected to the same potential on the printed circuit board (PCB). This pad can be connected to a PCB ground plane to provide a larger heat sink. This improves the package thermal resistance (θJA). Power Supply Pins The positive power supply (VDD) is 1.8V to 5.5V higher than the negative power supply (VSS). For normal operation, the other pins are between VSS and VDD. Typically, these parts are used in a single (positive) supply configuration. In this case, VSS is connected to ground and VDD is connected to the supply. VDD will need bypass capacitors. DS20006209A-page 16  2019 Microchip Technology Inc. MCP6V36/6U/7/9 NOTES:  2019 Microchip Technology Inc. DS20006209A-page 17 MCP6V36/6U/7/9 4.0 APPLICATIONS The MCP6V36/6U/7/9 family of zero-drift op amps is manufactured using Microchip’s state of the art CMOS process. It is designed for applications with requirements for small packages and low power. Its low supply voltage and low quiescent current make the MCP6V36/6U/7/9 devices ideal for battery-powered applications. 4.1 Overview of Zero-Drift Operation Figure 4-1 shows a simplified diagram of the MCP6V36/6U/7/9 zero-drift op amps. This diagram will be used to explain how slow voltage errors are reduced in this architecture (much better VOS, ∆VOS/∆TA (TC1), CMRR, PSRR, AOL and 1/f noise). The Low-Pass Filter reduces high-frequency content, including harmonics of the Chopping Clock. The Output Buffer drives external loads at the VOUT pin (VREF is an internal reference voltage). The Oscillator runs at fOSC1 = 200 kHz. Its output is divided by two, to produce the Chopping Clock rate of fCHOP = 100 kHz. The internal POR part starts the part in a known good state, protecting against power supply brown-outs. The Digital Control block controls switching and POR events. 4.1.2 CHOPPING ACTION Figure 4-2 shows the amplifier connections for the first phase of the Chopping Clock and Figure 4-3 shows them for the second phase. Its slow voltage errors alternate in polarity, making the average error small. VREF Output Buffer VOUT VIN+ VIN+ VIN– Main Amp. VIN– NC Aux. Amp. Chopper Output Switches Aux. Amp. FIGURE 4-2: First Chopping Clock Phase; Equivalent Amplifier Diagram. POR VIN+ FIGURE 4-1: Simplified Zero-Drift Op Amp Functional Diagram. VIN– Oscillator 4.1.1 Digital Control NC Low-Pass Filter Low-Pass Filter Chopper Input Switches Main Amp. Main Amp. NC BUILDING BLOCKS The Main Amplifier is designed for high gain and bandwidth, with a differential topology. Its main input pair (+ and - pins at the top left) is used for the higher frequency portion of the input signal. Its auxiliary input pair (+ and - pins at the bottom left) is used for the lowfrequency portion of the input signal and corrects the op amp’s input offset voltage. Both inputs are added together internally. The Auxiliary Amplifier, Chopper Input Switches and Chopper Output Switches provide a high DC gain to the input signal. DC errors are modulated to higher frequencies, while white noise is modulated to low frequency. DS20006209A-page 18 Low-Pass Filter Aux. Amp. FIGURE 4-3: Second Chopping Clock Phase; Equivalent Amplifier Diagram.  2019 Microchip Technology Inc. MCP6V36/6U/7/9 4.1.3 INTERMODULATION DISTORTION (IMD) These op amps will show intermodulation distortion (IMD) products when an AC signal is present. The signal and clock can be decomposed into sine wave tones (Fourier series components). These tones interact with the zero-drift circuitry’s nonlinear response to produce IMD tones at sum and difference frequencies. Each of the square wave clock’s harmonics has a series of IMD tones centered on it. See Figure 2-33 and Figure 2-34. 4.2 4.2.1 Other Functional Blocks RAIL-TO-RAIL INPUTS The input stage of the MCP6V36/6U/7/9 op amps uses two differential CMOS input stages in parallel. One operates at low Common-mode input voltage (VCM, which is approximately equal to VIN+ and VIN– in normal operation) and the other at high VCM. With this topology, the input operates with VCM up to VDD + 0.2V, and down to VSS – 0.15V, at +25°C (see Figure 2-15). The input offset voltage (VOS) is measured at VCM = VSS – 0.15V and VDD + 0.2V to ensure proper operation. The transition between the input stages occurs when VCM ≈ VDD – 0.9V (see Figure 2-7 and Figure 2-8). For the best distortion and gain linearity, with noninverting gains, avoid this region of operation. 4.2.1.1 VIN+ Bond Pad Input Voltage Limits In order to prevent damage and/or improper operation of these amplifiers, the circuit must limit the voltages at the input pins (see Section 1.1 “Absolute Maximum Ratings †”). This requirement is independent of the current limits discussed later on. Bond V – IN Pad Input Stage VSS Bond Pad FIGURE 4-4: Structures. Simplified Analog Input ESD The input ESD diodes clamp the inputs when they try to go more than one diode drop below VSS. They also clamp any voltages well above VDD; their breakdown voltage is high enough to allow normal operation, but not low enough to protect against slow overvoltage (beyond VDD) events. Very fast ESD events (that meet the spec) are limited so that damage does not occur. In some applications, it may be necessary to prevent excessive voltages from reaching the op amp inputs; Figure 4-5 shows one approach to protecting these inputs. D1 and D2 may be small signal silicon diodes, Schottky diodes for lower clamping voltages or diode connected FETs for low leakage. VDD Phase Reversal The input devices are designed to not exhibit phase inversion when the input pins exceed the supply voltages. Figure 2-38 shows an input voltage exceeding both supplies with no phase inversion. 4.2.1.2 VDD Bond Pad U1 D1 MCP6V3X V1 D2 VOUT V2 FIGURE 4-5: Protecting the Analog Inputs Against High Voltages. The ESD protection on the inputs can be depicted as shown in Figure 4-4. This structure was chosen to protect the input transistors against many (but not all) overvoltage conditions, and to minimize input bias current (IB).  2019 Microchip Technology Inc. DS20006209A-page 19 MCP6V36/6U/7/9 4.2.1.3 4.3 Input Current Limits In order to prevent damage and/or improper operation of these amplifiers, the circuit must limit the currents into the input pins (see Section 1.1 “Absolute Maximum Ratings †”). This requirement is independent of the voltage limits discussed previously. Figure 4-6 shows one approach to protecting these inputs. The resistors R1 and R2 limit the possible current in or out of the input pins (and into D1 and D2). The diode currents will dump onto VDD. V1 V2 R1 MCP6V3X Table 1-1 gives both the linear and quadratic temperature coefficients (TC1 and TC2) of input offset voltage. The input offset voltage, at any temperature in the specified range, can be calculated as follows: EQUATION 4-1: = TA – 25°C VOS(TA) = input offset voltage at TA VOS = input offset voltage at +25°C TC1 = linear temperature coefficient TC2 = quadratic temperature coefficient R2 VSS – min(V1, V2) 2 mA max(V1, V2) – VDD min(R1, R2) > 2 mA FIGURE 4-6: Protecting the Analog Inputs Against High Currents. It is also possible to connect the diodes to the left of resistors R1 and R2. In this case, the currents through the diodes D1 and D2 need to be limited by some other mechanism. The resistors then serve as in-rush current limiters; the DC current into the input pins (VIN+ and VIN–) should be very small. A significant amount of current can flow out of the inputs (through the ESD diodes) when the Commonmode voltage (VCM) is below ground (VSS); see Figure 2-14. RAIL-TO-RAIL OUTPUT The output voltage range of the MCP6V36/6U/7/9 zerodrift op amps is VDD – 20 mV (minimum) and VSS + 20 mV (maximum) when RL = 10 kΩ is connected to VDD/2 and VDD = 5.5V. Refer to Figure 216 and Figure 2-17 for more information. This op amp is designed to drive light loads; use another amplifier to buffer the output from heavy loads. DS20006209A-page 20 2 ∆T VOUT min(R1, R2) > 4.2.2 INPUT OFFSET VOLTAGE OVER TEMPERATURE Where: U1 D2 4.3.1 V OS  T A  = VOS + TC 1  T + TC2  T VDD D1 Application Tips 4.3.2 DC GAIN PLOTS Figures 2-9 to 2-11 are histograms of the reciprocals (in units of µV/V) of CMRR, PSRR and AOL, respectively. They represent the change in input offset voltage (VOS) with a change in Common-mode input voltage (VCM), power supply voltage (VDD) and output voltage (VOUT). The 1/AOL histogram is centered near 0 µV/V because the measurements are dominated by the op amp’s input noise. The negative values shown represent noise and tester limitations, not unstable behavior. Production tests make multiple VOS measurements, which validates an op amp's stability; an unstable part would show greater VOS variability, or the output would stick at one of the supply rails. 4.3.3 OFFSET AT POWER UP When these parts power up, the input offset (VOS) starts at its uncorrected value (usually less than ±5 mV). Circuits with high DC gain can cause the output to reach one of the two rails. In this case, the time to a valid output is delayed by an output overdrive time (like tODR), in addition to the start-up time (like tSTR). It can be simple to avoid this extra start-up time. Reducing the gain is one method. Adding a capacitor across the feedback resistor (RF) is another method.  2019 Microchip Technology Inc. MCP6V36/6U/7/9 SOURCE RESISTANCES The input bias currents have two significant components; switching glitches that dominate at room temperature and below, and input ESD diode leakage currents that dominate at +85°C and above. Make the resistances seen by the inputs small and equal. This minimizes the output offset caused by the input bias currents. The inputs should see a resistance on the order of 10 Ω to 1 kΩ at high frequencies (i.e., above 1 MHz). This helps minimize the impact of switching glitches, which are very fast, on overall performance. In some cases, it may be necessary to add resistors in series with the inputs to achieve this improvement in performance. Small input resistances may be needed for high gains. Without them, parasitic capacitances might cause positive feedback and instability. 4.3.5 SOURCE CAPACITANCE The capacitances seen by the two inputs should be small. Large input capacitances and source resistances, together with high gain, can lead to positive feedback and instability. 4.3.6 CAPACITIVE LOADS Driving large capacitive loads can cause stability problems for voltage feedback op amps. As the load capacitance increases, the feedback loop’s phase margin decreases and the closed-loop bandwidth is reduced. This produces gain peaking in the frequency response, with overshoot and ringing in the step response. These zero-drift op amps have a different output impedance than most op amps, due to their unique topology. When driving a capacitive load with these op amps, a series resistor at the output (RISO in Figure 4-7) improves the feedback loop’s phase margin (stability) by making the output load resistive at higher frequencies. The bandwidth will be generally lower than the bandwidth with no capacitive load. GN is the circuit’s noise gain. For noninverting gains, GN and the Signal Gain are equal. For inverting gains, GN is 1+|Signal Gain| (e.g., -1 V/V gives GN = +2 V/V). 1.E+04 10k RL||(RF + RG) • 100 kŸ Recom mmended RISO (Ÿ) 4.3.4 1.E+03 1k 1.E+02 100 10p 1.E-11 GN = 1 GN = 10 100p 1.E-10 GN = 100 1n 10n 100n 1.E-09 1.E-08 1.E-07 Capacitive Load (F) 1µ 1.E-06 FIGURE 4-8: Recommended RISO values for Capacitive Loads. After selecting RISO for your circuit, double check the resulting frequency response peaking and step response overshoot. Modify RISO's value until the response is reasonable. Bench evaluation is helpful. 4.3.7 STABILIZING OUTPUT LOADS This family of zero-drift op amps has an output impedance (Figure 2-27 and Figure 2-28) that has a double zero when the gain is low. This can cause a large phase shift in feedback networks that have lowimpedance near the part’s bandwidth. This large phase shift can cause stability problems. Figure 4-9 shows that the load on the output is (RL + RISO)||(RF + RG), where RISO is before the load (like Figure 4-7). This load needs to be large enough to maintain stability; it should be at least 10 kΩ. RG RF VOUT RL CL U1 RISO VOUT CL MCP6V3X FIGURE 4-9: Output Load. U1 MCP6V3X FIGURE 4-7: Output Resistor, RISO, Stabilizes Capacitive Loads. Figure 4-8 gives recommended RISO values for different capacitive loads and gains. The x-axis is the load capacitance (CL). The y-axis is the resistance (RISO).  2019 Microchip Technology Inc. DS20006209A-page 21 MCP6V36/6U/7/9 4.3.8 GAIN PEAKING 4.3.9 Figure 4-10 shows an op amp circuit that represents noninverting amplifiers (VM is a DC voltage and VP is the input) or inverting amplifiers (VP is a DC voltage and VM is the input). The capacitances CN and CG represent the total capacitance at the input pins; they include the op amp’s Common-mode input capacitance (CCM), board parasitic capacitance and any capacitor placed in parallel. The capacitance CFP represents the parasitic capacitance coupling the output and noninverting input pins. RN VP CN CFP Reduce undesired noise and signals with: • Low bandwidth signal filters: - Minimizes random analog noise - Reduces interfering signals • Good PCB layout techniques: - Minimizes crosstalk - Minimizes parasitic capacitances and inductances that interact with fast switching edges • Good power supply design: - Isolation from other parts - Filtering of interference on supply line(s) 4.3.10 U1 MCP6V3X VM RG FIGURE 4-10: Capacitance. CG RF VOUT Amplifier with Parasitic REDUCING UNDESIRED NOISE AND SIGNALS SUPPLY BYPASSING AND FILTERING With this family of operational amplifiers, the power supply pin (VDD for single supply) should have a local bypass capacitor (i.e., 0.01 µF to 0.1 µF) within 2 mm of the pin for good high-frequency performance. These parts also need a bulk capacitor (i.e., 1 µF or larger) within 100 mm to provide large, slow currents. This bulk capacitor can be shared with other low noise, analog parts. CG acts in parallel with RG (except for a gain of +1 V/V), which causes an increase in gain at high frequencies. CG also reduces the phase margin of the feedback loop, which becomes less stable. This effect can be reduced by either reducing CG or RF||RG. In some cases, high-frequency power supply noise (e.g., switched mode power supplies) may cause undue intermodulation distortion, with a DC offset shift; this noise needs to be filtered. Adding a resistor into the supply connection can be helpful. CN and RN form a low-pass filter that affects the signal at VP. This filter has a single real pole at 1/(2πRNCN). 4.3.11 The largest value of RF that should be used depends on noise gain (see GN in Section 4.3.6 “Capacitive Loads”), CG and the open-loop gain’s phase shift. An approximate limit for RF is: EQUATION 4-2: 2 12 pF R F   10 k    --------------  G N CG Some applications may modify these values to reduce either output loading or gain peaking (step response overshoot). At high gains, RN needs to be small, in order to prevent positive feedback and oscillations. Large CN values can also help. DS20006209A-page 22 PCB DESIGN FOR DC PRECISION In order to achieve DC precision on the order of ±1 µV, many physical errors need to be minimized. The design of the Printed Circuit Board (PCB), the wiring, and the thermal environment have a strong impact on the precision achieved. A poor PCB design can easily be more than 100 times worse than the MCP6V36/6U/7/9 op amps’ minimum and maximum specifications. 4.3.11.1 PCB Layout Any time two dissimilar metals are joined together, a temperature dependent voltage appears across the junction (the Seebeck or thermojunction effect). This effect is used in thermocouples to measure temperature. The following are examples of thermojunctions on a PCB: • Components (resistors, op amps, …) soldered to a copper pad • Wires mechanically attached to the PCB • Jumpers • Solder joints • PCB vias  2019 Microchip Technology Inc. MCP6V36/6U/7/9 Typical thermojunctions have temperature to voltage conversion coefficients of 1 to 100 µV/°C (sometimes higher). 4.4 Microchip’s AN1258 (“Op Amp Precision Design: PCB Layout Techniques”) contains in-depth information on PCB layout techniques that minimize thermojunction effects. It also discusses other effects, such as crosstalk, impedances, mechanical stresses and humidity. Many sensors are configured as Wheatstone bridges. Strain gauges and pressure sensors are two common examples. These signals can be small and the Common-mode noise large. Amplifier designs with high differential gain are desirable. 4.3.11.2 Crosstalk DC crosstalk causes offsets that appear as a larger input offset voltage. Common causes include: Typical Applications 4.4.1 WHEATSTONE BRIDGE Figure 4-11 shows how to interface to a Wheatstone bridge with a minimum of components. Because the circuit is not symmetric, the ADC input is single ended, and there is a minimum of filtering; the CMRR is good enough for moderate Common-mode noise. • Common-mode noise (remote sensors) • Ground loops (current return paths) • Power supply coupling 0.01C VDD R R Interference from the mains (usually 50 Hz or 60 Hz), and other AC sources, can also affect the DC performance. Nonlinear distortion can convert these signals to multiple tones, including a DC shift in voltage. When the signal is sampled by an ADC, these AC signals can also be aliased to DC, causing an apparent shift in offset. FIGURE 4-11: To reduce interference: 4.4.2 - Keep traces and wires as short as possible Use shielding Use ground plane (at least a star ground) Place the input signal source near to the DUT Use good PCB layout techniques Use a separate power supply filter (bypass capacitors) for these zero-drift op amps 4.3.11.3 Miscellaneous Effects Keep the resistances seen by the input pins as small and as near to equal as possible, to minimize biascurrent-related offsets. Make the (trace) capacitances seen by the input pins small and equal. This is helpful in minimizing switching glitch-induced offset voltages. Bending a coax cable with a radius that is too small causes a small voltage drop to appear on the center conductor (the triboelectric effect). Make sure the bending radius is large enough to keep the conductors and insulation in full contact. Mechanical stresses can make some capacitor types (such as some ceramics) output small voltages. Use more appropriate capacitor types in the signal path and minimize mechanical stresses and vibration. Humidity can cause electrochemical potential voltages to appear in a circuit. Proper PCB cleaning helps, as does the use of encapsulants.  2019 Microchip Technology Inc. 0.2R R R 1 kΩ 100R VDD ADC U1 0.2R MCP6V36 Simple Design. RTD SENSOR The ratiometric circuit in Figure 4-12 conditions a twowire RTD, for applications with a limited temperature range. U1 acts a difference amplifier, with a lowfrequency pole. The sensor’s wiring resistance (RW) is corrected in firmware. Failure (open) of the RTD is detected by an out-of-range voltage. VDD RT RN 34.8 kΩ 10.0 kΩ RF 2.00 MΩ RW RRTD 100Ω RW 10 nF U1 MCP6V36 RG RF 10.0 kΩ 2.00 MΩ 1.00 kΩ 100 nF RB 4.99 kΩ 1.0 µF 10 nF VDD ADC FIGURE 4-12: RTD Sensor. DS20006209A-page 23 MCP6V36/6U/7/9 4.4.3 OFFSET VOLTAGE CORRECTION Figure 4-13 shows MCP6V36 (U2) correcting the input offset voltage of another op amp (U1). R2 and C2 integrate the offset error seen at U1’s input; the integration needs to be slow enough to be stable (with the feedback provided by R1 and R3). R4 and R5 attenuate the integrator’s output; this shifts the integrator pole down in frequency. R1 VIN R3 R2 VOUT R4 C2 U1 R5 R2 VDD/2 MCP6XXX U2 VDD/2 MCP6V36 FIGURE 4-13: 4.4.4 Offset Correction. PRECISION COMPARATOR Use high gain before a comparator to improve the latter’s performance. Do not use MCP6V36/6U/7/9 as a comparator by itself; the VOS correction circuitry does not operate properly without a feedback loop. U1 VIN MCP6V36 R1 R2 R3 R4 R5 VOUT VDD/2 U2 MCP6541 FIGURE 4-14: DS20006209A-page 24 Precision Comparator.  2019 Microchip Technology Inc. MCP6V36/6U/7/9 NOTES:  2019 Microchip Technology Inc. DS20006209A-page 25 MCP6V36/6U/7/9 5.0 DESIGN AIDS Microchip provides the basic design aids needed for the MCP6V36/6U/7/9 family of op amps. 5.1 SPICE Macro Model The latest SPICE macro model for the MCP6V36/6U/7/9 op amps is available on the Microchip web site at www.microchip.com. This model is intended to be an initial design tool that works well in the op amp’s linear region of operation over the temperature range. See the model file for information on its capabilities. Bench testing is a very important part of any design and cannot be replaced with simulations. Also, simulation results using this macro model need to be validated by comparing them to the data sheet specifications and characteristic curves. 5.2 Microchip Advanced Part Selector (MAPS) MAPS is a software tool that helps efficiently identify Microchip devices that fit a particular design requirement. Available at no cost from the Microchip web site at www.microchip.com/maps, MAPS is an overall selection tool for Microchip’s product portfolio that includes Analog, Memory, MCUs and DSCs. Using this tool, a customer can define a filter to sort features for a parametric search of devices and export side-by-side technical comparison reports. Helpful links are also provided for Data Sheets, Purchase and Sampling of Microchip parts. 5.3 5.4 Application Notes The following Microchip Application Notes are available on the Microchip web site at www.microchip. com/sitesearch/Search/all and are recommended as supplemental reference resources. ADN003: “Select the Right Operational Amplifier for your Filtering Circuits”, DS21821 AN722: “Operational Amplifier Topologies and DC Specifications”, DS00722 AN723: “Operational Amplifier AC Specifications and Applications”, DS00723 AN884: “Driving Capacitive Loads With Op Amps”, DS00884 AN990: “Analog Sensor Conditioning Circuits – An Overview”, DS00990 AN1177: “Op Amp Precision Design: DC Errors”, DS01177 AN1228: “Op Amp Precision Design: Random Noise”, DS01228 AN1258: “Op Amp Precision Design: PCB Layout Techniques”, DS01258 These Application Notes and others are listed in the design guide: “Signal Chain Design Guide”, DS21825 Analog Demonstration and Evaluation Boards Microchip offers a broad spectrum of Analog Demonstration and Evaluation Boards that are designed to help customers achieve faster time to market. For a complete listing of these boards and their corresponding user’s guides and technical information, visit the Microchip web site at www.microchip.com/treelinktool. Some boards that are especially useful are: • MCP6V01 Thermocouple Auto-Zeroed Reference Design (P/N MCP6V01RD-TCPL) • MCP6XXX Amplifier Evaluation Board 2 (P/N DS51668) • MCP6XXX Amplifier Evaluation Board 3 (P/N DS51673) • 8-Pin SOIC/MSOP/TSSOP/DIP Evaluation Board (P/N SOIC8EV) • 14-Pin SOIC/TSSOP/DIP Evaluation Board (P/N SOIC14EV) DS20006209A-page 26  2019 Microchip Technology Inc. MCP6V36/6U/7/9 NOTES:  2019 Microchip Technology Inc. DS20006209A-page 27 MCP6V36/6U/7/9 6.0 PACKAGING INFORMATION 6.1 Package Marking Information Example: 5-Lead SC70 (MCP6V36U) Device MCP6V36UT-E/LTY Note: Code FSNN FS25 Applies to 5-Lead SC-70. Example: 5-Lead SOT-23 (MCP6V36, MCP6V36U) Device Code MCP6V36T-E/OT RBDF WWNNN MCP6V36UT-E/OT RBDG WWNNN Note: 8-Lead MSOP (3 x 3 mm) (MCP6V37) RBDF 10256 Applies to 5-Lead SOT-23. Example 6V37E 410256 Legend: XX...X Y YY WW NNN e3 * Note: DS20006209A-page 28 Customer-specific information Year code (last digit of calendar year) Year code (last 2 digits of calendar year) Week code (week of January 1 is week ‘01’) Alphanumeric traceability code Pb-free JEDEC® designator for Matte Tin (Sn) This package is Pb-free. The Pb-free JEDEC designator ( e3 ) can be found on the outer packaging for this package. In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information.  2019 Microchip Technology Inc. MCP6V36/6U/7/9 8-Lead TDFN (2 x 3 x 0.8 mm) (MCP6V37) Device DM2 MCP6V37T-E/MNY DM2 14-Lead TSSOP (4.4 mm) (MCP6V39)  2019 Microchip Technology Inc. Code MCP6V37-E/MNY Note: XXXXXXXX YYWW NNN Example Applies to 8-Lead 2x3 TDFN. DM2 410 25 Example 6V39E/ST 1410 256 DS20006209A-page 29 MCP6V36/6U/7/9 5-Lead Plastic Small Outline Transistor (LT) [SC70] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging D A e e 3 B 1 E1 E 2X 0.15 C 4 N 5X TIPS 0.30 C NOTE 1 2X 0.15 C 5X b 0.10 C A B TOP VIEW C c A2 A SEATING PLANE A1 L SIDE VIEW END VIEW Microchip Technology Drawing C04-061D Sheet 1 of 2 DS20006209A-page 30  2019 Microchip Technology Inc. MCP6V36/6U/7/9 5-Lead Plastic Small Outline Transistor (LT) [SC70] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging Units Dimension Limits Number of Pins N e Pitch Overall Height A Standoff A1 Molded Package Thickness A2 Overall Length D Exposed Pad Length D2 Overall Width E Exposed Pad Width E1 b Terminal Width Terminal Length L c Lead Thickness MIN 0.80 0.00 0.80 2.50 0.15 0.10 0.08 MILLIMETERS NOM 5 0.65 BSC 2.00 BSC 2.60 2.10 BSC 1.25 BSC 0.20 - MAX 1.10 0.10 1.00 2.70 0.40 0.46 0.26 Notes: 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.15mm per side. 3. Dimensioning and tolerancing per ASME Y14.5M BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only. Microchip Technology Drawing C04-061D Sheet 2 of 2  2019 Microchip Technology Inc. DS20006209A-page 31 MCP6V36/6U/7/9 5-Lead Plastic Small Outline Transistor (LT) [SC70] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging E Gx SILK SCREEN 3 2 1 C G 4 5 Y X RECOMMENDED LAND PATTERN Units Dimension Limits Contact Pitch E Contact Pad Spacing C Contact Pad Width X Contact Pad Length Y Distance Between Pads G Distance Between Pads Gx MIN MILLIMETERS NOM 0.65 BSC 2.20 MAX 0.45 0.95 1.25 0.20 Notes: 1. Dimensioning and tolerancing per ASME Y14.5M BSC: Basic Dimension. Theoretically exact value shown without tolerances. Microchip Technology Drawing No. C04-2061B DS20006209A-page 32  2019 Microchip Technology Inc. MCP6V36/6U/7/9 5-Lead Plastic Small Outline Transistor (OT) [SOT23] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging 0.20 C 2X D e1 A D N E/2 E1/2 E1 E (DATUM D) (DATUM A-B) 0.15 C D 2X NOTE 1 1 2 e B NX b 0.20 C A-B D TOP VIEW A A A2 0.20 C SEATING PLANE A SEE SHEET 2 A1 C SIDE VIEW Microchip Technology Drawing C04-091-OT Rev E Sheet 1 of 2  2019 Microchip Technology Inc. DS20006209A-page 33 MCP6V36/6U/7/9 5-Lead Plastic Small Outline Transistor (OT) [SOT23] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging c T L L1 VIEW A-A SHEET 1 Units Dimension Limits Number of Pins N e Pitch e1 Outside lead pitch Overall Height A Molded Package Thickness A2 Standoff A1 E Overall Width E1 Molded Package Width D Overall Length L Foot Length Footprint L1 I Foot Angle c Lead Thickness b Lead Width MIN 0.90 0.89 - 0.30 0° 0.08 0.20 MILLIMETERS NOM 5 0.95 BSC 1.90 BSC 2.80 BSC 1.60 BSC 2.90 BSC 0.60 REF - MAX 1.45 1.30 0.15 0.60 10° 0.26 0.51 Notes: 1. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.25mm per side. 2. Dimensioning and tolerancing per ASME Y14.5M BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only. Microchip Technology Drawing C04-091-OT Rev E Sheet 2 of 2 DS20006209A-page 34  2019 Microchip Technology Inc. MCP6V36/6U/7/9 5-Lead Plastic Small Outline Transistor (OT) [SOT23] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging X SILK SCREEN 5 Y Z C G 1 2 E GX RECOMMENDED LAND PATTERN Units Dimension Limits E Contact Pitch C Contact Pad Spacing X Contact Pad Width (X5) Contact Pad Length (X5) Y Distance Between Pads G Distance Between Pads GX Overall Width Z MIN MILLIMETERS NOM 0.95 BSC 2.80 MAX 0.60 1.10 1.70 0.35 3.90 Notes: 1. Dimensioning and tolerancing per ASME Y14.5M BSC: Basic Dimension. Theoretically exact value shown without tolerances. Microchip Technology Drawing No. C04-2091B [OT]  2019 Microchip Technology Inc. DS20006209A-page 35 MCP6V36/6U/7/9 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS20006209A-page 36  2019 Microchip Technology Inc. MCP6V36/6U/7/9 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2019 Microchip Technology Inc. DS20006209A-page 37 MCP6V36/6U/7/9 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS20006209A-page 38  2019 Microchip Technology Inc. MCP6V36/6U/7/9 8-Lead Plastic Dual Flat, No Lead Package (MN) – 2x3x0.8 mm Body [TDFN] With 1.4x1.3 mm Exposed Pad (JEDEC Package type WDFN) Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging D A B N (DATUM A) (DATUM B) E NOTE 1 2X 0.15 C 1 2 2X 0.15 C TOP VIEW 0.10 C C (A3) A SEATING PLANE 8X 0.08 C A1 SIDE VIEW 0.10 C A B D2 L 1 2 0.10 C A B NOTE 1 E2 K N 8X b e 0.10 0.05 C A B C BOTTOM VIEW Microchip Technology Drawing No. C04-129-MN Rev E Sheet 1 of 2  2019 Microchip Technology Inc. DS20006209A-page 39 MCP6V36/6U/7/9 8-Lead Plastic Dual Flat, No Lead Package (MN) – 2x3x0.8 mm Body [TDFN] With 1.4x1.3 mm Exposed Pad (JEDEC Package type WDFN) Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging Units Dimension Limits N Number of Pins e Pitch A Overall Height A1 Standoff Contact Thickness A3 D Overall Length Overall Width E Exposed Pad Length D2 Exposed Pad Width E2 b Contact Width L Contact Length Contact-to-Exposed Pad K MIN 0.70 0.00 1.35 1.25 0.20 0.25 0.20 MILLIMETERS NOM 8 0.50 BSC 0.75 0.02 0.20 REF 2.00 BSC 3.00 BSC 1.40 1.30 0.25 0.30 - MAX 0.80 0.05 1.45 1.35 0.30 0.45 - Notes: 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. Package may have one or more exposed tie bars at ends. 3. Package is saw singulated 4. Dimensioning and tolerancing per ASME Y14.5M BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only. Microchip Technology Drawing No. C04-129-MN Rev E Sheet 2 of 2 DS20006209A-page 40  2019 Microchip Technology Inc. MCP6V36/6U/7/9 8-Lead Plastic Dual Flat, No Lead Package (MN) – 2x3x0.8 mm Body [TDFN] With 1.4x1.3 mm Exposed Pad (JEDEC Package type WDFN) Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging X2 EV 8 ØV C Y2 EV Y1 1 2 SILK SCREEN X1 E RECOMMENDED LAND PATTERN Units Dimension Limits E Contact Pitch Optional Center Pad Width X2 Optional Center Pad Length Y2 Contact Pad Spacing C Contact Pad Width (X8) X1 Contact Pad Length (X8) Y1 Thermal Via Diameter V Thermal Via Pitch EV MIN MILLIMETERS NOM 0.50 BSC MAX 1.60 1.50 2.90 0.25 0.85 0.30 1.00 Notes: 1. Dimensioning and tolerancing per ASME Y14.5M BSC: Basic Dimension. Theoretically exact value shown without tolerances. 2. For best soldering results, thermal vias, if used, should be filled or tented to avoid solder loss during reflow process Microchip Technology Drawing No. C04-129-MN Rev. B  2019 Microchip Technology Inc. DS20006209A-page 41 MCP6V36/6U/7/9 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS20006209A-page 42  2019 Microchip Technology Inc. MCP6V36/6U/7/9 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2019 Microchip Technology Inc. DS20006209A-page 43 MCP6V36/6U/7/9 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS20006209A-page 44  2019 Microchip Technology Inc. MCP6V36/6U/7/9 APPENDIX A: REVISION HISTORY Revision A (July 2019) • Initial release of this document.  2019 Microchip Technology Inc. DS20006209A-page 45 MCP6V36/6U/7/9 NOTES: DS20006209A-page 46  2019 Microchip Technology Inc. MCP6V36/6U/7/9 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. [X](1) –X Device Tape and Reel Temperature Range Device: /XX Package MCP6V36T: Single Op Amp (Tape and Reel) (SOT-23) MCP6V36UT: Single Op Amp (Tape and Reel) (SC-70, SOT-23) MCP6V37: Dual Op Amp (MSOP, 2x3 TDFN) MCP6V37T: Dual Op Amp (Tape and Reel) (MSOP, 2x3 TDFN) MCP6V39: Quad Op Amp (TSSOP) MCP6V39T: Quad Op Amp (Tape and Reel) (TSSOP) Examples: a) MCP6V36T-E/OT: a) MCP6V36UT-E/LTY: Tape and Reel Extended temperature, 5LD SC70 package MCP6V36UT-E/OT: Tape and Reel, Extended temperature, 5LD SOT-23 package b) a) b) Temperature Range: E = -40°C to +125°C (Extended) Package: LTY* = Plastic Small Outline Transistor, 5-lead OT = Plastic Small Outline Transistor, 5-lead MNY* = Plastic Dual Flat, No-Lead - 2×3×0.8 mm Body, 8-lead MS = Plastic Micro Small Outline, 8-lead ST = Plastic Thin Shrink Small Outline - 4.4 mm Body, 14-lead c) MCP6V37-E/MS: Extended temperature, 8LD MSOP package MCP6V37T-E/MS: Tape and Reel, Extended temperature, 8LD MSOP package MCP6V37T-E/MNY: Tape and Reel, Extended temperature, 8LD 2x3 TDFN package a) MCP6V39-E/ST: b) MCP6V39T-E/ST: * Y = Nickel palladium gold manufacturing designator. Only available on the TDFN and SC-70 packages. Note 1:  2019 Microchip Technology Inc. Tape and Reel, Extended temperature, 5LD SOT-23 package Extended temperature, 14LD TSSOP package Tape and Reel Extended temperature, 14LD TSSOP package Tape and Reel identifier only appears in the catalog part number description. This identifier is used for ordering purposes and is not printed on the device package. Check with your Microchip Sales Office for package availability with the Tape and Reel option. DS20006209A-page 47 MCP6V36/6U/7/9 NOTES: DS20006209A-page 48  2019 Microchip Technology Inc. Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. • Microchip is willing to work with the customer who is concerned about the integrity of their code. • Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer’s risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights unless otherwise stated. Trademarks The Microchip name and logo, the Microchip logo, Adaptec, AnyRate, AVR, AVR logo, AVR Freaks, BesTime, BitCloud, chipKIT, chipKIT logo, CryptoMemory, CryptoRF, dsPIC, FlashFlex, flexPWR, HELDO, IGLOO, JukeBlox, KeeLoq, Kleer, LANCheck, LinkMD, maXStylus, maXTouch, MediaLB, megaAVR, Microsemi, Microsemi logo, MOST, MOST logo, MPLAB, OptoLyzer, PackeTime, PIC, picoPower, PICSTART, PIC32 logo, PolarFire, Prochip Designer, QTouch, SAM-BA, SenGenuity, SpyNIC, SST, SST Logo, SuperFlash, Symmetricom, SyncServer, Tachyon, TempTrackr, TimeSource, tinyAVR, UNI/O, Vectron, and XMEGA are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. APT, ClockWorks, The Embedded Control Solutions Company, EtherSynch, FlashTec, Hyper Speed Control, HyperLight Load, IntelliMOS, Libero, motorBench, mTouch, Powermite 3, Precision Edge, ProASIC, ProASIC Plus, ProASIC Plus logo, Quiet-Wire, SmartFusion, SyncWorld, Temux, TimeCesium, TimeHub, TimePictra, TimeProvider, Vite, WinPath, and ZL are registered trademarks of Microchip Technology Incorporated in the U.S.A. Adjacent Key Suppression, AKS, Analog-for-the-Digital Age, Any Capacitor, AnyIn, AnyOut, BlueSky, BodyCom, CodeGuard, CryptoAuthentication, CryptoAutomotive, CryptoCompanion, CryptoController, dsPICDEM, dsPICDEM.net, Dynamic Average Matching, DAM, ECAN, EtherGREEN, In-Circuit Serial Programming, ICSP, INICnet, Inter-Chip Connectivity, JitterBlocker, KleerNet, KleerNet logo, memBrain, Mindi, MiWi, MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach, Omniscient Code Generation, PICDEM, PICDEM.net, PICkit, PICtail, PowerSmart, PureSilicon, QMatrix, REAL ICE, Ripple Blocker, SAM-ICE, Serial Quad I/O, SMART-I.S., SQI, SuperSwitcher, SuperSwitcher II, Total Endurance, TSHARC, USBCheck, VariSense, ViewSpan, WiperLock, Wireless DNA, and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. The Adaptec logo, Frequency on Demand, Silicon Storage Technology, and Symmcom are registered trademarks of Microchip Technology Inc. in other countries. GestIC is a registered trademark of Microchip Technology Germany II GmbH & Co. KG, a subsidiary of Microchip Technology Inc., in other countries. All other trademarks mentioned herein are property of their respective companies. © 2019, Microchip Technology Incorporated, All Rights Reserved. For information regarding Microchip’s Quality Management Systems, please visit www.microchip.com/quality.  2019 Microchip Technology Inc. ISBN: 978-1-5224-4576-0 DS20006209A-page 49 Worldwide Sales and Service AMERICAS ASIA/PACIFIC ASIA/PACIFIC EUROPE Corporate Office 2355 West Chandler Blvd. Chandler, AZ 85224-6199 Tel: 480-792-7200 Fax: 480-792-7277 Technical Support: http://www.microchip.com/ support Web Address: www.microchip.com Australia - Sydney Tel: 61-2-9868-6733 India - Bangalore Tel: 91-80-3090-4444 China - Beijing Tel: 86-10-8569-7000 India - New Delhi Tel: 91-11-4160-8631 Austria - Wels Tel: 43-7242-2244-39 Fax: 43-7242-2244-393 China - Chengdu Tel: 86-28-8665-5511 India - Pune Tel: 91-20-4121-0141 Denmark - Copenhagen Tel: 45-4450-2828 Fax: 45-4485-2829 China - Chongqing Tel: 86-23-8980-9588 Japan - Osaka Tel: 81-6-6152-7160 Finland - Espoo Tel: 358-9-4520-820 China - Dongguan Tel: 86-769-8702-9880 Japan - Tokyo Tel: 81-3-6880- 3770 China - Guangzhou Tel: 86-20-8755-8029 Korea - Daegu Tel: 82-53-744-4301 France - Paris Tel: 33-1-69-53-63-20 Fax: 33-1-69-30-90-79 China - Hangzhou Tel: 86-571-8792-8115 Korea - Seoul Tel: 82-2-554-7200 China - Hong Kong SAR Tel: 852-2943-5100 Malaysia - Kuala Lumpur Tel: 60-3-7651-7906 China - Nanjing Tel: 86-25-8473-2460 Malaysia - Penang Tel: 60-4-227-8870 China - Qingdao Tel: 86-532-8502-7355 Philippines - Manila Tel: 63-2-634-9065 China - Shanghai Tel: 86-21-3326-8000 Singapore Tel: 65-6334-8870 China - Shenyang Tel: 86-24-2334-2829 Taiwan - Hsin Chu Tel: 886-3-577-8366 China - Shenzhen Tel: 86-755-8864-2200 Taiwan - Kaohsiung Tel: 886-7-213-7830 China - Suzhou Tel: 86-186-6233-1526 Taiwan - Taipei Tel: 886-2-2508-8600 China - Wuhan Tel: 86-27-5980-5300 Thailand - Bangkok Tel: 66-2-694-1351 China - Xian Tel: 86-29-8833-7252 Vietnam - Ho Chi Minh Tel: 84-28-5448-2100 Atlanta Duluth, GA Tel: 678-957-9614 Fax: 678-957-1455 Austin, TX Tel: 512-257-3370 Boston Westborough, MA Tel: 774-760-0087 Fax: 774-760-0088 Chicago Itasca, IL Tel: 630-285-0071 Fax: 630-285-0075 Dallas Addison, TX Tel: 972-818-7423 Fax: 972-818-2924 Detroit Novi, MI Tel: 248-848-4000 Houston, TX Tel: 281-894-5983 Indianapolis Noblesville, IN Tel: 317-773-8323 Fax: 317-773-5453 Tel: 317-536-2380 Los Angeles Mission Viejo, CA Tel: 949-462-9523 Fax: 949-462-9608 Tel: 951-273-7800 Raleigh, NC Tel: 919-844-7510 New York, NY Tel: 631-435-6000 San Jose, CA Tel: 408-735-9110 Tel: 408-436-4270 Canada - Toronto Tel: 905-695-1980 Fax: 905-695-2078 DS20006209A-page 50 China - Xiamen Tel: 86-592-2388138 China - Zhuhai Tel: 86-756-3210040 Germany - Garching Tel: 49-8931-9700 Germany - Haan Tel: 49-2129-3766400 Germany - Heilbronn Tel: 49-7131-72400 Germany - Karlsruhe Tel: 49-721-625370 Germany - Munich Tel: 49-89-627-144-0 Fax: 49-89-627-144-44 Germany - Rosenheim Tel: 49-8031-354-560 Israel - Ra’anana Tel: 972-9-744-7705 Italy - Milan Tel: 39-0331-742611 Fax: 39-0331-466781 Italy - Padova Tel: 39-049-7625286 Netherlands - Drunen Tel: 31-416-690399 Fax: 31-416-690340 Norway - Trondheim Tel: 47-7288-4388 Poland - Warsaw Tel: 48-22-3325737 Romania - Bucharest Tel: 40-21-407-87-50 Spain - Madrid Tel: 34-91-708-08-90 Fax: 34-91-708-08-91 Sweden - Gothenberg Tel: 46-31-704-60-40 Sweden - Stockholm Tel: 46-8-5090-4654 UK - Wokingham Tel: 44-118-921-5800 Fax: 44-118-921-5820  2019 Microchip Technology Inc. 05/14/19