MCP6V76/6U/7/9
170 µA, 2 MHz Zero-Drift Op Amps
Features
Description
• High DC Precision:
- VOS Drift: ±150 nV/°C (maximum)
- VOS: ±25 µV (maximum)
- AOL: 111 dB (minimum, VDD = 5.5V)
- PSRR: 110 dB (minimum, VDD = 5.5V)
- CMRR: 112 dB (minimum, VDD = 5.5V)
- Eni: 0.45 µVP-P (typical), f = 0.1 Hz to 10 Hz
- Eni: 0.15 µVP-P (typical), f = 0.01 Hz to 1 Hz
• Enhanced EMI Protection:
- Electromagnetic Interference Rejection Ratio
(EMIRR) at 1.8 GHz: 96 dB
• Low Power and Supply Voltages:
- IQ: 170 µA/amplifier (typical)
- Wide Supply Voltage Range: 2V to 5.5V
• Small Packages:
- Singles in SC70, SOT-23
- Duals in MSOP-8, 2x3 TDFN
- Quads in TSSOP-14
• Easy to Use:
- Rail-to-Rail Input/Output
- Gain Bandwidth Product: 2 MHz (typical)
- Unity Gain Stable
• Extended Temperature Range: -40°C to +125°C
The Microchip Technology Inc. MCP6V76/6U/7/9
family of operational amplifiers provides input offset
voltage correction for very low offset and offset drift.
These are low-power devices with a gain bandwidth
product of 2 MHz (typical). They are unity-gain stable,
have virtually no 1/f noise and have good Power Supply
Rejection Ratio (PSRR) and Common Mode Rejection
Ratio (CMRR). These products operate with a single
supply voltage as low as 2V, while drawing
170 µA/amplifier (typical) of quiescent current.
The MCP6V76/6U/7/9 family has enhanced EMI protection to minimize any electromagnetic interference
from external sources. This feature makes it well suited
for EMI sensitive applications such as power lines,
radio stations and mobile communications, etc.
The Microchip Technology Inc. MCP6V76/6U/7/9 op
amps are offered in single (MCP6V76 and
MCP6V76U), dual (MCP6V77) and quad (MCP6V79)
packages. They were designed using an advanced
CMOS process.
Typical Applications
•
•
•
•
•
Portable Instrumentation
Sensor Conditioning
Temperature Measurement
DC Offset Correction
Medical Instrumentation
Design Aids
•
•
•
•
FilterLab® Software
Microchip Advanced Part Selector (MAPS)
Analog Demonstration and Evaluation Boards
Application Notes
Related Parts
•
•
•
•
•
MCP6V11/1U/2/4: Zero-Drift, Low Power
MCP6V31/1U/2/4: Zero-Drift, Low Power
MCP6V61/1U: Zero-Drift 1 MHz
MCP6V81/1U: Zero-Drift, 5 MHz
MCP6V91/1U: Zero-Drift, 10 MHz
Package Types
MCP6V76
SOT-23
VOUT 1
VSS 2
VIN+ 3
MCP6V77
MSOP
5 VDD VOUTA
VINA–
4 VIN– VINA+
VSS
1
2
3
4
8
7
6
5
VDD
VOUTB
VINB–
VINB+
MCP6V77
2×3 TDFN *
MCP6V76U
SC70, SOT-23
VOUTA 1
VIN+ 1
5 VDD
VSS 2
VIN– 3
VINA– 2
4 VOUT VINA+ 3
VSS 4
8 VDD
EP
9
7 VOUTB
6 VINB–
5 VINB+
MCP6V79
TSSOP
1
2
3
4
VINB+ 5
VINB– 6
VOUTB 7
VOUTA
VINA–
VINA+
VDD
14 VOUTD
13 VIND–
12 VIND+
11 VSS
10 VINC+
9 VINC–
8 VOUTC
* Includes Exposed Thermal Pad (EP); see Table 3-1.
2020 Microchip Technology Inc.
DS20006323B-page 1
MCP6V76/6U/7/9
Typical Application Circuit
VIN
R1
R2
R3
VOUT
R4
C2
U1
R5
R2
VDD/2
U2
MCP6XXX
VDD/2
MCP6V76
Offset Voltage Correction for Power Driver
DS20006323B-page 2
2020 Microchip Technology Inc.
MCP6V76/6U/7/9
1.0
ELECTRICAL
CHARACTERISTICS
1.1
Absolute Maximum Ratings †
VDD – VSS .................................................................................................................................................................6.5V
Current at Input Pins ..............................................................................................................................................±2 mA
Analog Inputs (VIN+ and VIN-) (Note 1) .....................................................................................VSS – 1.0V to VDD+1.0V
All Other Inputs and Outputs ......................................................................................................VSS – 0.3V to VDD+0.3V
Difference Input Voltage .................................................................................................................................|VDD – VSS|
Output Short Circuit Current ........................................................................................................................... Continuous
Current at Output and Supply Pins ...................................................................................................................... ±30 mA
Storage Temperature .............................................................................................................................-65°C to +150°C
Maximum Junction Temperature .......................................................................................................................... +150°C
ESD protection on all pins (HBM, CDM, MM)
MCP6V76/6U 4 kV, 1.5 kV, 400V
MCP6V77/9 4 kV, 1.5 kV, 300V
† Notice: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only, and functional operation of the device at those or any other conditions above those
indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability.
Note 1: See Section 4.2.1, Rail-to-Rail Inputs.
1.2
Specifications
TABLE 1-1:
DC ELECTRICAL SPECIFICATIONS
Electrical Characteristics: Unless otherwise indicated, TA = +25°C, VDD = +2V to +5.5V, VSS = GND,
VCM = VDD/3,VOUT = VDD/2, VL = VDD/2, RL = 20 kΩ to VL and CL = 30 pF (refer to Figures 1-4 and 1-5).
Parameters
Sym.
Min.
Typ.
Max.
Units
Conditions
Input Offset Voltage
VOS
-25
—
+25
µV
Input Offset Voltage Drift with
Temperature (Linear Temp. Co.)
TC1
-150
—
+150
nV/°C TA = -40 to +125°C,
(Note 1)
Input Offset Voltage Quadratic
Temp. Co.
TC2
—
-30
—
pV/°C2 TA = -40 to +125°C
Input Offset Voltage Aging
∆VOS
—
±0.75
—
µV
Power Supply Rejection Ratio
PSRR
110
125
—
dB
Input Bias Current
IB
-50
±1
+50
pA
Input Bias Current across
Temperature
IB
—
+20
—
pA
TA = +85°C
IB
0
+0.2
+1.5
nA
TA = +125°C
Input Offset Current
IOS
-250
±60
+250
pA
Input Offset Current across
Temperature
IOS
—
±50
—
pA
TA = +85°C
IOS
-800
±50
+800
pA
TA = +125°C
Input Offset
TA = +25°C
408 hours Life Test at
+150°,
measured at +25°C
Input Bias Current and Impedance
Note 1:
For design guidance only; not tested.
2020 Microchip Technology Inc.
DS20006323B-page 3
MCP6V76/6U/7/9
TABLE 1-1:
DC ELECTRICAL SPECIFICATIONS (CONTINUED)
Electrical Characteristics: Unless otherwise indicated, TA = +25°C, VDD = +2V to +5.5V, VSS = GND,
VCM = VDD/3,VOUT = VDD/2, VL = VDD/2, RL = 20 kΩ to VL and CL = 30 pF (refer to Figures 1-4 and 1-5).
Sym.
Min.
Typ.
Max.
Units
Common Mode Input Impedance
Parameters
ZCM
—
1013||6
—
Ω||pF
Conditions
Differential Input Impedance
ZDIFF
—
1013||6
—
Ω||pF
Common Mode
Input Voltage Range Low
VCML
—
—
VSS 0.2
V
Common Mode
Input Voltage Range High
VCMH
VDD + 0.3
—
—
V
Common Mode Rejection Ratio
CMRR
103
122
—
dB
VDD = 2V,
VCM = -0.2V to 2.3V
CMRR
112
130
—
dB
VDD = 5.5V,
VCM = -0.2V to 5.8V
AOL
96
132
—
dB
VDD = 2V,
VOUT = 0.3V to 1.8V
AOL
111
137
—
dB
VDD = 5.5V,
VOUT = 0.3V to 5.3V
VOL
VSS
VSS + 35
VSS + 121
mV
RL = 2 kΩ, G = +2,
0.5V input overdrive
VOL
—
VSS + 3.5
—
mV
RL = 20 kΩ, G = +2,
0.5V input overdrive
VDD
mV
RL = 2 kΩ, G = +2,
0.5V input overdrive
—
mV
RL = 20 kΩ, G = +2,
0.5V input overdrive
Common Mode
Open-Loop Gain
DC Open-Loop Gain (large signal)
Output
Minimum Output Voltage Swing
Maximum Output Voltage Swing
Output Short Circuit Current
VOH
VDD – 121 VDD – 45
VOH
—
VDD – 4.5
ISC
—
±9
—
mA
VDD = 2V
ISC
—
±26
—
mA
VDD = 5.5V
VDD
2
—
5.5
V
IQ
100
170
260
µA
VPOR
0.9
1.2
1.6
V
Power Supply
Supply Voltage
Quiescent Current per Amplifier
POR Trip Voltage
Note 1:
IO = 0
For design guidance only; not tested.
DS20006323B-page 4
2020 Microchip Technology Inc.
MCP6V76/6U/7/9
TABLE 1-2:
AC ELECTRICAL SPECIFICATIONS
Electrical Characteristics: Unless otherwise indicated, TA = +25°C, VDD = +2V to +5.5V, VSS = GND,
VCM = VDD/3, VOUT = VDD/2, VL = VDD/2, RL = 20 kΩ to VL and CL = 30 pF (refer to Figure 1-4 and Figure 1-5).
Parameters
Sym.
Min.
Typ.
Max.
Units
GBWP
—
2
—
MHz
Conditions
Amplifier AC Response
Gain Bandwidth Product
Slew Rate
SR
—
1.0
—
V/µs
Phase Margin
PM
—
60
—
°
Eni
—
0.15
—
µVP-P
f = 0.01 Hz to 1 Hz
µVP-P
f = 0.1 Hz to 10 Hz
G = +1
Amplifier Noise Response
Input Noise Voltage
Eni
—
0.45
—
Input Noise Voltage Density
eni
—
21
—
nV/√Hz f < 2 kHz
Input Noise Current Density
ini
—
5
—
fA/√Hz
IMD
—
11
—
µVPK
Amplifier Distortion (Note 1)
Intermodulation Distortion (AC)
VCM tone = 100 mVPK at 1 kHz, GN = 1
Amplifier Step Response
Start Up Time
tSTR
—
200
—
µs
G = +1, 0.1% VOUT settling (Note 2)
Offset Correction Settling Time
tSTL
—
15
—
µs
G = +1, VIN step of 2V,
VOS within 100 µV of its final value
Output Overdrive Recovery Time
tODR
—
40
—
µs
G = -10, ±0.5V input overdrive to VDD/2,
VIN 50% point to VOUT 90% point (Note 3)
EMIRR
—
75
—
dB
VIN = 0.1 VPK, f = 400 MHz
—
89
—
VIN = 0.1 VPK, f = 900 MHz
—
96
—
VIN = 0.1 VPK, f = 1800 MHz
—
98
—
VIN = 0.1 VPK, f = 2400 MHz
EMI Protection
EMI Rejection Ratio
Note 1:
2:
3:
These parameters were characterized using the circuit in Figure 1-6. In Figures 2-36 and 2-37, there is
an IMD tone at DC, a residual tone at 1 kHz and other IMD tones and clock tones.
High gains behave differently; see Section 4.3.2, Offset at Power Up.
tODR includes some uncertainty due to clock edge timing.
TABLE 1-3:
TEMPERATURE SPECIFICATIONS
Electrical Characteristics: Unless otherwise indicated, all limits are specified for: VDD = +2V to +5.5V, VSS = GND.
Parameters
Sym.
Min.
Typ.
Max.
Units
Specified Temperature Range
TA
-40
—
+125
°C
Operating Temperature Range
TA
-40
—
+125
°C
Storage Temperature Range
TA
-65
—
+150
°C
Thermal Resistance, 5L-SC-70
JA
—
209
—
°C/W
Thermal Resistance, 5L-SOT-23
JA
—
201
—
°C/W
Thermal Resistance, 8L-2x3 TDFN
JA
—
53
—
°C/W
Thermal Resistance, 8L-MSOP
JA
—
211
—
°C/W
Thermal Resistance, 14L-TSSOP
JA
—
100
—
°C/W
Conditions
Temperature Ranges
(Note 1)
Thermal Package Resistances
Note 1:
Operation must not cause TJ to exceed Maximum Junction Temperature specification (+150°C).
2020 Microchip Technology Inc.
DS20006323B-page 5
MCP6V76/6U/7/9
1.3
Timing Diagrams
1.4
2V to 5.5V
2V
VDD 0V
tSTR
1.001(VDD/3)
VOUT
Test Circuits
The circuits used for most DC and AC tests are shown
in Figures 1-4 and 1-5. Lay out the bypass capacitors
as discussed in Section 4.3.9 “Supply Bypassing
and Filtering”. RN is equal to the parallel combination
of RF and RG to minimize bias current effects.
0.999(VDD/3)
FIGURE 1-1:
Amplifier Start Up.
VDD
1 µF
RN
VIN
RISO
VOUT
MCP6V7X
VIN
tSTL
VOS + 100 µV
RG
VOS
VOS – 100 µV
FIGURE 1-2:
Time.
100 nF
VDD/3
Offset Correction Settling
1 µF
RISO
VOUT
MCP6V7X
tODR
100 nF
VIN
VDD
RG
tODR
VDD/2
VSS
FIGURE 1-3:
VL
FIGURE 1-4:
AC and DC Test Circuit for
Most Noninverting Gain Conditions.
VDD/3 RN
VOUT
RL
RF
VDD
VIN
CL
Output Overdrive Recovery.
CL
RL
VL
RF
FIGURE 1-5:
AC and DC Test Circuit for
Most Inverting Gain Conditions.
The circuit in Figure 1-6 tests the input’s dynamic
behavior (i.e., IMD, tSTR, tSTL and tODR). The
potentiometer balances the resistor network (VOUT
should equal VREF at DC). The op amp’s Common
mode input voltage is VCM = VIN/2. The error at the
input (VERR) appears at VOUT with a noise gain of
10 V/V.
11.0 kΩ 100 kΩ 500Ω
0.1%
0.1% 25 turn
VREF = VDD/3
VDD
1 µF
VIN
100 nF
MCP6V7X
11.0 kΩ 100 kΩ 249Ω
1%
0.1%
0.1%
FIGURE 1-6:
Input Behavior.
DS20006323B-page 6
RISO
0Ω
VOUT
RL
open
CL
30 pF
VL
Test Circuit for Dynamic
2020 Microchip Technology Inc.
MCP6V76/6U/7/9
2.0
TYPICAL PERFORMANCE CURVES
Note:
The graphs and tables provided following this note are a statistical summary based on a limited number of
samples and are provided for informational purposes only. The performance characteristics listed herein
are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified
operating range (e.g., outside specified power supply range) and therefore outside the warranted range.
Note: Unless otherwise indicated, TA = +25°C, VDD = +2V to 5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2,
VL = VDD/2, RL = 20 kΩ to VL and CL = 30 pF.
DC Input Precision
8
28 Samples
6
2
0
-2
-4
-6
Representative Part
VCM = VCML
FIGURE 2-1:
Input Offset Voltage.
0%
FIGURE 2-2:
Input Offset Voltage Drift.
6.5
6.0
5.0
5.5
6.5
6.0
5.5
5.0
4.5
4.0
Power Supply Voltage (V)
FIGURE 2-5:
Input Offset Voltage vs.
Power Supply Voltage with VCM = VCMH.
8
28 Samples
TA = -40°C to +125°C
VDD = 5.5V
50%
40%
VDD = 2V
20%
10%
Input Offset Voltage (µV)
80%
Percentage of Occurrences
3.5
-8
8 10 12
Input Offset Voltage Drift; TC1 (nV/°C)
30%
4.5
Representative Part
VCM = VCMH
3.0
6
-6
2.5
4
-4
2.0
2
0
-2
0.0
-12 -10 -8 -6 -4 -2 0
2
1.5
10%
TA = - 40°C
TA = +25°C
TA = +85°C
TA = +125°C
4
1.0
20%
6
0.5
VDD = 2V
Input Offset Voltage (µV)
Percentage of Occurances
VDD = 5.5V
30%
60%
4.0
FIGURE 2-4:
Input Offset Voltage vs.
Power Supply Voltage with VCM = VCML.
8
28 Samples
TA = -40°C to +125°C
40%
70%
3.5
Power Supply Voltage (V)
60%
50%
3.0
0.0
Input Offset Voltage (µV)
2.5
-8
-2 -1.5 -1 -0.5 0 0.5 1 1.5 2 2.5 3 3.5 4
2.0
VDD = 2V
TA = +125°C
TA = +85°C
TA = +25°C
TA = - 40°C
4
1.5
VDD = 5.5V
1.0
TA = 25ºC
0.5
50%
45%
40%
35%
30%
25%
20%
15%
10%
5%
0%
Input Offset Voltage (µV)
Percentage of Occurences
2.1
Representative Part
VDD = 2.0V
6
4
2
0
TA = +125°C
TA = +85°C
TA = +25°C
TA = -40°C
-2
-4
-6
0%
-200 -160 -120 -80 -40
0
40
80 120
Input Offset Voltage Quadratric Temp Co;
TC2 (pV/°C2)
FIGURE 2-3:
Input Offset Voltage
Quadratic Temp. Co.
2020 Microchip Technology Inc.
-8
0.0
0.2
0.4
0.6 0.8 1.0 1.2 1.4
Output Voltage (V)
1.6
1.8
2.0
FIGURE 2-6:
Input Offset Voltage vs.
Output Voltage with VDD = 2.0V.
DS20006323B-page 7
MCP6V76/6U/7/9
Note: Unless otherwise indicated, TA = +25°C, VDD = +2V to 5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2,
VL = VDD/2, RL = 20 kΩ to VL and CL = 30 pF.
160
6
TA = - 40°C
TA = +25°C
TA = +85°C
TA = +125°C
4
2
CMRR, PSRR (dB)
Input Offset Voltage (µV)
8
0
-2
-4
Representative Part
VDD = 5.5V
-6
150
PSRR
140
130
CMRR @ VDD = 5.5V
@ VDD = 2V
120
110
-50
-8
-25
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Power Supply Voltage (V)
FIGURE 2-7:
Input Offset Voltage vs.
Output Voltage with VDD = 5.5V.
DC Open-Loop Gain (dB)
Input Offset Voltage (µV)
TA = +125°C
TA = +85°C
TA = +25°C
TA = - 40°C
4
2
0
-2
-4
-6
Representative Part
VDD = 2.0V
-8
-0.5
25
50
75
100
125
FIGURE 2-10:
CMRR and PSRR vs.
Ambient Temperature.
8
6
0
Ambient Temperature (°C)
170
VDD= 5.5V
160
150
140
VDD= 2V
130
120
110
0.0
0.5
1.0
1.5
2.0
Common Mode Input Voltage (V)
2.5
-50
-25
0
25
50
75
100
125
Ambient Temperature (°C)
FIGURE 2-11:
DC Open-Loop Gain vs.
Ambient Temperature.
FIGURE 2-8:
Input Offset Voltage vs.
Common Mode Voltage with VDD = 2V.
Input Offset Voltage (µV)
8
Representative Part
VDD = 5.5V
6
TA = +125°C
TA = +85°C
TA = +25°C
TA = -40°C
4
2
0
-2
-4
-6
5.5
6.0
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
-0.5
-8
Common Mode Input Voltage (V)
FIGURE 2-9:
Input Offset Voltage vs.
Common Mode Voltage with VDD = 5.5V.
DS20006323B-page 8
2020 Microchip Technology Inc.
MCP6V76/6U/7/9
Note: Unless otherwise indicated, TA = +25°C, VDD = +2V to 5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2,
VL = VDD/2, RL = 20 kΩ to VL and CL = 30 pF.
Input Bias and Offset Currents
(pA)
Input Current Magnitude (A)
1m
1,000
800
600
400
200
0
-200
-400
-600
-800
-1,000
VDD = 5.5 V
TA = 85ºC
Input Offset Current
6.0
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
-0.5
Input Bias Current
Input Common Mode Voltage (V)
1µ
100n
10n
1n
TA = +125°C
TA = +85°C
TA = +25°C
TA = -40°C
100p
-1.0 -0.9 -0.8 -0.7 -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0.0
FIGURE 2-15:
Input Bias Current vs. Input
Voltage (below VSS).
VDD = 5.5 V
TA = 125ºC
Input Bias Current
6.0
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
Input Offset Current
-0.5
Input Bias and Offset Currents
(pA)
10µ
Input Voltage (V)
FIGURE 2-12:
Input Bias and Offset
Currents vs. Common Mode Input Voltage with
TA = +85°C.
1000
800
600
400
200
0
-200
-400
-600
-800
-1000
100µ
Input Common Mode Voltage (V)
1000
1n
VDD = 5.5 V
Input Offset Current
100
100p
10
10p
Input Bias Current
1
1p
125
115
105
95
85
75
65
55
45
35
0.1
0.1p
25
Input Bias, Offset Currents (A)
FIGURE 2-13:
Input Bias and Offset
Currents vs. Common Mode Input Voltage with
TA = +125°C.
Ambient Temperature (°C)
FIGURE 2-14:
Input Bias and Offset
Currents vs. Ambient Temperature with
VDD = +5.5V.
2020 Microchip Technology Inc.
DS20006323B-page 9
MCP6V76/6U/7/9
Note: Unless otherwise indicated, TA = +25°C, VDD = +2V to 5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2,
VL = VDD/2, RL = 20 kΩ to VL and CL = 30 pF.
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.0
-0.1
-0.2
-0.3
-0.4
-0.5
Output Short Circuit Current
(mA)
Other DC Voltages and Currents
Input Common Mode Voltage
Headroom (V)
2.2
1 Wafer Lot
Upper (VCMH – VDD)
Lower (VCML – VSS)
40
20
10
0
-10
TA = +125°C
TA = +85°C
TA = +25°C
TA = -40°C
-20
-30
-40
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6 6.5
-50
-25
0
25
50
75
100
Ambient Temperature (°C)
125
Power Supply Voltage (V)
FIGURE 2-19:
Output Short Circuit Current
vs. Power Supply Voltage.
FIGURE 2-16:
Input Common Mode
Voltage Headroom (Range) vs. Ambient
Temperature.
1000
VDD = 2V
100
200
180
160
140
120
100
80
60
40
20
0
Quiescent Current
(µA/Amplifier)
Output Voltage Headroom
(mV)
TA = +125°C
TA = +85°C
TA = +25°C
TA = -40°C
30
VDD -VOH
VDD = 5.5V
10
VOL -VSS
1
0.1
1
10
TA = +125°C
TA = +85°C
TA = +25°C
TA = -40°C
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6 6.5
Output Current Magnitude (mA)
Power Supply Voltage (V)
90
80
50
Supply Current vs. Power
1.6
RL = 2 kΩ
1.4
VDD - VOH
70
60
FIGURE 2-20:
Supply Voltage.
POR Trip Voltage (V)
Output Voltage Headroom (mV)
FIGURE 2-17:
Output Voltage Headroom
vs. Output Current.
VDD = 5.5V
VOL - VSS
40
30
20
VDD = 2V
10
VDD - VOH
0
1.2
1
0.8
0.6
800 Samples
0.4
1 Wafer Lot
0.2
0
-50
-25
0
25
50
75
100
125
Ambient Temperature (°C)
FIGURE 2-18:
Output Voltage Headroom
vs. Ambient Temperature.
DS20006323B-page 10
-50
-25
0
25
50
75
100
125
Ambient Temperature (°C)
FIGURE 2-21:
Power-On Reset Voltage vs.
Ambient Temperature.
2020 Microchip Technology Inc.
MCP6V76/6U/7/9
Note: Unless otherwise indicated, TA = +25°C, VDD = +2V to 5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2,
VL = VDD/2, RL = 20 kΩ to VL and CL = 30 pF.
Frequency Response
4.0
CMRR
PSRRPSRR+
100
100
1000
1k
10000
10k
3.5
PM
60
2.5
50
GBWP
2.0
30
1.0
0.5
10
0
-50
-25
Open-Loop Phase
30
-120
20
-150
Open-Loop Gain
10
-180
0
-210
VDD = 2V
CL = 30 pF
-240
-270
1.E+07
10M
2.5
80
2
70
1.5
1
0.5
40
0
30
0
1
2
3
4
5
6
7
30
-90
-120
-150
Open-Loop Gain
10
-180
0
-210
VDD = 5.5V
CL = 30 pF
-240
1.E+06
1M
-270
1.E+07
10M
f (Hz)
FIGURE 2-24:
Open-Loop Gain vs.
Frequency with VDD = 5.5V.
2020 Microchip Technology Inc.
Gain Bandwidth Product (MHz)
Open-Loop Phase
4
Open-Loop Phase (°)
40
Open-Loop Gain (dB)
50
GBWP
FIGURE 2-26:
Gain Bandwidth Product
and Phase Margin vs. Common Mode Input
Voltage.
-60
1.E+05
100k
60
VDD = 5.5V
VDD = 2V
Common Mode Input Voltage (V)
50
-20
1.E+04
10k
100 125
90
-1
FIGURE 2-23:
Open-Loop Gain vs.
Frequency with VDD = 2V.
-10
75
PM
f (Hz)
20
50
3
Gain Bandwidth Product (MHz)
-90
1.E+06
1M
25
FIGURE 2-25:
Gain Bandwidth Product
and Phase Margin vs. Ambient Temperature.
Open-Loop Phase (°)
Open-Loop Gain (dB)
40
1.E+05
100k
0
Ambient Temperature (°C)
CMRR and PSRR vs.
-60
-20
1.E+04
10k
20
VDD = 2V
0.0
100000
100k
50
-10
40
1.5
Frequency (Hz)
FIGURE 2-22:
Frequency.
70
3.0
Phase Margin (º)
10
10
80
VDD = 5.5V
Phase Margin (°)
Representative Part
65
3.5
60
3
55
VDD = 5.5V
PM
2.5
50
2
45
1.5
40
VDD = 2V
1
35
Phase Margin (º)
CMRR, PSRR (dB)
140
130
120
110
100
90
80
70
60
50
40
30
Gain Bandwidth Product
(MHz)
2.3
GBWP
0.5
30
0
25
0
1
2
3
4
5
6
Output Voltage (V)
FIGURE 2-27:
Gain Bandwidth Product
and Phase Margin vs. Output Voltage.
DS20006323B-page 11
MCP6V76/6U/7/9
Note: Unless otherwise indicated, TA = +25°C, VDD = +2V to 5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2,
VL = VDD/2, RL = 20 kΩ to VL and CL = 30 pF.
Closed Loop Output
Impedance (:))
100000
100k
VDD = 2V
EMIRR (dB)
10000
10k
1000
1k
GN:
101 V/V
11 V/V
1 V/V
100
10
1.0E+03
1k
1.0E+04
10k
1.0E+05
1.0E+06
100k
1.0E+07
1M
10M
120
110
100
90
80
70
60
50
40
30
20
10
0
10
10M
VPK = 100 mV
VDD = 5.5V
100
100M
10000
10G
Frequency (Hz)
Frequency (Hz)
FIGURE 2-31:
FIGURE 2-28:
Closed-Loop Output
Impedance vs. Frequency with VDD = 2V.
100000
100k
1000
1G
EMIRR vs Frequency.
120
VDD = 5.5V
Closed Loop Output
Impedance (Ω)
100
10000
10k
EMIRR (dB)
80
1000
1k
GN:
101 V/V
11 V/V
1 V/V
100
100
10
10
1.0E+03
1k
1.0E+04
10k
1.0E+05
100k
60
40
EMIRR @ 2400 MHz
EMIRR @ 1800 MHz
EMIRR @ 900 MHz
EMIRR @ 400 MHz
VDD = 5.5V
20
1.0E+06
0
0.01
1.0E+07
1M
10M
Frequency (Hz)
FIGURE 2-29:
Closed-Loop Output
Impedance vs. Frequency with VDD = 5.5V.
FIGURE 2-32:
Voltage.
Channel-to-Channel Separation;
RTI (dB)
Output Voltage Swing (VP-P)
1.00
10.00
EMIRR vs RF Input Peak
130
10
VDD = 5.5V
VDD = 2V
1
0.1
0.10
RF Input Peak Voltage (Vp)
1000
1k
10000
10k
100000
100k
Frequency (Hz)
1000000
1M
10000000
10M
FIGURE 2-30:
Maximum Output Voltage
Swing vs. Frequency.
DS20006323B-page 12
120
110
VDD = 5.5V
100
90
VDD = 2.0V
80
70
60
10k
1.E+04
100k
1.E+05
Frequency (Hz)
1M
1.E+06
FIGURE 2-33:
Channel-to-Channel
Separation vs. Frequency.
2020 Microchip Technology Inc.
MCP6V76/6U/7/9
Note: Unless otherwise indicated, TA = +25°C, VDD = +2V to 5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2,
VL = VDD/2, RL = 20 kΩ to VL and CL = 30 pF.
Input Noise and Distortion
1000
VDD = 5.5V, green
VDD = 2V, blue
100
100
eni
10
10
1.E+3
1m
Eni(0 Hz to f)
FIGURE 2-34:
Input Noise Voltage Density
and Integrated Input Noise Voltage vs.
Frequency.
1.E+1
10µ
VDD = 2.0V
20
VDD = 5.5V
15
DC tone
100n
1.E-1
ǻf = 64 Hz
ǻf = 2 Hz
10
5
10
1.E+1
100
1k
1.E+2
1.E+3
Frequency (Hz)
NPBW = 10 Hz
NPBW = 1 Hz
0
10
20
30
40
Common Mode Input Voltage (V)
Residual
1 kHz tone
(due to resistor
mismatch)
DC tone
1.E+0
1µ
100n
1.E-1
60
70
80
90
100
FIGURE 2-38:
Input Noise vs. Time with
1 Hz and 10 Hz Filters and VDD = 2V.
VDD = 5.5V
Input Noise Voltage; eni(t)
(0.1 µV/div)
IMD Spectrum, RTI (VPK)
VDD = 2.0V
VDD = 5.5V
1.E+2
100µ
1.E+1
10µ
50
Time (s)
FIGURE 2-35:
Input Noise Voltage Density
vs. Input Common Mode Voltage.
G = 11 V/V
VCM tone = 100 mVPK, f = 1 kHz
100k
1.E+5
VDD = 2V
0
-0.5 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6
1.E+3
1m
10k
1.E+4
FIGURE 2-37:
Intermodulation Distortion
vs. Frequency with VDD Disturbance
(see Figure 1-6).
Input Noise Voltage; eni(t)
(0.1 µV/div)
Input Noise Voltage Density
Q9¥+]
f < 2 kHz
Residual
1 kHz tone
(due to resistor
mismatch)
1.E+0
1µ
35
30
VDD = 2.0V
VDD = 5.5V
1.E+2
100µ
10n
1.E-2
1
1.E+0
1
1
1
10
100 1.E+3
1k
10k 1.E+5
100k
1.E+0
1.E+1
1.E+2
1.E+4
Frequency (Hz)
25
G = 11 V/V
VCM tone = 100 mVPK, f = 1 kHz
IMD Spectrum, RTI (VPK)
Input Noise Voltage Density;
eni (nV/¥+]
1000
Integrated Input Noise Voltage;
Eni (µVP-P)
2.4
NPBW = 10 Hz
NPBW = 1 Hz
ǻf = 64 Hz
ǻf = 2 Hz
10n
1.E-2
1
1.E+0
0
10
1.E+1
100
1k
1.E+2
1.E+3
Frequency (Hz)
10k
1.E+4
FIGURE 2-36:
Intermodulation Distortion
vs. Frequency with VCM Disturbance (see
Figure 1-6).
2020 Microchip Technology Inc.
10
20
30
40
50
60
70
80
90
100
100k
1.E+5
Time (s)
FIGURE 2-39:
Input Noise vs. Time with
1 Hz and 10 Hz Filters and VDD = 5.5V.
DS20006323B-page 13
MCP6V76/6U/7/9
Note: Unless otherwise indicated, TA = +25°C, VDD = +2V to 5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2,
VL = VDD/2, RL = 20 kΩ to VL and CL = 30 pF.
Time Response
6
25
5
VDD
20
4
VDD = 5.5V
G = +1 V/V
15
3
2
10
POR Trip Point
5
1
VOS
0
0
-5
6
5
Output Voltage (V)
30
Power Supply Voltage (V)
Input Offset Voltage (mV)
2.5
1
2
3
4
5
6
7
8
9
3
2
VDD = 5.5 V
G = +1 V/V
1
0
-1
0
4
0
10
2.5
5
7.5
10
12.5
15
17.5
20
Time (µs)
Time (ms)
FIGURE 2-43:
Step Response.
FIGURE 2-40:
Input Offset Voltage vs.
Time at Power-Up.
Noninverting Large Signal
Output Voltage (20 mV/div)
Input, Output Voltages (V)
6
5
VOUT
VIN
4
3
2
1
VDD = 5.5 V
G = +1 V/V
0
-1
VDD = 5.5 V
G = -1 V/V
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
Time (µs)
Time (5 µs/div)
FIGURE 2-44:
Response.
FIGURE 2-41:
The MCP6V76/6U/7/9
Family Shows No Input Phase Reversal with
Overdrive.
Inverting Small Signal Step
Output Voltage (20 mV/div)
6
Output Voltage (V)
5
VDD = 5.5V
G = +1 V/V
VDD = 5.5 V
G = -1 V/V
4
3
2
1
0
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
0
2.5
DS20006323B-page 14
Noninverting Small Signal
7.5
10
12.5
15
17.5
20
Time (µs/div)
Time (µs)
FIGURE 2-42:
Step Response.
5
FIGURE 2-45:
Response.
Inverting Large Signal Step
2020 Microchip Technology Inc.
MCP6V76/6U/7/9
Slew Rate (V/µs)
Note: Unless otherwise indicated, TA = +25°C, VDD = +2V to 5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2,
VL = VDD/2, RL = 20 kΩ to VL and CL = 30 pF.
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
Falling Edge, VDD = 5.5V
Rising Edge, VDD = 5.5V
Falling Edge, VDD = 2V
Rising Edge, VDD = 2V
-50
-25
0
25
50
75
100
125
Ambient Temperature (°C)
FIGURE 2-46:
Temperature.
Slew Rate vs. Ambient
Input and Output Voltage (V)
7
6
VDD = 5.5 V
G = -10 V/V
0.5V Overdrive
5
4
VOUT
GVIN
GVIN
VOUT
3
2
1
0
-1
Time (50 µs/div)
FIGURE 2-47:
Output Overdrive Recovery
vs. Time with G = -10 V/V.
Overdrive Recovery Time (s)
1m
0.5V Input Overdrive
tODR, low
VDD = 2.0V
100µ
VDD = 5.5V
10µ
tODR, high
1µ
1
10
100
1000
Inverting Gain Magnitude (V/V)
FIGURE 2-48:
Output Overdrive Recovery
Time vs. Inverting Gain.
2020 Microchip Technology Inc.
DS20006323B-page 15
MCP6V76/6U/7/9
3.0
PIN DESCRIPTIONS
Descriptions of the pins are listed in Table 3-1.
TABLE 3-1:
PIN FUNCTION TABLE
MCP6V76
MCP6V76U
MCP6V77
MCP6V79
SOT-23
SOT-23,
SC-70
2×3 TDFN MSOP
TSSOP
1
4
1
1
1
2
2
4
4
11
VSS
3
1
3
3
3
VIN+, VINA+
4
3
2
2
2
VIN-, VINA-
5
5
8
8
4
VDD
—
—
5
5
5
VINB+
Noninverting Input (Op Amp B)
—
—
6
6
6
VINB-
Inverting Input (Op Amp B)
—
—
7
7
7
VOUTB
Output (Op Amp B)
—
—
—
—
8
VOUTC
Output (Op Amp C)
3.1
VOUT, VOUTA Output (Op Amp A)
Negative Power Supply
Noninverting Input (Op Amp A)
Inverting Input (Op Amp A)
Positive Power Supply
—
—
—
—
9
VINC-
Inverting Input (Op Amp C)
—
—
—
10
VINC+
Noninverting Input (Op Amp C)
—
—
—
—
12
VIND+
Noninverting Input (Op Amp D)
—
—
—
—
13
VIND-
Inverting Input (Op Amp D)
—
—
—
—
14
VOUTD
Output (Op Amp D)
—
—
9
—
—
EP
Analog Outputs
Analog Inputs
The noninverting and inverting inputs (VIN+, VIN-, …)
are high-impedance CMOS inputs with low bias
currents.
3.3
Description
—
The analog output pins (VOUT) are low-impedance
voltage sources.
3.2
Symbol
3.4
Exposed Thermal Pad (EP); must be
connected to VSS
Exposed Thermal Pad (EP)
There is an internal connection between the exposed
thermal pad (EP) and the VSS pin; they must be
connected to the same potential on the printed circuit
board (PCB).
This pad can be connected to a PCB ground plane to
provide a larger heat sink. This improves the package
thermal resistance (θJA).
Power Supply Pins
The positive power supply (VDD) is 2V to 5.5V higher
than the negative power supply (VSS). For normal
operation, the other pins are between VSS and VDD.
Typically, these parts are used in a single (positive)
supply configuration. In this case, VSS is connected to
ground and VDD is connected to the supply. VDD will
need bypass capacitors.
DS20006323B-page 16
2020 Microchip Technology Inc.
MCP6V76/6U/7/9
4.0
APPLICATIONS
The MCP6V76/6U/7/9 family of zero-drift op amps is
manufactured using Microchip’s state of the art CMOS
process. It is designed for applications with requirements for small packages and low power. Its low supply
voltage and low quiescent current make the
MCP6V76/6U/7/9 devices ideal for battery-powered
applications.
4.1
Overview of Zero-Drift Operation
Figure 4-1 shows a simplified diagram of the
MCP6V76/6U/7/9 zero-drift op amp. This diagram will
be used to explain how slow voltage errors are reduced
in this architecture (much better VOS, ∆VOS/∆TA (TC1),
CMRR, PSRR, AOL and 1/f noise).
The low-pass filter reduces high-frequency content,
including harmonics of the chopping clock.
The output buffer drives external loads at the VOUT pin
(VREF is an internal reference voltage).
The oscillator runs at fOSC1 = 200 kHz. Its output is
divided by two to produce the chopping clock rate of
fCHOP = 100 kHz.
The internal POR part starts the part in a known good
state, protecting against power supply brown-outs.
The digital control block controls switching and POR
events.
4.1.2
CHOPPING ACTION
Figure 4-2 shows the amplifier connections for the first
phase of the chopping clock and Figure 4-3 shows
them for the second phase. Its slow voltage errors
alternate in polarity, making the average error small.
VREF
Output
Buffer
VOUT
VIN+
VIN+
VIN–
Main
Amp.
VIN–
NC
Aux.
Amp.
Chopper
Output
Switches
Aux.
Amp.
FIGURE 4-2:
First Chopping Clock Phase;
Equivalent Amplifier Diagram.
POR
VIN+
FIGURE 4-1:
Simplified Zero-Drift Op
Amp Functional Diagram.
VIN–
Oscillator
4.1.1
Digital Control
NC
Low-Pass
Filter
Low-Pass
Filter
Chopper
Input
Switches
Main
Amp.
Main
Amp.
NC
BUILDING BLOCKS
The Main amplifier is designed for high gain and
bandwidth, with a differential topology. Its main input
pair (+ and - pins at the top left) is used for the higher
frequency portion of the input signal. Its auxiliary input
pair (+ and - pins at the bottom left) is used for the lowfrequency portion of the input signal and corrects the
op amp’s input offset voltage. Both inputs are added
together internally.
The Auxiliary amplifier, chopper input switches and
chopper output switches provide a high DC gain to the
input signal. DC errors are modulated to higher
frequencies, while white noise is modulated to low
frequencies.
2020 Microchip Technology Inc.
Low-Pass
Filter
Aux.
Amp.
FIGURE 4-3:
Second Chopping Clock
Phase; Equivalent Amplifier Diagram.
DS20006323B-page 17
MCP6V76/6U/7/9
4.1.3
INTERMODULATION DISTORTION
(IMD)
These op amps will show intermodulation distortion
(IMD) products when an AC signal is present.
The signal and clock can be decomposed into sine
wave tones (Fourier series components). These tones
interact with the zero-drift circuitry’s nonlinear response
to produce IMD tones at sum and difference frequencies. Each of the square wave clock’s harmonics has a
series of IMD tones centered on it. See Figures 2-36
and 2-37.
4.2
Other Functional Blocks
4.2.1
The input ESD diodes clamp the inputs when they try
to go more than one diode drop below VSS. They also
clamp any voltages well above VDD; their breakdown
voltage is high enough to allow normal operation, but
not low enough to protect against slow overvoltage
(beyond VDD) events. Very fast ESD events (that meet
the spec) are limited so that damage does not occur.
In some applications, it may be necessary to prevent
excessive voltages from reaching the op amp inputs;
Figure 4-5 shows one approach to protecting these
inputs. D1 and D2 may be small signal silicon diodes,
Schottky diodes for lower clamping voltages or diodeconnected FETs for low leakage.
RAIL-TO-RAIL INPUTS
The input stage of the MCP6V76/6U/7/9 op amps uses
two differential CMOS input stages in parallel. One
operates at low Common Mode Input Voltage (VCM,
which is approximately equal to VIN+ and VIN- in normal
operation) and the other at high VCM. With this
topology, the input operates with VCM up to VDD + 0.3V,
and down to VSS – 0.2V, at +25°C (see Figure 2-16).
The input offset voltage (VOS) is measured at
VCM = VSS – 0.2V and VDD + 0.3V to ensure proper
operation.
4.2.1.1
Phase Reversal
VDD
U1
D1
MCP6V7X
V1
D2
VOUT
V2
FIGURE 4-5:
Protecting the Analog Inputs
Against High Voltages.
The input devices are designed to not exhibit phase
inversion when the input pins exceed the supply
voltages. Figure 2-41 shows an input voltage
exceeding both supplies with no phase inversion.
4.2.1.2
Input Voltage Limits
In order to prevent damage and/or improper operation
of these amplifiers, the circuit must limit the voltages at
the input pins (see Section 1.1 “Absolute Maximum
Ratings †”). This requirement is independent of the
current limits discussed later.
The ESD protection on the inputs can be depicted as
shown in Figure 4-4. This structure was chosen to
protect the input transistors against many (but not all)
overvoltage conditions and to minimize input bias
current (IB).
VDD Bond
Pad
VIN+
Bond
Pad
Input
Stage
Bond
VIN–
Pad
VSS Bond
Pad
FIGURE 4-4:
Structures.
DS20006323B-page 18
Simplified Analog Input ESD
2020 Microchip Technology Inc.
MCP6V76/6U/7/9
4.2.1.3
4.3
Input Current Limits
In order to prevent damage and/or improper operation
of these amplifiers, the circuit must limit the currents
into the input pins (see Section 1.1 “Absolute Maximum Ratings †”). This requirement is independent of
the voltage limits discussed previously.
Figure 4-6 shows one approach to protecting these
inputs. The resistors R1 and R2 limit the possible
current in or out of the input pins (and into D1 and D2).
The diode currents will dump onto VDD.
V1
V2
R1
INPUT OFFSET VOLTAGE OVER
TEMPERATURE
Table 1-1 gives both the linear and quadratic
temperature coefficients (TC1 and TC2) of input offset
voltage. The input offset voltage, at any temperature in
the specified range, can be calculated as follows:
EQUATION 4-1:
2
Where:
U1
MCP6V7X
D2
4.3.1
V OS T A = VOS + TC 1 T + TC 2 T
VDD
D1
Application Tips
∆T
=
TA – 25°C
VOS(TA)
=
input offset voltage at TA
VOS
=
input offset voltage at +25°C
TC1
=
linear temperature coefficient
TC2
=
quadratic temperature coefficient
VOUT
R2
VSS – min(V1, V2)
2 mA
max(V1, V2) – VDD
min(R1, R2) >
2 mA
min(R1, R2) >
FIGURE 4-6:
Protecting the Analog Inputs
Against High Currents.
It is also possible to connect the diodes to the left of
resistors R1 and R2. In this case, the currents through
diodes D1 and D2 need to be limited by some other
mechanism. The resistors then serve as in-rush current
limiters; the DC current into the input pins (VIN+ and
VIN-) should be very small.
4.3.2
OFFSET AT POWER UP
When these parts power up, the input offset (VOS) starts
at its uncorrected value. Circuits with high DC gain can
cause the output to reach one of the two rails. In this
case, the time to a valid output is delayed by an output
overdrive time (like tODR) in addition to the start-up time
(like tSTR).
It can be simple to avoid this extra start-up time.
Reducing the gain is one method. Adding a capacitor
across the feedback resistor (RF) is another method.
A significant amount of current can flow out of the
inputs (through the ESD diodes) when the Common
Mode Voltage (VCM) is below ground (VSS) (see
Figure 2-15).
4.2.2
RAIL-TO-RAIL OUTPUT
The output voltage range of the MCP6V76/6U/7/9 zerodrift op amps is VDD – 5.9 mV (typical) and
VSS + 4.5 mV (typical) when RL = 20 kΩ is connected to
VDD/2 and VDD = 5.5V. Refer to Figures 2-17 and 2-18
for more information.
This op amp is designed to drive light loads; use
another amplifier to buffer the output from heavy loads.
2020 Microchip Technology Inc.
DS20006323B-page 19
MCP6V76/6U/7/9
SOURCE RESISTANCES
The input bias currents have two significant
components: switching glitches that dominate at room
temperature and below and input ESD diode leakage
currents that dominate at +85°C and above.
Make the resistances seen by the inputs small and
equal. This minimizes the output offset caused by the
input bias currents.
The inputs should see a resistance on the order of 10Ω
to 1 kΩ at high frequencies (i.e., above 1 MHz). This
helps minimize the impact of switching glitches, which
are very fast, on overall performance. In some cases, it
may be necessary to add resistors in series with the
inputs to achieve this improvement in performance.
Small input resistances may be needed for high gains.
Without them, parasitic capacitances might cause
positive feedback and instability.
4.3.4
SOURCE CAPACITANCE
The capacitances seen by the two inputs should be
small. Large input capacitances and source resistances, together with high gain, can lead to positive
feedback and instability.
4.3.5
CAPACITIVE LOADS
Driving large capacitive loads can cause stability
problems for voltage feedback op amps. As the load
capacitance increases, the feedback loop’s phase
margin decreases and the closed-loop bandwidth is
reduced. This produces gain peaking in the frequency
response, with overshoot and ringing in the step
response. These zero-drift op amps have a different
output impedance than most op amps, due to their
unique topology.
When driving a capacitive load with these op amps, a
series resistor at the output (RISO in Figure 4-7)
improves the feedback loop’s phase margin (stability)
by making the output load resistive at higher
frequencies. The bandwidth will be generally lower
than the bandwidth with no capacitive load.
GN is the circuit’s noise gain. For noninverting gains,
GN and the Signal Gain are equal. For inverting gains,
GN is 1+|Signal Gain| (e.g., -1 V/V gives GN = +2 V/V).
10000
Recommended R ISO (Ω)
4.3.3
VDD = 5.5 V
RL = 20 kȍ
1000
100
GN:
1 V/V
10 V/V
100 V/V
10
1
100p
1.E-10
1n
1.E-09
10n
1.E-08
100n
1.E-07
1µ
1.E-06
Normalized Load Capacitance; CL/¥GN (F)
FIGURE 4-8:
Recommended RISO Values
for Capacitive Loads.
After selecting RISO for your circuit, double check the
resulting frequency response peaking and step
response overshoot. Modify RISO's value until the
response is reasonable. Bench evaluation is helpful.
4.3.6
STABILIZING OUTPUT LOADS
This family of zero-drift op amps has an output
impedance (Figures 2-28 and 2-29) that has a double
zero when the gain is low. This can cause a large phase
shift in feedback networks that have low-impedance
near the part’s bandwidth. This large phase shift can
cause stability problems.
Figure 4-9 shows that the load on the output is
(RL + RISO)||(RF + RG), where RISO is before the load
(like Figure 4-7). This load needs to be large enough to
maintain stability; it should be at least 10 kΩ.
RG
RF
RISO
VOUT
RL
CL
U1
RISO
VOUT
CL
MCP6V7X
FIGURE 4-9:
Output Load.
U1
MCP6V7X
FIGURE 4-7:
Output Resistor, RISO,
Stabilizes Capacitive Loads.
Figure 4-8 gives recommended RISO values for
different capacitive loads and gains. The x-axis is the
normalized load capacitance (CL/√GN). The y-axis is
the resistance (RISO).
DS20006323B-page 20
2020 Microchip Technology Inc.
MCP6V76/6U/7/9
4.3.7
GAIN PEAKING
4.3.8
Figure 4-10 shows an op amp circuit that represents
noninverting amplifiers (VM is a DC voltage and VP is
the input) or inverting amplifiers (VP is a DC voltage
and VM is the input). The capacitances CN and CG
represent the total capacitance at the input pins; they
include the op amp’s Common Mode Input
Capacitance (CCM), board parasitic capacitance and
any capacitor placed in parallel. The capacitance CFP
represents the parasitic capacitance coupling the
output and noninverting input pins.
RN
VP
CN
CFP
Reduce undesired noise and signals with:
• Low bandwidth signal filters:
- Minimize random analog noise
- Reduce interfering signals
• Good PCB layout techniques:
- Minimize crosstalk
- Minimize parasitic capacitances and
inductances that interact with fast switching
edges
• Good power supply design:
- Isolation from other parts
- Filtering of interference on supply line(s)
4.3.9
U1
MCP6V7X
VM
RG
FIGURE 4-10:
Capacitance.
CG
RF
VOUT
Amplifier with Parasitic
REDUCING UNDESIRED NOISE
AND SIGNALS
SUPPLY BYPASSING AND
FILTERING
With this family of operational amplifiers, the power
supply pin (VDD for single supply) should have a local
bypass capacitor (i.e., 0.01 µF to 0.1 µF) within 2 mm
of the pin for good high-frequency performance.
These parts also need a bulk capacitor (i.e., 1 µF or
larger) within 100 mm to provide large, slow currents.
This bulk capacitor can be shared with other low-noise
analog parts.
CG acts in parallel with RG (except for a gain of +1 V/V),
which causes an increase in gain at high frequencies.
CG also reduces the phase margin of the feedback
loop, which becomes less stable. This effect can be
reduced by either reducing CG or RF||RG.
In some cases, high-frequency power supply noise
(e.g., switched mode power supplies) may cause
undue intermodulation distortion with a DC offset shift;
this noise needs to be filtered. Adding a resistor into the
supply connection can be helpful.
CN and RN form a low-pass filter that affects the signal
at VP. This filter has a single real pole at 1/(2πRNCN).
4.3.10
The largest value of RF that should be used depends
on noise gain (see GN in Section 4.3.5 “Capacitive
Loads”), CG and the open-loop gain’s phase shift. An
approximate limit for RF is:
EQUATION 4-2:
2
12 pF
R F 10 k -------------- G N
CG
Some applications may modify these values to reduce
either output loading or gain peaking (step response
overshoot).
At high gains, RN needs to be small in order to prevent
positive feedback and oscillations. Large CN values
can also help.
2020 Microchip Technology Inc.
PCB DESIGN FOR DC PRECISION
In order to achieve DC precision on the order of ±1 µV,
many physical errors need to be minimized. The design
of the Printed Circuit Board (PCB), the wiring and the
thermal environment have a strong impact on the
precision achieved. A poor PCB design can easily be
more than 100 times worse than the MCP6V76/6U/7/9
op amps’ minimum and maximum specifications.
4.3.10.1
PCB Layout
Any time two dissimilar metals are joined together, a
temperature dependent voltage appears across the
junction (the Seebeck or thermojunction effect). This
effect is used in thermocouples to measure
temperature. The following are examples of
thermojunctions on a PCB:
• Components (resistors, op amps, …) soldered to
a copper pad
• Wires mechanically attached to the PCB
• Jumpers
• Solder joints
• PCB vias
DS20006323B-page 21
MCP6V76/6U/7/9
Typical thermojunctions have temperature to voltage
conversion coefficients of 1 to 100 µV/°C (sometimes
higher).
4.4
Microchip’s AN1258 (“Op Amp Precision Design: PCB
Layout Techniques”) contains in-depth information on
PCB layout techniques that minimize thermojunction
effects. It also discusses other effects, such as
crosstalk, impedances, mechanical stresses and
humidity.
Many sensors are configured as Wheatstone bridges.
Strain gauges and pressure sensors are two common
examples. These signals can be small and the
Common mode noise large. Amplifier designs with high
differential gain are desirable.
4.3.10.2
Crosstalk
DC crosstalk causes offsets that appear as a larger
input offset voltage. Common causes include:
Typical Applications
4.4.1
WHEATSTONE BRIDGE
Figure 4-11 shows how to interface to a Wheatstone
bridge with a minimum of components. Because the
circuit is not symmetric, the ADC input is single-ended
and there is a minimum of filtering; the CMRR is good
enough for moderate Common mode noise.
• Common mode noise (remote sensors)
• Ground loops (current return paths)
• Power supply coupling
0.01C
VDD
R R
Interference from the mains (usually 50 Hz or 60 Hz)
and other AC sources can also affect the DC
performance. Nonlinear distortion can convert these
signals to multiple tones, including a DC shift in voltage.
When the signal is sampled by an ADC, these AC
signals can also be aliased to DC, causing an apparent
shift in offset.
FIGURE 4-11:
To reduce interference:
4.4.2
-
Keep traces and wires as short as possible
Use shielding
Use ground plane (at least a star ground)
Place the input signal source near to the DUT
Use good PCB layout techniques
Use a separate power supply filter (bypass
capacitors) for these zero-drift op amps
4.3.10.3
Miscellaneous Effects
Keep the resistances seen by the input pins as small
and as near to equal as possible to minimize biascurrent-related offsets.
Make the (trace) capacitances seen by the input pins
small and equal. This is helpful in minimizing switching
glitch-induced offset voltages.
Bending a coax cable with a radius that is too small
causes a small voltage drop to appear on the center
conductor (the triboelectric effect). Make sure the
bending radius is large enough to keep the conductors
and insulation in full contact.
Mechanical stresses can make some capacitor types
(such as some ceramics) output small voltages. Use
more appropriate capacitor types in the signal path and
minimize mechanical stresses and vibration.
Humidity can cause electrochemical potential voltages
to appear in a circuit. Proper PCB cleaning helps, as
does the use of encapsulants.
DS20006323B-page 22
0.2R
R R
1 kΩ
100R
VDD
ADC
U1
0.2R
MCP6V76
Simple Design.
RTD SENSOR
The ratiometric circuit in Figure 4-12 conditions a twowire RTD for applications with a limited temperature
range. U1 acts as a difference amplifier with a lowfrequency pole. The sensor’s wiring resistance (RW) is
corrected in firmware. Failure (open) of the RTD is
detected by an out-of-range voltage.
VDD
RT
RN
34.8 kΩ 10.0 kΩ
10 nF
RF
2.00 MΩ
RW
RRTD
100Ω
RW
U1
MCP6V76
RG
RF
10.0 kΩ 2.00 MΩ
1.00 kΩ
100 nF
RB
4.99 kΩ
1.0 µF
10 nF
VDD
ADC
FIGURE 4-12:
RTD Sensor.
2020 Microchip Technology Inc.
MCP6V76/6U/7/9
4.4.3
OFFSET VOLTAGE CORRECTION
Figure 4-13 shows MCP6V76 (U2) correcting the input
offset voltage of another op amp (U1). R2 and C2
integrate the offset error seen at U1’s input; the
integration needs to be slow enough to be stable (with
the feedback provided by R1 and R3). R4 and R5
attenuate the integrator’s output; this shifts the
integrator pole down in frequency.
R1
VIN
R3
R2
VOUT
R4
C2
U1
R5
R2
VDD/2
MCP6XXX
U2
VDD/2
MCP6V76
FIGURE 4-13:
4.4.4
Offset Correction.
PRECISION COMPARATOR
Use high gain before a comparator to improve the
latter’s performance. Do not use MCP6V76/6U/7/9 as
a comparator by itself; the VOS correction circuitry does
not operate properly without a feedback loop.
U1
VIN
MCP6V76
R1
R2
R3
R4
R5
VOUT
VDD/2
U2
MCP6541
FIGURE 4-14:
Precision Comparator.
2020 Microchip Technology Inc.
DS20006323B-page 23
MCP6V76/6U/7/9
5.0
DESIGN AIDS
Microchip provides the basic design aids needed for
the MCP6V76/6U/7/9 family of op amps.
5.1
Microchip Advanced Part Selector
(MAPS)
MAPS is a software tool that helps efficiently identify
Microchip devices that fit a particular design requirement. Available at no cost from the Microchip web site
at www.microchip.com/maps, MAPS is an overall
selection tool for Microchip’s product portfolio that
includes Analog, Memory, MCUs and DSCs. Using this
tool, a customer can define a filter to sort features for a
parametric search of devices and export side-by-side
technical comparison reports. Helpful links are also
provided for data sheets, purchase and sampling of
Microchip parts.
5.2
5.3
Application Notes
The following Microchip Application Notes are
available on the Microchip web site at www.microchip.
com/appnotes and are recommended as supplemental
reference resources.
ADN003: “Select the Right Operational Amplifier for
your Filtering Circuits”, DS21821
AN722: “Operational Amplifier Topologies and DC
Specifications”, DS00722
AN723: “Operational Amplifier AC Specifications and
Applications”, DS00723
AN884: “Driving Capacitive Loads With Op Amps”,
DS00884
AN990: “Analog Sensor Conditioning Circuits – An
Overview”, DS00990
AN1177: “Op Amp Precision Design: DC Errors”,
DS01177
Analog Demonstration and
Evaluation Boards
AN1228: “Op Amp Precision Design: Random Noise”,
DS01228
Microchip offers a broad spectrum of Analog
Demonstration and Evaluation Boards that are
designed to help customers achieve faster time to
market. For a complete listing of these boards and their
corresponding user’s guides and technical information,
visit
the
Microchip
web
site
at
www.microchip.com/analog tools.
AN1258: “Op Amp Precision Design: PCB Layout
Techniques”, DS01258
These Application Notes and others are listed in the
design guide:
“Signal Chain Design Guide”, DS21825
Some boards that are especially useful are:
• MCP6V01 Thermocouple Auto-Zeroed Reference
Design (P/N MCP6V01RD-TCPL)
• MCP6XXX Amplifier Evaluation Board 2 (P/N
DS51668)
• MCP6XXX Amplifier Evaluation Board 3 (P/N
DS51673)
• 8-Pin SOIC/MSOP/TSSOP/DIP Evaluation Board
(P/N SOIC8EV)
• 14-Pin SOIC/TSSOP/DIP Evaluation Board (P/N
SOIC14EV)
DS20006323B-page 24
2020 Microchip Technology Inc.
MCP6V76/6U/7/9
6.0
PACKAGING INFORMATION
6.1
Package Marking Information
Example:
5-Lead SC70 (MCP6V76U)
Device
MCP6V76UT-E/LTY
Code
Example:
5-Lead SOT-23 (MCP6V76, MCP6V76U)
XXXXY
WWNNN
Device
Code
MCP6V76T-E/OT
REBHY
MCP6V76UT-E/OT
REBJY
8-Lead MSOP (3x3 mm) (MCP6V77)
FV56
FVNN
REBH0
03256
Example
6V77
003256
Legend: XX...X
Y
YY
WW
NNN
e3
*
Note:
Customer-specific information
Year code (last digit of calendar year)
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code
Pb-free JEDEC® designator for Matte Tin (Sn)
This package is Pb-free. The Pb-free JEDEC designator ( e3 )
can be found on the outer packaging for this package.
In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
2020 Microchip Technology Inc.
DS20006323B-page 25
MCP6V76/6U/7/9
8-Lead TDFN (2x3x0.8 mm) (MCP6V77)
Device
MCP6V77T-E/MNY
Note:
14-Lead TSSOP (4.4 mm) (MCP6V79)
XXXXXXXX
YYWW
NNN
DS20006323B-page 26
Example
Code
DM8
Applies to 8-Lead 2x3 TDFN.
DM8
003
25
Example
6V79E/ST
2003
256
2020 Microchip Technology Inc.
MCP6V76/6U/7/9
5-Lead Plastic Small Outline Transistor (LTY) [SC70]
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
D
A
e
e
3
B
1
E1
E
2X
0.15 C
4
N
5X TIPS
0.30 C
NOTE 1
2X
0.15 C
5X b
0.10
C A B
TOP VIEW
C
c
A2
A
SEATING
PLANE
A1
L
SIDE VIEW
END VIEW
Microchip Technology Drawing C04-061-LTY Rev E Sheet 1 of 2
2020 Microchip Technology Inc.
DS20006323B-page 27
MCP6V76/6U/7/9
5-Lead Plastic Small Outline Transistor (LTY) [SC70]
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Units
Dimension Limits
N
Number of Pins
e
Pitch
Overall Height
A
Standoff
A1
Molded Package Thickness
A2
Overall Length
D
Overall Width
E
Molded Package Width
E1
b
Terminal Width
Terminal Length
L
c
Lead Thickness
MIN
0.80
0.00
0.80
0.15
0.10
0.08
MILLIMETERS
NOM
5
0.65 BSC
2.00 BSC
2.10 BSC
1.25 BSC
0.20
-
MAX
1.10
0.10
1.00
0.40
0.46
0.26
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or
protrusions shall not exceed 0.15mm per side.
3. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
Microchip Technology Drawing C04-061-LTY Rev E Sheet 2 of 2
DS20006323B-page 28
2020 Microchip Technology Inc.
MCP6V76/6U/7/9
5-Lead Plastic Small Outline Transistor (LTY) [SC70]
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
E
Gx
SILK SCREEN
3
2
1
C
G
4
5
Y
X
RECOMMENDED LAND PATTERN
Units
Dimension Limits
E
Contact Pitch
Contact Pad Spacing
C
Contact Pad Width
X
Contact Pad Length
Y
Distance Between Pads
G
Distance Between Pads
Gx
MIN
MILLIMETERS
NOM
0.65 BSC
2.20
MAX
0.45
0.95
1.25
0.20
Notes:
1. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
Microchip Technology Drawing No. C04-2061-LTY Rev E
2020 Microchip Technology Inc.
DS20006323B-page 29
MCP6V76/6U/7/9
5-Lead Plastic Small Outline Transistor (OT) [SOT23]
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
0.20 C 2X
D
e1
A
D
N
E/2
E1/2
E1
E
(DATUM D)
(DATUM A-B)
0.15 C D
2X
NOTE 1
1
2
e
B
NX b
0.20
C A-B D
TOP VIEW
A
A A2
0.20 C
SEATING PLANE
A
SEE SHEET 2
A1
C
SIDE VIEW
Microchip Technology Drawing C04-091-OT Rev F Sheet 1 of 2
DS20006323B-page 30
2020 Microchip Technology Inc.
MCP6V76/6U/7/9
5-Lead Plastic Small Outline Transistor (OT) [SOT23]
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
c
T
L
L1
VIEW A-A
SHEET 1
Units
Dimension Limits
N
Number of Pins
e
Pitch
e1
Outside lead pitch
A
Overall Height
A2
Molded Package Thickness
Standoff
A1
Overall Width
E
Molded Package Width
E1
Overall Length
D
Foot Length
L
Footprint
L1
I
Foot Angle
c
Lead Thickness
b
Lead Width
MIN
0.90
0.89
-
0.30
0°
0.08
0.20
MILLIMETERS
NOM
5
0.95 BSC
1.90 BSC
2.80 BSC
1.60 BSC
2.90 BSC
0.60 REF
-
MAX
1.45
1.30
0.15
0.60
10°
0.26
0.51
Notes:
1. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or
protrusions shall not exceed 0.25mm per side.
2. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
Microchip Technology Drawing C04-091-OT Rev F Sheet 2 of 2
2020 Microchip Technology Inc.
DS20006323B-page 31
MCP6V76/6U/7/9
5-Lead Plastic Small Outline Transistor (OT) [SOT23]
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
X
SILK SCREEN
5
Y
Z
C
G
1
2
E
GX
RECOMMENDED LAND PATTERN
Units
Dimension Limits
E
Contact Pitch
C
Contact Pad Spacing
X
Contact Pad Width (X5)
Contact Pad Length (X5)
Y
Distance Between Pads
G
Distance Between Pads
GX
Overall Width
Z
MIN
MILLIMETERS
NOM
0.95 BSC
2.80
MAX
0.60
1.10
1.70
0.35
3.90
Notes:
1. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
Microchip Technology Drawing No. C04-2091-OT Rev F
DS20006323B-page 32
2020 Microchip Technology Inc.
MCP6V76/6U/7/9
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2020 Microchip Technology Inc.
DS20006323B-page 33
MCP6V76/6U/7/9
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS20006323B-page 34
2020 Microchip Technology Inc.
MCP6V76/6U/7/9
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2020 Microchip Technology Inc.
DS20006323B-page 35
MCP6V76/6U/7/9
8-Lead Plastic Dual Flat, No Lead Package (MNY) – 2x3x0.8 mm Body [TDFN]
With 1.4x1.3 mm Exposed Pad (JEDEC Package type WDFN)
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
D
A
B
N
(DATUM A)
(DATUM B)
E
NOTE 1
2X
0.15 C
1
2
2X
0.15 C
TOP VIEW
0.10 C
C
(A3)
A
SEATING
PLANE
8X
0.08 C
A1
SIDE VIEW
0.10
C A B
D2
L
1
2
0.10
C A B
NOTE 1
E2
K
N
8X b
e
0.10
0.05
C A B
C
BOTTOM VIEW
Microchip Technology Drawing No. C04-129-MNY Rev E Sheet 1 of 2
DS20006323B-page 36
2020 Microchip Technology Inc.
MCP6V76/6U/7/9
8-Lead Plastic Dual Flat, No Lead Package (MNY) – 2x3x0.8 mm Body [TDFN]
With 1.4x1.3 mm Exposed Pad (JEDEC Package type WDFN)
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Units
Dimension Limits
N
Number of Pins
e
Pitch
A
Overall Height
A1
Standoff
Contact Thickness
A3
D
Overall Length
E
Overall Width
Exposed Pad Length
D2
Exposed Pad Width
E2
b
Contact Width
L
Contact Length
Contact-to-Exposed Pad
K
MIN
0.70
0.00
1.35
1.25
0.20
0.25
0.20
MILLIMETERS
NOM
8
0.50 BSC
0.75
0.02
0.20 REF
2.00 BSC
3.00 BSC
1.40
1.30
0.25
0.30
-
MAX
0.80
0.05
1.45
1.35
0.30
0.45
-
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. Package may have one or more exposed tie bars at ends.
3. Package is saw singulated
4. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
Microchip Technology Drawing No. C04-129-MNY Rev E Sheet 2 of 2
2020 Microchip Technology Inc.
DS20006323B-page 37
MCP6V76/6U/7/9
8-Lead Plastic Dual Flat, No Lead Package (MNY) – 2x3x0.8 mm Body [TDFN]
With 1.4x1.3 mm Exposed Pad (JEDEC Package type WDFN)
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
X2
EV
8
ØV
C
Y2
EV
Y1
1
2
SILK SCREEN
X1
E
RECOMMENDED LAND PATTERN
Units
Dimension Limits
E
Contact Pitch
Optional Center Pad Width
X2
Optional Center Pad Length
Y2
Contact Pad Spacing
C
Contact Pad Width (X8)
X1
Contact Pad Length (X8)
Y1
Thermal Via Diameter
V
Thermal Via Pitch
EV
MIN
MILLIMETERS
NOM
0.50 BSC
MAX
1.60
1.50
2.90
0.25
0.85
0.30
1.00
Notes:
1. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
2. For best soldering results, thermal vias, if used, should be filled or tented to avoid solder loss during
reflow process
Microchip Technology Drawing No. C04-129-MNY Rev. B
DS20006323B-page 38
2020 Microchip Technology Inc.
MCP6V76/6U/7/9
14Lead Thin Shrink Small Outline Package [ST] 4.4 mm Body [TSSOP]
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
D
A
B
N
E
2
E1
2
E1
E
1
2X 7 TIPS
0.20 C B A
2
e
TOP VIEW
A
C
A2 A
SEATING
PLANE
14X
0.10 C
14X b
0.10
A1
A
C B A
SIDE VIEW
SEE DETAIL B
VIEW A–A
Microchip Technology Drawing C04-087 Rev D Sheet 1 of 2
2020 Microchip Technology Inc.
DS20006323B-page 39
MCP6V76/6U/7/9
14Lead Thin Shrink Small Outline Package [ST] 4.4 mm Body [TSSOP]
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
(ș2)
R1
H
R2
c
L
ș1
(L1)
(ș3)
DETAIL B
Number of Terminals
Pitch
Overall Height
Standoff
Molded Package Thickness
Overall Length
Overall Width
Molded Package Width
Terminal Width
Terminal Thickness
Terminal Length
Footprint
Lead Bend Radius
Lead Bend Radius
Foot Angle
Mold Draft Angle
Mold Draft Angle
Notes:
Units
Dimension Limits
N
e
A
A1
A2
D
E
E1
b
c
L
L1
R1
R2
ș1
ș2
ș3
MIN
–
0.05
0.80
4.90
4.30
0.19
0.09
0.45
0.09
0.09
0°
–
–
MILLIMETERS
NOM
14
0.65 BSC
–
–
1.00
5.00
6.40 BSC
4.40
–
–
0.60
1.00 REF
–
–
–
12° REF
12° REF
MAX
1.20
0.15
1.05
5.10
4.50
0.30
0.20
0.75
–
–
8°
–
–
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
Microchip Technology Drawing C04-087 Rev D Sheet 2 of 2
DS20006323B-page 40
2020 Microchip Technology Inc.
MCP6V76/6U/7/9
14Lead Thin Shrink Small Outline Package [ST] 4.4 mm Body [TSSOP]
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
G
SILK SCREEN
C
Y
X
E
RECOMMENDED LAND PATTERN
Units
Dimension Limits
Contact Pitch
E
Contact Pad Spacing
C
Contact Pad Width (Xnn)
X
Contact Pad Length (Xnn)
Y
Contact Pad to Contact Pad (Xnn)
G
MIN
MILLIMETERS
NOM
0.65 BSC
5.90
MAX
0.45
1.45
0.20
Notes:
1. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
Microchip Technology Drawing C04-2087 Rev D
2020 Microchip Technology Inc.
DS20006323B-page 41
MCP6V76/6U/7/9
NOTES:
DS20006323B-page 42
2020 Microchip Technology Inc.
MCP6V76/6U/7/9
APPENDIX A:
REVISION HISTORY
Revision B (April 2020)
• Updated Section 6.1 “Package Marking
Information” for 5-Lead SOT-23.
Revision A (March 2020)
• Original release of this document.
2020 Microchip Technology Inc.
DS20006323B-page 43
MCP6V76/6U/7/9
NOTES:
DS20006323B-page 44
2020 Microchip Technology Inc.
MCP6V76/6U/7/9
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
PART NO.
[X](1)
–X
Device Tape and Reel Temperature
Range
Device:
/XX
Package
MCP6V76T:
Single Op Amp (Tape and Reel)
(SOT-23 only)
MCP6V76UT: Single Op Amp (Tape and Reel)
(SC-70, SOT-23)
MCP6V77:
Dual Op Amp (MSOP, 2x3 TDFN)
MCP6V77T: Dual Op Amp (Tape and Reel) (MSOP,
2x3 TDFN)
MCP6V79:
Quad Op Amp (TSSOP)
MCP6V79T: Quad Op Amp (Tape and Reel) (TSSOP)
Temperature Range:
E
Package:
LTY* = Plastic Small Outline Transistor, 5-lead SC70
OT
= Plastic Small Outline Transistor, 5-lead SOT-23
MNY* = Plastic Dual Flat, No-Lead - 2×3×0.8 mm Body,
8-lead
MS
= Plastic Micro Small Outline, 8-lead
ST
= Plastic Thin Shrink Small Outline - 4.4 mm Body,
14-lead
*Y
= -40°C to +125°C (Extended)
= Nickel palladium gold manufacturing designator.
Only available on the SC70 and TDFN packages.
2020 Microchip Technology Inc.
Examples:
a)
MCP6V76T-E/OT:
a)
MCP6V76UT-E/LTY: Tape and Reel,
Extended temperature,
5LD SC70 package
MCP6V76UT-E/OT: Tape and Reel,
Extended temperature,
5LD SOT-23 package
b)
a)
b)
c)
Tape and Reel,
Extended temperature,
5LD SOT-23 package
MCP6V77-E/MS:
Extended temperature,
8LD MSOP package
MCP6V77T-E/MS: Tape and Reel,
Extended temperature,
8LD MSOP package
MCP6V77T-E/MNY: Tape and Reel,
Extended temperature,
8LD 2x3 TDFN package
a)
MCP6V79-E/ST:
b)
MCP6V79T-E/ST:
Note 1:
Extended temperature,
14LD TSSOP package
Tape and Reel,
Extended temperature,
14LD TSSOP package
Tape and Reel identifier only appears in the
catalog part number description. This
identifier is used for ordering purposes and
is not printed on the device package. Check
with your Microchip Sales Office for package
availability with the Tape and Reel option.
DS20006323B-page 45
MCP6V76/6U/7/9
NOTES:
DS20006323B-page 46
2020 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
•
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights unless otherwise stated.
Trademarks
The Microchip name and logo, the Microchip logo, Adaptec,
AnyRate, AVR, AVR logo, AVR Freaks, BesTime, BitCloud, chipKIT,
chipKIT logo, CryptoMemory, CryptoRF, dsPIC, FlashFlex,
flexPWR, HELDO, IGLOO, JukeBlox, KeeLoq, Kleer, LANCheck,
LinkMD, maXStylus, maXTouch, MediaLB, megaAVR, Microsemi,
Microsemi logo, MOST, MOST logo, MPLAB, OptoLyzer,
PackeTime, PIC, picoPower, PICSTART, PIC32 logo, PolarFire,
Prochip Designer, QTouch, SAM-BA, SenGenuity, SpyNIC, SST,
SST Logo, SuperFlash, Symmetricom, SyncServer, Tachyon,
TempTrackr, TimeSource, tinyAVR, UNI/O, Vectron, and XMEGA
are registered trademarks of Microchip Technology Incorporated in
the U.S.A. and other countries.
APT, ClockWorks, The Embedded Control Solutions Company,
EtherSynch, FlashTec, Hyper Speed Control, HyperLight Load,
IntelliMOS, Libero, motorBench, mTouch, Powermite 3, Precision
Edge, ProASIC, ProASIC Plus, ProASIC Plus logo, Quiet-Wire,
SmartFusion, SyncWorld, Temux, TimeCesium, TimeHub,
TimePictra, TimeProvider, Vite, WinPath, and ZL are registered
trademarks of Microchip Technology Incorporated in the U.S.A.
Adjacent Key Suppression, AKS, Analog-for-the-Digital Age, Any
Capacitor, AnyIn, AnyOut, BlueSky, BodyCom, CodeGuard,
CryptoAuthentication, CryptoAutomotive, CryptoCompanion,
CryptoController, dsPICDEM, dsPICDEM.net, Dynamic Average
Matching, DAM, ECAN, EtherGREEN, In-Circuit Serial
Programming, ICSP, INICnet, Inter-Chip Connectivity, JitterBlocker,
KleerNet, KleerNet logo, memBrain, Mindi, MiWi, MPASM, MPF,
MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach,
Omniscient Code Generation, PICDEM, PICDEM.net, PICkit,
PICtail, PowerSmart, PureSilicon, QMatrix, REAL ICE, Ripple
Blocker, SAM-ICE, Serial Quad I/O, SMART-I.S., SQI,
SuperSwitcher, SuperSwitcher II, Total Endurance, TSHARC,
USBCheck, VariSense, ViewSpan, WiperLock, Wireless DNA, and
ZENA are trademarks of Microchip Technology Incorporated in the
U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated in
the U.S.A.
The Adaptec logo, Frequency on Demand, Silicon Storage
Technology, and Symmcom are registered trademarks of Microchip
Technology Inc. in other countries.
GestIC is a registered trademark of Microchip Technology Germany
II GmbH & Co. KG, a subsidiary of Microchip Technology Inc., in
other countries.
All other trademarks mentioned herein are property of their
respective companies.
© 2020, Microchip Technology Incorporated, All Rights Reserved.
For information regarding Microchip’s Quality Management Systems,
please visit www.microchip.com/quality.
2020 Microchip Technology Inc.
ISBN: 978-1-5224-5930-9
DS20006323B-page 47
Worldwide Sales and Service
AMERICAS
ASIA/PACIFIC
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Corporate Office
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Technical Support:
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DS20006323B-page 48
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2020 Microchip Technology Inc.
02/28/20
