MCP7940N
Battery-Backed I2C Real-Time Clock/Calendar with SRAM
Timekeeping Features
General Description
• Real-Time Clock/Calendar (RTCC):
- Hours, Minutes, Seconds, Day of Week, Day,
Month, Year
- Leap year compensated to 2399
- 12/24 hour modes
• Oscillator for 32.768 kHz Crystals:
- Optimized for 6-9 pF crystals
• On-Chip Digital Trimming/Calibration:
- ±1 PPM resolution
- ±129 PPM range
• Dual Programmable Alarms
• Versatile Output Pin:
- Clock output with selectable frequency
- Alarm output
- General purpose output
• Power-Fail Time-Stamp:
- Time logged on switchover to and from
Battery mode
The MCP7940N Real-Time Clock/Calendar (RTCC)
tracks time using internal counters for hours, minutes,
seconds, days, months, years, and day of week.
Alarms can be configured on all counters up to and
including months. For usage and configuration, the
MCP7940N supports I2C communications up to
400 kHz.
Low-Power Features
• Wide Voltage Range:
- Operating voltage range of 1.8V to 5.5V
- Backup voltage range of 1.3V to 5.5V
• Low Typical Timekeeping Current:
- Operating from VCC: 1.2 µA at 3.3V
- Operating from battery backup: 925 nA at
3.0V
• Automatic Switchover to Battery Backup
User Memory
The open-drain, multi-functional output can be
configured to assert on an alarm match, to output a
selectable frequency square wave, or as a general
purpose output.
The MCP7940N is designed to operate using a
32.768 kHz tuning fork crystal with external crystal
load capacitors. On-chip digital trimming can be used
to adjust for frequency variance caused by crystal
tolerance and temperature.
SRAM and timekeeping circuitry are powered from the
back-up supply when main power is lost, allowing the
device to maintain accurate time and the SRAM
contents. The times when the device switches over to
the back-up supply and when primary power returns
are both logged by the power-fail time-stamp.
Package Types
MSOP, PDIP (1) , SOIC, TSSOP (1)
TDFN
(1)
X1
1
8
VCC
X2
2
7
MFP
X2 2
7 MFP
VBAT 3
6 SCL
VSS 4
5 SDA
VBAT
3
6
SCL
VSS
4
5
SDA
X1 1
8 VCC
• 64-byte Battery-Backed SRAM
Operating Ranges
• Two-Wire Serial Interface, I2C Compatible
- I2C clock rate up to 400 kHz
• Temperature Range:
- Industrial (I): -40°C to +85°C
- Extended (E): -40°C to +125°C
• Automotive AEC-Q100 Qualified
Note 1:
Available in I-temp only.
Packages
• 8-Lead MSOP, 8-Lead PDIP, 8-Lead SOIC,
8-Lead 2x3 TDFN and 8-Lead TSSOP
2011-2022 Microchip Technology Inc. and its subsidiares
DS20005010J-page 1
MCP7940N
FIGURE 1-1:
TYPICAL APPLICATION SCHEMATIC
VCC
VCC
VCC
8
VCC
6
PIC®
MCU
5
7
SCL
MCP7940N
2
SDA
X2
VBAT
MFP
VCC
VSS
VBAT
SCL
SDA
CX2
3
VBAT
VSS
4
FIGURE 1-2:
CX1
1
32.768 KHZ
X1
BLOCK DIAGRAM
Power Control
and Switchover
Power-Fail
Time-Stamp
Control Logic
I2C Interface
and Addressing
Configuration
Seconds
SRAM
Minutes
X1
32.768 kHz
Oscillator
Hours
Clock Divider
X2
Day of Week
Digital Trimming
Square Wave
Output
Date
Alarms
Month
Year
MFP
DS20005010J-page 2
Output Logic
2011-2022 Microchip Technology Inc. and its subsidiares
MCP7940N
1.0
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings (†)
VCC.............................................................................................................................................................................6.5V
All inputs and outputs (except SDA and SCL) w.r.t. VSS .....................................................................-0.6V to VCC +1.0V
SDA and SCL w.r.t. VSS ............................................................................................................................... -0.6V to 6.5V
Storage temperature ............................................................................................................................... -65°C to +150°C
Ambient temperature with power applied................................................................................................ -40°C to +125°C
ESD protection on all pins 4 kV
† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions above those
indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability.
TABLE 1-1:
DC CHARACTERISTICS
VCC = +1.8V to 5.5V
VCC = +1.8V to 5.5V
DC CHARACTERISTICS
Industrial (I):
Extended (E):
Param.
Symbol
No.
Minimum Typical(1) Maximum Units
D1
VIH
Characteristic
High-Level Input Voltage
TA = -40°C to +85°C
TA = -40°C to +125°C
Conditions
0.7 VCC
—
—
V
—
—
0.3 VCC
V
VCC 2.5V
—
—
0.2 VCC
V
VCC < 2.5V
0.05 VCC
—
—
V
Note 2
D2
VIL
Low-Level Input Voltage
D3
VHYS
Hysteresis of Schmitt
Trigger Inputs
(SDA, SCL pins)
D4
VOL
Low-Level Output Voltage
(MFP, SDA pins)
—
—
0.40
V
IOL = 3.0 mA @
VCC = 4.5V
IOL = 2.1 mA @
VCC = 2.5V
D5
ILI
Input Leakage Current
—
—
±1
µA
VIN = VSS or VCC
D6
ILO
Output Leakage Current
—
—
±1
µA
VOUT = VSS or VCC
D7
CIN,
COUT
Pin Capacitance
(SDA, SCL, MFP pins)
—
—
10
pF
VCC = 5.0V (Note 2)
TA = +25°C, f = 1 MHz
D8
COSC
Oscillator Pin
Capacitance (X1, X2 pins)
—
3
—
pF
Note 2
—
—
300
µA
VCC = 5.5V,
SCL = 400 kHz
—
—
400
µA
VCC = 5.5V,
SCL = 400 kHz
—
—
1
µA
SCL, SDA, VCC = 5.5V
(I-Temp)
—
—
5
µA
SCL, SDA, VCC = 5.5V
(E-temp)
VCC = 3.3V (Note 2)
ICCREAD
D9
ICCWRITE
D10
D11
ICCDAT
SRAM/RTCC Register
Operating Current
VCC Data-Retention
Current (oscillator off)
ICCT
Timekeeping Current
—
1.2
—
µA
D12
VTRIP
Power-fail Switchover
Voltage
1.3
1.5
1.7
V
D13
VBAT
Backup Supply Voltage
Range
1.3
—
5.5
V
Note 1:
2:
Note 2
Typical measurements taken at room temperature.
This parameter is not tested but ensured by characterization.
2011-2022 Microchip Technology Inc. and its subsidiares
DS20005010J-page 3
MCP7940N
VCC = +1.8V to 5.5V
VCC = +1.8V to 5.5V
DC CHARACTERISTICS (Continued)
Industrial (I):
Extended (E):
Param.
Symbol
No.
Minimum Typical(1) Maximum Units
D14
IBATT
Characteristic
Timekeeping Backup
Current
Note 1:
2:
IBATDAT
VBAT Data Retention
Current (oscillator off)
Conditions
—
—
850
nA
VBAT = 1.3V, VCC = VSS
(Note 2)
—
925
1200
nA
VBAT = 3.0V, VCC = VSS
(Note 2)
9000
nA
VBAT = 5.5V, VCC = VSS
(Note 2)
750
nA
VBAT = 3.6V, VCC = VSS
—
D15
TA = -40°C to +85°C
TA = -40°C to +125°C
—
—
Typical measurements taken at room temperature.
This parameter is not tested but ensured by characterization.
DS20005010J-page 4
2011-2022 Microchip Technology Inc. and its subsidiares
MCP7940N
TABLE 1-2:
AC CHARACTERISTICS
Industrial (I): VCC = +1.8V to 5.5V TA = -40°C to +85°C
Extended (E): VCC = +1.8V to 5.5V TA = -40°C to +125°C
AC CHARACTERISTICS
Param.
Symbol
No.
1
2
3
4
5
6
FCLK
THIGH
TLOW
TR
TF
Characteristic
Minimum Typical Maximum Units
Clock Frequency
Clock High Time
Clock Low Time
—
100
kHz
1.8V VCC < 2.5V
—
—
400
kHz
2.5V VCC 5.5V
4000
—
—
ns
1.8V VCC < 2.5V
600
—
—
ns
2.5V VCC 5.5V
4700
—
—
ns
1.8V VCC < 2.5V
1300
—
—
ns
2.5V VCC 5.5V
—
—
1000
ns
1.8V VCC < 2.5V
(Note 1)
—
—
300
ns
2.5V VCC 5.5V
(Note 1)
—
—
1000
ns
1.8V VCC < 2.5V
(Note 1)
—
—
300
ns
2.5V VCC 5.5V
(Note 1)
4000
—
—
ns
1.8V VCC < 2.5V
SDA and SCL Fall Time
600
—
—
ns
2.5V VCC 5.5V
4700
—
—
ns
1.8V VCC < 2.5V
600
—
—
ns
2.5V VCC 5.5V
0
—
—
ns
Note 2
7
TSU:STA Start Condition Setup Time
8
THD:DAT Data Input Hold Time
9
TSU:DAT Data Input Setup Time
10
TSU:STO Stop Condition Setup Time
11
TAA
Output Valid From Clock
12
TBUF
Bus free time: Time the bus
must be free before a new
transmission can start
13
TSP
Input Filter Spike Suppression
(SDA and SCL pins)
14
TFVCC
VCC fall time
15
TRVCC
VCC rise time
16
FOSC
Oscillator frequency
17
TOSF
Oscillator timeout period
1
Note 1:
2:
—
SDA and SCL Rise Time
THD:STA Start Condition Hold Time
Conditions
250
—
—
ns
1.8V VCC < 2.5V
100
—
—
ns
2.5V VCC 5.5V
4000
—
—
ns
1.8V VCC < 2.5V
600
—
—
ns
2.5V VCC 5.5V
—
—
3500
ns
1.8V VCC < 2.5V
—
—
900
ns
2.5V VCC 5.5V
4700
—
—
ns
1.8V VCC < 2.5V
1300
—
—
ns
2.5V VCC 5.5V
—
—
50
ns
Note 1
300
—
—
s
Note 1
0
—
—
s
Note 1
—
32.768
—
kHz
—
—
ms
Note 1
Not 100% tested.
As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region
(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions.
2011-2022 Microchip Technology Inc. and its subsidiares
DS20005010J-page 5
MCP7940N
I2C BUS TIMING DATA
FIGURE 1-3:
5
SCL
7
SDA
In
D3
2
3
8
9
4
10
6
13
12
11
SDA
Out
FIGURE 1-4:
POWER SUPPLY TRANSITION TIMING
VCC
VTRIP(MAX)
VTRIP(MIN)
14
DS20005010J-page 6
15
2011-2022 Microchip Technology Inc. and its subsidiares
MCP7940N
2.0
TYPICAL PERFORMANCE CURVE
Note:
The graphs and tables provided following this note are a statistical summary based on a limited number of
samples and are provided for informational purposes only. The performance characteristics listed herein
are not tested or guaranteed. In some graphs or tables, the data represented may be outside the specified
operating range (e.g., outside specified power supply range) and therefore, outside the warranted range.
IBATT Current (μA)
FIGURE 2-1:
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
1.30
TIMEKEEPING BACKUP
CURRENT VS. BACKUP
SUPPLY VOLTAGE
TA = -40°C
TA = 25°C
TA = 85°C
Ͳ40
25
85
1.90
2.50 3.10 3.70 4.30
VBAT Voltage (V)
4.90
5.50
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DS20005010J-page 7
MCP7940N
3.0
PIN DESCRIPTIONS
The descriptions of the pins are listed in Table 3-1.
TABLE 3-1:
Name
X1
X2
VBAT
Vss
SDA
SCL
MFP
Vcc
Note:
3.1
PIN FUNCTION TABLE
MSOP
PDIP
SOIC
TDFN
Serial Data (SDA)
This is a bidirectional pin used to transfer addresses
and data into and out of the device. It is an open-drain
terminal. Therefore, the SDA bus requires a pull-up
resistor to VCC (typically 10 k for 100 kHz, 2 k for
400 kHz). For normal data transfer, SDA is allowed to
change only during SCL low. Changes during SCL high
are reserved for indicating the Start and Stop
conditions.
3.2
TSSOP
Function
1
1
1
1
1
Quartz Crystal Input, External Oscillator Input
2
2
2
2
2
Quartz Crystal Output
3
3
3
3
3
Battery Backup Supply Input
4
4
4
4
4
Ground
5
5
5
5
5
Bidirectional Serial Data (I2C)
6
6
6
6
6
Serial Clock (I2C)
7
7
7
7
7
Multifunction Pin
8
8
8
8
8
Primary Power Supply
Exposed pad on TFDN can be connected to Vss or left floating.
3.5
Backup Supply (VBAT)
This is the input for a backup supply to maintain the
RTCC and SRAM registers during the time when VCC
is unavailable.
If the battery backup feature is not being used, the
VBAT pin should be connected to VSS.
Serial Clock (SCL)
This input is used to synchronize the data transfer to
and from the device.
3.3
Oscillator Input/Output (X1, X2)
These pins are used as the connections for an external
32.768 kHz quartz crystal and load capacitors. X1 is
the crystal oscillator input and X2 is the output. The
MCP7940N is designed to allow for the use of external
load capacitors in order to provide additional flexibility
when choosing external crystals. The MCP7940N is
optimized for crystals with a specified load capacitance
of 6-9 pF.
X1 also serves as the external clock input when the
MCP7940N is configured to use an external oscillator.
3.4
Multifunction Pin (MFP)
This is an output pin used for the alarm and square
wave output functions. It can also serve as a general
purpose output pin by controlling the OUT bit in the
CONTROL register.
The MFP is an open-drain output and requires a pull-up
resistor to Vcc (typically 10 k). This pin may be left
floating if not used.
DS20005010J-page 8
2011-2022 Microchip Technology Inc. and its subsidiares
MCP7940N
4.0
I2C BUS CHARACTERISTICS
4.1.1.3
4.1
I2C Interface
A low-to-high transition of the SDA line while the clock
(SCL) is high determines a Stop condition. All
operations must end with a Stop condition.
The MCP7940N supports a bidirectional two-wire bus
and data transmission protocol. A device that sends
data onto the bus is defined as transmitter, and a
device receiving data as receiver. The bus has to be
controlled by a host device which generates the Start
and Stop conditions, while the MCP7940N works as client. Both host and client can operate as transmitter or
receiver but the host device determines which mode is
activated.
4.1.1
BUS CHARACTERISTICS
The following bus protocol has been defined:
• Data transfer may be initiated only when the bus
is not busy.
• During data transfer, the data line must remain
stable whenever the clock line is high. Changes in
the data line while the clock line is high will be
interpreted as a Start or Stop condition.
Accordingly, the following bus conditions have been
defined (Figure 4-1).
4.1.1.1
Both data and clock lines remain high.
Start Data Transfer (B)
A high-to-low transition of the SDA line while the clock
(SCL) is high determines a Start condition. All
commands must be preceded by a Start condition.
FIGURE 4-1:
(A)
Data Valid (D)
The state of the data line represents valid data when,
after a Start condition, the data line is stable for the
duration of the high period of the clock signal.
The data on the line must be changed during the low
period of the clock signal. There is one bit of data per
clock pulse.
Each data transfer is initiated with a Start condition and
terminated with a Stop condition. The number of the
data bytes transferred between the Start and Stop
conditions is determined by the host device.
4.1.1.5
Acknowledge
Each receiving device, when addressed, is obliged to
generate an Acknowledge signal after the reception of
each byte. The host device must generate an extra
clock pulse which is associated with this Acknowledge
bit.
Note:
Bus Not Busy (A)
4.1.1.2
4.1.1.4
Stop Data Transfer (C)
The I2C interface is disabled while operating from the backup power supply.
A device that acknowledges must pull down the SDA
line during the Acknowledge clock pulse in such a way
that the SDA line is stable-low during the high period of
the Acknowledge-related clock pulse. Of course, setup
and hold times must be taken into account. During
reads, a host must signal an end of data to the client by
NOT generating an Acknowledge bit on the last byte
that has been clocked out of the client. In this case, the
client (MCP7940N) will leave the data line high to
enable the host to generate the Stop condition.
DATA TRANSFER SEQUENCE ON THE SERIAL BUS
(B)
(D)
Start
Condition
Address or
Acknowledge
Valid
(D)
(C)
(A)
SCL
SDA
2011-2022 Microchip Technology Inc. and its subsidiares
Data
Allowed
to Change
Stop
Condition
DS20005010J-page 9
MCP7940N
FIGURE 4-2:
ACKNOWLEDGE TIMING
Acknowledge
Bit
SCL
1
SDA
2
3
4
5
6
7
8
9
1
DEVICE ADDRESSING
The control byte is the first byte received following the
Start condition from the host device (Figure 4-3). The
control byte begins with a 4-bit control code. For the
MCP7940N, this is set ‘1101’ for register read and
write operations. The next three bits are non-configurable Chip Select bits that must always be set to ‘1’.
The last bit of the control byte defines the operation to
be performed. When set to a ‘1’ a read operation is
selected, and when set to a ‘0’ a write operation is
selected.
3
Data from transmitter
Data from transmitter
Receiver must release the SDA line at this point
so the Transmitter can continue sending data.
Transmitter must release the SDA line at this point
allowing the Receiver to pull the SDA line low to
acknowledge the previous eight bits of data.
4.1.2
2
FIGURE 4-3:
CONTROL BYTE FORMAT
Acknowledge Bit
Read/Write Bit
Start Bit
Chip Select
Bits
Control Code
S
1
1
0
1
1
1
1 R/W ACK
RTCC Register/SRAM Control Byte
The combination of the 4-bit control code and the three
Chip Select bits is called the client address. Upon
receiving a valid client address, the client device outputs an acknowledge signal on the SDA line. Depending on the state of the R/W bit, the MCP7940N will
select a read or a write operation.
DS20005010J-page 10
2011-2022 Microchip Technology Inc. and its subsidiares
MCP7940N
5.0
FUNCTIONAL DESCRIPTION
5.1
The MCP7940N is a highly-integrated Real-Time
Clock/Calendar (RTCC). Using an on-board,
low-power oscillator, the current time is maintained in
seconds, minutes, hours, day of week, date, month,
and year. The MCP7940N also features 64 bytes of
general purpose SRAM. Two alarm modules allow
interrupts to be generated at specific times with flexible
comparison options. Digital trimming can be used to
compensate for inaccuracies inherent with crystals.
Using the backup supply input and an integrated power
switch, the MCP7940N will automatically switch to
backup power when primary power is unavailable,
allowing the current time and the SRAM contents to be
maintained. The time-stamp module captures the time
when primary power is lost and when it is restored.
Memory Organization
The MCP7940N features two different blocks of memory: the RTCC registers and general purpose SRAM
(Figure 5-1). They share the same address space,
accessed through the ‘1101111X’ control byte.
Unused locations are not accessible. The MCP7940N
will not acknowledge if the address is out of range, as
shown in the shaded region of the memory map in
Figure 5-1.
The RTCC registers are contained in addresses
0x00-0x1F. Table 5-1 shows the detailed RTCC register map. There are 64 bytes of user-accessible SRAM,
located in the address range 0x20-0x5F. The SRAM is
a separate block from the RTCC registers. All RTCC
registers and SRAM locations are maintained while
operating from backup power.
The RTCC configuration and Status registers are used
to access all of the modules featured on the
MCP7940N.
FIGURE 5-1:
MEMORY MAP
RTCC Registers/SRAM
0x00
Time and Date
0x06
0x07
0x09
0x0A
Configuration and Trimming
Alarm 0
0x10
0x11
Alarm 1
0x17
0x18
Power-Fail/Power-Up Time-Stamps
0x1F
0x20
SRAM (64 Bytes)
0x5F
0x60
Unimplemented; device does not ACK
0xFF
I2C Address: 1101111x
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DS20005010J-page 11
MCP7940N
TABLE 5-1:
DETAILED RTCC REGISTER MAP
Addr. Register Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Section 5.3 “Timekeeping”
00h
RTCSEC
ST
SECTEN2
SECTEN1
SECTEN0
SECONE3
SECONE2
SECONE1
SECONE0
01h
RTCMIN
—
MINTEN2
MINTEN1
MINTEN0
MINONE3
MINONE2
MINONE1
MINONE0
02h
RTCHOUR
—
12/24
AM/PM
HRTEN1
HRTEN0
HRONE3
HRONE2
HRONE1
HRONE0
03h
RTCWKDAY
—
—
OSCRUN
PWRFAIL
VBATEN
WKDAY2
WKDAY1
WKDAY0
04h
RTCDATE
—
—
DATETEN1
DATETEN0
DATEONE3 DATEONE2 DATEONE1 DATEONE0
05h
RTCMTH
—
—
LPYR
MTHTEN0
MTHONE3
MTHONE2
MTHONE1
06h
RTCYEAR
YRTEN3
YRTEN2
YRTEN1
YRTEN0
YRONE3
YRONE2
YRONE1
MTHONE0
YRONE0
07h
CONTROL
OUT
SQWEN
ALM1EN
ALM0EN
EXTOSC
CRSTRIM
SQWFS1
SQWFS0
SIGN
TRIMVAL6
TRIMVAL5
TRIMVAL4
TRIMVAL3
TRIMVAL2
TRIMVAL1
TRIMVAL0
08h
OSCTRIM
09h
Reserved
0Ah
ALM0SEC
—
SECTEN2
SECTEN1
SECTEN0
SECONE3
SECONE2
SECONE1
SECONE0
0Bh
ALM0MIN
—
MINTEN2
MINTEN1
MINTEN0
MINONE3
MINONE2
MINONE1
MINONE0
0Ch
ALM0HOUR
—
12/24(2)
AM/PM
HRTEN1
HRTEN0
HRONE3
HRONE2
HRONE1
HRONE0
ALM0IF
WKDAY2
WKDAY1
WKDAY0
Reserved – Do not use
Section 5.4 “Alarms”
0Dh
ALM0WKDAY
0Eh
ALM0DATE
ALMPOL
ALM0MSK2 ALM0MSK1 ALM0MSK0
—
—
DATETEN1
DATETEN0
DATEONE3 DATEONE2 DATEONE1 DATEONE0
—
—
—
MTHTEN0
MTHONE3
MTHONE2
MTHONE1
MTHONE0
0Fh
ALM0MTH
10h
Reserved
11h
ALM1SEC
—
SECTEN2
SECTEN1
SECTEN0
SECONE3
SECONE2
SECONE1
SECONE0
12h
ALM1MIN
—
MINTEN2
MINTEN1
MINTEN0
MINONE3
MINONE2
MINONE1
MINONE0
13h
ALM1HOUR
—
12/24(2)
AM/PM
HRTEN1
HRTEN0
HRONE3
HRONE2
HRONE1
HRONE0
ALM1IF
WKDAY2
WKDAY1
WKDAY0
Reserved – Do not use
Section 5.4 “Alarms”
14h
ALM1WKDAY
15h
ALM1DATE
ALMPOL(3)
ALM1MSK2 ALM1MSK1 ALM1MSK0
—
—
DATETEN1
DATETEN0
DATEONE3 DATEONE2 DATEONE1 DATEONE0
—
—
—
MTHTEN0
MTHONE3
16h
ALM1MTH
17h
Reserved
MTHONE2
MTHONE1
MTHONE0
18h
PWRDNMIN
—
MINTEN2
MINTEN1
MINTEN0
19h
PWRDNHOUR
—
12/24
AM/PM
HRTEN1
HRTEN0
MINONE3
MINONE2
MINONE1
MINONE0
HRONE3
HRONE2
HRONE1
HRONE0
1Ah
PWRDNDATE
—
—
DATETEN1
DATETEN0
DATEONE3 DATEONE2 DATEONE1 DATEONE0
1Bh
PWRDNMTH
WKDAY2
WKDAY1
WKDAY0
MTHTEN0
MTHONE3
Reserved – Do not use
Section 5.7.1 “Power-Fail Time-Stamp”
MTHONE2
MTHONE1
MTHONE0
Section 5.7.1 “Power-Fail Time-Stamp”
1Ch
PWRUPMIN
—
MINTEN2
MINTEN1
MINTEN0
MINONE3
MINONE2
MINONE1
MINONE0
1Dh
PWRUPHOUR
—
12/24
AM/PM
HRTEN1
HRTEN0
HRONE3
HRONE2
HRONE1
HRONE0
1Eh
PWRUPDATE
—
—
DATETEN1
DATETEN0
DATEONE3 DATEONE2 DATEONE1 DATEONE0
1Fh
PWRUPMTH
WKDAY2
WKDAY1
WKDAY0
MTHTEN0
MTHONE3
Note 1:
2:
3:
MTHONE2
MTHONE1
MTHONE0
Grey areas are unimplemented.
The 12/24 bits in the ALMxHOUR registers are read-only and reflect the value of the 12/24 bit in the
RTCHOUR register.
The ALMPOL bit in the ALM1WKDAY register is read-only and reflects the value of the ALMPOL bit in the
ALM0WKDAY register.
DS20005010J-page 12
2011-2022 Microchip Technology Inc. and its subsidiares
MCP7940N
5.2
Oscillator Configuration
EQUATION 5-1:
The MCP7940N can be operated in two different oscillator configurations: using an external crystal or using
an external clock input.
5.2.1
Figure 5-2 shows the pin connections when using an
external crystal.
FIGURE 5-2:
CRYSTAL OPERATION
MCP7940N
X1
CX1
To Internal
Logic
Quartz
Crystal
CX 2
ST
X2
Note 1: The ST bit must be set to enable the
crystal oscillator circuit.
2: Always verify oscillator performance over
the voltage and temperature range that is
expected for the application.
5.2.1.1
Choosing Load Capacitors
CL is the effective load capacitance as seen by the
crystal, and includes the physical load capacitors, pin
capacitance, and stray board capacitance. Equation 5-1
can be used to calculate CL.
CX1 and CX2 are the external load capacitors. They
must be chosen to match the selected crystal’s
specified load capacitance.
Note:
C X1 C X2
- + C STRAY
C L = ------------------------C X1 + C X2
EXTERNAL CRYSTAL
The crystal oscillator circuit on the MCP7940N is
designed to operate with a standard 32.768 kHz tuning
fork crystal and matching external load capacitors. By
using external load capacitors, the MCP7940N allows
for a wide selection of crystals. Suitable crystals have a
load capacitance (CL) of 6-9 pF. Crystals with a load
capacitance of 12.5 pF are not recommended.
LOAD CAPACITANCE
CALCULATION
Where:
C L = Effective load capacitance
C X1 = Capacitor value on X1 + C OSC
C X2 = Capacitor value on X2 + C OSC
C STRAY = PCB stray capacitance
5.2.1.2
Layout Considerations
The oscillator circuit should be placed on the same
side of the board as the device. Place the oscillator
circuit close to the respective oscillator pins. The load
capacitors should be placed next to the oscillator
itself, on the same side of the board.
Use a grounded copper pour around the oscillator
circuit to isolate it from surrounding circuits. The
grounded copper pour should be routed directly to VSS.
Do not run any signal traces or power traces inside the
ground pour. Also, if using a two-sided board, avoid any
traces on the other side of the board where the crystal
is placed.
Layout suggestions are shown in Figure 5-3. In-line
packages may be handled with a single-sided layout
that completely encompasses the oscillator pins. With
fine-pitch packages, it is not always possible to completely surround the pins and components. A suitable
solution is to tie the broken guard sections to a mirrored
ground layer. In all cases, the guard trace(s) must be
returned to ground.
For additional information and design guidance on
oscillator circuits, refer to these Microchip Application
Notes, available at the corporate website
(www.microchip.com):
• AN1365, “Recommended Usage of Microchip
Serial RTCC Devices”
• AN1519, “Recommended Crystals for Microchip
Stand-Alone Real-Time Clock Calendar Devices”
If the load capacitance is not correctly
matched to the chosen crystal’s specified
value, the crystal may give a frequency
outside of the crystal manufacturer’s
specifications.
2011-2022 Microchip Technology Inc. and its subsidiares
DS20005010J-page 13
MCP7940N
FIGURE 5-3:
SUGGESTED PLACEMENT OF THE OSCILLATOR CIRCUIT
Single-Sided and In-line Layouts:
Copper Pour
(tied to ground)
Fine-Pitch (Dual-Sided) Layouts:
Oscillator
Crystal
Top Layer Copper Pour
(tied to ground)
Bottom Layer
Copper Pour
(tied to ground)
X1
X1
CX1
CX1
X2
GND
CX2
Oscillator
Crystal
GND
CX2
`
X2
DEVICE PINS
DEVICE PINS
5.2.2
5.2.3
EXTERNAL CLOCK INPUT
A 32.768 kHz external clock source can be connected
to the X1 pin (Figure 5-4). When using this
configuration, the X2 pin should be left floating.
Note:
The EXTOSC bit must be set to enable an
external clock source.
FIGURE 5-4:
EXTERNAL CLOCK INPUT
OPERATION
OSCILLATOR FAILURE STATUS
The MCP7940N features an oscillator failure flag,
OSCRUN, that indicates whether or not the oscillator is
running. The OSCRUN bit is automatically set after 32
oscillator cycles are detected. If no oscillator cycles are
detected for more than TOSF, then the OSCRUN bit is
automatically cleared (Figure 5-5). This can occur if the
oscillator is stopped by clearing the ST bit or due to
oscillator failure.
MCP7940N
X1
Clock from
Ext. Source
FIGURE 5-5:
OSCILLATOR FAILURE STATUS TIMING DIAGRAM
X1
32 Clock Cycles
TOSF
< TOSF
OSCRUN Bit
TABLE 5-2:
Name
RTCSEC
RTCWKDAY
CONTROL
Legend:
SUMMARY OF REGISTERS ASSOCIATED WITH OSCILLATOR CONFIGURATION
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
ST
SECTEN2
SECTEN1
SECTEN0
SECONE3
SECONE2
Bit 1
Bit 0
SECONE1 SECONE0
Register
on Page
16
—
—
OSCRUN
PWRFAIL
VBATEN
WKDAY2
WKDAY1
WKDAY0
18
OUT
SQWEN
ALM1EN
ALM0EN
EXTOSC
CRSTRIM
SQWFS1
SQWFS0
26
— = unimplemented location, read as ‘0’. Shaded cells are not used by oscillator configuration.
DS20005010J-page 14
2011-2022 Microchip Technology Inc. and its subsidiares
MCP7940N
5.3
Timekeeping
The MCP7940N maintains the current time and date
using an external 32.768 kHz crystal or clock source.
Separate registers are used for tracking seconds, minutes, hours, day of week, date, month, and year. The
MCP7940N automatically adjusts for months with less
than 31 days and compensates for leap years from
2001 to 2399. The year is stored as a two-digit value.
Both 12-hour and 24-hour time formats are supported
and are selected using the 12/24 bit.
The day of week value counts from 1 to 7, increments
at midnight, and the representation is user-defined (i.e.,
the MCP7940N does not require 1 to equal Sunday,
etc.).
All time and date values are stored in the registers as
binary-coded decimal (BCD) values. The MCP7940N
will continue to maintain the time and date while operating off the backup supply.
When reading from the timekeeping registers, the registers are buffered to prevent errors due to rollover of
counters. The following events cause the buffers to be
updated:
• When a read is initiated from the RTCC registers
(addresses 0x00 to 0x1F)
• During an RTCC register read operation, when
the register address rolls over from 0x1F to 0x00
The timekeeping registers should be read in a single
operation to utilize the on-board buffers and avoid
rollover issues.
Note 1: Loading invalid values into the time and
date registers will result in undefined
operation.
5.3.1
DIGIT CARRY RULES
The following list explains which timer values cause a
digit carry when there is a rollover:
• Time of day: from 11:59:59 PM to 12:00:00 AM
(12-hour mode) or 23:59:59 to 00:00:00 (24-hour
mode), with a carry to the Date and Weekday
fields
• Date: carries to the Month field according to Table
5-3
• Weekday: from 7 to 1 with no carry
• Month: from 12/31 to 01/01 with a carry to the
Year field
• Year: from 99 to 00 with no carry
TABLE 5-3:
DAY TO MONTH ROLLOVER
SCHEDULE
Month
Name
Maximum Date
01
January
31
02
February
28 or 29(1)
03
March
31
04
April
30
05
May
31
06
June
30
07
July
31
08
August
31
09
September
30
10
October
31
11
November
30
December
31
12
Note 1:
29 during leap years, otherwise 28.
2: To avoid rollover issues when loading
new time and date values, the oscillator/clock input should be disabled by
clearing the ST bit for External Crystal
mode and the EXTOSC bit for External
Clock Input mode. After waiting for the
OSCRUN bit to clear, the new values can
be loaded and the ST or EXTOSC bit can
then be re-enabled.
2011-2022 Microchip Technology Inc. and its subsidiares
DS20005010J-page 15
MCP7940N
REGISTER 5-1:
RTCSEC: TIMEKEEPING SECONDS VALUE REGISTER (ADDRESS 0x00)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
ST
SECTEN2
SECTEN1
SECTEN0
SECONE3
SECONE2
SECONE1
SECONE0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is clear
bit 7
ST: Start Oscillator bit
1 = Oscillator enabled
0 = Oscillator disabled
bit 6-4
SECTEN: Binary-Coded Decimal Value of Second’s Tens Digit
Contains a value from 0 to 5
bit 3-0
SECONE: Binary-Coded Decimal Value of Second’s Ones Digit
Contains a value from 0 to 9
DS20005010J-page 16
x = Bit is unknown
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MCP7940N
REGISTER 5-2:
RTCMIN: TIMEKEEPING MINUTES VALUE REGISTER (ADDRESS 0x01)
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
MINTEN2
MINTEN1
MINTEN0
MINONE3
MINONE2
MINONE1
MINONE0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is clear
x = Bit is unknown
bit 7
Unimplemented: Read as ‘0’
bit 6-4
MINTEN: Binary-Coded Decimal Value of Minute’s Tens Digit
Contains a value from 0 to 5
bit 3-0
MINONE: Binary-Coded Decimal Value of Minute’s Ones Digit
Contains a value from 0 to 9
REGISTER 5-3:
RTCHOUR: TIMEKEEPING HOURS VALUE REGISTER (ADDRESS 0x02)
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
12/24
AM/PM
HRTEN1
HRTEN0
HRONE3
HRONE2
HRONE1
HRONE0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is clear
x = Bit is unknown
If 12/24 = 1 (12-hour format):
bit 7
Unimplemented: Read as ‘0’
bit 6
12/24: 12 or 24 Hour Time Format bit
1 = 12-hour format
0 = 24-hour format
bit 5
AM/PM: AM/PM Indicator bit
1 = PM
0 = AM
bit 4
HRTEN0: Binary-Coded Decimal Value of Hour’s Tens Digit
Contains a value from 0 to 1
bit 3-0
HRONE: Binary-Coded Decimal Value of Hour’s Ones Digit
Contains a value from 0 to 9
If 12/24 = 0 (24-hour format):
bit 7
Unimplemented: Read as ‘0’
bit 6
12/24: 12 or 24 Hour Time Format bit
1 = 12-hour format
0 = 24-hour format
bit 5-4
HRTEN: Binary-Coded Decimal Value of Hour’s Tens Digit
Contains a value from 0 to 2.
bit 3-0
HRONE: Binary-Coded Decimal Value of Hour’s Ones Digit
Contains a value from 0 to 9
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DS20005010J-page 17
MCP7940N
REGISTER 5-4:
RTCWKDAY: TIMEKEEPING WEEKDAY VALUE REGISTER (ADDRESS 0x03)
U-0
U-0
R-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-1
—
—
OSCRUN
PWRFAIL
VBATEN
WKDAY2
WKDAY1
WKDAY0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is clear
x = Bit is unknown
bit 7-6
Unimplemented: Read as ‘0’
bit 5
OSCRUN: Oscillator Status bit
1 = Oscillator is enabled and running
0 = Oscillator has stopped or has been disabled
bit 4
PWRFAIL: Power Failure Status bit(1,2)
1 = Primary power was lost and the power-fail time-stamp registers have been loaded (must be
cleared in software). Clearing this bit resets the power-fail time-stamp registers to ‘0’.
0 = Primary power has not been lost
bit 3
VBATEN: External Battery Backup Supply (VBAT) Enable bit
1 = VBAT input is enabled
0 = VBAT input is disabled
bit 2-0
WKDAY: Binary-Coded Decimal Value of Day of Week
Contains a value from 1 to 7. The representation is user-defined.
Note 1:
2:
The PWRFAIL bit must be cleared to log new time-stamp data. This is to ensure previous time-stamp data
is not lost.
The PWRFAIL bit cannot be written to a ‘1’ in software. Writing to the RTCWKDAY register will always
clear the PWRFAIL bit.
REGISTER 5-5:
RTCDATE: TIMEKEEPING DATE VALUE REGISTER (ADDRESS 0x04)
U-0
U-0
R/W-0
—
—
DATETEN1
R/W-0
R/W-0
DATETEN0 DATEONE3
R/W-0
R/W-0
R/W-1
DATEONE2
DATEONE1
DATEONE0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is clear
bit 7-6
Unimplemented: Read as ‘0’
bit 5-4
DATETEN: Binary-Coded Decimal Value of Date’s Tens Digit
Contains a value from 0 to 3
bit 3-0
DATEONE: Binary-Coded Decimal Value of Date’s Ones Digit
Contains a value from 0 to 9
DS20005010J-page 18
x = Bit is unknown
2011-2022 Microchip Technology Inc. and its subsidiares
MCP7940N
REGISTER 5-6:
RTCMTH: TIMEKEEPING MONTH VALUE REGISTER (ADDRESS 0x05)
U-0
U-0
R-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-1
—
—
LPYR
MTHTEN0
MTHONE3
MTHONE2
MTHONE1
MTHONE0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is clear
x = Bit is unknown
bit 7-6
Unimplemented: Read as ‘0’
bit 5
LPYR: Leap Year bit
1 = Year is a leap year
0 = Year is not a leap year
bit 4
MTHTEN0: Binary-Coded Decimal Value of Month’s Tens Digit
Contains a value of 0 or 1
bit 3-0
MTHONE: Binary-Coded Decimal Value of Month’s Ones Digit
Contains a value from 0 to 9
REGISTER 5-7:
RTCYEAR: TIMEKEEPING YEAR VALUE REGISTER (ADDRESS 0x06)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-1
YRTEN3
YRTEN2
YRTEN1
YRTEN0
YRONE3
YRONE2
YRONE1
YRONE0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is clear
bit 7-4
YRTEN: Binary-Coded Decimal Value of Year’s Tens Digit
Contains a value from 0 to 9
bit 3-0
YRONE: Binary-Coded Decimal Value of Year’s Ones Digit
Contains a value from 0 to 9
TABLE 5-4:
Name
x = Bit is unknown
SUMMARY OF REGISTERS ASSOCIATED WITH TIMEKEEPING
Register
on Page
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RTCSEC
ST
SECTEN2
SECTEN1
SECTEN0
SECONE3
SECONE2
SECONE1
SECONE0
16
RTCMIN
—
MINTEN2
MINTEN1
MINTEN0
MINONE3
MINONE2
MINONE1
MINONE0
17
RTCHOUR
—
12/24
AM/PM
HRTEN1
HRTEN0
HRONE3
HRONE2
HRONE1
HRONE0
17
RTCWKDAY
—
—
OSCRUN
PWRFAIL
VBATEN
WKDAY2
WKDAY1
WKDAY0
18
RTCDATE
—
—
DATETEN1 DATETEN0 DATEONE3 DATEONE2 DATEONE1 DATEONE0
18
RTCMTH
—
—
LPYR
MTHTEN0
MTHONE3
MTHONE2
MTHONE1
MTHONE0
19
RTCYEAR
YRTEN3
YRTEN2
YRTEN1
YRTEN0
YRONE3
YRONE2
YRONE1
YRONE0
19
Legend:
— = unimplemented location, read as ‘0’. Shaded cells are not used in timekeeping.
2011-2022 Microchip Technology Inc. and its subsidiares
DS20005010J-page 19
MCP7940N
5.4
Alarms
TABLE 5-5:
ALARM MASKS
The MCP7940N features two independent alarms.
Each alarm can be used to either generate an interrupt
at a specific time in the future, or to generate a periodic
interrupt every minute, hour, day, day of week, or
month.
ALMxMSK
Alarm Asserts on Match of
000
Seconds
001
Minutes
010
Hours
There is a separate interrupt flag, ALMxIF, for each
alarm. The interrupt flags are set by hardware when the
chosen alarm mask condition matches (Table 5-5). The
interrupt flags must be cleared in software.
011
Day of Week
100
Date
101
Reserved
110
Reserved
111
Seconds, Minutes, Hours, Day of
Week, Date, and Month
If either alarm module is enabled by setting the corresponding ALMxEN bit in the CONTROL register, and if
the square wave clock output is disabled (SQWEN =
0), then the MFP will operate in Alarm Interrupt Output
mode. Refer to Section 5.5 “Output Configurations”
for details. The alarm interrupt output is available while
operating from the backup power supply.
Note 1: The alarm interrupt flags must be cleared
by the user. If a flag is cleared while the
corresponding alarm condition still
matches, the flag will be set again, generating another interrupt.
Both Alarm0 and Alarm1 offer identical operation. All
time and date values are stored in the registers as
binary-coded decimal (BCD) values.
Note:
2: Loading invalid values into the alarm registers will result in undefined operation.
Throughout this section, references to the
register and bit names for the alarm modules are referred to generically by the use
of ‘x’ in place of the specific module number. Thus, “ALMxSEC” might refer to the
seconds register for Alarm0 or Alarm1.
FIGURE 5-6:
ALARM BLOCK DIAGRAM
Alarm0
Registers
Timekeeping
Registers
Alarm1
Registers
ALM0SEC
RTCSEC
ALM1SEC
ALM0MIN
RTCMIN
ALM1MIN
ALM0HOUR
RTCHOUR
ALM1HOUR
ALM0WKDAY
RTCWKDAY
ALM1WKDAY
ALM0DATE
RTCDATE
ALM1DATE
ALM0MTH
RTCMTH
ALM1MTH
Alarm0 Mask
Comparator
Comparator
Set
ALM0IF
ALM0MSK
DS20005010J-page 20
Alarm1 Mask
Set
ALM1IF
MFP Output Logic
MFP
ALM1MSK
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MCP7940N
5.4.1
CONFIGURING THE ALARM
In order to configure the alarm modules, the following
steps need to be performed:
1.
2.
3.
4.
5.
6.
Load the timekeeping registers and enable the
oscillator
Configure the ALMxMSK bits to select the
desired alarm mask
Set or clear the ALMPOL bit according to the
desired output polarity
Ensure the ALMxIF flag is cleared
Based on the selected alarm mask, load the
alarm match value into the appropriate register(s)
Enable the alarm module by setting the
ALMxEN bit
REGISTER 5-8:
ALMxSEC: ALARM0/1 SECONDS VALUE REGISTER (ADDRESSES 0x0A/0x11)
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
SECTEN2
SECTEN1
SECTEN0
SECONE3
SECONE2
SECONE1
SECONE0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is clear
x = Bit is unknown
bit 7
Unimplemented: Read as ‘0’
bit 6-4
SECTEN: Binary-Coded Decimal Value of Second’s Tens Digit
Contains a value from 0 to 5
bit 3-0
SECONE: Binary-Coded Decimal Value of Second’s Ones Digit
Contains a value from 0 to 9
REGISTER 5-9:
ALMxMIN: ALARM0/1 MINUTES VALUE REGISTER (ADDRESSES 0x0B/0x12)
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
MINTEN2
MINTEN1
MINTEN0
MINONE3
MINONE2
MINONE1
MINONE0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is clear
bit 7
Unimplemented: Read as ‘0’
bit 6-4
MINTEN: Binary-Coded Decimal Value of Minute’s Tens Digit
Contains a value from 0 to 5
bit 3-0
MINONE: Binary-Coded Decimal Value of Minute’s Ones Digit
Contains a value from 0 to 9
2011-2022 Microchip Technology Inc. and its subsidiares
x = Bit is unknown
DS20005010J-page 21
MCP7940N
REGISTER 5-10:
ALMxHOUR: ALARM0/1 HOURS VALUE REGISTER (ADDRESSES 0x0C/0x13)
U-0
R-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
12/24
AM/PM
HRTEN1
HRTEN0
HRONE3
HRONE2
HRONE1
HRONE0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is clear
x = Bit is unknown
If 12/24 = 1 (12-hour format):
bit 7
Unimplemented: Read as ‘0’
bit 6
12/24: 12 or 24 Hour Time Format bit(1)
1 = 12-hour format
0 = 24-hour format
bit 5
AM/PM: AM/PM Indicator bit
1 = PM
0 = AM
bit 4
HRTEN0: Binary-Coded Decimal Value of Hour’s Tens Digit
Contains a value from 0 to 1
bit 3-0
HRONE: Binary-Coded Decimal Value of Hour’s Ones Digit
Contains a value from 0 to 9
If 12/24 = 0 (24-hour format):
bit 7
Unimplemented: Read as ‘0’
bit 6
12/24: 12 or 24 Hour Time Format bit(1)
1 = 12-hour format
0 = 24-hour format
bit 5-4
HRTEN: Binary-Coded Decimal Value of Hour’s Tens Digit
Contains a value from 0 to 2.
bit 3-0
HRONE: Binary-Coded Decimal Value of Hour’s Ones Digit
Contains a value from 0 to 9
Note 1:
This bit is read-only and reflects the value of the 12/24 bit in the RTCHOUR register.
DS20005010J-page 22
2011-2022 Microchip Technology Inc. and its subsidiares
MCP7940N
REGISTER 5-11:
ALMxWKDAY: ALARM0/1 WEEKDAY VALUE REGISTER (ADDRESSES
0x0D/0x14)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-1
ALMPOL
ALMxMSK2
ALMxMSK1
ALMxMSK0
ALMxIF
WKDAY2
WKDAY1
WKDAY0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is clear
x = Bit is unknown
bit 7
ALMPOL: Alarm Interrupt Output Polarity bit
1 = Asserted output state of MFP is a logic high level
0 = Asserted output state of MFP is a logic low level
bit 6-4
ALMxMSK: Alarm Mask bits
000 = Seconds match
001 = Minutes match
010 = Hours match (logic takes into account 12-/24-hour operation)
011 = Day of week match
100 = Date match
101 = Reserved; do not use
110 = Reserved; do not use
111 = Seconds, Minutes, Hour, Day of Week, Date and Month
bit 3
ALMxIF: Alarm Interrupt Flag bit(1,2)
1 = Alarm match occurred (must be cleared in software)
0 = Alarm match did not occur
bit 2-0
WKDAY: Binary-Coded Decimal Value of Day bits
Contains a value from 1 to 7. The representation is user-defined.
Note 1:
2:
If a match condition still exists when this bit is cleared, it will be set again automatically.
The ALMxIF bit cannot be written to a 1 in software. Writing to the ALMxWKDAY register will always clear
the ALMxIF bit.
REGISTER 5-12:
ALMxDATE: ALARM0/1 DATE VALUE REGISTER (ADDRESSES 0x0E/0x15)
U-0
U-0
R/W-0
—
—
DATETEN1
R/W-0
R/W-0
DATETEN0 DATEONE3
R/W-0
R/W-0
R/W-1
DATEONE2
DATEONE1
DATEONE0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is clear
bit 7-6
Unimplemented: Read as ‘0’
bit 5-4
DATETEN: Binary-Coded Decimal Value of Date’s Tens Digit
Contains a value from 0 to 3
bit 3-0
DATEONE: Binary-Coded Decimal Value of Date’s Ones Digit
Contains a value from 0 to 9
2011-2022 Microchip Technology Inc. and its subsidiares
x = Bit is unknown
DS20005010J-page 23
MCP7940N
REGISTER 5-13:
ALMxMTH: ALARM0/1 MONTH VALUE REGISTER (ADDRESSES 0x0F/0x16)
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-1
—
—
—
MTHTEN0
MTHONE3
MTHONE2
MTHONE1
MTHONE0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is clear
x = Bit is unknown
bit 7-5
Unimplemented: Read as ‘0’
bit 4
MTHTEN0: Binary-Coded Decimal Value of Month’s Tens Digit
Contains a value of 0 or 1
bit 3-0
MTHONE: Binary-Coded Decimal Value of Month’s Ones Digit
Contains a value from 0 to 9
TABLE 5-6:
SUMMARY OF REGISTERS ASSOCIATED WITH ALARMS
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Register
on Page
ALM0SEC
—
SECTEN2
SECTEN1
SECTEN0
SECONE3
SECONE2
SECONE1
SECONE0
21
ALM0MIN
—
MINTEN2
MINTEN1
MINTEN0
MINONE3
MINONE2
MINONE1
MINONE0
21
ALM0HOUR
—
12/24
AM/PM
HRTEN1
HRTEN0
HRONE3
HRONE2
HRONE1
HRONE0
22
ALMPOL
ALM0MSK2
ALM0MSK1
ALM0MSK0
ALM0IF
WKDAY2
WKDAY1
WKDAY0
23
ALM0DATE
—
—
DATETEN1
DATETEN0
DATEONE3
DATEONE2
DATEONE1
DATEONE0
23
ALM0MTH
—
—
—
MTHTEN0
MTHONE3
MTHONE2
MTHONE1
MTHONE0
24
ALM1SEC
—
SECTEN2
SECTEN1
SECTEN0
SECONE3
SECONE2
SECONE1
SECONE0
21
ALM1MIN
—
MINTEN2
MINTEN1
MINTEN0
MINONE3
MINONE2
MINONE1
MINONE0
21
ALM1HOUR
—
12/24
AM/PM
HRTEN1
HRTEN0
HRONE3
HRONE2
HRONE1
HRONE0
22
Name
ALM0WKDAY
ALMPOL
ALM1MSK2
ALM1MSK1
ALM1MSK0
ALM1IF
WKDAY2
WKDAY1
WKDAY0
23
ALM1DATE
—
—
DATETEN1
DATETEN0
DATEONE3
DATEONE2
DATEONE1
DATEONE0
23
ALM1MTH
—
—
—
MTHTEN0
MTHONE3
MTHONE2
MTHONE1
MTHONE0
24
CONTROL
OUT
SQWEN
ALM1EN
ALM0EN
EXTOSC
CRSTRIM
SQWFS1
SQWFS0
26
ALM1WKDAY
Legend:
— = unimplemented location, read as ‘0’. Shaded cells are not used by alarms.
DS20005010J-page 24
2011-2022 Microchip Technology Inc. and its subsidiares
MCP7940N
5.5
Output Configurations
TABLE 5-7:
SQWEN ALM0EN ALM1EN
The MCP7940N features Square Wave Clock Output,
Alarm Interrupt Output, and General Purpose Output
modes. All of the output functions are multiplexed onto
MFP according to Table 5-7.
Only the alarm interrupt outputs are available while
operating from the backup power supply. If none of the
output functions are being used, the MFP can safely be
left floating.
Note:
MFP OUTPUT MODES
0
0
0
0
1
0
0
0
1
0
1
1
1
x
x
General Purpose
Output
Alarm Interrupt
Output
Square Wave Clock
Output
The MFP is an open-drain output and
requires a pull-up resistor to VCC (typically
10 k).
FIGURE 5-7:
Mode
MFP OUTPUT BLOCK DIAGRAM
MCP7940N
SQWFS
Oscillator
8.192 kHz
X2
4.096 kHz
Postscaler
EXTOSC
Digital
Trim
ST
1 Hz
64 Hz
11
10
01
00
MUX
32.768 kHz
X1
0
1
CRSTRIM
ALM1EN,ALM0EN
ALMPOL
11
1
10
0
01
OUT
ALM0IF
00
MFP
1
MUX
ALM1IF
0
SQWEN
1
0
2011-2022 Microchip Technology Inc. and its subsidiares
DS20005010J-page 25
MCP7940N
REGISTER 5-14:
CONTROL: RTCC CONTROL REGISTER (ADDRESS 0x07)
R/W-1
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
OUT
SQWEN
ALM1EN
ALM0EN
EXTOSC
CRSTRIM
SQWFS1
SQWFS0
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is clear
bit 7
x = Bit is unknown
OUT: Logic Level for General Purpose Output bit
Square Wave Clock Output Mode (SQWEN = 1):
Unused.
Alarm Interrupt Output mode (ALM0EN = 1 or ALM1EN = 1):
Unused.
General Purpose Output mode (SQWEN = 0, ALM0EN = 0, and ALM1EN = 0):
1 = MFP signal level is logic high
0 = MFP signal level is logic low
bit 6
SQWEN: Square Wave Output Enable bit
1 = Enable Square Wave Clock Output mode
0 = Disable Square Wave Clock Output mode
bit 5
ALM1EN: Alarm 1 Module Enable bit
1 = Alarm 1 enabled
0 = Alarm 1 disabled
bit 4
ALM0EN: Alarm 0 Module Enable bit
1 = Alarm 0 enabled
0 = Alarm 0 disabled
bit 3
EXTOSC: External Oscillator Input bit
1 = Enable X1 pin to be driven by external 32.768 kHz source
0 = Disable external 32.768 kHz input
bit 2
CRSTRIM: Coarse Trim Mode Enable bit
Coarse Trim mode results in the MCP7940N applying digital trimming every 64 Hz clock cycle.
1 = Enable Coarse Trim mode. If SQWEN = 1, MFP will output trimmed 64 Hz(1) nominal clock signal.
0 = Disable Coarse Trim mode
See Section 5.6 “Digital Trimming” for details
bit 1-0
SQWFS: Square Wave Clock Output Frequency Select bits
If SQWEN = 1 and CRSTRIM = 0:
Selects frequency of clock output on MFP
00 = 1 Hz(1)
01 = 4.096 kHz(1)
10 = 8.192 kHz(1)
11 = 32.768 kHz
If SQWEN = 0 or CRSTRIM = 1:
Unused.
Note 1:
The 8.192 kHz, 4.096 kHz, 64 Hz, and 1 Hz square wave clock output frequencies are affected by digital
trimming.
DS20005010J-page 26
2011-2022 Microchip Technology Inc. and its subsidiares
MCP7940N
5.5.1
SQUARE WAVE OUTPUT MODE
The MCP7940N can be configured to generate a
square wave clock signal on MFP. The input clock
frequency, FOSC, is divided according to the
SQWFS bits as shown in Table 5-8.
The square wave output is not available when operating from the backup power supply.
Note:
All of the clock output rates are affected by
digital trimming except for the 1:1
postscaler value (SQWFS = 11).
5.5.2.2
When both alarm modules are enabled, the MFP output is determined by a combination of the ALM0IF,
ALM1IF, and ALMPOL flags.
If ALMPOL = 1, the ALM0IF and ALM1IF flags are
OR’d together and the result is output on MFP. If
ALMPOL = 0, the ALM0IF and ALM1IF flags are AND’d
together, and the result is inverted and output on MFP
(Table 5-10). This provides the user with flexible
options for combining alarms.
Note:
TABLE 5-8:
CLOCK OUTPUT RATES
SQWFS
Postscaler
Nominal
Frequency
00
1:32,768
1 Hz
01
1:8
4.096 kHz
10
1:4
8.192 kHz
11
1:1
32.768 kHz
Note 1:
5.5.2
The ALMxIF flags control when the MFP is asserted, as
described in the following sections.
5.5.2.1
Single Alarm Operation
When only one alarm module is enabled, the MFP output
is based on the corresponding ALMxIF flag and the
ALMPOL flag. If ALMPOL = 1, the MFP output reflects
the value of the ALMxIF flag. If ALMPOL = 0, the MFP
output reflects the inverse of the ALMxIF flag (Table 5-9).
TABLE 5-9:
DUAL ALARM OUTPUT
TRUTH TABLE
ALMPOL
ALM0IF
ALM1IF
MFP
0
0
0
1
0
0
1
1
0
1
0
1
0
1
1
0
1
0
0
0
1
0
1
1
1
1
0
1
1
1
1
1
ALARM INTERRUPT OUTPUT
MODE
The alarm interrupt output is available when operating
from the backup power supply.
If ALMPOL = 0 and both alarms are
enabled, the MFP will only assert when
both ALM0IF and ALM1IF are set.
TABLE 5-10:
Nominal frequency assumes FOSC is
32.768 kHz.
The MFP will provide an interrupt output when enabled
alarms match and the square wave clock output is disabled. This prevents the user from having to poll the
alarm interrupt flag to check for a match.
Dual Alarm Operation
5.5.3
GENERAL PURPOSE OUTPUT
MODE
If the square wave clock output and both alarm modules are disabled, the MFP acts as a general purpose
output. The output logic level is controlled by the OUT
bit.
The general purpose output is not available when
operating from the backup power supply.
SINGLE ALARM OUTPUT
TRUTH TABLE
ALMPOL
ALMxIF(1)
MFP
0
0
1
0
1
0
1
0
0
1
1
1
Note 1: ALMxIF refers to the interrupt flag corresponding to the alarm module that is
enabled.
2011-2022 Microchip Technology Inc. and its subsidiares
DS20005010J-page 27
MCP7940N
TABLE 5-11:
SUMMARY OF REGISTERS ASSOCIATED WITH OUTPUT CONFIGURATION
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Register
on Page
ALM0WKDAY
ALMPOL
ALM0MSK2
ALM0MSK1
ALM0MSK0
ALM0IF
WKDAY2
WKDAY1
WKDAY0
23
ALM1WKDAY
ALMPOL
ALM1MSK2
ALM1MSK1
ALM1MSK0
ALM1IF
WKDAY2
WKDAY1
WKDAY0
23
OUT
SQWEN
ALM1EN
ALM0EN
EXTOSC
CRSTRIM
SQWFS1
SQWFS0
26
Name
CONTROL
Legend:
— = unimplemented location, read as ‘0’. Shaded cells are not used in output configuration.
DS20005010J-page 28
2011-2022 Microchip Technology Inc. and its subsidiares
MCP7940N
5.6
Digital Trimming
The MCP7940N features digital trimming to correct for
inaccuracies of the external crystal or clock source, up
to roughly ±129 PPM when CRSTRIM = 0. In addition
to compensating for intrinsic inaccuracies in the clock,
this feature can also be used to correct for error due to
temperature variation. This can enable the user to
achieve high levels of accuracy across a wide temperature operating range.
Digital trimming consists of the MCP7940N periodically
adding or subtracting clock cycles, resulting in small
adjustments in the internal timing. The adjustment
REGISTER 5-15:
occurs once per minute when CRSTRIM = 0. The SIGN
bit specifies whether to add cycles or to subtract them.
The TRIMVAL bits are used to specify by how
many clock cycles to adjust. Each step in the
TRIMVAL value equates to adding or subtracting
two clock pulses to or from the 32.768 kHz clock signal.
This results in a correction of roughly 1.017 PPM per
step when CRSTRIM = 0. Setting TRIMVAL to
0x00 disables digital trimming.
Digital trimming also occurs while operating off the
backup supply.
OSCTRIM: OSCILLATOR DIGITAL TRIM REGISTER (ADDRESS 0x08)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
SIGN
TRIMVAL6
TRIMVAL5
TRIMVAL4
TRIMVAL3
TRIMVAL2
TRIMVAL1
TRIMVAL0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is clear
bit 7
SIGN: Trim Sign bit
1 = Add clocks to correct for slow time
0 = Subtract clocks to correct for fast time
bit 6-0
TRIMVAL: Oscillator Trim Value bits
When CRSTRIM = 0:
1111111 = Add or subtract 254 clock cycles every minute
1111110 = Add or subtract 252 clock cycles every minute
•
•
•
0000010 = Add or subtract 4 clock cycles every minute
0000001 = Add or subtract 2 clock cycles every minute
0000000 = Disable digital trimming
x = Bit is unknown
When CRSTRIM = 1:
1111111 = Add or subtract 254 clock cycles 128 times per second
1111110 = Add or subtract 252 clock cycles 128 times per second
•
•
•
0000010 = Add or subtract 4 clock cycles 128 times per second
0000001 = Add or subtract 2 clock cycles 128 times per second
0000000 = Disable digital trimming
2011-2022 Microchip Technology Inc. and its subsidiares
DS20005010J-page 29
MCP7940N
5.6.1
CALIBRATION
In order to perform calibration, the number of error
clock pulses per minute must be found and the corresponding trim value must be loaded into
TRIMVAL.
There are two methods for determining the trim value.
The first method involves measuring an output frequency directly and calculating the deviation from ideal.
The second method involves observing the number of
seconds gained or lost over a period of time.
Once the OSCTRIM register has been loaded, digital
trimming will automatically occur every minute.
5.6.1.1
5.6.1.2
Calibration by Observing Time
Deviation
To calibrate the MCP7940N by observing the deviation
over time, perform the following steps:
1.
2.
3.
4.
Calibration by Measuring Frequency
Ensure TRIMVAL is reset to 0x00.
Load the timekeeping registers to synchronize
the MCP7940N with a known-accurate reference time.
Enable the crystal oscillator or external clock
input by setting the ST bit or EXTOSC bit,
respectively.
Observe how many seconds are gained or lost
over a period of time (larger time periods offer
more accuracy).
Calculate the PPM deviation (see Equation 5-3).
To calibrate the MCP7940N by measuring the output
frequency, perform the following steps:
5.
1.
EQUATION 5-3:
2.
3.
4.
5.
6.
Enable the crystal oscillator or external clock
input by setting the ST bit or EXTOSC bit,
respectively.
Ensure TRIMVAL is reset to 0x00.
Select an output frequency by setting
SQWFS.
Set SQWEN to enable the square wave output.
Measure the resulting output frequency using a
calibrated measurement tool, such as a
frequency counter.
Calculate the number of error clocks per minute
(see Equation 5-2).
EQUATION 5-2:
SecDeviation
PPM = ----------------------------------- 1000000
ExpectedSec
Where:
ExpectedSec = Number of seconds in chosen period
SecDeviation = Number of seconds gained or lost
CALCULATING TRIM
VALUE FROM MEASURED
FREQUENCY
32768
F IDEAL – F MEAS ------------------- 60
F
IDEAL
TRIMVAL = -------------------------------------------------------------------------------2
6.
F IDEAL = Ideal frequency based on SQWFS
F MEAS = Measured frequency
7.
Note:
• If the MCP7940N has gained time relative to
the reference clock, then the oscillator is
faster than ideal and the SIGN bit must be
cleared.
• If the MCP7940N has lost time relative to the
reference clock, then the oscillator is slower
than ideal and the SIGN bit must be set.
Calculate the trim value (see Equation 5-4).
EQUATION 5-4:
Where:
• If the number of error clocks per minute is
negative, then the oscillator is faster than
ideal and the SIGN bit must be cleared.
• If the number of error clocks per minute is
positive, then the oscillator is slower than
ideal and the SIGN bit must be set.
Load the correct value into TRIMVAL.
CALCULATING ERROR
PPM
CALCULATING TRIM
VALUE FROM ERROR
PPM
32768 60TRIMVAL = PPM
-----------------------------------------1000000 2
7.
Load the correct value into TRIMVAL.
Note 1: Choosing a longer time period for observing deviation will improve accuracy.
2: Large temperature variations during the
observation period can skew results.
Using a lower output frequency and/or
averaging the measured frequency over a
number of clock pulses will reduce the
effects of jitter and improve accuracy.
DS20005010J-page 30
2011-2022 Microchip Technology Inc. and its subsidiares
MCP7940N
5.6.2
COARSE TRIM MODE
When CRSTRIM = 1, Coarse Trim mode is enabled.
While in this mode, the MCP7940N will apply trimming
at a rate of 128 Hz. If SQWEN is set, the MFP will output a trimmed 64 Hz nominal clock signal.
Because trimming is applied at a rate of 128 Hz rather
than once every minute, each step of the
TRIMVAL value has a significantly larger effect
on the resulting time deviation and output clock
frequency.
TABLE 5-12:
Name
Note 1: The 64 Hz Coarse Trim mode square
wave output is not available while operating from the backup power supply.
2: With Coarse Trim mode enabled, the
TRIMVAL value has a drastic effect
on timing. Leaving the mode enabled
during normal operation will likely result
in inaccurate time.
SUMMARY OF REGISTERS ASSOCIATED WITH DIGITAL TRIMMING
Bit 7
CONTROL
OUT
OSCTRIM
SIGN
Legend:
By monitoring the MFP output frequency while in this
mode, the user can easily observe the TRIMVAL
value affecting the clock timing.
Bit 6
Bit 5
Bit 4
SQWEN
ALM1EN
ALM0EN
TRIMVAL6 TRIMVAL5 TRIMVAL4
Bit 3
Bit 2
EXTOSC
CRSTRIM
TRIMVAL3
TRIMVAL2
Bit 1
Bit 0
Register
on Page
SQWFS1
SQWFS0
26
TRIMVAL1 TRIMVAL0
29
— = unimplemented location, read as ‘0’. Shaded cells are not used by digital trimming.
2011-2022 Microchip Technology Inc. and its subsidiares
DS20005010J-page 31
MCP7940N
5.7
Battery Backup
The MCP7940N features a backup power supply input
(VBAT) that can be used to provide power to the timekeeping circuitry, RTCC registers, and SRAM while primary power is unavailable. The MCP7940N will
automatically switch to backup power when VCC falls
below VTRIP, and back to VCC when it is above VTRIP.
5.7.1
The MCP7940N includes a power-fail time-stamp module that stores the minutes, hours, date, and month
when primary power is lost and when it is restored
(Figure 5-8). The PWRFAIL bit is also set to indicate
that a power failure occurred.
Note:
The VBATEN bit must be set to enable the VBAT input.
The following functionality is maintained while operating on backup power:
•
•
•
•
•
Timekeeping
Alarms
Alarm Output
Digital Trimming
RTCC Register and SRAM Contents
The following features are not available while operating
on backup power:
•
•
•
Throughout this section, references to the
register and bit names for the Power-Fail
Time-Stamp module are referred to generically by the use of ‘x’ in place of the specific module name. Thus, “PWRxxMIN”
might refer to the minutes register for
Power-Down or Power-Up.
To utilize the power-fail time-stamp feature, a backup
power supply must be available with the VBAT input
enabled, and the oscillator should also be running to
ensure accurate functionality.
I2C Communication
Square Wave Clock Output
General Purpose Output
FIGURE 5-8:
POWER-FAIL TIME-STAMP
Note 1: The PWRFAIL bit must be cleared to log
new time-stamp data. This is to ensure
previous time-stamp data is not lost.
2: Clearing the PWRFAIL bit will clear all
time-stamp registers.
POWER-FAIL TIME-STAMP TIMING
VCC
VTRIP
Power-Down
Time-Stamp
DS20005010J-page 32
Power-Up
Time-Stamp
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MCP7940N
REGISTER 5-16:
PWRxxMIN: POWER-DOWN/POWER-UP TIME-STAMP MINUTES VALUE
REGISTER (ADDRESSES 0x18/0x1C)
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
MINTEN2
MINTEN1
MINTEN0
MINONE3
MINONE2
MINONE1
MINONE0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is clear
x = Bit is unknown
bit 7
Unimplemented: Read as ‘0’
bit 6-4
MINTEN: Binary-Coded Decimal Value of Minute’s Tens Digit
Contains a value from 0 to 5
bit 3-0
MINONE: Binary-Coded Decimal Value of Minute’s Ones Digit
Contains a value from 0 to 9
REGISTER 5-17:
PWRxxHOUR: POWER-DOWN/POWER-UP TIME-STAMP HOURS VALUE
REGISTER (ADDRESSES 0x19/0x1D)
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
12/24
AM/PM
HRTEN1
HRTEN0
HRONE3
HRONE2
HRONE1
HRONE0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is clear
x = Bit is unknown
If 12/24 = 1 (12-hour format):
bit 7
Unimplemented: Read as ‘0’
bit 6
12/24: 12 or 24 Hour Time Format bit
1 = 12-hour format
0 = 24-hour format
bit 5
AM/PM: AM/PM Indicator bit
1 = PM
0 = AM
bit 4
HRTEN0: Binary-Coded Decimal Value of Hour’s Tens Digit
Contains a value from 0 to 1
bit 3-0
HRONE: Binary-Coded Decimal Value of Hour’s Ones Digit
Contains a value from 0 to 9
If 12/24 = 0 (24-hour format):
bit 7
Unimplemented: Read as ‘0’
bit 6
12/24: 12 or 24 Hour Time Format bit
1 = 12-hour format
0 = 24-hour format
bit 5-4
HRTEN: Binary-Coded Decimal Value of Hour’s Tens Digit
Contains a value from 0 to 2.
bit 3-0
HRONE: Binary-Coded Decimal Value of Hour’s Ones Digit
Contains a value from 0 to 9
2011-2022 Microchip Technology Inc. and its subsidiares
DS20005010J-page 33
MCP7940N
REGISTER 5-18:
PWRxxDATE: POWER-DOWN/POWER-UP TIME-STAMP DATE VALUE
REGISTER (ADDRESSES 0x1A/0x1E)
U-0
U-0
R/W-0
—
—
DATETEN1
R/W-0
R/W-0
DATETEN0 DATEONE3
R/W-0
R/W-0
R/W-0
DATEONE2
DATEONE1
DATEONE0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is clear
x = Bit is unknown
bit 7-6
Unimplemented: Read as ‘0’
bit 5-4
DATETEN: Binary-Coded Decimal Value of Date’s Tens Digit
Contains a value from 0 to 3
bit 3-0
DATEONE: Binary-Coded Decimal Value of Date’s Ones Digit
Contains a value from 0 to 9
REGISTER 5-19:
PWRxxMTH: POWER-DOWN/POWER-UP TIME-STAMP MONTH VALUE
REGISTER (ADDRESSES 0x1B/0x1F)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
WKDAY2
WKDAY1
WKDAY0
MTHTEN0
MTHONE3
MTHONE2
MTHONE1
MTHONE0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is clear
x = Bit is unknown
bit 7-5
WKDAY: Binary-Coded Decimal Value of Day bits
Contains a value from 1 to 7. The representation is user-defined.
bit 4
MTHTEN0: Binary-Coded Decimal Value of Month’s Ones Digit
Contains a value of 0 or 1
bit 3-0
MTHONE: Binary-Coded Decimal Value of Month’s Ones Digit
Contains a value from 0 to 9
TABLE 5-13:
Name
SUMMARY OF REGISTERS ASSOCIATED WITH BATTERY BACKUP
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Register
on Page
RTCWKDAY
—
—
OSCRUN
PWRFAIL
VBATEN
WKDAY2
WKDAY1
WKDAY0
18
PWRDNMIN
—
MINTEN2
MINTEN1
MINTEN0
MINONE3
MINONE2
MINONE1
MINONE0
33
PWRDNHOUR
—
12/24
AM/PM
HRTEN1
HRTEN0
HRONE3
HRONE2
HRONE1
HRONE0
33
PWRDNDATE
—
—
DATETEN1
DATETEN0
DATEONE3
DATEONE2
DATEONE1
DATEONE0
34
PWRDNMTH
WKDAY2
WKDAY1
WKDAY0
MTHTEN0
MTHONE3
MTHONE2
MTHONE1
MTHONE0
34
PWRUPMIN
—
MINTEN2
MINTEN1
MINTEN0
MINONE3
MINONE2
MINONE1
MINONE0
33
PWRUPHOUR
—
12/24
AM/PM
HRTEN1
HRTEN0
HRONE3
HRONE2
HRONE1
HRONE0
33
PWRUPDATE
—
—
DATETEN1
DATETEN0
DATEONE3
DATEONE2
DATEONE1
DATEONE0
34
PWRUPMTH
WKDAY2
WKDAY1
WKDAY0
MTHTEN0
MTHONE3
MTHONE2
MTHONE1
MTHONE0
34
Legend:
— = unimplemented location, read as ‘0’. Shaded cells are not used with battery backup.
DS20005010J-page 34
2011-2022 Microchip Technology Inc. and its subsidiares
MCP7940N
6.0
ON-BOARD MEMORY
device transmits the data byte to be written into the
addressed memory location. The MCP7940N stores
the data byte into memory and acknowledges again,
and the host generates a Stop condition (Figure 6-1).
The MCP7940N has 64 bytes of SRAM for general purpose usage. It is retained when the primary power
supply is removed if a backup supply is present and
enabled.
If an attempt is made to write to an address past 0x5F,
the MCP7940N will not acknowledge the address or
data bytes, and no data will be written. After a byte
Write command, the internal Address Pointer will point
to the address location following the one that was just
written.
Although the SRAM is a separate block from the RTCC
registers, they are accessed using the same control
byte, ‘1101111X’.
6.1
SRAM/RTCC Registers
6.1.2
The RTCC registers are located at addresses 0x00 to
0x1F, and the SRAM is located at addresses 0x20 to
0x5F. The SRAM can be accessed while the RTCC registers are being internally updated. The SRAM is not
initialized by a Power-On Reset (POR).
The write control byte, address, and the first data byte
are transmitted to the MCP7940N in the same way as
in a byte write. But instead of generating a Stop condition, the host transmits additional data bytes. Upon
receipt of each byte, the MCP7940N responds with an
Acknowledge, during which the data is latched into
memory and the Address Pointer is internally incremented by one. As with the byte write operation, the
host ends the command by generating a Stop condition
(Figure 6-2).
Neither the RTCC registers nor the SRAM can be
accessed when the device is operating off the backup
power supply.
6.1.1
SRAM/RTCC REGISTER BYTE
WRITE
Following the Start condition from the host, the control
code and the R/W bit (which is a logic low) are clocked
onto the bus by the host transmitter. This indicates to
the addressed client receiver that the address byte will
follow after it has generated an Acknowledge bit during
the ninth clock cycle. Therefore, the next byte transmitted by the host is the address and will be written into the
Address Pointer of the MCP7940N. After receiving
another Acknowledge bit from the MCP7940N, the host
FIGURE 6-1:
S
T
A
R
T
SDA Line
Control
Byte
SDA Line
Bus Activity
Address
Byte
S11 01111 0
S
T
O
P
Data
P
0
A
C
K
Bus Activity
Bus Activity
Host
There is no limit to the number of bytes that can be written in a single command. However, because the RTCC
registers and SRAM are separate blocks, writing past
the end of each block will cause the Address Pointer to
roll over to the beginning of the same block. Specifically, the Address Pointer will roll over from 0x1F to
0x00, and from 0x5F to 0x20.
SRAM/RTCC BYTE WRITE
Bus Activity
Host
FIGURE 6-2:
SRAM/RTCC REGISTER
SEQUENTIAL WRITE
A
C
K
A
C
K
SRAM/RTCC SEQUENTIAL WRITE
S
T
A
R
T
Control
Byte
Address
Byte
Data Byte 0
Data Byte N
S
T
O
P
P
0
S110 11110
A
C
K
2011-2022 Microchip Technology Inc. and its subsidiares
A
C
K
A
C
K
A
C
K
DS20005010J-page 35
MCP7940N
6.1.3
SRAM/RTCC REGISTER CURRENT
ADDRESS READ
address is sent, the host generates a Start condition
following the Acknowledge. This terminates the write
operation, but not before the internal Address Pointer is
set. Then, the host issues the control byte again but
with the R/W bit set to a ‘1’. The MCP7940N will then
issue an Acknowledge and transmit the 8-bit data word.
The host will not acknowledge the transfer but it does
generate a Stop condition which causes the
MCP7940N to discontinue transmission (Figure 6-4).
After a random Read command, the internal address
counter will point to the address location following the
one that was just read.
The MCP7940N contains an address counter that
maintains the address of the last byte accessed, internally incremented by one. Therefore, if the previous
read access was to address n (n is any legal address),
the next current address read operation would access
data from address n + 1.
Upon receipt of the control byte with R/W bit set to ‘1’,
the MCP7940N issues an Acknowledge and transmits
the 8-bit data word. The host will not acknowledge the
transfer but does generate a Stop condition and the
MCP7940N discontinues transmission (Figure 6-3).
FIGURE 6-3:
SRAM/RTCC CURRENT
ADDRESS READ
Bus Activity
Host
S
T
A
R
T
SDA Line
S 1 1 0 1 1 1 1 1
Control
Byte
P
A
C
K
N
O
A
C
K
SRAM/RTCC REGISTER RANDOM
READ
Because the RTCC registers and SRAM are separate
blocks, reading past the end of each block will cause
the Address Pointer to roll over to the beginning of the
same block. Specifically, the Address Pointer will roll
over from 0x1F to 0x00, and from 0x5F to 0x20.
Random read operations allow the host to access any
memory location in a random manner. To perform this
type of read operation, first the address must be set.
This is done by sending the address to the MCP7940N
as part of a write operation (R/W bit set to ‘0’). After the
FIGURE 6-4:
SRAM/RTCC RANDOM READ
Bus Activity
Host
SDA Line
S
T
A
R
T
Control
Byte
Bus Activity
Host
S
T
A
R
T
Address
Byte
S1 1 0 1 1 1 1 0
Control
Byte
A
C
K
P
N
O
A
C
K
A
C
K
SRAM/RTCC SEQUENTIAL READ
CONTROL
BYTE
DATA n
DATA n + 1
DATA n + 2
DS20005010J-page 36
S
T
O
P
DATA n + X
P
SDA Line
Bus Activity
S
T
O
P
Data
Byte
S 1 1 0 1 1 1 1 1
A
C
K
Bus Activity
FIGURE 6-5:
SRAM/RTCC REGISTER
SEQUENTIAL READ
Sequential reads are initiated in the same way as a
random read except that after the MCP7940N transmits the first data byte, the host issues an Acknowledge
as opposed to the Stop condition used in a random
read. This Acknowledge directs the MCP7940N to
transmit the next sequentially addressed 8-bit word
(Figure 6-5). Following the final byte transmitted to the
host, the host will NOT generate an Acknowledge but
will generate a Stop condition. To provide sequential
reads, the MCP7940N contains an internal Address
Pointer which is incremented by one at the completion
of each operation. This Address Pointer allows the
entire memory block to be serially read during one
operation.
S
T
O
P
Data
Byte
Bus Activity
6.1.4
6.1.5
A
C
K
A
C
K
A
C
K
A
C
K
N
O
A
C
K
2011-2022 Microchip Technology Inc. and its subsidiares
MCP7940N
7.0
PACKAGING INFORMATION
7.1
Package Marking Information
8-Lead MSOP
Example
XXXXXT
YWWNNN
7940NI
20113F
8-Lead PDIP (300 mil)
Example
XXXXXXXX
T/XXXNNN
YYWW
MCP7940N
I/P e313F
2201
8-Lead SOIC (3.90 mm)
Example
XXXXXXXT
XXXXYYWW
NNN
7940NI
SN e3 2201
13F
8-Lead 2x3 TDFN
XXX
YWW
NN
Example
AAV
201
13
8-Lead TSSOP
Example
XXXX
940N
TYWW
I201
NNN
13F
2011-2022 Microchip Technology Inc. and its subsidiares
DS20005010J-page 37
MCP7940N
Part Number
MCP7940N
Note 1:
Note:
DS20005010J-page 38
MSOP
PDIP
SOIC
TDFN
TSSOP
7940NT
MCP7940N
7940NT
AAV
940N
T = Temperature grade
Legend: XX...X
Y
YY
WW
NNN
*
1st Line Marking Codes
e3
Customer-specific information
Year code (last digit of calendar year)
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code
JEDEC® designator for Matte Tin (Sn)
This package is RoHs compliant. The JEDEC designator ( e3 )
can be found on the outer packaging for this package.
In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
2011-2022 Microchip Technology Inc. and its subsidiares
MCP7940N
8-Lead Plastic Micro Small Outline Package (MS) - 3x3 mm Body [MSOP]
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2X
0.20 H
D
D
2
A
D
N
E
2
E1
2
E1
E
2X
0.20 H
NOTE 1
1
2X 4 TIPS
0.25 C
2
e
B
TOP VIEW
A
8X
0.10 C
A A2
SEATING
PLANE
A1
8X b
0.25
C A-B D
C
A
SIDE VIEW
SEE DETAIL B
H
VIEW A–A
Microchip Technology Drawing C04-111-MS Rev D Sheet 1 of 2
2011-2022 Microchip Technology Inc. and its subsidiares
DS20005010J-page 39
MCP7940N
8-Lead Plastic Micro Small Outline Package (MS) - 3x3 mm Body [MSOP]
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
4X ș1
R1
H
R
c
SEATING
PLANE
C
L
ș
(L1)
4X ș1
DETAIL B
Number of Terminals
Pitch
Overall Height
Standoff
Molded Package Thickness
Overall Length
Overall Width
Molded Package Width
Terminal Width
Terminal Thickness
Terminal Length
Footprint
Lead Bend Radius
Lead Bend Radius
Foot Angle
Mold Draft Angle
Units
Dimension Limits
N
e
A
A1
A2
D
E
E1
b
c
L
L1
R
R1
ș
ș1
MIN
–
0.00
0.75
0.22
0.08
0.40
0.07
0.07
0°
5°
MILLIMETERS
NOM
8
0.65 BSC
–
–
0.85
3.00 BSC
4.90 BSC
3.00 BSC
–
–
0.60
0.95 REF
–
–
–
–
MAX
1.10
0.15
0.95
0.40
0.23
0.80
–
–
8°
15°
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or
protrusions shall not exceed 0.15mm per side.
3. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
Microchip Technology Drawing C04-111-MS Rev D Sheet 2 of 2
DS20005010J-page 40
2011-2022 Microchip Technology Inc. and its subsidiares
MCP7940N
8-Lead Plastic Micro Small Outline Package (MS) - 3x3 mm Body [MSOP]
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
GX
SILK SCREEN
C G1
Y
X
E
RECOMMENDED LAND PATTERN
Units
Dimension Limits
Contact Pitch
E
Contact Pad Spacing
C
Contact Pad Width (X8)
X
Contact Pad Length (X8)
Y
Contact Pad to Contact Pad (X4)
G1
Contact Pad to Contact Pad (X6)
GX
MIN
MILLIMETERS
NOM
0.65 BSC
4.40
MAX
0.45
1.45
2.95
0.20
Notes:
1. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
Microchip Technology Drawing C04-2111-MS Rev D
2011-2022 Microchip Technology Inc. and its subsidiares
DS20005010J-page 41
MCP7940N
8-Lead Plastic Dual In-Line (P) - 300 mil Body [PDIP]
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
D
A
N
B
E1
NOTE 1
1
2
TOP VIEW
E
C
A2
A
PLANE
L
c
A1
e
eB
8X b1
8X b
.010
C
SIDE VIEW
END VIEW
Microchip Technology Drawing No. C04-018-P Rev E Sheet 1 of 2
DS20005010J-page 42
2011-2022 Microchip Technology Inc. and its subsidiares
MCP7940N
8-Lead Plastic Dual In-Line (P) - 300 mil Body [PDIP]
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
ALTERNATE LEAD DESIGN
(NOTE 5)
DATUM A
DATUM A
b
b
e
2
e
2
e
e
Units
Dimension Limits
Number of Pins
N
e
Pitch
Top to Seating Plane
A
Molded Package Thickness
A2
Base to Seating Plane
A1
Shoulder to Shoulder Width
E
Molded Package Width
E1
Overall Length
D
Tip to Seating Plane
L
c
Lead Thickness
b1
Upper Lead Width
b
Lower Lead Width
eB
Overall Row Spacing
§
MIN
.115
.015
.290
.240
.348
.115
.008
.040
.014
-
INCHES
NOM
8
.100 BSC
.130
.310
.250
.365
.130
.010
.060
.018
-
MAX
.210
.195
.325
.280
.400
.150
.015
.070
.022
.430
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. § Significant Characteristic
3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or
protrusions shall not exceed .010" per side.
4. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
5. Lead design above seating plane may vary, based on assembly vendor.
Microchip Technology Drawing No. C04-018-P Rev E Sheet 2 of 2
2011-2022 Microchip Technology Inc. and its subsidiares
DS20005010J-page 43
MCP7940N
8-Lead Plastic Small Outline (SN) - Narrow, 3.90 mm (.150 In.) Body [SOIC]
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2X
0.10 C A–B
D
A
D
NOTE 5
N
E
2
E1
2
E1
E
2X
0.10 C A–B
2X
0.10 C A–B
NOTE 1
2
1
e
B
NX b
0.25
C A–B D
NOTE 5
TOP VIEW
0.10 C
C
A A2
SEATING
PLANE
8X
A1
SIDE VIEW
0.10 C
h
R0.13
h
R0.13
H
SEE VIEW C
VIEW A–A
0.23
L
(L1)
VIEW C
Microchip Technology Drawing No. C04-057-SN Rev F Sheet 1 of 2
DS20005010J-page 44
2011-2022 Microchip Technology Inc. and its subsidiares
MCP7940N
8-Lead Plastic Small Outline (SN) - Narrow, 3.90 mm (.150 In.) Body [SOIC]
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Units
Dimension Limits
Number of Pins
N
e
Pitch
Overall Height
A
Molded Package Thickness
A2
§
Standoff
A1
Overall Width
E
Molded Package Width
E1
Overall Length
D
Chamfer (Optional)
h
Foot Length
L
L1
Footprint
Foot Angle
c
Lead Thickness
b
Lead Width
Mold Draft Angle Top
Mold Draft Angle Bottom
MIN
1.25
0.10
0.25
0.40
0°
0.17
0.31
5°
5°
MILLIMETERS
NOM
8
1.27 BSC
6.00 BSC
3.90 BSC
4.90 BSC
1.04 REF
-
MAX
1.75
0.25
0.50
1.27
8°
0.25
0.51
15°
15°
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. § Significant Characteristic
3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or
protrusions shall not exceed 0.15mm per side.
4. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
5. Datums A & B to be determined at Datum H.
Microchip Technology Drawing No. C04-057-SN Rev F Sheet 2 of 2
2011-2022 Microchip Technology Inc. and its subsidiares
DS20005010J-page 45
MCP7940N
8-Lead Plastic Small Outline (SN) - Narrow, 3.90 mm (.150 In.) Body [SOIC]
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
SILK SCREEN
C
Y1
X1
E
RECOMMENDED LAND PATTERN
Units
Dimension Limits
E
Contact Pitch
Contact Pad Spacing
C
Contact Pad Width (X8)
X1
Contact Pad Length (X8)
Y1
MIN
MILLIMETERS
NOM
1.27 BSC
5.40
MAX
0.60
1.55
Notes:
1. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
Microchip Technology Drawing C04-2057-SN Rev F
DS20005010J-page 46
2011-2022 Microchip Technology Inc. and its subsidiares
MCP7940N
8-Lead Plastic Dual Flat, No Lead Package (MN) – 2x3x0.8 mm Body [TDFN]
With 1.4x1.3 mm Exposed Pad (JEDEC Package type WDFN)
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
D
A
B
N
(DATUM A)
(DATUM B)
E
NOTE 1
2X
0.15 C
1
2
2X
0.15 C
TOP VIEW
0.10 C
C
(A3)
A
SEATING
PLANE
8X
0.08 C
A1
SIDE VIEW
0.10
C A B
D2
L
1
2
0.10
C A B
NOTE 1
E2
K
N
8X b
e
0.10
0.05
C A B
C
BOTTOM VIEW
2011-2022 Microchip Technology Inc. and its subsidiares
DS20005010J-page 47
MCP7940N
8-Lead Plastic Dual Flat, No Lead Package (MN) – 2x3x0.8 mm Body [TDFN]
With 1.4x1.3 mm Exposed Pad (JEDEC Package type WDFN)
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Units
Dimension Limits
N
Number of Pins
e
Pitch
A
Overall Height
A1
Standoff
Contact Thickness
A3
D
Overall Length
Overall Width
E
Exposed Pad Length
D2
Exposed Pad Width
E2
b
Contact Width
L
Contact Length
Contact-to-Exposed Pad
K
MIN
0.70
0.00
1.35
1.25
0.20
0.25
0.20
MILLIMETERS
NOM
8
0.50 BSC
0.75
0.02
0.20 REF
2.00 BSC
3.00 BSC
1.40
1.30
0.25
0.30
-
MAX
0.80
0.05
1.45
1.35
0.30
0.45
-
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. Package may have one or more exposed tie bars at ends.
3. Package is saw singulated
4. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
Microchip Technology Drawing No. C04-129-MN Rev E Sheet 2 of 2
DS20005010J-page 48
2011-2022 Microchip Technology Inc. and its subsidiares
MCP7940N
8-Lead Plastic Dual Flat, No Lead Package (MN) – 2x3x0.8 mm Body [TDFN]
With 1.4x1.3 mm Exposed Pad (JEDEC Package type WDFN)
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
X2
EV
8
ØV
C
Y2
EV
Y1
1
2
SILK SCREEN
X1
E
RECOMMENDED LAND PATTERN
Units
Dimension Limits
E
Contact Pitch
Optional Center Pad Width
X2
Optional Center Pad Length
Y2
Contact Pad Spacing
C
Contact Pad Width (X8)
X1
Contact Pad Length (X8)
Y1
Thermal Via Diameter
V
Thermal Via Pitch
EV
MIN
MILLIMETERS
NOM
0.50 BSC
MAX
1.60
1.50
2.90
0.25
0.85
0.30
1.00
Notes:
1. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
2. For best soldering results, thermal vias, if used, should be filled or tented to avoid solder loss during
reflow process
Microchip Technology Drawing No. C04-129-MN Rev. B
2011-2022 Microchip Technology Inc. and its subsidiares
DS20005010J-page 49
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