MCP795W1X/MCP795W2X
Battery-Backed SPI Real-Time Clock/Calendar with Enhanced Features
Device Selection Table
User Memory
Part Number
EEPROM
(Kbits)
Protected
EEPROM
MCP795W10
1
Blank
MCP795W20
2
Blank
MCP795W11
1
EUI-48™
MCP795W21
2
EUI-48™
MCP795W12
1
EUI-64™
MCP795W22
2
EUI-64™
• 64-Byte Battery-Backed SRAM
• 1 Kbit or 2 Kbit EEPROM:
- Software write-protect
- Page write up to 8 bytes
- Endurance: 1M erase/write cycles
• 128-Bit Protected EEPROM Area:
- Robust write unlock sequence
- EUI-48™ MAC address (MCP795WX1)
- EUI-64™ MAC address (MCP795WX2)
Timekeeping Features
• Real-Time Clock/Calendar (RTCC):
- Hours, minutes, seconds, hundredth of
seconds, day of week, date, month, year
- Leap year compensated to 2399
- 12/24-hour modes
• Oscillator for 32.768 kHz Crystals:
- Optimized for 6-9 pF crystals
• On-Chip Digital Trimming/Calibration:
- ±1 ppm resolution
- ±259 ppm range
• Dual Programmable Alarms
• Clock Output Function with Selectable Frequency
• Power-Fail Timestamp:
- Time logged on switchover to and from Battery
mode
Low-Power Features
• Wide Voltage Range:
- Operating voltage range of 1.8V to 3.6V
- Backup voltage range of 1.3V to 3.6V
• Low Typical Timekeeping Current:
- Operating from VCC: 1.2 µA at 3.0V
- Operating from VBAT: 1.0 µA at 3.0V
• Automatic Switchover to Battery Backup
Operating Ranges
• SPI Serial Interface:
- SPI clock rate up to 5 MHz
• Temperature Range:
- Industrial (I): -40°C to +85°C
Packages
• 14-Lead SOIC and TSSOP
Package Types (not to scale)
SOIC/TSSOP
X1
1
14 VCC
X2
2
13 CLKOUT
VBAT
3
12 EVHS
WDO 4
11 EVLS
IRQ
5
10 SCK
CS 6
9
SI
VSS 7
8
SO
Enhanced Features
• Programmable Watchdog Timer:
- Dedicated output pin
- Cleared via SPI bus or EVHS input
• Dual Configurable Event Detect Modules:
- High-Speed Digital Event Detect for programmable pulse count detection
- Low-Speed Event Detect for programmable
switch debouncing
2011-2018 Microchip Technology Inc.
DS20002280E-page 1
MCP795W1X/MCP795W2X
Description
The
MCP795WX1
and
MCP795WX2
are
preprogrammed with EUI-48 and EUI-64 addresses,
respectively. Custom programming is also available.
The MCP795WXX Real-Time Clock/Calendar (RTCC)
tracks time using internal counters for hours, minutes,
seconds, hundredth of seconds, days, months, years
and day of week. Alarms can be configured on all
counters up to and including months. For usage and
configuration, the MCP795WXX supports SPI
communications up to 5 MHz.
Two event detect modules are included on the
MCP795WXX. The high-speed event detect module
will generate an interrupt after a programmable
number of pulses have been detected. The low-speed
event detect module can be used to debounce
mechanical switches and includes a selectable
debounce period.
The MCP795WXX is designed to operate using a
32.768 kHz tuning fork crystal with external crystal
load capacitors. On-chip digital trimming can be used
to adjust for frequency variance caused by crystal
tolerance and temperature.
The MCP795WXX also features an integrated
Watchdog Timer peripheral. This allows applications to
improve system robustness by moving this
functionality outside of the microcontroller.
SRAM and timekeeping circuitry are powered from the
backup supply when main power is lost, allowing the
device to maintain accurate time and the SRAM
contents. The times when the device switches over to
the backup supply and when primary power returns
are both logged by the power-fail timestamp.
The MCP795WXX has versatile output options. There
is a dedicated pin for outputting a selectable frequency
square wave or for use as a general purpose output.
Additionally, the alarms can be assigned to either the
Watchdog Timer interrupt output or the event detect
interrupt output.
The MCP795WXX features 128 bits of EEPROM
which is only writable after an unlock sequence,
making it ideal for storing a unique ID or other critical
information.
FIGURE 1-1:
TYPICAL APPLICATION SCHEMATIC
VCC
VCC
VCC
14
VCC
6
10
9
PIC® MCU
8
MCLR
4
5
13
CS
SCK
SI
X2
VBAT
MCP795WXX
CX1
1
2
32.768 KHZ
X1
CX2
3
VBAT
SO
WDO
IRQ
EVHS
CLKOUT
EVLS
12
11
EVHS
EVLS
VSS
7
2011-2018 Microchip Technology Inc.
DS20002280E-page 2
MCP795W1X/MCP795W2X
FIGURE 1-2:
BLOCK DIAGRAM
VCC
VSS
Power Control
and Switchover
Power-Fail
Timestamp
VBAT
CS
SCK
SI
Control Logic
Configuration
SPI Interface
and Addressing
Hundredth of
Seconds
SO
SRAM
EEPROM
Seconds
X1
32.768 kHz
Oscillator
Clock Divider
Minutes
X2
Hours
Digital Trimming
Day of Week
CLKOUT
Square Wave
Output
Date
Watchdog
Timer
WDT
Output Logic
WDO
Month
Year
Alarms
EVHS
EVLS
2011-2018 Microchip Technology Inc.
Event
Detect
Interrupt
Output Logic
IRQ
DS20002280E-page 3
MCP795W1X/MCP795W2X
1.0
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings (†)
VCC.............................................................................................................................................................................6.5V
All inputs and outputs w.r.t. VSS ...........................................................................................................-0.6V to VCC+1.0V
Storage temperature ...............................................................................................................................-65°C to +150°C
Ambient temperature under bias............................................................................................................... -40°C to +85°C
ESD protection on all pins.......................................................................................................................................... 4 kV
† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions above those
indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability.
TABLE 1-1:
DC CHARACTERISTICS
Electrical Characteristics:
Industrial (I):
TA = -40°C to +85°C
DC CHARACTERISTICS
Param.
No.
Sym.
Characteristic
Min.
Typ.(2)
Max.
Units
VCC = 1.8V to 3.6V
Test Conditions
D1
VIH
High-Level Input Voltage
0.7 VCC
—
VCC + 1
V
D2
VIL
Low-Level Input Voltage
-0.3
—
0.3VCC
V
VCC2.5V
-0.3
—
0.2VCC
D3
VOL
Low-Level Output Voltage
—
—
0.4
V
IOL = 2.1 mA, VCC 2.5V
—
—
0.2
VCC - 0.5
—
—
V
IOH = -400 µA
High-Level Output Voltage
VCC < 2.5V
IOL = 1.0 mA, VCC < 2.5V
D4
VOH
D5
ILI
Input Leakage Current
—
—
±1
µA
CS = VCC, VIN = VSS or
VCC
D6
ILO
Output Leakage Current
—
—
±1
µA
CS = VCC, VOUT = VSS or
VCC
D7
CINT
Pin Capacitance
(all inputs and outputs)
—
—
7
pF
VCC = 3.6V (Note 1)
TA = 25°C, f = 1 MHz
D8
COSC
Oscillator Pin Capacitance
(X1, X2 pins)
—
3
—
pF
Note 1
D9
ICCEERD
EEPROM Operating Current
—
—
3
mA
VCC = 3.6V, FCLK = 5 MHz
SO = Open
5
mA
VCC = 3.6V
3
mA
VCC = 3.6V, FCLK = 5 MHz
SO = Open
3
mA
VCC = 3.6V, FCLK = 5 MHz
1
µA
VCC = 3.6V
ICCEEWR
D10
ICCREAD
SRAM/RTCC Operating
Current
—
—
ICCWRITE
D11
ICCDAT
Vcc Data Retention Current
(oscillator off)
—
—
Note 1: This parameter is not tested but ensured by characterization.
2: Typical measurements taken at room temperature.
2011-2018 Microchip Technology Inc.
DS20002280E-page 4
MCP795W1X/MCP795W2X
DC CHARACTERISTICS (Continued)
Param.
No.
Sym.
D12
ICCT
Characteristic
Timekeeping Current
Electrical Characteristics:
Industrial (I):
TA = -40°C to +85°C
VCC = 1.8V to 3.6V
Min.
Typ.(2)
Max.
Units
Test Conditions
—
—
1.2
µA
VCC = 1.8V, CS = VCC,
EVHS = VSS, EVLS = VSS
(Note 1)
—
1.2
1.8
µA
VCC = 3.0V, CS = VCC,
EVHS = VSS, EVLS = VSS
(Note 1)
—
—
2.6
µA
VCC = 3.6V, CS = VCC,
EVHS = VSS, EVLS = VSS
(Note 1)
D13
VTRIP
Power-Fail Switchover
Voltage
1.3
1.5
1.7
V
D14
VBAT
Backup Supply Voltage
Range
1.3
—
3.6
V
D15
IBATT
Timekeeping Backup Current
—
—
850
nA
VBAT = 1.3V, VCC = VSS
(Note 1)
—
1000
1200
nA
VBAT = 3.0V, VCC = VSS
(Note 1)
—
—
2300
nA
VBAT = 3.6V, VCC = VSS
(Note 1)
—
—
850
nA
VBAT = 3.6V, VCC = VSS
D16
IBATDAT
VBAT Data-Retention Current
(oscillator off)
Note 1: This parameter is not tested but ensured by characterization.
2: Typical measurements taken at room temperature.
2011-2018 Microchip Technology Inc.
DS20002280E-page 5
MCP795W1X/MCP795W2X
TABLE 1-2:
AC CHARACTERISTICS
Electrical Characteristics:
Industrial (I):
TA = -40°C to +85°C
AC CHARACTERISTICS
VCC = 1.8V to 3.6V
Param.
No.
Sym.
1
FCLK
Clock Frequency
—
2
TCSS
CS Setup Time
100
150
—
—
ns
1.8V Vcc 2.5V
3
TCSH
CS Hold Time
100
—
—
ns
2.5V Vcc 3.6V
1.8V Vcc 2.5V
4
TCSD
CS Disable Time
5
TSU
Data Setup Time
6
THD
Characteristic
Data Hold Time
Min.
Typ.
Max.
Units
—
—
5
MHz
—
3
MHz
1.8V Vcc 2.5V
—
—
ns
2.5V Vcc 3.6V
150
—
—
ns
50
—
—
ns
Test Conditions
2.5V Vcc 3.6V
20
—
—
ns
2.5V Vcc 3.6V
30
—
—
ns
1.8V Vcc 2.5V
40
—
—
ns
2.5V Vcc 3.6V
50
—
—
ns
1.8V Vcc 2.5V
7
TR
SCK Rise Time
—
—
100
ns
Note 1
8
TF
SCK Fall Time
—
—
100
ns
Note 1
9
THI
Clock High Time
10
TLO
Clock Low Time
100
—
—
ns
2.5V Vcc 3.6V
150
—
—
ns
1.8V Vcc 2.5V
100
—
—
ns
2.5V Vcc 3.6V
150
—
—
ns
1.8V Vcc 2.5V
11
TCLD
Clock Delay Time
50
—
—
ns
12
TCLE
Clock Enable Time
50
—
—
ns
13
TV
Output Valid from Clock
Low
—
—
100
ns
2.5V Vcc 3.6V
—
—
160
ns
1.8V Vcc 2.5V
14
THO
Output Hold Time
0
—
ns
Note 1
15
TDIS
Output Disable Time
—
—
80
ns
2.5V Vcc 3.6V (Note 1)
—
—
160
ns
1.8V Vcc 2.5V (Note 1)
16
TWC
Internal Write Cycle Time
—
—
5
ms
Note 2
17
TFVCC
VCC Fall Time
300
—
—
µs
Note 1
18
TRVCC
VCC Rise Time
0
—
—
µs
Note 1
19
FOSC
Oscillator Frequency
—
32.768
—
kHz
20
TOSF
Oscillator Timeout Period
—
1
—
ms
Endurance
1M
—
—
21
Note 1
E/W Page Mode, 25°C
cycles VCC = 3.6V (Note 1
Note 1: This parameter is not tested but ensured by characterization.
2: TWC begins on the rising edge of CS after a valid write sequence and ends when the internal write cycle
is complete.
2011-2018 Microchip Technology Inc.
DS20002280E-page 6
MCP795W1X/MCP795W2X
FIGURE 1-1:
SERIAL INPUT TIMING
4
CS
12
2
7
10
SCK
8
6
MSB In
LSB In
High-Impedance
SO
FIGURE 1-2:
3
9
5
SI
11
SERIAL OUTPUT TIMING
CS
9
3
10
SCK
13
14
MSB Out
SO
15
LSB Out
Don’t Care
SI
FIGURE 1-3:
POWER SUPPLY TRANSITION TIMING
VCC
VTRIP(MAX)
VTRIP(MIN)
17
2011-2018 Microchip Technology Inc.
18
DS20002280E-page 7
MCP795W1X/MCP795W2X
2.0
TYPICAL PERFORMANCE CURVES
Note:
The graphs and tables provided following this note are a statistical summary based on a limited number of
samples and are provided for informational purposes only. The performance characteristics listed herein
are not tested or guaranteed. In some graphs or tables, the data represented may be outside the specified
operating range (e.g., outside specified power supply range) and therefore, outside the warranted range.
FIGURE 2-1:
TIMEKEEPING BACKUP
CURRENT VS. BACKUP
SUPPLY VOLTAGE
FIGURE 2-2:
1.8
1.6
1.2
TA = -40°C
TA = 25°C
TA = 85°C
1.6
Ͳ40
25
85
1.0
0.8
0.6
0.4
ICCT Current (µA)
IBATT Current (µA)
1.4
TIMEKEEPING CURRENT
VS. SUPPLY VOLTAGE
1.4
1.2
25
85
1.0
0.8
0.6
0.4
0.2
0.2
0.0
1.30 1.60 1.90 2.20 2.50 2.80 3.10 3.40
VBAT Voltage (V)
0.0
1.80
2011-2018 Microchip Technology Inc.
TA = -40°C
TA = 25°C
TA = 85°C
Ͳ40
2.10
2.40
2.70
3.00
VCC Voltage (V)
3.30
3.60
DS20002280E-page 8
MCP795W1X/MCP795W2X
3.0
PIN DESCRIPTIONS
The descriptions of the pins are listed in Table 3-1.
TABLE 3-1:
PIN FUNCTION TABLE
14-pin
SOIC
14-pin
TSSOP
X1
X2
VBAT
1
2
3
1
2
3
Quartz Crystal Input, External Oscillator Input
Quartz Crystal Output
Battery Backup Supply Input
WDO
4
4
Watchdog Output
IRQ
5
5
Interrupt Output
CS
VSS
SO
SI
SCK
EVHS
EVLS
CLKOUT
VCC
6
7
8
9
10
11
12
13
14
6
7
8
9
10
11
12
13
14
Chip Select Input
Ground
Serial Data Output
Serial Data Input
Serial Clock Input
High-Speed Event Detect Input
Low-Speed Event Detect Input
Square Wave Clock Output
Primary Power Supply
Name
3.1
Pin Function
Chip Select (CS)
A low level on this pin selects the device, whereas a
high level deselects the device. A nonvolatile memory
programming cycle which is already initiated or in
progress will be completed, regardless of the CS input
signal. When the device is deselected, SO goes into
the high-impedance state, allowing multiple parts to
share the same SPI bus. After power-up, a high-to-low
transition on CS is required prior to any sequence
being initiated.
3.2
Serial Clock (SCK)
This pin is used to synchronize the communication
between a master and the MCP795WXX. Instructions,
addresses or data present on the SI pin are latched on
the rising edge of the clock input, while data on the SO
pin is updated after the falling edge of the clock input.
3.3
Serial Input (SI)
3.5
Oscillator Input/Output (X1, X2)
These pins are used as the connections for an external
32.768 kHz quartz crystal and load capacitors. X1 is the
crystal oscillator input and X2 is the output. The
MCP795WXX is designed to allow for the use of
external load capacitors in order to provide additional
flexibility when choosing external crystals. The
MCP795WXX is optimized for crystals with a specified
load capacitance of 6-9 pF.
X1 also serves as the external clock input when the
MCP795WXX is configured to use an external oscillator.
3.6
Watchdog Output (WDO)
This is an output pin for the Watchdog Timer and,
optionally, the alarms. During normal operation, the pin
remains high. If a Watchdog Timer overflow occurs, the
pin outputs a low pulse. The width of the pulse is
user-selectable.
This pin is used to transfer data into the device. It
receives instructions, addresses and data. Data is
latched on the rising edge of the serial clock.
If an alarm output is assigned to the WDO pin, then the
pin will output a low pulse when the alarm triggers.
3.4
The WDO pin is an open-drain output and requires a
pull-up resistor to VCC (typically 10 k). This pin may
be left floating if not used.
Serial Output (SO)
This pin is used to transfer data out of the
MCP795WXX. During a read cycle, data is shifted out
on this pin after the falling edge of the serial clock.
2011-2018 Microchip Technology Inc.
DS20002280E-page 9
MCP795W1X/MCP795W2X
3.7
Interrupt Output (IRQ)
This is an output pin for the event detect modules and,
optionally, the alarms. If an event is detected by either
module, then this pin will output a low signal until the
interrupt flag has been cleared.
If an alarm output is assigned to the IRQ pin, then the
pin will output a low signal when the alarm triggers. The
pin will remain low until the alarm interrupt flag has
been cleared.
The IRQ pin is an open-drain output and requires a
pull-up resistor to VCC or VBAT (typically 10 k). This
pin may be left floating if not used.
3.8
Square Wave Clock Output
(CLKOUT)
This is the output pin for the square wave output
function. This pin may be left floating if not used.
3.9
High-Speed Event Detect Input
(EVHS)
This pin is used as the input for the high-speed event
detect module.
If the high-speed event detect module is not being
used, the EVHS pin should be connected to VCC or
VSS.
3.10
Low-Speed Event Detect Input
(EVLS)
This pin is used as the input for the low-speed event
detect module.
If the low-speed event detect module is not being used,
the EVLS pin should be connected to VCC or VSS.
3.11
Backup Supply (VBAT)
This is the input for a backup supply to maintain the
RTCC and SRAM registers during the time when VCC
is unavailable.
Power should be applied to VCC before VBAT.
If the battery backup feature is not being used, the
VBAT pin should be connected to VSS.
2011-2018 Microchip Technology Inc.
DS20002280E-page 10
MCP795W1X/MCP795W2X
4.0
SPI BUS OPERATION
The MCP795WXX is designed to interface directly with
the Serial Peripheral Interface (SPI) port of many of
today’s popular microcontroller families, including
Microchip’s PIC® microcontrollers. It may also interface
with microcontrollers that do not have a built-in SPI port
by using discrete I/O lines programmed properly in
software to match the SPI protocol.
TABLE 4-1:
The MCP795WXX contains an 8-bit instruction register.
The device is accessed via the SI pin, with data being
clocked in on the rising edge of SCK. The CS pin must
be low for the entire operation.
Table 4-1 contains a list of the possible instruction
bytes and format for device operation. All instructions,
addresses, and data are transferred MSb first, LSb last.
Data (SI) is sampled on the first rising edge of SCK
after CS goes low.
INSTRUCTION SET SUMMARY
Instruction Name Instruction Format
Description
EEREAD
0000 0011
Read data from EEPROM array beginning at selected address
EEWRITE
0000 0010
Write data to EEPROM array beginning at selected address
EEWRDI
0000 0100
Reset the write enable latch (disable write operations)
EEWREN
0000 0110
Set the write enable latch (enable write operations)
SRREAD
0000 0101
Read STATUS register
SRWRITE
0000 0001
Write STATUS register
READ
0001 0011
Read data from RTCC/SRAM array beginning at selected address
WRITE
0001 0010
Write data to RTCC/SRAM array beginning at selected address
UNLOCK
0001 0100
Unlock the protected EEPROM block for a write operation
IDWRITE
0011 0010
Write data to the protected EEPROM block beginning at selected address
IDREAD
0011 0011
Read data from the protected EEPROM block beginning at the selected
address
CLRWDT
0100 0100
Clear Watchdog Timer
CLRRAM
0101 0100
Clear all SRAM data to ‘0’
2011-2018 Microchip Technology Inc.
DS20002280E-page 11
MCP795W1X/MCP795W2X
5.0
FUNCTIONAL DESCRIPTION
The MCP795WXX is a highly-integrated Real-Time
Clock/Calendar (RTCC). Using an on-board,
low-power oscillator, the current time is maintained in
hundredths of seconds, seconds, minutes, hours, day
of week, date, month, and year. The MCP795WXX also
features 64 bytes of general purpose SRAM, either
2 Kbits (MCP795W2X) or 1 Kbit (MCP795W1X) of
EEPROM, and 16 bytes of protected EEPROM. Two
alarm modules allow interrupts to be generated at
specific times with flexible comparison options. Digital
trimming can be used to compensate for inaccuracies
inherent with crystals. Using the backup supply input
and an integrated power switch, the MCP795WXX will
automatically switch to backup power when primary
power is unavailable, allowing the current time and the
SRAM contents to be maintained. The timestamp
module captures the time when primary power is lost
and when it is restored. The Watchdog Timer module
can be used to reset an application that has become
unresponsive. The high-speed event detect module
can be used to detect pulse signals recovered from
communication links, while the low-speed event detect
module can be used to debounce switches and detect
button presses.
5.1
Memory Organization
The MCP795WXX features four different blocks of
memory: the RTCC registers, general purpose SRAM,
2 Kbit EEPROM (1 Kbit for the MCP795W1X) with
software write-protect, and protected EEPROM. The
RTCC registers and SRAM share the same address
space and are accessed through the READ and WRITE
instructions. The EEPROM region is accessed using
the EEREAD and EEWRITE instructions, and the
protected EEPROM is accessed using the IDREAD and
IDWRITE instructions. Unused locations are not
accessible. The MCP795WXX will not respond if the
address is out of range, as shown in the shaded region
of the memory maps in Figure 5-1 and Figure 5-2.
The RTCC registers are contained in addresses
0x00-0x1F. Table 5-1 shows the detailed RTCC
register map. There are 64 bytes of user-accessible
SRAM, located in the address range 0x20-0x5F. The
SRAM is a separate block from the RTCC registers. All
RTCC registers and SRAM locations are maintained
while operating from backup power.
The RTCC configuration and STATUS registers are
used to access all of the modules featured on the
MCP795WXX.
FIGURE 5-1:
MEMORY MAP FOR MCP795W1X
RTCC Registers/SRAM
EEPROM
0x00
0x00
Time and Date
0x07
0x08
0x0B
0x0C
EEPROM (128 Bytes)
Configuration and Trimming
Alarm 0
0x7F
0x80
0x11
0x12
Alarm 1
0x17
0x18
Unimplemented; mapped back to 0x00-0x7F
Power-Fail/Power-Up Timestamps
0x1F
0x20
0xFF
SRAM (64 Bytes)
Protected EEPROM
0x5F
0x60
0x00
Protected EEPROM (16 Bytes)
EUI-48/EUI-64 Node Address
Unimplemented; device does not respond
0x0F
0x10
Unimplemented; device does not respond
0xFF
2011-2018 Microchip Technology Inc.
0xFF
DS20002280E-page 12
MCP795W1X/MCP795W2X
FIGURE 5-2:
MEMORY MAP FOR MCP795W2X
RTCC Registers/SRAM
EEPROM
0x00
0x00
Time and Date
0x07
0x08
0x0B
0x0C
Configuration and Trimming
Alarm 0
0x11
0x12
EEPROM (256 Bytes)
Alarm 1
0x17
0x18
Power-Fail/Power-Up Timestamps
0x1F
0x20
0xFF
SRAM (64 Bytes)
Protected EEPROM
0x5F
0x60
0x00
Protected EEPROM (16 Bytes)
EUI-48/EUI-64 Node Address
Unimplemented; device does not respond
0x0F
0x10
Unimplemented; device does not respond
0xFF
2011-2018 Microchip Technology Inc.
0xFF
DS20002280E-page 13
MCP795W1X/MCP795W2X
TABLE 5-1:
DETAILED RTCC REGISTER MAP
Addr. Register Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Section 5.3 “Timekeeping”
00h
RTCHSEC
01h
RTCSEC
HSECTEN3 HSECTEN2
ST
SECTEN2
HSECTEN1
SECTEN1
HSECTEN0 HSECONE3 HSECONE2 HSECONE1 HSECONE0
SECTEN0
SECONE3
SECONE2
SECONE1
SECONE0
02h
RTCMIN
—
MINTEN2
MINTEN1
MINTEN0
MINONE3
MINONE2
MINONE1
MINONE0
03h
RTCHOUR
TRIMSIGN
12/24
AM/PM
HRTEN1
HRTEN0
HRONE3
HRONE2
HRONE1
HRONE0
04h
RTCWKDAY
—
—
OSCRUN
PWRFAIL
VBATEN
WKDAY2
WKDAY1
WKDAY0
05h
RTCDATE
—
—
DATETEN1
DATETEN0
DATEONE3
DATEONE2
DATEONE1
DATEONE0
06h
RTCMTH
—
—
LPYR
MTHTEN0
MTHONE3
MTHONE2
MTHONE1
MTHONE0
07h
RTCYEAR
YRTEN3
YRTEN2
YRTEN1
YRTEN0
YRONE3
YRONE2
YRONE1
YRONE0
08h
CONTROL
OUT
SQWEN
ALM1EN
ALM0EN
EXTOSC
CRSTRIM
SQWFS1
SQWFS0
09h
OSCTRIM
TRIMVAL7
TRIMVAL6
TRIMVAL5
TRIMVAL4
TRIMVAL3
TRIMVAL2
TRIMVAL1
TRIMVAL0
0Ah
WDTCON
WDTEN
WDTIF
WDTPS2
WDTPS1
WDTPS0
0Bh
EVDTCON
EVHIF
EVLIF
EVWDTEN
EVLPS
EVHCS1
EVHCS0
Section 5.5 “Watchdog Timer”
WDTDLYEN
WDTPWS
WDTPS3
Section 5.6 “Event Detection”
EVHEN
EVLEN
Section 5.4 “Alarms”
0Ch
ALM0SEC
—
SECTEN2
SECTEN1
SECTEN0
SECONE3
SECONE2
SECONE1
SECONE0
0Dh
ALM0MIN
—
MINTEN2
MINTEN1
MINTEN0
MINONE3
MINONE2
MINONE1
MINONE0
—
12/24(2)
AM/PM
HRTEN1
HRTEN0
HRONE3
HRONE2
HRONE1
HRONE0
ALM0PIN
ALM0MSK2
ALM0MSK1
ALM0MSK0
ALM0IF
WKDAY2
WKDAY1
WKDAY0
0Eh
ALM0HOUR
0Fh
ALM0WKDAY
10h
ALM0DATE
—
—
DATETEN1
DATETEN0
DATEONE3
DATEONE2
DATEONE1
DATEONE0
11h
ALM0MTH
—
—
—
MTHTEN0
MTHONE3
MTHONE2
MTHONE1
MTHONE0
12h
ALM1HSEC
13h
ALM1SEC
—
SECTEN2
SECTEN1
SECTEN0
SECONE3
SECONE2
SECONE1
SECONE0
14h
ALM1MIN
—
MINTEN2
MINTEN1
MINTEN0
MINONE3
MINONE2
MINONE1
MINONE0
15h
ALM1HOUR
—
12/24(2)
AM/PM
HRTEN1
HRTEN0
HRONE3
HRONE2
HRONE1
HRONE0
16h
ALM1WKDAY
ALM1PIN
ALM1MSK2
ALM1MSK1
ALM1MSK0
ALM1IF
WKDAY2
WKDAY1
WKDAY0
17h
ALM1DATE
—
—
DATETEN1
DATETEN0
DATEONE3
DATEONE2
DATEONE1
DATEONE0
Section 5.4 “Alarms”
HSECTEN3 HSECTEN2
HSECTEN1
HSECTEN0 HSECONE3 HSECONE2 HSECONE1 HSECONE0
Section 5.10.1 “Power-Fail Timestamp”
Power-Down Timestamp
18h
PWRDNMIN
—
MINTEN2
MINTEN1
MINTEN0
MINONE3
MINONE2
MINONE1
MINONE0
19h
PWRDNHOUR
—
12/24
AM/PM
HRTEN1
HRTEN0
HRONE3
HRONE2
HRONE1
HRONE0
1Ah
PWRDNDATE
—
—
DATETEN1
DATETEN0
DATEONE3
DATEONE2
DATEONE1
DATEONE0
1Bh
PWRDNMTH
WKDAY2
WKDAY1
WKDAY0
MTHTEN0
MTHONE3
MTHONE2
MTHONE1
MTHONE0
1Ch
PWRUPMIN
—
MINTEN2
MINTEN1
MINTEN0
MINONE3
MINONE2
MINONE1
MINONE0
1Dh
PWRUPHOUR
—
12/24
AM/PM
HRTEN1
HRTEN0
HRONE3
HRONE2
HRONE1
HRONE0
1Eh
PWRUPDATE
—
—
DATETEN1
DATETEN0
DATEONE3
DATEONE2
DATEONE1
DATEONE0
1Fh
PWRUPMTH
WKDAY2
WKDAY1
WKDAY0
MTHTEN0
MTHONE3
MTHONE2
MTHONE1
MTHONE0
Power-Up Timestamp
Note 1:
2:
Grey areas are unimplemented.
The 12/24 bits in the ALMxHOUR registers are read-only and reflect the value of the 12/24 bit in the RTCHOUR register.
2011-2018 Microchip Technology Inc.
DS20002280E-page 14
MCP795W1X/MCP795W2X
5.2
Oscillator Configurations
EQUATION 5-1:
The MCP795WXX can be operated in two different
oscillator configurations: using an external crystal or
using an external clock input.
5.2.1
By using external load capacitors, the MCP795WXX
allows for a wide selection of crystals. Suitable crystals
have a load capacitance (CL) of 6-9 pF. Crystals with a
load capacitance of 12.5 pF are not recommended.
Figure 5-3 shows the pin connections when using an
external crystal.
FIGURE 5-3:
CRYSTAL OPERATION
MCP795WXX
X1
CX 1
To Internal
Logic
Quartz
Crystal
CX 2
ST
X2
Note 1: The ST bit must be set to enable the
crystal oscillator circuit.
2: Always verify oscillator performance over
the voltage and temperature range that is
expected for the application.
5.2.1.1
Choosing Load Capacitors
CL is the effective load capacitance as seen by the
crystal, and includes the physical load capacitors, pin
capacitance, and stray board capacitance. Equation 5-1
can be used to calculate CL.
CX1 and CX2 are the external load capacitors. They
must be chosen to match the selected crystal’s
specified load capacitance.
Note:
C X1 C X2
C L = -------------------------- + C STRAY
CX1 + CX2
EXTERNAL CRYSTAL
The crystal oscillator circuit on the MCP795WXX is
designed to operate with a standard 32.768 kHz tuning
fork crystal and matching external load capacitors.
LOAD CAPACITANCE
CALCULATION
Where:
C L = Effective load capacitance
C X1 = Capacitor value on X1 + C OSC
C X2 = Capacitor value on X2 + C OSC
C STRAY = PCB stray capacitance
5.2.1.2
Layout Considerations
The oscillator circuit should be placed on the same
side of the board as the device. Place the oscillator
circuit close to the respective oscillator pins. The load
capacitors should be placed next to the oscillator
itself, on the same side of the board.
Use a grounded copper pour around the oscillator
circuit to isolate it from surrounding circuits. The
grounded copper pour should be routed directly to VSS.
Do not run any signal traces or power traces inside the
ground pour. Also, if using a two-sided board, avoid any
traces on the other side of the board where the crystal
is placed.
Layout suggestions are shown in Figure 5-4. In-line
packages may be handled with a single-sided layout
that completely encompasses the oscillator pins. With
fine-pitch packages, it is not always possible to
completely surround the pins and components. A
suitable solution is to tie the broken guard sections to a
mirrored ground layer. In all cases, the guard trace(s)
must be returned to ground.
For additional information and design guidance on
oscillator circuits, please refer to these Microchip
Application Notes, available at the corporate website
(www.microchip.com):
• AN1365, “Recommended Usage of Microchip
Serial RTCC Devices”
• AN1519, “Recommended Crystals for Microchip
Stand-Alone Real-Time Clock Calendar Devices”
If the load capacitance is not correctly
matched to the chosen crystal’s specified
value, the crystal may give a frequency
outside of the crystal manufacturer’s
specifications.
2011-2018 Microchip Technology Inc.
DS20002280E-page 15
MCP795W1X/MCP795W2X
FIGURE 5-4:
SUGGESTED PLACEMENT OF THE OSCILLATOR CIRCUIT
Single-Sided and In-line Layouts:
Copper Pour
(tied to ground)
Fine-Pitch (Dual-Sided) Layouts:
Oscillator
Crystal
Top Layer Copper Pour
(tied to ground)
Bottom Layer
Copper Pour
(tied to ground)
X1
X1
CX1
CX1
X2
GND
CX2
Oscillator
Crystal
GND
CX2
`
X2
DEVICE PINS
DEVICE PINS
5.2.2
5.2.3
EXTERNAL CLOCK INPUT
A 32.768 kHz external clock source can be connected
to the X1 pin (Figure 5-5). When using this
configuration, the X2 pin should be left floating.
Note:
The EXTOSC bit must be set to enable an
external clock source.
FIGURE 5-5:
EXTERNAL CLOCK INPUT
OPERATION
FIGURE 5-6:
The MCP795WXX features an oscillator failure flag,
OSCRUN, that indicates whether or not the oscillator is
running. The OSCRUN bit is automatically set after 32
oscillator cycles are detected. If no oscillator cycles are
detected for more than TOSF, then the OSCRUN bit is
automatically cleared (Figure 5-6). This can occur if the
oscillator is stopped by clearing the ST bit or due to
oscillator failure.
MCP795WXX
X1
Clock from
Ext. Source
OSCILLATOR FAILURE STATUS
OSCILLATOR FAILURE STATUS TIMING DIAGRAM
X1
32 Clock Cycles
TOSF
< TOSF
OSCRUN Bit
TABLE 5-2:
Name
RTCSEC
RTCWKDAY
CONTROL
Legend:
SUMMARY OF REGISTERS ASSOCIATED WITH OSCILLATOR CONFIGURATION
Bit 1
Bit 0
Register
on Page
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
ST
SECTEN2
SECTEN1
SECTEN0
SECONE3
SECONE2
—
—
OSCRUN
PWRFAIL
VBATEN
WKDAY2
WKDAY1
WKDAY0
20
OUT
SQWEN
ALM1EN
ALM0EN
EXTOSC
CRSTRIM
SQWFS1
SQWFS0
35
SECONE1 SECONE0
18
— = unimplemented location, read as ‘0’. Shaded cells are not used by oscillator configuration.
2011-2018 Microchip Technology Inc.
DS20002280E-page 16
MCP795W1X/MCP795W2X
5.3
Timekeeping
The MCP795WXX maintains the current time and date
using an external 32.768 kHz crystal or clock source.
Separate registers are used for tracking hundredths of
seconds, seconds, minutes, hours, day of week, date,
month, and year. The MCP795WXX automatically
adjusts for months with less than 31 days and
compensates for leap years from 2001 to 2399. The
year is stored as a two-digit value.
Both 12-hour and 24-hour time formats are supported
and are selected using the 12/24 bit.
The day of week value counts from 1 to 7, increments
at midnight, and the representation is user-defined (i.e.,
the MCP795WXX does not require 1 to equal Sunday,
etc.).
All time and date values are stored in the registers as
binary-coded
decimal
(BCD)
values.
The
MCP795WXX will continue to maintain the time and
date while operating off the backup supply.
When reading from the timekeeping registers, the
registers are buffered to prevent errors due to rollover
of counters. The following events cause the buffers to
be updated:
• When a read is initiated from the RTCC registers
(addresses 0x00 to 0x1F)
• During an RTCC register read operation, when
the register address rolls over from 0x1F to 0x00
The timekeeping registers should be read in a single
operation to utilize the on-board buffers and avoid
rollover issues.
Note 1: Loading invalid values into the time and
date registers will result in undefined
operation.
2: To avoid rollover issues when loading
new time and date values, the
oscillator/clock input should be disabled
by clearing the ST bit for External Crystal
mode and the EXTOSC bit for External
Clock Input mode. After waiting for the
OSCRUN bit to clear, the new values can
be loaded and the ST or EXTOSC bit can
then be re-enabled.
5.3.1
DIGIT CARRY RULES
The following list explains which timer values cause a
digit carry when there is a rollover:
• Time of day: from 11:59:59.99 PM to 12:00:00.00
AM (12-hour mode) or 23:59:59.99 to 00:00:00.00
(24-hour mode), with a carry to the Date and
Weekday fields
• Date: carries to the Month field according to
Table 5-3
• Weekday: from 7 to 1 with no carry
• Month: from 12/31 to 01/01 with a carry to the
Year field
• Year: from 99 to 00 with no carry
TABLE 5-3:
DAY TO MONTH ROLLOVER
SCHEDULE
Month
Name
Maximum Date
01
January
31
02
February
28 or 29(1)
03
March
31
04
April
30
05
May
31
06
June
30
07
July
31
08
August
31
09
September
30
10
October
31
11
November
30
December
31
12
Note 1:
5.3.2
29 during leap years, otherwise 28.
GENERATING HUNDREDTH OF
SECONDS
A special algorithm is required to accurately generate
hundredth of seconds. The circuitry utilizes the
4.096 kHz clock signal and counts 41 clock pulses
each for 24 increments of the hundredth of seconds
count. The circuitry then counts 40 clock pulses for the
next increment of the hundredth of second count. This
results in every 25 hundredth of seconds increments
equaling exactly 250 ms. Long term, the hundredth of
seconds frequency will average the desired 100 Hz,
while jitter is minimized short term.
EQUATION 5-2:
HUNDREDTH OF
SECONDS GENERATION
41 clocks 24 counts + 40 clocks 1 count
--------------------------------------------------------------------------------------------------------------- = 250 ms
4,096 Hz
2011-2018 Microchip Technology Inc.
DS20002280E-page 17
MCP795W1X/MCP795W2X
REGISTER 5-1:
RTCHSEC: TIMEKEEPING HUNDREDTH OF SECONDS VALUE REGISTER
(ADDRESS 0x00)
R/W-0
R/W-0
HSECTEN3
HSECTEN2
R/W-0
R/W-0
R/W-0
HSECTEN1 HSECTEN0 HSECONE3
R/W-0
HSECONE2
R/W-0
R/W-0
HSECONE1 HSECONE0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is clear
x = Bit is unknown
bit 7-4
HSECTEN: Binary-Coded Decimal Value of Hundredth of Second’s Tens Digit
Contains a value from 0 to 9
bit 3-0
HSECONE: Binary-Coded Decimal Value of Hundredth of Second’s Ones Digit
Contains a value from 0 to 9
REGISTER 5-2:
RTCSEC: TIMEKEEPING SECONDS VALUE REGISTER (ADDRESS 0x01)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
ST
SECTEN2
SECTEN1
SECTEN0
SECONE3
SECONE2
SECONE1
SECONE0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is clear
x = Bit is unknown
bit 7
ST: Start Oscillator bit
1 = Oscillator enabled
0 = Oscillator disabled
bit 6-4
SECTEN: Binary-Coded Decimal Value of Second’s Tens Digit
Contains a value from 0 to 5
bit 3-0
SECONE: Binary-Coded Decimal Value of Second’s Ones Digit
Contains a value from 0 to 9
REGISTER 5-3:
RTCMIN: TIMEKEEPING MINUTES VALUE REGISTER (ADDRESS 0x02)
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
MINTEN2
MINTEN1
MINTEN0
MINONE3
MINONE2
MINONE1
MINONE0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is clear
bit 7
Unimplemented: Read as ‘0’
bit 6-4
MINTEN: Binary-Coded Decimal Value of Minute’s Tens Digit
Contains a value from 0 to 5
bit 3-0
MINONE: Binary-Coded Decimal Value of Minute’s Ones Digit
Contains a value from 0 to 9
2011-2018 Microchip Technology Inc.
x = Bit is unknown
DS20002280E-page 18
MCP795W1X/MCP795W2X
REGISTER 5-4:
RTCHOUR: TIMEKEEPING HOURS VALUE REGISTER (ADDRESS 0x03)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
TRIMSIGN
12/24
AM/PM
HRTEN1
HRTEN0
HRONE3
HRONE2
HRONE1
HRONE0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is clear
x = Bit is unknown
If 12/24 = 1 (12-hour format):
bit 7
TRIMSIGN: Trim Sign bit
1 = Add clocks to correct for slow time
0 = Subtract clocks to correct for fast time
bit 6
12/24: 12 or 24 Hour Time Format bit
1 = 12-hour format
0 = 24-hour format
bit 5
AM/PM: AM/PM Indicator bit
1 = PM
0 = AM
bit 4
HRTEN0: Binary-Coded Decimal Value of Hour’s Tens Digit
Contains a value from 0 to 1
bit 3-0
HRONE: Binary-Coded Decimal Value of Hour’s Ones Digit
Contains a value from 0 to 9
If 12/24 = 0 (24-hour format):
bit 7
TRIMSIGN: Trim Sign bit
1 = Add clocks to correct for slow time
0 = Subtract clocks to correct for fast time
bit 6
12/24: 12 or 24 Hour Time Format bit
1 = 12-hour format
0 = 24-hour format
bit 5-4
HRTEN: Binary-Coded Decimal Value of Hour’s Tens Digit
Contains a value from 0 to 2.
bit 3-0
HRONE: Binary-Coded Decimal Value of Hour’s Ones Digit
Contains a value from 0 to 9
2011-2018 Microchip Technology Inc.
DS20002280E-page 19
MCP795W1X/MCP795W2X
REGISTER 5-5:
RTCWKDAY: TIMEKEEPING WEEKDAY VALUE REGISTER (ADDRESS 0x04)
U-0
U-0
R-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-1
—
—
OSCRUN
PWRFAIL
VBATEN
WKDAY2
WKDAY1
WKDAY0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is clear
x = Bit is unknown
bit 7-6
Unimplemented: Read as ‘0’
bit 5
OSCRUN: Oscillator Status bit
1 = Oscillator is enabled and running
0 = Oscillator has stopped or has been disabled
bit 4
PWRFAIL: Power Failure Status bit(1,2)
1 = Primary power was lost and the power-fail timestamp registers have been loaded (must be cleared
in software). Clearing this bit resets the power-fail timestamp registers to ‘0’.
0 = Primary power has not been lost
bit 3
VBATEN: External Battery Backup Supply (VBAT) Enable bit
1 = VBAT input is enabled
0 = VBAT input is disabled
bit 2-0
WKDAY: Binary-Coded Decimal Value of Day of Week
Contains a value from 1 to 7. The representation is user-defined.
Note 1:
2:
The PWRFAIL bit must be cleared to log new timestamp data. This is to ensure previous timestamp data is
not lost.
The PWRFAIL bit can be cleared by writing a ‘0’. Once cleared, the PWRFAIL bit cannot be written to a ‘1’
in software.
REGISTER 5-6:
RTCDATE: TIMEKEEPING DATE VALUE REGISTER (ADDRESS 0x05)
U-0
U-0
R/W-0
—
—
DATETEN1
R/W-0
R/W-0
DATETEN0 DATEONE3
R/W-0
R/W-0
R/W-1
DATEONE2
DATEONE1
DATEONE0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is clear
bit 7-6
Unimplemented: Read as ‘0’
bit 5-4
DATETEN: Binary-Coded Decimal Value of Date’s Tens Digit
Contains a value from 0 to 3
bit 3-0
DATEONE: Binary-Coded Decimal Value of Date’s Ones Digit
Contains a value from 0 to 9
2011-2018 Microchip Technology Inc.
x = Bit is unknown
DS20002280E-page 20
MCP795W1X/MCP795W2X
REGISTER 5-7:
RTCMTH: TIMEKEEPING MONTH VALUE REGISTER (ADDRESS 0x06)
U-0
U-0
R-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-1
—
—
LPYR
MTHTEN0
MTHONE3
MTHONE2
MTHONE1
MTHONE0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is clear
x = Bit is unknown
bit 7-6
Unimplemented: Read as ‘0’
bit 5
LPYR: Leap Year bit
1 = Year is a leap year
0 = Year is not a leap year
bit 4
MTHTEN0: Binary-Coded Decimal Value of Month’s Tens Digit
Contains a value of 0 or 1
bit 3-0
MTHONE: Binary-Coded Decimal Value of Month’s Ones Digit
Contains a value from 0 to 9
REGISTER 5-8:
RTCYEAR: TIMEKEEPING YEAR VALUE REGISTER (ADDRESS 0x07)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-1
YRTEN3
YRTEN2
YRTEN1
YRTEN0
YRONE3
YRONE2
YRONE1
YRONE0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is clear
x = Bit is unknown
bit 7-4
YRTEN: Binary-Coded Decimal Value of Year’s Tens Digit
Contains a value from 0 to 9
bit 3-0
YRONE: Binary-Coded Decimal Value of Year’s Ones Digit
Contains a value from 0 to 9
TABLE 5-4:
Name
RTCHSEC
RTCSEC
SUMMARY OF REGISTERS ASSOCIATED WITH TIMEKEEPING
Bit 7
Bit 6
Bit 5
HSECTEN3 HSECTEN2 HSECTEN1
Bit 4
Bit 3
Bit 2
Bit 1
HSECTEN0 HSECONE3 HSECONE2 HSECONE1
Bit 0
Register
on Page
HSECONE0
18
ST
SECTEN2
SECTEN1
SECTEN0
SECONE3
SECONE2
SECONE1
SECONE0
18
—
MINTEN2
MINTEN1
MINTEN0
MINONE3
MINONE2
MINONE1
MINONE0
18
TRIMSIGN
12/24
AM/PM
HRTEN1
HRTEN0
HRONE3
HRONE2
HRONE1
HRONE0
19
RTCWKDAY
—
—
OSCRUN
PWRFAIL
VBATEN
WKDAY2
WKDAY1
WKDAY0
20
RTCDATE
—
—
DATETEN1
DATETEN0
DATEONE3
DATEONE2
DATEONE1
DATEONE0
20
RTCMTH
—
—
LPYR
MTHTEN0
MTHONE3
MTHONE2
MTHONE1
MTHONE0
21
YRTEN3
YRTEN2
YRTEN1
YRTEN0
YRONE3
YRONE2
YRONE1
YRONE0
21
RTCMIN
RTCHOUR
RTCYEAR
Legend:
— = unimplemented location, read as ‘0’. Shaded cells are not used in timekeeping.
2011-2018 Microchip Technology Inc.
DS20002280E-page 21
MCP795W1X/MCP795W2X
5.4
TABLE 5-6:
Alarms
ALARM 1 MASKS
The MCP795WXX features two independent alarms.
Each alarm can be used to either generate an interrupt
at a specific time in the future, or to generate a periodic
interrupt every second (Alarm 1 only), minute, hour,
day, day of week, or month.
ALM1MSK
Alarm 1 Asserts on Match of
000
Seconds
001
Minutes
010
Hours
There is a separate interrupt flag, ALMxIF, for each
alarm. The interrupt flags are set by hardware when the
chosen alarm mask condition matches (Table 5-5 and
Table 5-6). The interrupt flags must be cleared in
software.
011
Day of Week
100
Date
101
Hundredth of Seconds
110
Reserved
111
Seconds, Minutes, Hours, Day of
Week, and Date
Each alarm can independently be assigned to either
the IRQ pin or the WDO pin by configuring
the ALMxPIN bits. Refer to Section 5.8 “Interrupt
Outputs” for details. The alarm interrupt output is
available while operating from the backup power
supply, regardless of the output pin assignments.
All time and date values are stored in the registers as
binary-coded decimal (BCD) values.
Note:
Note 1: The alarm interrupt flags must be cleared
by the user.
2: Loading invalid values into the alarm registers will result in undefined operation.
Throughout this section, references to the
register and bit names for the alarm
modules are referred to generically by the
use of ‘x’ in place of the specific module
number. Thus, “ALMxSEC” might refer to
the seconds register for Alarm 0 or
Alarm 1.
TABLE 5-5:
ALARM 0 MASKS
ALM0MSK
Alarm 0 Asserts on Match of
000
Seconds
001
Minutes
010
Hours
011
Day of Week
100
Date
101
Reserved
110
Reserved
111
Seconds, Minutes, Hours, Day of
Week, Date, and Month
2011-2018 Microchip Technology Inc.
DS20002280E-page 22
MCP795W1X/MCP795W2X
FIGURE 5-7:
ALARM BLOCK DIAGRAM
Timekeeping
Registers
Alarm 1
Registers
RTCHSEC
ALM1HSEC
ALM0SEC
RTCSEC
ALM1SEC
ALM0MIN
RTCMIN
ALM1MIN
ALM0HOUR
RTCHOUR
ALM1HOUR
ALM0WKDAY
RTCWKDAY
ALM1WKDAY
ALM0DATE
RTCDATE
ALM1DATE
ALM0MTH
RTCMTH
Alarm 0
Registers
Alarm 0 Mask
Comparator
Comparator
Set
ALM0IF
ALM0MSK
5.4.1
Alarm 1 Mask
Set
ALM1IF
Interrupt
Output Logic
IRQ
ALM1MSK
WDO
CONFIGURING THE ALARM
In order to configure the alarm modules, the following
steps need to be performed:
1.
2.
3.
4.
5.
6.
Load the timekeeping registers and enable the
oscillator.
Configure the ALMxMSK bits to select the
desired alarm mask.
Set or clear the ALMxPIN bit according to the
desired output pin assignment.
Ensure the ALMxIF flag is cleared.
Based on the selected alarm mask, load the
alarm match value into the appropriate
register(s).
Enable the alarm module by setting the
ALMxEN bit.
2011-2018 Microchip Technology Inc.
DS20002280E-page 23
MCP795W1X/MCP795W2X
REGISTER 5-9:
ALM1HSEC: ALARM 1 HUNDREDTHS OF SECONDS VALUE REGISTER
(ADDRESS 0x12)
R/W-0
R/W-0
HSECTEN3
HSECTEN2
R/W-0
R/W-0
R/W-0
HSECTEN1 HSECTEN0 HSECONE3
R/W-0
HSECONE2
R/W-0
R/W-0
HSECONE1 HSECONE0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is clear
x = Bit is unknown
bit 7-4
HSECTEN: Binary-Coded Decimal Value of Hundredth of Second’s Tens Digit
Contains a value from 0 to 9
bit 3-0
HSECONE: Binary-Coded Decimal Value of Hundredth of Second’s Ones Digit
Contains a value from 0 to 9
Note 1:
Hundredth of seconds matching is only available on Alarm 1.
REGISTER 5-10:
ALMxSEC: ALARM 0/1 SECONDS VALUE REGISTER (ADDRESSES 0x0C/0x13)
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
SECTEN2
SECTEN1
SECTEN0
SECONE3
SECONE2
SECONE1
SECONE0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is clear
bit 7
Unimplemented: Read as ‘0’
bit 6-4
SECTEN: Binary-Coded Decimal Value of Second’s Tens Digit
Contains a value from 0 to 5
bit 3-0
SECONE: Binary-Coded Decimal Value of Second’s Ones Digit
Contains a value from 0 to 9
2011-2018 Microchip Technology Inc.
x = Bit is unknown
DS20002280E-page 24
MCP795W1X/MCP795W2X
REGISTER 5-11:
ALMxMIN: ALARM 0/1 MINUTES VALUE REGISTER (ADDRESSES 0x0D/0x14)
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
MINTEN2
MINTEN1
MINTEN0
MINONE3
MINONE2
MINONE1
MINONE0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is clear
x = Bit is unknown
bit 7
Unimplemented: Read as ‘0’
bit 6-4
MINTEN: Binary-Coded Decimal Value of Minute’s Tens Digit
Contains a value from 0 to 5
bit 3-0
MINONE: Binary-Coded Decimal Value of Minute’s Ones Digit
Contains a value from 0 to 9
REGISTER 5-12:
ALMxHOUR: ALARM 0/1 HOURS VALUE REGISTER (ADDRESSES 0x0E/0x15)
U-0
R-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
12/24
AM/PM
HRTEN1
HRTEN0
HRONE3
HRONE2
HRONE1
HRONE0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is clear
x = Bit is unknown
If 12/24 = 1 (12-hour format):
bit 7
Unimplemented: Read as ‘0’
bit 6
12/24: 12 or 24 Hour Time Format bit(1)
1 = 12-hour format
0 = 24-hour format
bit 5
AM/PM: AM/PM Indicator bit
1 = PM
0 = AM
bit 4
HRTEN0: Binary-Coded Decimal Value of Hour’s Tens Digit
Contains a value from 0 to 1
bit 3-0
HRONE: Binary-Coded Decimal Value of Hour’s Ones Digit
Contains a value from 0 to 9
If 12/24 = 0 (24-hour format):
bit 7
Unimplemented: Read as ‘0’
bit 6
12/24: 12 or 24 Hour Time Format bit(1)
1 = 12-hour format
0 = 24-hour format
bit 5-4
HRTEN: Binary-Coded Decimal Value of Hour’s Tens Digit
Contains a value from 0 to 2.
bit 3-0
HRONE: Binary-Coded Decimal Value of Hour’s Ones Digit
Contains a value from 0 to 9
Note 1:
This bit is read-only and reflects the value of the 12/24 bit in the RTCHOUR register.
2011-2018 Microchip Technology Inc.
DS20002280E-page 25
MCP795W1X/MCP795W2X
REGISTER 5-13:
ALMxWKDAY: ALARM 0/1 WEEKDAY VALUE REGISTER
(ADDRESSES 0x0F/0x16)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-1
ALMxPIN
ALMxMSK2
ALMxMSK1
ALMxMSK0
ALMxIF
WKDAY2
WKDAY1
WKDAY0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is clear
x = Bit is unknown
bit 7
ALMxPIN: Alarm Interrupt Output Pin Assignment bit
1 = Alarm output is assigned to WDO
0 = Alarm output is assigned to IRQ
bit 6-4
ALMxMSK: Alarm Mask bits
000 = Seconds match
001 = Minutes match
010 = Hours match (logic takes into account 12-/24-hour operation)
011 = Day of week match
100 = Date match
101 = Hundredth of Seconds(1)
110 = Reserved; do not use
111 = Seconds, Minutes, Hour, Day of Week, Date and Month(2)
bit 3
ALMxIF: Alarm Interrupt Flag bit(3)
1 = Alarm match occurred (must be cleared in software)
0 = Alarm match did not occur
bit 2-0
WKDAY: Binary-Coded Decimal Value of Day bits
Contains a value from 1 to 7. The representation is user-defined.
Note 1:
2:
3:
Hundredth of seconds matching is available on Alarm 1 only. This setting is reserved on Alarm 0.
Month matching is available on Alarm 0 only.
The ALMxIF bit can be cleared by writing a ‘0’. Once cleared, the ALMxIF bit cannot be written to a ‘1’ in
software.
REGISTER 5-14:
ALMxDATE: ALARM 0/1 DATE VALUE REGISTER (ADDRESSES 0x10/0x17)
U-0
U-0
R/W-0
—
—
DATETEN1
R/W-0
R/W-0
DATETEN0 DATEONE3
R/W-0
R/W-0
R/W-1
DATEONE2
DATEONE1
DATEONE0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is clear
bit 7-6
Unimplemented: Read as ‘0’
bit 5-4
DATETEN: Binary-Coded Decimal Value of Date’s Tens Digit
Contains a value from 0 to 3
bit 3-0
DATEONE: Binary-Coded Decimal Value of Date’s Ones Digit
Contains a value from 0 to 9
2011-2018 Microchip Technology Inc.
x = Bit is unknown
DS20002280E-page 26
MCP795W1X/MCP795W2X
REGISTER 5-15:
ALM0MTH: ALARM 0 MONTH VALUE REGISTER (ADDRESS 0x11)
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-1
—
—
—
MTHTEN0
MTHONE3
MTHONE2
MTHONE1
MTHONE0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is clear
x = Bit is unknown
bit 7-5
Unimplemented: Read as ‘0’
bit 4
MTHTEN0: Binary-Coded Decimal Value of Month’s Tens Digit
Contains a value of 0 or 1
bit 3-0
MTHONE: Binary-Coded Decimal Value of Month’s Ones Digit
Contains a value from 0 to 9
Note 1:
Month matching is only available on Alarm 0.
TABLE 5-7:
SUMMARY OF REGISTERS ASSOCIATED WITH ALARMS
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Register
on Page
ALM0SEC
—
SECTEN2
SECTEN1
SECTEN0
SECONE3
SECONE2
SECONE1
SECONE0
24
ALM0MIN
—
MINTEN2
MINTEN1
MINTEN0
MINONE3
MINONE2
MINONE1
MINONE0
25
ALM0HOUR
—
12/24
AM/PM
HRTEN1
HRTEN0
HRONE3
HRONE2
HRONE1
HRONE0
25
Name
ALM0WKDAY
ALM0PIN
ALM0MSK2
ALM0MSK1
ALM0MSK0
ALM0IF
WKDAY2
WKDAY1
WKDAY0
26
ALM0DATE
—
—
DATETEN1
DATETEN0
DATEONE3
DATEONE2
DATEONE1
DATEONE0
26
ALM0MTH
—
—
—
MTHTEN0
MTHONE3
MTHONE2
MTHONE1
MTHONE0
27
HSECTEN3
HSECTEN2
HSECTEN1
HSECTEN0
ALM1SEC
—
SECTEN2
SECTEN1
SECTEN0
SECONE3
SECONE2
SECONE1
SECONE0
24
ALM1MIN
—
MINTEN2
MINTEN1
MINTEN0
MINONE3
MINONE2
MINONE1
MINONE0
25
ALM1HOUR
—
12/24
AM/PM
HRTEN1
HRTEN0
HRONE3
HRONE2
HRONE1
HRONE0
25
ALM1PIN
ALM1MSK2
ALM1MSK1
ALM1MSK0
ALM1IF
WKDAY2
WKDAY1
WKDAY0
26
ALM1DATE
—
—
DATETEN1
DATETEN0
DATEONE3
DATEONE2
DATEONE1
DATEONE0
26
CONTROL
OUT
SQWEN
ALM1EN
ALM0EN
EXTOSC
CRSTRIM
SQWFS1
SQWFS0
35
ALM1HSEC
ALM1WKDAY
Legend:
HSECONE3 HSECONE2 HSECONE1 HSECONE0
24
— = unimplemented location, read as ‘0’. Shaded cells are not used by alarms.
2011-2018 Microchip Technology Inc.
DS20002280E-page 27
MCP795W1X/MCP795W2X
5.5
Watchdog Timer
The MCP795WXX features a Watchdog Timer (WDT)
module that can be used to enhance the robustness of
an application. The WDT continuously counts up
toward a specified time-out period. During normal
operation, the application would clear the WDT before
it times out. However, if a failure occurs, the application
would not clear the WDT, causing it to time out, set the
WDTIF interrupt flag, and assert the WDO pin low for a
specified pulse width. This can then be used to reset
the application and recover from the failure.
The WDT time-out period can be configured by setting
the WDTPS bits according to Table 5-8. Setting
the WDTDLYEN bit will enable a 64-second nominal
start-up delay. With this enabled, every time the WDT
is restarted or cleared, the WDT will wait for 64 seconds
before starting the time-out period.
Once the WDTIF flag has been set due to a WDT
time-out, the WDTIF flag must be cleared to restart the
WDT.
The WDT is driven by the oscillator. If the oscillator is
not running, then the WDT time-out will not occur.
Note 1: The WDT time-out period should only be
changed while the WDT module is
disabled.
TABLE 5-8:
WATCHDOG TIMER TIME-OUT
PERIOD SELECTION
WDTPS
Time-out Period
(FOSC Cycles)
Nominal
Time-out
Period(1)
0000
32 cycles
977 µs
0001
512 cycles
15.6 ms
0010
2,048 cycles
62.5 ms
0011
4,096 cycles
125 ms
0100
32,768 cycles
1 second
0101
524,288 cycles
16 seconds
0110
1,048,576 cycles
32 seconds
0111
2,097,152 cycles
64 seconds
1xxx
Note 1:
5.5.1
The WDT interrupt output will operate regardless of
whether or not either alarm module interrupt output is
assigned to the WDO pin. See Section 5.8.2 “WDO
Interrupt Output” for additional details.
TABLE 5-9:
WATCHDOG TIMER OUTPUT
PULSE WIDTH SELECTION
WDTPWS
Pulse Width
(FOSC Cycles)
Nominal Pulse
Width(1)
0
4 cycles
122 µs
4,096 cycles
125 ms
1
Note 1:
5.5.2
Nominal period assumes FOSC is
32.768 kHz.
CONFIGURING THE WATCHDOG
TIMER
In order to configure the WDT module, the following
steps need to be performed:
1.
2.
3.
4.
5.
6.
Enable the oscillator.
Configure the WDTPS bits to select the
desired time-out period.
If desired, set the WDTDLYEN bit to enable the
64-second start-up delay.
Configure the WDTPWS bit to select the desired
output pulse width.
Ensure the WDTIF flag is cleared.
Enable the WDT module by setting the WDTEN
bit.
5.5.3
CLEARING THE WATCHDOG TIMER
The WDT must be cleared before the time-out period
occurs in order to prevent it from timing out. The WDT
can be cleared using any of the following methods:
1.
2.
3.
4.
Executing a CLRWDT instruction.
Toggling the EVHS pin with the EVWDTEN bit
set.
Disabling/re-enabling the WDT module.
Clearing the WDTIF flag after it has been set.
Reserved
Nominal period assumes FOSC is
32.768 kHz.
WATCHDOG TIMER INTERRUPT
OUTPUT
When the WDT times out, the WDTIF interrupt flag gets
set and the WDO pin is asserted low for a short pulse.
The width of the pulse is determined by the WDTPWS
bit according to Table 5-9.
2011-2018 Microchip Technology Inc.
DS20002280E-page 28
MCP795W1X/MCP795W2X
FIGURE 5-8:
WATCHDOG TIMER BLOCK DIAGRAM
MCP795WXX
WDTPS
2,097,152
FOSC
WDT
Counter
1,048,576
Reset
0
WDTIF
WDTEN
64-sec Start-up
Delay
Reset
CLRWDT
EVHS
EVHS
Block
2011-2018 Microchip Technology Inc.
1
WDTDLYEN
Clear WDT
Postscaler
524,288
32,768
4,096
2,048
512
32
0111
0110
0101
0100
0011
MUX
Oscillator
Block
WDT Time Out
0010
0001
0000
Set WDTIF
Output
Pulse Gen
WDO
WDTPWS
DS20002280E-page 29
MCP795W1X/MCP795W2X
REGISTER 5-16:
WDTCON: WATCHDOG TIMER CONTROL REGISTER (ADDRESS 0x0A)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
WDTEN
WDTIF
WDTDLYEN
WDTPWS
WDTPS3
WDTPS2
WDTPS1
WDTPS0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is clear
x = Bit is unknown
bit 7
WDTEN: Watchdog Timer Enable bit(1)
1 = Watchdog Timer enabled
0 = Watchdog Timer disabled
bit 6
WDTIF: Watchdog Timer Interrupt Flag bit
1 = Watchdog Timer has timed out (must be cleared in software)
0 = Watchdog Timer has not timed out
bit 5
WDTDLYEN: Watchdog Timer Delay Enable bit
1 = Enable 2,097,152 oscillator cycle (64-second nominal) start-up delay before time-out period
begins after WDT is reset
0 = Disable start-up delay
bit 4
WDTPWS: Watchdog Timer Output Pulse Width Select bit
1 = 4,096 oscillator cycles (125 ms nominal)
0 = 4 oscillator cycles (122 µs nominal)
bit 3-0
WDTPS: Watchdog Timer Time-out Period Select bits
0000 = 32 oscillator cycles (977 µs nominal)
0001 = 512 oscillator cycles (15.6 ms nominal)
0010 = 2,048 oscillator cycles (62.5 ms nominal)
0011 = 4,096 oscillator cycles (125 ms nominal)
0100 = 32,768 oscillator cycles (1 second nominal)
0101 = 524,288 oscillator cycles (16 second nominal)
0110 = 1,048,576 oscillator cycles (32 second nominal)
0111 = 2,097,152 oscillator cycles (64 second nominal)
1xxx = Reserved; do not use
Note 1:
The WDTEN bit is automatically cleared when operating from the backup power supply.
TABLE 5-10:
Name
WDTCON
Legend:
SUMMARY OF REGISTERS ASSOCIATED WITH WATCHDOG TIMER
Bit 7
Bit 6
WDTEN
WDTIF
Bit 5
Bit 4
WDTDLYEN WDTPWS
Bit 3
Bit 2
Bit 1
Bit 0
Register
on Page
WDTPS3
WDTPS2
WDTPS1
WDTPS0
30
— = unimplemented location, read as ‘0’. Shaded cells are not used in Watchdog Timer configuration.
2011-2018 Microchip Technology Inc.
DS20002280E-page 30
MCP795W1X/MCP795W2X
5.6
Event Detection
If the total number of transitions specified by the
EVHCS bits do not occur within the time-out
period, then the transition count will be reset and counting will start over (Figure 5-10). The time-out period is
driven by the oscillator. If the oscillator is not running,
then the time-out will not occur.
The MCP795WXX features two separate event
detection modules: a high-speed event detect and a
low-speed event detect. The high-speed event detect
can be used to detect signal preambles, while the
low-speed event detect is meant for debouncing
mechanical switches.
TABLE 5-11:
HIGH-SPEED EVENT COUNT
SELECTION
The event detection modules are not available while
operating from the backup power supply.
5.6.1
HIGH-SPEED EVENT DETECT
The high-speed event detect module is designed to
detect a series of digital transitions (both low-to-high
and high-to-low) on the EVHS input, and then generate
an interrupt. The number of transitions required to
occur is determined by the EVHCS bits as shown
in Table 5-11. Once the specified number of transitions
have occurred, the EVHIF interrupt flag is set and the
IRQ pin is asserted low.
Required Transitions
for Interrupt
00
1
01
4
10
16
11
32
5.6.1.1
Clearing the WDT Using EVHS
The EVHS input can also be used to clear the
Watchdog Timer on both low-to-high and high-to-low
transitions by setting the EVWDTEN bit. Note that
when this bit is set, the high-speed event detect module
is disabled and the EVHEN bit is ignored.
The high-speed event detect has a time-out period of
8,192 oscillator cycles (250 ms nominal assuming a
32.768 kHz clock frequency).
FIGURE 5-9:
EVHCS
HIGH-SPEED EVENT DETECT BLOCK DIAGRAM
MCP795WXX
EVHEN
FOSC
Oscillator
Block
Time Out
Occurred
Postscaler
1:8,192
S Q
Reset
R
Reset
and
Edge Detect
EVHS
Edge
Detected
0
Prescaler
1, 4, 16, 32
Interrupt
Output Logic
Set EVHIF
IRQ
1
EVHCS
EVWDTEN
Clear WDT
FIGURE 5-10:
HIGH-SPEED EVENT DETECT WAVEFORM EXAMPLE
1
2
3
4
n-1(1)
1
2
3
4
5
n(1)
EVHS
8,192 osc. cycles
< 8,192 osc. cycles
EVHIF Bit
Note 1: ‘n’ refers to the required number of transitions as determined by the EVHCS bits.
2011-2018 Microchip Technology Inc.
DS20002280E-page 31
MCP795W1X/MCP795W2X
5.6.1.2
Configuring High-Speed Event
Detect
The low-speed event detect module is driven by the
oscillator. If the oscillator is not running, then the
debounce period will not expire and the EVLIF flag will
not be set.
In order to configure the high-speed event detect
module, the following steps need to be performed:
1.
2.
3.
4.
5.
Enable the oscillator.
Configure the EVHCS bits to select the
desired number of transitions.
Ensure the EVWDTEN bit is cleared.
Ensure the EVHIF flag is cleared.
Enable the high-speed event detect module by
setting the EVHEN bit.
TABLE 5-12:
EVLPS
Debounce Period
(FOSC Cycles)
Nominal Debounce
Period(1)
0
1,024 cycles
31.25 ms
16,384 cycles
500 ms
1
5.6.2
LOW-SPEED EVENT DETECT
Note 1:
The low-speed event detect module is designed to
interface directly with mechanical switches to provide a
debounced signal. The debounce period is selectable
through the EVLPS bit as shown in Table 5-12. Low
speed events occur when the EVLS input toggles and
remains stable for the selected debounce period.
Nominal period assumes FOSC is
32.768 kHz.
5.6.2.1
Configuring Low-Speed Event
Detect
In order to configure the low-speed event detect
module, the following steps need to be performed:
After a transition on the EVLS input, the MCP795WXX
will begin counting the debounce period. Either a
high-to-low or a low-to-high transition will initiate
counting. Once the debounce period has expired, the
EVLIF flag is set and the IRQ pin is asserted low
(Figure 5-12). If the EVLS input returns to its original
level before the debounce period expires, then
counting is aborted and the EVLIF flag will not be set.
FIGURE 5-11:
LOW-SPEED EVENT
DEBOUNCE PERIOD
SELECTION
1.
2.
3.
4.
Enable the oscillator.
Configure the EVLPS bit to select the desired
debounce period.
Ensure the EVLIF flag is cleared.
Enable the low-speed event detect module by
setting the EVLEN bit.
LOW-SPEED EVENT DETECT BLOCK DIAGRAM
MCP795WXX
EVLPS
31.25 ms
Oscillator
Block
FOSC
EVLEN
Postscaler
1:1,024
Postscaler
1:16
500 ms
0
Set EVLIF
1
Reset
D
EVLS
Latch New
EVLS State
FIGURE 5-12:
Q
Interrupt
Output Logic
EVLS Matches
Latched State
IRQ
CK
LOW-SPEED EVENT DETECT WAVEFORM EXAMPLE
EVLS
Debounce Period(1)
EVLIF Bit
Note 1: The debounce period is determined by the EVLPS bit.
2011-2018 Microchip Technology Inc.
DS20002280E-page 32
MCP795W1X/MCP795W2X
REGISTER 5-17:
EVDTCON: EVENT DETECT CONTROL REGISTER (ADDRESS 0x0B)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
EVHIF
EVLIF
EVHEN
EVLEN
EVWDTEN
EVLPS
EVHCS1
EVHCS0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is clear
x = Bit is unknown
bit 7
EVHIF: High-Speed Event Detect Interrupt Flag bit
1 = High-speed event detection occurred (must be cleared in software)
0 = High-speed event detection did not occur
bit 6
EVLIF: Low-Speed Event Detect Interrupt Flag bit
1 = Low-speed event detection occurred (must be cleared in software)
0 = Low-speed event detection did not occur
bit 5
EVHEN: High-Speed Event Detect Module Enable bit
If EVWDTEN = 0:
1 = High-Speed Event Detect enabled
0 = High-Speed Event Detect disabled
If EVWDTEN = 1:
Unused.
bit 4
EVLEN: Low-Speed Event Detect Module Enable bit
1 = Low-Speed Event Detect enabled
0 = Low-Speed Event Detect disabled
bit 3
EVWDTEN: EVHS Input WDT Clear Enable bit
1 = Enable Watchdog Timer clear on EVHS input transition. Disables high-speed event detect module.
0 = Disable EVHS input clearing Watchdog Timer.
bit 2
EVLPS: Low-Speed Event Detect Debounce Period Select bit
1 = 16,384 oscillator cycles (500 ms nominal)
0 = 1,024 oscillator cycles (31.25 ms nominal)
bit 1-0
EVHCS: High-Speed Event Detect Transition Count Select bits
Selects how many transitions must occur on the EVHS input before an interrupt is triggered
00 = 1 transition
01 = 4 transitions
10 = 16 transitions
11 = 32 transitions
TABLE 5-13:
Name
EVDTCON
Legend:
SUMMARY OF REGISTERS ASSOCIATED WITH EVENT DETECTION
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Register
on Page
EVHIF
EVLIF
EVHEN
EVLEN
EVWDTEN
EVLPS
EVHCS1
EVHCS0
33
— = unimplemented location, read as ‘0’. Shaded cells are not used in event detect configuration.
2011-2018 Microchip Technology Inc.
DS20002280E-page 33
MCP795W1X/MCP795W2X
5.7
TABLE 5-14:
Clock Output
The MCP795WXX features Square Wave Clock Output
and General Purpose Output modes through the
CLKOUT pin. If the SQWEN bit is set, then CLKOUT
operates in Square Wave Clock Output mode.
Otherwise, CLKOUT operates in General Purpose
Output mode (Table 5-14).
CLKOUT OUTPUT MODES
SQWEN
OUT
Mode
0
0
Logic Low Output
0
1
Logic High Output
1
x
Square Wave Clock Output
The CLKOUT pin is disabled while operating from the
backup power supply.
FIGURE 5-13:
CLKOUT OUTPUT BLOCK DIAGRAM
MCP795WXX
SQWFS
Oscillator
X2
Postscaler
Digital
Trim
EXTOSC
8.192 kHz
11
10
4.096 kHz
ST
1 Hz
01
00
MUX
32.768 kHz
X1
0
1
1
CRSTRIM
CLKOUT
OUT
0
SQWEN
5.7.1
SQUARE WAVE OUTPUT MODE
5.7.2
GENERAL PURPOSE OUTPUT
MODE
The MCP795WXX can be configured to generate a
square wave clock signal on CLKOUT. The input clock
frequency, FOSC, is divided according to the
SQWFS bits as shown in Table 5-15.
If the square wave clock output is disabled, CLKOUT
acts as a general purpose output. The output logic level
is controlled by the OUT bit.
The square wave output is not available when
operating from the backup power supply.
The general purpose output is not available when
operating from the backup power supply.
Note:
All of the clock output rates are affected by
digital trimming except for the 1:1
postscaler value (SQWFS = 11).
TABLE 5-15:
CLOCK OUTPUT RATES
Nominal
Frequency
SQWFS
Postscaler
00
1:32,768
1 Hz
01
1:8
4.096 kHz
10
1:4
8.192 kHz
11
1:1
32.768 kHz
Note 1:
Nominal frequency assumes FOSC is
32.768 kHz.
2011-2018 Microchip Technology Inc.
DS20002280E-page 34
MCP795W1X/MCP795W2X
REGISTER 5-18:
CONTROL: RTCC CONTROL REGISTER (ADDRESS 0x08)
R/W-1
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
OUT
SQWEN
ALM1EN
ALM0EN
EXTOSC
CRSTRIM
SQWFS1
SQWFS0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is clear
bit 7
x = Bit is unknown
OUT: Logic Level for General Purpose Output
Square Wave Clock Output Mode (SQWEN = 1):
Unused.
General Purpose Output Mode (SQWEN = 0):
1 = CLKOUT signal level is logic high
0 = CLKOUT signal level is logic low
bit 6
SQWEN: Square Wave Output Enable bit
1 = Enable Square Wave Clock Output mode
0 = Disable Square Wave Clock Output mode
bit 5
ALM1EN: Alarm 1 Module Enable bit
1 = Alarm 1 enabled
0 = Alarm 1 disabled
bit 4
ALM0EN: Alarm 0 Module Enable bit
1 = Alarm 0 enabled
0 = Alarm 0 disabled
bit 3
EXTOSC: External Oscillator Input bit
1 = Enable X1 pin to be driven by external 32.768 kHz source
0 = Disable external 32.768 kHz input
bit 2
CRSTRIM: Coarse Trim Mode Enable bit
Coarse Trim mode results in the MCP795WXX applying digital trimming every second.
1 = Enable Coarse Trim mode. If SQWEN = 1, CLKOUT will output trimmed 1 Hz(1) nominal clock
signal.
0 = Disable Coarse Trim mode
See Section 5.9 “Digital Trimming” for details
bit 1-0
SQWFS: Square Wave Clock Output Frequency Select bits
If SQWEN = 1 and CRSTRIM = 0:
Selects frequency of clock output on CLKOUT
00 = 1 Hz(1)
01 = 4.096 kHz(1)
10 = 8.192 kHz(1)
11 = 32.768 kHz
If SQWEN = 0 or CRSTRIM = 1:
Unused.
Note 1:
The 8.192 kHz, 4.096 kHz, and 1 Hz square wave clock output frequencies are affected by digital
trimming.
TABLE 5-16:
SUMMARY OF REGISTERS ASSOCIATED WITH CLOCK OUTPUT CONFIGURATION
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Register
on Page
CONTROL
OUT
SQWEN
ALM1EN
ALM0EN
EXTOSC
CRSTRIM
SQWFS1
SQWFS0
35
Legend:
— = unimplemented location, read as ‘0’. Shaded cells are not used in clock output configuration.
2011-2018 Microchip Technology Inc.
DS20002280E-page 35
MCP795W1X/MCP795W2X
5.8
5.8.2
Interrupt Outputs
The MCP795WXX features interrupt outputs for the
alarm and event detect modules. The alarm interrupt
output can be assigned to either the IRQ pin or the
WDO pin, based on the setting of the ALMxPIN bit for
each alarm module. Setting ALMxPIN to a ‘1’ assigns
the associated alarm module to the WDO pin and clearing ALMxPIN to a ‘0’ assigns the module to the IRQ pin.
The event detect modules are always assigned to the
IRQ pin.
Both the IRQ and the WDO pins are active-low.
5.8.1
IRQ INTERRUPT OUTPUT
The interrupt outputs of modules that are enabled and
assigned to the IRQ pin are OR’d together. If any of the
interrupt flags are set, then the IRQ pin will assert low.
In order to deassert the IRQ pin, all of the assigned
interrupt flags must be cleared or the modules must be
disabled.
The IRQ interrupt output is available when operating
from the backup power supply.
WDO INTERRUPT OUTPUT
If an alarm module is enabled and assigned to the
WDO pin, then when the alarm triggers and the
interrupt flag, ALMxIF, is set, the WDO pin will be
asserted low for 8 oscillator cycles (244 µs nominal
assuming a 32.768 kHz clock frequency) and then
deasserted again. The ALMxIF flag must then be
cleared to rearm the WDO output and allow it to trigger
again upon the next alarm interrupt.
If both alarm modules are enabled and assigned to the
WDO pin, then either module can trigger the WDO
output pulse. However, both ALMxIF flags must be
cleared for the WDO output to trigger upon the next
alarm interrupt.
The Watchdog Timer output on the WDO pin is
independent of the alarm modules and will occur
regardless of the state of the alarm modules and their
interrupt flags.
The WDO interrupt output is available when operating
from the backup power supply.
FIGURE 5-15:
FIGURE 5-14:
IRQ OUTPUT BLOCK
DIAGRAM
ALM0IF
ALM0EN
ALM0PIN
ALM0IF
ALM0EN
ALM0PIN
ALM1IF
ALM1EN
ALM1PIN
WDO OUTPUT BLOCK
DIAGRAM
Pulse Gen
ALM1IF
ALM1EN
ALM1PIN
IRQ
EVLIF
EVLEN
WDO
WDT
Output
EVHIF
EVHEN
TABLE 5-17:
Name
SUMMARY OF REGISTERS ASSOCIATED WITH INTERRUPT OUTPUT
CONFIGURATION
Bit 7
EVDTCON
Bit 5
Bit 4
Bit 3
EVLIF
EVHEN
EVLEN
Bit 2
Bit 1
Bit 0
Register
on Page
EVWDTEN
EVLPS
EVHCS1
EVHCS0
TBD
ALM0WKDAY
ALM0PIN
ALM0MSK2 ALM0MSK1 ALM0MSK0
ALM0IF
WKDAY2
WKDAY1
WKDAY0
26
ALM1WKDAY
ALM1PIN
ALM1MSK2 ALM1MSK1 ALM1MSK0
ALM1IF
WKDAY2
WKDAY1
WKDAY0
26
EXTOSC
CRSTRIM
SQWFS1
SQWFS0
35
CONTROL
Legend:
EVHIF
Bit 6
OUT
SQWEN
ALM1EN
ALM0EN
— = unimplemented location, read as ‘0’. Shaded cells are not used in interrupt output configuration.
2011-2018 Microchip Technology Inc.
DS20002280E-page 36
MCP795W1X/MCP795W2X
5.9
Digital Trimming
The MCP795WXX features digital trimming to correct
for inaccuracies of the external crystal or clock source,
up to roughly ±259 ppm when CRSTRIM = 0. In
addition to compensating for intrinsic inaccuracies in
the clock, this feature can also be used to correct for
error due to temperature variation. This can enable the
user to achieve high levels of accuracy across a wide
temperature operating range.
Digital trimming consists of the MCP795WXX
periodically adding or subtracting clock cycles,
resulting in small adjustments in the internal timing.
REGISTER 5-19:
The adjustment occurs once per minute when
CRSTRIM = 0. The TRIMSIGN bit specifies whether to
add cycles or to subtract them. The TRIMVAL bits
are used to specify by how many clock cycles to adjust.
Each step in the TRIMVAL value equates to
adding or subtracting two clock pulses to or from the
32.768 kHz clock signal. This results in a correction of
roughly 1.017 ppm per step when CRSTRIM = 0.
Setting TRIMVAL to 0x00 disables digital
trimming.
Digital trimming also occurs while operating off the
backup supply.
OSCTRIM: OSCILLATOR DIGITAL TRIM REGISTER (ADDRESS 0x09)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
TRIMVAL7
TRIMVAL6
TRIMVAL5
TRIMVAL4
TRIMVAL3
TRIMVAL2
TRIMVAL1
TRIMVAL0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is clear
bit 7-0
x = Bit is unknown
TRIMVAL: Oscillator Trim Value bits
When CRSTRIM = 0:
11111111 = Add or subtract 510 clock cycles every minute
11111110 = Add or subtract 508 clock cycles every minute
•
•
•
00000010 = Add or subtract 4 clock cycles every minute
00000001 = Add or subtract 2 clock cycles every minute
00000000 = Disable digital trimming
When CRSTRIM = 1:
11111111 = Add or subtract 510 clock cycles every second
11111110 = Add or subtract 508 clock cycles every second
•
•
•
00000010 = Add or subtract 4 clock cycles every second
00000001 = Add or subtract 2 clock cycles every second
00000000 = Disable digital trimming
2011-2018 Microchip Technology Inc.
DS20002280E-page 37
MCP795W1X/MCP795W2X
5.9.1
CALIBRATION
In order to perform calibration, the number of error
clock pulses per minute must be found and the
corresponding trim value must be loaded into
TRIMVAL.
There are two methods for determining the trim value.
The first method involves measuring an output
frequency directly and calculating the deviation from
ideal. The second method involves observing the
number of seconds gained or lost over a period of time.
Once the OSCTRIM register has been loaded, digital
trimming will automatically occur every minute
(CRSTRIM = 0).
5.9.1.1
Calibration by Measuring Frequency
To calibrate the MCP795WXX by measuring the output
frequency, perform the following steps:
1.
2.
3.
4.
5.
6.
Enable the crystal oscillator or external clock
input by setting the ST bit or EXTOSC bit,
respectively.
Ensure TRIMVAL is reset to 0x00.
Select an output frequency by setting
SQWFS.
Set SQWEN to enable the square wave output.
Measure the resulting output frequency using a
calibrated measurement tool, such as a
frequency counter.
Calculate the number of error clocks per minute
(see Equation 5-3).
EQUATION 5-3:
CALCULATING TRIM
VALUE FROM MEASURED
FREQUENCY
32768
F IDEAL – F MEAS ------------------- 60
F IDEAL
TRIMVAL = --------------------------------------------------------------------------------2
5.9.1.2
To calibrate the MCP795WXX by observing the
deviation over time, perform the following steps:
1.
2.
3.
4.
5.
CALCULATING ERROR
PPM
SecDeviation
PPM = ----------------------------------- 1000000
ExpectedSec
Where:
ExpectedSec = Number of seconds in chosen period
SecDeviation = Number of seconds gained or lost
• If the MCP795WXX has gained time relative to
the reference clock, then the oscillator is
faster than ideal and the TRIMSIGN bit must
be cleared.
• If the MCP795WXX has lost time relative to the
reference clock, then the oscillator is slower
than ideal and the TRIMSIGN bit must be set.
6. Calculate the trim value (see Equation 5-5).
EQUATION 5-5:
CALCULATING TRIM
VALUE FROM ERROR
PPM
PPM 32768 60
TRIMVAL = ------------------------------------------1000000 2
F IDEAL = Ideal frequency based on SQWFS
F MEAS = Measured frequency
Note:
Ensure TRIMVAL is reset to 0x00.
Load the timekeeping registers to synchronize
the MCP795WXX with a known-accurate
reference time.
Enable the crystal oscillator or external clock
input by setting the ST bit or EXTOSC bit,
respectively.
Observe how many seconds are gained or lost
over a period of time (larger time periods offer
more accuracy).
Calculate the PPM deviation (see Equation 5-4).
EQUATION 5-4:
Where:
• If the number of error clocks per minute is
negative, then the oscillator is faster than
ideal and the TRIMSIGN bit must be cleared.
• If the number of error clocks per minute is
positive, then the oscillator is slower than
ideal and the TRIMSIGN bit must be set.
7. Load the correct value into TRIMVAL.
Calibration by Observing Time
Deviation
7.
Load the correct value into TRIMVAL.
Note 1: Choosing a longer time period for
observing
deviation
will
improve
accuracy.
2: Large temperature variations during the
observation period can skew results.
Using a lower output frequency and/or
averaging the measured frequency over a
number of clock pulses will reduce the
effects of jitter and improve accuracy.
2011-2018 Microchip Technology Inc.
DS20002280E-page 38
MCP795W1X/MCP795W2X
5.9.2
COARSE TRIM MODE
When CRSTRIM = 1, Coarse Trim mode is enabled.
While in this mode, the MCP795WXX will apply
trimming every second. If SQWEN is set, the CLKOUT
pin will output a trimmed 1 Hz nominal clock signal.
Because trimming is applied every second rather than
every minute, each step of the TRIMVAL value
has a larger effect on the resulting time deviation and
output clock frequency.
TABLE 5-18:
Name
RTCHOUR
CONTROL
OSCTRIM
Legend:
By monitoring the CLKOUT output frequency while in
this mode, the user can easily observe the
TRIMVAL value affecting the clock timing.
Note 1: The 1 Hz Coarse Trim mode square
wave output is not available while
operating from the backup power supply.
2: With Coarse Trim mode enabled, the
TRIMVAL value has a larger effect
on timing. Leaving the mode enabled
during normal operation will likely result
in inaccurate time.
SUMMARY OF REGISTERS ASSOCIATED WITH DIGITAL TRIMMING
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Register
on Page
TRIMSIGN
12/24
AM/PM
HRTEN1
HRTEN0
HRONE3
HRONE2
HRONE1
HRONE0
19
OUT
SQWEN
ALM1EN
ALM0EN
SQWFS1
SQWFS0
35
TRIMVAL1 TRIMVAL0
37
TRIMVAL7 TRIMVAL6 TRIMVAL5 TRIMVAL4
EXTOSC
CRSTRIM
TRIMVAL3
TRIMVAL2
— = unimplemented location, read as ‘0’. Shaded cells are not used by digital trimming.l
2011-2018 Microchip Technology Inc.
DS20002280E-page 39
MCP795W1X/MCP795W2X
5.10
5.10.1
Battery Backup
The MCP795WXX features a backup power supply
input (VBAT) that can be used to provide power to the
timekeeping circuitry, RTCC registers, and SRAM while
primary power is unavailable. The MCP795WXX will
automatically switch to backup power when VCC falls
below VTRIP, and back to VCC when it is above VTRIP.
POWER-FAIL TIMESTAMP
The MCP795WXX includes a power-fail timestamp
module that stores the minutes, hours, date, and month
when primary power is lost and when it is restored
(Figure 5-16). The PWRFAIL bit is also set to indicate
that a power failure occurred.
Note:
Throughout this section, references to the
register and bit names for the Power-Fail
Timestamp module are referred to
generically by the use of ‘x’ in place of the
specific
module
name.
Thus,
“PWRxxMIN” might refer to the minutes
register for power-down or power-up.
The VBATEN bit must be set to enable the VBAT input.
The following functionality
operating on backup power:
•
•
•
•
•
is
maintained
while
Timekeeping
Alarms
Alarm Outputs
Digital Trimming
RTCC Register and SRAM Contents
The following features are not available while operating
on backup power:
•
•
•
•
•
SPI Communication
Watchdog Timer
Event Detect
Square Wave Clock Output
General Purpose Output
Note:
The Watchdog Timer is automatically
disabled when primary power is lost and is
not automatically re-enabled when power
is restored.
To utilize the power-fail timestamp feature, a backup
power supply must be available with the VBAT input
enabled, and the oscillator should also be running to
ensure accurate functionality.
Note 1: The PWRFAIL bit must be cleared to log
new timestamp data. This is to ensure
previous timestamp data is not lost.
2: Clearing the PWRFAIL bit will clear all
timestamp registers.
5.10.1.1
1.
2.
3.
FIGURE 5-16:
Configuring Battery Backup
In order to configure the battery backup feature, the
following steps need to be performed:
Enable the oscillator.
Wait for the OSCRUN bit to be set, indicating the
oscillator has started.
Enable battery backup by setting the VBATEN
bit.
POWER-FAIL TIMESTAMP TIMING
VCC
VTRIP
Power-Down
Timestamp
2011-2018 Microchip Technology Inc.
Power-Up
Timestamp
DS20002280E-page 40
MCP795W1X/MCP795W2X
REGISTER 5-20:
PWRxxMIN: POWER-DOWN/POWER-UP TIMESTAMP MINUTES VALUE
REGISTER (ADDRESSES 0x18/0x1C)
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
MINTEN2
MINTEN1
MINTEN0
MINONE3
MINONE2
MINONE1
MINONE0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is clear
x = Bit is unknown
bit 7
Unimplemented: Read as ‘0’
bit 6-4
MINTEN: Binary-Coded Decimal Value of Minute’s Tens Digit
Contains a value from 0 to 5
bit 3-0
MINONE: Binary-Coded Decimal Value of Minute’s Ones Digit
Contains a value from 0 to 9
REGISTER 5-21:
PWRxxHOUR: POWER-DOWN/POWER-UP TIMESTAMP HOURS VALUE
REGISTER (ADDRESSES 0x19/0x1D)
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
12/24
AM/PM
HRTEN1
HRTEN0
HRONE3
HRONE2
HRONE1
HRONE0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is clear
x = Bit is unknown
If 12/24 = 1 (12-hour format):
bit 7
Unimplemented: Read as ‘0’
bit 6
12/24: 12 or 24 Hour Time Format bit
1 = 12-hour format
0 = 24-hour format
bit 5
AM/PM: AM/PM Indicator bit
1 = PM
0 = AM
bit 4
HRTEN0: Binary-Coded Decimal Value of Hour’s Tens Digit
Contains a value from 0 to 1
bit 3-0
HRONE: Binary-Coded Decimal Value of Hour’s Ones Digit
Contains a value from 0 to 9
If 12/24 = 0 (24-hour format):
bit 7
Unimplemented: Read as ‘0’
bit 6
12/24: 12 or 24 Hour Time Format bit
1 = 12-hour format
0 = 24-hour format
bit 5-4
HRTEN: Binary-Coded Decimal Value of Hour’s Tens Digit
Contains a value from 0 to 2.
bit 3-0
HRONE: Binary-Coded Decimal Value of Hour’s Ones Digit
Contains a value from 0 to 9
2011-2018 Microchip Technology Inc.
DS20002280E-page 41
MCP795W1X/MCP795W2X
REGISTER 5-22:
PWRxxDATE: POWER-DOWN/POWER-UP TIMESTAMP DATE VALUE REGISTER
(ADDRESSES 0x1A/0x1E)
U-0
U-0
R/W-0
—
—
DATETEN1
R/W-0
R/W-0
DATETEN0 DATEONE3
R/W-0
R/W-0
R/W-0
DATEONE2
DATEONE1
DATEONE0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is clear
x = Bit is unknown
bit 7-6
Unimplemented: Read as ‘0’
bit 5-4
DATETEN: Binary-Coded Decimal Value of Date’s Tens Digit
Contains a value from 0 to 3
bit 3-0
DATEONE: Binary-Coded Decimal Value of Date’s Ones Digit
Contains a value from 0 to 9
REGISTER 5-23:
PWRxxMTH: POWER-DOWN/POWER-UP TIMESTAMP MONTH VALUE
REGISTER (ADDRESSES 0x1B/0x1F)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
WKDAY2
WKDAY1
WKDAY0
MTHTEN0
MTHONE3
MTHONE2
MTHONE1
MTHONE0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is clear
x = Bit is unknown
bit 7-5
WKDAY: Binary-Coded Decimal Value of Day bits
Contains a value from 1 to 7. The representation is user-defined.
bit 4
MTHTEN0: Binary-Coded Decimal Value of Month’s Ones Digit
Contains a value of 0 or 1
bit 3-0
MTHONE: Binary-Coded Decimal Value of Month’s Ones Digit
Contains a value from 0 to 9
TABLE 5-19:
Name
SUMMARY OF REGISTERS ASSOCIATED WITH BATTERY BACKUP
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Register
on Page
RTCWKDAY
—
—
OSCRUN
PWRFAIL
VBATEN
WKDAY2
WKDAY1
WKDAY0
20
PWRDNMIN
—
MINTEN2
MINTEN1
MINTEN0
MINONE3
MINONE2
MINONE1
MINONE0
41
PWRDNHOUR
—
12/24
AM/PM
HRTEN1
HRTEN0
HRONE3
HRONE2
HRONE1
HRONE0
41
PWRDNDATE
—
—
DATETEN1
DATETEN0
DATEONE3
DATEONE2
DATEONE1
DATEONE0
42
PWRDNMTH
WKDAY2
WKDAY1
WKDAY0
MTHTEN0
MTHONE3
MTHONE2
MTHONE1
MTHONE0
42
PWRUPMIN
—
MINTEN2
MINTEN1
MINTEN0
MINONE3
MINONE2
MINONE1
MINONE0
41
PWRUPHOUR
—
12/24
AM/PM
HRTEN1
HRTEN0
HRONE3
HRONE2
HRONE1
HRONE0
41
PWRUPDATE
—
—
DATETEN1
DATETEN0
DATEONE3
DATEONE2
DATEONE1
DATEONE0
42
PWRUPMTH
WKDAY2
WKDAY1
WKDAY0
MTHTEN0
MTHONE3
MTHONE2
MTHONE1
MTHONE0
42
Legend:
— = unimplemented location, read as ‘0’. Shaded cells are not used with battery backup.
2011-2018 Microchip Technology Inc.
DS20002280E-page 42
MCP795W1X/MCP795W2X
6.0
ON-BOARD MEMORY
There is no limit to the number of bytes that can be
written in a single command. However, because the
RTCC registers and SRAM are separate blocks, writing
past the end of each block will cause the internal
Address Pointer to roll over to the beginning of the
same block. Specifically, the Address Pointer will roll
over from 0x1F to 0x00, and from 0x5F to 0x20.
The MCP795W2X has 2 Kbits (256 bytes) of
EEPROM, while the MCP795W1X has 1 Kbit
(128 bytes) of EEPROM. In addition, the devices have
16 bytes of protected EEPROM for storing crucial
information, and 64 bytes of SRAM for general purpose
usage. The SRAM is retained when the primary power
supply is removed if a backup supply is present and
enabled. Since the EEPROM is nonvolatile, it does not
require a supply for data retention.
Each data byte is latched into memory as it is received.
Once all data bytes have been transmitted, CS is
driven high to end the operation (Figure 6-1).
6.1.2
Although the SRAM is a separate block from the RTCC
registers, they are accessed using the same
instructions, READ and WRITE. The EEPROM is
accessed using the EEREAD and EEWRITE
instructions, and the protected EEPROM is accessed
using the IDREAD and IDWRITE instructions. RTCC
and SRAM can be accessed for reads or writes
immediately after starting an EEPROM write cycle.
6.1
The device is selected by pulling CS low. The 8-bit
READ instruction is transmitted to the MCP795WXX
followed by an 8-bit address.
After the READ instruction and address are sent, the
data stored in the memory at the selected address is
shifted out on the SO pin. Data stored in the memory at
the next address can be read sequentially by
continuing to provide clock pulses to the slave. The
internal Address Pointer automatically increments to
the next higher address after each byte of data is
shifted out. The Address Pointer allows the entire
memory block to be serially read during one operation.
The read operation is terminated by driving CS high
(Figure 6-2).
SRAM/RTCC Registers
The RTCC registers are located at addresses 0x00 to
0x1F, and the SRAM is located at addresses 0x20 to
0x5F. The SRAM can be accessed while the RTCC
registers are being internally updated. The SRAM is not
initialized by a Power-on Reset (POR).
Neither the RTCC registers nor the SRAM can be
accessed when the device is operating off the backup
power supply.
6.1.1
SRAM/RTCC REGISTER READ
SEQUENCE
Because the RTCC registers and SRAM are separate
blocks, reading past the end of each block will cause
the Address Pointer to roll over to the beginning of the
same block. Specifically, the Address Pointer will roll
over from 0x1F to 0x00, and from 0x5F to 0x20.
SRAM/RTCC REGISTER WRITE
SEQUENCE
The device is selected by pulling CS low. The 8-bit
WRITE instruction is transmitted to the MCP795WXX
followed by an 8-bit address. Next, the data to be
written is transmitted.
FIGURE 6-1:
SRAM/RTCC WRITE SEQUENCE
CS
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
SCK
Address Byte
Instruction
SI
0
0
0
1
0
0
1
Data Byte 1
0 A7 A6 A5 A4 A3 A2 A1 A0 7
6
5
4
3
2
1
0
CS
24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39
SCK
Data Byte 2
SI
7
6
5
4
3
2
2011-2018 Microchip Technology Inc.
Data Byte 3
1
0
7
6
5
4
3
2
Data Byte n
1
0
7
6
5
4
3
2
1
0
DS20002280E-page 43
MCP795W1X/MCP795W2X
FIGURE 6-2:
SRAM/RTCC READ SEQUENCE
CS
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
SCK
Instruction
SI
0
0
0
1
0
Address Byte
0
1
1 A7 A6 A5 A4 A3 A2 A1 A0
Data Out
High-Impedance
7
SO
6.1.3
6
5
4
3
2
1
0
CLEAR SRAM INSTRUCTION
The CLRRAM instruction can be used to quickly clear
the contents of SRAM to 0x00. The RTCC registers are
not affected.
The device is selected by pulling CS low. The 8-bit
CLRRAM instruction is transmitted to the MCP795WXX
followed by an 8-bit dummy data byte. CS is driven high
to end the operation (Figure 6-3). The value of the data
byte is ignored.
FIGURE 6-3:
CLEAR SRAM SEQUENCE
CS
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
1
0
SCK
Instruction
SI
0
1
0
1
0
Dummy Data Byte
1
0
0
7
6
5
4
3
2
High-Impedance
SO
2011-2018 Microchip Technology Inc.
DS20002280E-page 44
MCP795W1X/MCP795W2X
6.2
STATUS Register
The STATUS register contains the BP, WEL and
WIP bits. The STATUS register is accessed using the
SRREAD and SRWRITE instructions.
The Block Protection (BP) bits are used to set the
block write protection for the EEPROM array according
to Table 6-1. These bits are set by the user issuing the
SRWRITE instruction. These bits are nonvolatile.
The WIP bit indicates whether the MCP795WXX is
busy with a nonvolatile memory write operation. When
set to a ‘1’, a write is in progress. When set to a ‘0’, no
write is in progress. This bit is read-only.
TABLE 6-1:
BP1
BP0
Array Addresses
Write-Protected
0
0
None
0
1
Upper 1/4
60h-7Fh (MCP795W1X)
C0h-FFh (MCP795W2X)
1
0
Upper 1/2
40h-7Fh (MCP795W1X)
80h-FFh (MCP795W2X)
1
1
All
The Write Enable Latch (WEL) bit indicates the status
of the write enable latch. When set to a ‘1’, the latch
allows writes to the nonvolatile memory, when set to a
‘0’, the latch prohibits writes to the nonvolatile memory.
The state of this bit can be updated via the EEWREN or
EEWRDI instructions. This bit is read-only.
REGISTER 6-1:
BLOCK PROTECTION
STATUS: EEPROM WRITE PROTECTION REGISTER
U-0
U-0
U-0
U-0
R/W
R/W
R-0
R-0
—
—
—
—
BP1
BP0
WEL
WIP
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is clear
x = Bit is unknown
bit 7-4
Unimplemented: Read as ‘0’
bit 3-2
BP: EEPROM Array Block Protection bits
Selects which EEPROM region is write-protected
00 = None
01 = Upper 1/4
10 = Upper 1/2
11 = All
bit 1
WEL: Write Enable Latch bit
Indicates whether or not nonvolatile memory writes are enabled. It is automatically cleared at the end
of a nonvolatile memory write cycle.
0 = Writes to nonvolatile memory are not enabled
1 = Writes to nonvolatile memory are enabled
bit 0
WIP: Write-In-Process bit
Indicates whether or not a nonvolatile memory write cycle is in process
0 = Nonvolatile write cycle is not in process
1 = Nonvolatile write cycle is in process
6.2.1
STATUS REGISTER WRITE
SEQUENCE
The Write Status Register instruction (SRWRITE)
allows the user to write to the nonvolatile bits in the
STATUS register.
Prior to any attempt to write data to the STATUS
register, the write enable latch must be set by issuing
the EEWREN instruction. This is done by setting CS low
and then clocking out the proper instruction into the
MCP795WXX.
2011-2018 Microchip Technology Inc.
After all eight bits of the instruction are transmitted, CS
must be driven high to set the write enable latch. If the
write operation is initiated immediately after the
EEWREN instruction without CS driven high, data will not
be written to the array since the write enable latch was
not properly set. The device is selected by pulling CS
low. The 8-bit SRWRITE instruction is transmitted to the
MCP795WXX followed by the 8-bit data byte. CS is
driven high to end the operation and initiate the
nonvolatile write cycle (Figure 6-4).
DS20002280E-page 45
MCP795W1X/MCP795W2X
FIGURE 6-4:
WRITE STATUS REGISTER SEQUENCE
CS
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
1
0
SCK
Instruction
0
SI
0
0
0
Data to STATUS Register
0
0
0
7
1
6
5
4
3
2
High-Impedance
SO
6.2.2
STATUS REGISTER READ
SEQUENCE
The device is selected by pulling CS low. The 8-bit
SRREAD instruction is transmitted to the MCP795WXX.
The STATUS register value is then shifted out on the
SO pin. The read operation is terminated by driving CS
high (Figure 6-5).
The Read Status Register instruction (SRREAD)
provides access to the STATUS register. The STATUS
register may be read at any time, even during a write
cycle. This allows the user to poll the WIP bit to
determine when a write cycle is complete.
FIGURE 6-5:
READ STATUS REGISTER SEQUENCE
CS
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
SCK
Instruction
SI
0
0
0
0
0
1
0
1
Data from STATUS Register
High-Impedance
SO
2011-2018 Microchip Technology Inc.
7
6
5
4
3
2
1
0
DS20002280E-page 46
MCP795W1X/MCP795W2X
6.3
EEPROM
The following is a list of conditions under which the
write enable latch will be reset:
The MCP795W2X features 2 Kbits of EEPROM, and
the MCP795W1X features 1 Kbit of EEPROM. It is
organized in 8-byte pages with software write
protection configurable through the STATUS register.
6.3.1
•
•
•
•
•
•
WRITE ENABLE AND WRITE
DISABLE
The MCP795WXX contains a write enable latch. This
latch must be set before any write operation will be
completed internally. The EEWREN instruction will set
the latch, and the EEWRDI instruction will reset the
latch.
FIGURE 6-6:
Power-up
WRDI instruction successfully executed
EEWRITE instruction successfully executed
SRWRITE instruction successfully executed
IDWRITE instruction successfully executed
Unlock sequence for protected EEPROM not
followed correctly
WRITE ENABLE SEQUENCE
CS
0
1
2
3
4
5
6
7
SCK
0
SI
0
0
0
0
1
1
0
High-Impedance
SO
FIGURE 6-7:
WRITE DISABLE SEQUENCE
CS
0
1
2
3
4
5
6
7
SCK
SI
0
0
0
0
0
1
0
0
High-Impedance
SO
2011-2018 Microchip Technology Inc.
DS20002280E-page 47
MCP795W1X/MCP795W2X
6.3.2
EEPROM READ SEQUENCE
The device is selected by pulling CS low. The 8-bit
EEREAD instruction is transmitted to the MCP795WXX
followed by an 8-bit address. See Figure 6-8 for more
details.
After the correct EEREAD instruction and address are
sent, the data stored in the EEPROM at the selected
address is shifted out on the SO pin. Data stored in the
memory at the next address can be read sequentially
by continuing to provide clock pulses to the slave. The
internal Address Pointer automatically increments to
the next higher address after each byte of data is
shifted out. When the highest address is reached, the
address counter rolls over to address 00h allowing the
read cycle to be continued indefinitely. The read
operation is terminated by raising the CS pin
(Figure 6-8).
6.3.3
Additionally, a page address begins with XXXX x000
and ends with XXXX x111. If the internal address
counter reaches XXXX
x111 and clock signals
continue to be applied to the chip, the address counter
will roll back to the first address of the page and
over-write any data that previously existed in those
locations.
Note:
EEPROM WRITE SEQUENCE
Prior to any attempt to write data to the MCP795WXX
EEPROM, the write enable latch must be set by issuing
the EEWREN instruction. This is done by setting CS low
and then clocking out the proper instruction into the
MCP795WXX. After all eight bits of the instruction are
transmitted, CS must be driven high to set the write
enable latch. If the write operation is initiated
immediately after the EEWREN instruction without CS
driven high, data will not be written to the array since
the write enable latch was not properly set.
After setting the write enable latch, the user may
proceed by driving CS low, issuing an EEWRITE
instruction, followed by the address, and then the data
to be written. Up to eight bytes of data can be sent to
the device before a write cycle is necessary. The only
restriction is that all of the bytes must reside in the
same page.
FIGURE 6-8:
EEPROM write operations are limited to
writing bytes within a single physical page,
regardless of the number of bytes
actually being written. Physical page
boundaries start at addresses that are
integer multiples of the page buffer size
(or ‘page size’) and, end at addresses that
are integer multiples of page size – 1. If an
EEWRITE command attempts to write
across a physical page boundary, the
result is that the data wraps around to the
beginning of the current page (overwriting
data previously stored there), instead of
being written to the next page as might be
expected. It is therefore necessary for the
application software to prevent EEPROM
write operations that would attempt to
cross a page boundary.
For the data to be actually written to the array, the CS
must be brought high after the Least Significant bit (D0)
of the nth data byte has been clocked in. If CS is driven
high at any other time, the write operation will not be
completed. Refer to Figure 6-9 and Figure 6-10 for
more detailed illustrations on the byte write sequence
and the page write sequence, respectively. While the
write is in progress, the STATUS register may be read
to check the status of the WIP, WEL, BP1 and BP0 bits.
Attempting to read a memory array location will not be
possible during a write cycle. Polling the WIP bit in the
STATUS register is recommended in order to
determine if a write cycle is in progress. When the write
cycle is completed, the write enable latch is reset.
EEPROM READ SEQUENCE
CS
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
SCK
Instruction
SI
0
0
0
0
0
Address Byte
0
1
1 A7 A6 A5 A4 A3 A2 A1 A0
Data Out
High-Impedance
SO
2011-2018 Microchip Technology Inc.
7
6
5
4
3
2
1
0
DS20002280E-page 48
MCP795W1X/MCP795W2X
FIGURE 6-9:
EEPROM BYTE WRITE SEQUENCE
CS
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
Twc
SCK
Instruction
SI
0
0
0
0
0
Address Byte
0
Data Byte
0 A7 A6 A5 A4 A3 A2 A1 A0
1
7
6
5
4
3
2
1
0
High-Impedance
SO
FIGURE 6-10:
EEPROM PAGE WRITE SEQUENCE
CS
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
SCK
Address Byte
Instruction
SI
0
0
0
0
0
0 1
Data Byte 1
0 A7 A6 A5 A4 A3 A2 A1 A0 7
6
5
4
3
2
1
0
CS
24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39
SCK
Data Byte 2
SI
6.4
7
6
5
4
3
2
Data Byte 3
1
0
7
6
Protected EEPROM
The MCP795WXX features a 128-bit protected
EEPROM block, organized as two 8-byte pages, that
requires a special unlock sequence to be followed in
order to write to the memory. The protected EEPROM
can be used for storing crucial information such as a
unique serial number. The MCP795WX1 and
MCP795WX2 include an EUI-48 and EUI-64 node
address, respectively, preprogrammed into the
protected EEPROM block. Custom programming is
also available.
The protected EEPROM block is located at addresses
0x00 to 0x0F and is accessed using the IDREAD and
IDWRITE instructions.
Note:
Attempts to access addresses outside of
0x00 to 0x0F will result in the
MCP795WXX ignoring the instruction.
2011-2018 Microchip Technology Inc.
5
4
3
2
6.4.1
Data Byte n (8 max)
1
0
7
6
5
4
3
2
1
0
PROTECTED EEPROM READ
SEQUENCE
The device is selected by pulling CS low. The 8-bit
IDREAD instruction is transmitted to the MCP795WXX
followed by an 8-bit address. See Figure 6-11 for more
details.
After the correct IDREAD instruction and address are
sent, the data stored in the protected EEPROM at the
selected address is shifted out on the SO pin. Data
stored in the memory at the next address can be read
sequentially by continuing to provide clock pulses to
the slave. The internal Address Pointer automatically
increments to the next higher address after each byte
of data is shifted out. When the highest address is
reached, the address counter rolls over to address 00h
allowing the read cycle to be continued indefinitely. The
read operation is terminated by raising the CS pin.
DS20002280E-page 49
MCP795W1X/MCP795W2X
6.4.2
PROTECTED EEPROM UNLOCK
SEQUENCE
The protected EEPROM block requires a special
unlock sequence to prevent unintended writes, utilizing
the UNLOCK instruction.
Before performing the unlock sequence, the WEL bit
must first be set by executing an EEWREN instruction
(see Section 6.3.1 “Write Enable and Write Disable”
for details).
To unlock the block, the following sequence must be
followed after setting the WEL bit:
1.
2.
3.
Execute an UNLOCK instruction with a data byte
of 0x55
Execute an UNLOCK instruction with a data byte
of 0xAA
Write the desired data bytes to the protected
EEPROM using the IDWRITE instruction
Figure 6-12 illustrates the sequence.
Note 1: Diverging from any step of the unlock
sequence may result in the EEPROM
remaining locked, the write operation
being ignored, and the WEL bit being
reset.
2: Unlocking the EEPROM is not required in
order to read from the memory.
An entire protected EEPROM page does not have to be
written in a single operation. However, the block is
locked after each write operation and must be unlocked
again to start a new Write command.
6.4.3
PROTECTED EEPROM WRITE
SEQUENCE
Prior to any attempt to write data to the MCP795WXX
protected EEPROM block, the write enable latch must
be set by issuing the EEWREN instruction, and then the
protected EEPROM unlock sequence must be
performed. The EEWREN instruction is issued by setting
CS low and then clocking out the proper instruction into
the MCP795WXX. After all eight bits of the instruction
are transmitted, CS must be driven high to set the write
enable latch.
Note:
Protected EEPROM write operations are
limited to writing bytes within a single
physical page, regardless of the number
of bytes actually being written. Physical
page boundaries start at addresses that
are integer multiples of the page buffer
size (or ‘page size’) and, end at addresses
that are integer multiples of page size – 1.
If an IDWRITE command attempts to write
across a physical page boundary, the
result is that the data wraps around to the
beginning of the current page (overwriting
data previously stored there), instead of
being written to the next page as might be
expected. It is therefore necessary for the
application software to prevent protected
EEPROM write operations that would
attempt to cross a page boundary.
For the data to be actually written to the array, the CS
must be brought high after the Least Significant bit (D0)
of the nth data byte has been clocked in. If CS is driven
high at any other time, the write operation will not be
completed. Refer to Figure 6-12 for more detailed
illustrations on the page write sequence. While the
write is in progress, the STATUS register may be read
to check the status of the WIP, WEL, BP1 and BP0 bits.
Attempting to read a memory array location will not be
possible during a write cycle. Polling the WIP bit in the
STATUS register is recommended in order to
determine if a write cycle is in progress. When the write
cycle is completed, the write enable latch is reset.
If an attempt is made to write to an address outside of
the 0x00 to 0x0F range, the MCP795WXX will not
execute the WRITE instruction, no data will be written,
and the device will immediately accept a new
command.
After setting the write enable latch and performing the
unlock sequence, the user may proceed by driving CS
low, issuing an IDWRITE instruction, followed by the
address, and then the data to be written. Up to 8 bytes
of data can be sent to the device before a write cycle is
necessary. The only restriction is that all of the bytes
must reside in the same page. Additionally, a page
address begins with XXXX x000 and ends with
XXXX x111. If the internal address counter reaches
XXXX x111 and clock signals continue to be applied to
the chip, the address counter will roll back to the first
address of the page and over-write any data that
previously existed in those locations.
2011-2018 Microchip Technology Inc.
DS20002280E-page 50
MCP795W1X/MCP795W2X
FIGURE 6-11:
PROTECTED EEPROM READ SEQUENCE
CS
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
SCK
Instruction
SI
0
0
1
1
0
Address Byte
0
1
1
0
0
0 A3 A2 A1 A0
0
Data Out
High-Impedance
7
SO
FIGURE 6-12:
6
5
4
3
2
1
0
PROTECTED EEPROM UNLOCK AND PAGE WRITE SEQUENCE
1. UNLOCK
Instruction
with 0x55
Data Byte
CS
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
SCK
Data Byte
Instruction
0
SI
2. UNLOCK
Instruction
with 0xAA
Data Byte
0
0
1
0
1
0
0
0
1
0
1
0
1
0
1
CS
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
SCK
Data Byte
Instruction
0
SI
0
0
1
0
1
0
1
0
0
1
0
1
0
1
0
3. IDWRITE
Instruction
CS
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
SCK
Address Byte
Instruction
SI
0
0
1
1
0
0
1
0
0
0
0
Data Byte 1
0 A3 A2 A1 A0
7
6
5
4
3
2
1
0
CS
24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39
SCK
Data Byte 2
SI
7
6
5
4
3
2
2011-2018 Microchip Technology Inc.
Data Byte 3
1
0
7
6
5
4
3
2
Data Byte n (8 max)
1
0
7
6
5
4
3
2
1
0
DS20002280E-page 51
MCP795W1X/MCP795W2X
6.5
Preprogrammed EUI-48 or EUI-64
Node Address
The MCP795WX1 and MCP795WX2 are programmed
at the factory with a globally unique node address
stored in the protected EEPROM block.
6.5.1
EUI-48 NODE ADDRESS
(MCP795WX1)
The 6-byte EUI-48™ node address value of the
MCP795WX1 is stored in protected EEPROM
locations 0x02 through 0x07, as shown in Figure 6-13.
The first three bytes are the Organizationally Unique
Identifier (OUI) assigned to Microchip by the IEEE
Registration Authority. The remaining three bytes are
the Extension Identifier, and are generated by
Microchip to ensure a globally-unique, 48-bit value.
6.5.1.1
Organizationally Unique Identifiers
(OUIs)
Each OUI provides roughly 16M (224) addresses. Once
the address pool for an OUI is exhausted, Microchip
will acquire a new OUI from IEEE to use for
programming this model. For more information on past
and current OUIs see “Organizationally Unique
Identifiers For Preprogrammed EUI-48 and EUI-64
Address Devices” Technical Brief (DS90003187).
Note:
The OUI will change as addresses are
exhausted. Customers are not guaranteed to receive a specific OUI and should
design their application to accept new
OUIs as they are introduced.
FIGURE 6-13:
Description
6.5.1.2
EUI-64 Support Using the
MCP795WX1
The preprogrammed EUI-48 node address of the
MCP795WX1 can easily be encapsulated at the
application level to form a globally unique, 64-bit node
address for systems utilizing the EUI-64 standard. This
is done by adding 0xFFFE between the OUI and the
Extension Identifier, as shown below.
Note:
6.5.2
As an alternative, the MCP795WX2
features an EUI-64 node address that can
be used in EUI-64 applications directly
without the need for encapsulation,
thereby simplifying system software. See
Section 6.5.2 “EUI-64 Node Address
(MCP795WX2)” for details.
EUI-64 NODE ADDRESS
(MCP795WX2)
The 8-byte EUI-64™ node address value of the
MCP795WX2 is stored in array locations 0x00 through
0x07, as shown in Figure 6-14. The first three bytes are
the Organizationally Unique Identifier (OUI) assigned
to Microchip by the IEEE Registration Authority.
The remaining five bytes are the Extension Identifier,
and are generated by Microchip to ensure a
globally-unique, 64-bit value.
Note:
In conformance with IEEE guidelines,
Microchip will not use the values 0xFFFE
and 0xFFFF for the first two bytes of the
EUI-64 Extension Identifier. These two
values are specifically reserved to allow
applications to encapsulate EUI-48
addresses into EUI-64 addresses.
EUI-48 NODE ADDRESS PHYSICAL MEMORY MAP EXAMPLE (MCP795WX1)
24-bit Organizationally
Unique Identifier
Data
00h
Array
Address
02h
04h
A3h
24-bit Extension
Identifier
12h
34h
56h
07h
Corresponding EUI-48™ Node Address: 00-04-A3-12-34-56
Corresponding EUI-64™ Node Address After Encapsulation: 00-04-A3-FF-FE-12-34-56
2011-2018 Microchip Technology Inc.
DS20002280E-page 52
MCP795W1X/MCP795W2X
FIGURE 6-14:
Description
EUI-64 NODE ADDRESS PHYSICAL MEMORY MAP EXAMPLE (MCP795WX2)
24-bit Organizationally
Unique Identifier
Data
00h
Array
Address
00h
04h
A3h
40-bit Extension
Identifier
12h
34h
56h
78h
90h
07h
Corresponding EUI-64™ Node Address: 00-04-A3-12-34-56-78-90
2011-2018 Microchip Technology Inc.
DS20002280E-page 53
MCP795W1X/MCP795W2X
7.0
PACKAGING INFORMATION
7.1
Package Marking Information
14-Lead SOIC (3.90 mm)
Example
MCP795W20
I/SL e3
1621256
14-Lead TSSOP
Example
795W20I
1621
256
1st Line Marking Codes
Part Number
SOIC
TSSOP
MCP795W20
MCP795W20
795W20T
MCP795W10
MCP795W10
795W10T
MCP795W21
MCP795W21
795W21T
MCP795W11
MCP795W11
795W11T
MCP795W22
MCP795W22
795W22T
MCP795W12
MCP795W12
795W12T
Note:
Legend: XX...X
Y
YY
WW
NNN
e3
*
Note:
T = Temperature grade
Customer-specific information
Year code (last digit of calendar year)
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code
JEDEC® designator for Matte Tin (Sn)
This package is RoHS compliant. The JEDEC designator ( e3 )
can be found on the outer packaging for this package.
In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
2011-2018 Microchip Technology Inc.
DS20002280E-page 54
MCP795W1X/MCP795W2X
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2011-2018 Microchip Technology Inc.
DS20002280E-page 55
MCP795W1X/MCP795W2X
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2011-2018 Microchip Technology Inc.
DS20002280E-page 56
MCP795W1X/MCP795W2X
! "# $ %
&" '
#
())$$$
) "
2011-2018 Microchip Technology Inc.
DS20002280E-page 57
MCP795W1X/MCP795W2X
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2011-2018 Microchip Technology Inc.
DS20002280E-page 58
MCP795W1X/MCP795W2X
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2011-2018 Microchip Technology Inc.
DS20002280E-page 59
MCP795W1X/MCP795W2X
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2011-2018 Microchip Technology Inc.
DS20002280E-page 60
MCP795W1X/MCP795W2X
APPENDIX A:
REVISION HISTORY
TABLE -1:
Revision A (11/2011)
Initial release of this document.
Revision B (03/2012)
Added detailed descriptions for Registers.
Revision C (06/2012)
Revised data sheet for 3V operation.
Revision D (06/2016)
Removed preliminary status; Updated overall content
for improved clarity; Added detailed descriptions of
registers; Expanded descriptions of peripheral
features; Updated block diagram and application
schematic; Defined names for all bits and registers,
and renamed the bits shown in Table 1 for clarification;
Renamed the DC characteristics shown in Table 2 for
clarification.
TABLE -2:
BIT NAME CHANGES
Old Bit Name
New Bit Name
CALSGN
TRIMSIGN
OSCON
OSCRUN
VBAT
PWRFAIL
LP
LPYR
SQWE
SQWEN
ALM0
ALM0EN
ALM1
ALM1EN
RS0
SQWFS0
RS1
SQWFS1
RS2
CRSTRIM
CALIBRATION
TRIMVAL
WDDEL
WDTDLYEN
WDTPLS
WDTPWS
WD
WDTPS
EVEN0
EVLEN
EVEN1
EVHEN
EVWDT
EVWDTEN
EVLDB
EVLPS
EVHS
EVHCS
ALM0C
ALM0MSK
ALM1C
ALM1MSK
DC CHARACTERISTIC NAME CHANGES
Old Name
Operating Current
Old Symbol
ICC Read
New Name
New Symbol
EEPROM Operating Current
ICCEERD
IDD Write
ICCEEWR
VBAT Current
IBAT
Timekeeping Backup Current
Standby Current
ICCS
VCC Data Retention Current (oscillator off)
IBATT
ICCDAT
Revision E (02/2018)
Added detailed description of OUIs.
2011-2018 Microchip Technology Inc.
DS20002280E-page 61
MCP795W1X/MCP795W2X
NOTES:
2011-2018 Microchip Technology Inc.
DS20002280E-page 62
MCP795W1X/MCP795W2X
THE MICROCHIP WEBSITE
CUSTOMER SUPPORT
Microchip provides online support via our website at
www.microchip.com. This website is used as a means
to make files and information easily available to
customers. Accessible by using your favorite Internet
browser, the website contains the following information:
Users of Microchip products can receive assistance
through several channels:
• Product Support – Data sheets and errata,
application notes and sample programs, design
resources, user’s guides and hardware support
documents, latest software releases and archived
software
• General Technical Support – Frequently Asked
Questions (FAQ), technical support requests,
online discussion groups, Microchip consultant
program member listing
• Business of Microchip – Product selector and
ordering guides, latest Microchip press releases,
listing of seminars and events, listings of
Microchip sales offices, distributors and factory
representatives
•
•
•
•
Distributor or Representative
Local Sales Office
Field Application Engineer (FAE)
Technical Support
Customers
should
contact
their
distributor,
representative or Field Application Engineer (FAE) for
support. Local sales offices are also available to help
customers. A listing of sales offices and locations is
included in the back of this document.
Technical support is available through the website
at: http://microchip.com/support
CUSTOMER CHANGE NOTIFICATION
SERVICE
Microchip’s customer notification service helps keep
customers current on Microchip products. Subscribers
will receive e-mail notification whenever there are
changes, updates, revisions or errata related to a
specified product family or development tool of interest.
To register, access the Microchip website at
www.microchip.com. Under “Support”, click on
“Customer Change Notification” and follow the
registration instructions.
2011-2018 Microchip Technology Inc.
DS20002280E-page 63
MCP795W1X/MCP795W2X
NOTES:
2011-2018 Microchip Technology Inc.
DS20002280E-page 64
MCP795W1X/MCP795W2X
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. Not every possible ordering
combination is listed below.
PART NO.
X
Device
EEPROM
Density
X
[X](1)
–
Protected Tape & Reel
Option
EEPROM
X
/XX
Temp.
Range
Package
Examples:
a)
Device:
MCP795W 1.8V - 3.6V SPI Serial RTCC with
Watchdog Timer and Event Detection
b)
EEPROM
Density:
1
2
=
=
1 Kbit EEPROM
2 Kbit EEPROM
c)
Protected
EEPROM:
0
1
2
=
=
=
Blank
Preprogrammed EUI-48™ address
Preprogrammed EUI-64™ address
d)
Tape & Reel
Option:
Blank
T
= Tube
= Tape & Reel
Temperature
Range:
I
=
Package:
SL
ST
= 14-Lead Plastic Small Outline (3.90 mm body)
= 14-Lead Plastic Thin Shrink Small Outline
(4.4 mm body)
-40C to +85C
2011-2018 Microchip Technology Inc.
MCP795W20-I/SL:
2 Kbit EEPROM,
Industrial
Temperature,
SOIC Package.
MCP795W10-I/ST: 1 Kbit EEPROM,
Industrial Temperature, TSSOP Package.
MCP795W21-I/SL: 2 Kbit EEPROM,
Preprogrammed
EUI-48™ address,
Industrial
Temperature,
SOIC Package.
MCP795W22-I/ST: 2 Kbit EEPROM,
Preprogrammed EUI-64™ address,
Industrial Temperature, TSSOP Package.
Note 1: Tape and Reel identifier only
appears in the catalog part number
description. This identifier is used
for ordering purposes and is not
printed on the device package.
Check with your Microchip Sales
Office for package availability with
the Tape and Reel option.
DS20002280E-page 65
MCP795W1X/MCP795W2X
NOTES:
2011-2018 Microchip Technology Inc.
DS20002280E-page 66
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
•
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights unless otherwise stated.
Microchip received ISO/TS-16949:2009 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
Trademarks
The Microchip name and logo, the Microchip logo, AnyRate, AVR,
AVR logo, AVR Freaks, BeaconThings, BitCloud, chipKIT, chipKIT
logo, CryptoMemory, CryptoRF, dsPIC, FlashFlex, flexPWR,
Heldo, JukeBlox, KEELOQ, KEELOQ logo, Kleer, LANCheck, LINK
MD, maXStylus, maXTouch, MediaLB, megaAVR, MOST, MOST
logo, MPLAB, OptoLyzer, PIC, picoPower, PICSTART, PIC32
logo, Prochip Designer, QTouch, RightTouch, SAM-BA, SpyNIC,
SST, SST Logo, SuperFlash, tinyAVR, UNI/O, and XMEGA are
registered trademarks of Microchip Technology Incorporated in
the U.S.A. and other countries.
ClockWorks, The Embedded Control Solutions Company,
EtherSynch, Hyper Speed Control, HyperLight Load, IntelliMOS,
mTouch, Precision Edge, and Quiet-Wire are registered
trademarks of Microchip Technology Incorporated in the U.S.A.
Adjacent Key Suppression, AKS, Analog-for-the-Digital Age, Any
Capacitor, AnyIn, AnyOut, BodyCom, CodeGuard,
CryptoAuthentication, CryptoCompanion, CryptoController,
dsPICDEM, dsPICDEM.net, Dynamic Average Matching, DAM,
ECAN, EtherGREEN, In-Circuit Serial Programming, ICSP, InterChip Connectivity, JitterBlocker, KleerNet, KleerNet logo, Mindi,
MiWi, motorBench, MPASM, MPF, MPLAB Certified logo, MPLIB,
MPLINK, MultiTRAK, NetDetach, Omniscient Code Generation,
PICDEM, PICDEM.net, PICkit, PICtail, PureSilicon, QMatrix,
RightTouch logo, REAL ICE, Ripple Blocker, SAM-ICE, Serial
Quad I/O, SMART-I.S., SQI, SuperSwitcher, SuperSwitcher II,
Total Endurance, TSHARC, USBCheck, VariSense, ViewSpan,
WiperLock, Wireless DNA, and ZENA are trademarks of Microchip
Technology Incorporated in the U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated in
the U.S.A.
Silicon Storage Technology is a registered trademark of Microchip
Technology Inc. in other countries.
GestIC is a registered trademark of Microchip Technology
Germany II GmbH & Co. KG, a subsidiary of Microchip Technology
Inc., in other countries.
All other trademarks mentioned herein are property of their
respective companies.
QUALITY MANAGEMENT SYSTEM
CERTIFIED BY DNV
© 2011-2018, Microchip Technology Incorporated, All Rights
Reserved.
ISBN: 978-1-5224-2726-1
== ISO/TS 16949 ==
2011-2018 Microchip Technology Inc.
DS20002280E-page 67
Worldwide Sales and Service
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Corporate Office
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Technical Support:
http://www.microchip.com/
support
Web Address:
www.microchip.com
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Tel: 61-2-9868-6733
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Tel: 91-80-3090-4444
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Fax: 905-695-2078
2011-2018 Microchip Technology Inc.
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Romania - Bucharest
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Sweden - Stockholm
Tel: 46-8-5090-4654
UK - Wokingham
Tel: 44-118-921-5800
Fax: 44-118-921-5820
DS20002280E-page 68
10/25/17
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