MD1210
High-Speed Dual MOSFET Driver
Features
General Description
•
•
•
•
•
•
•
•
•
•
Applications
The MD1210 is a high-speed, dual-MOSFET driver. It
is designed to drive high-voltage P-channel and
N-channel MOSFETs for medical ultrasound and other
applications requiring a high output current for a
capacitive load. The high-speed input stage of the
MD1210 can operate from 1.2V to 5V logic interface
with an optimum operating input signal range of 1.8V to
3.3V. An adaptive threshold circuit is used to set the
level translator switch threshold to the average of the
input logic 0 and logic 1 levels. The input logic levels
may be ground referenced even though the driver is
putting out bipolar signals. The level translator uses a
proprietary circuit, which provides DC coupling
together with high-speed operation.
•
•
•
•
•
•
VDD1, VDD2 and VH should be connected to the positive
supply voltage, and VSS1, VSS2 and VL should be
connected to 0V or ground. The GND pin is the logic
control input signal digital ground. The output stage is
capable of peak currents of up to ±2A, depending on
the supply voltages used and load capacitance
present.
6 ns Rise and Fall Time with 1000 pF Load
2A Peak Output Source/Sink Current
1.2V to 5V Input CMOS Compatible
4.5V to 13V Single Positive Supply Voltage
Smartlogic Threshold
Low-Jitter Design
Two Matched Channels
Outputs can Swing Below Ground
Low-Inductance Package
Thermally Enhanced Package
Medical Ultrasound Imaging
Piezoelectric Transducer Drivers
Non-Destructive Testing
PIN Diode Drivers
CCD Clock Drivers/Buffers
High-Speed Level Translators
The OE pin serves a dual purpose. First, its logic H
level is used to compute the threshold voltage level for
the channel input level translators. Second, when OE is
low, the outputs are disabled with the A output high and
the B output low. This assists in properly pre-charging
the AC coupling capacitors that may be used in series
in the gate drive circuit of an external PMOS and
NMOS transistor pair.
Package Type
12-lead QFN
(Top view)
12
1
See Table 2-1 for pin information.
2020 Microchip Technology Inc.
DS20005694A-page 1
MD1210
Functional Block Diagram
VDD1
OE
Level
Shifter
INA
Level
Shifter
VDD2
VH
OUTA
VSS2
VL
VH
VDD2
INB
OUTB
Level
Shifter
SUB
GND
VSS1
VDD1
VSS2
VDD2
VL
VH
MD1210
OE
OUTA
INA
OUTB
INB
GND VSS1
VSS2
VL
Simplified Block Diagram
DS20005694A-page 2
2020 Microchip Technology Inc.
MD1210
Typical Application Circuit
+12V
VDD1
OE
VDD2
0.47µF
VH
Level
Shifter
+100V
OUTA
INA
Level
Shifter
1.0µF
VSS2
3.3V CMOS
Logic Inputs
VL
VH
VDD2
10nF
To Piezoelectric
Transducer
10nF
-100V
INB
Level
Shifter
OUTB
1.0µF
TC6320TG
GND
2020 Microchip Technology Inc.
VSS1
VSS2
VL
MD1210
DS20005694A-page 3
MD1210
1.0
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings†
Supply Voltage—VDD1, VDD2, VH ...........................................................................................................–0.5V to +13.5V
Supply Voltage—VSS1, VSS2, VL ................................................................................................................................. 0V
Logic Input Levels .......................................................................................................................................–0.5V to +7V
Maximum Junction Temperature, TJ ................................................................................................................... +125°C
Operating Ambient Temperature, TA ...................................................................................................... –20°C to +85°C
Storage Temperature, TS ..................................................................................................................... –65°C to +150°C
ESD Rating (Note 1) .................................................................................................................................ESD Sensitive
† Notice: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only, and functional operation of the device at those or any other conditions above those
indicated in the operational sections of this specification is not intended. Exposure to maximum rating conditions for
extended periods may affect device reliability.
Note 1: Device is ESD sensitive. Handling precautions are recommended.
DC ELECTRICAL CHARACTERISTICS
Electrical Specifications: Over operating conditions unless otherwise specified, VH = VDD1 = VDD2 = 12V,
VL = VSS1 = VSS2 = 0V, VOE = 3.3V, TA = 25°C.
Parameter
Sym.
Min.
Typ.
Max.
Unit
VDD1, VDD2
4.5
—
13
V
Output High Supply Voltage
VH
VSS +2
—
VDD
V
Output Low Supply Voltage
VL
0
—
VDD –2
V
VDD1 Quiescent Current
IDD1Q
—
0.55
—
mA
VDD2 Quiescent Current
IDD2Q
—
—
10
µA
VH Quiescent Current
IHQ
—
—
10
µA
VDD1 Average Current
IDD1
—
0.88
—
mA
VDD2 Average Current
IDD2
—
6.6
—
mA
IH
—
23
—
mA
Input Logic Voltage High
VIH
VOE–0.3
—
5
V
Input logic Voltage Low
VIL
0
—
0.3
V
Input Logic Current High
IIH
—
—
1
µA
Input Logic Current Low
IIL
—
—
1
µA
Supply Voltage
VH Average Current
Conditions
No input transitions
One channel on at 5 MHz,
no load
For logic inputs INA and INB
OE Input Logic Voltage High
VIH
1.2
—
5
V
OE Input Logic Voltage Low
VIL
0
—
0.3
V
OE Input Logic Impedance
to GND
RIN
12
20
30
kΩ
Logic Input Capacitance
CIN
—
5
10
pF
All inputs
Output Sink Resistance
Output Source Resistance
Peak Output Sink Current
Peak Output Source Current
DS20005694A-page 4
For logic input OE
RSINK
—
—
12.5
Ω
ISINK = 50 mA
RSOURCE
—
—
12.5
Ω
ISOURCE = 50 mA
ISINK
—
2
—
A
ISOURCE
—
2
—
A
2020 Microchip Technology Inc.
MD1210
AC ELECTRICAL CHARACTERISTICS
Electrical Specifications: VH = VDD1 = VDD2 = 12V, VL = VSS1 = VSS2 = 0V, VOE = 3.3V, TA = 25°C.
Parameter
Sym.
Min.
Typ.
Max.
Unit
Inputs or OE Rise and Fall
Time
tirf
—
—
10
ns
Propagation Delay when
Output is from Low to High
tPLH
—
7
—
ns
Propagation Delay when
Output is from High to Low
tPHL
—
7
—
ns
Propagation Delay OE
to Outputs
tPOE
—
9
—
ns
Output Rise Time
tr
—
6
—
ns
Output Fall Time
tf
—
6
—
ns
Rise and Fall Time Matching
l tr–tf l
—
1
—
ns
Propagation Low to High and
High-to-Low Matching
l tPLH–tPHL l
—
1
—
ns
Δtdm
—
±2
—
ns
Propagation Delay Match
Conditions
Logic input edge speed
requirement
CLOAD = 1000 pF, input signal
rise/fall time of 2 ns (See Timing Diagram and Figure 3-1.)
CLOAD = 1000 pF, input signal
rise/fall time of 2 ns (See Timing Diagram.)
For each channel
Device-to-device delay match
TEMPERATURE SPECIFICATIONS
Parameter
Sym.
Min.
Typ.
Max.
Unit
Maximum Junction Temperature
TJ
—
—
+125
°C
Operating Ambient Temperature
TA
–20
—
+85
°C
Storage Temperature
TS
–65
—
+150
°C
Conditions
TEMPERATURE RANGE
PACKAGE THERMAL RESISTANCE
12-lead QFN
JA
—
32
—
°C/W
Thermal Resistance to Case
θJC
—
7
—
°C/W
Note 1:
Note 1
1 oz. 4-layer 3” x 4” PCB with thermal pad and thermal via array
2020 Microchip Technology Inc.
DS20005694A-page 5
MD1210
Timing Diagram
3.3V
50%
IN
50%
0V
tPLH
tPHL
90%
90%
OUT
TABLE 1-1:
10%
10%
0V
tf
tr
TRUTH FUNCTION TABLE
Logic Input
Output
OE
INA
INB
OUTA
OUTB
H
L
L
VH
VH
H
L
H
VH
VL
H
H
L
VL
VH
H
H
H
VL
VL
L
X
X
VH
VL
DS20005694A-page 6
2020 Microchip Technology Inc.
MD1210
2.0
PIN DESCRIPTION
The details on the pins of MD1210 are listed on
Table 2-1. See Package Type for the location of pins.
TABLE 2-1:
PIN FUNCTION TABLE
Pin Number
Pin Name
1
INA
Logic input. Controls OUTA when OE is high. Input logic high will cause the output to
swing to VL. Input logic low will cause the output to swing to VH. (See Figure 3-2.)
2
VL
Supply voltage for N-channel output stage
3
INB
Logic input. Controls OUTB when OE is high. Input logic high will cause the output to
swing to VL. Input logic low will cause the output to swing to VH. (See Figure 3-2.)
4
GND
Logic input ground reference
5
VSS1
Low-side analog circuit and level shifter supply voltage. Should be at the same potential
as VSS2. Thermal Pad and Pin 5 must be connected externally.
6
VSS2
Low-side gate drive supply voltage.
7
OUTB
Output driver. Swings from VH to VL. Intended to drive the gate of an external
N-channel MOSFET via a series capacitor. When OE is low, the output is disabled.
OUTB will swing to VL turning off the external N-channel MOSFET.
8
VH
9
OUTA
Output driver. Swings from VH to VL. Intended to drive the gate of an external
P-channel MOSFET via a series capacitor. When OE is low, the output is disabled.
OUTA will swing to VH, turning off the external P-channel MOSFET.
10
VDD2
High-side gate drive supply voltage.
11
VDD1
High-side analog circuit and level shifter supply voltage. Should be at the same
potential as VDD2.
12
OE
Thermal Pad
Description
Supply voltage for P-channel output stage
Output-enable logic input. When OE is high, (VOE + VGND)/2 sets the threshold transition between logic level high and low for INA and INB. When OE is low, OUTA is at VH
and OUTB is at VL regardless of INA and INB.
Should be connected externally to pin 5
2020 Microchip Technology Inc.
DS20005694A-page 7
MD1210
APPLICATION INFORMATION
For proper operation of the MD1210, low-inductance
bypass capacitors should be used on the various
supply pins. The GND input pin should be connected to
the digital ground. The INA, INB and OE pins should be
connected to their logic source with a swing of GND to
logic level high, which is 1.2V to 5V. Good trace
practices should be followed corresponding to the
desired operating speed. The internal circuitry of the
MD1210 is capable of operating up to 100 MHz, with
the primary speed limitation being the loading effect of
the load capacitance. Because of this speed and the
high transient currents due to the capacitive loads, the
bypass capacitors should be as close to the chip pins
as possible. The VSS1, VSS2, and VL pins should have
direct low-inductance feed-through connections to a
ground plane. The power connections VDD1 and VDD2
should have a ceramic bypass capacitor to the ground
plane with short leads and decoupling components to
prevent resonance in the power leads. A common
capacitor and voltage source may be used for these
two pins, which should always have the same DC
voltage applied. For applications sensitive to jitter and
noise, separate decoupling networks may be used for
VDD1 and VDD2.
VTH vs. VOE
2.0
VTH (volts)
3.0
VOE/2
1.5
1.0
0.6V
0.5
0
1.0
2.0
3.0
4.0
5.0
VOE (volts)
FIGURE 3-2:
Logic Input Threshold.
Pay particular attention to minimizing trace lengths and
using sufficient trace width to reduce inductance.
Surface-mount components are highly recommended.
Since the output impedance of this driver is very low, in
some cases, it may be desirable to add a small series
resistor in series with the output signal to obtain better
waveform integrity at the load terminals.
Propagation Delay (ns)
Propagation Delay vs. Logic Voltage
10
9.0
8.0
7.0
6.0
1
1.5
2.0
2.5
3.0
3.5
Logic Voltage (V)
FIGURE 3-1:
This will reduce the output voltage slew rate at the
terminals of a capacitive load. Focus on parasitic
coupling from the driver output to the input signal
terminals. This feedback may cause oscillations or
spurious waveform shapes on the edges of signal
transitions. Since the input operates with signals down
to 1.2V, even small coupled voltages may cause
problems. The use of a solid ground plane and good
power and signal layout practices will prevent this
problem. Make sure that the circulating ground return
current from a capacitive load will not react with
common inductance and cause noise voltages in the
input logic circuitry.
Propagation Delay.
The VH and VL can draw fast transient currents of up to
2A, so they should be provided with a suitable bypass
capacitor located next to the chip pins. A ceramic
capacitor of up to 1 µF may be appropriate, with a
series ferrite bead to prevent resonance in the power
supply lead coming to the capacitor.
DS20005694A-page 8
2020 Microchip Technology Inc.
MD1210
4.0
PACKAGING INFORMATION
4.1
Package Marking Information
Legend: XX...X
Y
YY
WW
NNN
e3
*
Note:
12-lead QFN
Example
XXXXXX
XXXXXX
e3 YYWW
NNN
MD
1210K6
e3 2020
784
Product Code or Customer-specific information
Year code (last digit of calendar year)
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code
Pb-free JEDEC® designator for Matte Tin (Sn)
This package is Pb-free. The Pb-free JEDEC designator ( e3 )
can be found on the outer packaging for this package.
In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available characters
for product code or customer-specific information. Package may or not include
the corporate logo.
2020 Microchip Technology Inc.
DS20005694A-page 9
MD1210
Note: For the most current package drawings, see the Microchip Packaging Specification at www.microchip.com/packaging.
DS20005694A-page 10
2020 Microchip Technology Inc.
MD1210
APPENDIX A:
REVISION HISTORY
Revision A (January 2020)
• Converted Supertex Doc# DSFP-MD1210 to
Microchip DS20005694A
• Updated the quantity of the 12-lead QFN K6 package from 3000/Reel to 5000/Reel to align it with
the actual BQM
• Made minor text changes throughout the document
2020 Microchip Technology Inc.
DS20005694A-page 11
MD1210
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, contact your local Microchip representative or sales office.
XX
PART NO.
Device
-
Package
Options
X
-
Environmental
X
Media Type
Device:
MD1210
=
High-Speed Dual MOSFET Driver
Package:
K6
=
12-lead (4x4) QFN
Environmental:
G
=
Lead (Pb)-free/RoHS-compliant Package
Media Type:
(blank)
=
5000/Reel for a K6 Package
DS20005694A-page 12
Example:
a)
MD1210K6-G:
High-Speed Dual MOSFET Driver 12lead (4x4) QFN, 5000/Reel
2020 Microchip Technology Inc.
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•
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2020 Microchip Technology Inc.
ISBN: 978-1-5224-5501-1
DS20005694A-page 13
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DS20005694A-page 14
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05/14/19
