MD1715
2-Channel 5-Level High-Speed Ultrasound Driver IC
Features
General Description
•
•
•
•
•
•
•
•
•
•
The MD1715, paired with Microchip’s TC8020, forms a
2-channel five-level high-voltage high-speed transmit
pulser chip set. The chip set is designed for medical
ultrasound imaging applications but can also be used
for metal flaw detection, NDT and piezoelectric
transducer drivers.
Advanced CMOS Technology
±4.75 to 12.9V Gate Drive Voltage
2A Output Source and Sink Current
6.5 ns Rise and Fall Time with 1 nF Load
10 ns Propagation Delay
±2 ns Matched Delay Times
12 Matched Channels
1.8V to 3.3V CMOS Logic Interface
Smart Logic Threshold
Low-inductance Package
The MD1715 is a 2-channel logic controller circuit with
12 low-impedance MOSFET gate drivers. There are
two sets of control logic inputs—one for Channel A and
one for Channel B. Each channel consists of three pairs
of MOSFET gate drivers. These drivers are designed to
match the drive requirements of Microchip’s TC8020.
Applications
•
•
•
•
The TC8020 is the output stage of the pulser, with six
pairs of MOSFETs. Each pair consists of a P-channel
and an N-channel MOSFET. They are designed to
have the same impedance and can provide typical
peak currents of ±3.5A at 200V.
Medical Ultrasound Imaging
Piezoelectric Transducer Drivers
Metal Flaw Detection
Non-destructive Testing (NDT)
Package Type
40-lead QFN
(Top view)
40
1
See Table 2-1 for pin information.
2018 Microchip Technology Inc.
DS20005921A-page 1
MD1715
Functional Block Diagram
+12V
+12V
AVDD
VDD1
+12V
VPP1
VDD2
SP1
VDD2
OP1
GP1
DP1
VDD2
DN1
ON1
GN1
VNN1
SN1
High Speed
Gate Buffers
VPP2
VLL/EN
SP2
VDD1
OP2
SEL
POS
NEG
Control
Logic
and
Level
Translation
GP2
DP2
VDD1
DN2
100Ω
ON2
GN2
VNN2
SN2
GND
High Speed
Gate Buffers
SP3
OP3
GP3
DP3
VSS
VDD1
DN3
ON3
SN3
MD1715
1 OF 2-CH
GND
PAD
AVSS
-12V
DS20005921A-page 2
GN3
VSS
TC8020
6 of 12-FETs
PAD
-12V
2018 Microchip Technology Inc.
MD1715
Typical Application Circuit
+3.3V
+12V
+12V
+12V
VLL/EN
AVDD
VDD1
VDD2
GP1
OP1A
VPP2
VPP1
SP6 SP3 SP5 SP2
SP4 SP1
DP1
10nF
GN1
ON1A
DN1
10nF
GP2
OP2A
DP2
10nF
1.8 to 3.3V
CMOS
Input Logic
GN2
SELA
ON2A
POSA
OP3A
GP3
NEGA
ON3A
GN3
OP1B
GP4
POSB
DN2
10nF
MD1715
DP3
TC8020
ON1B
SELB
OP2B
GN4
DN4
10nF
GP5
DP5
10nF
GN5
ON2B
AGND GND
AVSS(SUB)
VSS
-12V
-12V
2018 Microchip Technology Inc.
GP6
ON3B
GN6
TX(B)
DN5
10nF
OP3B
DN3
DP4
10nF
NEGB
TX(A)
DP6
DN6
PAD SN6 SN3 SN5 SN2 SN4 SN1
VNN2
VNN1
DS20005921A-page 3
MD1715
1.0
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings†
GND and AGND, Ground .......................................................................................................................................... 0V
Logic Input Pin, VLL ................................................................................................................................ –0.5V to +5.5V
Positive Gate Drive Supply, AVDD, VDD1, VDD2 ................................................................................... –0.5V to +14.5V
Negative Gate Drive Supply, AVSS, VSS ............................................................................................... –14.5V to +0.5V
Operating Junction Temperature, TJ ....................................................................................................... 0°C to +125°C
Storage Temperature, TS ..................................................................................................................... –65°C to +150°C
Power Dissipation:
40-lead QFN (Note 1) ................................................................................................................................. 1.3W
† Notice: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only, and functional operation of the device at those or any other conditions above those
indicated in the operational sections of this specification is not intended. Exposure to maximum rating conditions for
extended periods may affect device reliability.
Note 1: 1 oz. four-layer 3 inches x 4 inches PCB
OPERATING SUPPLY VOLTAGES AND CURRENTS
Electrical Specifications for Operating Supply Currents: Over operating conditions unless otherwise specified,
VLL = 3.3V, AVDD = VDD1 = VDD2 = +12V, AVSS = VSS = –12V, TA = 25°C
Parameter
Logic Supply
Positive Analog Supply
Sym.
Min.
Typ.
Max.
Unit
VLL
1.8
3.3
3.6
V
AVDD
8
—
12.9
V
Positive Gate Drive Supply
VDD2, VDD1
4.75
—
12.9
V
Negative Gate Drive Supply
AVSS, VSS
–12.9
—
–4.75
V
IVLL
—
10
—
µA
AVDD Power-down Current
IAVDDQ
—
0.4
—
mA
VSS Power-down Current
IVSSQ
—
0.1
—
mA
Logic Reference Current
Conditions
AVDD ≥ (VDD1 or VDD2)
VDD1 Power-down Current
IVDD1Q
—
10
25
µA
VDD2 Power-down Current
IVDD2Q
—
10
25
µA
AVDD Power-up Current
IAVDDEN
—
2
3
mA
VSS Power-up Current
IVSSEN
—
0.7
1
mA
VLL = 3.3V
EN = 0, all inputs low
EN = 0, all inputs low
EN = 1, all inputs low
VDD1 Power-up Current
IVDD1EN
—
10
—
µA
VDD2 Power-up Current
IVDD2EN
—
10
—
µA
AVDD CW 5 MHz Current
IAVDDCW
—
10
—
VSS CW 5 MHz Current
IVSSCW
—
5
—
mA A and B Channels on
at 5 MHz, no load,
mA V 1 = 12V, V 2 = 5V
DD
DD
VDD1 CW 5 MHz Current
IVDD1CW
—
25
—
A and B Channels on
mA at 5 MHz, no load,
VDD1 = 5V, VDD2 = 12V
VDD2 CW 5 MHz Current
IVDD2CW
—
25
—
A and B Channels on
mA at 5 MHz, no load,
VDD1 = 12V, VDD2 = 5V
DS20005921A-page 4
EN = 1, all inputs low
2018 Microchip Technology Inc.
MD1715
DC ELECTRICAL CHARACTERISTICS
Parameter
Sym.
Min.
Typ.
Max.
Unit
5
6
Ω
Conditions
P-CHANNEL AND N-CHANNEL GATE DRIVER OUTPUTS
Output Sink Resistance
Output Source Resistance
Peak Output Sink Current
Peak Output Source Current
P-Channel
N-Channel
P-Channel
N-Channel
P-Channel
N-Channel
P-Channel
N-Channel
RSINK
RSOURCE
ISINK
ISOURCE
—
ISINK = 100 mA
—
5
6
Ω
ISINK = 100 mA
—
5
6
Ω
ISOURCE = 100 mA
—
5
6
Ω
ISOURCE = 100 mA
1.7
2
—
A
1.7
2
—
A
1.7
2
—
A
1.7
2
—
A
—
0.3
V
LOGIC INPUTS
Chip Disable Low Voltage
VENL
0
Input Logic High Voltage
VIH
0.8 VLL
—
VLL
V
Input Logic Low Voltage
VIL
0
—
0.2 VLL
V
Input Logic High Current
IIH
—
—
1
µA
Input Logic Low Current
IIL
–1
—
—
µA
VLL/EN is a dual function
pin
AC ELECTRICAL CHARACTERISTICS
Electrical Specifications: Over operating conditions unless otherwise specified, VLL = 3.3V,
AVDD = VDD1 = VDD2 = +12V, AVSS = VSS = –12V, TA = 25°C
Parameter
Sym.
Min.
Typ.
Max.
Unit
Input Rise and Fall Time
tirf
—
—
10
ns
Logic input edge speed
requirement
Output Rise Time
tr
—
6.5
—
ns
1 nF load, input signal
rise/fall time 2 ns (Timing
Waveforms)
Output Fall Time
tf
—
6.5
—
ns
Output Rise Delay
tdr
—
10
—
ns
Output Fall Delay
tdf
—
10
—
ns
Rise and Fall Time Matching
|tr–tf|
—
1
—
—
Propagation Delay Matching
|tdr–tdf|
—
1
—
—
Delay Time Matching
tdm
—
±2
—
ns
Channel to channel and
device to device
Output Jitter
∆tj
—
20
—
ps
VDD = 10V
IC Enable Time
tEN_ON
—
25
50
μs
IC Disable Time
tEN_OFF
—
0.5
2
μs
HD2
–40
—
—
dB
Second Harmonic Distortion
2018 Microchip Technology Inc.
Conditions
For each channel
DS20005921A-page 5
MD1715
TEMPERATURE SPECIFICATIONS
Parameter
Sym.
Min.
Typ.
Max.
Unit
Operating Junction Temperature
TJ
–0
—
+125
°C
Storage Temperature
TS
–65
—
+150
°C
JA
—
24
—
°C/W
Conditions
TEMPERATURE RANGE
PACKAGE THERMAL RESISTANCE
40-lead QFN
DS20005921A-page 6
2018 Microchip Technology Inc.
MD1715
Timing Waveforms
Input
50%
50%
tdf
tdr
VDD
90%
Output
10%
0V
tr
2018 Microchip Technology Inc.
tf
DS20005921A-page 7
MD1715
2.0
PIN DESCRIPTION
The details on the pins of MD1715 are listed on
Table 2-1. See Package Type for the location of pins.
TABLE 2-1:
PIN FUNCTION TABLE
Pin Number
Pin Name
1
SELA
SEL input logic control for Channel A. See Table 3-1.
2
POSA
POS input logic control for Channel A. See Table 3-1.
3
NEGA
NEG input logic control for Channel A. See Table 3-1.
4
VLL/EN
Logic High reference voltage and chip enable input
5
AVDD
Positive supply voltage of analog circuitry. AVDD should be at the same or higher
potential than the highest voltages of VDD1 or VDD2.
6
AGND
Digital ground
7
AVSS
Negative supply voltage of analog circuitry and connection of IC substrate.
Should be at the same potential as VSS.
8
SELB
SEL input logic control for Channel B. See Table 3-2.
9
POSB
POS input logic control for Channel B. See Table 3-2.
10
NEGB
NEG input logic control for Channel B. See Table 3-2.
11
VDD2
Positive supply voltage of the gate drivers for the output stages OP1 and ON1 in
Channel A and Channel B. VDD2 can be at a different voltage than VDD1.
12
OP1B
First output P-channel gate driver for Channel B
13
VDD1
Positive supply voltage of the gate drivers for the output stages OP2, ON2 and
ON3 in Channel A and Channel B. VDD1 can be at a different voltage than
VDD2.
14
GND
Power ground
15
OP2B
Second output P-channel gate driver for Channel B
16
VDD2
Positive supply voltage of the gate drivers for the output stages OP1 and ON1 in
Channel A and Channel B. VDD2 can be at a different voltage than VDD1.
17
ON1B
First output N-channel gate driver for Channel B
18
GND
Power ground
19
VDD1
Positive supply voltage of the gate drivers for the output stages OP2, ON2 and
ON3 in Channel A and Channel B. VDD1 can be at a different voltage than
VDD2.
20
ON2B
Second output N-channel gate driver for Channel B
21
GND
Power ground
22
ON3B
Damping output N-channel gate driver for Channel B
23
VSS
24
OP3B
Damping output P-channel gate driver for Channel B
25
GND
Power ground
26
VSS
Negative supply voltage for gate drive of OP3. Should be the same voltage as
AVSS.
27
OP3A
Damping output P-channel gate driver for Channel A
28
GND
Power ground
DS20005921A-page 8
Description
Negative supply voltage for the gate drive of OP3. Should be the same voltage as
AVSS.
2018 Microchip Technology Inc.
MD1715
TABLE 2-1:
PIN FUNCTION TABLE (CONTINUED)
Pin Number
Pin Name
29
GND
Power ground
30
ON3A
Damping output N-channel gate driver for Channel A
31
ON2A
Second output N-channel gate driver for Channel A
32
VDD1
Positive supply voltage of the gate drivers for the output stages OP2, ON2 and
ON3 in Channel A and Channel B. VDD1 can be at a different voltage than
VDD2.
33
GND
Power ground
34
ON1A
First output N-channel gate driver for Channel A
35
VDD2
Positive supply voltage of the gate drivers for the output stages OP1 and ON1 in
Channel A and Channel B. VDD2 can be at a different voltage than VDD1.
36
OP2A
Second output P-channel gate driver for Channel A
37
GND
Power ground
38
VDD1
Positive supply voltage of the gate drivers for the output stages OP2, ON2 and
ON3 in Channel A and Channel B. VDD1 can be at a different voltage than
VDD2.
39
OP1A
First output P-channel gate driver for Channel A
40
VDD2
Positive supply voltage of the gate drivers for the output stages OP1 and ON1 in
Channel A and Channel B. VDD2 can be at a different voltage than VDD1.
Center Pad
Thermal Pad
2018 Microchip Technology Inc.
Description
IC substrate, must connect to AVSS externally
DS20005921A-page 9
MD1715
ON2A
VDD1
GND
ON1A
VDD2
OP2A
GND
VDD1
OP1A
VDD2
NC
NC
SP2
NC
SP1
NC
VSUB
NC
SN1
NC
SN2
NC
GP1
FUNCTIONAL DESCRIPTION
GP2
3.0
GN1
DN1
GN2
DP1
NC
DN2
SELA
ON3A
POSA
GND
GN3
DP2
NEGA
GND
GP3
DN3
OP3A
NC
DP3
VLL/EN
VSS
SN3
GND
SN6
AVSS
OP3B
NC
DN6
SELB
VSS
GP6
DP6
POSB
ON3B
GN6
DN5
NEGB
GND
NC
DP5
GN5
DN4
GN4
DP4
FIGURE 3-1:
DS20005921A-page 10
SP3
TX(B)
NC
NC
SP5
NC
SP6
SP4
NC
VSUB
NC
SN4
NC
SN5
NC
TC8020
GP5
ON2B
VDD1
GND
ON1B
VDD2
OP2B
GND
VDD2
OP1B
VDD1
MD1715
AGND
GP4
AVDD
TX(A)
Circuit Pin Layout.
2018 Microchip Technology Inc.
MD1715
TABLE 3-1:
TRUTH FUNCTION TABLE FOR CHANNEL A
Logic Inputs A
NEGA
SP1
to
DP1
SN1
to
DN1
SP2
to
DP2
SN2
to
DN2
SP3
to
DP3
SN3
to
DN3
0
0
OFF
OFF
OFF
OFF
ON
ON
0
0
1
OFF
OFF
OFF
ON
OFF
OFF
0
1
0
OFF
OFF
ON
OFF
OFF
OFF
1
0
1
1
OFF
OFF
OFF
OFF
OFF
OFF
1
1
0
0
OFF
OFF
OFF
OFF
ON
ON
1
1
0
1
OFF
ON
OFF
OFF
OFF
OFF
1
1
1
0
ON
OFF
OFF
OFF
OFF
OFF
1
1
1
1
OFF
OFF
OFF
OFF
OFF
OFF
EN
SELA
POSA
1
0
1
1
TABLE 3-2:
TRUTH FUNCTION TABLE FOR CHANNEL B
Logic Inputs B
SELB
POSB
NEGB
SP4
to
DP4
1
0
0
0
OFF
OFF
OFF
1
0
0
1
OFF
OFF
OFF
ON
OFF
OFF
1
0
1
0
OFF
OFF
ON
OFF
OFF
OFF
1
0
1
1
OFF
OFF
OFF
OFF
OFF
OFF
1
1
0
0
OFF
OFF
OFF
OFF
ON
ON
1
1
0
1
OFF
ON
OFF
OFF
OFF
OFF
1
1
1
0
ON
OFF
OFF
OFF
OFF
OFF
EN
SN4
to
DN4
SP5
to
DP5
SN5
to
DN5
SP6
to
DP6
SN6
to
DN6
OFF
ON
ON
1
1
1
1
OFF
OFF
OFF
OFF
OFF
OFF
0
X
X
X
OFF
OFF
OFF
OFF
ON
ON
0→1
0
0
0
1→0
0
0
0
2018 Microchip Technology Inc.
EN transitions from low to high or high to low should occur at all logic
inputs low.
DS20005921A-page 11
MD1715
4.0
PACKAGING INFORMATION
4.1
Package Marking Information
40-lead QFN
XXXXXXX
XX e3
YYWWNNN
Legend: XX...X
Y
YY
WW
NNN
e3
*
Note:
DS20005921A-page 12
Example
MD1715
K6 e3
1836985
Product Code or Customer-specific information
Year code (last digit of calendar year)
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code
Pb-free JEDEC® designator for Matte Tin (Sn)
This package is Pb-free. The Pb-free JEDEC designator ( e3 )
can be found on the outer packaging for this package.
In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available characters
for product code or customer-specific information. Package may or not include
the corporate logo.
2018 Microchip Technology Inc.
MD1715
Note: For the most current package drawings, see the Microchip Packaging Specification at www.microchip.com/packaging.
2018 Microchip Technology Inc.
DS20005921A-page 13
MD1715
NOTES:
DS20005921A-page 14
2018 Microchip Technology Inc.
MD1715
APPENDIX A:
REVISION HISTORY
Revision A (January 2018)
• Converted Supertex Doc# DSFP-MD1715 to
Microchip DS20005921A
• Changed the package marking format
• Changed the quantity of the 40-lead VQFN K6
M935 package from 2000/Reel to 3000/Reel
• Made minor text changes throughout the
document
2018 Microchip Technology Inc.
DS20005921A-page 15
MD1715
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, contact your local Microchip representative or sales office.
XX
PART NO.
Device
Device:
-
Package
Options
MD1715
X
-
Environmental
=
X
Media Type
2-Channel 5-Level High-Speed Ultrasound
Driver IC
Package:
K6
=
40-lead VQFN
Environmental:
G
=
Lead (Pb)-free/RoHS-compliant Package
Media Types:
(blank)
=
490/Tray for a K6 Package
M935
=
3000/Reel for a K6 Package
DS20005921A-page 16
Examples:
a) MD1715K6-G:
2-Channel 5-Level HighSpeed Ultrasound Driver
IC, 40-lead VQFN,
490/Tray
b) MD1715K6-G-M935:
2-Channel 5-Level HighSpeed Ultrasound Driver
IC, 40-lead VQFN,
3000/Reel
2018 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
•
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
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FITNESS FOR PURPOSE. Microchip disclaims all liability
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headquarters, design and wafer fabrication facilities in Chandler and
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are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
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CERTIFIED BY DNV
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© 2018, Microchip Technology Incorporated, All Rights Reserved.
ISBN: 978-1-5224-2591-5
== ISO/TS 16949 ==
2018 Microchip Technology Inc.
DS20005921A-page 17
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DS20005921A-page 18
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2018 Microchip Technology Inc.
10/25/17