MD1822K6-G

MD1822 High-Speed 4-Channel MOSFET Driver with Two Inverting and Two Non-Inverting Outputs Features General Description • • • • • • • • • The MD1822 is a high-speed, four-channel MOSFET driver designed to drive high-voltage P-channel and N-channel MOSFETs for medical ultrasound applications and other applications requiring a highoutput current for a capacitive load. The high-speed input stage of the MD1822 can operate from a 1.8V to 5V logic interface with an optimum operating input signal range of 1.8V to 3.3V. An adaptive threshold circuit is used to set the level translator switch threshold to the average of the input logic 0 and logic 1 levels. The input logic levels may be ground referenced even though the driver is putting out bipolar signals. The level translator uses a proprietary circuit, which provides DC coupling together with high-speed operation. Mixed Inversion MOSFET Driver 6 ns Rise and Fall Time 2A Peak Output Source-and-Sink Current 1.8V to 5V Input CMOS Compatible 5V to 10V Total Supply Voltage Smart Logic Threshold Low-Jitter Design Four Matched Channels Drives Two P-Channel and Two N-Channel MOSFETs • Outputs can swing below Ground • Low-Inductance, Quad-Flat No-Lead Package • High-Performance, Thermally Enhanced Packaging Applications • • • • • • Medical Ultrasound Imaging Piezoelectric Transducer Drivers Non-Destructive Testing PIN Diode Driver CCD Clock Driver/Buffer High-Speed Level Translator The output stage of the MD1822 has separate power connections, enabling the output signal L and H levels to be chosen independently from the supply voltages used for the majority of the circuit. As an example, the input logic levels may be 0V and 1.8V, the control logic may be powered by +5V and –5V, and the output L and H levels may be varied anywhere over the range of –5V to +5V. The output stage is capable of peak currents of up to ±2A, depending on the supply voltages used and load capacitance present. The PE pin serves a dual purpose. First, its logic H level is used to compute the threshold voltage level for the channel input level translators. (See Figure 3-1.) Second, when PE is low, the outputs are disabled, with the A and C outputs high and the B and D outputs low. This assists in properly precharging the AC coupling capacitors that may be used in series in the gate drive circuit of an external PMOS and NMOS transistor pair. Package Type 16-lead QFN (Top view) 1 See Table 2-1 for pin information.  2018 Microchip Technology Inc. DS20005706A-page 1 MD1822 Functional Block Diagrams MD1822 VH VDD PE OUTA INA OUTB INB OUTC INC OUTD IND VSS GND MD1822 PE Level Shifter INA Level Shifter VDD VDD OUTB VDD VH OUTC VDD Level Shifter GND DS20005706A-page 2 VL Level Shifter VSS IND VL VH Level Shifter VSS INC VH OUTA VSS INB VL VL VH OUTD SUB VSS VL  2018 Microchip Technology Inc. MD1822 Typical Application Circuit +10V +10V 0.1µF +3.3V PIN 3.3V CMOS Logic Inputs NIN 0.47µF MD1822 PE VDD +100V VH 0.47µF 10nF OUTA INA OUTB INB 10nF -100V 0.47µF TC6320 DMP INC OUTD IND GND HVOUT OUTC VSS VL 10nF 10nF TC6320   2018 Microchip Technology Inc. DS20005706A-page 3 MD1822 1.0 ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings† Logic Supply Voltage, VDD–VSS ........................................................................................................... –0.5V to +12.5V Output High Supply Voltage, VH ................................................................................................... VL–0.5V to VDD+0.5V Output Low Supply Voltage, VL ..................................................................................................... VSS–0.5V to VH+0.5V Low-Side Supply Voltage, VSS .................................................................................................................. –6V to +0.5V Logic Input Levels ................................................................................................................... VSS–0.5V to GND +5.5V Maximum Junction Temperature, TJ ................................................................................................................... +125°C Operating Ambient Temperature, TA ..................................................................................................... –20°C to +85°C Storage Temperature, TS ..................................................................................................................... –65°C to +150°C Power Dissipation (Thermal Resistance, JA = 55 °C/W) (Note 2): 16-lead QFN ................................................................................................................................................ 2.2W ESD Rating (Note 1) .................................................................................................................................ESD Sensitive † Notice: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at those or any other conditions above those indicated in the operational sections of this specification is not intended. Exposure to maximum rating conditions for extended periods may affect device reliability. Note 1: Device is ESD sensitive. Handling precautions are recommended. 2: Mounted on a 1 oz. four-layer 3” x 4” PCB DC ELECTRICAL CHARACTERISTICS Electrical Specifications: VH = VDD = 10V, VL = VSS = GND = 0V, VPE = 3.3V, TA = 25°C Parameter Logic Supply Voltage Sym. Min. Typ. Max. Unit VDD–VSS 4.75 — 11.5 V Low-Side Supply Voltage VSS –5.5 — 0 V Output High Supply Voltage VH VSS+2 — VDD V Output Low Supply Voltage VL VSS — VDD–4 V VDD Quiescent Current IDDQ — 60 VH Quiescent Current IHQ — 2 — μA μA VDD Quiescent Current IDDQ — 1 — mA VH Quiescent Current IHQ — 2 — μA VDD Average Current IDD — 4 — mA VH Average Current IH — 10 — mA Input Logic Voltage High VIH VPE–0.3 — VPE V Input Logic Voltage Low VIL 0 — 0.3 V Input Logic Current High IIH — — 1 μA Input Logic Current Low IIL — — 1 μA Conditions 4V ≤ VDD ≤ 11.5V No input transitions, PE = 0 No input transitions, PE = 1 One channel on at 5 MHz, no load For logic inputs INA, INB, INC, and IND PE Input logic Voltage High VIH 1.7 3.3 5.25 V PE Input Logic Voltage Low VIL 0 — 0.3 V PE Input Impedance to GND RIN_PE 100 — — kΩ CIN — 5 10 pF ISINK = 50 mA ISOURCE = 50 mA Logic Input Capacitance Output Sink Resistance Output Source Resistance Peak Output Sink Current Peak Output Source Current DS20005706A-page 4 RSINK — 1.5 — Ω RSOURCE — 2 — Ω ISINK — 2 — A ISOURCE — 2 — A For logic input PE  2018 Microchip Technology Inc. MD1822 AC ELECTRICAL CHARACTERISTICS Electrical Specifications: VH = VDD = 10V, VL = VSS = GND = 0V, VPE = 3.3V, TA = 25°C unless otherwise indicated. Parameter Sym. Min. Typ. Max. Unit tirf — — 10 ns Propagation Delay when Output is from Low to High tPLH — 6.5 — ns Propagation Delay when Output is from High to Low tPHL — 6.5 — ns Output Rise Time tr — 7 — ns Output Fall Time tf — 7 — ns l tr–tf l — 1 — ns l tPLH–tPHL l — 1 — ns Input or PE Rise and Fall Time Rise and Fall Time Matching Propagation Low to High and High to Low Matching Propagation Delay Matching Conditions Logic input edge speed requirement CLOAD = 1000 pF (see Timing Diagram), input signal rise/fall time 2 ns For each channel ∆tdm — ±2 — ns Device to device delay match PE On Time tPE–ON — — 5 µs PE Off-Time tPE–OFF — — 4 µs VPE = 1.7V–5.25V, VDD = 7.5V–11.5V,  –20°C–85°C Sym. Min. Typ. Max. Units Maximum Junction Temperature TJ — — +125 °C Operating Ambient Temperature TA –20 — +85 °C Storage Temperature TS –65 — +150 °C JA — 55 — °C/W TEMPERATURE SPECIFICATIONS Parameter Conditions TEMPERATURE RANGE PACKAGE THERMAL RESISTANCE 16-lead QFN  2018 Microchip Technology Inc. DS20005706A-page 5 MD1822 Timing Diagram 3.3V IN 50% 50% 0V tPLH tPHL 10V 90% OUT 0V TABLE 1-1: 90% 10% 10% tr tf TRUTH FUNCTION TABLE Logic Input Output PE INA INB OUTA OUTB H L H VH VH H L L VH VL H H H VL VH H H L VL VL L X X VH VL PE INC IND OUTC OUTD H L H VH VH H L L VH VL H H H VL VH H H L VL VL L X X VH VL DS20005706A-page 6  2018 Microchip Technology Inc. MD1822 2.0 PIN DESCRIPTION The details on the pins of MD1822 are listed on Table 2-1. See Package Type for the location of pins. TABLE 2-1: PIN FUNCTION TABLE Pin Number Pin Name 1 INB Logic input 2 VDD High-side supply voltage 3 VSS Low-side supply voltage. VSS is also connected to the IC substrate. It is required to connect to the most negative potential of voltage supplies. 4 INC Logic input 5 IND Logic input 6 GND Logic input ground reference 7 VL 8 OUTC Output driver 9 OUTD Output driver 10, 11 VH 12 OUTA Output driver 13 OUTB Output driver 14 VL Supply voltage for N-channel output stage 15 PE Power enable logic input. When PE is high, it sets the input logic threshold. When PE is low, all outputs are at default state (See Table 1-1.) and the IC is in Standby mode. 16 INA Logic input Substrate Description Supply voltage for N-channel output stage Supply voltage for P-channel output stage The IC substrate is internally connected to the thermal pad. The thermal pad and VSS must be connected externally.  2018 Microchip Technology Inc. DS20005706A-page 7 MD1822 3.0 APPLICATION INFORMATION For proper operation of the MD1822, low-inductance bypass capacitors should be used on the various supply pins. The GND pin should be connected to the logic ground. The INA, INB, INC, IND and PE pins should be connected to a logic source with a swing of GND to PE, where PE is from 1.8V to 5V. Good trace practices should be followed corresponding to the desired operating speed. The internal circuitry of the MD1822 is capable of operating up to 100 MHz, with the primary speed limitation being the loading effects of the load capacitance. Because of this speed and the high transient currents that result in capacitive loads, the bypass capacitors should be as close to the chip pins as possible. Unless the load specifically requires bipolar drive, the VSS and VL pins should have low-inductance feed-through connections directly to a ground plane. If these voltages are not zero, then they need bypass capacitors in a manner similar to the positive power supplies. The power connection VDD should have a ceramic bypass capacitor to the ground plane with short leads and decoupling components to prevent resonance in the powerleads. 1.0 0.5 0 2.0 FIGURE 3-1: 3.0 4.0 5.0 VTH/VPE Graph. 8 Time (ns) 7 tPHL 6 tPLH 5 tr tf 7 6 5 4 4 -50 0 50 Temperature (OC) 3 125 MD1822 Delay vs VDD -50 0 50 125 10 12 Temperature (OC) MD1822 tr & tf vs VDD 12 12 10 10 Time (ns) Delay Time (ns) 1.0 VPE 8 8 6 tPLH 4 tPHL 2 0 0 9 9 Delay Time (ns) 1.5 VTH MD1822 tr & tf vs Temperature MD1822 Delay vs Temperature 3 VPE/2 2.0 tf 8 tr 6 4 2 5 FIGURE 3-2: 8 10 VDD Voltage (V) 12 5 8 VDD Voltage (V) Rise/Fall times, propagation delay vs. VDD voltage and Temperature. The voltages of VH and VL decide the output signal levels. These two pins can draw fast transient currents of up to 2A, so they should be provided with an appropriate bypass capacitor located next to the chip pins. A ceramic capacitor of up to 1 µF may be appropriate, with a series ferrite bead to prevent resonance in the power supply lead coming to the capacitor. Pay particular attention to minimizing trace lengths, current loop area and using sufficient trace DS20005706A-page 8 0 width to reduce inductance. Surface-mount components are highly recommended. Since the output impedance of this driver is very low, in some cases, it may be desirable to add a small series resistance in series with the output signal to obtain better waveform transitions at the load terminals. This will reduce the output voltage slew rate at the terminals of a capacitive load.  2018 Microchip Technology Inc. MD1822 Make sure that parasitic couplings are minimized from the output to the input signal terminals. The parasitic feedback may cause oscillations or spurious waveform shapes on the edges of signal transitions. Since the input operates with signals down to 1.8V, even small coupled voltages may cause problems. The use of a solid ground plane and good power and signal layout practices will prevent this problem. Be careful that a circulating ground return current from a capacitive load cannot react with common inductance to cause noise voltages in the input logic circuitry.  2018 Microchip Technology Inc. DS20005706A-page 9 MD1822 4.0 PACKAGING INFORMATION 4.1 Package Marking Information 16-lead QFN XXXXX XYWW NNN Legend: XX...X Y YY WW NNN e3 * Note: DS20005706A-page 10 Example 182 2815 232 Product Code or Customer-specific information Year code (last digit of calendar year) Year code (last 2 digits of calendar year) Week code (week of January 1 is week ‘01’) Alphanumeric traceability code Pb-free JEDEC® designator for Matte Tin (Sn) This package is Pb-free. The Pb-free JEDEC designator ( e3 ) can be found on the outer packaging for this package. In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for product code or customer-specific information. Package may or not include the corporate logo.  2018 Microchip Technology Inc. MD1822 Note: For the most current package drawings, see the Microchip Packaging Specification at www.microchip.com/packaging.  2018 Microchip Technology Inc. DS20005706A-page 11 MD1822 NOTES: DS20005706A-page 12  2018 Microchip Technology Inc. MD1822 APPENDIX A: REVISION HISTORY Revision A (October 2018) • Converted Supertex Doc# DSFP-MD1822 to Microchip DS20005706A • Changed the package marking format • Changed the quantity of the K6 package from 3000/Reel to 3300/Reel • Made minor text changes throughout the document  2018 Microchip Technology Inc. DS20005706A-page 13 MD1822 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, contact your local Microchip representative or sales office. XX PART NO. Device - Package Options X - Environmental X Media Type Device: MD1822 = High-Speed 4-Channel MOSFET Driver with Two Inverting and Two Non-Inverting Outputs Package: K6 = 16-lead (3x3) VQFN Environmental: G = Lead (Pb)-free/RoHS-compliant Package Media Type: (blank) = 3300/Reel for a K6 Package DS20005706A-page 14 Example: a) MD1822K6-G: High-Speed 4-Channel MOSFET Driver with Two Inverting and Two Non-Inverting Outputs, 16-lead (3x3) VQFN, 3300/Reel  2018 Microchip Technology Inc. Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. • Microchip is willing to work with the customer who is concerned about the integrity of their code. • Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer’s risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights unless otherwise stated. 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Adjacent Key Suppression, AKS, Analog-for-the-Digital Age, Any Capacitor, AnyIn, AnyOut, BodyCom, CodeGuard, CryptoAuthentication, CryptoAutomotive, CryptoCompanion, CryptoController, dsPICDEM, dsPICDEM.net, Dynamic Average Matching, DAM, ECAN, EtherGREEN, In-Circuit Serial Programming, ICSP, INICnet, Inter-Chip Connectivity, JitterBlocker, KleerNet, KleerNet logo, memBrain, Mindi, MiWi, motorBench, MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach, Omniscient Code Generation, PICDEM, PICDEM.net, PICkit, PICtail, PowerSmart, PureSilicon, QMatrix, REAL ICE, Ripple Blocker, SAM-ICE, Serial Quad I/O, SMART-I.S., SQI, SuperSwitcher, SuperSwitcher II, Total Endurance, TSHARC, USBCheck, VariSense, ViewSpan, WiperLock, Wireless DNA, and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. Silicon Storage Technology is a registered trademark of Microchip Technology Inc. in other countries. GestIC is a registered trademark of Microchip Technology Germany II GmbH & Co. KG, a subsidiary of Microchip Technology Inc., in other countries. All other trademarks mentioned herein are property of their respective companies. © 2018, Microchip Technology Incorporated, All Rights Reserved. ISBN: 978-1-5224-3755-0 == ISO/TS 16949 ==  2018 Microchip Technology Inc. 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