MD2131K7-G

Supertex inc. MD2131 High Speed Ultrasound Beamforming Source Driver Features General Description ►► High resolution transmitting waveform ►► Up to 3.0A push-pull source-driving current ►► 230VP-P maximum output, uses two DN2625 FETs ►► Angle vector beamforming I-Q switcher matrix ►► 8-bit apodization DAC and 7.5° angular resolution ►► Flexible frequency-resolution trade-off ►► Programmable aperture windowing ►► 250MHz maximum sampling rate ►► 25MHz ultrasound maximum frequency ►► PWM modulation push-pull current source ►► Focusing phase adjustment & chirp waveform ►► Fast SPI interface ►► 2.5V CMOS logic interface ►► +5.0V single power supply ►► Low second order harmonic distortions The MD2131 is a high-speed, arbitrary waveform, push-pull source driver. It is designed for medical ultrasound imaging and HIFU beamforming applications. It also can be used in NDT, Sonar and other ultrasound phase-array focusing beamforming applications. The MD2131 consists of CMOS digital logic input circuits, an 8-bit current DAC for waveform amplitude control, and four PWM current-sources. These current sources are constructed with the high-speed, in-phase and quadrature current-switch matrix and the built-in sine and cosine angle-to-vector look-up table. The angular resolution of the vector table is 7.5O per step, with a total range of 48 steps. There are four logic input signals to control the in-phase and quadrature PWM push-pull current-source’s output timing, frequency, cycle in the burst and waveform envelope. Applications ►► Medical ultrasound imaging transmit beamforming ►► High resolution NDT and Sonar phase arrays ►► HIFU transducer phase arrays beamforming and focus scanning ►► Piezoelectric & MEMS transducer waveform drivers ►► High speed, high voltage, arbitrary waveform generator MD2131 Block Diagram +2.5V VLL The MD2131’s output stage is designed to drive two DN2625 depletion N-type MOSFETs. The MOSFET drains are connected to a center-tap ultrasound frequency pulse transformer. The secondary winding of the transformer can connect to the ultrasound piezo or capacitive transducer via a cable with a good impendence match. The MD2131 has a high-speed, SPIcompatible interface to achieve per-scan-line fast updating of the data register for changing the beamforming phase angles and apodization amplitudes. +5.0V C3A VDD C2A KA C1A +5.0V +3.3V IA QA IB Level Translator D1 PA DN2625 QB I EN SDI SDO SCK Data Latch & Control Logic A SIN/COS Table & Level Translator Vector Beamforming Switch Matrix SUB GND D2 +5.0V AGND VREF XDRC DN2625 PB DAC DGND +70-100V VPP Q CS LD T1 RFB C3B C2B KB +3.3V C1B +VREF Doc.# DSFP-MD2131 C102412 Supertex inc. www.supertex.com MD2131 Pin Configuration Ordering Information Part Number Package Option Packing MD2131K7-G 40-Lead (5x5) QFN 490/Tray 40 1 -G indicates package is RoHS compliant (‘Green’) 40-Lead QFN (K7) Absolute Maximum Ratings (top view) Parameter Package Marking Value VLL, Logic supply -0.5V to +3.5V VDD, Positive supply -0.5V to +6.0V VPA VPB Driver outputs -0.5V to +6.0V VSUB, Ground Operating temperature Storage temperature MD2131 LLLLLL YYWW AAACCC 0V L = Lot Number YY = Year Sealed WW = Week Sealed A = Assembler ID C = Country of Origin = “Green” Packaging Package may or may not include the following marks: Si or 40-Lead QFN (K7) 0°C to +70°C -65°C to +150°C Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied. Continuous operation of the device at the absolute rating level may affect device reliability. All voltages are referenced to device ground. Typical Thermal Resistance Package θja 40-Lead QFN 26OC/W* * 4”x3”, 4-layer 1oz 16-via PCB Operating Supply Voltages (Over operating conditions unless otherwise specified, VLL = +2.5V, VDD = +5.0V, RFB = 50kΩ, DAC = 0, VREF = 2.5V, TA = 25°C) Sym Parameter Min Typ Max Units VLL Logic supply 2.3 2.5 2.7 V VDD Power supply 4.75 5.00 5.25 V ILLQ VLL supply current EN = 0 - 0.1 1.0 IDDQ VDD supply current EN = 0 - 0.2 1.0 ILLEN VLL supply current EN = 1 - 5.0 20 µA IDDEN VDD supply current EN = 1 - 5.0 12 mA ILL50 VLL supply current EN = 1 - 0.5 3.0 mA fCLK = 50MHz, CW, IA, IB, QA, QB = 0 IDD50 VDD supply current EN = 1 - 80 - mA EN = 1, IA, IB, QA, QB = 50MHz, CW µA Output Characteristics (Over operating conditions unless otherwise specified, V Angle = 45° IA = QA = Hi or IB = QB = Hi of 1μs, D% = 0.1%, TA = 25°C) Sym LL Conditions TA = 0 to 70°C Standby condition fCLK = 0, all logic input no transit = +2.5V, VDD = +5.0V, VREF = 2.5V, RFB = 50kΩ, Parameter Min Typ Max Units Conditions IMAX-A/B Full scale output peak current 2.88 - 3.52 A DAC = 255 IOO-A/B Output current offset - 0.5 2.0 mA 5.3 5.8 - IPA/B = 1.0A 5.0 5.5 - IPA/B = 1.5A 4.5 5.0 - - 1.0 1.5 - 1.2 1.7 IPA/B = 1.5A - 1.8 2.3 IPA/B = 3.0A Output voltage range, +10% of IPA/B VPA, VPB Output voltage range, -10% of IPA/B Doc.# DSFP-MD2131 C102412 2 V DAC = 0 IPA/B = 3.0A IPA/B = 1.0A Supertex inc. www.supertex.com MD2131 Aperture DAC Characteristics (Over operating conditions unless otherwise specified, VLL = +3.3V, VDD = +5V, RFB = 50kΩ, TA = 25°C) Sym Parameter Min Typ Max Units Conditions Reso Resolution - 8 - Bits ELINEAR Linearity error - 1.0 3.0 % ±% of FSR EDNL Differential nonlinearity error - 0.6 1.0 % ±% of FSR MON Monotonicity - 8 - Bits --- VREF External reference voltage 1.25 - 2.5 V --- --- Logic and Data Input Characteristics (Over operating conditions unless otherwise specified, VLL = +3.3V, VDD = +5V, RFB = 50kΩ, TA = 0 - 70°C) Sym Parameter Min Typ Max Units Conditions VIH Input logic high voltage 0.8VLL - VLL V --- VIL Input logic low voltage 0 - 0.2VLL V --- IIH Input logic high current - - 1.0 µA --- IIL Input logic low current -1.0 - - µA --- AC Electrical Characteristics (Over operating conditions unless otherwise specified, VLL = +3.3V, VDD = +5V, RFB = 50kΩ, TA = 25°C) Sym Parameter Min Typ Max Units Conditions µs All caps 10nF, DAC = 0 to 255, settle to 1LSB ns 1.0Ω resistor load to VDD, DAC = 85, Angle = 45O, VREF = 2.5V tST DAC to output setup time - - 10 tr Output current rise time - 2.0 3.0 tf Output current fall time - 2.0 3.0 tdr Input to output delay on rise - 4.0 5.0 tdf Input to output delay on fall - 4.0 5.0 tM Delay time matching - ±2.0 ±3.0 ns From PA to PB and device to device tJ Output jitter - 50 - ps --- t1 SDI valid to SCK setup time 0 2.0 - t2 SDI valid to SCK hold time 4.0 - - ns See serial interface timing diagram t3 SCK high time (% of 1/fSCK) 45 - 55 t4 SCK low time (% of 1/fSCK) 45 - 55 % See serial interface timing diagram t5 CS pulse width 4.0 - 6.0 t6 LSB SCK high to CS high 7.0 - - t7 CS low to SCK high 7.0 - - t8 SDO propagation delay from SCK failing edge - - 10 ns See serial interface timing diagram t9 CS high to SCK raising edge 7.0 - - t10 CS high to LD raising edge 10 - - fSCK Serial clock maximum frequency 40 50 - MHz --- THD Total harmonic distortion - -45 -40 dB --- tEN-OFF EN fall to PA/PB turn OFF time - 5.0 8.0 ns 50% to 90% tEN-ON EN rise to PA/PB turn ON time - 13.5 20.0 µs 50% to 10% Doc.# DSFP-MD2131 C102412 3 Supertex inc. www.supertex.com MD2131 Serial Register Description Command MSB C1 D7 C0 DAC Value Register D6 D5 D4 D3 D2 D1 LSB MSB D0 A5 Vector Angle Register A4 A3 A2 A1 LSB A0 Command Description Command Description C1 C0 0 0 Write to input register 0 1 Read register 1 0 Power down triggered at C[1:0] = 10 and cs rise edge, other state power-up 1 1 No operation DAC Input and Output Description DAC Value Register MSB LSB PA/PB Output Current D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 0 0 0 0 (0/255)IMAX-A/B + IOO-A/B 0 0 0 0 0 0 0 1 (1/255)IMAX-A/B + IOO-A/B 0 1 1 1 1 1 1 1 (127/255)IMAX-A/B + IOO-A/B 1 0 0 0 0 0 0 0 (128/255)IMAX-A/B + IOO-A/B 1 1 1 1 1 1 1 0 (254/255)IMAX-A/B + IOO-A/B 1 1 1 1 1 1 1 1 (255/255)IMAX-A/B + IOO-A/B Angle Register and I/Q Vector Description Angle Register MSB LSB Angle I-Vector (6-bit) Q-Vector (6-bit) A5 A4 A3 A2 A1 A0 Degree COS SIN 0 0 0 0 0 0 0 111111 000000 0 0 0 0 0 1 7.5 111110 001000 0 0 0 1 1 0 451 101101 101101 0 0 1 1 0 0 90 000000 111111 0 1 0 0 1 0 135 -101101 101101 0 1 1 0 0 0 180 -111111 000000 0 1 1 1 1 0 225 -101101 -101101 1 0 0 1 0 0 270 -000000 -111111 1 0 1 0 1 0 315 101101 -101101 1 0 1 1 1 1 352.5 111110 -001000 1 1 0 0 0 0 360 = 02 111111 000000 Notes: 1. Maximum current magnitude of output PA or PB is at 45° angle, when IA = QA = Hi or IB = QB = Hi. 2. Angle>110000B (48) are reserved states. Doc.# DSFP-MD2131 C102412 4 Supertex inc. www.supertex.com MD2131 Serial Interface Timing Diagram t1 t3 t2 SCK 1 t4 2 t6 15 3 16 t9 SDI t5 t7 CS t8 SDO t10 LD PWM Interface Timing Diagram In-Phase PWM Waveforms IA IB -64 -56 -48 -40 -32 -24 -16 -8 0 8 16 24 32 40 48 56 64 32 40 48 56 64 Sample Number Quadrature PWM Waveforms QA QB -64 -56 -48 -40 -32 -24 -16 -8 0 8 16 24 Sample Number Doc.# DSFP-MD2131 C102412 5 Supertex inc. www.supertex.com MD2131 In-Phase and Quadrature Output Current Equations The in-phase and quadrature phase output sinking current magnitudes, Ii and Iq, can be calculated by the following equations: 24 • VREF • DAC • (26 - 1) • cos(α) Ii = 9 • RFB 24 • VREF • DAC • (26 - 1) • sin(α) Iq = 9 • RFB The absolute values of the results from the equations represent the magnitude of the output sinking current. The plus or minus sign of the results indicate the current flow in to the output port PA or PB, respectively. Note that the maximum full scale of pulse current at PA or PB port only can be obtained at DAC = 255, VREF = 2.5V, RFB = 50kΩ, α = 45° and IA = QA = Hi or IB = QB = Hi conditions. Where the VREF is the voltage reference, DAC is the decimal value of the data in the DAC register, RFB is the setting resistor value in ohms, and α is the value of the vector angle in degrees. Doc.# DSFP-MD2131 C102412 6 Supertex inc. www.supertex.com MD2131 Pin Description Pin # Function 1 KA Description Kelvin connection A 2 GND High current output ground 3 C1A Bypass cap KA, 10nF low ESR X7R ceramic cap 4 GND High current output ground 5 VDD Supplies voltage of the gate driver and internal analog circuit 6 C3A Bypass cap to GND of Pin#7, 10nF low ESR X7R ceramic cap 7 GND High current output ground 8 VLL 9 DGND Supply voltage of logic circuit 10 SCK Serial clock input 11 SDI Serial data input 12 QA PWM control logic input of quadrature-phase A 13 QB PWM control logic input of quadrature-phase B 14 IA PWM control logic input of in-phase A 15 IB PWM control logic input of in-phase B Digital logic ground 16 VDD 17 AGND Supplies voltage of the gate driver and internal analog circuit 18 SDO 19 CS Serial chip select, active low, and buffer register loading clock on rising edge 20 LD DAC data register loading clock on rising edge Enable, EN = Low, PA = PB = Hi-Z Analog reference ground Serial data output, updated at SCK falling edge 21 EN 22 VREF 23 RFB 24 GND High current output ground 25 C3B Bypass cap to GND of Pin#24, 10nF low ESR X7R ceramic cap 26 VDD Supplies voltage of the gate driver and internal analog circuit 27 GND High current output ground 28 C1B Bypass cap to KB, 10nF low ESR X7R ceramic cap 29 GND High current output ground External reference voltage input Resistor to GND, 50kΩ 0.1% for the best accuracy 30 KB 31 C2B 32 PB Current sinking source driver output B, external Schottky diode to VDD 33 PB Current sinking source driver output B, external Schottky diode to VDD 34 PB Current sinking source driver output B, external Schottky diode to VDD 35 36 VSUB Kelvin connection B Bypass cap to KB, 10nF low ESR X7R ceramic cap Substrate voltage must connected to the lowest potential of the IC, the ground 37 PA Current sinking source driver output A, external Schottky diode to VDD 38 PA Current sinking source driver output A, external Schottky diode to VDD 39 PA Current sinking source driver output A, external Schottky diode to VDD 40 C2A Bypass Cap to KA, 10nF low ESR X7R ceramic cap Notes: 1. Pins #35 & #36 are VSUB connected to the center thermal pad internally in the package. 2. All bypass capacitors need be very close to the pins Doc.# DSFP-MD2131 C102412 7 Supertex inc. www.supertex.com MD2131 40-Lead QFN Package Outline (K7) 5.00x5.00mm body, 0.80mm height (max), 0.40mm pitch D 40 D2 40 1 1 Note 1 (Index Area D/2 x E/2) Note 1 (Index Area D/2 x E/2) e E E2 b View B Top View Bottom View Note 3 θ A A3 L Seating Plane A1 Note 2 Side View L1 View B Notes: 1. A Pin 1 identifier must be located in the index area indicated. The Pin 1 identifier can be: a molded mark/identifier; an embedded metal marker; or a printed indicator. 2. Depending on the method of manufacturing, a maximum of 0.15mm pullback (L1) may be present. 3. The inner tip of the lead may be either rounded or square. Symbol Dimension (mm) A A1 MIN 0.70 0.00 NOM 0.75 0.02 MAX 0.80 0.05 A3 0.20 REF b D D2 E E2 e 0.15 4.85* 3.45 4.85* 3.45 0.20 5.00 3.60 5.00 3.60 0.25 5.15* 3.70† 5.15* 3.70† 0.40 BSC L L1 θ 0.25† 0.00 0O 0.35† - - 0.45† 0.15 14O JEDEC Registration MO-220, Variation WHHE-1, Issue K, June 2006 * This dimension is not specified in the JEDEC drawing. † This dimension differs from the JEDEC drawing. Drawings not to scale. Supertex Doc. #: DSPD-40QFNK75X5P040, Version C041009. (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to http://www.supertex.com/packaging.html.) Supertex inc. does not recommend the use of its products in life support applications, and will not knowingly sell them for use in such applications unless it receives an adequate “product liability indemnification insurance agreement.” Supertex inc. does not assume responsibility for use of devices described, and limits its liability to the replacement of the devices determined defective due to workmanship. No responsibility is assumed for possible omissions and inaccuracies. Circuitry and specifications are subject to change without notice. For the latest product specifications refer to the Supertex inc. (website: http//www.supertex.com) Supertex inc. ©2012 Supertex inc. All rights reserved. Unauthorized use or reproduction is prohibited. 1235 Bordeaux Drive, Sunnyvale, CA 94089 Tel: 408-222-8888 www.supertex.com Doc.# DSFP-MD2131 C102412 8