MIC2155
Two-Phase Single-Output PWM Synchronous Buck Control IC
Features
General Description
• Synchronous Buck Control IC with Outputs
Switching 180 Degrees Out of Phase
• Remote Sensing with Internal Differential
Amplifier
• 4.5V-to-14.5V Input Voltage Range
• Adjustable Output Voltages down to 0.7V
• 1% Output Voltage Accuracy
• Starts up into a Pre-biased Output
• 500 kHz PWM Operation
• Adaptive Gate Drive allows Efficiencies of over
95%
• Adjustable Current Limit with no Sense Resistor
• Senses Low-Side MOSFET Current
• Internal Drivers allow 25A per Phase
• Power Good Output allows Simple Sequencing
• Dual Enable Pins with Micro-Power Shutdown
and UVLO
• Programmable Soft-Start Pin
• Output Overvoltage Protection
• Works with Ceramic Output Capacitors
• Multi-Input Supply Capability
• Single-Output High-Current Capability with
Master/Slave Current Sharing
• External Synchronization
• Small Footprint 32-Pin 5 mm × 5 mm VQFN
• Junction Temperature Range of –40°C to +125°C
The MIC2155 is a two-phase, single-output
synchronous buck control IC that features small size,
high efficiency, and a high level of flexibility. The IC
implements a 500 kHz Voltage mode PWM control with
the outputs switching 180 degrees out of phase. The
result of the out-of-phase operation is 1 MHz (or 600
kHz) input ripple with ripple current cancellation,
minimizing the required input filter capacitance. A 1%
output voltage tolerance allows the maximum level of
system performance. Internal drivers with adaptive
gate drive allow the highest efficiency with the
minimum external components.
Two independent enable pins and a power good output
are provided, allowing a high level of control and
sequencing capability.
The MIC2155 has an operating junction temperature
ranging from –40°C to +125°C.
Data sheets and support documentation can be found
on the Microchip website at www.microchip.com.
Applications
•
•
•
•
•
Multi-Output Power Supplies with Sequencing
DSP, FPGA, CPU and ASIC Power Supplies
DSL Modems
Telecommunications and Networking Equipment
Servers
Package Type
BST2
PGND1
LSD1
VIN1
EN1
VDD
LSD2
PGND2
32-lead 5 mm x 5 mm VQFN
(Top view)
32 31 30 29 28 27 26 25
BST1
HSD1
SW1
CS1
EN2
SS
1
24
2
23
3
22
4
21
5
20
COMP1
FB1
7
6
19
17
2019 Microchip Technology Inc.
FB2
EA2+
15 16
PGOOD
10 11 12 13 14
DIFFOUT
RMVOUT
RMGND
AGND
AVDD
N/C
SYNC
9
See Table 3-1 for pin information.
18
EP
8
HSD2
SW2
N/C
VIN2
VOUT
COMP2
DS20006106A-page 1
MIC2155
Functional Block Diagram
AVDD
(13)
BST1
(1)
Band
gap
BG
(700mV)
HSD1
(2)
E/A1
FB1
(8)
COMP1
(7)
S
2uA
SS
(6)
BG
+
BG +3%
+
BG -3%
+
Rmp1
-
OutH
R
Clk1
SET
CL R
Adap
-tive
Drive
Q
Q
SW1
(3)
VDD
LSD1
(31)
PGND1
(32)
-
200uA
BG -25%
-
OC retry
CS1
(4)
Current Limit
+
-
EN1
(29)
LOGIC
OV
BG +15%
+
-
PGOOD
(16)
PG
BG-10%
VOUT
+
-
VDD
UVLO
VDD
(28)
Pre-Bias
Startup
Circuit
VIN1
VOUT
(20)
EN1
VIN1
(30)
LDO
DIFFOUT
(9)
VIN1
UVLO
RMVOUT
(10)
RMGND
(11)
Rmp1
Clk1
SYNC
(15)
Rmp2
BS2
(25)
Clk2
2 phase
Oscillator
FB2
(18)
HSD2
(24)
AVDD
E/A2
OutH
Gm
EA2+
(17)
S
Rmp2
COMP2
(19)
R
Clk2
SET
CL R
Q
Q
Adap
-tive
Drive
SW2
(23)
VDD
LSD2
(27)
PGND2
(26)
SS
EN2
(5)
VIN2
UVLO
VOUT
VIN2
(21)
10mV
AGND
(12)
DS20006106A-page 2
2019 Microchip Technology Inc.
MIC2155
Typical Application Circuit
VIN
500μF
30
VIN1
VIN2
21
29
EN1
EN2
5
28
VDD
AVDD
10μF
1
0.1μF 2
FDMS7672
VOUT
1.8V
30A
1.5μH
Nȍ
0.22μF
FDMS7660
×2
25
SW1
HSD2
24
CS1
SW2
23
31
LSD1
LSD2
27
10
RMVOUT
FB2
18
PGND2
26
VOUT
20
250μF
Nȍ
Nȍ
1nF
0.1μF
11
RMGND
32
PGND1
17
EA2+
15
SYNC
Nȍ
DIFFOUT
8
FB1
0.1μF
7
MIC2155
0.1μF
FDMS7672
1.5μH
(Connect to VOUT)
FDMS7660 ×2
Nȍ
0.22μF
250μF
AVDD
9
100pF 6
Nȍ
BST1
BST2
4
ȍ
0.1μF
HSD1
3
ȍ
13
Nȍ
PGOOD
16
AGND COMP2
19
Power Good
SS
COMP1 EPAD
0.1μF
12
Nȍ
30A Two-Phase Converter
2019 Microchip Technology Inc.
DS20006106A-page 3
MIC2155
1.0
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings†
Supply Voltage, (VIN1,VIN2) ....................................................................................................................... –0.3V to 15V
Bootstrapped Voltage, (VBST) ............................................................................................................................ VIN +6V
SS, FB1, RMVOUT, RMGND, AVDD, SYNC, EA2+, FB2, VOUT ..................................................................... –0.3V to 6V
CS1, EN1, EN2 ......................................................................................................................................... –0.3V to 15V
Junction Temperature, TJ .................................................................................................................... –40°C to +150°C
Storage Temperature, TS ..................................................................................................................... –65°C to +150°C
ESD, Machine Model .............................................................................................................................................. 100V
ESD, Human Body Model .................................................................................................................................... 1500V
Lead Temperature (Soldering 10 Seconds) .......................................................................................................... 260°C
† Notice: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only, and functional operation of the device at those or any other conditions above those
indicated in the operational sections of this specification is not intended. Exposure to maximum rating conditions for
extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
Parameter
Sym.
Min.
Typ.
Max.
Unit
Supply Voltage
VIN1,VIN2
+4.5
—
+14.5
V
Note 1
Output Voltage
VOUT
+0.7
—
+3.6
V
Note 1
Note 1:
Conditions
The device is not guaranteed to function outside its operating rating.
DC ELECTRICAL CHARACTERISTICS
Electrical Specifications: TJ = 25°C; VEN = VIN1 = VIN2 =12V; unless otherwise specified. Bold values indicate
–40°C ≤ TJ ≤ 125°C.
Parameter
Sym.
Min. Typ. Max. Unit
Conditions
Supply Voltage
Output Voltage
VIN,VDD, VREF SUPPLY
Total Quiescent Supply Current, IVIN1 +
IVIN2
Shutdown Current
CH1 VIN UVLO Start Voltage
CH1 VIN UVLO Stop Voltage
CH2 VIN UVLO Start Voltage
CH2 VIN UVLO Stop Voltage
VDD UVLO Start Voltage
VDD UVLO Stop Voltage
VIN UVLO Hysteresis
VEN Shutdown Threshold
VEN Hysteresis
VIN1,VIN2
+4.5
—
+14.5
V
VOUT
+0.7
—
+3.6
V
IVIN
—
6
10
mA
VFB = 0.8V (both O/Ps;
non-switching)
210
300
µA
VEN1 = VEN2 = 0V
ISD
—
VIN1UV_R
3.6
4
4.4
V
VIN1UV_F
VDD = Open
3.4
3.97
4.2
V
VIN2UV_R
VDD = Open
2.5
2.7
2.9
V
VIN2UV_F
VDD = Open
2.3
2.5
2.7
V
VDDUV_R
VDD = Open
—
3.6
—
V
VDDUV_F
VIN1 = VDD for VIN < 6V
—
3.3
—
V
VINUV_HYS
VIN1 = VDD for VIN < 6V
—
40
—
mV
VEN_SD
0.6
1
1.6
V
VEN_HYS
—
30
—
mV
4.9 5.25
5.6
V
Internal Bias Voltage
VDD
V
4.9
5
5.6
Note 1: Specification is obtained by characterization and is not 100% tested.
2: Minimum on-time before automatic cycle skipping begins.
DS20006106A-page 4
VDD = open
Each Channel
Each Channel
IVDD = –75 mA
IVDD = –50 mA, VIN = 6V
2019 Microchip Technology Inc.
MIC2155
DC ELECTRICAL CHARACTERISTICS
Electrical Specifications: TJ = 25°C; VEN = VIN1 = VIN2 =12V; unless otherwise specified. Bold values indicate
–40°C ≤ TJ ≤ 125°C.
Parameter
Sym.
Min. Typ. Max. Unit
Conditions
OSCILLATOR/PWM SECTION
PWM Frequency per Channel
fs
450
510
550
kHz
Sync Range
fSYNC
860
—
1200
kHz
Sync Level
VSYNC
0.5
—
3
V
Maximum Duty Cycle
Minimum Headroom between VDD and
VOUT
D(MAX)
80
—
—
%
Each channel
Minimum On-Time
Sync Input is 2x PWM
Frequency
VHR(MIN)
—
—
1.3
V
Required for remote sense
amplifier use
tON(MIN)
—
30
—
ns
Each channel (Note 2)
VFB
693
686
697
697
707
714
mV
mV
+/–1%
+/–2%
REGULATION
CH1 Feedback Voltage Reference
IFB
—
30
—
nA
ΔVOUT_LINE
VFB = 0.7V
Output Voltage Line Regulation
—
0.08
—
%
Output Voltage Load Regulation
ΔVOUT_LOAD
4.5V VIN 14.5V
—
0.5
—
%
Output Voltage Total Regulation
ΔVOUT_TOTAL
—
0.6
—
%
VTH_ASYN
—
10
—
mV
CH1 Feedback Bias Current
CHANNEL CURRENT BALANCING
Asynchronous Mode VTH for Slave
Output
ERROR AMPLIFIER (CH1)
DC Gain
GEA1
—
70
—
dB
ISNK/SRC
—
1
—
mA
GEA2
—
70
—
dB
Transconductance
DIFFERENTIAL AMPLIFIER
Voltage Gain
gm
—
1.25
—
mS
GDA
—
1
—
Offset Voltage
VOS
–20
—
+20
mV
0
—
500
µA
106
109
114
—
1
—
µs
Output Sourcing/Sinking Current
ERROR AMPLIFIER (CH2)
DC Gain
ISRC_DA
Output Sourcing Current Range
OUTPUT OVERVOLTAGE PROTECTION
OVTH
OV Threshold
t
Delay Blanking time
BLANK_OV
4.5V VIN 14.5V; 1A IOUT
10A (VOUT = 2.5V)
%VREF VFB = OVTH, Latch LSD High
SOFT START
Internal Soft-Start Source Current
ISS
1.25
1
2
2.75
4
µA
µA
CURRENT SENSE
CS Overcurrent Trip Point Program
Current
ICL
180
195
220
µA
VCL_OS
–10
0
+10
mV
PGTH
86
88.5
91
CS Comparator Sense Offset Voltage
POWER GOOD
Power Good Threshold
Senses drop across low-side
FET
%VREF Sweep VFB from Low to High
VPG_LOW
— 0.225 0.3
V
Power Good Voltage Low
Note 1: Specification is obtained by characterization and is not 100% tested.
2: Minimum on-time before automatic cycle skipping begins.
2019 Microchip Technology Inc.
TJ = 25°C
–40°C TJ 125°C
VFB = 0 V; IPGOOD = 1 mA
DS20006106A-page 5
MIC2155
DC ELECTRICAL CHARACTERISTICS
Electrical Specifications: TJ = 25°C; VEN = VIN1 = VIN2 =12V; unless otherwise specified. Bold values indicate
–40°C ≤ TJ ≤ 125°C.
Parameter
Sym.
Min. Typ. Max. Unit
Conditions
GATE DRIVERS
tRISE
23
—
—
tFALL
16
Sink
1.6
3.5
Source
RHSD_H
—
High-Side Drive Resistance
RHSD_L
Sink
1.7
2.5
—
2
3.5
Source
RLSD_H
Low-Side Drive Resistance
RLSD_L
Sink
—
1.4
2.5
Driver Non-Overlap Time (Adaptive)
tNON
—
60
—
Note 1: Specification is obtained by characterization and is not 100% tested.
2: Minimum on-time before automatic cycle skipping begins.
Source
Rise/Fall Time
ns
ns
Ω
Ω
Ω
Ω
ns
Source into 3000 pF
Sink out of 3000 pF
VDD = VIN = 5V
VDD = VIN = 5V
TEMPERATURE SPECIFICATIONS
Parameter
Sym.
Min.
Typ.
Max.
Unit
Operating Junction Temperature
TJ
–40
—
+125
°C
Maximum Junction Temperature
TJ(ABSMAX)
—
—
+150
°C
TS
–65
—
+150
°C
JA
—
50
—
°C/W
JC
—
5
—
°C/W
Conditions
TEMPERATURE RANGE
Ambient Storage Temperature
PACKAGE THERMAL RESISTANCE
32-lead 5mm × 5mm VQFN
DS20006106A-page 6
2019 Microchip Technology Inc.
MIC2155
TYPICAL PERFORMANCE CURVES
The graphs and tables provided following this note are a statistical summary based on a limited number of
samples and are provided for informational purposes only. The performance characteristics listed herein
are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified
operating range (e.g. outside specified power supply range) and therefore outside the warranted range.
4.08
0.10
4.06
0.09
4.04
4.02
UVLO Rising
4.00
3.98
3.96
UVLO Falling
3.94
0.08
0.07
0.06
0.05
0.04
0.03
0.02
3.92
140
120
No Switching
0
4
6
TEMPERATURE (°C)
FIGURE 2-4:
Input Voltage.
0.20
2.55
2.50
140
120
100
80
60
40
20
-40
0
UVLO Falling
0.18
0.16
0.14
0.12
0.10
0.08
ISD2
0.06
0.04
0.02
0
4
6
TEMPERATURE (°C)
7
6
5
4
3
2
No Switching
0
4
FIGURE 2-3:
Input Voltage.
6
8
10 12 14
INPUT VOLTAGE (V)
16
Quiescent Current 1 vs.
2019 Microchip Technology Inc.
16
Shutdown Current vs. Input
1.08
VIN = 12V
1.06
1.04
CH1 Rising CH2 Rising
1.02
1.00
0.98
0.96
0.94 CH2 Falling
0.92
CH1 Falling
0.90
0.88
-40
ENABLE THRESHOLD (V)
QUIESCENT CURRENT (mA)
9
8
8
10 12 14
INPUT VOLTAGE (V)
FIGURE 2-5:
Voltage.
-20
VIN2 UVLO Threshold.
ISD1
ENABLE1,2 = 0V
140
2.60
1
16
Quiescent Current 2 vs.
120
2.65
FIGURE 2-2:
14
100
SHUTDOWN CURRENT (mA)
2.70
-20
UVLO THRESHOLD (V)
UVLO Rising
2.40
12
80
2.75
2.45
10
60
VN1 UVLO Threshold.
0
FIGURE 2-1:
8
INPUT VOLTAGE (V)
40
100
80
60
40
20
0
-40
-20
0.01
3.90
20
UVLO THRESHOLD (V)
Note:
QUIESCENT CURRENT (mA)
2.0
TEMPERATURE (°C)
FIGURE 2-6:
Temperature.
Enable Threshold vs
DS20006106A-page 7
1.00
5.5
0.50
5.0
-0.50
-1.00
4.5
4.0
V
-1.50
IN
= 5V
3.5
-2.00
-2.5
4
6
8
10 12 14
INPUT VOLTAGE (V)
4.00
2.00
3.0
0
16
FIGURE 2-7:
Change in Switching
Frequency vs. Input Voltage.
IN
10 20 30 40 50 60 70
LOAD (mA)
FIGURE 2-10:
5.5
V
= 12V
VDD vs. Load.
No Switching
5.0
0.00
VDD (V)
-2.00
-4.00
-6.00
-8.00
-10.00
4.5
4.0
3.5
3.0
4
6
TEMPERATURE (°C)
0.6990
140
120
100
80
60
40
20
0
VIN = 5V
-20
-40
4.0
TEMPERATURE (°C)
FIGURE 2-9:
DS20006106A-page 8
VDD vs. Temperature.
0.6975
0.6970
0.6965
0.6960
140
4.2
0.6980
120
4.4
0.6985
100
4.6
= 12V
80
4.8
IN
60
VDD (V)
5.0
V
40
IN
= 12V
-40
V
16
VDD vs. Input Voltage.
0
No Switching
5.2
FEEDBACK VOLTAGE (V)
5.4
FIGURE 2-11:
-20
FIGURE 2-8:
Change in Switching
Frequency vs. Temperature.
8
10 12 14
INPUT VOLTAGE (V)
20
140
120
100
80
60
40
-20
-40
-14
0
-12.00
20
FREQUENCY CHANGE (%)
VIN = 12V
No Switching
0.00
VDD (V)
FREQUENCY CHANGE (%)
MIC2155
TEMPERATURE (°C)
FIGURE 2-12:
Temperature.
Feedback Voltage vs.
2019 Microchip Technology Inc.
MIC2155
FIGURE 2-16:
vs. Temperature.
CS Pin Current vs.
2019 Microchip Technology Inc.
40
140
120
100
140
120
100
80
60
SINK
1.8
1.7
140
120
SOURCE
100
1.6
1.5
1.4
1.3
1.2
TEMPERATURE (°C)
TEMPERATURE (°C)
FIGURE 2-15:
Temperature.
20
2.2
V = 5V
2.1 IN
2.0
1.9
80
140
120
80
100
60
0
170
Soft-Start Current vs.
60
180
-20
0.5
-40
190
-40
1
40
= 5V
RDSON (ohms)
IN
1.5
20
210
200
= 5V
IN
FIGURE 2-17:
Temperature.
VIN = 12V
V
V
TEMPERATURE (°C)
CS Pin Current vs. Input
220
2
0
FIGURE 2-14:
Voltage.
= 12V
2.5
0
16
IN
0
8
10 12 14
INPUT VOLTAGE (V)
V
-20
6
3
-20
SOFT START CURRENT (μA)
197
196
195
194
193
192
191
160
Differential Amplifier Gain
3.5
200
199
198
190
4
CS PIN CURRENT (μA)
TEMPERATURE (°C)
Feedback Voltage vs. Input
40
CS PIN CURRENT (μA)
FIGURE 2-13:
Voltage.
16
80
8
10 12 14
INPUT VOLTAGE (V)
VIN = 5V
= 12V
60
6
-40
0.6950
4
IN
-40
0.6955
V
40
0.6960
20
0.6965
0
GAIN
0.6970
1.022
1.020
1.018
1.016
1.014
1.012
1.010
1.008
1.006
1.004
1.002
1.000
-20
0.6975
20
FEEDBACK VOLTAGE (V)
0.6980
FIGURE 2-18:
Source/Sink.
RDSON High-Side Drive
DS20006106A-page 9
MIC2155
1.8
V
RDSON (ohms)
1.7
IN
= 5V
SINK
1.6
1.5
1.4
SOURCE
1.3
1.2
140
120
100
80
60
40
0
20
-40
1
-20
1.1
TEMPERATURE (°C)
FIGURE 2-19:
Source/Sink.
DS20006106A-page 10
RDSON Low-Side Drive
2019 Microchip Technology Inc.
MIC2155
3.0
PIN DESCRIPTION
The details on the pins of MIC2155 are listed in
Table 3-1. Refer to Package Type for the location of
pins.
TABLE 3-1:
PIN FUNCTION TABLE
Pin Number
Pin Name
Description
1
BST1
Boost 1 (input): Provides voltage for high-side MOSFET Driver 1. The gate drive
voltage is higher than the high-side MOSFET source voltage by VDD minus a diode
drop.
2
HSD1
High-side Driver 1 (output): High-current driver output for Channel 1 external
high-side MOSFET.
3
SW1
Switch Node 1 (output): Return for HSD1
4
CS1
Current Sense 1 (input): Current-limit comparator non-inverting input. Current is
sensed across the Channel 1 low-side FET during the off-time. Current limit is set
by the resistor between the CS1 pin and drain of the Channel 1 low-side FET.
5
EN2
Enable 2 (input): Channel 2 enable. Pull high to enable. Pull low to disable.
6
SS
Soft Start (input): Controls the turn-on time of the output voltage. Active at
Power-up, Enable, and Current limit recovery.
7
COMP1
8
FB1
9
DIFFOUT
Output of remote sense differential amplifier.
10
RMVOUT
Remote VOUT: Connect to VOUT at the remote sense point. Input to precision
differential amplifier.
11
RMGND
Remote Ground: Connect to ground at the remote sense point. Input to precision
differential amplifier.
Compensation 1 (input): Output of the internal error amplifier for Channel 1.
Feedback 1 (input): Negative input to the error amplifier of Channel 1.
12
AGND
Analog Ground
13
AVDD
Analog Supply Voltage (input): Connect to VDD through an RC filter network.
14
N/C
15
SYNC
Sync (input): Synchronizes switching to an external source. Leave floating when not
used.
16
PGOOD
Power Good (output): Asserts high when voltage on the FB pin rises above Power
Good threshold.
17
EA2+
Positive Input to Channel 2 (current-sharing) error amplifier (Input): Connect to
Channel 1 current sense.
18
FB2
Negative input to Channel 2 (current sharing) error amplifier (Input): Connect to
Channel 2 current sense.
19
COMP2
Compensation 2 (input): Pin for external compensation of Channel 2 error amplifier.
20
VOUT
Output Sense (input): Connect to output side of inductors. Used for current sharing.
21
VIN2
Supply Voltage for Channel 2 (input): Used for Channel 2 UVLO circuit.
22
N/C
No connect
23
SW2
Switch Node 2 (output): Return for HSD2.
24
HSD2
High-side Driver 2 (output): High-current driver output for Channel 2 high-side
MOSFET.
25
BST2
Boost 2 (input): Provides voltage for high-side MOSFET driver in Channel 2. The
gate drive voltage is higher than the high-side MOSFET source voltage by VDD
minus a diode drop.
26
PGND2
27
LSD2
2019 Microchip Technology Inc.
No connect
Power Ground 2: High current return for Low-Side Driver 2.
Low-side Driver 2 (output): High-current driver output for Channel 2 low-side
external MOSFET.
DS20006106A-page 11
MIC2155
TABLE 3-1:
PIN FUNCTION TABLE (CONTINUED)
Pin Number
Pin Name
28
VDD
5V Internal Linear Regulator from VIN1 (output): VDD is the external MOSFET gate
driver supply voltage and an internal supply bus for the IC. When VIN1 is fZ (when ESR is relatively large),
1
G BOOST = -----------------------------------------------------------H 1 V IN f O 2 f Z
---------------------- ----- -----
VM
fZ
f C
Where:
fO = LC filter resonant frequency
fC = open loop bandwidth chosen in Step 1
fZ = zero formed by COUT and its ESR
H1 = voltage divider attenuation
VM = amplitude of the internal sawtooth ramp (VM = 1)
VIN = Input voltage to the power supply
EQUATION 4-71:
For fC < fZ (when ESR is very small),
1
G BOOST = ------------------------------------------H 1 V IN f O 2
---------------------- -----
VM
f C
Where:
fO = LC filter resonant frequency
fC = open loop bandwidth chosen in Step 1
fZ = zero formed by COUT and its ESR
H1 = voltage divider attenuation
VM = amplitude of the internal sawtooth ramp (VM = 1)
VIN = Input voltage to the power supply
Step 3: Determine the phase boost needed at the
crossover frequency.
FIGURE 4-26:
Type III Compensated Error
Amplifier Gain/Phase.
2019 Microchip Technology Inc.
Typically, 52 degrees of phase margin can be used for
most applications. This is a good trade off between an
overdamped system (slower response to transients)
and an underdamped system (overshoot or unstable
response to transients). It also allows some margin for
component tolerances and variations due to ambient
temperature changes. The phase margin excluding the
error amplifier phase boost at the crossover frequency
DS20006106A-page 31
MIC2155
(fC) can be determined by plotting the GVD(s) phase on
a bode plot or can be estimated with the formula in
Equation 4-72.
lead to jitter of the switching waveform or instability
under certain conditions. The fP2 can be calculated with
Equation 4-76.
EQUATION 4-72:
EQUATION 4-76:
f C 2
-
1 – --- f O
–1
– 1 f C
M XBOOST = tan ----------------------- + tan -----
fC
fZ
----------------
Q
fO
fS
f P2 = ---2
4.21
Calculating Error Amplifier
Component Values
The additional phase boost required from the error
amplifier is shown in Equation 4-73.
Once the pole and zero frequencies have been fixed,
the error amplifier's resistor and capacitor values are
calculated.
EQUATION 4-73:
R1: This value is chosen first. All other component
values are calculated from R1. A value of 10 kΩ is
suggested. If R1 is chosen too high, R2 may be very
large and the high impedances could be sensitive to
noise. If the remote sense amplifier is used, R1 must be
large enough so than not more than 500 µA of current
is drawn from the amplifier.
BOOST = 52 – M XBOOST
Step 4: Determine the frequencies fZ2 and fP1.
The frequencies for the zero and pole (fZ2 and fP1) are
calculated for the desired amount of phase boost at the
crossover frequency (fC). See Equation 4-74.
EQUATION 4-74:
BOOST
1 – sin --------------------2
f Z2 = f C ------------------------------------------ BOOST
1 + sin --------------------2
BOOST
1 + sin --------------------2
f P1 = f C ------------------------------------------ BOOST
1 – sin --------------------2
Step 5: Determine the frequency for fZ1.
The low-frequency zero, fZ1, is initially set to one-fifth of
the LC resonant frequency. If it is set too low, it forces
the low frequency gain to be low and impact transient
response. If set too high, it does not add enough phase
boost at the LC resonant frequency. This could cause
conditional stability, which is when the phase drops
below –180 degrees before the gain crosses 0 dB. If
the DC gain should drop in this situation, this may lead
to an unstable system. Refer to Equation 4-75.
EQUATION 4-75:
fO
f Z1 = ----5
Step 6: Determine the frequency for fP2.
This is the high frequency pole, which is useful in
additional attenuation of the switching frequency. It
should initially be set at half of the switching frequency.
If it is set too low, it lowers the phase margin at the
crossover frequency, making it difficult to achieve the
proper phase margin. If set too high, it does not provide
attenuation of the switching frequency, which could
DS20006106A-page 32
R2: The value of R2 is determined from the mid-band
gain of the error amplifier. This gain depends on the
frequencies of the poles, zeros and LC filter resonant
frequency.
Based on the amount of GEA1 gain necessary at the
crossover frequency, the error amplifier mid-band gain
and R2 values are calculated using the formulas in
Equation 4-77.
EQUATION 4-77:
For fC > fZ and fP1 = fZ,
VM
f Z 2 f C f Z2
G CO = ---------------------- ----- ----- -------H 1 V IN f O
f Z f P1
R2 = R1 G CO
EQUATION 4-78:
For fC < fZ and fP1 = fZ,
VM
f C 2 f Z2
G CO = ---------------------- ----- ------H 1 V IN f O
fC
R2 = R1 G CO
The other component values are calculated as
indicated
in
Equation 4-79,
Equation 4-80,
Equation 4-81 and Equation 4-82.
EQUATION 4-79:
1
C2 = ---------------------------------------2 f Z1 R2
2019 Microchip Technology Inc.
MIC2155
4.22
EQUATION 4-80:
1
C3 = ---------------------------------------------------------2 f Z2 R1 + R3
For R1>> R3,
1
C3 = ---------------------------------------2 f Z2 R1
EQUATION 4-81:
Compensation of the Current
Sharing Loop
The control circuitry for Channel 2 forces the channel's
output current to match the current in Channel 1. The
Channel 2 error amplifier compares the inductor
currents in the two channels and adjusts the duty cycle
of Channel 2 to control its output current. A block
diagram is shown in Figure 4-27.
C2
C1 = ------------------------------------------------------------------2 f P1 C2 R2 – 1
EQUATION 4-82:
1
R3 = ---------------------------------------2 f P2 C3
FIGURE 4-27:
Current Sharing Loop and Transfer Functions.
Unlike the voltage output amplifier used for Channel 1
compensation, a transconductance amplifier is used for
the Channel 2 compensation since only a pole/zero
combination is required for compensation. The
transconductance amplifier transfer function is shown
in Equation 4-83.
EQUATION 4-83:
1 + s R Z1 C Z1
G EA2 s = g m -------------------------------------------sC
Z1
Where:
RZ1 and CZ1 = the external components connected to the
COMP2 pin
gm = the transconductance of the internal error amplifier 2
2019 Microchip Technology Inc.
The pole and zero frequencies are indicted in
Equation 4-84 and Equation 4-85.
EQUATION 4-84:
gm
f POLE = ---------------------------2 C Z1
EQUATION 4-85:
1
f ZERO = --------------------------------------------2 R Z1 C Z1
The gain of the modulator is indicated in Equation 4-86.
DS20006106A-page 33
MIC2155
EQUATION 4-86:
The gain boost required at 50 kHz is 28 dB which is a
gain of 25. The gain for frequencies above the zero is
indicated in Equation 4-90.
V IN
G MOD2 = --------VM
Where:
VM = the peak-to-peak amplitude of the internal sawtooth
EQUATION 4-90:
G MID = R Z1 g m
The gain H2 of the feedback circuit is the Channel 2
output current sense voltage divided by Channel 2
output current as shown in Equation 4-87.
For a typical gm = 1.25 mS, use Equation 4-91 in
solving for RZ1.
EQUATION 4-87:
EQUATION 4-91:
G MID
25
R Z1 = --------------- = ------------------ = 20k
gm
1.25mS
H 2 = R L2
The filter transfer function is the output current over the
applied voltage. See Equation 4-88.
EQUATION 4-88:
Set the zero frequency to be 1/5 of the crossover
frequency. See Equation 4-92.
EQUATION 4-92:
V IN – V OUT
G FILTER2 s = ------------------------------s L2 V IN
1
C Z1 = -----------------------------------------2 R Z1 f Z1
The open loop transfer function is indicated in
Equation 4-89.
EQUATION 4-89:
G OL2 s = G EA2 s G MOD2 H 2 G FILTER2 s
1
= -------------------------------------------------------- = 800pF
2 20k 10kHz
The compensated open-loop gain/phase plot is shown
in Figure 4-29.
g m 1 + s R Z1 C Z1 R L2 V IN – V OUT
= ---------------------------------------------------------------------------------------------------------------------- s C Z1 V m s L2
Gain
bb(f)
θH2(f)
0
-100
GAIN/PHASE
50
VIN = 12V
VOUT = 1.8V
L = 1.5 μH
RL = 1.9 mΩ
0
Gain
fZERO = 10kHz
fC = 50kHz
Phase margin = 80°
100
GAIN/PHASE
The loop is inherently stable because the phase shift is
only 90 degrees. The error amplifier pole and zero is
selected to achieve a desired crossover frequency. In
this example, the desired crossover frequency is 50
kHz. The transfer function of the filter, modulator and
feedback is plotted in Figure 4-28.
200
134.17466
Phase
-179.9424
-200
10
100
1k
10k 100k
FREQUENCY
1M
FIGURE 4-29:
Compensated Current
Sharing Loop Gain/Phase.
-50
Phase
-100
10
100
1k
10k 100k
FREQUENCY
1M
FIGURE 4-28:
Current Sharing Loop
GFILTER2(s) x GMOD2 x H2 Gain/Phase.
DS20006106A-page 34
2019 Microchip Technology Inc.
MIC2155
4.23
General Layout and Component
Placement
There are three basic types of currents in a switching
power supply—high di/dt, moderate di/dt and DC.
Examples of each are shown in Figure 4-30.
High di/dt
Moderate di/dt
FIGURE 4-30:
DC
Current Diagram.
In a buck converter, high di/dt currents in the 0.5 A/ns
range are generated by MOSFETs switching on and
off. These fast switching currents flow in the high-side
and low-side MOSFETs, external freewheeling
Schottky diode and the input capacitor. Fast-switching
currents also flow in the gate drive and return etch
between the controller and the power FETs. At that
switching speed at a 10 nH piece of etch generates 5V
across itself. Therefore, attention to proper layout
techniques is essential. Traces that have high di/dt
currents must be kept short and wide. Additionally, a
power ground plane should be used on an adjacent
layer to help minimize etch inductance. Figure 4-31
shows a layout example that minimizes inductance.
DC currents in a high-current buck converter require
wide etch paths to minimize voltage drop and power
dissipation. The input and output current are mainly
DC. At or near maximum output power, the inductor
current is also predominately DC and requires ample
etch to reduce copper loss, reduce temperature rise
and improve efficiency. Minimizing voltage drops in the
output and ground path helps improve output voltage
regulation for configurations without remote voltage
sensing.
The gate drive connections to both the high-side and
low-side MOSFETs must each have their own return
current path. The high-side MOSFET's source is
connected to the switch node and returns back to the
controller's SW1 or SW2 pin. The high-side gate drive
and return (switch node) traces should be routed on top
of each other on adjacent layers to minimize
inductance. These traces swing between VIN and
ground and should be routed away from low-voltage
and noise-sensitive analog etch or components. The
low-side MOSFET return path is power ground. High
di/dt currents flow in the low-side gate drive and return
paths. These must be kept away from noise sensitive
signal traces and signal ground planes.
Ceramic capacitors are recommended for most
decoupling and filtering applications because of their
low impedance and small size. Depending on the
application, most dielectrics (X5R, X7R, NPO) are
acceptable, however, Z5U type ceramic capacitor
dielectrics are not recommended due to their large
change in capacitance over temperature and voltage.
4.24
Co
LSFET
Vo
Load
HSFET
Cin
Vin
Lo
FIGURE 4-31:
Layout.
Moderate di/dt currents flow in the inductor and output
capacitor. Although layout is not as critical, it is still
important to minimize inductance by using short, wide
traces and a ground plane. Figure 4-31 shows the etch
connecting the inductor to the output is shaped to force
current to flow past the output capacitor before
reaching the output terminal (or output load). This
minimizes the series inductance between the inductor
and the capacitor, which improves the ability of the
capacitor to filter ripple. Additionally, the inductor
current has a large DC component and requires a wide
trace to minimize voltage drop and power dissipation.
2019 Microchip Technology Inc.
Design and Layout Checklist
• Ceramic capacitor placed between the high-side
FET drain and the low-side FET source.
• MOSFET gate drive traces must be low
inductance and routed away from noise-sensitive
analog signals, components and ground planes.
• The signal and power ground planes must be
separated to prevent high current and fast
switching signals from interfering with the
low-level, noise-sensitive analog signals. These
planes should be connected at only 1 point, next
to the MIC2155 controller.
• The following signals and their components
should be decoupled or referenced to the power
ground plane:VIN1, VIN2, VDD, PGND1, PGND2
• These analog signals should be referenced or
decoupled to the analog ground plane: AVDD,
SYNC, EN, SS, PGOOD, COMP1, COMP2, FB2,
EA2, VOUT, FB1, AGND
• Place the current sharing RC components (that
connect across the inductor) and any related
filtering components close to the FB2, EA2+ and
VOUT pins (18, 17, 20). The traces connecting
the inductors and these components should be
routed close together to minimize pickup or EMI
DS20006106A-page 35
MIC2155
radiation.
• Place the overcurrent setting resistor close to the
CS1 pin (pin 4).The switch node to this resistor
connection should be connected close to the
drain pin of the Channel 1 low-side MOSFET. The
trace coming from the switch node to this resistor
has high dv/dt and should be routed away from
other noise-sensitive components and traces.
• The remote sense traces must be routed close
together or on adjacent layers to minimize noise
pickup. The traces should be routed away from
the switch node, inductors, MOSFETs and other
high dv/dt or di/dt sources.
DS20006106A-page 36
2019 Microchip Technology Inc.
MIC2155
5.0
PACKAGE INFORMATION
5.1
Package Marking Information
32-lead VQFN
XXX
XXXXXXX
WNNN
Legend: XX...X
Y
YY
WW
NNN
e3
*
Note:
Example
MIC
2155YML
3230
Product Code or Customer-specific information
Year code (last digit of calendar year)
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code
Pb-free JEDEC® designator for Matte Tin (Sn)
This package is Pb-free. The Pb-free JEDEC designator ( e3 )
can be found on the outer packaging for this package.
In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for product code or customer-specific information. Package may or
not include the corporate logo.
2019 Microchip Technology Inc.
DS20006106A-page 37
MIC2155
5.2
Package Outline Drawing
DS20006106A-page 38
2019 Microchip Technology Inc.
MIC2155
APPENDIX A:
REVISION HISTORY
Revision A (April 2019)
• Converted Micrel Doc# DSFP-MIC2155 to Microchip DS20006106A. Removed all references to
MIC2156.
• Added some sections to comply with the standard
Microchip format
• Changed the package marking format
• Made minor text changes throughout
the document
2019 Microchip Technology Inc.
DS20006106A-page 39
MIC2155
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, contact your local Microchip representative or sales office.
Example:
X
XX
PART NO.
XX
Device
Junction
Package Media Type
Temp.
Options
Range
Device:
MIC2155
=
Two-Phase Single-Output PWM
Synchronous-Buck-Control IC
Junction Temperature Range:
Y
=
–40°C to +125°C RoHS-Compliant
Package:
ML
=
32-lead (5mm x 5mm) VQFN
Media Type:
TR
=
1000/Reel for an ML Package
DS20006106A-page 40
a) MIC2155YML-TR: Two-Phase Single-Output PWM
Synchronous-Buck-Control IC,
32-lead VQFN, 1000/Reel
Note:
Tape and reel identifier only appears in the
catalog part number description. This identifier is used for ordering purposes and is
not printed on the device package. Check
with your Microchip Sales Office for package availability with the Tape and Reel
option.
2019 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
•
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Trademarks
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and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
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All other trademarks mentioned herein are property of their
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© 2019, Microchip Technology Incorporated, All Rights Reserved.
ISBN: 978-1-5224-4438-1
== ISO/TS 16949 ==
2019 Microchip Technology Inc.
DS20006106A-page 41
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