MIC24054
12V, 9A High-Efficiency Buck Regulator
SuperSwitcher II
General Description
Features
• Hyper Light Load efficiency – up to 80% at 10mA
The Micrel MIC24054 is a constant-frequency,
synchronous DC/DC buck regulator featuring adaptive on• Hyper Speed Control architecture enables
time control architecture. The MIC24054 operates over a
− High delta V operation (VIN = 19V and VOUT = 0.8V)
supply range of 4.5V to 19V. It has an internal linear
− Small output capacitance
regulator which provides a regulated 5V to power the
• Input voltage range: 4.5V to 19V
internal control circuitry. The MIC24054 operates at a
constant 600kHz switching frequency in continuous
• Output current up to 9A
conduction mode and can be used to provide up to 9A of
• Up to 95% efficiency
output current. The output voltage is adjustable down to
• Adjustable output voltage from 0.8V to 5.5V
0.8V.
• ±1% FB accuracy
®
Micrel’s Hyper Light Load architecture provides the same
•
Any Capacitor stable − zero-to-high ESR
high-efficiency and ultra-fast transient response as the
• 600kHz switching frequency
Hyper Speed Control architecture under medium to heavy
loads, but also maintains high efficiency under light load
• Power good (PG) output
conditions by transitioning to variable frequency,
• Foldback current-limit and “hiccup” mode short-circuit
discontinuous mode operation.
protection
The MIC24054 offers a full suite of protection features to
• Safe start-up into pre-biased loads
ensure protection of the IC during fault conditions. These
• –40°C to +125°C junction temperature range
include undervoltage lockout to ensure proper operation
•
Available in 28-pin 5mm × 6mm QFN package
under power-sag conditions, thermal shutdown, internal
soft-start to reduce the inrush current, foldback current
Applications
limit and “hiccup mode” short-circuit protection. The
MIC24054 includes a power good (PG) output to allow
• Servers and work stations
simple sequencing.
• Routers, switches, and telecom equipment
The 9A Hyper Speed Control part, MIC24053, is also
• Base stations
available on Micrel’s web site.
All support documentation can be found on Micrel’s web
site at: www.micrel.com.
___________________________________________________________________________________________________________
Typical Application
Efficiency (VIN = 12V)
vs. Output Current
100
95
5.0V
3.3V
2.5V
1.8V
1.5V
1.2V
1.0V
0.9V
0.8V
EFFICIENCY (%)
90
85
80
75
70
65
60
55
VIN = 12V
50
0
2
4
6
8
10
12
OUTPUT CURRENT (A)
Hyper Light Load is a registered trademark of Micrel, Inc.
Hyper Speed Control, SuperSwitcher II, and Any Capacitor are trademarks of Micrel, Inc.
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1 (408) 944-0800 • fax + 1 (408) 474-1000 • http://www.micrel.com
October 2012
M9999-102512-A
Micrel, Inc.
MIC24054
Ordering Information
Part Number
Switching Frequency
Voltage
Package
Junction Temperature
Range
Lead Finish
MIC24054YJL
600kHz
Adjustable
28-Pin 5mm × 6mm QFN
–40°C to +125°C
Pb-Free
Pin Configuration
28-Pin 5mm x 6mm QFN (JL)
(Top View)
Pin Description
Pin Number
Pin Name
1
PVDD
5V Internal Linear Regulator output. PVDD supply is the power MOSFET gate drive supply voltage
and created by internal LDO from VIN. When VIN < +5.5V, PVDD should be tied to PVIN pins. A
2.2µF ceramic capacitor from the PVDD pin to PGND (Pin 2) must be placed next to the IC.
2, 5, 6, 7, 8, 21
PGND
Power Ground. PGND is the ground path for the MIC24054 buck converter power stage. The
PGND pins connect to the low-side N-Channel internal MOSFET gate drive supply ground, the
sources of the MOSFETs, the negative terminals of input capacitors, and the negative terminals of
output capacitors. The loop for the power ground should be as small as possible and separate
from the signal ground (SGND) loop.
3
NC
No Connect.
4, 9, 10, 11, 12
SW
Switch Node output. Internal connection for the high-side MOSFET source and low-side MOSFET
drain. Due to the high speed switching on this pin, the SW pin should be routed away from
sensitive nodes.
PVIN
High-Side N-internal MOSFET Drain Connection input. The PVIN operating voltage range is from
4.5V to 19V. Input capacitors between the PVIN pins and the power ground (PGND) are required
and keep the connection short.
BST
Boost output. Bootstrapped voltage to the high-side N-channel MOSFET driver. A Schottky diode is
connected between the PVDD pin and the BST pin. A boost capacitor of 0.1μF is connected
between the BST pin and the SW pin. Adding a small resistor at the BST pin can slow down the
turn-on time of high-side N-Channel MOSFETs.
13,14,15,
16,17,18,19
20
October 2012
Pin Function
2
M9999-102512-A
Micrel, Inc.
MIC24054
Pin Description (Continued)
Pin Number
Pin Name
Pin Function
22
CS
Current Sense input. The CS pin senses current by monitoring the voltage across the low-side
MOSFET during the OFF-time. The current sensing is necessary for short circuit protection and zero
current cross comparator. In order to sense the current accurately, connect the low-side MOSFET
drain to SW using a Kelvin connection. The CS pin is also the high-side MOSFET’s output driver
return.
23
SGND
Signal Ground. SGND must be connected directly to the ground planes. Do not route the SGND pin
to the PGND pad on the top layer, see PCB layout guidelines for details.
24
FB
Feedback input. Input to the transconductance amplifier of the control loop. The FB pin is regulated
to 0.8V. A resistor divider connecting the feedback to the output is used to adjust the desired output
voltage.
25
PG
Power Good output. Open drain output. The PG pin is externally tied with a resistor to VDD. A high
output is asserted when VOUT > 92% of nominal.
26
EN
Enable input. A logic level control of the output. The EN pin is CMOS-compatible. Logic high =
enable, logic low = shutdown. In the off state, supply current of the device is greatly reduced (typically
5µA). The EN pin should not be left floating.
27
VIN
Power Supply Voltage input. Requires bypass capacitor to SGND.
28
VDD
5V Internal Linear Regulator output. VDD supply is the supply bus for the IC control circuit. VDD is
created by internal LDO from VIN. When VIN < +5.5V, VDD should be tied to PVIN pins. A 1µF
ceramic capacitor from the VDD pin to SGND pins must be place next to the IC.
October 2012
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M9999-102512-A
Micrel, Inc.
MIC24054
Absolute Maximum Ratings(1)
Operating Ratings(3)
PVIN to PGND............................................... −0.3V to +29V
VIN to PGND ................................................. −0.3V to PVIN
PVDD, VDD to PGND ..................................... −0.3V to +6V
VSW , VCS to PGND ............................. −0.3V to (PVIN +0.3V)
VBST to VSW ........................................................ −0.3V to 6V
VBST to PGND .................................................. −0.3V to 35V
VFB, VPG to PGND ............................. −0.3V to (VDD + 0.3V)
VEN to PGND ....................................... −0.3V to (VIN +0.3V)
PGND to SGND............................................ −0.3V to +0.3V
Junction Temperature .............................................. +150°C
Storage Temperature (TS) ......................... −65°C to +150°C
Lead Temperature (soldering, 10s) ............................ 260°C
(2).
ESD Rating ................................................ ESD Sensitive
Supply Voltage (PVIN, VIN) .............................. 4.5V to 19V
PVDD, VDD Supply Voltage (PVDD, VDD) ..... 4.5V to 5.5V
Enable Input (VEN) .................................................. 0V to VIN
Junction Temperature (TJ) ........................ −40°C to +125°C
Maximum Power Dissipation ...................................... Note 4
(4)
Package Thermal Resistance
5mm x 6mm QFN-28 (θJA) ................................ 28°C/W
Electrical Characteristics(5)
PVIN = VIN = VEN = 12V, VBST – VSW = 5V; TA = 25°C, unless noted. Bold values indicate −40°C ≤ TJ ≤ +125°C.
Parameter
Condition
Min.
Typ.
Max.
Units
19
V
Power Supply Input
4.5
Input Voltage Range (VIN, PVIN)
Quiescent Supply Current
VFB = 1.5V (non-switching)
Shutdown Supply Current
VEN = 0V
450
750
µA
5
10
µA
5
5.4
V
4.2
4.5
VDD Supply Voltage
VDD Output Voltage
VDD UVLO Threshold
VIN = 7V to 19V, IDD = 25mA
4.8
VDD Rising
3.7
VDD UVLO Hysteresis
Dropout Voltage (VIN – VDD)
400
IDD = 25mA
380
V
mV
600
mV
5.5
V
DC/DC Controller
Output-Voltage Adjust Range (VOUT)
0.8
Reference
Feedback Reference Voltage
0°C ≤ TJ ≤ 85°C (±1.0%)
0.792
0.8
0.808
−40°C ≤ TJ ≤ 125°C (±1.5%)
0.788
0.8
0.812
V
Load Regulation
IOUT = 3A to 9A (Continuous Mode)
0.25
%
Line Regulation
VIN = 4.5V to 19V
0.25
%
FB Bias Current
VFB = 0.8V
50
500
nA
Notes:
1.
Exceeding the absolute maximum rating may damage the device.
2.
Devices are ESD sensitive. Handling precautions recommended. Human body model, 1.5kΩ in series with 100pF.
3.
The device is not guaranteed to function outside operating range.
4.
PD(MAX) = (TJ(MAX) – TA)/ θJA, where θJA depends upon the printed circuit layout. A 5 square inch 4 layer, 0.62”, FR-4 PCB with 2oz finish copper
weight per layer is used for the θJA.
5.
Specification for packaged product only.
October 2012
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Micrel, Inc.
MIC24054
Electrical Characteristics(5) (Continued)
PVIN = VIN = VEN = 12V, VBST – VSW = 5V; TA = 25°C, unless noted. Bold values indicate −40°C ≤ TJ ≤ +125°C.
Parameter
Condition
Min.
Typ.
Max.
Units
Enable Control
1.8
EN Logic Level High
V
0.6
V
6
30
µA
600
750
kHz
EN Logic Level Low
EN Bias Current
VEN = 12V
Oscillator
(6)
VOUT = 2.5V
(7)
VFB = 0V
82
%
VFB = 1.0V
0
%
300
ns
3
ms
Switching Frequency
Maximum Duty Cycle
Minimum Duty Cycle
450
Minimum Off-Time
Soft-Start
Soft-Start time
Short-Circuit Protection
Peak Inductor Current-Limit Threshold
Short-Circuit Current
VFB = 0.8V, TJ = 25°C
12.5
VFB = 0.8V, TJ = 125°C
11.25
VFB = 0V
14
20
A
8
A
Internal FETs
Top-MOSFET RDS (ON)
ISW = 3A
27
mΩ
Bottom-MOSFET RDS (ON)
ISW = 3A
10.5
mΩ
SW Leakage Current
VEN = 0V
60
µA
VIN Leakage Current
VEN = 0V
25
µA
95
%VOUT
Power Good (PG)
85
PG Threshold Voltage
Sweep VFB from Low to High
92
PG Hysteresis
Sweep VFB from High to Low
5.5
%VOUT
PG Delay Time
Sweep VFB from Low to High
100
µs
PG Low Voltage
Sweep VFB < 0.9 × VNOM, IPG = 1mA
70
TJ Rising
160
°C
15
°C
200
mV
Thermal Protection
Over-Temperature Shutdown
Over-Temperature Shutdown Hysteresis
Notes:
6.
Measured in test mode.
7.
The maximum duty-cycle is limited by the fixed mandatory off-time tOFF of typically 300ns.
October 2012
5
M9999-102512-A
Micrel, Inc.
MIC24054
Typical Characteristics
VIN Shutdown Current
vs. Input Voltage
VIN Operating Supply Current
vs. Input Voltage
10
40
0.8
0.6
0.4
VOUT = 1.8V
0.2
IOUT = 0A
SWITCHING
VEN = 0V
REN = OPEN
VDD VOLTAGE (V)
SHUTDOWN CURRENT (µA)
SUPPLY CURRENT (mA)
1.0
30
20
4
7
10
13
16
4
19
7
16
4
19
0.796
VOUT = 1.8V
0.5%
0.0%
-0.5%
4
19
7
VOUT = 1.8V
10
13
16
4
19
550
VOUT = 1.8V
12
8
4
IOUT = 2A
October 2012
19
19
95%
90%
85%
VFB = 0.8V
VEN = VIN
0
500
16
100%
VPG THRESHOLD/VREF (%)
EN INPUT CURRENT (µA)
600
13
PG/VREF Ratio
vs. Input Voltage
16
650
10
INPUT VOLTAGE (V)
Enable Input Current
vs. Input Voltage
700
16
7
INPUT VOLTAGE (V)
Switching Frequency
vs. Input Voltage
13
5
0
INPUT VOLTAGE (V)
10
10
VOUT = 1.8V
-1.0%
16
19
15
IOUT = 2A to 9A
0.792
16
20
IOUT = 2A
13
13
Output Current Limit
vs. Input Voltage
CURRENT LIMIT (A)
0.800
INPUT VOLTAGE (V)
10
INPUT VOLTAGE (V)
1.0%
7
7
Total Regulation
vs. Input Voltage
TOTAL REGULATION (%)
FEEDBACK VOLTAGE (V)
13
10
INPUT VOLTAGE (V)
0.804
4
VFB = 0.9V
IDD = 10mA
0.808
10
4
0
Feedback Voltage
vs. Input Voltage
7
6
2
INPUT VOLTAGE (V)
4
8
10
0
0.0
FREQUENCY (kHz)
VDD Output Voltage
vs. Input Voltage
80%
4
7
10
13
INPUT VOLTAGE (V)
6
16
19
4
7
10
13
16
19
INPUT VOLTAGE (V)
M9999-102512-A
Micrel, Inc.
MIC24054
Typical Characteristics (Continued)
VIN Operating Supply Current
vs. Temperature
VIN Shutdown Current
vs. Temperature
14
0.8
0.6
0.4
VIN = 12V
VOUT = 1.8V
0.2
IOUT = 0A
SWITCHING
RISING
12
10
0.0
8
6
4
VIN = 12V
IOUT = 0A
VEN = 0V
2
0
-50
-25
0
25
50
75
100
3.9
FALLING
2.9
1.9
0.9
-25
0
25
50
75
100
125
-50
0
25
50
75
TEMPERATURE (°C)
Feedback Voltage
vs. Temperature
Load Regulation
vs. Temperature
Line Regulation
vs. Temperature
0.800
0.796
VIN = 12V
VOUT = 1.8V
0.792
0.5%
0.0%
VIN = 12V
VOUT = 1.8V
-0.5%
IOUT =2A to 9A
50
75
-25
650
5
VDD (V)
6
600
0
25
50
75
100
125
TEMPERATURE (°C)
October 2012
25
50
125
75
100
125
Output Current Limit
vs. Temperature
VIN = 12V
VOUT = 1.8V
15
10
5
VIN = 12V
VOUT = 1.8V
2
100
0
-25
IOUT =0A
500
75
-50
TEMPERATURE (°C)
4
IOUT = 2A
50
VIN = 4.5V to 19V
VOUT = 1.8V
20
3
VIN = 12V
VOUT = 1.8V
25
-0.4%
VDD
vs. Temperature
700
0
-0.3%
TEMPERATURE (°C)
Switching Frequency
vs. Temperature
-25
-0.2%
-0.6%
-50
125
TEMPERATURE (°C)
550
0.0%
-0.1%
IOUT = 2A
100
CURRENT LIMIT (A)
25
0.1%
-0.5%
-1.0%
0.788
0
125
0.2%
IOUT = 2A
-25
100
0.3%
LINE REGULATION (%)
LOAD REGULATION (%)
0.804
-50
-25
TEMPERATURE (°C)
TEMPERATURE (°C)
1.0%
-50
HYST
-0.1
-50
125
0.808
FEEBACK VOLTAGE (V)
4.9
VDD THRESHOLD (V)
SHUTDOWN CURRENT (µA)
SUPPLY CURRENT (mA)
1.0
FREQUENCY (kHz)
VDD UVLO Threshold
vs. Temperature
0
-50
-25
0
25
50
75
TEMPERATURE (°C)
7
100
125
-50
-25
0
25
50
75
100
125
TEMPERATURE (°C)
M9999-102512-A
Micrel, Inc.
MIC24054
Typical Characteristics (Continued)
Feedback Voltage
vs. Output Current
Output Voltage
vs. Output Current
1.0%
1.819
0.804
0.800
0.796
VIN = 12V
VOUT = 1.8V
LINE REGULATION (%)
1.814
OUTPUT VOLTAGE (V)
1.810
1.805
1.800
1.796
1.791
1.787
0.792
1.5
3
4.5
6
7.5
9
1.5
4.5
6
7.5
9
0
OUTPUT VOLTAGE (V)
650
600
550
VIN = 12V
VOUT = 1.8V
8
4.6
4.2
TA
25ºC
85ºC
125ºC
3.8
3.4
2
Die Temperature* (VIN = 12V)
vs. Output Current
4
6
8
10
3
5
6
8
9
4.5
6
7.5
9
VIN = 12V
3.0
2.5
VOUT = 3.3V
2.0
1.5
1.0
VOUT = 0.8V
0.5
0.0
0
3
3.5
POWER DISSIPATION (W)
POWER DISSIPATION (W)
DIE TEMPERATURE (°C)
VIN = 12V
VOUT = 1.8V
OUTPUT CURRENT (A)
1.5
IC Power Dissipation (VIN = 12V)
vs. Output Current
VIN = 5V
2
VIN = 5V
VOUT = 1.8V
OUTPUT CURRENT (A)
3.5
0
20
0
12
80
20
9
40
IC Power Dissipation (VIN = 5V)
vs. Output Current
40
7.5
60
OUTPUT CURRENT (A)
OUTPUT CURRENT (A)
60
6
0
0
10
4.5
80
VIN = 5V
VFB < 0.8V
3.0
500
3
Die Temperature* (VIN = 5V)
vs. Output Current
5.0
6
1.5
OUTPUT CURRENT (A)
Output Voltage (VIN = 5V)
vs. Output Current
700
FREQUENCY (kHz)
3
OUTPUT CURRENT (A)
Switching Frequency
vs. Output Current
4
-0.5%
-1.0%
0
OUTPUT CURRENT (A)
2
0.0%
VIN = 4.5V to 19V
VOUT = 1.8V
1.782
0
0.5%
VIN = 12V
VOUT = 1.8V
DIE TEMPERATURE (°C)
FEEDBACK VOLTAGE (V)
0.808
Line Regulation
vs. Output Current
3.0
2.5
VOUT = 5.0V
2.0
1.5
1.0
0.5
VOUT = 0.8V
0.0
0
1.5
3
4.5
6
OUTPUT CURRENT (A)
7.5
9
0
1.5
3
4.5
6
7.5
9
OUTPUT CURRENT (A)
Die Temperature* : The temperature measurement was taken at the hottest point on the MIC24054 case mounted on a 5 square inch 4 layer, 0.62”,
FR-4 PCB with 2oz finish copper weight per layer, see Thermal Measurement section. Actual results will depend upon the size of the PCB, ambient
temperature and proximity to other heat emitting components.
October 2012
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Micrel, Inc.
MIC24054
Typical Characteristics (Continued)
Efficiency (VIN = 12V)
vs. Output Current
Efficiency (VIN = 5V)
vs. Output Current
100
100
3.3V
2.5V
1.8V
1.5V
1.2V
1.0V
0.9V
0.8V
85
80
75
70
5.0V
3.3V
2.5V
1.8V
1.5V
1.2V
1.0V
0.9V
0.8V
90
EFFICIENCY (%)
90
65
85
80
75
70
65
60
60
55
VIN = 5V
55
0
2
4
6
8
10
8
6
4
10
OUTPUT CURRENT (A)
OUTPUT CURRENT (A)
Thermal Derating*
vs. Ambient Temperature
Thermal Derating*
vs. Ambient Temperature
14
OUTPUT CURRENT (A)
1.8V
10
8
3.3V
6
4
VIN = 5V
VOUT = 1.8, 2.5, 3.3V
2
-25
0
25
50
75
100
AMBIENT TEMPERATURE (°C)
125
VIN = 5V
VOUT = 0.8, 1.2, 1.5V
-50
-25
0
25
50
75
100
125
AMBIENT TEMPERATURE (°C)
Thermal Derating*
vs. Ambient Temperature
12
0.8V
10
8
1.8V
6
4
VIN = 12V
VOUT = 0.8, 1.2, 1.8V
12
2.5V
10
5V
8
6
4
VIN = 12V
VOUT = 2.5, 3.3, 5V
2
0
-50
4
14
2
0
1.5V
6
12
14
12
8
0
2
0
12
0.8V
10
VIN = 12V
50
50
12
2
OUTPUT CURRENT (A)
EFFICIENCY (%)
14
95
OUTPUT CURRENT (A)
95
OUTPUT CURRENT (A)
Thermal Derating*
vs. Ambient Temperature
0
-50
-25
0
25
50
75
100
AMBIENT TEMPERATURE (°C)
125
-50
-25
0
25
50
75
100
125
AMBIENT TEMPERATURE (°C)
Die Temperature* : The temperature measurement was taken at the hottest point on the MIC24054 case mounted on a 5 square inch 4 layer, 0.62”,
FR-4 PCB with 2oz finish copper weight per layer, see Thermal Measurement section. Actual results will depend upon the size of the PCB, ambient
temperature and proximity to other heat emitting components.
October 2012
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M9999-102512-A
Micrel, Inc.
MIC24054
Functional Characteristics
October 2012
10
M9999-102512-A
Micrel, Inc.
MIC24054
Functional Characteristics (Continued)
October 2012
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M9999-102512-A
Micrel, Inc.
MIC24054
Functional Characteristics (Continued)
October 2012
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Micrel, Inc.
MIC24054
Functional Diagram
Figure 1. MIC24054 Block Diagram
October 2012
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Micrel, Inc.
MIC24054
The maximum duty cycle is obtained from the 300ns
tOFF(min):
Functional Description
The MIC24054 is an adaptive ON-time synchronous
step-down DC/DC regulator with an internal 5V linear
regulator and a Power Good (PG) output. It is designed
to operate over a wide input voltage range from 4.5V to
19V and provides a regulated output voltage at up to 9A
of output current. An adaptive ON-time control scheme is
employed in to obtain a constant switching frequency
and to simplify the control compensation. Over-current
protection is implemented without the use of an external
sense resistor. The device includes an internal soft-start
function which reduces the power supply input surge
current at start-up by controlling the output voltage rise
time.
Dmax =
= 1-
300ns
tS
Eq. 2
It is not recommended to use MIC24054 with a OFF-time
close to tOFF(min) during steady-state operation. Also, as
VOUT increases, the internal ripple injection will increase
and reduce the line regulation performance. Therefore,
the maximum output voltage of the MIC24054 should be
limited to 5.5V and the maximum external ripple injection
should be limited to 200mV. Please refer to “Setting
Output Voltage” subsection in Application Information for
more details.
The actual ON-time and resulting switching frequency
will vary with the part-to-part variation in the rise and fall
times of the internal MOSFETs, the output load current,
and variations in the VDD voltage. Also, the minimum tON
results in a lower switching frequency in high VIN to VOUT
applications, such as 18V to 1.0V. The minimum tON
measured on the MIC24054 evaluation board is about
100ns. During load transients, the switching frequency is
changed due to the varying OFF-time.
To illustrate the control loop operation, we will analyze
both the steady-state and load transient scenarios.
Figure 2 shows the MIC24054 control loop timing during
steady-state operation. During steady-state, the gm
amplifier senses the feedback voltage ripple, which is
proportional to the output voltage ripple and the inductor
current ripple, to trigger the ON-time period. The ONtime is predetermined by the tON estimator. The
termination of the OFF-time is controlled by the feedback
voltage. At the valley of the feedback voltage ripple,
which occurs when VFB falls below VREF, the OFF period
ends and the next ON-time period is triggered through
the control logic circuitry.
Continuous Mode
In continuous mode, the output voltage is sensed by the
MIC24054 feedback pin FB via the voltage divider R1
and R2, and compared to a 0.8V reference voltage VREF
at the error comparator through a low gain
transconductance (gm) amplifier. If the feedback voltage
decreases and the output of the gm amplifier is below
0.8V, then the error comparator will trigger the control
logic and generate an ON-time period. The ON-time
period length is predetermined by the “FIXED tON
ESTIMATION” circuitry:
VOUT
VIN × 600kHz
tS
where tS = 1/600kHz = 1.66μs.
Theory of Operation
The MIC24054 is able to operate in either continuous
mode or discontinuous mode. The operating mode is
determined by the output of the Zero Cross comparator
(ZC) as shown in Figure 1.
t ON(estimated) =
t S - t OFF(min)
Eq. 1
where VOUT is the output voltage and VIN is the power
stage input voltage.
At the end of the ON-time period, the internal high-side
driver turns off the high-side MOSFET and the low-side
driver turns on the low-side MOSFET. The OFF-time
period length depends upon the feedback voltage in
most cases. When the feedback voltage decreases and
the output of the gm amplifier is below 0.8V, the ON-time
period is triggered and the OFF-time period ends. If the
OFF-time period determined by the feedback voltage is
less than the minimum OFF-time tOFF(min), which is about
300ns, the MIC24054 control logic will apply the tOFF(min)
instead. tOFF(min) is required to maintain enough energy in
the boost capacitor (CBST) to drive the high-side
MOSFET.
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MIC24054
Unlike true current-mode control, the MIC24054 uses the
output voltage ripple to trigger an ON-time period. The
output voltage ripple is proportional to the inductor
current ripple if the ESR of the output capacitor is large
enough. The MIC24054 control loop has the advantage
of eliminating the need for slope compensation.
In order to meet the stability requirements, the
MIC24054 feedback voltage ripple should be in phase
with the inductor current ripple and large enough to be
sensed by the gm amplifier and the error comparator.
The recommended feedback voltage ripple is
20mV~100mV. If a low-ESR output capacitor is selected,
then the feedback voltage ripple may be too small to be
sensed by the gm amplifier and the error comparator.
Also, the output voltage ripple and the feedback voltage
ripple are not necessarily in phase with the inductor
current ripple if the ESR of the output capacitor is very
low. In these cases, ripple injection is required to ensure
proper operation. Please refer to “Ripple Injection”
subsection in Application Information for more details
about the ripple injection technique.
Figure 2. MIC24054 Control Loop Timing
Figure 3 shows the operation of the MIC24054 during a
load transient. The output voltage drops due to the
sudden load increase, which causes the VFB to be less
than VREF. This will cause the error comparator to trigger
an ON-time period. At the end of the ON-time period, a
minimum OFF-time tOFF(min) is generated to charge CBST
since the feedback voltage is still below VREF. Then, the
next ON-time period is triggered due to the low feedback
voltage. Therefore, the switching frequency changes
during the load transient, but returns to the nominal fixed
frequency once the output has stabilized at the new load
current level. With the varying duty cycle and switching
frequency, the output recovery time is fast and the
output voltage deviation is small in MIC24054 converter.
Discontinuous Mode
In continuous mode, the inductor current is always
greater than zero; however, at light loads the MIC24054
is able to force the inductor current to operate in
discontinuous mode. Discontinuous mode is where the
inductor current falls to zero, as indicated by trace (IL)
shown in Figure 4. During this period, the efficiency is
optimized by shutting down all the non-essential circuits
and minimizing the supply current. The MIC24054 wakes
up and turns on the high-side MOSFET when the
feedback voltage VFB drops below 0.8V.
The MIC24054 has a zero crossing comparator that
monitors the inductor current by sensing the voltage
drop across the low-side MOSFET during its ON-time. If
the VFB > 0.8V and the inductor current goes slightly
negative, then the MIC24054 automatically powers down
most of the IC circuitry and goes into a low-power mode.
Once the MIC24054 goes into discontinuous mode, both
LSD and HSD are low, which turns off the high-side and
low-side MOSFETs. The load current is supplied by the
output capacitors and VOUT drops. If the drop of VOUT
causes VFB to go below VREF, then all the circuits will
wake up into normal continuous mode. First, the bias
currents of most circuits reduced during the
discontinuous mode are restored, then a tON pulse is
triggered before the drivers are turned on to avoid any
possible glitches. Finally, the high-side driver is turned
on. Figure 4 shows the control loop timing in
discontinuous mode.
Figure 3. MIC24054 Load Transient Response
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MIC24054
Current Limit
The MIC24054 uses the RDS(ON) of the internal low-side
power MOSFET to sense over-current conditions. This
method will avoid adding cost, board space and power
losses taken by a discrete current sense resistor. The
low-side MOSFET is used because it displays much
lower parasitic oscillations during switching than the
high-side MOSFET.
In each switching cycle of the MIC24054 converter, the
inductor current is sensed by monitoring the low-side
MOSFET in the OFF period. If the inductor current is
greater than 14A, then the MIC24054 turns off the highside MOSFET and a soft-start sequence is triggered.
This mode of operation is called “hiccup mode” and its
purpose is to protect the downstream load in case of a
hard short. The load current-limit threshold has a fold
back characteristic related to the feedback voltage as
shown in Figure 5.
Figure 4. MIC24054 Control Loop Timing
(Discontinuous Mode)
Current Limit Threshold
vs. Feedback Voltage
CURRENT LIMIT THRESHOLD (A)
20
During discontinuous mode, the zero crossing
comparator and the current limit comparator are turned
off. The bias current of most circuits are reduced. As a
result, the total power supply current during
discontinuous mode is only about 450μA, allowing the
MIC24054 to achieve high efficiency in light load
applications.
16
12
VDD Regulator
The MIC24054 provides a 5V regulated output for input
voltage VIN ranging from 5.5V to 19V. When VIN < 5.5V,
VDD should be tied to PVIN pins to bypass the internal
linear regulator.
4
0
0.0
0.2
0.4
0.6
0.8
1.0
FEEDBACK VOLTAGE (V)
Soft-Start
Soft-start reduces the power supply input surge current
at startup by controlling the output voltage rise time. The
input surge appears while the output capacitor is
charged up. A slower output rise time will draw a lower
input surge current.
The MIC24054 implements an internal digital soft-start
by making the 0.8V reference voltage VREF ramp from 0
to 100% in about 3ms with 9.7mV steps. Therefore, the
output voltage is controlled to increase slowly by a staircase VFB ramp. Once the soft-start cycle ends, the
related circuitry is disabled to reduce current
consumption. VDD must be powered up at the same time
or after VIN to make the soft-start function correctly.
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Figure 5. MIC24054 Current-Limit Foldback Characteristic
Power-Good (PG)
The Power Good (PG) pin is an open drain output which
indicates logic high when the output is nominally 92% of
its steady state voltage. A pull-up resistor of more than
10kΩ should be connected from PG to VDD.
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MIC24054
MOSFET Gate Drive
The Block Diagram (Figure 1) shows a bootstrap circuit,
consisting of D1 (a Schottky diode is recommended) and
CBST. This circuit supplies energy to the high-side drive
circuit. Capacitor CBST is charged, while the low-side
MOSFET is on, and the voltage on the SW pin is
approximately 0V. When the high-side MOSFET driver is
turned on, energy from CBST is used to turn the MOSFET
on. As the high-side MOSFET turns on, the voltage on
the SW pin increases to approximately VIN. Diode D1 is
reverse biased and CBST floats high while continuing to
keep the high-side MOSFET on. The bias current of the
high-side driver is less than 10mA so a 0.1μF to 1μF is
sufficient to hold the gate voltage with minimal droop for
the power stroke (high-side switching) cycle, i.e. ΔBST =
10mA x 1.67μs/0.1μF = 167mV. When the low-side
MOSFET is turned back on, CBST is recharged through
D1. A small resistor RG, which is in series with CBST, can
be used to slow down the turn-on time of the high-side
N-channel MOSFET.
The drive voltage is derived from the VDD supply voltage.
The nominal low-side gate drive voltage is VDD and the
nominal high-side gate drive voltage is approximately
VDD – VDIODE, where VDIODE is the voltage drop across
D1. An approximate 30ns delay between the high-side
and low-side driver transitions is used to prevent current
from simultaneously flowing unimpeded through both
MOSFETs.
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MIC24054
Maximizing efficiency requires the proper selection of
core material and minimizing the winding resistance. The
high frequency operation of the MIC24054 requires the
use of ferrite materials for all but the most cost sensitive
applications. Lower cost iron powder cores may be used
but the increase in core loss will reduce the efficiency of
the power supply. This is especially noticeable at low
output power. The winding resistance decreases
efficiency at the higher output current levels. The
winding resistance must be minimized although this
usually comes at the expense of a larger inductor. The
power dissipated in the inductor is equal to the sum of
the core and copper losses. At higher output loads, the
core losses are usually insignificant and can be ignored.
At lower output currents, the core losses can be a
significant contributor. Core loss information is usually
available from the magnetics vendor. Copper loss in the
inductor is calculated by Equation 7:
Application Information
Inductor Selection
Values for inductance, peak, and RMS currents are
required to select the output inductor. The input and
output voltages and the inductance value determine the
peak-to-peak inductor ripple current. Generally, higher
inductance values are used with higher input voltages.
Larger peak-to-peak ripple currents will increase the
power dissipation in the inductor and MOSFETs. Larger
output ripple currents will also require more output
capacitance to smooth out the larger ripple current.
Smaller peak-to-peak ripple currents require a larger
inductance value and therefore a larger and more
expensive inductor. A good compromise between size,
loss and cost is to set the inductor ripple current to be
equal to 20% of the maximum output current. The
inductance value is calculated by Equation 3:
2
L=
PINDUCTOR(Cu) = IL(RMS) × RWINDING
VOUT × (VIN(max) − VOUT )
VIN(max) × fsw × 20% × IOUT(max)
Eq. 3
The resistance of the copper wire, RWINDING, increases
with the temperature. The value of the winding
resistance used should be at the operating temperature.
where:
fSW = switching frequency, 600kHz
20% = ratio of AC ripple current to DC output current
VIN(max) = maximum power stage input voltage
The peak-to-peak inductor current ripple is:
∆IL(pp) =
VOUT × (VIN(max) − VOUT )
VIN(max) × fsw × L
PWINDING(Ht) = RWINDING(20°C) × (1 + 0.0042 × (TH – T20°C))
Eq. 8
where:
TH = temperature of wire under full load
T20°C = ambient temperature
RWINDING(20°C) = room temperature winding resistance
(usually specified by the manufacturer)
Eq. 4
The peak inductor current is equal to the average output
current plus one half of the peak-to-peak inductor current
ripple.
IL(pk) =IOUT(max) + 0.5 × ΔIL(pp)
Output Capacitor Selection
The type of the output capacitor is usually determined by
its equivalent series resistance (ESR). Voltage and RMS
current capability are two other important factors for
selecting the output capacitor. Recommended capacitor
types are tantalum, low-ESR aluminum electrolytic, OSCON and POSCAP. The output capacitor’s ESR is
usually the main cause of the output ripple. The output
capacitor ESR also affects the control loop from a
stability point of view.
Eq. 5
2
The RMS inductor current is used to calculate the I R
losses in the inductor.
2
IL(RMS) = IOUT(max) +
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ΔIL(PP)
12
Eq. 7
2
Eq. 6
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MIC24054
Input Capacitor Selection
The input capacitor for the power stage input VIN should
be selected for ripple current rating and voltage rating.
Tantalum input capacitors may fail when subjected to
high inrush currents, caused by turning the input supply
on. A tantalum input capacitor’s voltage rating should be
at least two times the maximum input voltage to
maximize reliability. Aluminum electrolytic, OS-CON, and
multilayer polymer film capacitors can handle the higher
inrush currents without voltage de-rating. The input
voltage ripple will primarily depend on the input
capacitor’s ESR. The peak input current is equal to the
peak inductor current, so:
The maximum value of ESR is calculated:
ESR COUT ≤
ΔVOUT(pp)
Eq. 9
ΔIL(PP)
where:
ΔVOUT(pp) = peak-to-peak output voltage ripple
ΔIL(PP) = peak-to-peak inductor current ripple
The total output ripple is a combination of the ESR and
output capacitance. The total ripple is calculated in
Equation 10:
2
ΔVIN = IL(pk) × ESRCIN
ΔIL(PP)
2
+ ΔIL(PP) × ESR C
ΔVOUT(pp) =
OUT
C
×
f
×
8
OUT SW
Eq. 10
(
)
The input capacitor must be rated for the input current
ripple. The RMS value of input capacitor current is
determined at the maximum output current. Assuming
the peak-to-peak inductor current ripple is low:
where:
D = Duty cycle
COUT = Output capacitance value
fSW = Switching frequency
ICIN(RMS) ≈ IOUT(max) × D × (1 − D)
2
ΔIL(PP)
Eq. 14
The power dissipated in the input capacitor is:
PDISS(CIN) = ICIN(RMS) × ESRCIN
As described in the “Theory of Operation” subsection in
the Functional Description section, the MIC24054
requires at least 20mV peak-to-peak ripple at the FB pin
to make the gm amplifier and the error comparator
behave properly. Also, the output voltage ripple should
be in phase with the inductor current. Therefore, the
output voltage ripple caused by the output capacitors
value should be much smaller than the ripple caused by
the output capacitor ESR. If low-ESR capacitors, such
as ceramic capacitors, are selected as the output
capacitors, a ripple injection method should be applied to
provide the enough feedback voltage ripple. Please refer
to the “Ripple Injection” subsection for more details.
The voltage rating of the capacitor should be twice the
output voltage for a tantalum and 20% greater for
aluminum electrolytic or OS-CON. The output capacitor
RMS current is calculated below:
ICOUT (RMS) =
Eq. 13
Eq. 15
Ripple Injection
The VFB ripple required for proper operation of the
MIC24054 gm amplifier and error comparator is 20mV to
100mV. However, the output voltage ripple is generally
designed as 1% to 2% of the output voltage. For a low
output voltage, such as a 1V, the output voltage ripple is
only 10mV to 20mV, and the feedback voltage ripple is
less than 20mV. If the feedback voltage ripple is so small
that the gm amplifier and error comparator can’t sense it,
then the MIC24054 will lose control and the output
voltage is not regulated. In order to have some amount
of VFB ripple, a ripple injection method is applied for low
output voltage ripple applications.
Eq. 11
12
The power dissipated in the output capacitor is:
2
PDISS(COUT ) = ICOUT (RMS) × ESR COUT
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Eq. 12
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MIC24054
The applications are divided into three situations
according to the amount of the feedback voltage ripple:
1. Enough ripple at the feedback voltage due to the
large ESR of the output capacitors.
As shown in Figure 6, the converter is stable without any
ripple injection. The feedback voltage ripple is:
Figure 8. Invisible Ripple at FB
ΔVFB(pp)
R2
=
× ESR COUT × ΔIL (pp)
R1 + R2
Eq. 16
In this situation, the output voltage ripple is less than
20mV. Therefore, additional ripple is injected into the FB
pin from the switching node SW via a resistor Rinj and a
capacitor Cinj, as shown in Figure 8. The injected ripple
is:
where: ΔIL(pp) is the peak-to-peak value of the inductor
current ripple.
2. Inadequate ripple at the feedback voltage due to the
small ESR of the output capacitors.
ΔVFB(pp) = VIN × K div × D × (1 - D) ×
The output voltage ripple is fed into the FB pin through a
feedforward capacitor Cff in this situation, as shown in
Figure 7. The typical Cff value is between 1nF and
100nF. With the feedforward capacitor, the feedback
voltage ripple is very close to the output voltage ripple:
ΔVFB(pp) ≈ ESR × ΔIL (pp)
K div =
R1//R2
R inj + R1//R2
1
fSW × τ
Eq. 18
Eq. 19
where:
VIN = Power stage input voltage
D = Duty cycle
fSW = Switching frequency
τ = (R1//R2//Rinj) × Cff
Eq. 17
3. Virtually no ripple at the FB pin voltage due to the
very low ESR of the output capacitors.
In Equations 18 and 19, it is assumed that the time
constant associated with Cff must be much greater than
the switching period:
1
T
=
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