MIC4100/1
100V Half-Bridge MOSFET Drivers
Features
General Description
• Bootstrap Supply Voltage to 118V DC
• Supply Voltage up to 16V
• Drives High- and Low-Side N-Channel MOSFETs
with Independent Inputs
• CMOS Input Thresholds (MIC4100)
• TTL Input Thresholds (MIC4101)
• On-Chip Bootstrap Diode
• Fast 30 ns Propagation Times
• Drives 1000 pF Load with 10 ns Rise and Fall
Times
• Low Power Consumption
• Supply Undervoltage Protection
• 3Ω Pull-Up, 3Ω Pull-Down Output Resistance
• Space Saving 8-Lead SOIC Package
• –40°C to +125°C Junction Temperature Range
The MIC4100 and MIC4101 are high frequency, 100V
half-bridge MOSFET driver ICs that feature fast 30 ns
propagation delay times. The low-side and high-side
gate drivers are independently controlled and matched
to within 3 ns typical. The MIC4100 has CMOS input
thresholds and the MIC4101 has TTL input thresholds.
The MIC4100/1 include a high voltage internal diode
that charges the high-side gate drive bootstrap
capacitor.
A robust, high-speed, and low-power level shifter
provides clean level transitions to the high-side output.
The robust operation of the MIC4100/1 ensure the
outputs are not affected by supply glitches, HS ringing
below ground, or HS slewing with high speed voltage
transitions. Undervoltage protection is provided on both
the low-side and high-side drivers.
The MIC4100/1 is available in the 8-lead SOIC
package with a junction operating range from
–40°C to +125°C.
Applications
•
•
•
•
High Voltage Buck Converters
Push-Pull Converters
Full- and Half-Bridge Converters
Active Clamp Forward Converters
Typical Application Schematic
MIC4100/1
9V to 16V Bias
100V Supply
VDD
PWM
Controller
HI
MIC4100/1
SOIC-8
HO
V OUT
HS
LI
GND
2022 Microchip Technology Inc. and its subsidiaries
HB
LO
DS20006699A-page 1
MIC4100/1
Functional Block Diagram
MIC4100/1
HV
HB
HO
UVLO
LEVEL
SHIFT
DRIVER
HS
HI
VDD
UVLO
LO
DRIVER
LI
VSS
DS20006699A-page 2
2022 Microchip Technology Inc. and its subsidiaries
MIC4100/1
1.0
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings †
Supply Voltage (VDD, VHB – VHS) .............................................................................................................. –0.3V to +18V
Input Voltages (VLI, VHI)....................................................................................................................–0.3V to VDD + 0.3V
Voltage on LO (VLO)..........................................................................................................................–0.3V to VDD + 0.3V
Voltage on HO (VHO).................................................................................................................VHS – 0.3V to VHB + 0.3V
Voltage on HS (Continuous) ........................................................................................................................–1V to +110V
Voltage on HB ......................................................................................................................................................... +118V
Average Current in VDD to HB Diode ....................................................................................................................100 mA
ESD Rating .............................................................................................................................................................Note 1
Operating Ratings ‡
Supply Voltage (VDD) .................................................................................................................................... +9V to +16V
Voltage on HS ............................................................................................................................................. –1V to +100V
Voltage on HS (Repetitive Transient) .......................................................................................................... –5V to +105V
HS Slew Rate........................................................................................................................................................ 50 V/ns
Voltage on HB .............................................................................................................................. VHS + 8V to VHS + 16V
and ............................................................................................................................................. VDD – 1V to VDD + 100V
† Notice: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device.
This is a stress rating only and functional operation of the device at those or any other conditions above those indicated
in the operational sections of this specification is not intended. Exposure to maximum rating conditions for extended
periods may affect device reliability.
‡ Notice: The device is not guaranteed to function outside its operating ratings.
Note 1: Devices are ESD sensitive. Handling precautions are recommended. Human body model, 1.5 kΩ in series
with 100 pF.
2022 Microchip Technology Inc. and its subsidiaries
DS20006699A-page 3
MIC4100/1
ELECTRICAL CHARACTERISTICS
Electrical Characteristics: VDD = VHB = 12V; VSS = VHS = 0V; No load on LO or HO; TA = +25°C; unless noted.
Bold values are valid for –40°C ≤ TJ ≤ +125°C. (Note 1).
Parameters
Symbol
Min.
Typ.
Max.
—
40
150
—
—
200
—
2.5
3.4
—
25
150
—
—
200
—
1.4
2.5
—
—
3
Units
Conditions
Supply Current
VDD Quiescent Current
IDD
VDD Operating Current
IDDO
µA
LI = HI = 0V
mA
f = 500 kHz
µA
LI = HI = 0V
mA
f = 500 kHz
Total HB Quiescent Current
IHB
Total HB Operating Current
IHBO
HB to VSS Quiescent Current
IHBS
—
0.05
1
µA
VHS = VHB = 110V
HB to VSS Operating Current
IHBSO
—
10
—
µA
f = 500 kHz
4
5.3
—
3
—
—
V
—
—
5.7
7
—
—
8
V
—
VIHYS
—
0.4
—
V
—
RI
100
200
500
kΩ
—
Low Level Input Voltage Threshold
VIL
0.8
1.5
—
V
—
High Level Input Voltage Threshold
VIH
—
1.5
2.2
V
—
Input Pull-Down Resistance
RI
100
200
500
kΩ
—
VDD Rising Threshold
VDDR
6.5
7.4
8.0
V
—
VDD Threshold Hysteresis
VDDH
—
0.5
—
V
—
HB Rising Threshold
VHBR
6.0
7.0
8.0
V
—
HB Threshold Hysteresis
VHBH
—
0.4
—
V
—
—
0.4
0.55
—
—
0.70
V
IVDD-HB = 100 µA
—
0.7
0.8
—
—
1.0
V
IVDD-HB = 100 mA
—
1.0
1.5
—
—
2.0
Ω
IVDD-HB = 100 mA
Input Pins: MIC4100 (CMOS Input)
Low Level Input Voltage Threshold
VIL
High Level Input Voltage Threshold
VIH
Input Voltage Hysteresis
Input Pull-Down Resistance
Input Pins: MIC4101 (TTL Input)
Undervoltage Protection
Bootstrap Diode
Low-Current Forward Voltage
VDL
High-Current Forward Voltage
VDH
Dynamic Resistance
RD
Note 1:
2:
Specification for packaged product only.
Ensured by design. Not production tested.
DS20006699A-page 4
2022 Microchip Technology Inc. and its subsidiaries
MIC4100/1
ELECTRICAL CHARACTERISTICS (CONTINUED)
Electrical Characteristics: VDD = VHB = 12V; VSS = VHS = 0V; No load on LO or HO; TA = +25°C; unless noted.
Bold values are valid for –40°C ≤ TJ ≤ +125°C. (Note 1).
Parameters
Symbol
Min.
Typ.
Max.
—
0.22
0.3
—
—
0.4
—
0.25
0.3
—
—
0.45
Units
Conditions
LO Gate Driver
V
ILO = 100 mA
V
ILO = –100 mA,
VOHL = VDD – VLO
—
A
VLO = 0V
2
—
A
VLO = 12V
—
0.22
0.3
—
—
0.4
V
IHO = 100 mA
—
0.25
0.3
—
—
0.45
V
IHO = –100 mA,
VOHH = VHB – VHO
Low Level Output Voltage
VOLL
High Level Output Voltage
VOHL
Peak Sink Current
IOHL
—
2
Peak Source Current
IOLL
—
HO Gate Driver
Low Level Output Voltage
VOLH
High Level Output Voltage
VOHH
Peak Sink Current
IOHH
—
2
—
A
VHO = 0V
Peak Source Current
IOLH
—
2
—
A
VHO = 12V
Lower Turn-Off Propagation Delay
(LI Falling to LO Falling)
tLPHL
—
27
45
ns
(MIC4100)
Upper Turn-Off Propagation Delay
(HI Falling to HO Falling)
tHPHL
—
27
45
ns
(MIC4100)
Lower Turn-On Propagation Delay
(LI Rising to LO Rising)
tLPLH
—
27
45
ns
(MIC4100)
Upper Turn-On Propagation Delay
(HI Rising to HO Rising)
tHPLH
—
27
45
ns
(MIC4100)
Lower Turn-Off Propagation Delay
(LI Falling to LO Falling)
tLPHL
—
31
55
ns
(MIC4101)
Upper Turn-Off Propagation Delay
(HI Falling to HO Falling)
tHPHL
—
31
55
ns
(MIC4101)
Lower Turn-On Propagation Delay
(LI Rising to LO Rising)
tLPLH
—
31
55
ns
(MIC4101)
Upper Turn-On Propagation Delay
(HI Rising to HO Rising)
tHPLH
—
31
55
ns
(MIC4101)
Delay Matching: Lower Turn-On
and Upper Turn-Off
tM(ON)
—
3
8
ns
—
—
10
ns
Delay Matching: Lower Turn-Off
and Upper Turn-On
tM(OFF)
—
3
8
ns
—
—
10
ns
Either Output Rise/Fall Time
tRC/tFC
—
10
—
ns
Switching Specifications
Note 1:
2:
—
—
CL = 1000 pF
Specification for packaged product only.
Ensured by design. Not production tested.
2022 Microchip Technology Inc. and its subsidiaries
DS20006699A-page 5
MIC4100/1
ELECTRICAL CHARACTERISTICS (CONTINUED)
Electrical Characteristics: VDD = VHB = 12V; VSS = VHS = 0V; No load on LO or HO; TA = +25°C; unless noted.
Bold values are valid for –40°C ≤ TJ ≤ +125°C. (Note 1).
Parameters
Symbol
Min.
Typ.
Max.
—
0.4
0.6
—
—
0.8
Either Output Rise/Fall Time
(3V to 9V)
tR/tF
Minimum Input Pulse Width that
changes the output
tPW
—
—
Bootstrap Diode Turn-On or
Turn-Off Time
tBS
—
10
Note 1:
2:
Units
Conditions
µs
CL = 0.1 µF
50
ns
Note 2
—
ns
—
Specification for packaged product only.
Ensured by design. Not production tested.
TEMPERATURE SPECIFICATIONS
Parameters
Sym.
Min.
Typ.
Max.
Units
Conditions
Max. Junction Temperature Range
TJ
–55
—
+150
°C
Note 1
Storage Temperature Range
TS
–60
—
+150
°C
—
Operating Junction Temperature
Range
TJ
–40
—
+125
°C
—
JA
—
140
—
°C/W
—
Temperature Ranges
Package Thermal Resistances
Thermal Resistance, SOIC-8Ld
Note 1:
The maximum allowable power dissipation is a function of ambient temperature, the maximum allowable
junction temperature and the thermal resistance from junction to air (i.e., TA, TJ, JA). Exceeding the
maximum allowable power dissipation will cause the device operating junction temperature to exceed the
maximum +125°C rating. Sustained junction temperatures above +125°C can impact the device reliability.
DS20006699A-page 6
2022 Microchip Technology Inc. and its subsidiaries
MIC4100/1
2.0
Note:
TYPICAL PERFORMANCE CURVES
The graphs and tables provided following this note are a statistical summary based on a limited number of
samples and are provided for informational purposes only. The performance characteristics listed herein
are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified
operating range (e.g., outside specified power supply range) and therefore outside the warranted range.
FIGURE 2-1:
Supply Voltage.
Quiescent Current vs.
FIGURE 2-4:
Temperature.
Operating Current vs.
FIGURE 2-2:
Temperature.
Quiescent Current vs.
FIGURE 2-5:
Frequency.
Operating Current vs.
FIGURE 2-3:
Supply Voltage.
Operating Current vs.
FIGURE 2-6:
vs. Temperature.
Low Level Output Voltage
2022 Microchip Technology Inc. and its subsidiaries
DS20006699A-page 7
MIC4100/1
FIGURE 2-7:
vs. Temperature.
High Level Output Voltage
FIGURE 2-10:
vs. Temperature.
MIC4100 Propagation Delay
FIGURE 2-8:
Temperature.
UVLO Thresholds vs.
FIGURE 2-11:
vs. Temperature.
MIC4101 Propagation Delay
FIGURE 2-9:
Temperature.
UVLO Thresholds vs.
FIGURE 2-12:
MIC4100 Propagation Delay
Matching vs. Temperature.
DS20006699A-page 8
2022 Microchip Technology Inc. and its subsidiaries
MIC4100/1
FIGURE 2-13:
MIC4101 Propagation Delay
Matching vs. Temperature.
FIGURE 2-16:
Characteristics.
Bootstrap Diode I-V
FIGURE 2-14:
MIC4100 Propagation Delay
vs. Supply Voltage.
FIGURE 2-17:
Current.
Bootstrap Diode Reverse
FIGURE 2-15:
MIC4101 Propagation Delay
vs. Supply Voltage.
2022 Microchip Technology Inc. and its subsidiaries
DS20006699A-page 9
MIC4100/1
3.0
PIN DESCRIPTIONS
The descriptions of the pins are listed in Table 3-1.
Package Type
MIC4100/1
8-Lead SOIC (M)
(Top View)
VDD 1
TABLE 3-1:
8 LO
HB 2
7 VSS
HO 3
6 LI
HS 4
5 HI
PIN FUNCTION TABLE
Pin Number
Pin Name
1
VDD
2
HB
High-Side Bootstrap supply. External bootstrap capacitor is required. Connect positive
side of bootstrap capacitor to this pin. Bootstrap diode is on-chip.
3
HO
High-Side Output. Connect to gate of high-side power MOSFET.
4
HS
High-Side Source connection. Connect to source of high-side power MOSFET.
Connect negative side of bootstrap capacitor to this pin.
5
HI
High-Side Input.
6
LI
Low-Side Input.
7
VSS
8
LO
DS20006699A-page 10
Description
Positive supply to lower gate drivers. Decouple this pin to VSS (Pin 7). Bootstrap
diode connected to HB (Pin 2).
Chip negative supply. Generally, this will be grounded.
Low-Side Output. Connect to gate of low-side power MOSFET.
2022 Microchip Technology Inc. and its subsidiaries
MIC4100/1
4.0
TIMING DIAGRAM
LI
HI, LI
HI
tHPLH
tLPLH
t HPLH
t LPLH
LO
HO,LO
tMON
t MOFF
HO
FIGURE 4-1:
Note:
MIC4100/1 Timing Diagram.
All propagation delays are measured from the 50% voltage level.
2022 Microchip Technology Inc. and its subsidiaries
DS20006699A-page 11
MIC4100/1
5.0
FUNCTIONAL DESCRIPTION
The MIC4100 is a high voltage, non-inverting,
synchronous MOSFET driver that has independent
high-side and low-side PWM input pins that drive both
high-side and low-side N-Channel MOSFETs. Refer to
the Functional Block Diagram.
Both drivers contain an input buffer with hysteresis, a
UVLO circuit and an output buffer. The high-side output
buffer includes a high speed level shifting circuit that is
referenced to the HS pin. An internal diode is used as
part of a bootstrap circuit to provide the drive voltage for
the high-side output.
5.1
Startup and UVLO
The UVLO circuit forces both driver outputs low until
the supply voltage exceeds the UVLO threshold. The
low-side UVLO circuit monitors the voltage between
the VDD and VSS pins. The high-side UVLO circuit
monitors the voltage between the HB and HS pins.
Hysteresis in the UVLO circuit prevents noise and finite
circuit impedance from causing chatter during turn-on.
5.2
Input Stage
The MIC4100 and MIC4101 have different input
stages, which lets these parts cover a wide range of
driver applications. Both the HI and LI pins are
referenced to the VSS pin. The voltage state of the
input signal does not change the quiescent current
draw of the driver.
The MIC4100 has a high impedance, CMOS
compatible input range and is recommended for
applications where the input signal is noisy or where
the input signal swings the full range of voltage (from
VDD to GND). There is typically 400 mV of hysteresis
on the input pins throughout the VDD range. The
hysteresis improves noise immunity and prevents input
signals with slow rise times from falsely triggering the
output. The threshold voltage of the MIC4100 varies
proportionally with the VDD supply voltage.
The amplitude of the input signal affects the VDD supply
current. Vin voltages that are a diode drop less than the
VDD supply voltage will cause an increase in the VDD
pin current. The graph in Figure 5-1 shows the typical
dependence between IVDD and VIN for VDD = 12V.
FIGURE 5-1:
Voltage.
5.3
Supply Current vs. Input
Low-Side Driver
A block diagram of the low-side driver is shown in
Figure 5-2. The low-side driver is designed to drive a
ground (VSS pin) referenced N-channel MOSFET. Low
driver impedances allow the external MOSFET to be
turned on and off quickly. The rail-to-rail drive capability
of the output ensures a low RDS(ON) from the external
MOSFET.
A high level applied to LI pin causes the upper driver
FET to turn on and VDD voltage is applied to the gate of
the external MOSFET. A low level on the LI pin turns off
the upper driver and turns on the low side driver to
ground the gate of the external MOSFET.
VDD
External
FET
LO
VSS
FIGURE 5-2:
Diagram.
Low-Side Driver Block
The MIC4101 has a TTL compatible input range and is
recommended for use with inputs signals whose
amplitude is less than the supply voltage. The
threshold level is independent of the VDD supply
voltage and there is no dependence between IVDD and
the input signal amplitude with the MIC4101. This
feature makes the MIC4101 an excellent level
translator that will drive high threshold MOSFETs from
a low voltage PWM IC.
DS20006699A-page 12
2022 Microchip Technology Inc. and its subsidiaries
MIC4100/1
5.4
High-Side Driver and Bootstrap
Circuit
A block diagram of the high-side driver and bootstrap
circuit is shown in Figure 5-3. This driver is designed to
drive a floating N-channel MOSFET, whose source
terminal is referenced to the HS pin.
VDD
HB
CB
External
FET
The bootstrap circuit consists of an internal diode and
external capacitor, CB. In a typical application, such as
the synchronous buck converter shown in Figure 5-4,
the HS pin is at ground potential while the low-side
MOSFET is on. The internal diode allows capacitor CB
to charge up to VDD – VD during this time (where VD is
the forward voltage drop of the internal diode). After the
low-side MOSFET is turned off and the HO pin turns
on, the voltage across capacitor CB is applied to the
gate of the upper external MOSFET. As the upper
MOSFET turns on, voltage on the HS pin rises with the
source of the high-side MOSFET until it reaches VIN.
As the HS and HB pin rise, the internal diode is
reverse-biased, preventing capacitor CB from
discharging.
HO
VIN
CVDD
HI
VDD
HB
Q1
Level
shift
LOUT
HO
HS
VOUT
HS
FIGURE 5-3:
Diagram.
High-Side Driver Block
A low-power, high-speed, level-shifting circuit isolates
the low-side (VSS pin) referenced circuitry from the
high-side (HS pin) referenced driver. Power to the
high-side driver and UVLO circuit is supplied by the
bootstrap circuit while the voltage level of the HS pin is
shifted high.
2022 Microchip Technology Inc. and its subsidiaries
LI
Q2
COUT
LO
VSS
FIGURE 5-4:
Bootstrap Circuit.
High-Side Driver and
DS20006699A-page 13
MIC4100/1
6.0
APPLICATION INFORMATION
6.1
Power Dissipation Considerations
Power dissipation in the driver can be separated into
three areas:
• Internal diode dissipation in the bootstrap circuit
• Internal driver dissipation
• Quiescent current dissipation used to supply the
internal logic and control functions.
6.2
Bootstrap Circuit Power
Dissipation
Power dissipation of the internal bootstrap diode
primarily comes from the average charging current of
the CB capacitor times the forward voltage drop of the
diode. Secondary sources of diode power dissipation
are the reverse leakage current and reverse recovery
effects of the diode.
The average current drawn by repeated charging of the
high-side MOSFET is calculated by:
by computing the average reverse current due to
reverse recovery charge multiplied by the reverse
voltage across the diode. The average reverse current
and power dissipation due to reverse recovery can be
estimated by:
EQUATION 6-3:
I RR AVE = 0.5 I RRM t RR f S
Pdiode RR = I RR AVE V REV
Where:
IRRM =
Peak Reverse Recovery Current
tRR =
Reverse Recovery Time
The total diode power dissipation is:
EQUATION 6-4:
Pdiode total = Pdiode fwd + Pdiode RR
EQUATION 6-1:
I F AVE = Q gate f S
Where:
Qgate =
Total Gate Charge at VHB
fS
Gate Drive Switching Frequency
=
The average power dissipated by the forward voltage
drop of the diode equals:
EQUATION 6-2:
Pdiode fwd = I F AVE V F
Where:
VF =
Diode Forward Voltage Drop
The value of VF should be taken at the peak current
through the diode. However, this current is difficult to
calculate because of differences in source
impedances. The peak current can either be measured
or the value of VF at the average current can be used
and will yield a good approximation of diode power
dissipation.
The reverse leakage current of the internal bootstrap
diode is typically 11 µA at a reverse voltage of 100V
and 125°C. Power dissipation due to reverse leakage
is typically much less than 1 mW and can be ignored.
An optional external bootstrap diode may be used
instead of the internal diode (Figure 6-1). An external
diode may be useful if high gate charge MOSFETs are
being driven and the power dissipation of the internal
diode is contributing to excessive die temperatures.
The voltage drop of the external diode must be less
than the internal diode for this option to work. The
reverse voltage across the diode will be equal to the
input voltage minus the VDD supply voltage. A 100V
Schottky diode will work for most 72V input telecom
applications. The equations above can be used to
calculate power dissipation in the external diode.
However, if the external diode has significant reverse
leakage current, the power dissipated in that diode due
to reverse leakage can be calculated as:
EQUATION 6-5:
Pdiode REV = I R V REV 1 – D
Where:
IR
=
Reverse Current Flow at VREV & TJ
VREV =
Diode Reverse Voltage
D
=
Duty Cycle = tON/fS
fS
= Switching Frequency of Power Supply
Reverse recovery time is the time required for the
injected minority carriers to be swept away from the
depletion region during turn-off of the diode. Power
dissipation due to reverse recovery can be calculated
DS20006699A-page 14
2022 Microchip Technology Inc. and its subsidiaries
MIC4100/1
The on-time is the time the high-side switch is
conducting. In most power supply topologies, the diode
is reverse-biased during the switching cycle off-time.
external
diode
VIN
CB
VDD
HI
HB
Level
shift
HO
HS
LI
LO
MIC4100. RG is the series resistor (if any) between the
driver IC and the MOSFET. RG_FET is the gate
resistance of the MOSFET. RG_FET is usually listed in
the power MOSFET’s specifications. The ESR of
capacitor CB and the resistance of the connecting etch
can be ignored because they are much less than RON
and RG_FET.
The effective capacitance of CGD and CGS is difficult to
calculate because they vary non-linearly with ID, VGS,
and VDS. Fortunately, most power MOSFET
specifications include a typical graph of total gate
charge vs. VGS. Figure 6-3 shows a typical gate charge
curve for an arbitrary power MOSFET. This chart
shows that for a gate voltage of 10V, the MOSFET
requires about 23.5 nC of charge. The energy
dissipated by the resistive components of the gate
drive circuit during turn-on is calculated as:
EQUATION 6-6:
VSS
Where:
FIGURE 6-1:
6.3
Optional Bootstrap Diode.
Gate Drive Power Dissipation
Power dissipation in the output driver stage is mainly
caused by charging and discharging the gate to source
and gate to drain capacitance of the external MOSFET.
Figure 6-2 shows a simplified equivalent circuit of the
MIC4100 driving an external high-side MOSFET.
CISS =
2
1
E = --- C ISS V GS
2
Total Gate Capacitance of MOSFET
but
EQUATION 6-7:
Q = CV
so
VDD
HB
EXTERNAL
FET
CGD
RON
CB
EQUATION 6-8:
1
E = --- Q G V GS
2
HO
RG
ROFF
RG_FET
CGS
HS
FIGURE 6-2:
MIC4100 Driving an
External MOSFET.
6.3.1
DISSIPATION DURING THE
EXTERNAL MOSFET TURN-ON
Energy from capacitor CB is used to charge up the input
capacitance of the MOSFET (CGD and CGS). The
energy delivered to the MOSFET is dissipated in the
three resistive components, RON, RG, and RG_FET. RON
is the on resistance of the upper driver MOSFET in the
2022 Microchip Technology Inc. and its subsidiaries
FIGURE 6-3:
VGS.
Typical Gate Charge vs.
DS20006699A-page 15
MIC4100/1
The same energy is dissipated by ROFF, RG, and
RG_FET when the driver IC turns the MOSFET off.
Assuming RON is approximately equal to ROFF, the total
energy and power dissipated by the resistive drive
elements is:
EQUATION 6-9:
EQUATION 6-12:
Pdiss supply = V DD I DD + V HB I HB
6.5
Total Power Dissipation and
Thermal Considerations
E driver = Q G V GS
Where:
Edriver =
Energy Dissipated per Switching
Cycle
and
EQUATION 6-13:
EQUATION 6-10:
P driver = Q G V GS f S
Where:
Pdriver =
Power Dissipated by Switching the
MOSFET On and Off
QG
=
Total Gate Charge at VGS
VGS
=
Gate-to-Source Voltage on the
MOSFET
fS
=
Switching Frequency of the Gate
Drive Circuit
The power dissipated inside the MIC4100/1 equals the
ratio of RON and ROFF to the external resistive losses in
RG and RG_FET. Letting RON = ROFF, the power
dissipated in the MIC4100 due to driving the external
MOSFET is:
EQUATION 6-11:
R ON
Pdiss drive = P driver ------------------------------------------------R ON + R G + R G_FET
6.4
Total power dissipation in the MIC4100 or MIC4101
equals the power dissipation caused by driving the
external MOSFETs, the supply current, and the internal
bootstrap diode.
Supply Current Power Dissipation
Power is dissipated in the MIC4100 even if there is
nothing being driven. The supply current is drawn by
the bias for the internal circuitry, the level shifting
circuitry, and shoot-through current in the output
drivers. The supply current is proportional to operating
frequency and the VDD and VHB voltages. The typical
characteristic graphs show how supply current varies
with switching frequency and supply voltage.
The power dissipated by the MIC4100 due to supply
current is:
DS20006699A-page 16
Pdiss total = Pdiss supply + Pdiss drive + Pdiode total
The die temperature may be calculated once the total
power dissipation is known.
EQUATION 6-14:
T J = T A + Pdiss total JA
Where:
TJ
= Junction Temperature (°C)
TA
= Maximum Ambient Temperature
Pdisstotal = Power Dissipation of the MIC4100/1
θJA
6.6
= Thermal Resistance from Junction to
Ambient Air (°C/W)
Propagation Delay, and Delay
Matching and Other Timing
Considerations
Propagation delay and signal timing is an important
consideration in a high performance power supply. The
MIC4100 is designed not only to minimize propagation
delay but to minimize the mismatch in delay between
the high-side and low-side drivers.
Fast propagation delay between the input and output
drive waveform is desirable. It improves overcurrent
protection by decreasing the response time between
the control signal and the MOSFET gate drive.
Minimizing propagation delay also minimizes phase
shift errors in power supplies with wide bandwidth
control loops.
Many power supply topologies use two switching
MOSFETs operating 180° out of phase from each
other. These MOSFETs must not be on at the same
time or a short circuit will occur, causing high peak
2022 Microchip Technology Inc. and its subsidiaries
MIC4100/1
currents and higher power dissipation in the MOSFETs.
The MIC4100 and MIC4101 output gate drivers are not
designed with anti shoot through protection circuitry.
The output drives signals simply follow the inputs. The
power supply design must include timing delays (dead
time) between the input signals to prevent
shoot-through. The MIC4100 and MIC4101 drivers
specify delay matching between the two drivers to help
improve power supply performance by reducing the
amount of dead time required between the input
signals.
impedance is recommended. Refer to the Grounding,
Component Placement, and Circuit Layout section for
more information.
Care must be taken to insure the input signal pulse
width is greater than the minimum specified pulse
width. An input signal that is less than the minimum
pulse width may result in no output pulse or an output
pulse whose width is significantly less than the input.
EQUATION 6-15:
The maximum duty cycle (ratio of high side on-time to
switching period) is controlled by the minimum pulse
width of the low side and by the time required for the CB
capacitor to charge during the off-time. Adequate time
must be allowed for the CB capacitor to charge up
before the high-side driver is turned on.
6.7
Decoupling and Bootstrap
Capacitor Selection
Decoupling capacitors are required for both the
low-side (VDD) and high-side (HB) supply pins. These
capacitors supply the charge necessary to drive the
external MOSFETs as well as minimize the voltage
ripple on these pins. The capacitor from HB to HS
serves double duty by providing decoupling for the
high-side circuitry as well as providing current to the
high-side circuit while the high-side external MOSFET
is on. Ceramic capacitors are recommended because
of their low impedance and small size. Z5U type
ceramic capacitor dielectrics are not recommended
due to the large change in capacitance over
temperature and voltage. A minimum value of 0.1 µF is
required for each of the capacitors, regardless of the
MOSFETs being driven. Larger MOSFETs may require
larger capacitance values for proper operation. The
voltage rating of the capacitors depends on the supply
voltage, ambient temperature, and the voltage derating
used for reliability. 25V rated X5R or X7R ceramic
capacitors are recommended for most applications.
The minimum capacitance value should be increased if
low voltage capacitors are used because even good
quality dielectric capacitors, such as X5R, will lose 40%
to 70% of their capacitance value at the rated voltage.
Placement of the decoupling capacitors is critical. The
bypass capacitor for VDD should be placed as close as
possible between the VDD and VSS pins. The bypass
capacitor (CB) for the HB supply pin must be located as
close as possible between the HB and HS pins. The
etch connections must be short, wide, and direct. The
use of a ground plane to minimize connection
2022 Microchip Technology Inc. and its subsidiaries
The voltage on the bootstrap capacitor drops each time
it delivers charge to turn on the MOSFET. The voltage
drop depends on the gate charge required by the
MOSFET. Most MOSFET specifications specify gate
charge vs. VGS voltage. Based on this information and
a recommended ΔVHB of less than 0.1V, the minimum
value of bootstrap capacitance is calculated as:
QG
C B -------------V HB
Where:
QGATE =
Total Gate Charge at VHB
ΔVHB =
Voltage Drop at the HB Pin
The decoupling capacitor for the VDD input may be
calculated in with the same formula; however, the two
capacitors are usually equal in value.
6.8
Grounding, Component
Placement, and Circuit Layout
Nanosecond switching speeds and ampere peak
currents in and around MIC4100 and MIC4101 driver
require proper placement and trace routing of all
components. Improper placement may cause
degraded noise immunity, false switching, excessive
ringing, or circuit latch-up.
Figure 6-4 shows the critical current paths when the
driver outputs go high and turn on the external
MOSFETs. It also shows the need for a low impedance
ground plane. The charge needed to turn-on the
MOSFET gates comes from the decoupling capacitors
CVDD and CB. Current in the low-side gate driver flows
from CVDD through the internal driver, into the MOSFET
gate, and out the source. The return connection back to
the decoupling capacitor is made through the ground
plane. Any inductance or resistance in the ground
return path causes a voltage spike or ringing to appear
on the source of the MOSFET. This voltage works
against the gate voltage and can either slow down or
turn off the MOSFET during the period where it should
be turned on.
Current in the high-side driver is sourced from
capacitor CB, flows into the HB pin, and out the HO pin,
into the gate of the high-side MOSFET. The return path
for the current is from the source of the MOSFET and
back to capacitor CB. The high-side circuit return path
usually does not have a low impedance ground plane,
so the etch connections in this critical path should be
short and wide to minimize parasitic inductance. As
with the low-side circuit, impedance between the
DS20006699A-page 17
MIC4100/1
MOSFET source and the decoupling capacitor causes
negative voltage feedback that fights the turn-on of the
MOSFET.
It is important to note that capacitor CB must be placed
close to the HB and HS pins. This capacitor not only
provides all the energy for turn-on, but it must also keep
HB pin noise and ripple low for proper operation of the
high-side drive circuitry.
A typical layout of a synchronous buck converter power
stage using the MIC4100 (Figure 6-6) is shown in
Figure 6-7.
Low-side drive turn-on
current path
LO
Vdd
gnd
plane
MIC4100, the decoupling capacitors, and the
external MOSFET will degrade the performance
of the driver.
• Trace out the high di/dt and dv/dt paths, as shown
in Figure 6-4 and Figure 6-5 to minimize the etch
length and loop area for these connections.
Minimizing these parameters decreases the
parasitic inductance and the radiated EMI
generated by fast rise and fall times.
CVdd
HB
CB
Vss
HO
LI
VIN
HB
gnd
plane
CVDD
HI
High-Side Fet
Level
shift
HO
HS (switch) Node
CB
HS
HS
Level
shift
HI
Low-Side Fet
LI
High-side drive turn-on
current path
CIN
LO
MIC4100
Turn-On Current Paths
FIGURE 6-4:
Vss
Turn-On Current Paths.
Figure 6-5 shows the critical current paths when the
driver outputs go low and turn off the external
MOSFETs. Short, low impedance connections are
important during turn-off for the same reasons given in
the turn-on explanation. Current flowing through the
internal diode replenishes charge in the bootstrap
capacitor, CB.
FIGURE 6-6:
Stage.
Typical Converter Power
VIN (FET Drain)
High-side FET
Low-side FET
HS Node
(switching node)
CIN
Low-side drive turn-off
current path
GND
(FET Source)
LO
Vdd
Cvdd
CVdd
LO
Vss
LI
HI
HB
Vss
CB
LI
CB
HO
HS
Level
shift
HI
MIC4100/1
HO
HB
Vdd
HS
High-side drive turn-on
current path
Turn-Off Current Paths
FIGURE 6-5:
Turn-Off Current Paths.
GND
The following circuit guidelines should be adhered to
for optimum circuit performance:
• The VDD and HB bypass capacitors must be
placed close to the supply and ground pins. It is
critical that the etch length between the high side
decoupling capacitor (CB) and the HB and HS
pins be minimized to reduce lead inductance.
• A ground plane should be used to minimize
parasitic inductance and impedance of the return
paths. The MIC4100 is capable of greater than 2A
peak currents. Any impedance between the
DS20006699A-page 18
HO trace
FIGURE 6-7:
Typical Layout of a
Synchronous Buck Converter Power Stage.
2022 Microchip Technology Inc. and its subsidiaries
MIC4100/1
The circuit is configured as a synchronous buck power
stage. The high-side MOSFET drain connects to the
input supply voltage (drain) and the source connects to
the switching node. The low-side MOSFET drain
connects to the switching node and its source is
connected to ground. The buck converter output
inductor (not shown) would connect to the switching
node. The high-side drive trace, HO, is routed on top
of its return trace, HS, to minimize loop area and
parasitic inductance. The low-side drive trace, LO, is
routed over the ground plane and minimizes the
impedance of that current path. The decoupling
capacitors, CB and CVDD, are placed to minimize etch
length between the capacitors and their respective
pins. This close placement is necessary to efficiently
charge capacitor CB when the HS node is low. All
traces are 0.025” wide or greater to reduce impedance.
CIN is used to decouple the high current path through
the MOSFETs.
2022 Microchip Technology Inc. and its subsidiaries
DS20006699A-page 19
MIC4100/1
7.0
PACKAGING INFORMATION
7.1
Package Marking Information
8-Lead SOIC*
XXX
XXXXXX
WNNN
Legend: XX...X
Y
YY
WW
NNN
e3
*
Example
MIC
4100YM
4AG7
Product code or customer-specific information
Year code (last digit of calendar year)
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code
Pb-free JEDEC® designator for Matte Tin (Sn)
This package is Pb-free. The Pb-free JEDEC designator ( e3 )
can be found on the outer packaging for this package.
●, ▲, ▼ Pin one index is identified by a dot, delta up, or delta down (triangle
mark).
Note:
In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information. Package may or may not include
the corporate logo.
Underbar (_) symbol may not be to scale.
Note:
If the full seven-character YYWWNNN code cannot fit on the package, the following truncated codes are
used based on the available marking space:
6 Characters = YWWNNN; 5 Characters = WWNNN; 4 Characters = WNNN; 3 Characters = NNN;
2 Characters = NN; 1 Character = N
DS20006699A-page 20
2022 Microchip Technology Inc. and its subsidiaries
MIC4100/1
8-Lead Plastic Small Outline (3BX) - Narrow, 3.90 mm (.150 In.) Body [SOIC]
Atmel Legacy Global Package Code SWB
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2X
0.10 C A–B
D
A
D
NOTE 5
N
E
2
E1
2
E1
E
2X
0.10 C A–B
2X
0.10 C A–B
NOTE 1
2
1
e
NX b
0.25
B
C A–B D
NOTE 5
TOP VIEW
0.10 C
C
A A2
SEATING
PLANE
8X
A1
SIDE VIEW
0.10 C
4X ș1
ș2
h
R1
h
R
H
L
SEE VIEW C
VIEW A–A
c
ș
(L1)
4X ș1
VIEW C
Microchip Technology Drawing No. C04-057-3BX Rev J Sheet 1 of 2
2022 Microchip Technology Inc. and its subsidiaries
DS20006699A-page 21
MIC4100/1
8-Lead Plastic Small Outline (3BX) - Narrow, 3.90 mm (.150 In.) Body [SOIC]
Atmel Legacy Global Package Code SWB
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Units
Dimension Limits
Number of Pins
N
e
Pitch
Overall Height
A
Molded Package Thickness
A2
§
Standoff
A1
Overall Width
E
Molded Package Width
E1
Overall Length
D
Chamfer (Optional)
h
Foot Length
L
Footprint
L1
c
Lead Thickness
b
Lead Width
Lead Bend Radius
R
Lead Bend Radius
R1
Foot Angle
ș
Mold Draft Angle
ș1
Lead Angle
ș2
MIN
–
1.25
0.10
0.25
0.40
0.17
0.31
0.07
0.07
0°
5°
0°
MILLIMETERS
NOM
8
1.27 BSC
–
–
–
6.00 BSC
3.90 BSC
4.90 BSC
–
–
1.04 REF
–
–
–
–
–
–
–
MAX
1.75
0.25
0.50
1.27
0.25
0.51
–
–
8°
15°
8°
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. § Significant Characteristic
3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or
protrusions shall not exceed 0.15mm per side.
4. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
5. Datums A & B to be determined at Datum H.
Microchip Technology Drawing No. C04-057-3BX Rev J Sheet 2 of 2
DS20006699A-page 22
2022 Microchip Technology Inc. and its subsidiaries
MIC4100/1
8-Lead Plastic Small Outline (3BX) - Narrow, 3.90 mm (.150 In.) Body [SOIC]
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
SILK SCREEN
C
Y1
X1
E
RECOMMENDED LAND PATTERN
Units
Dimension Limits
Contact Pitch
E
Contact Pad Spacing
C
Contact Pad Width (X8)
X1
Contact Pad Length (X8)
Y1
MIN
MILLIMETERS
NOM
1.27 BSC
5.40
MAX
0.60
1.55
Notes:
1. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
Microchip Technology Drawing C04-2057-3BX Rev J
2022 Microchip Technology Inc. and its subsidiaries
DS20006699A-page 23
MIC4100/1
NOTES:
DS20006699A-page 24
2022 Microchip Technology Inc. and its subsidiaries
MIC4100/1
APPENDIX A:
REVISION HISTORY
Revision A (July 2022)
• Converted Micrel document MIC4100/1 to Microchip data sheet DS20006699A.
• Minor text changes throughout.
2022 Microchip Technology Inc. and its subsidiaries
DS20006699A-page 25
MIC4100/1
NOTES:
DS20006699A-page 26
2022 Microchip Technology Inc. and its subsidiaries
MIC4100/1
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, contact your local Microchip representative or sales office.
PART NO.
X
X
-XX
Device
Junction
Temperature Range
Package
Media Type
Device:
MIC4100:
MIC4101:
100V Half-Bridge MOSFET Driver
2A Source/Sink Current, CMOS Input
100V Half-Bridge MOSFET Driver
2A Source/Sink Current, TTL Input
Temperature:
Y
=
–40°C to +125°C (RoHS Compliant)
Package:
M
=
8-Lead SOIC
Media Type:
(blank) = 95/Tube
TR
= 2,500/Reel
Examples:
a) MIC4100YM:
100V Half-Bridge MOSFET Driver
2A Source/Sink Current, CMOS
Input, –40°C to +125°C Junction
Temperature Range, 8-Lead SOIC,
95/Tube
b) MIC4100YM-TR:
100V Half-Bridge MOSFET Driver
2A Source/Sink Current, CMOS
Input, –40°C to +125°C Junction
Temperature Range, 8-Lead SOIC,
2,500/Reel
c) MIC4101YM:
100V Half-Bridge MOSFET Driver
2A Source/Sink Current, TTL Input,
–40°C to +125°C Junction
Temperature Range, 8-Lead SOIC,
95/Tube
b) MIC4101YM-TR:
100V Half-Bridge MOSFET Driver
2A Source/Sink Current, TTL Input,
–40°C to +125°C Junction
Temperature Range, 8-Lead SOIC,
2,500/Reel
Note 1:
2022 Microchip Technology Inc. and its subsidiaries
Tape and Reel identifier only appears in the catalog
part number description. This identifier is used for
ordering purposes and is not printed on the device
package. Check with your Microchip Sales Office
for package availability with the Tape and Reel
option.
DS20006699A-page 27
MIC4100/1
NOTES:
DS20006699A-page 28
2022 Microchip Technology Inc. and its subsidiaries
Note the following details of the code protection feature on Microchip products:
•
Microchip products meet the specifications contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is secure when used in the intended manner, within operating specifications, and
under normal conditions.
•
Microchip values and aggressively protects its intellectual property rights. Attempts to breach the code protection features of
Microchip product is strictly prohibited and may violate the Digital Millennium Copyright Act.
•
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of its code. Code protection does not
mean that we are guaranteeing the product is "unbreakable" Code protection is constantly evolving. Microchip is committed to
continuously improving the code protection features of our products.
This publication and the information herein may be used only
with Microchip products, including to design, test, and integrate
Microchip products with your application. Use of this information in any other manner violates these terms. Information
regarding device applications is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your
specifications. Contact your local Microchip sales office for
additional support or, obtain additional support at https://
www.microchip.com/en-us/support/design-help/client-supportservices.
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© 2022, Microchip Technology Incorporated and its subsidiaries.
All Rights Reserved.
ISBN: 978-1-6683-0981-0
For information regarding Microchip’s Quality Management Systems,
please visit www.microchip.com/quality.
2022 Microchip Technology Inc. and its subsidiaries
DS20006699A-page 29
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Tel: 281-894-5983
Indianapolis
Noblesville, IN
Tel: 317-773-8323
Fax: 317-773-5453
Tel: 317-536-2380
Los Angeles
Mission Viejo, CA
Tel: 949-462-9523
Fax: 949-462-9608
Tel: 951-273-7800
Raleigh, NC
Tel: 919-844-7510
New York, NY
Tel: 631-435-6000
San Jose, CA
Tel: 408-735-9110
Tel: 408-436-4270
Canada - Toronto
Tel: 905-695-1980
Fax: 905-695-2078
DS20006699A-page 30
China - Xiamen
Tel: 86-592-2388138
China - Zhuhai
Tel: 86-756-3210040
Denmark - Copenhagen
Tel: 45-4485-5910
Fax: 45-4485-2829
Finland - Espoo
Tel: 358-9-4520-820
France - Paris
Tel: 33-1-69-53-63-20
Fax: 33-1-69-30-90-79
Germany - Garching
Tel: 49-8931-9700
Germany - Haan
Tel: 49-2129-3766400
Germany - Heilbronn
Tel: 49-7131-72400
Germany - Karlsruhe
Tel: 49-721-625370
Germany - Munich
Tel: 49-89-627-144-0
Fax: 49-89-627-144-44
Germany - Rosenheim
Tel: 49-8031-354-560
Israel - Ra’anana
Tel: 972-9-744-7705
Italy - Milan
Tel: 39-0331-742611
Fax: 39-0331-466781
Italy - Padova
Tel: 39-049-7625286
Netherlands - Drunen
Tel: 31-416-690399
Fax: 31-416-690340
Norway - Trondheim
Tel: 47-7288-4388
Poland - Warsaw
Tel: 48-22-3325737
Romania - Bucharest
Tel: 40-21-407-87-50
Spain - Madrid
Tel: 34-91-708-08-90
Fax: 34-91-708-08-91
Sweden - Gothenberg
Tel: 46-31-704-60-40
Sweden - Stockholm
Tel: 46-8-5090-4654
UK - Wokingham
Tel: 44-118-921-5800
Fax: 44-118-921-5820
2022 Microchip Technology Inc. and its subsidiaries
09/14/21
