MIC4102
100V Half-Bridge MOSFET Driver
with Anti-Shoot-Through Protection
Features
General Description
• Drives High- and Low-Side N-Channel MOSFETs
with Single Input
• Adaptive Anti-Shoot-Through Protection
• Low-Side Drive Disable Pin
• Bootstrap Supply Voltage to 118V DC
• Supply Voltage up to 16V
• TTL Input Thresholds
• On-Chip Bootstrap Diode
• Fast 30 ns Propagation Times
• Drives 1000 pF Load with 10 ns Rise and Fall
Times
• Low Power Consumption
• Supply Undervoltage Protection
• 2.5Ω Pull-Up, 1.5Ω Pull-Down Output Resistance
• Space Saving SOIC-8L Package
• –40°C to +125°C Junction Temperature Range
The MIC4102 is a high frequency, 100V half-bridge
MOSFET driver IC featuring internal anti-shoot-through
protection. The low-side and high-side gate drivers are
controlled by a single input signal to the PWM pin. The
MIC4102 implements adaptive anti-shoot-through
circuitry to optimize the switching transitions for
maximum efficiency. The single input control also
reduces system complexity and greatly simplifies the
overall design.
The MIC4102 also features a low-side drive disable
pin. This gives the MIC4102 the capability to operate in
a non-synchronous buck mode. This feature allows the
MIC4102 to start up into applications where a bias
voltage may already be present without pulling the
output voltage down.
Undervoltage protection on both the low-side and
high-side supplies forces the outputs low. An on-chip
bootstrap diode eliminates the discrete diode required
with other driver ICs.
Applications
•
•
•
•
•
•
The MIC4102 is available in the SOIC-8L package with
a junction operating range from –40°C to +125°C.
High Voltage Buck Converters
Networking/Telecom Power Supplies
Automotive Power Supplies
Current-Fed Push-Pull Power Topologies
Ultrasonic Drivers
Avionic Power Supplies
Typical Application Schematic
MIC4102
SOIC-8L
9V TO 16V BIAS
100V SUPPLY
VDD
HB
MIC4102
PWM
CONTROLLER
HI
HO
LS
HS
VOUT
GND
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LO
DS20005575B-page 1
MIC4102
Functional Block Diagram
MIC4102
HV
HB
2
UVLO
PWM
5
VDD
1
LEVEL
SHIFT
DRIVER
HO
3
HS
4
LEVEL
SHIFT
UVLO
DRIVER
LO
8
LS
6
VSS
7
DS20005575B-page 2
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MIC4102
1.0
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings †
Supply Voltage (VDD, VHB – VHS) .............................................................................................................. –0.3V to +18V
Input Voltages (VPWM, VLS)...............................................................................................................–0.3V to VDD + 0.3V
Voltage on LO (VLO)..........................................................................................................................–0.3V to VDD + 0.3V
Voltage on HO (VHO).................................................................................................................VHS – 0.3V to VHB + 0.3V
Voltage on HS (Continuous) ........................................................................................................................–1V to +110V
Voltage on HB ......................................................................................................................................................... +118V
Average Current in VDD to HB Diode ....................................................................................................................100 mA
ESD Rating .............................................................................................................................................................Note 1
Operating Ratings ‡
Supply Voltage (VDD) .................................................................................................................................... +9V to +16V
Voltage on HS ............................................................................................................................................. –1V to +100V
Voltage on HS (Repetitive Transient) .......................................................................................................... –5V to +105V
HS Slew Rate........................................................................................................................................................ 50 V/ns
Voltage on HB .............................................................................................................................. VHS + 8V to VHS + 16V
and ............................................................................................................................................. VDD – 1V to VDD + 100V
† Notice: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device.
This is a stress rating only and functional operation of the device at those or any other conditions above those indicated
in the operational sections of this specification is not intended. Exposure to maximum rating conditions for extended
periods may affect device reliability.
‡ Notice: The device is not guaranteed to function outside its operating ratings.
Note 1: Devices are ESD sensitive. Handling precautions are recommended. Human body model, 1.5 kΩ in series
with 100 pF.
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DS20005575B-page 3
MIC4102
ELECTRICAL CHARACTERISTICS
Electrical Characteristics: VDD = VHB = 12V; VSS = VHS = 0V; No load on LO or HO; TA = +25°C; unless noted.
Bold values are valid for –40°C ≤ TJ ≤ +125°C. (Note 1).
Parameters
Sym.
Min.
Typ.
Max.
—
150
450
—
—
600
—
3
3.5
—
—
4.0
—
25
150
—
—
200
—
1.5
2.5
—
—
3
—
0.05
1
—
—
30
Units
Conditions
µA
PWM = 0V
mA
f = 500 kHz
µA
PWM = 0V
mA
f = 500 kHz
µA
VHS = VHB = 110V
Supply Current
VDD Quiescent Current
IDD
VDD Operating Current
IDDO
Total HB Quiescent Current
IHB
Total HB Operating Current
IHBO
HB to VSS Quiescent Current
IHBS
Input Pins (TTL)
Low Level Input Voltage Threshold
VIL
0.8
1.5
—
V
—
High Level Input Voltage Threshold
VIH
—
1.5
2.2
V
—
Input Pull-Down Resistance
RI
100
200
500
kΩ
—
VDD Rising Threshold
VDDR
6.5
7.3
8.0
V
—
VDD Threshold Hysteresis
VDDH
—
0.5
—
V
—
HB Rising Threshold
VHBR
6.0
7.0
8.0
V
—
HB Threshold Hysteresis
VHBH
—
0.4
—
V
—
—
0.4
0.55
—
—
0.70
V
IVDD-HB = 100 µA
—
0.7
0.8
—
—
1.0
V
IVDD-HB = 100 mA
—
1.0
1.5
—
—
2.0
Ω
IVDD-HB = 100 mA
—
0.18
0.3
—
—
0.4
V
ILO = 160 mA
—
0.25
0.3
—
—
0.45
V
ILO = –100 mA,
VOHL = VDD – VLO
Undervoltage Protection
Bootstrap Diode
Low-Current Forward Voltage
VDL
High-Current Forward Voltage
VDH
Dynamic Resistance
RD
LO Gate Driver
Low Level Output Voltage
VOLL
High Level Output Voltage
VOHL
Peak Sink Current
IOHL
—
3
—
A
VLO = 0V
Peak Source Current
IOLL
—
2
—
A
VLO = 12V
Note 1:
2:
3:
Specification for packaged product only.
All voltages relative to Pin 7, VSS, unless otherwise specified.
Guaranteed by design. Not production tested.
DS20005575B-page 4
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MIC4102
ELECTRICAL CHARACTERISTICS (CONTINUED)
Electrical Characteristics: VDD = VHB = 12V; VSS = VHS = 0V; No load on LO or HO; TA = +25°C; unless noted.
Bold values are valid for –40°C ≤ TJ ≤ +125°C. (Note 1).
Parameters
Sym.
Min.
Typ.
Max.
—
0.22
0.3
—
—
0.4
—
0.25
0.3
—
—
0.45
Units
Conditions
V
IHO = 160 mA
V
IHO = –100 mA,
VOHH = VHB – VHO
HO Gate Driver
Low Level Output Voltage
VOLH
High Level Output Voltage
VOHH
Peak Sink Current
IOHH
—
3
—
A
VHO = 0V
Peak Source Current
IOLH
—
2
—
A
VHO = 12V
—
30
45
—
—
60
ns
—
—
1.7
—
V
—
—
30
50
—
—
60
ns
—
—
45
65
—
—
70
ns
—
1
2.5
4
V
—
—
30
60
—
—
70
ns
—
—
36
45
—
—
70
ns
CL = 1000 pF
120
250
450
ns
—
Switching Specifications (Anti-Shoot-Through Circuitry)
Delay between PWM going high to
LO going low
tLOOFF
Voltage threshold for LO MOSFET
to be considered OFF
VLOOFF
Delay between LO OFF to HO
going High
tHOON
Delay between PWM going Low to
HO going low
tHOOFF
Switch Node Voltage Threshold
when HO turns off
VSWth
Delay between HO MOSFET being
considered off to LO turning ON
tLOON
Delay between LS going low and
LO turning OFF
tLSOFF
Forced LO ON, if VLOTH is not
detected
tSWTO
Switching Specifications
Either Output Rise Time (3V to 9V)
tR
—
10
—
ns
CL = 1000 pF
Either Output Fall Time (3V to 9V)
tF
—
6
—
ns
CL = 1000 pF
Either Output Rise Time (3V to 9V)
tR
—
0.33
0.6
—
—
0.8
µs
CL = 0.1 µF
Either Output Fall Time (3V to 9V)
tF
—
0.2
0.3
—
—
0.4
µs
CL = 0.1 µF
Minimum Input Pulse Width that
changes the output with LS = 5V
tPW
—
40
60
ns
CL = 0, Note 3
Minimum Output Pulse Width on
HO with min pulse width on PWM
with LS = 5V
tPW
—
15
—
ns
CL = 0, Note 3
Note 1:
2:
3:
Specification for packaged product only.
All voltages relative to Pin 7, VSS, unless otherwise specified.
Guaranteed by design. Not production tested.
2016 - 2022 - 2021 Microchip Technology Inc. and its subsidiaries.
DS20005575B-page 5
MIC4102
ELECTRICAL CHARACTERISTICS (CONTINUED)
Electrical Characteristics: VDD = VHB = 12V; VSS = VHS = 0V; No load on LO or HO; TA = +25°C; unless noted.
Bold values are valid for –40°C ≤ TJ ≤ +125°C. (Note 1).
Parameters
Sym.
Min.
Typ.
Max.
Units
Conditions
Minimum Input Pulse Width that
changes the output with LS = 0V
tPW
—
13
20
ns
CL = 0, Note 3
Minimum Output Pulse Width on
HO with min pulse width on PWM
with LS = 0V
—
—
20
—
—
CL = 0, Note 3
Bootstrap Diode Turn-On or
Turn-Off Time
tBS
—
10
—
ns
—
Note 1:
2:
3:
Specification for packaged product only.
All voltages relative to Pin 7, VSS, unless otherwise specified.
Guaranteed by design. Not production tested.
DS20005575B-page 6
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MIC4102
TEMPERATURE SPECIFICATIONS
Parameters
Sym.
Min.
Typ.
Max.
Units
Conditions
Max. Junction Temperature Range
TJ
–55
—
+150
°C
Note 1
Storage Temperature Range
TS
–60
—
+150
°C
—
Operating Junction Temperature
Range
TJ
–40
—
+125
°C
—
JA
—
140
—
°C/W
—
Temperature Ranges
Package Thermal Resistances
Thermal Resistance, SOIC-8L
Note 1:
The maximum allowable power dissipation is a function of ambient temperature, the maximum allowable
junction temperature and the thermal resistance from junction to air (i.e., TA, TJ, JA). Exceeding the
maximum allowable power dissipation will cause the device operating junction temperature to exceed the
maximum +125°C rating. Sustained junction temperatures above +125°C can impact the device reliability.
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DS20005575B-page 7
MIC4102
2.0
Note:
TYPICAL PERFORMANCE CURVES
The graphs and tables provided following this note are a statistical summary based on a limited number of
samples and are provided for informational purposes only. The performance characteristics listed herein
are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified
operating range (e.g., outside specified power supply range) and therefore outside the warranted range.
FIGURE 2-1:
Supply Voltage.
Quiescent Current vs.
FIGURE 2-4:
Supply Current vs. Supply
Voltage vs. LS Level.
FIGURE 2-2:
Temperature.
Quiescent Current vs.
FIGURE 2-5:
Temperature.
Operating Current vs.
FIGURE 2-3:
Supply Voltage.
Operating Current vs.
FIGURE 2-6:
Frequency.
Supply Current vs.
DS20005575B-page 8
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MIC4102
FIGURE 2-7:
Supply Current vs.
Frequency for Pin L and H.
FIGURE 2-10:
Low Level Output of
Low-Side Driver vs. Temperature.
FIGURE 2-8:
vs. Temperature.
FIGURE 2-11:
Temperature.
UVLO Thresholds vs.
FIGURE 2-12:
Temperature.
UVLO Hysteresis vs.
High Level Output Voltage
FIGURE 2-9:
Low Level Output of
Low-Side Driver vs. Temperature.
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DS20005575B-page 9
MIC4102
FIGURE 2-13:
Characteristics.
Bootstrap Diode I-V
FIGURE 2-14:
Current.
Bootstrap Diode Reverse
DS20005575B-page 10
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MIC4102
3.0
PIN DESCRIPTIONS
The descriptions of the pins are listed in Table 3-1.
Package Type
MIC4102
SOIC-8L (M)
(Top View)
VDD 1
TABLE 3-1:
8 LO
HB 2
7 VSS
HO 3
6 LS
HS 4
5 PWM
PIN FUNCTION TABLE
Pin Number
Pin Name
Description
1
VDD
Positive supply to lower gate drivers. Decouple this pin to VSS (Pin 7). Bootstrap diode
connected to HB (Pin 2).
2
HB
High-Side Bootstrap supply. External bootstrap capacitor is required. Connect positive
side of bootstrap capacitor to this pin. Bootstrap diode is on-chip.
3
HO
High-Side Output. Connect to gate of high-side power MOSFET.
4
HS
High-Side Source connection. Connect to source of high-side power MOSFET.
Connect negative side of bootstrap capacitor to this pin.
5
PWM
Control Input. PWM high signal makes high-side HO output high and low-side LO
output low. PWM low signal makes high-side HO output low and low-side LO output
high.
6
LS
Low-Side Disable. When pulled low, this control signal immediately terminates the
low-side LO output drive. The low-side LO output drive will remain low until this signal
is removed. HS drive is not affected by the LS signal. The logic table is below (see
Table 3-2).
7
VSS
Chip negative supply. Generally, this will be grounded.
8
LO
Low-Side Output. Connect to gate of low-side power MOSFET.
TABLE 3-2:
LS PIN LOGIC TABLE
LS
PWM
LO
HO
0
0
0
0
0
1
0
1
1
0
1
0
1
1
0
1
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DS20005575B-page 11
MIC4102
4.0
TIMING DIAGRAM
tHOOFF
45ns
70ns
tHOON
30ns
60ns
HO
6
4
2
LO
tLOON
30ns
70ns
8
3 VLOOFF < 1.7V
Switch node
(HS Pin)
PWM
10
7 VSWth < (VDD – 2.5V)
5
1
tLOOFF
30ns
60ns
tLSOFF
36ns
70ns
9
LS
FIGURE 4-1:
TABLE 4-1:
Time Point
MIC4102 Timing Diagram.
TIME POINTS AND ACTIONS FOR Figure 4-1
Action
1-2
PWM signal goes high. This initiates the LO signal to go low. The delay between PWM high to
(VLO – 10%) is typically 30 ns (tLOOFF).
2-4
LO goes low. When LO reaches 1.7V (VLOOFF) the low-side MOSFET is deemed to be off. The
high-side output HO then goes high. The delay between 3 and 4 is typically 30 ns (THOON); this
allows for large turn off delay times of MOSFETs.
5-7
PWM goes low; HO goes low, typically within 45 ns, tHOOFF. The switch node (HS pin) is then
monitored; when the switch node is VDD – 2.5V (VSWTH) the high-side MOSFET is deemed to be
off and the LO output goes high within typically 30 ns (tLOON). This is controlled by a one shot
and remains high until PWM goes high. This is because it is possible to have the SW node
oscillate, and could easily bounce through 10V level. If the LO high transition has not happened
within 250 ns, it is forced to happen, unless the LS input is low.
8-10
If at any time after 7 has occurred and LS pin goes low, the LO output will turn off within 36 ns
(VLSOFF). HO will remain off. The LS pin overrides all shoot-through control logic. If LS is low at
the start of the next cycle when PWM signal goes high then HO shall switch transition 1-4 as
normal. (i.e. PWM signal equals HO output, LO = 0V).
DS20005575B-page 12
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MIC4102
5.0
FUNCTIONAL DESCRIPTION
VDD
The MIC4102 is a high voltage, non-inverting,
synchronous MOSFET driver that uses a single PWM
input signal to alternately drive both high-side and
low-side N-Channel MOSFETs. The Functional Block
Diagram of the MIC4102 is shown on page two.
The MIC4102 input is TTL-compatible. The high-side
output buffer includes a high speed level-shifting circuit
that is referenced to the HS pin. An internal diode is
used as part of a bootstrap circuit to provide the drive
voltage for the high-side output.
5.1
The VDD pin voltage is supplied to the HS pin through
the internal bootstrap diode. The HB pin voltage will
always be a diode drop less than VDD.
EXTERNAL
FET
LS
VSS
FIGURE 5-1:
Diagram.
5.4
Low-Side Driver Block
High-Side Driver and Bootstrap
Circuit
A block diagram of the high-side driver and bootstrap
circuit is shown in Figure 5-2. This driver is designed to
drive a floating N-channel MOSFET, whose source
terminal is referenced to the HS pin.
Input Stage
The MIC4102 utilizes a TTL-compatible input stage.
The PWM input pin is referenced to the VSS pin. The
voltage state of the input signal does not change the
quiescent current draw of the driver. The threshold
level is independent of the VDD supply voltage and
there is no dependence between IVDD and the input
signal amplitude. This feature makes the MIC4102 an
excellent level translator that will drive high threshold
MOSFETs from a low voltage PWM IC.
5.3
LO
Startup and UVLO
The UVLO circuit forces both driver outputs low until
the supply voltage exceeds the UVLO threshold. The
low-side UVLO circuit monitors the voltage between
the VDD and VSS pins. The high-side UVLO circuit
monitors the voltage between the HB and HS pins.
Hysteresis in the UVLO circuit prevents noise and finite
circuit impedance from causing chatter during turn-on.
5.2
DRIVE
SIGNAL
VDD
A low level applied to PWM pin will cause the HO
output to go low and the LO output to go high. The
upper driver FET turns on and VDD is applied to the
gate of the external MOSFET. A high level on the PWM
pin forces the LO output low by turning off the upper
driver and turning on the lower driver which ground the
gate of the external MOSFET.
Pulling the LS pin low disables the LO pin.
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EXTERNAL
FET
CB
HO
Low-Side Driver
A block diagram of the low-side driver is shown in
Figure 5-1. The low-side driver is designed to drive a
ground (VSS pin) referenced N-channel MOSFET. Low
driver impedances allow the external MOSFET to be
turned on and off quickly. The rail-to-rail drive capability
of the output ensures a low RDS(ON) from the external
MOSFET.
HB
HS
FIGURE 5-2:
Diagram.
High-Side Driver Block
A low-power, high-speed, level-shifting circuit isolates
the low-side (VSS pin) referenced circuitry from the
high-side (HS pin) referenced driver. Power to the
high-side driver and UVLO circuit is supplied by the
bootstrap circuit while the voltage level of the HS pin is
shifted high.
The bootstrap circuit consists of an internal diode and
external capacitor, CB. In a typical application, such as
the synchronous buck converter shown in Figure 5-3,
the HS pin is at ground potential while the low-side
MOSFET is on. The internal diode allows capacitor CB
to charge up to VDD – VD during this time (where VD is
the forward voltage drop of the internal diode). After the
low-side MOSFET is turned off and the HO pin turns
on, the voltage across capacitor CB is applied to the
DS20005575B-page 13
MIC4102
gate of the upper external MOSFET. As the upper
MOSFET turns on, voltage on the HS pin rises with the
source of the high-side MOSFET until it reaches VIN.
As the HS and HB pin rise, the internal diode is
reverse-biased, preventing capacitor CB from
discharging.
VDD
CB
VDD
VIN
HB
Q1
CVDD
LOUT
HO
LEVEL
SHIFT
VOUT
PWM
HS
Q
FF_
Q
Q2
COUT
LO
VSS
FIGURE 5-3:
Bootstrap Circuit.
DS20005575B-page 14
High-Side Driver and
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MIC4102
6.0
APPLICATION INFORMATION
6.1
Power Dissipation Considerations
Power dissipation in the driver can be separated into
three areas:
• Internal diode dissipation in the bootstrap circuit
• Internal driver dissipation
• Quiescent current dissipation used to supply the
internal logic and control functions.
6.2
Bootstrap Circuit Power
Dissipation
Power dissipation of the internal bootstrap diode
primarily comes from the average charging current of
the CB capacitor times the forward voltage drop of the
diode. Secondary sources of diode power dissipation
are the reverse leakage current and reverse recovery
effects of the diode.
by computing the average reverse current due to
reverse recovery charge multiplied by the reverse
voltage across the diode. The average reverse current
and power dissipation due to reverse recovery can be
estimated by:
EQUATION 6-3:
I RR AVE = 2 I RRM t rr f S
Where:
IRRM
Peak Reverse Recovery Current
Reverse Recovery Time
trr
EQUATION 6-4:
Pdiode RR = I RR AVE V REV
The average current drawn by repeated charging of the
high-side MOSFET is calculated by:
The total diode power dissipation is:
EQUATION 6-1:
EQUATION 6-5:
I F AVE = Q gate f S
Where:
Qgate
fS
Total Gate Charge at VHB
Gate Drive Switching Frequency
The average power dissipated by the forward voltage
drop of the diode equals:
EQUATION 6-2:
Pdiode fwd = I F AVE V F
Where:
VF
Diode Forward Voltage Drop
The value of VF should be taken at the peak current
through the diode. However, this current is difficult to
calculate because of differences in source
impedances. The peak current can either be measured
or the value of VF at the average current can be used
and will yield a good approximation of diode power
dissipation.
The reverse leakage current of the internal bootstrap
diode is typically 11 µA at a reverse voltage of 100V
and 125°C. Power dissipation due to reverse leakage
is typically much less than 1 mW and can be ignored.
Reverse recovery time is the time required for the
injected minority carriers to be swept away from the
depletion region during turn-off of the diode. Power
dissipation due to reverse recovery can be calculated
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Pdiode total = Pdiode fwd + Pdiode RR
An optional external bootstrap diode may be used
instead of the internal diode (Figure 6-1). An external
diode may be useful if high gate charge MOSFETs are
being driven and the power dissipation of the internal
diode is contributing to excessive die temperatures.
The voltage drop of the external diode must be less
than the internal diode for this option to work. The
reverse voltage across the diode will be equal to the
input voltage minus the VDD supply voltage. A 100V
Schottky diode will work for most 72V input telecom
applications. The equations above can be used to
calculate power dissipation in the external diode.
However, if the external diode has significant reverse
leakage current, the power dissipated in that diode due
to reverse leakage can be calculated as:
EQUATION 6-6:
Pdiode REV = I R V REV 1 – D
Where:
IR
VREV
Reverse Current Flow at VREV & TJ
Diode Reverse Voltage
D
Duty Cycle = tON/fS
fS
Switching Freq. of Power Supply
DS20005575B-page 15
MIC4102
The on-time is the time the high-side switch is
conducting. In most power supply topologies, the diode
is reverse-biased during the switching cycle off-time.
EXTERNAL
DIODE
CB
HO
LEVEL
SHIFT
PWM
VIN
HB
VDD
HS
Q
FF
_
Q
LO
MIC4102. RG is the series resistor (if any) between the
driver IC and the MOSFET. RG_FET is the gate
resistance of the MOSFET. RG_FET is usually listed in
the power MOSFET’s specifications. The ESR of
capacitor CB and the resistance of the connecting etch
can be ignored because they are much less than RON
and RG_FET.
The effective capacitance of CGD and CGS is difficult to
calculate because they vary non-linearly with ID, VGS,
and VDS. Fortunately, most power MOSFET
specifications include a typical graph of total gate
charge vs. VGS. Figure 6-3 shows a typical gate charge
curve for an arbitrary power MOSFET. This chart
shows that for a gate voltage of 10V, the MOSFET
requires about 23.5 nC of charge. The energy
dissipated by the resistive components of the gate
drive circuit during turn-on is calculated as:
EQUATION 6-7:
VSS
Where:
FIGURE 6-1:
6.3
Optional Bootstrap Diode.
Gate Drive Power Dissipation
Power dissipation in the output driver stage is mainly
caused by charging and discharging the gate to source
and gate to drain capacitance of the external MOSFET.
Figure 6-2 shows a simplified equivalent circuit of the
MIC4102 driving an external high-side MOSFET.
CISS
2
1
E = --- C ISS V GS
2
Total Gate Capacitance of MOSFET
but
EQUATION 6-8:
Q = CV
so
VDD
HB
EXTERNAL
FET
CGD
RON
CB
EQUATION 6-9:
1
E = --- Q G V GS
2
HO
RG
ROFF
RG_FET
CGS
HS
FIGURE 6-2:
MIC4102 Driving an
External MOSFET.
6.4
Dissipation During the External
MOSFET Turn-On
Energy from capacitor CB is used to charge up the input
capacitance of the MOSFET (CGD and CGS). The
energy delivered to the MOSFET is dissipated in the
three resistive components, RON, RG, and RG_FET. RON
is the on resistance of the upper driver MOSFET in the
DS20005575B-page 16
FIGURE 6-3:
VGS.
Typical Gate Charge vs.
2016 - 2022 - 2021 Microchip Technology Inc. and its subsidiar-
MIC4102
The same energy is dissipated by ROFF, RG, and
RG_FET when the driver IC turns the MOSFET off.
EQUATION 6-13:
Pdiss supply = V DD I DD + V HB I HB
EQUATION 6-10:
1
E driver = --- Q G V GS
2
Where:
Edriver
Energy Dissipated during Turn-On
or Turn-Off
and
EQUATION 6-11:
P driver
1
= --- Q G V GS f S
2
Where:
Total power dissipation in the MIC4102 equals the
power dissipation caused by driving the external
MOSFETs, the supply current, and the internal
bootstrap diode.
EQUATION 6-14:
Power Dissipated during Turn-On
or Turn-Off
QG
Total Gate Charge at VGS
VGS
Gate-to-Source Voltage on the
MOSFET
Switching Frequency of the Gate
Drive Circuit
The power dissipated inside the MIC4102 equals the
ratio of RON and ROFF to the external resistive losses in
RG and RG_FET. The power dissipated in the MIC4102
due to driving the external MOSFET is:
EQUATION 6-12:
The die temperature may be calculated once the total
power dissipation is known.
EQUATION 6-15:
T J = T A + Pdiss total JA
Where:
R ON
= P driver -----------------------------------------------R ON + R G + R G_FET
R OFF
+ P driver ---------------------------------------------------R OFF + R G + R G_FET
Supply Current Power Dissipation
Power is dissipated in the MIC4102 even if there is
nothing being driven. The supply current is drawn by
the bias for the internal circuitry, the level shifting
circuitry, and shoot-through current in the output
drivers. The supply current is proportional to operating
frequency and the VDD and VHB voltages. The typical
characteristic graphs show how supply current varies
with switching frequency and supply voltage.
The power dissipated by the MIC4102 due to supply
current is:
2016 - 2022 - 2021 Microchip Technology Inc. and its subsidiaries.
TJ
Junction Temperature
TA
Maximum Ambient Temperature
Pdisstotal
Power Dissipation of the MIC4102
θJA
Thermal Resistance from Junction
to Ambient Air
Pdiss drive
6.5
Total Power Dissipation and
Thermal Considerations
Pdiss total = Pdiss supply + Pdiss drive + Pdiode total
Pdriver
fS
6.6
6.7
Anti-Shoot-Through, Propagation
Delay, and Other Timing
Considerations
The block diagram on page two illustrates how the
MIC4102 drives the power stage of a synchronous
buck converter. It is important that only one of the two
MOSFETs is on at any given time. If both MOSFETs are
simultaneously on, they will short VIN to ground,
causing high current from the VIN supply to “shoot
through” the MOSFETs and into ground. Excessive
shoot-through causes higher power dissipation in the
MOSFETs, voltage spikes, and ringing in the circuit.
The high current and voltage ringing generate
conducted and radiated EMI.
Minimizing shoot-through can be done passively,
actively, or though a combination of both. Passive
shoot-through protection uses delays between the high
and low gate drivers to prevent both MOSFETs from
being on at the same time. These delays can be
adjusted for different applications. Although simple, the
DS20005575B-page 17
MIC4102
disadvantage of this approach is the long delays
required to account for process and temperature
variations in the MOSFET and the MOSFET driver.
voltage settle out. An external resistor between the LO
output and the MOSFET may affect the performance of
the LO pin monitoring circuit and is not recommended.
Active shoot-though monitors voltages on the gate
drive outputs and switch node to determine when to
switch the MOSFETs on and off. This active approach
adjusts the delays to account for some of the
variations, but it also has its disadvantages. High
currents and fast switching voltages in the gate drive
and return paths can cause parasitic ringing that may
turn the MOSFETs back on even though the gate driver
output is low. Another disadvantage is that the driver
cannot monitor the gate voltage inside the MOSFET.
Figure 6-4 shows an equivalent circuit, including
parasitics, of the gate driver section. The internal gate
resistance (RG_GATE) and any external damping
resistor (RG) isolate the MOSFET’s gate from the driver
output. There is a delay between when the driver
output goes low and the MOSFET turns off. This
turn-off delay is usually specified in the MOSFET data
sheet. This delay increases when an external damping
resistor is used.
A low on the PWM pin causes the HO pin to go low after
a short delay (tHOOFF). Before the LO pin can go high,
the voltage on the switching node (HS pin) must have
dropped to 2.5V below the VDD voltage. Monitoring the
switch voltage instead of the HO pin voltage eliminates
timing variations and excessive delays due to the high
side MOSFET turn-off. The LO driver turns on after a
short delay (tLOON). Once the LO driver is turned on, it
is latched on until the PWM signal goes high. This
prevents any ringing or oscillations on the switch node
or HS pin from turning off the LO driver. If the PWM pin
goes low and the voltage on the HS pin does not cross
the VSWth threshold, the LO pin will be forced high after
a short delay (tSWTO), ensuring proper operation.
VDD
VIN
HB
RON
CGD
RG_FET
HO
HS FET
RG
CGS
ROFF
HS
SWITCHING
NODE
RON
CGD
LO
RG_FET
LS FET
CGS
ROFF
VSS
FIGURE 6-4:
Parasitics.
Gate Drive Circuit with
The MIC4102 uses a combination of active sensing
and passive delay to ensure that both MOSFETs are
not on at the same time and to minimize shoot-through
current. The timing diagram helps illustrate how the
anti-shoot-through circuitry works. A high level on the
PWM pin causes the LO pin to go low. The MIC4102
monitors the LO pin voltage and prevents the HO pin
from turning on until the voltage on the LO pin reaches
the VLOOFF threshold. After a short delay, the MIC4102
drives the HO pin high. Monitoring the LO voltage
eliminates any excessive delay due to the MOSFET
drivers turn-off time and the short delay accounts for
the MOSFET turn-off delay as well as letting the LO pin
DS20005575B-page 18
Fast propagation delay between the input and output
drive waveform is desirable. It improves overcurrent
protection by decreasing the response time between
the control signal and the MOSFET gate drive.
Minimizing propagation delay also minimizes phase
shift errors in power supplies with wide bandwidth
control loops.
Care must be taken to ensure the input signal pulse
width is greater than the minimum specified pulse
width. An input signal that is less than the minimum
pulse width may result in no output pulse or an output
pulse whose width is significantly less than the input.
The maximum duty cycle (ratio of high-side on-time to
switching period) is determined by the time required for
the CB capacitor to charge during the off-time.
Adequate time must be allowed for the CB capacitor to
charge up before the high-side driver is turned back on.
The anti-shoot-through circuit in the MIC4102 prevents
the driver from turning both MOSFETs on at the same
time; however, other factors outside of the
anti-shoot-through circuit’s control can cause
shoot-through. Some of these include ringing on the
gate drive node and capacitive coupling of the
switching node voltage on the gate of the low-side
MOSFET.
6.8
Decoupling and Bootstrap
Capacitor Selection
Decoupling capacitors are required for both the
low-side (VDD) and high-side (HB) supply pins. These
capacitors supply the charge necessary to drive the
external MOSFETs as well as minimize the voltage
ripple on these pins. The capacitor from HB to HS
serves double duty by providing decoupling for the
high-side circuitry as well as providing current to the
high-side circuit while the high-side external MOSFET
is on. Ceramic capacitors are recommended because
of their low impedance and small size. Z5U type
ceramic capacitor dielectrics are not recommended
due to the large change in capacitance over
2016 - 2022 - 2021 Microchip Technology Inc. and its subsidiar-
MIC4102
temperature and voltage. A minimum value of 0.1 µF is
required for each of the capacitors, regardless of the
MOSFETs being driven. Larger MOSFETs may require
larger capacitance values for proper operation. The
voltage rating of the capacitors depends on the supply
voltage, ambient temperature, and the voltage derating
used for reliability. 25V rated X5R or X7R ceramic
capacitors are recommended for most applications.
The minimum capacitance value should be increased if
low voltage capacitors are used because even good
quality dielectric capacitors, such as X5R, will lose 40%
to 70% of their capacitance value at the rated voltage.
Placement of the decoupling capacitors is critical. The
bypass capacitor for VDD should be placed as close as
possible between the VDD and VSS pins. The bypass
capacitor (CB) for the HB supply pin must be located as
close as possible between the HB and HS pins. The
etch connections must be short, wide, and direct. The
use of a ground plane to minimize connection
impedance is recommended. Refer to the section on
layout and component placement for more information.
The voltage on the bootstrap capacitor drops each time
it delivers charge to turn on the MOSFET. The voltage
drop depends on the gate charge required by the
MOSFET. Most MOSFET specifications specify gate
charge vs. VGS voltage. Based on this information and
a recommended ΔVHB of less than 0.1V, the minimum
value of bootstrap capacitance is calculated as:
from CVDD through the internal driver, into the MOSFET
gate, and out the source. The return connection back to
the decoupling capacitor is made through the ground
plane. Any inductance or resistance in the ground
return path causes a voltage spike or ringing to appear
on the source of the MOSFET. This voltage works
against the gate voltage and can either slow down or
turn off the MOSFET during the period where it should
be turned on.
Current in the high-side driver is sourced from
capacitor CB, flows into the HB pin, and out the HO pin,
into the gate of the high-side MOSFET. The return path
for the current is from the source of the MOSFET and
back to capacitor CB. The high-side circuit return path
usually does not have a low impedance ground plane,
so the etch connections in this critical path should be
short and wide to minimize parasitic inductance. As
with the low-side circuit, impedance between the
MOSFET source and the decoupling capacitor causes
negative voltage feedback that fights the turn-on of the
MOSFET.
It is important to note that capacitor CB must be placed
close to the HB and HS pins. This capacitor not only
provides all the energy for turn-on, but it must also keep
HB pin noise and ripple low for proper operation of the
high-side drive circuitry.
LOW-SIDE DRIVE
TURN-ON
CURRENT PATH
EQUATION 6-16:
QG
C B -------------V HB
Where:
QG
ΔVHB
VDD
GND
PLANE
HB
Grounding, Component
Placement, and Circuit Layout
Nanosecond switching speeds and ampere peak
currents in and around the MIC4102 driver require
proper placement and trace routing of all components.
Improper placement may cause degraded noise
immunity, false switching, excessive ringing, or circuit
latch-up.
GND
PLANE
FF
HO
Voltage Drop at the HB Pin
CB
HS
6.9
VSS
_
Q
Total Gate Charge at VHB
The decoupling capacitor for the VDD input may be
calculated in with the same formula; however, the two
capacitors are usually equal in value.
LO
C VDD
HIGH-SIDE DRIVE
TURN-ON
CURRENT PATH
FIGURE 6-5:
PWM
Q
LEVEL
SHIFT
LS
Turn-On Current Paths.
Figure 6-6 shows the critical current paths when the
driver outputs go low and turn off the external
MOSFETs. Short, low impedance connections are
important during turn-off for the same reasons given in
the turn-on explanation. Current flowing through the
internal diode replenishes charge in the bootstrap
capacitor, CB.
Figure 6-5 shows the critical current paths when the
driver outputs go high and turn on the external
MOSFETs. It also shows the need for a low impedance
ground plane. The charge needed to turn-on the
MOSFET gates comes from the decoupling capacitors
CVDD and CB. Current in the low-side gate driver flows
2016 - 2022 - 2021 Microchip Technology Inc. and its subsidiaries.
DS20005575B-page 19
MIC4102
LOW-SIDE DRIVE TURN-OFF
CURRENT PATH
CVDD
VDD
LO
V
CHARGE CB THROUGH
INTERNAL DIODE WHEN
HS PIN IS LOW
V
V
VSS
HB
V
_
Q
V
FF
HO
CB
Q
PWM
LEVEL
SHIFT
HS
LS
HIGH-SIDE DRIVE
TURN-OFF CURRENT PATH
FIGURE 6-6:
Turn-Off Current Paths.
The following circuit guidelines should be adhered to
for optimum circuit performance:
• The VDD and HB bypass capacitors must be
placed close to the supply and ground pins. It is
critical that the etch length between the high side
decoupling capacitor (CB) and the HB and HS
pins be minimized to reduce lead inductance.
• A ground plane should be used to minimize
parasitic inductance and impedance of the return
paths. The MIC4102 is capable of greater than 3A
peak currents. Any impedance between the
MIC4102, the decoupling capacitors, and the
external MOSFET will degrade the performance
of the driver.
• Trace out the high di/dt and dv/dt paths, as shown
in Figure 6-5 and Figure 6-6 to minimize the etch
length and loop area for these connections.
Minimizing these parameters decreases the
parasitic inductance and the radiated EMI
generated by fast rise and fall times.
A typical layout of a synchronous buck converter power
stage using the MIC4102 (Figure 6-7) is shown in
Figure 6-8.
VDD
CB
HIGH-SIDE
FET
CVDD
HO
LEVEL
SHIFT
PWM
VIN
HB
VDD
HS
Q
FF_
Q
LO
HS
(SWITCH NODE)
LOW-SIDE
FET
VSS
FIGURE 6-7:
Stage.
DS20005575B-page 20
CIN
FIGURE 6-8:
Typical Layout of a
Synchronous Buck Converter Power Stage.
The circuit is configured as a synchronous buck power
stage. The high-side MOSFET drain connects to the
input supply voltage (drain) and the source connects to
the switching node. The low-side MOSFET drain
connects to the switching node and its source is
connected to ground. The buck converter output
inductor (not shown) would connect to the switching
node. The high-side drive trace, HO, is routed on top
of its return trace, HS, to minimize loop area and
parasitic inductance. The low-side drive trace, LO, is
routed over the ground plane and minimizes the
impedance of that current path. The decoupling
capacitors, CB and CVDD, are placed to minimize etch
length between the capacitors and their respective
pins. This close placement is necessary to efficiently
charge capacitor CB when the HS node is low. All
traces are 0.025” wide or greater to reduce impedance.
CIN is used to decouple the high current path through
the MOSFETs.
Typical Converter Power
2016 - 2022 - 2021 Microchip Technology Inc. and its subsidiar-
MIC4102
7.0
PACKAGING INFORMATION
7.1
Package Marking Information
8-Lead SOIC*
4102YM
WNNN
Legend: XX...X
Y
YY
WW
NNN
e3
*
Example
4102YM
6921
Product code or customer-specific information
Year code (last digit of calendar year)
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code
Pb-free JEDEC® designator for Matte Tin (Sn)
This package is Pb-free. The Pb-free JEDEC designator ( e3 )
can be found on the outer packaging for this package.
●, ▲, ▼ Pin one index is identified by a dot, delta up, or delta down (triangle
mark).
Note:
In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information. Package may or may not include
the corporate logo.
Underbar (_) symbol may not be to scale.
2016 - 2022 - 2021 Microchip Technology Inc. and its subsidiaries.
DS20005575B-page 21
MIC4102
8-Lead SOIC Package Outline and Recommended Land Pattern
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS20005575B-page 22
2016 - 2022 - 2021 Microchip Technology Inc. and its subsidiar-
MIC4102
APPENDIX A:
REVISION HISTORY
Revision A (June 2016)
• Converted Micrel document MIC4102 to Microchip data sheet DS20005575A.
• Minor text changes throughout.
Revision B (May 2022)
• Updated package marking drawing in Section 7.1
“Package Marking Information”.
2016 - 2021 Microchip Technology Inc.and its subsidiaries.
DS20005575B-page 23
MIC4102
NOTES:
DS20005575B-page 24
2016 - 2021 Microchip Technology Inc.and its subsidiaries.
MIC4102
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, contact your local Microchip representative or sales office.
PART NO.
Device
X
X
XX
Examples:
a)
MIC4102YM:
b)
MIC4102YM-TR:
Temperature Package Media Type
Device:
MIC4102:
Temperature:
Y
=
–40°C to +125°C
Package:
M
=
SOIC-8L
Media Type:
(blank) = 95/Tube
TR
= 2,500/Reel
100V Half-Bridge MOSFET Driver with
Anti-Shoot-Through Protection
2016 - 2022 - 2021 Microchip Technology Inc. and its subsidiaries.
100V Half-Bridge MOSFET Driver with AntiShoot-Through Protection,
–40°C to +125°C Temp.
Range, SOIC-8L Package,
95/Tube
100V Half-Bridge MOSFET Driver with AntiShoot-Through Protection, –40°C to +125°C
Temp. Range, SOIC-8L
Package, 2,500/Reel
DS20005575B-page 25
MIC4102
NOTES:
DS20005575B-page 26
2016 - 2022 - 2021 Microchip Technology Inc. and its subsidiar-
Note the following details of the code protection feature on Microchip products:
•
Microchip products meet the specifications contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is secure when used in the intended manner, within operating specifications, and
under normal conditions.
•
Microchip values and aggressively protects its intellectual property rights. Attempts to breach the code protection features of
Microchip product is strictly prohibited and may violate the Digital Millennium Copyright Act.
•
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of its code. Code protection does not
mean that we are guaranteeing the product is “unbreakable”. Code protection is constantly evolving. Microchip is committed to
continuously improving the code protection features of our products.
This publication and the information herein may be used only
with Microchip products, including to design, test, and integrate
Microchip products with your application. Use of this information in any other manner violates these terms. Information
regarding device applications is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your
specifications. Contact your local Microchip sales office for
additional support or, obtain additional support at https://
www.microchip.com/en-us/support/design-help/client-supportservices.
THIS INFORMATION IS PROVIDED BY MICROCHIP "AS IS".
MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED,
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RELATED TO THE INFORMATION INCLUDING BUT NOT
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© 2016 - 2016 - 2022, Microchip Technology Incorporated and its
subsidiaries.
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2016 - 2016 - 2022 Microchip Technology Inc. and its subsidiaries.
ISBN: 978-1-5224-9340-2
DS20005575B-page 27
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Tel: 408-436-4270
Canada - Toronto
Tel: 905-695-1980
Fax: 905-695-2078
DS20005575B-page 28
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Fax: 44-118-921-5820
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09/14/21
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