MIC4125YME

MIC4123/4/5 Dual 3A Peak Low-Side MOSFET Drivers Features General Description • Reliable, Low-Power Bipolar/CMOS/DMOS Construction • Latch-Up Protected to >200 mA Reverse Current • Logic Input Withstands Swing to –5V • High 3A Peak Output Current • Wide 4.5V to 20V Operating Range • Drives 1800 pF Capacitance in 25 ns • Short 2.5 V/μs. Note 1 Parameter Sym. Min. Typ. Max. Units Conditions Logic 1 Input Voltage VIH 2.4 1.5 — V — Logic 0 Input Voltage VIL — 1.3 0.8 V — Input Current IIN –1 — 1 –10 — 10 — — V IOUT = 100 µA V IOUT = –100 µA Input µA 0V ≤ VIN ≤ VS — Output High Output Voltage VOH VS – 0.025 Low Output Voltage VOL — — 0.025 — 2.3 5 — — 8 — 2.2 5 — — 8 Output Resistance High State Output Resistance Low State RO IOUT = 10 mA, VS = 20V Ω — IOUT = 10 mA, VS = 20V — Peak Output Current IPK — 3 — A — Latch-Up Protection Withstand Reverse Current I >200 — — mA — — 11 35 — — 60 — 11 35 — — 60 Switching Time Rise Time tr Fall Time tf Note 1: ns ns Test Figure 1-1, CL = 1800 pF — Test Figure 1-1, CL = 1800 pF — Specification for packaged product only.  2018 Microchip Technology Inc. DS20006035A-page 3 MIC4123/4/5 ELECTRICAL CHARACTERISTICS (CONTINUED) Electrical Characteristics: 4.5V ≤ VS ≤ 20V; TA = +25°C, bold values indicate –40°C ≤ TJ ≤ +125°C; unless noted. Input voltage slew rate >2.5 V/μs. Note 1 Parameter Sym. Delay Time tD1 Delay Time tD2 Min. Typ. Max. — 44 75 — — 100 — 59 75 — — 100 — 1.5 2.5 — — 3.5 — 0.15 0.25 — — 0.3 Units ns ns Conditions Test Figure 1-1, CL = 1800 pF — Test Figure 1-1, CL = 1800 pF — Power Supply Power Supply Current IS Power Supply Current IS Note 1: mA mA VIN = 3.0V (both inputs) — VIN = 0V (both inputs) — Specification for packaged product only. DS20006035A-page 4  2018 Microchip Technology Inc. MIC4123/4/5 TEMPERATURE SPECIFICATIONS Parameters Sym. Min. Typ. Max. Units Maximum Junction Temperature TJ — — +150 °C Conditions Temperature Ranges — Storage Temperature Range TS –65 — +150 °C — Lead Temperature — — — +300 °C 10 sec. Junction Operating Temperature Range TJ –40 — +125 °C — Thermal Resistance, 4x4 VDFN 8-Ld JA — 45 — °C/W — Thermal Resistance, EP SOIC-8 JA — 58 — °C/W — Package Thermal Resistances Note 1: The maximum allowable power dissipation is a function of ambient temperature, the maximum allowable junction temperature and the thermal resistance from junction to air (i.e., TA, TJ, JA). Exceeding the maximum allowable power dissipation will cause the device operating junction temperature to exceed the maximum +125°C rating. Sustained junction temperatures above +125°C can impact the device reliability.  2018 Microchip Technology Inc. DS20006035A-page 5 MIC4123/4/5 Test Circuits V S = 20V 0.1μF OUTA A INA 4.7μF 1800pF MIC4123 B INB OUTB 1800pF INPUT 5V 90% 2.5V 10% 0V VS 90% tD1 tP W tF tD2 tR OUTPUT 10% 0V FIGURE 1-1: Inverting Driver Switching Time. V S = 20V 0.1μF OUTA A INA 4.7μF 1800pF MIC4124 B INB OUTB 1800pF INPUT 5V 90% 2.5V 10% 0V VS 90% tD1 tP W tR tD2 tF OUTPUT 10% 0V FIGURE 1-2: DS20006035A-page 6 Non-Inverting Driver Switching Time.  2018 Microchip Technology Inc. MIC4123/4/5 TYPICAL PERFORMANCE CURVES The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore outside the warranted range. RISE TIME (ns) Note: 140 100 120 90 80 PROPAGATION DELAY (ns) 2.0 100 5V 80 12V 60 40 20 20V 0 100 FIGURE 2-1: Load. 1000 10000 CAPACITIVE LOAD (pF) Rise Time vs. Capacitive 50 40 td1 30 20 10 C LOAD = 1000pF 0 5 10 15 SUPPLY VOLTAGE (V) FIGURE 2-4: Supply Voltage. 140 20 Propagation Delay vs. 25 120 20 Rise Time 100 TIME (ns) FALL TIME (ns) td2 70 60 5V 80 20V 60 15 Fall Time 10 40 5 20 0 100 FIGURE 2-2: Load. 12V 1000 10000 CAPACITIVE LOAD (pF) Fall Time vs. Capacitive 0 5 CLOAD = 1000pF FIGURE 2-5: Supply Voltage. 10 15 SUPPLY VOLTAGE (V) 20 Rise and Fall Time vs. 2873875(6,67$1&(Ÿ 4.5 4.0 3.5 3.0 Output High 2.5 2.0 Output Low 1.5 1.0 0.5 0 5 FIGURE 2-3: Supply Voltage. 10 15 ,138792/7$*(9 20 Output Resistance vs.  2018 Microchip Technology Inc. DS20006035A-page 7 MIC4123/4/5 3.0 PIN DESCRIPTIONS The descriptions of the pins are listed in Table 3-1. TABLE 3-1: PIN FUNCTION TABLE Pin Number Pin Name 2, 4 INA, INB 3 GND 6 VS 7, 5 Description Control Input Ground: Duplicate pins must be externally connected together Supply Input: Duplicate pins must be externally connected together OUTA, OUT B Output: Duplicate pins must be externally connected together 1, 8 NC EP GND DS20006035A-page 8 Not connected Ground: Backside Pad  2018 Microchip Technology Inc. MIC4123/4/5 4.0 APPLICATION INFORMATION Although the MIC4123/4/5 drivers have been specifically constructed to operate reliably under any practical circumstances, there are nonetheless details of usage that will provide better operation of the device. 4.1 Supply Bypassing Charging and discharging large capacitive loads quickly requires large currents. For example, charging 2000 pF from 0 to 15 volts in 20 ns requires a constant current of 1.5A. In practice, the charging current is not constant and will usually peak at around 3A. In order to charge the capacitor, the driver must be capable of drawing this much current, this quickly, from the system power supply. In turn, this means that, as far as the driver is concerned, the system power supply, as seen by the driver, must have a very low impedance. As a practical matter, this means that the power supply bus must be capacitively bypassed at the driver with at least 100 times the load capacitance in order to achieve optimum driving speed. It also implies that the bypassing capacitor must have very low internal inductance and resistance at all frequencies of interest. Generally, this means using two capacitors: one a high-performance low-ESR film, the other a low internal resistance ceramic. Together, the valleys in their two impedance curves allow adequate performance over a broad enough band to get the job done. Please note that many film capacitors can be sufficiently inductive as to be useless for this service. Likewise, many multilayer ceramic capacitors have unacceptably high internal resistance. Use capacitors intended for high pulse current service. The high pulse current demands of capacitive drivers also mean that the bypass capacitors must be mounted very close to the driver in order to prevent the effects of lead inductance or PCB land inductance from nullifying what you are trying to accomplish. For optimum results the sum of the lengths of the leads and the lands from the capacitor body to the driver body should total 2.5 cm or less. Bypass capacitance, and its close mounting to the driver, serves two purposes. Not only does it allow optimum performance from the driver, it minimizes the amount of lead length radiating at high frequency during switching, (due to the large ∆I) thus minimizing the amount of EMI later available for system disruption and subsequent cleanup. It should also be noted that the actual frequency of the EMI produced by a driver is not the clock frequency at which it is driven, but is related to the highest rate of change of current produced during switching, a frequency generally one or two orders of magnitude higher, and thus more difficult to filter if you let it permeate your system. Good bypassing practice is essential to proper operation of high speed driver ICs.  2018 Microchip Technology Inc. 4.2 Grounding Both proper bypassing and proper grounding are necessary for optimum driver operation. Bypassing capacitance only allows a driver to turn the load on. Eventually, except in rare circumstances, it is also necessary to turn the load off. This requires attention to the ground path. Two things other than the driver affect the rate at which it is possible to turn a load off: the adequacy of the grounding available for the driver and the inductance of the leads from the driver to the load. The latter will be discussed in a separate section. The SOIC and VDFN packages have an exposed pad under the package. It's important for good thermal performance that this pad is connected to a ground plane. Best practice for a ground path is a well laid out ground plane. However, this is not always practical, and a poorly laid out ground plane can be worse than none. Attention to the paths taken by return currents even in a ground plane is essential. In general, the leads from the driver to its load, the driver to the power supply, and the driver to whatever is driving it should all be as low in resistance and inductance as possible. Of the three paths, the ground lead from the driver to the logic driving it is most sensitive to resistance or inductance, and ground current from the load is what is most likely to cause disruption. Thus, these ground paths should be arranged so that they never share a land, or do so for as short a distance as is practical. To illustrate what can happen, consider the following: the inductance of a 2 cm long land, 1.59 mm (0.062") wide, on a PCB with no ground plane is approximately 45 nH. Assuming a dl/dt of 0.3 A/ns (which will allow a current of 3A to flow after 10 ns, and is thus slightly slow for our purposes) a voltage of 13.5V will develop along this land in response to our postulated ∆Ι. For a 1 cm land, (approximately 15 nH) 4.5V is developed. Either way, anyone using TTL-level input signals to the driver will find that the response of their driver has been seriously degraded by a common ground path for input to and output from the driver of the given dimensions. Note that this is before accounting for any resistive drops in the circuit. The resistive drop in a 1.59 mm (0.062") land of 2 oz. copper carrying 3A will be about 4 mV/cm (10 mV/in) at DC, and the resistance will increase with frequency as skin effect comes into play. The problem is most obvious in inverting drivers where the input and output currents are in phase so that any attempt to raise the driver’s input voltage (in order to turn the driver’s load off) is countered by the voltage developed on the common ground path as the driver attempts to do what it was supposed to. It takes very little common ground path under these circumstances to alter circuit operation drastically. DS20006035A-page 9 MIC4123/4/5 4.3 Output Lead Inductance The same descriptions just given for PCB land inductance apply equally well for the output leads from a driver to its load, except that commonly the load is located much further away from the driver than the driver’s ground bus. Generally, the best way to treat the output lead inductance problem, when distances greater than 4 cm (2") are involved, requires treating the output leads as a transmission line. Unfortunately, as both the output impedance of the driver and the input impedance of the MOSFET gate are at least an order of magnitude lower than the impedance of common coax, using coax is seldom a cost-effective solution. A twisted pair works about as well, is generally lower in cost, and allows the use of a wider variety of connectors. The second wire of the twisted pair should carry common from as close as possible to the ground pin of the driver directly to the ground terminal of the load. Do not use a twisted pair where the second wire in the pair is the output of the other driver because this will not provide a complete current path for either driver. Likewise, do not use a twisted triad with two outputs and a common return unless both of the loads to be driver are mounted extremely close to each other and you can guarantee that they will never be switching at the same time. For output leads on a printed circuit, the general rule is to make them as short and as wide as possible. The lands should also be treated as transmission lines: i.e., minimize sharp bends, or narrowings in the land because these will cause ringing. For a rough estimate on a 1.59 mm (0.062") thick G-10 PCB, a pair of opposing lands each 2.36 mm (0.093") wide translates to a characteristic impedance of about 50Ω. Half that width suffices on a 0.787 mm (0.031") thick board. For accurate impedance matching with a MIC4123/4/5 driver on a 1.59 mm (0.062") board, a land width of 42.75 mm (1.683") would be required, due to the low impedance of the driver and (usually) its load. This is impractical under most circumstances. Generally, the trade off point between lands and wires comes when lands narrower than 3.18 mm (0.125") would be required on a 1.59 mm (0.062") board. To obtain minimum delay between the driver and the load, it is considered best to locate the driver as close as possible to the load using adequate bypassing. Using matching transformers at both ends of a piece of coax, or several matched lengths of coax between the driver and the load, works in theory, but is not optimal. 4.4 Driving at Controlled Rates Occasionally there are situations where a controlled rise or fall time, which may be considerably longer than the normal rise or fall time of the driver’s output, is desired for a load. In such cases, it is still prudent to employ the best possible practice in terms of bypassing, grounding, and PCB layout, then reduce the DS20006035A-page 10 switching speed of the load, not the driver, by adding a non-inductive series resistor of an appropriate value between the output of the driver and the load. For situations where only rise or only fall should be slowed, the resistor can be paralleled with a fast diode so that switching in the other direction remains fast. Due to the Schmitt-trigger action of the driver’s input, it is not possible to slow the rate of rise or fall of the driver’s input signal to achieve slowing of the output. 4.5 Input Signal The input stage of the MIC4123/4/5 consists of a single-MOSFET class A stage with an input capacitance of