MIC5166YML-TR

MIC5166 3A High-Speed, Low-VIN DDR Terminator Features General Description • Operating Voltage Range: - VDDQ Supply: 0.9V to 3.6V - Bias Supply: 2.5V to 5.5V • High Bandwidth: Very Fast Transient Response • Stable with Two 10 µF Ceramic Output Capacitors • Two 10 µF Output Capacitors used in Most Applications • High Output Voltage Accuracy: - 0.015% Line Regulation - 1.5% Load Regulation • Logic Level Enable Input • Power Good (PG) • Thermally Enhanced 3 mm x 3 mm DFN • Junction Temperature Range –40°C to +125°C • This Device Meets DDR4 Requirements The MIC5166 is a 3A, high-speed, linear, low VIN, double data rate (DDR), memory terminator power supply. The part is small and requires small output capacitors, making it a tiny overall solution. This allows it to be conveniently placed close to the DDR memory, minimizing circuit board layout inductance that may cause excessive voltage ripple at the DDR memory. Applications • • • • • Desktop Computers Notebook Computers Datacom Systems Servers Video Cards The MIC5166 contains a precision voltage divider network in order to take in the VDDQ voltage as a reference voltage and conveniently output the terminator voltage (VTT) at one half of the VDDQ input voltage. The MIC5166 is capable of sinking and sourcing up to 3A. It is stable with only two 10 µF ceramic output capacitors. The part is available in a small 3 mm x 3 mm DFN thermally-enhanced package. The MIC5166 has a high-side NMOS output stage offering very low output impedance, and very high bandwidth. The NMOS output stage offers a unique ability to respond very quickly to sudden load changes such as is required for DDR memory termination power supply applications. Package Type MIC5166 10-Lead 3 mm x 3 mm DFN (ML) (Top View)  2018 - 2019 Microchip Technology Inc. VREF 1 10 VIN BIAS 2 9 VTT AGND 3 8 PGND VDDQ 4 7 EN PG 5 6 SNS EP DS20006085B-page 1 MIC5166 Typical Application Circuit MIC5166 VBIAS 2.5V TO 5.5V 2 BIAS VDDQ 4.7μF 1.0μF VIN 0.9V TO 3.6V 10Nȍ 10 10μF 8 7 EN VTT VIN SNS 5 PG VDDQ 0.9V TO 3.6V 4 PGND PG EN 6 22μF EP AGND VREF VTT ±3A 9 3 VREF 10mA 1 1.0μF Functional Block Diagram MIC5166 VBIAS 2.5V TO 5.5V BIAS UVLO 1μF UVLO EN CONTROL LOGIC EN VIN 0.9V TO 3.6V VIN 10μF THERMAL SHUTDOWN VTT VTT ±3A 2x10μF EP VDDQ 0.9V TO 3.6V VDDQ 4.7μF PGND 45Nȍ SNS 5Nȍ 110% VREF VBIAS VREF 10Nȍ 1 .0μF 5Nȍ PG 90% VREF PG 45Nȍ AGND DS20006085B-page 2  2018 - 2019 Microchip Technology Inc. MIC5166 1.0 ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings † VBIAS ............................................................................................................................................................ –0.3V to +6V VIN .............................................................................................................................................................. –0.3V to VBIAS VDDQ ..............................................................................................................................................................–0.3V to VIN VTT .................................................................................................................................................................–0.3V to VIN VEN ............................................................................................................................................................. –0.3V to VBIAS VPG............................................................................................................................................................. –0.3V to VBIAS PGND to AGND ........................................................................................................................................ –0.3V to +0.3V Junction Temperature (TJ)..................................................................................................................................... +150°C Storage Temperature (TS)...................................................................................................................... –65°C to +150°C Lead Temperature (Soldering, 10 sec.)................................................................................................................. +260°C Continuous Power Dissipation (TA = +25°C; De-Rated 16.4 mW/°C above 25°C).................................................1.64W Continuous Power Dissipation (TA = +85°C) .......................................................................................................656 mW ESD Rating (HBM, Note 1) ........................................................................................................................................ 2 kV Operating Ratings †† Supply Voltage (VBIAS).............................................................................................................................. +2.5V to +5.5V Supply Voltage (VIN, Note 2)..................................................................................................................... +0.9V to +3.6V Supply Voltage (VDDQ, Note 3)...................................................................................................................... +0.9V to VIN Power Good Voltage (VPG) ............................................................................................................................. 0V to VBIAS Enable Input Voltage (VEN) ............................................................................................................................. 0V to VBIAS Junction Temperature Range (TJ) .......................................................................................................... –40°C to +125°C Package Thermal Resistance 3 mm x 3 mm DFN (JC) ....................................................................................................................................28.7°C/W 3 mm x 3 mm DFN (JA) ....................................................................................................................................60.7°C/W † Notice: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational sections of this specification is not intended. Exposure to maximum rating conditions for extended periods may affect device reliability. †† Notice: The device is not guaranteed to function outside its operating ratings. Note 1: Devices are ESD sensitive. Handling precautions recommended. Human body model, 1.5 kΩ in series with 100 pF. 2: If VBIAS ≤ 3.6V, then VIN(MAX) = VBIAS. 3: If VBIAS ≤ 4V, then VDDQ(MAX) = 2 x (VBIAS – 2.2V). If VBIAS > 4V, then VDDQ(MAX) = 3.6V.  2018 - 2019 Microchip Technology Inc. DS20006085B-page 3 MIC5166 ELECTRICAL CHARACTERISTICS Electrical Characteristics: VIN = 1.5V, VBIAS = 3.3V, VDDQ = 1.5V, TA = +25°C, unless noted. Bold values indicate –40°C ≤ TJ ≤ +125°C. Note 1 Parameter Sym. Min. Typ. Max. Units Conditions Input Voltage Range VIN 0.9 — 3.6 V — Undervoltage Lockout Trip Level — 0.625 0.8 0.9 V VIN rising UVLO Hysteresis — — 150 — mV — Quiescent Supply Current IIN — 0.1 10 µA IOUT = 0A ISHDN — 0.1 5 µA VEN = 0V VBIAS 2.5 — 5.5 V — Undervoltage Lockout Trip Level — 1.9 2.23 2.33 V VBIAS rising UVLO Hysteresis — — 70 — mV — 1.6 3 — 1.6 3 Power Input Supply Shutdown Current Bias Supply Bias Voltage Range mA — IOUT = 1 mA Quiescent Supply Current IBIAS Shutdown Current ISHDN — 0.1 5 µA VEN = 0V VTT Accuracy — –25 — 25 mV Variation from VREF, IOUT = –2A to 2A Load Regulation — — 1.5 2.1 –1.8 –1.4 — –0.05 0.005 0.05 –0.1 0.015 0.17 –1 — 1 — 1.15 — — 1.25 — — 1.65 2.2 IOUT = 1A VTT Output Line Regulation — % %/V VSNS = 0.75V, IOUT = +10 mA to +3A VSNS = 0.75V, IOUT = –10 mA to –3A VIN = 1.5V to 3.6V, VBIAS = 5.5V, IOUT = 100 mA VIN = 1.5V, VBIAS = 2.5V to 5.5V, IOUT = 100 mA VREF Output VREF Voltage Accuracy VREF % Variation from (VDDQ/2), IREF = –10 mA to 10 mA, VREF Output = 0.6V (DDR4), IOUT = 0A. Bias Supply Dropout Voltage Dropout Voltage (VBIAS – VTT) VDO IOUT = 100 mA V IOUT = 500 mA IOUT = 3A Enable Control EN Logic High Level VIH 1.2 — — EN Logic Low Level VIL — — 0.2 EN Current IEN — 1.0 — — 6.0 — Start-Up Time tSU — 55 — Note 1: V µA µs Logic high Logic low VEN = 0.2V VEN = 1.2V From EN pin going high to VTT 90% of VREF Specification for packaged product only. DS20006085B-page 4  2018 - 2019 Microchip Technology Inc. MIC5166 ELECTRICAL CHARACTERISTICS (CONTINUED) Electrical Characteristics: VIN = 1.5V, VBIAS = 3.3V, VDDQ = 1.5V, TA = +25°C, unless noted. Bold values indicate –40°C ≤ TJ ≤ +125°C. Note 1 Parameter Sym. Min. Typ. Max. Units Conditions Sourcing Current Limit ILIM 3.1 4.9 7.8 A VIN = 2.7V, VTT = 0V Sinking Current Limit ILIM –3.1 –4.9 –7.8 A VIN = 2.7V, VTT = VIN Top MOSFET RDS(ON) — 130 190 mΩ Source, IOUT = 3A (VTT to PGND) Bottom MOSFET RDS(ON) — 130 190 mΩ Sink, IOUT = –3A (VIN to VTT) PG Window — ≥90 — ≤110 % Threshold percent of VTT from VREF Hysteresis — — 2 — % — PG Output Low Voltage — — 430 — mV IPG = 4 mA (sinking) PG Leakage Current — — — 1.0 µA VPG = 5.5V, VSNS = VREF Overtemperature Shutdown — — 150 — °C TJ rising Overtemperature Shutdown Hysteresis — — 10 — °C — Short-Current Protection Internal FETs Power Good (PG) Thermal Protection Note 1: Specification for packaged product only.  2018 - 2019 Microchip Technology Inc. DS20006085B-page 5 MIC5166 TEMPERATURE SPECIFICATIONS Parameters Sym. Min. Typ. Max. Units TJ –40 — +125 °C Conditions Temperature Ranges Junction Temperature Range Maximum Junction Temperature — TJ(MAX) — — +150 °C — Lead Temperature — — — +260 °C Soldering, 10 sec. Storage Temperature Range TS –65 — +150 °C — Thermal Resistance, 3x3 DFN 10-Ld JC — 28.7 — °C/W — Thermal Resistance, 3x3 DFN 10-Ld JA — 60.7 — °C/W — Package Thermal Resistances Note 1: The maximum allowable power dissipation is a function of ambient temperature, the maximum allowable junction temperature and the thermal resistance from junction to air (i.e., TA, TJ, JA). Exceeding the maximum allowable power dissipation will cause the device operating junction temperature to exceed the maximum +125°C rating. Sustained junction temperatures above +125°C can impact the device reliability. DS20006085B-page 6  2018 - 2019 Microchip Technology Inc. MIC5166 2.0 Note: TYPICAL PERFORMANCE CURVES The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore outside the warranted range. FIGURE 2-1: VIN Operating Supply Current vs. Input Voltage. FIGURE 2-4: VBIAS Operating Supply Current vs. BIAS Voltage. FIGURE 2-2: Input Voltage. VIN Shutdown Current vs. FIGURE 2-5: BIAS Voltage. VBIAS Shutdown Current vs. FIGURE 2-3: vs. VDDQ Voltage. VREF/VDDQ Tracking Ratio FIGURE 2-6: vs. BIAS Voltage. VREF/VDDQ Tracking Ratio  2018 - 2019 Microchip Technology Inc. DS20006085B-page 7 MIC5166 FIGURE 2-7: Voltage. Enable Threshold vs. Input FIGURE 2-10: Top MOSFET On-Resistance vs. Input Voltage. FIGURE 2-8: Voltage. Enable Pin Current vs. Input FIGURE 2-11: Bottom MOSFET On-Resistance vs. Input Voltage. FIGURE 2-9: Power Good Window/VTT Ratio vs. Input Voltage. DS20006085B-page 8 FIGURE 2-12: Voltage. Current Limit vs. Input  2018 - 2019 Microchip Technology Inc. MIC5166 FIGURE 2-13: Voltage. Load Regulation vs. Input FIGURE 2-16: VREF/VDDQ vs. I_Load. FIGURE 2-14: VREF – VTT vs. I_Load. FIGURE 2-17: VTT/VDDQ vs. I_Load. FIGURE 2-15: VTT vs. I_Load. FIGURE 2-18: VIN Operating Supply Current vs. Temperature.  2018 - 2019 Microchip Technology Inc. DS20006085B-page 9 MIC5166 FIGURE 2-19: Temperature. VIN Shutdown Current vs. FIGURE 2-22: vs. Temperature. Sourcing Load Regulation FIGURE 2-20: Temperature. VIN UVLO Threshold vs. FIGURE 2-23: Temperature. Sinking Load Regulation vs. FIGURE 2-21: Temperature. Enable Threshold vs. FIGURE 2-24: vs. Temperature. VREF/VDDQ Tracking Ration DS20006085B-page 10  2018 - 2019 Microchip Technology Inc. MIC5166 FIGURE 2-25: Temperature. Output Voltage vs. FIGURE 2-28: Top MOSFET On-Resistance vs. Temperature. FIGURE 2-26: Temperature. Current Limit vs. FIGURE 2-29: Bottom MOSFET On-Resistance vs. Temperature. FIGURE 2-27: Temperature. Enable Pin Current vs. FIGURE 2-30:  2018 - 2019 Microchip Technology Inc. EN Turn-On. DS20006085B-page 11 MIC5166 FIGURE 2-31: EN Turn-Off. FIGURE 2-34: VBIAS Turn-On (UVLO). FIGURE 2-32: VIN Turn-On (UVLO). FIGURE 2-35: VBIAS Turn-Off (UVLO). FIGURE 2-33: VIN Turn-Off UVLO. FIGURE 2-36: Load Transient (±3A). DS20006085B-page 12  2018 - 2019 Microchip Technology Inc. MIC5166 FIGURE 2-37: Line Transient.  2018 - 2019 Microchip Technology Inc. DS20006085B-page 13 MIC5166 3.0 PIN DESCRIPTIONS The descriptions of the pins are listed in Table 3-1. TABLE 3-1: PIN FUNCTION TABLE Pin Number Pin Name Description 1 VREF Reference Voltage. This output provides an output of the internal reference voltage VDDQ/2. The VREF output is used to provide the reference voltage for the memory chip. Connect a 1.0 µF capacitor to ground at this pin. This pin can sink and source 10 mA. 2 BIAS BIAS Supply Voltage. The BIAS supply is the power MOSFET gate drive supply voltage and the supply bus for the IC. The BIAS voltage must be greater than (VTT + 2.2V). A 1.0 µF ceramic capacitor from the BIAS pin to PGND must be placed next to the IC. 3 AGND Analog Ground. Internal signal ground for all low-power circuits. 4 VDDQ Input Supply. VDDQ is connected to an internal precision divider that provides the VREF. Connect a 4.7 µF capacitor to ground at this pin. Power Good. This is an open-drain output that indicates when the output voltage is within ±10% of the reference voltage. The PG flag is asserted typically with 65 µs delay when the enable is set low or when the output goes outside ±10% the window threshold. 5 PG 6 SNS 7 EN Enable. Logic level control of the output. Logic high enables the MIC5166 and a logic low shuts down the MIC5166. In the off state, supply current of the device is greatly reduced (typically 0.2 µA). The EN pin should not be left open. 8 PGND Power Ground. Internal ground connection to the source of the internal, low-side drive, N-channel MOSFET. 9 VTT Power Output. This is the connection to the source of the internal high-side N-channel MOSFET and drain of the low-side N-channel MOSFET. This is a high-frequency, high-power connection, therefore two 10 µF output capacitors must be placed as close to the IC as possible. 10 VIN High-Side N-Channel MOSFET Drain Connection. The VIN operating voltage range is from 0.9V to 3.6V. An input capacitor between the VIN pin and the PGND is required as close to the chip as possible. EP ePAD DS20006085B-page 14 Feedback. Input to the error amplifier. Exposed Pad. Must be connected to a GND plane for best thermal performance.  2018 - 2019 Microchip Technology Inc. MIC5166 4.0 FUNCTIONAL DIAGRAM 4.1 DDR memory requires two power supplies: one for the memory chip, referred to as VDDQ, and the other for a termination supply, VTT, which is one-half VDDQ. With memory speeds in excess of 300 MHz, the memory system bus must be treated as a transmission line. To maintain good signal integrity the memory bus must be terminated to minimize signal reflections. Figure 4-1 shows the simplified termination circuit. Each control, address and data lines have these termination resistors RS and RT connected to them. VDDQ 1.8V + VDDQ VDDQ DDR MEMORY CHIP SET RS + RT VDDQ RS - VREF RT + MIC5166 VBIAS BIAS VDDQ 1.0μF 4.7μF VIN 10μF 10Nȍ PGND PG PG EN EN FIGURE 4-1: Circuit. VTT SNS EP AGND 22μF VTT is regulated to VREF. Due to high-speed signaling, the load current seen by VTT is constantly changing. To maintain adequate transient response, two 10 µF ceramic capacitors are required. The proper placement of ceramic capacitors is important to reduce both ESR and ESL such that high-current and high-speed transients do not exceed the dynamic voltage tolerance requirement of VTT. The ceramic capacitors provide current during the fast edges of the bus transition. Using several smaller ceramic capacitors distributed near the termination resistors is important to reduce the effects of PCB trace inductance. 4.2 1.0μF DDR Memory Termination Bus termination provides a means to increase signaling speed while maintaining good signal integrity. The termination network consists of a series resistor (RS) and a terminating resistor (RT). Values of RS range between 10Ω to 30Ω with a typical of 22Ω, while RT ranges from 22Ω to 28Ω with a typical value of 25Ω. VREF must maintain half VDDQ with a ±1% tolerance, while VTT will dynamically sink and source current to maintain a termination voltage of ±40 mV from the VREF line under all conditions. This method of bus termination reduces common-mode noise, settling time, voltage swings, EMI/RFI, and improves slew rates. VDDQ powers all the memory ICs, memory drivers and receivers for all the memory bits in the DDR memory system. The MIC5166 regulates VTT to VDDQ/2 during sourcing or sinking current. The memory bits are not usually all at a logic high or logic low at the same time, so the VTT supply is usually not sinking or sourcing –3A or +3A current continuously.  2018 - 2019 Microchip Technology Inc. VDDQ The VDDQ input on the MIC5166 is used to create the internal reference voltage for VTT. The reference voltage is generated from an internal resistor divider network of two 500 kΩ resistors, generating a reference voltage VREF that is VDDQ/2. The VDDQ input should be Kelvin connected as close as possible to the memory supply voltage. Because the reference is simply VDDQ/2, any perturbations on VDDQ will also appear at half the amplitude on the reference. For this reason, a 4.7 µF ceramic capacitor is required on the VDDQ supply. This will aid performance by improving the source impedance over a wide frequency range. 4.3 VREF VTT Sense The sense (SNS) pin provides the path for the error amplifier to regulate VTT. The SNS input must also be Kelvin connected to the VTT bypass capacitors. If the SNS input is connected too close to the MIC5166, the IR drop of the PCB trace can cause the VTT voltage at the memory chip to be too low. Placing the MIC5166 as close as possible to the DDR memory will improve the load regulation performance. 4.4 Enable The MIC5166 features an active-high enable input (EN) that allows on-off control of the regulator. The current through the device reduces to near “zero” when the device is shutdown, with only